# Hello-FPGA

**Repository Path**: ChesterLeeRepo/hello-fpga

## Basic Information

- **Project Name**: Hello-FPGA
- **Description**: Hello-FPGA 🚀: A personal FPGA journey using Xilinx dev boards. Designs in Verilog, simulated in Modelsim, and developed in Vivado. Explore, learn, and innovate! 😎✨
- **Primary Language**: Verilog
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-04-15
- **Last Updated**: 2025-05-06

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Hello-FPGA

This repository documents my personal FPGA learning journey, focusing on the Xilinx development board. Projects are implemented using Verilog, simulated in Modelsim 🎯, and further developed through Vivado. It's a curated collection of experiments, tutorials, and insights into FPGA design, intended to inspire and guide fellow enthusiasts along the way! 😎✨

## Draw oscillogram of signal in VSCode

- Install `Waveform Render` extension in VSCode.
- Create a *json* file with the signals you want to render.
- Enter `ctrl+shift+P` and select `Waveform Render: Draw`.
- Save the file as *png* or *svg*.

> Click here to see [*Hitchhiker's Guide to the WaveDrom*](https://wavedrom.com/tutorial.html)