# proj_train

**Repository Path**: GordenZhang/proj_train

## Basic Information

- **Project Name**: proj_train
- **Description**: 仅用于记录学习经历与感悟
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2022-02-26
- **Last Updated**: 2023-03-22

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

No README documentation available for this project.