# opentimer **Repository Path**: Jyx206078/opentimer ## Basic Information - **Project Name**: opentimer - **Description**: OpenTimer is a new static timing analysis (STA) tool to help IC designers quickly verify the circuit timing. - **Primary Language**: Unknown - **License**: Not specified - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 0 - **Created**: 2021-12-20 - **Last Updated**: 2022-07-08 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # Verilog Netlist OpenTimer reads *gate-level* (aka structural) verilog files (.v) to initialize circuit netlists. Logics are described by gates and modules only. There are no `always` blocks or `assign` statements. # Admissible Verilog Format The input verilog must specify the top-level hierarchy of the design. For now, OpenTimer uses a small set of keywords in the Verilog language. ```verilog module circuit_name ( // begin module definition input_name_1, ..., input_name_n, output_name_1, ..., output_name_m ); input input_name_1; // begin input ports definition ... input input_name_n; // end input ports definition output output_name_1; // begin output ports definition ... output output_name_m; // end output ports definition wire wire_name_1; // begin wire (net) definition ... wire wire_name_k; // end wire (net) definition cell_type cell_instance_name ( .pin_name (net name), ... ); ... end module // end module definition ``` The admissible structure of the verilog file is to start with a module declaration, which defines the module interface with name ``. The input and output pins are explicitly declared with the keywords `input` and `output`. The internal nets are declared with the keyword `wire`. For each instance, `cell_type` and every cell pin `pin_name` should be found in the library. Connection between instances are described in terms of wire-pin mapping. ## Example The following example demonstrates a valid verilog format for OpenTimer. ```verilog module simple (inp1, inp2, tau2015_clk, out); // Start PIs input inp1; // declare the inp1 direction input inp2; // declare the inp2 direction input tau2015_clk; // declare the clock direction // Start POs output out; // deckare the out direction // Start wires wire n1; wire n2; wire n3; wire n4; wire inp1; wire inp2; wire tau2015_clk; wire out; // Start cells NAND2_X1 u1 ( .a(inp1), .b(inp2), .o(n1) ); DFF_X80 f1 ( .d(n2), .ck(tau2015_clk), .q(n3) ); INV_X1 u2 ( .a(n3), .o(n4) ); INV_X2 u3 ( .a(n4), .o(out) ); NOR2_X1 u4 ( .a(n1), .b(n3), .o(n2) ); endmodule ```

Diagram of the design.

The example declares a module *simple* with four ports: + primary input port `inp1` + primary input port `inp2` + primary input port `tau2015_clk` + primary output port `out` The design contains eight nets for internal connections: + wire `n1` connecting instance `u1` and instance `u4` + wire `n2` connecting instance `f1` and instance `u4` + wire `n3` connecting instance `f1`, instance `u2`, and instance `u4` + wire `n4` connecting instance `u2` and instance `u3` + wire `inp1` connecting primary input port `inp1` and instance `u1` + wire `inp2` connecting primary input port `inp2` and instance `u1` + wire `out` connecting primary output port `out` and instance `u3` The design uses five cells: + instance `u1` of cell `NAND2_X1`, connecting to instance `u4` and ports `inp1` and `inp2` + instance `f1` of cell `DFF_X80`, connecting to port `tau2015_clk`, instances `u4` and `u2` + instance `u2` of cell `INV_X1`, connecting to instances `f1` and `u3` + instance `u3` of cell `INV_X2`, connecting to instance `u2` and port `out` + instance `u4` of cell `NOR2_X1`, connecting to instances `u1` and `f1` # Work In Progress We are currently improving OpenTimer's capability of parsing verilog files. This includes support for: + Array syntax and bus declaration. + Hierarchical designs with multiple modules. # Reference 1. [2015 ACM TAU Timing Analysis Contest][TAU15] * * * [TAU15]: https://sites.google.com/site/taucontest2015/ # Timer The class [Timer](../../ot/timer/timer.hpp) defines a set of core methods for timing analysis under the namespace `ot`. Each method belongs to either a builder, an action, or an accessor operation. | Command | Form | Description | | :------ | :--- | :---------- | | [read_celllib](#read_celllib) | builder | reads a liberty format library file | | [read_verilog](#read_verilog) | builder | reads a gate-level verilog netlist | | [read_spef](#read_spef) | builder | reads a file of net parasitics in SPEF format | | [read_sdc](#read_sdc) | builder | reads a Synopsys Design Constraint (sdc) file of version 2.1 | | [read_timing](#read_timing) | builder | reads a TAU15 Contest assertion file of timing constraints | | [set_at](#set_at) | builder | specifies the arrival time of an input port | | [set_rat](#set_rat) | builder | specifies the required arrival time of an output port | | [set_slew](#set_slew) | builder | specifies the transition time of an input port | | [set_load](#set_load) | builder | specifies the load capacitance of an output port | | [insert_gate](#insert_gate) | builder | inserts a gate (instance) to the design | | [remove_gate](#remove_gate) | builder | removes a gate (instance) from the design | | [repower_gate](#repower_gate) | builder | repowers a gate (instance) with a new cell | | [insert_net](#insert_net) | builder | inserts an empty net to the design | | [remove_net](#remove_net) | builder | removes a net from the design | | [connect_pin](#connect_pin) | builder | connects a pin to a net | | [disconnect_pin](#disconnect_pin) | builder | disconnect a pin from the net it connects to | | [enable_cppr](#enable_cppr) | builder | enables common path pessimism removal analysis | | [disable_cppr](#disable_cppr) | builder | disables common path pessimism removal analysis | | [update_timing](#update_timing) | action | updates the timer to keep all timing values up-to-date | | [report_timing](#report_timing) | action | report the critical paths of the design | | [report_at](#report_at) | action | reports the arrival time at a pin | | [report_slew](#report_slew) | action | reports the transition time at a pin | | [report_rat](#report_rat) | action | reports the required arrival time at a pin | | [report_slack](#report_slack) | action | reports the slack at a pin | | [report_tns](#report_tns) | action | reports the total negative slack of the design | | [report_wns](#report_wns) | action | reports the worst negative slack of the design | | [report_fep](#report_fep) | action | reports the total failing endpoints in the design | | [dump_graph](#dump_graph) | accessor | dumps the timing graph to an output stream | | [dump_taskflow](#dump_taskflow) | accessor | dumps the lineage graph to an output stream | | [dump_timer](#dump_timer) | accessor | dumps the statistics of the design | | [num_primary_inputs](#num_primary_inputs)| accessor | queries the number of primary inputs in the design | | [num_primary_outputs](#num_primary_outputs)| accessor | queries the number of primary outputs in the design | | [num_pins](#num_pins)| accessor | queries the number of pins in the design | | [num_nets](#num_nets)| accessor | queries the number of nets in the design | | [num_arcs](#num_arcs)| accessor | queries the number of arcs in the timing graph | | [num_gates](#num_gates)| accessor | queries the number of gates in the design | | [num_tests](#num_tests)| accessor | queries the number of timing tests (checks) in the design | | [primary_inputs](#primary_inputs)| accessor | acquires a const reference to the data structure of primary inputs | | [primary_outputs](#primary_outputs)| accessor | acquires a const reference to the data structure of primary outputs | | [pins](#pins) | accessor | acquires a const reference to the data structure of pins | | [nets](#nets) | accessor | acquires a const reference to the data structure of nets | | [gates](#gates) | accessor | acquires a const reference to the data structure of gates | | [clocks](#clocks)| accessor | acquires a const reference to the data structure of clocks | | [tests](#tests) | accessor | acquires a const reference to the data structure of tests | | [arcs](#arcs)| accessor | acquires a const reference to the data structure of arcs | The above list of methods is consider stable. Other methods found in [timer.hpp](../../ot/timer/timer.hpp) but not listed in the table may change in the future release. --- ## read_celllib Reads a Liberty format library file. In most cases, this is the first method to initialize a timing analysis framework. ```cpp Timer& read_celllib(std::filesystem::path path, std::optional split = {}); ``` #### Parameters + path: the file path of the liberty file to read + split: use this library for either min or max delay calculation #### Return Value `*this` #### Notes The method adds two tasks to the lineage graph; one parses the library and the other attaches the library to the timer.
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--- ## read_verilog Reads a gate-level verilog netlist and initializes the circuit graph from the library. ```cpp Timer& read_verilog(std::filesystem::path path); ``` #### Parameters + path: the file path of the verilog netlist to read #### Return Value `*this` #### Notes The method adds two tasks to the lineage graph; one parses the verilog file and the other initializes the circuit graph from it.
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--- ## read_spef Reads a parasitics file in SPEF. ```cpp Timer& read_spef(std::filesystem::path path); ``` #### Parameters + path: the path of the SPEF file to read #### Return Value `*this` #### Notes The method adds two tasks to the lineage graph; one parses the SPEF file and the other digests the net parasitics.
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--- ## read_sdc Reads a Synopsys Design Constraint (SDC) file. ```cpp Timer& read_sdc(std::filesystem::path path); ``` #### Parameters + path: the path of the sdc file to read #### Return Value `*this` #### Notes The method adds two tasks to the lineage graph; one parses the sdc file and the other digests the timing constraints. The supporting status of SDC commands is described [here](../io/sdc.md).
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--- ## read_timing Reads a [TAU15 Contest Format][TAU15] timing assertion file. ```cpp Timer& read_timing(std::filesystem::path path); ``` #### Parameters + path: the path of the timing assertion file to read #### Return Value `*this` #### Notes The method adds two tasks to the lineage graph; one parses the timing file and the other digests the timing constraints.
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--- ## set_at Specifies the arrival time of an input port at a given min/max split and rise/fall transition. ```cpp Timer& set_at(std::string port, Split split, Tran tran, std::optional value); ``` #### Parameters + port: the name of the input port + split: the minimum or maximum arrival time + tran: the rising or falling edge + value: the arrival time value; use `std::nullopt` to unset the arrival time of the port #### Return Value `*this`
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--- ## set_rat Specifies the required arrival time of an output port at a given min/max split and rise/fall transition. ```cpp Timer& set_rat(std::string port, Split split, Tran tran, std::optional value); ``` #### Parameters + port: the name of the output port + split: the required arrival time at min or max split + tran: the rising or falling edge + value: the arrival time value; use `std::nullopt` to unset the arrival time of the port #### Return Value `*this`
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--- ## set_slew Specifies the transition time of an input port at a given min/max split and rise/fall transition. ```cpp Timer& set_at(std::string port, Split split, Tran tran, std::optional value); ``` #### Parameters + port: the name of the input port + split: the minimum or maximum transition time + tran: the rising or falling edge + value: the transition time value; use `std::nullopt` to unset the transition time of the port #### Return Value `*this` --- ## set_load Specifies the load capacitance of an output port at a given min/max split and rise/fall transition. ```cpp Timer& set_load(std::string port, Split split, Tran tran, std::optional value); ``` #### Parameters + port: the name of the output port + split: the load capacitance at min or max split + tran: the load capacitance at rising or falling edge + value: the load capacitance value; use `std::nullopt` to unset the load capacitance of the port #### Return Value `*this` --- ## insert_gate Inserts a gate into the design. The newly inserted gate is not connected to any other gates or wires. ```cpp Timer& insert_gate(std::string gate, std::string cell); ``` #### Parameters + gate: the name of the gate to insert to the design + cell: the name of the cell to associate with the gate #### Return Value `*this` --- ## remove_gate Removes a gate from the design. The gate will be disconnected from the design before removal. ```cpp Timer& remove_gate(std::string gate); ``` #### Parameters + gate: the name of the gate to remove from the design #### Return Value `*this` --- ## repower_gate Changes the size or the level of an existing gate, or insert a new gate if it does not exist. ```cpp Timer& repower_gate(std::string gate, std::string cell); ``` #### Parameters + gate: the name of the gate to repower + cell: the name of the cell to associate with the gate #### Return Value `*this` #### Notes The topology of the new cell must be the same as the old cell, or it can result in undefined behavior. However the pin capacitance, for example, of the new cell can be different. --- ## insert_net Inserts an empty net object to the design. ```cpp Timer& insert_net(std::string net); ``` #### Parameters + net: the name of the net to insert to the design #### Return Value `*this` #### Notes The net will be connected to existing pins in the design by the method `connect_pin`. --- ## remove_net Removes a net from the design. ```cpp Timer& remove_net(std::string net); ``` #### Parameters + net: the name of the net to remove from the design #### Return Value `*this` #### Note If a net is connected to pins, the pins will be automatically disconnected from the net. The corresponding parasitics will also be removed. --- ## connect_pin Connects a pin to a net. ```cpp Timer& connect_pin(std::string pin, std::string net); ``` #### Parameters + pin: the name of the pin + net: the name of the net #### Return Value `*this` --- ## disconnect_pin Disconnects a pin from the net it connects to. ```cpp Timer& disconnect_pin(std::string pin); ``` #### Parameters + pin: the name of the pin #### Return Value `*this` --- ## enable_cppr Enables the common path pessimism removal (CPPR) analysis. ```cpp Timer& enable_cppr(); ``` #### Parameters none #### Return Value `*this` --- ## disable_cppr Disables the common path pessimism removal (CPPR) analysis. ```cpp Timer& disable_cppr(); ``` #### Parameters none #### Return Value `*this` --- ## update_timing Triggers the timing update to keep all timing information (arrival time, slew, required arrival time, etc) up-to-date. ```cpp void update_timing(); ``` #### Paramters none #### Return Value none #### Notes This is the bottom-most call of all action methods. --- ## report_timing Reports the critical paths of the design. ```cpp 1. std::vector report_timing(size_t k); 2. std::vector report_timing(size_t k, Split split, Tran tran) 3. std::vector report_timing(size_t k, Split split) 4. std::vector report_timing(size_t k, Tran tran) ``` #### Paramters 1. reports the top-k critical paths across all endpoints + K: the number of paths to report 2. reports the top-k critical min/max paths for rising/falling endpoints + K: the number of paths to report + split: minimum or maximum path + tran: rising or falling endpoints 3. report the top-k critical min/max paths across both rising and falling endpoints + K: the number of paths to report + split: minimum or maximum path 4. report the top-k critical paths for rising/falling endpoints + K: the number of paths to report + tran: rising or falling endpoints #### Return Value A vector of paths of type `Path`, defined in [path.hpp][ot::Path]. --- ## report_at Reports the arrival time of a pin at a given min/max split and rise/fall edge. ```cpp std::optional report_at(const std::string& pin, Split split, Tran tran); ``` #### Parameters + pin: the name of the pin to report + split: the minimum or maximum arrival time + tran: the rising or falling edge #### Return Value Returns the arrival time if found, or `std::nullopt`. #### Notes The arrival time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin. --- ## report_rat Reports the required arrival time of a pin at a given min/max split and rise/fall edge. ```cpp std::optional report_rat(const std::string& pin, Split split, Tran tran); ``` #### Parameters + pin: the name of the pin to report + split: the minimum or maximum required arrival time + tran: the rising or falling edge #### Return Value Returns the required arrival time if found, or `std::nullopt`. #### Notes The required arrival time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin. --- ## report_slew Reports the transition time of a pin at a given min/max split and rise/fall edge. ```cpp std::optional report_slew(const std::string& pin, Split split, Tran tran); ``` #### Parameters + pin: the name of the pin to report + split: the minimum or maximum transition time + tran: the rising or falling edge #### Return Value Returns the transition time if found, or `std::nullopt`. #### Notes The transition time may not be found, for example, the pin doesn't exist or the timing propagation doesn't go through the pin. --- ## report_load Reports the load capacitance of a net at a given min/max split and rise/fall edge. ```cpp std::optional report_load(const std::string& pin, Split split, Tran tran); ``` #### Parameters + pin: the name of the pin to report + split: the minimum or maximum load capacitance + tran: the rising or falling edge #### Return Value Returns the load capacitance if found, or `std::nullopt`. #### Notes The load capacitance may not be found, for example, the net doesn't exist or the timing propagation doesn't go through the net. --- ## report_tns Reports the total negative slack (TNS) across all endpoints. ```cpp std::optional report_tns(); ``` #### Parameters none #### Return Value Returns the total negative slack if found, or `std::nullopt`. #### Notes The total negative slack may not be found, for example, the timing propagation doesn't go through any endpoints. --- ## report_wns Reports the worst negative slack (WNS) across all endpoints. ```cpp std::optional report_wns(); ``` #### Parameters none #### Return Value Returns the worst negative slack if found, or `std::nullopt`. #### Notes The worst negative slack may not be found, for example, the timing propagation doesn't go through any endpoints. --- ## report_fep Reports the total number of failing endpoints (FEP) across all endpoints. ```cpp std::optional report_fep(); ``` #### Parameters none #### Return Value Returns the total number of failing endpoints if found, or `std::nullopt`. #### Notes The total number of failing endpoints may be be found, for example, the timing propagation doesn't go through any endpoints. --- ## dump_graph Dumps the timing graph to a DOT format. ```cpp void dump_graph(std::ostream& ostream) const; ``` #### Parameters + ostream: the target output stream to dump #### Return Value none --- ## dump_taskflow Dumps the lineage graph to a DOT format. ```cpp void dump_taskflow(std::ostream& ostream) const; ``` #### Parameters + ostream: the target output stream to dump #### Return Value none --- ## dump_timer Dumps the statistics of the design. ```cpp void dump_timer(std::ostream& ostream) const; ``` #### Parameters + ostream: the target output stream to dump #### Return Value none --- ## num_primary_inputs Queries the number of primary inputs in the design. ```cpp size_t num_primary_inputs() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of primary inputs in the design. --- ## num_primary_outputs Queries the number of primary outputs in the design. ```cpp size_t num_primary_outputs() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of primary outputs in the design. --- ## num_pins Queries the number of pins in the design. ```cpp size_t num_pins() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of pins in the design. --- ## num_nets Queries the number of nets in the design. ```cpp size_t num_nets() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of nets in the design. --- ## num_arcs Queries the number of arcs in the design. ```cpp size_t num_arcs() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of arcs in the design. --- ## num_gates Queries the number of gates in the design. ```cpp size_t num_gates() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of gates in the design. --- ## num_tests Queries the number of tests (checks) in the design. ```cpp size_t num_tests() const; ``` #### Parameters none #### Return Value An unsigned integer for the number of tests in the design. --- ## primary_inputs Acquires a const reference to the data structure of primary inputs. ```cpp const std::unordered_map& primary_inputs() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of primary inputs. --- ## primary_outputs Acquires a const reference to the data structure of primary outputs. ```cpp const std::unordered_map& primary_outputs() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of primary outputs. --- ## pins Acquires a const reference to the data structure of pins. ```cpp const std::unordered_map& pins() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of pins. --- ## nets Acquires a const reference to the data structure of nets. ```cpp const std::unordered_map& nets() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of nets. --- ## gates Acquires a const reference to the data structure of gates. ```cpp const std::unordered_map& gates() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of gates. --- ## clocks Acquires a const reference to the data structure of clocks. ```cpp const std::unordered_map& clocks() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of clocks. --- ## tests Acquires a const reference to the data structure of tests (timing checks). ```cpp const std::list& tests() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of tests. --- ## arcs Acquires a const reference to the data structure of arcs. ```cpp const std::list& arcs() const; ``` #### Parameters none #### Return Value A constant reference to the data structure of arcs. * * * [TAU15]: https://sites.google.com/site/taucontest2015/ [ot::Path]: ../../ot/timer/path.hpp