# VerilogHDL-Tutorial **Repository Path**: Shadowsgho/VerilogHDL-Tutorial ## Basic Information - **Project Name**: VerilogHDL-Tutorial - **Description**: FPGA&VerilogHDL应用设计教程,包括课程思维导图、各章实例、各实验源码、综合实验例程。 - **Primary Language**: Verilog - **License**: GPL-2.0 - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 78 - **Created**: 2020-09-30 - **Last Updated**: 2020-12-17 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # VerilogHDL-Tutorial #### Description FPGA&VerilogHDL应用设计教程,包括课程思维导图、各章实例、各实验源码、综合实验例程。 #### Software Architecture Software architecture description #### Installation 1. xxxx 2. xxxx 3. xxxx #### Instructions 1. xxxx 2. xxxx 3. xxxx #### Contribution 1. Fork the repository 2. Create Feat_xxx branch 3. Commit your code 4. Create Pull Request #### Gitee Feature 1. You can use Readme\_XXX.md to support different languages, such as Readme\_en.md, Readme\_zh.md 2. Gitee blog [blog.gitee.com](https://blog.gitee.com) 3. Explore open source project [https://gitee.com/explore](https://gitee.com/explore) 4. The most valuable open source project [GVP](https://gitee.com/gvp) 5. The manual of Gitee [https://gitee.com/help](https://gitee.com/help) 6. The most popular members [https://gitee.com/gitee-stars/](https://gitee.com/gitee-stars/)