# apb_uart_sv

**Repository Path**: bianw11/apb_uart_sv

## Basic Information

- **Project Name**: apb_uart_sv
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: pulpinov1
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-12-24
- **Last Updated**: 2021-12-24

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# APB UART (SystemVerilog)

This module implements the basic interface you would expect from a standard TI 16550 UART. It exists because of current incompatibility of Verilator to understand our VHDL based UART. This UART will likely vanish with the release of our uDMA based peripherals.