# qrio_handout

**Repository Path**: chen-guanxuQAQ/qrio_handout

## Basic Information

- **Project Name**: qrio_handout
- **Description**: 复旦大学《计算机体系结构》课程lab
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 200
- **Created**: 2023-03-23
- **Last Updated**: 2023-06-10

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Architecture Labs: QRIO – Lab4

### 0. Overall

In this lab you will complete a cache simulator whose codes are stored in *interrio\clients\drcachesim\simulator*. 

The cache simulator is based on [DynamoRIO](https://dynamorio.org/) drcachesim which can simulate the full cache hierarchy. In this lab we configure a 16-cores hierarchy including three cache level: L1, L2 and LLC. There are totally 16 CPU cores, every core has a L1i cache and L1d cache which only store instruction and ordinary data separately. The L1i cache and L1d cache in the same core have a common parent(means cache in the lower level of hierarchy) named L2 cache which store instruction and ordinary data in the meantime. That is, every core has 2 L1 cache and 1 L2 cache. And every 4 cores share a LLC(Last Level Cache). You can examine the configuration details in *interrio/cache16.config*.

The most parts of the simulator has been implemented, you should mainly complete the function caching_device::request in *interrio\clients\drcachesim\simulator\caching_device.cpp* and some other functions as required. The **TODO** notes will tell you what to do. You are just asked to write codes of simulating a single cache device and don't have to care about the relation between caches in the hierarchy. Actually only a few of codes need to be written. 

### 1. Run the cache tool

Before execute the **run-rio** script, add *cache* into *qr/tools.config*.

When you want to validate your cache simulator with your own program, you may find that the results are not as expected. This is because the simulator will receive the data from your program and operating system at the same time. You can modify *interrio/run.sh*, use option -only_usr to filter out the kernel data like this:

```bash
./build/bin64/drrun -t drcachesim -only_usr -ins 1000 -channel 1 -indir drmemtrace.a.out.48252.0183.dir/ -config_file cache16.config
```
Remember to delete -only_usr after validation.

### 2. Task

(1) Complete the cache simulator, replace policy LRU and FIFO are both needed.

(2) Add the detail of how you identify three types of cache miss in report.

(3) Design one or several applications to validate your cache simulator, show the detail and results in report. Just a large array access is enough.

**Hint: Option -only_usr mentioned above may help.**

(4) Use your cache simulator to run the benchmark **bzip2**, try to analyze the app's character with the output of simulator.

(5) Design several experiments to check the effect of cache size or replace policy on miss rate.

### 3. Cross-compile application

In this lab, you are asked to write several small applications to validate your cache simulator. We have provided the aarch64 cross-compiler in docker container and the path is **/usr/bin/aarch64-linux-gnu-gcc**.

When you finished your applications, use **aarch64-linux-gnu-gcc** to compile it and then put it in your disk image as the following step:

```bash
docker exec -it qrio /bin/bash
use cross-compiler to compiler your app
mount /root/assets/disk.img /mnt
cp "your app" /mnt/home
umount /mnt
```

### 4. Submit

After finishing lab4, please mark your final version using git tag as follows:

```bash
git tag -a v4.0 -m "Lab4 finish"
```

(We will take the commit marked by this tag as the source code submission of your lab4)

Submit your lab report which contains:

* Your lab repository link (formats like https://gitee.com/xxx/qrio_handout.git)

* Description of your implememtation of cache simulator.

* Other required text described in **TASK** section.

* The output and your analysis of all of your experiments.