# uvm-project-template

**Repository Path**: courageheart/uvm-project-template

## Basic Information

- **Project Name**: uvm-project-template
- **Description**: No description available
- **Primary Language**: Python
- **License**: Not specified
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-12-04
- **Last Updated**: 2025-12-04

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# UVM Project Generator

A Python script to quickly scaffold a complete UVM (Universal Verification Methodology) verification project structure with all necessary template files.

## Features

**Generates a complete UVM project structure** including:
- RTL directory with placeholder DUT file
- Testbench with interface, transaction, driver, monitor, agent, scoreboard, and environment
- Sequence library with random and directed sequences
- Test directory with base and random tests
- Simulation directory with Makefile
- Documentation with README

**Production-ready templates** based on industry-standard UVM practices

**Customizable** - All files include TODO comments to guide customization

## Requirements

- Python 3.6 or higher
- SystemVerilog simulator with UVM support (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)

## Installation

No installation required! Just clone or download this directory.

## Usage

### Windows (PowerShell/CMD)

```batch
cd uvm-template
make_uvm_project.bat <project_name> [output_directory]
```

### Linux/Mac/Git Bash

```bash
cd uvm-template
chmod +x make_uvm_project.sh
./make_uvm_project.sh <project_name> [output_directory]
```

### Direct Python Usage

```bash
python generate_uvm_project.py <project_name> [--output OUTPUT_DIR]
```

### Example

```bash
# Create a project for a 16-bit adder
python generate_uvm_project.py adder_16b

# Create in specific directory
python generate_uvm_project.py adder_16b --output C:/Projects

# Using short form
python generate_uvm_project.py fifo_sync -o ../my_projects
```

This will create:
```
adder_16b/
├── README.md
├── doc/
├── rtl/
│   └── adder_16b.sv
├── sim/
│   └── Makefile
└── tb/
    ├── adder_16b_if.sv
    ├── tb_top.sv
    ├── uvm_env/
    │   ├── adder_16b_transaction.sv
    │   ├── adder_16b_driver.sv
    │   ├── adder_16b_monitor.sv
    │   ├── adder_16b_agent.sv
    │   ├── adder_16b_scoreboard.sv
    │   ├── adder_16b_env.sv
    │   └── adder_16b_env_pkg.sv
    ├── seq_lib/
    │   ├── adder_16b_random_seq.sv
    │   ├── adder_16b_read_write_seq.sv
    │   └── seq_lib_pkg.sv
    └── tests/
        ├── adder_16b_base_test.sv
        ├── adder_16b_random_test.sv
        └── tests_pkg.sv
```

## Project Structure

The generated project follows this hierarchy:

```
<project_name>/
├── README.md                          # Project documentation
├── doc/                               # Documentation directory
├── rtl/                               # RTL design files
│   └── <project_name>.sv              # DUT module (placeholder)
├── tb/                                # Testbench files
│   ├── <project_name>_if.sv           # Interface definition
│   ├── tb_top.sv                      # Testbench top module
│   ├── uvm_env/                       # UVM environment components
│   │   ├── <project_name>_transaction.sv
│   │   ├── <project_name>_sequencer.sv
│   │   ├── <project_name>_driver.sv
│   │   ├── <project_name>_monitor.sv
│   │   ├── <project_name>_agent.sv
│   │   ├── <project_name>_scoreboard.sv
│   │   ├── <project_name>_env.sv
│   │   └── <project_name>_env_pkg.sv
│   ├── seq_lib/                       # Sequence library
│   │   ├── <project_name>_random_seq.sv
│   │   ├── <project_name>_read_write_seq.sv
│   │   └── seq_lib_pkg.sv
│   └── tests/                         # Test cases
│       ├── <project_name>_base_test.sv
│       ├── <project_name>_random_test.sv
│       └── tests_pkg.sv
└── sim/                               # Simulation files
    ├── Makefile
    └── vc_hdrs.h
```

## After Generation

Once the project is generated, follow these steps:

1. **Navigate to the project directory**
   ```bash
   cd <project_name>
   ```

2. **Read the generated README.md**
   ```bash
   cat README.md
   ```

3. **Customize the components** (see TODO items in each file):
   - Define interface signals in `tb/<project_name>_if.sv`
   - Add transaction fields in `tb/uvm_env/<project_name>_transaction.sv`
   - Implement drive logic in `tb/uvm_env/<project_name>_driver.sv`
   - Implement monitor logic in `tb/uvm_env/<project_name>_monitor.sv`
   - Add checking logic in `tb/uvm_env/<project_name>_scoreboard.sv`
   - Implement your RTL design in `rtl/<project_name>.sv`
   - Connect DUT in `tb/tb_top.sv`

4. **Run simulation**
   ```bash
   cd sim
   make clean
   make
   ```

## Customization Guide

### 1. Interface Signals
Edit `tb/<project_name>_if.sv` to add your protocol signals:
```systemverilog
logic [31:0] data_in;
logic [31:0] data_out;
logic        valid;
logic        ready;
```

### 2. Transaction Fields
Edit `tb/uvm_env/<project_name>_transaction.sv`:
```systemverilog
rand bit [31:0] operand_a;
rand bit [31:0] operand_b;
bit [31:0] result;
```

### 3. Driver Logic
Implement `drive_transfer()` in `tb/uvm_env/<project_name>_driver.sv`

### 4. Monitor Logic
Implement `monitor_transactions()` in `tb/uvm_env/<project_name>_monitor.sv`

### 5. Scoreboard Checking
Add your checking logic in `tb/uvm_env/<project_name>_scoreboard.sv`

## UVM Component Hierarchy

```
Test
 └── Environment
      ├── Agent
      │    ├── Driver
      │    ├── Sequencer
      │    └── Monitor
      └── Scoreboard
```

## Running Tests

From the `sim/` directory:

```bash
# Run default test
make

# Run specific test
make TESTNAME=<project_name>_random_test

# Clean build artifacts
make clean
```

## Viewing Waveforms

The simulation generates `dump.vcd` files:

```bash
# Using GTKWave
gtkwave dump.vcd &

# Using DVE (Synopsys)
dve -vpd dump.vcd &
```

## Tips

1. **Start Simple**: Begin with the base test and verify basic functionality
2. **Incremental Development**: Add one feature at a time
3. **Use Waveforms**: Debug with waveform viewers when tests fail
4. **Check Logs**: Review `compile.log` and `run.log` for errors
5. **Follow TODO Items**: Each generated file has TODO comments to guide you

## Examples of Valid Project Names

- `fifo_sync`
- `alu_32bit`
- `spi_master`
- `uart_tx`
- `cache_controller`
- `adder_16b`

## Output Directory Control

You can specify where projects are generated:

```bash
# Current directory (default)
python generate_uvm_project.py my_design

# Parent directory
python generate_uvm_project.py my_design -o ..

# Specific path
python generate_uvm_project.py my_design -o C:/Projects

# Using wrapper
make_uvm_project.bat my_design C:/Projects
```

## Troubleshooting

### Python not found
- Ensure Python 3.6+ is installed
- On Windows: Add Python to PATH
- Try `python3` instead of `python`

### Simulator not found
- Ensure VCS/Questa/Xcelium is installed
- Source the simulator setup script
- Check Makefile for correct simulator commands

### Compilation errors
- Verify all TODO items are addressed
- Check interface signal connections
- Ensure DUT is properly instantiated in tb_top

## Contributing

Feel free to customize this template generator for your specific needs!

## License

Free to use and modify for educational and commercial purposes.

## Author

Based on UVM best practices and industry-standard verification methodologies.