# verilog-can

**Repository Path**: courageheart/verilog-can

## Basic Information

- **Project Name**: verilog-can
- **Description**: No description available
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2025-08-04
- **Last Updated**: 2025-08-04

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

Verilog CAN controller
======================

This is a fork of https://opencores.org/projects/can with the intention
to improve code quality and fix several bugs.

This is very much work in progess. I started working on it in 2019 when
I needed fixes, but then lost track as issues were solved a different way.
Hopefully the project can be picked up again now.


More information to come.


State
=====

Currently nonfunctional.


Authors
=======

Authors:

 * Igor Mohor <igorm@opencores.org> --  Author of the original version
   at http://www.opencores.org/projects/can/
   (which has been unmaintained since about 2009)

 * David Piegdon <dgit@piegdon.de> -- Picked up project for cleanup and
   bugfixes in 2019


License
=======

Please see LICENSE file.