# riscv_emulator

**Repository Path**: feng-qi/riscv_emulator

## Basic Information

- **Project Name**: riscv_emulator
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-06-03
- **Last Updated**: 2021-06-03

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

Code from video =Writing an Extremely Fast RISC-V Emulator and Fuzzing with it!=

- YouTube: https://www.youtube.com/playlist?list=PLSkhUfcCXvqEZwThjTGBORXnBYaO9TwLD
- Bilibili: https://www.bilibili.com/video/BV1Fv411a7ED

Up to time point 02:36:39. After this point the code in the video is coded from
scratch, so I'm unable to type that out. But the decode part can still be
useful.

I also recorded the timeline for decode part:

```
00:00:00  skim risc-v spec
00:46:52  clean up old codes
00:53:40  begin coding for I-type (decode begin)
01:44:15    end coding for I-type
01:45:12  begin coding for U-type
01:59:51    end coding for U-type
01:59:52  begin coding for R-type
02:06:52    end coding for R-type
02:06:54  begin coding for B-type
02:19:15    end coding for B-type
02:19:17  begin coding for J-type
02:26:59    end coding for J-type
02:27:00  search for and add missed instruction
02:28:45    Add: Addiw Slliw Srliw Sraiw
02:33:44    Add: Addw Subw Sllw Srlw Sraw
02:36:39  decode finish
```