# pyhdl

**Repository Path**: gendai/pyhdl

## Basic Information

- **Project Name**: pyhdl
- **Description**: 使用mhdl来减少verilog的逻辑申明和连接
- **Primary Language**: Python
- **License**: AGPL-3.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-09-14
- **Last Updated**: 2026-09-23

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# PyHDL

A lightweight Python-based HDL toolchain centered around **MetaHDL** (`.mhdl`),
a small hardware description language that compiles to **Verilog** (`.v`).

## What's inside

| Component | Description |
|-----------|-------------|
| `mhdlc/` | MetaHDL compiler: lexer, parser, AST, code generator and wrapper |
| `bin/` | Command-line entry points |
| `scripts/` | Helper scripts: FIFO generator, BNF-to-LaTeX, `.vp` state-machine converter, simulation runner |
| `tests/` | pytest test suite |
| `examples/` | Sample MetaHDL source files |
| `docs/` | Markdown design notes |

## Quick start

Compile a MetaHDL source file to Verilog:

```bash
python bin/mhdlc.py examples/moda.mhdl -o out/moda.v
```

Or use the unified entry point:

```bash
python bin/pyhdl_run.py mhdlc examples/moda.mhdl -o out
```

## Running tests

```bash
python -m pytest tests
```

All existing tests should pass.

## Roadmap

- [x] Basic MetaHDL lexer / parser
- [x] AST and Verilog code generation
- [x] CLI entry points (`mhdlc`, `pyhdl_run`)
- [ ] Extended language features (interfaces, structs, packages)
- [ ] End-to-end simulation workflow verification
- [ ] More examples and documentation