# SIFT-implementation-in-Verilog
**Repository Path**: greitzmann/SIFT-implementation-in-Verilog
## Basic Information
- **Project Name**: SIFT-implementation-in-Verilog
- **Description**: Using Verilog to implement the SIFT algorithm into an FPGA for small robotic situations
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No
## Statistics
- **Stars**: 0
- **Forks**: 0
- **Created**: 2019-11-18
- **Last Updated**: 2020-12-19
## Categories & Tags
**Categories**: Uncategorized
**Tags**: None
## README
Project Report
Nathan Brummel (cs150-ba) & Tyler McAtee (cs150-ar)
abstract
This paper discusses our process for adding a hardware acceleration module to the Scale Invariant Feature Transform (SIFT) algorithm. When running an algorithm often about 90 percent of program runtime energy is consumed by 10 percent of the code. These parts of the code are frequently data processing intensive, and by adding custom hardware to speed up these sections, the overall algorithm speeds up drastically.
The SIFT algorithm is a computer vision algorithm used to detect and describe local features in images. We described several hardware modules using Verilog to aid in expediting the process of this algorithm. The first major module discussed in this paper is the SRAM Arbiter, which efficiently services two write ports and two read ports that aretrying to connect to an external SRAM module. The second major module discussed is the Difference of Gaussians calculation module, which takes in a byte stream of pixel data, down samples it to a more manageable size (due to on-board FPGA memory constraints), runs a Difference of Gaussians calculation, and up samples it to the original size again.
The REPORT
Tools Used
-
Bonato, V.; Marques, E.; Constantinides, G.A.,
"A Parallel Hardware
Architecture for Scale and Rotation Invariant Feature Detection,"
Circuits and Systems for Video Technology, IEEE Transactions on ,
vol.18, no.12, pp.1703,1712, Dec. 2008
doi: 10.1109/TCSVT.2008.2004936
- Verilog
- Virtex-5 FPGA Documentation
- ChipScope
- ModelSim
- Ready/Valid handshake
Protocols & Standards
Checkpoint Progress
Checkpoint 1:
Checkpoint 1 PDF
PatternGenerator.v and PatternGeneratorTest.v up to date and working
All tests for PatternGenerator in sim folder working
Checkpoint 2:
Checkpoint 2 PDF pdf
Finished and working.
Checkpoint 3:
Checkpoint 3 PDF pdf
Finished the block diagrams.
Working.
Checkpoint 4:
Checkpoint 4 PDF pdf
Working. DOG and Gaussian filters working.
Can switch between all views.
SIFT algorithm can easily be implimented to work with entire octave.