diff --git a/arch/arm/include/armv7-m/atomic.h b/arch/arm/include/armv7-m/atomic.h new file mode 100644 index 0000000000000000000000000000000000000000..fd4cafaf62bbd4741a398685fc0ed5b29b6f1495 --- /dev/null +++ b/arch/arm/include/armv7-m/atomic.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2025 Li Auto Inc. and its affiliates + * Licensed under the Apache License, Version 2.0(the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This file should never be included directly but, rather, + * only indirectly through arch/chip/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_RTFW_ATOMIC_H +#define __ARCH_ARM_INCLUDE_ARMV7_M_RTFW_ATOMIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile aligned_data(4) int32_t Atomic; +//todo add spinlock +/* \brief Atomic addition + * \param[in/out] ptr The address of the data to perform atomic addition on + * \param[in] addVal The value to be added + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicAdd(Atomic *ptr, int32_t addVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr += addVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic subtraction + * \param[in/out] ptr The address of the data to perform atomic subtraction on + * \param[in] subVal The value to be subtracted + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicSub(Atomic *ptr, int32_t subVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr -= subVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic increment + * \param[in/out] ptr The address of the data to perform atomic increment on + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicInc(Atomic *ptr) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr += 1; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic decrement + * \param[in/out] ptr The address of the data to perform atomic decrement on + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicDec(Atomic *ptr) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr -= 1; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic OR + * \param[in/out] ptr The address of the data to perform atomic OR on + * \param[in] orVal The value to OR with + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicOr(Atomic *ptr, int32_t orVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr |= orVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic XOR + * \param[in/out] ptr The address of the data to perform atomic XOR on + * \param[in] xorVal The value to XOR with + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicXor(Atomic *ptr, int32_t xorVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr ^= xorVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic AND + * \param[in/out] ptr The address of the data to perform atomic AND on + * \param[in] andVal The value to AND with + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicAnd(Atomic *ptr, int32_t andVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr &= andVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic AND-NOT + * \param[in/out] ptr The address of the data to perform atomic AND-NOT on + * \param[in] xandVal The value to AND-NOT with + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicXand(Atomic *ptr, int32_t xandVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr &= (~xandVal); // Perform the bitwise AND-NOT operation + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic set value + * \param[in/out] ptr The address of the data to perform atomic set value on + * \param[in] setVal The value to set + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicSet(Atomic *ptr, int32_t setVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr = setVal; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic clear value + * \param[in/out] ptr The address of the data to perform atomic clear on + * \return The value before the atomic operation + */ + +static inline Atomic Os_AtomicClean(Atomic *ptr) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + *ptr = 0; + ret = *ptr; + __asm __volatile__("cpsie if"); + return ret; +} + +/* \brief Atomic compare and swap + * \details Compare *ptr with oldVal; if they are equal, update *ptr to newVal and return true, + * otherwise return false + * \param[in/out] ptr The address of the data to perform atomic compare and swap on + * \param[in] oldVal The old value to compare with + * \param[in] newVal The new value to update if comparison succeeds + * \return + * true (1) Compare and swap succeeded + * false (0) Compare and swap failed + */ + +static inline int32_t Os_AtomicCmpSwap(Atomic *ptr, int32_t oldVal, int32_t newVal) +{ + Atomic ret; + __asm __volatile__("cpsid if"); + if (*ptr == oldVal) + { + *ptr = newVal; + ret = 1; + } + else + { + ret = 0; + } + __asm __volatile__("cpsie if"); + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_RTFW_ATOMIC_H */ diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index 1fd9d48a67df0dcd2cccc7338ef421b7e8aa6530..85138ac94f17da8ae8f90554886b94e520a2c7f2 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -36,6 +36,9 @@ # include # include # include +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +#include +#endif /* CONFIG_RT_FRAMEWORK */ #endif /**************************************************************************** @@ -260,7 +263,14 @@ struct xcptcontext * such value for each processor that can receive an interrupt. */ -extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +#ifdef CONFIG_BMP +extern volatile uint32_t *g_current_regs[CONFIG_BMP_NCPUS]; +extern volatile uint32_t *g_interrupt_context[CONFIG_BMP_NCPUS]; +#else +extern volatile uint32_t *g_current_regs[CONFIG_SMP_CPUS]; +extern volatile uint32_t *g_interrupt_context[CONFIG_SMP_NCPUS]; +#endif + /**************************************************************************** * Inline functions @@ -571,7 +581,7 @@ static inline_function uint32_t up_getsp(void) noinstrument_function static inline_function uint32_t *up_current_regs(void) { -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) return (uint32_t *)g_current_regs[up_cpu_index()]; #else return (uint32_t *)g_current_regs[0]; @@ -581,7 +591,7 @@ static inline_function uint32_t *up_current_regs(void) noinstrument_function static inline_function void up_set_current_regs(uint32_t *regs) { -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) g_current_regs[up_cpu_index()] = regs; #else g_current_regs[0] = regs; @@ -594,6 +604,45 @@ static inline_function bool up_interrupt_context(void) return getipsr() != 0; } +noinstrument_function static inline void up_set_contexthdl(void * const ctxhdl) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) + g_interrupt_context[up_cpu_index()] = ctxhdl; +#else + g_interrupt_context[0] = ctxhdl; +#endif +} + +noinstrument_function static inline void * up_get_contexthdl(void) +{ +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) + irqstate_t flags = up_irq_save(); + uint32_t * ret = g_interrupt_context[up_cpu_index()]; + up_irq_restore(flags); + return (void *)ret; +#else + return g_interrupt_context[0]; +#endif +} + +static inline_function irqlevel_t up_kernel_int_save(void) +{ +#if defined(CONFIG_RT_FRAMEWORK_INT_LEVEL) && (CONFIG_RT_FRAMEWORK_INT_LEVEL == 1) + // return up_irq_level_save(CONFIG_RT_FRAMEWORK_MAX_TP_INT_LEVEL); +#else + return up_irq_save(); +#endif +} + +static inline_function void up_kernel_int_restore(irqlevel_t level) +{ +#if defined(CONFIG_RT_FRAMEWORK_INT_LEVEL) && (CONFIG_RT_FRAMEWORK_INT_LEVEL == 1) + // return up_irq_level_restore(level); +#else + return up_irq_restore(level); +#endif +} + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 61aa9d74e5de524e31c4cf342b355bb1a718541d..61eb755f8275670701cb047d1c17585e6d7ee255 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -117,7 +117,8 @@ typedef uint8_t spinlock_t; #if defined(CONFIG_ARCH_HAVE_TESTSET) \ && !defined(CONFIG_ARCH_CHIP_LC823450) \ && !defined(CONFIG_ARCH_CHIP_CXD56XX) \ - && !defined(CONFIG_ARCH_CHIP_RP2040) + && !defined(CONFIG_ARCH_CHIP_RP2040) \ + && !defined(CONFIG_ARCH_CHIP_FC7300F8MDT) static inline_function spinlock_t up_testset(volatile spinlock_t *lock) { spinlock_t ret = SP_UNLOCKED; diff --git a/arch/arm/src/armv7-m/CMakeLists.txt b/arch/arm/src/armv7-m/CMakeLists.txt index 14f7954f54b73f549a4ee22d1052115df4a379ef..bfc2d69d9ab0d468e8d4acdf1f347c8e74e2ab4c 100644 --- a/arch/arm/src/armv7-m/CMakeLists.txt +++ b/arch/arm/src/armv7-m/CMakeLists.txt @@ -71,4 +71,8 @@ if(CONFIG_ARM_COREDUMP_REGION) list(APPEND SRCS arm_dumpnvic.c) endif() +if(CONFIG_SMP OR CONFIG_BMP) + list(APPEND SRCS arm_cpuidlestack.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/armv7-m/arm_cpuidlestack.c b/arch/arm/src/armv7-m/arm_cpuidlestack.c new file mode 100644 index 0000000000000000000000000000000000000000..a1608e65e523e02d5b78cb722b34b0fee48c6ec3 --- /dev/null +++ b/arch/arm/src/armv7-m/arm_cpuidlestack.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arm_cpuidlestack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "smp.h" +#include "arm_internal.h" + +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Stack alignment macros */ + +#define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~SMP_STACK_MASK) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if CONFIG_NR_CPUS > 1 +static const uint32_t *g_cpu_stackalloc[CONFIG_NR_CPUS] = +{ + 0 + , g_cpu1_idlestack +#if CONFIG_NR_CPUS > 2 + , g_cpu2_idlestack +#if CONFIG_NR_CPUS > 3 + , g_cpu3_idlestack +#endif /* CONFIG_NR_CPUS > 3 */ +#endif /* CONFIG_NR_CPUS > 2 */ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_idlestack + * + * Description: + * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and + * setup up stack-related information in the IDLE task's TCB. This + * function is always called before up_cpu_start(). This function is + * only called for the CPU's initial IDLE task; up_create_task is used for + * all normal tasks, pthreads, and kernel threads for all CPUs. + * + * The initial IDLE task is a special case because the CPUs can be started + * in different wans in different environments: + * + * 1. The CPU may already have been started and waiting in a low power + * state for up_cpu_start(). In this case, the IDLE thread's stack + * has already been allocated and is already in use. Here + * up_cpu_idlestack() only has to provide information about the + * already allocated stack. + * + * 2. The CPU may be disabled but started when up_cpu_start() is called. + * In this case, a new stack will need to be created for the IDLE + * thread and this function is then equivalent to: + * + * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - cpu: CPU index that indicates which CPU the IDLE task is + * being created for. + * - tcb: The TCB of new CPU IDLE task + * - stack_size: The requested stack size for the IDLE task. At least + * this much must be allocated. This should be + * CONFIG_SMP_STACK_SIZE. + * + ****************************************************************************/ + +int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) +{ +#if CONFIG_NR_CPUS > 1 + uintptr_t stack_alloc; + + DEBUGASSERT(cpu > 0 && cpu < CONFIG_NR_CPUS && tcb != NULL); + + /* Get the top of the stack */ + + stack_alloc = (uintptr_t)(g_idle_topstack - CONFIG_IDLETHREAD_STACKSIZE); + + tcb->adj_stack_size = SMP_STACK_SIZE; + tcb->stack_alloc_ptr = (void *)stack_alloc; + tcb->stack_base_ptr = tcb->stack_alloc_ptr; +#endif + + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/armv7-m/arm_doirq.c b/arch/arm/src/armv7-m/arm_doirq.c index a14b24e6a4222d004b23594c68de08869bcda8fd..5c9193ff7aeec530c04ea1769324beb1b92db395 100644 --- a/arch/arm/src/armv7-m/arm_doirq.c +++ b/arch/arm/src/armv7-m/arm_doirq.c @@ -43,6 +43,7 @@ void exception_direct(void) { + int irq = getipsr(); arm_ack_irq(irq); @@ -52,6 +53,10 @@ void exception_direct(void) { up_trigger_irq(NVIC_IRQ_PENDSV, 0); } + +#if defined(CONFIG_RT_FRAMEWORK ) && (CONFIG_RT_FRAMEWORK == 1) + up_set_contexthdl(g_running_tasks[this_cpu()]->contexthdl); +#endif } uint32_t *arm_doirq(int irq, uint32_t *regs) @@ -118,5 +123,9 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) board_autoled_off(LED_INIRQ); +#if defined(CONFIG_RT_FRAMEWORK ) && (CONFIG_RT_FRAMEWORK == 1) + up_set_contexthdl(tcb->contexthdl); +#endif + return regs; } diff --git a/arch/arm/src/armv7-m/arm_initialstate.c b/arch/arm/src/armv7-m/arm_initialstate.c index ef8bbc939e78c2e3e9d0c90eb79fe4ef8b57f9bb..6e9b6a3be151818bc6a01df8d886008629ebf746 100644 --- a/arch/arm/src/armv7-m/arm_initialstate.c +++ b/arch/arm/src/armv7-m/arm_initialstate.c @@ -65,10 +65,20 @@ void up_initial_state(struct tcb_s *tcb) if (tcb->pid == IDLE_PROCESS_ID) { - tcb->stack_alloc_ptr = (void *)(g_idle_topstack - - CONFIG_IDLETHREAD_STACKSIZE); - tcb->stack_base_ptr = tcb->stack_alloc_ptr; - tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; +#ifdef CONFIG_BMP + if (up_cpu_index() > 0) + { + up_cpu_idlestack(up_cpu_index(), tcb, + CONFIG_IDLETHREAD_STACKSIZE); + } + else +#endif + { + tcb->stack_alloc_ptr = (void *)(g_idle_topstack - + CONFIG_IDLETHREAD_STACKSIZE); + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; + } #ifdef CONFIG_STACK_COLORATION /* If stack debug is enabled, then fill the stack with a @@ -186,7 +196,7 @@ void up_initial_state(struct tcb_s *tcb) noinline_function void arm_initialize_stack(void) { - uint32_t stack = up_get_intstackbase(this_cpu()) + INTSTACK_SIZE; + uint32_t stack = up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE; uint32_t temp = 0; __asm__ __volatile__ diff --git a/arch/arm/src/armv7-m/arm_systick.c b/arch/arm/src/armv7-m/arm_systick.c index 14a00bafd551b31b3fa2371bf84a6f4adaec21ad..491afa9435f76b88c15083522e68414ccad4bcfc 100644 --- a/arch/arm/src/armv7-m/arm_systick.c +++ b/arch/arm/src/armv7-m/arm_systick.c @@ -322,5 +322,4 @@ struct timer_lowerhalf_s *systick_initialize(bool coreclk, return (struct timer_lowerhalf_s *)lower; } - #endif /* CONFIG_ARMV7M_SYSTICK */ diff --git a/arch/arm/src/armv7-m/arm_vectors.c b/arch/arm/src/armv7-m/arm_vectors.c index 0afab18fd4ed67f5dc20254a772a2f75f8fe49ad..0ca0d61d316c31f6115550c7c917909739ca69cd 100644 --- a/arch/arm/src/armv7-m/arm_vectors.c +++ b/arch/arm/src/armv7-m/arm_vectors.c @@ -47,7 +47,12 @@ * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_BMP) +extern uint32_t _dtcm_stack_end[]; +#define IDLE_STACK (_dtcm_stack_end) +#else #define IDLE_STACK (_ebss + CONFIG_IDLETHREAD_STACKSIZE) +#endif /**************************************************************************** * Private Functions @@ -59,6 +64,10 @@ extern void __start(void); static void start(void) { + /* Set MSP & PSP to the value at reset */ + + arm_initialize_stack(); + /* Zero lr to mark the end of backtrace */ asm volatile ("mov lr, #0\n\t" diff --git a/arch/arm/src/armv7-m/smp.h b/arch/arm/src/armv7-m/smp.h new file mode 100644 index 0000000000000000000000000000000000000000..f04120a789f08650bf3fb1f480263f05384a21ee --- /dev/null +++ b/arch/arm/src/armv7-m/smp.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/smp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_M_SMP_H +#define __ARCH_ARM_SRC_ARMV7_M_SMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_SMP) || defined(CONFIG_BMP) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ARM requires at least a 4-byte stack alignment. For use with EABI and + * floating point, the stack must be aligned to 8-byte addresses. We will + * always use the EABI stack alignment + */ + +#define SMP_STACK_ALIGNMENT 8 +#define SMP_STACK_MASK 7 +#define SMP_STACK_SIZE ((CONFIG_IDLETHREAD_STACKSIZE + 7) & ~7) +#define SMP_STACK_WORDS (SMP_STACK_SIZE >> 2) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#if CONFIG_NR_CPUS > 1 +extern uint32_t g_cpu1_idlestack[SMP_STACK_WORDS]; +#if CONFIG_NR_CPUS > 2 +extern uint32_t g_cpu2_idlestack[SMP_STACK_WORDS]; +#if CONFIG_NR_CPUS > 3 +extern uint32_t g_cpu3_idlestack[SMP_STACK_WORDS]; +#if CONFIG_NR_CPUS > 4 +# error This logic needs to extended for CONFIG_NR_CPUS > 4 +#endif /* CONFIG_NR_CPUS > 4 */ +#endif /* CONFIG_NR_CPUS > 3 */ +#endif /* CONFIG_NR_CPUS > 2 */ +#endif /* CONFIG_NR_CPUS > 1 */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_SMP */ +#endif /* __ARCH_ARM_SRC_ARMV7_M_SMP_H */ diff --git a/arch/arm/src/common/arm_initialize.c b/arch/arm/src/common/arm_initialize.c index d1861e81901a89c2c7d2840976405f187778a56a..4c7a764d457a2c96f705f0998378c6c7feed07e5 100644 --- a/arch/arm/src/common/arm_initialize.c +++ b/arch/arm/src/common/arm_initialize.c @@ -40,7 +40,10 @@ #if defined(CONFIG_ARCH_ARMV7M) || defined(CONFIG_ARCH_ARMV8M) || \ defined(CONFIG_ARCH_ARMV6M) || defined(CONFIG_ARCH_ARM) -volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +volatile uint32_t *g_current_regs[CONFIG_NR_CPUS]; +#if defined(CONFIG_ARCH_CHIP_FC7300F8MDT) +volatile uint32_t *g_interrupt_context[CONFIG_NR_CPUS]; +#endif #endif #if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) diff --git a/include/nuttx/compiler.h b/include/nuttx/compiler.h index 5a405ac50e5b6636d47bdfe137c17cc12ac24d2e..a2ac5bac87d84d73229f2370e1c16351191db6da 100644 --- a/include/nuttx/compiler.h +++ b/include/nuttx/compiler.h @@ -1245,7 +1245,7 @@ extern unsigned long g_cpu_data_size; #ifdef CONFIG_BMP -#if defined(CONFIG_ARCH_TRICORE) || defined(CONFIG_ARCH_CHIP_E3650) || defined(CONFIG_ARCH_CHIP_J6E) || defined(CONFIG_ARCH_CHIP_SCHU_ISP) +#if defined(CONFIG_ARCH_TRICORE) || defined(CONFIG_ARCH_CHIP_E3650) || defined(CONFIG_ARCH_CHIP_J6E) || defined(CONFIG_ARCH_CHIP_SCHU_ISP) || defined(CONFIG_ARCH_CHIP_FC7300F8MDT) #include "arch/chip/per_cpu_def.h" #else #define __percpu_data