diff --git a/CMakeLists.txt b/CMakeLists.txt index 72c4b58a131c4c2a0b7e32f40487d9ffcbe26d2e..b03844151514d6cccc9e4981db0de77eeca709cc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -32,7 +32,6 @@ # ~~~ # Request a version available on latest Ubuntu LTS (20.04) - cmake_minimum_required(VERSION 3.16) # Handle newer CMake versions correctly by setting policies @@ -132,12 +131,18 @@ else() list(GET CONFIG_ARRAY 0 NUTTX_BOARD) list(GET CONFIG_ARRAY 1 NUTTX_CONFIG) - + message("vcos kernel nutxx*****************") + message("${NUTTX_CONFIG}") + message("vcos kernel nutxx*****************") + message("${NUTTX_BOARD_DIR}") + message("vcos kernel nutxx*****************") file( GLOB NUTTX_BOARD_DIR LIST_DIRECTORIES true "${NUTTX_DIR}/boards/*/*/${NUTTX_BOARD}") - + message("vcos kernel nutxx*****************1111") + message("${NUTTX_BOARD_DIR}") + message("vcos kernel nutxx*****************1111") if(EXISTS ${NUTTX_BOARD_DIR}/configs/${NUTTX_CONFIG}/defconfig) set(NUTTX_DEFCONFIG ${NUTTX_BOARD_DIR}/configs/${NUTTX_CONFIG}/defconfig) endif() @@ -394,7 +399,6 @@ if(CONFIG_ARCH_BOARD_COMMON) endif() # Setup toolchain ############################################################ - # This needs to happen before project() when binaries are searched for list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/arch/${CONFIG_ARCH}/src/cmake) @@ -403,19 +407,15 @@ set(CMAKE_TOOLCHAIN_FILE # Define project ############################################################# # This triggers configuration - project(NuttX LANGUAGES C CXX ASM) - # include common toolchain setting include(nuttx_toolchain) if(WIN32) enable_language(ASM_MASM) endif() - # Setup platform options (this needs to happen after project(), once the # toolchain file has been processed) - # Support custom Toolchain options by custom Boards if(CONFIG_ARCH_BOARD_CUSTOM) if(EXISTS ${NUTTX_BOARD_ABS_DIR}/cmake @@ -428,7 +428,6 @@ endif() include(platform) # Setup main nuttx target #################################################### - add_executable(nuttx) add_custom_target(nuttx_post) if(CONFIG_BUILD_PROTECTED) @@ -528,11 +527,13 @@ endif() # deterministic. Debuggers usually have a path mapping feature to ensure the # files are still found. if(NOT MSVC) - if(CONFIG_OUTPUT_STRIP_PATHS AND NOT CONFIG_TRICORE_TOOLCHAIN_HIGHTEC) - add_compile_options(-fmacro-prefix-map=${NUTTX_DIR}=) - add_compile_options(-fmacro-prefix-map=${NUTTX_APPS_DIR}=) - add_compile_options(-fmacro-prefix-map=${NUTTX_BOARD_ABS_DIR}=) - add_compile_options(-fmacro-prefix-map=${NUTTX_CHIP_ABS_DIR}=) + if (NOT (CONFIG_ARCH_RH850 AND CONFIG_ARCH_TOOLCHAIN_GHS)) + if(CONFIG_OUTPUT_STRIP_PATHS AND NOT CONFIG_TRICORE_TOOLCHAIN_HIGHTEC) + add_compile_options(-fmacro-prefix-map=${NUTTX_DIR}=) + add_compile_options(-fmacro-prefix-map=${NUTTX_APPS_DIR}=) + add_compile_options(-fmacro-prefix-map=${NUTTX_BOARD_ABS_DIR}=) + add_compile_options(-fmacro-prefix-map=${NUTTX_CHIP_ABS_DIR}=) + endif() endif() endif() @@ -585,9 +586,7 @@ if(TARGET nuttx_post_build) endif() # Add apps/ to the build (if present) - if(NOT CONFIG_BUILD_KERNEL) - if(EXISTS ${NUTTX_APPS_DIR}/CMakeLists.txt) add_subdirectory(${NUTTX_APPS_DIR} apps) else() @@ -606,14 +605,21 @@ get_property(ldscript GLOBAL PROPERTY LD_SCRIPT) if(NOT CONFIG_ARCH_SIM) get_filename_component(LD_SCRIPT_NAME ${ldscript} NAME) set(LD_SCRIPT_TMP "${CMAKE_BINARY_DIR}/${LD_SCRIPT_NAME}.tmp") + message("LD_SCRIPT_TMP: ${LD_SCRIPT_TMP}") - nuttx_generate_preproces_target(SOURCE_FILE ${ldscript} TARGET_FILE - ${LD_SCRIPT_TMP}) - - add_custom_target(ldscript_tmp DEPENDS ${LD_SCRIPT_TMP}) - add_dependencies(nuttx ldscript_tmp) + # Only for CCRH850 + if(CONFIG_ARCH_RH850) + else() + nuttx_generate_preproces_target(SOURCE_FILE ${ldscript} TARGET_FILE + ${LD_SCRIPT_TMP}) + add_custom_target(ldscript_tmp DEPENDS ${LD_SCRIPT_TMP}) + # todo fix linker not found in apps + add_dependencies(nuttx ldscript_tmp) + # todo end + + set(ldscript ${LD_SCRIPT_TMP}) + endif() - set(ldscript ${LD_SCRIPT_TMP}) endif() # Perform link @@ -856,8 +862,6 @@ if(CONFIG_BUILD_PROTECTED) # TODO: could also merge elf binaries endif() - if(CONFIG_BUILD_KERNEL) # TODO: generate nuttx-export-xxx.tar.gz for userland development - -endif() +endif() \ No newline at end of file diff --git a/arch/CMakeLists.txt b/arch/CMakeLists.txt index 66ce262e71644a8c0d39c93e61fb6d886825060f..f7347867f14abf299d69e8ba3cb0b4b92c3ae52a 100644 --- a/arch/CMakeLists.txt +++ b/arch/CMakeLists.txt @@ -1,6 +1,6 @@ # ############################################################################## # arch/CMakeLists.txt -# +# # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for # additional information regarding copyright ownership. The ASF licenses this @@ -36,4 +36,5 @@ endif() # EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd endif # include corresponding arch subdirectory + add_subdirectory(${CONFIG_ARCH}) diff --git a/arch/Kconfig b/arch/Kconfig index f3ecf0b610b90f70a08e85d3abd61dbaa266c960..6a6b7cd3506928a87c201fe4e3e84320f59ea729 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -200,6 +200,12 @@ config ARCH_TRICORE ---help--- Infineon 32-bit AURIX TriCore architectures +config ARCH_RH850 + bool "Renesas RH850 Core" + select ARCH_HAVE_INTERRUPTSTACK + ---help--- + Renesas RH850 Core + endchoice @@ -222,6 +228,7 @@ config ARCH default "or1k" if ARCH_OR1K default "sparc" if ARCH_SPARC default "tricore" if ARCH_TRICORE + default "rh850" if ARCH_RH850 source "arch/arm/Kconfig" source "arch/arm64/Kconfig" @@ -240,6 +247,7 @@ source "arch/z80/Kconfig" source "arch/or1k/Kconfig" source "arch/sparc/Kconfig" source "arch/tricore/Kconfig" +source "arch/rh850/Kconfig" config ARCH_CHIP_CUSTOM bool "Custom Chip Support" diff --git a/arch/renesas/include/setjmp.h b/arch/renesas/include/setjmp.h index 5c288b78cdc258bce5314f6072e31e5290cdb5b9..e74e4b1db56a3f515b84ca37ced3f7e0cdfdcbaa 100644 --- a/arch/renesas/include/setjmp.h +++ b/arch/renesas/include/setjmp.h @@ -51,6 +51,6 @@ typedef struct setjmp_buf_s jmp_buf[1]; ****************************************************************************/ int setjmp(jmp_buf env); -void longjmp(jmp_buf env, int val) noreturn_function; +void longjmp(jmp_buf env, int val); #endif /* __ARCH_RENESAS_INCLUDE_SETJUMP_H */ diff --git a/arch/renesas/src/rx65n/rx65n_vector.S b/arch/renesas/src/rx65n/rx65n_vector.S index 983b3e31b96f6cded208d9b19ba5a2955e5e1547..e72117489317a69258237ed5c92b4cb3d023e42c 100644 --- a/arch/renesas/src/rx65n/rx65n_vector.S +++ b/arch/renesas/src/rx65n/rx65n_vector.S @@ -191,9 +191,9 @@ _up_vector: #endif MOV.L #_up_num_irq, R2 MOV.W [R2], R1 - MVFC ISP, R2 /* stack pointer as 2nd args of _renesas_doirq */ + MVFC ISP, R2 /* stack pointer as 2nd args of _renesas_doirq */ BSR.A _renesas_doirq /* remaining R1 register as 1st args of _renesas_doirq */ - NOP + NOP MVFC ISP, R2 CMP R2, R1 BEQ .lint_contextswitch diff --git a/arch/rh850/CMakeLists.txt b/arch/rh850/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..7b2ba19c09e5a1f2738dad79469e2fd3663fcee7 --- /dev/null +++ b/arch/rh850/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# arch/rh850/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +nuttx_add_subdirectory() diff --git a/arch/rh850/Kconfig b/arch/rh850/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..c104356349af4a5df2fa048a82105ccd43390622 --- /dev/null +++ b/arch/rh850/Kconfig @@ -0,0 +1,43 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RH850 + +choice + prompt "Renesas chip selection" + default RH850_TOOLCHAIN_GHS + +config RH850_TOOLCHAIN_GHS + bool "RH850s Compiler Green Hills Software toolchain" + select ARCH_TOOLCHAIN_GHS + +endchoice + +config ARCH_CHIP_U2B24E + bool "U2B24_E" + default y + select TIMER + select TIMER_ARCH + select ARCH_HAVE_SETJMP + ---help--- + Renesas U2B24-E + +config ARCH_RH850G4KH + bool + default n + +config ARCH_RH850G4MH + bool + default n + +config ARCH_FAMILY + string + default "g4x" if ARCH_RH850G4KH + default "g4x" if ARCH_RH850G4MH + +source "arch/rh850/src/common/Kconfig" +source "arch/rh850/src/g4x/Kconfig" + +endif # ARCH_RH850 \ No newline at end of file diff --git a/arch/rh850/include/.gitignore b/arch/rh850/include/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..af8911db0617259c4b392316ab81bfa47c14b3cb --- /dev/null +++ b/arch/rh850/include/.gitignore @@ -0,0 +1,2 @@ +/board +/chip diff --git a/arch/rh850/include/arch.h b/arch/rh850/include/arch.h new file mode 100644 index 0000000000000000000000000000000000000000..21ec3a394bc7a30231fc30e114c95cd7dd040544 --- /dev/null +++ b/arch/rh850/include/arch.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/renesas/include/arch.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/arch.h + */ + +#ifndef __ARCH_RH850_INCLUDE_ARCH_H +#define __ARCH_RH850_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include chip-specific definitions */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_RH850_INCLUDE_ARCH_H */ diff --git a/arch/rh850/include/inttypes.h b/arch/rh850/include/inttypes.h new file mode 100644 index 0000000000000000000000000000000000000000..baf9e7120e928b9fef082a3848b7f9d8f8c2ca30 --- /dev/null +++ b/arch/rh850/include/inttypes.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/renesas/include/inttypes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_INTTYPES_H +#define __ARCH_RH850_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RH850_INCLUDE_INTTYPES_H */ diff --git a/arch/rh850/include/irq.h b/arch/rh850/include/irq.h new file mode 100644 index 0000000000000000000000000000000000000000..a1786cd016ae7e9fa9ac57ccf194680f0b388ff6 --- /dev/null +++ b/arch/rh850/include/irq.h @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/renesas/include/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_RH850_INCLUDE_IRQ_H +#define __ARCH_RH850_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +#ifndef __ASSEMBLY__ +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +#include +#endif /* CONFIG_RT_FRAMEWORK */ +#endif + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This holds a references to the current interrupt level + * register storage structure. It is non-NULL only during + * interrupt processing. + */ + +EXTERN volatile uint32_t *g_current_regs; + +EXTERN const uintptr_t g_idle_topstack; + +extern void up_set_contexthdl(void *const ctxhdl); + +extern void *up_get_contexthdl(); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +void up_init_irq(int irq, int irq_prio); +int up_trigger_ipicall(unsigned int cpu); +void up_trigger_ipicalls(unsigned int cpu_mask); +void up_ipicall_attach(void *handler); +bool up_irq_is_enabled(int irq); +void up_clear_irq(int irq); +int up_timer_value(FAR clock_t *ticks); +uint32_t up_timer_freq(void); +#endif + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +static inline_function uint32_t *up_current_regs(void) +{ + return (uint32_t *)g_current_regs; +} + + +static inline_function void up_set_current_regs(uint32_t *regs) +{ + g_current_regs = regs; +} + + +static inline_function void up_irq_level_restore(irqlevel_t level) +{ +// up_set_irq_mask_level(level); +} + +static inline_function void up_kernel_int_restore(irqlevel_t level) +{ +#if defined(CONFIG_RT_FRAMEWORK_INT_LEVEL) && (CONFIG_RT_FRAMEWORK_INT_LEVEL == 1) + return up_irq_level_restore(level); +#else + return up_irq_restore(level); +#endif +} + + +static inline_function irqlevel_t up_irq_level_save(irqlevel_t level) +{ +// irqlevel_t pre_level = up_get_irq_mask_level(); + +// if (level < pre_level) { +// up_set_irq_mask_level(level); +// } +// return pre_level; + return 0; +} + +static inline_function irqlevel_t up_kernel_int_save(void) +{ +#if defined(CONFIG_RT_FRAMEWORK_INT_LEVEL) && (CONFIG_RT_FRAMEWORK_INT_LEVEL == 1) + return up_irq_level_save(CONFIG_RT_FRAMEWORK_MAX_TP_INT_LEVEL); +#else + return up_irq_save(); +#endif +} + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: + * Return true is we are currently executing in the interrupt + * handler context. + * + ****************************************************************************/ + +#define up_interrupt_context() (up_current_regs() != NULL) + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_RH850_INCLUDE_IRQ_H */ diff --git a/arch/rh850/include/limits.h b/arch/rh850/include/limits.h new file mode 100644 index 0000000000000000000000000000000000000000..0ed7b5b158b8e28c78266d0c5a31e3f74c29d7fc --- /dev/null +++ b/arch/rh850/include/limits.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/renesas/include/limits.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_LIMITS_H +#define __ARCH_RH850_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RH850_INCLUDE_LIMITS_H */ diff --git a/arch/rh850/include/setjmp.h b/arch/rh850/include/setjmp.h new file mode 100644 index 0000000000000000000000000000000000000000..3c968dfab150f7ec4f42dc9e31393008bd53acf9 --- /dev/null +++ b/arch/rh850/include/setjmp.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/renesas/include/setjmp.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_SETJUMP_H +#define __ARCH_RH850_INCLUDE_SETJUMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#if defined(CONFIG_ARCH_RH850) +struct setjmp_buf_s +{ + uint32_t regs[38]; +}; + +/* Traditional typedef for setjmp_buf */ + +typedef struct setjmp_buf_s jmp_buf[1]; + +#else +# error "setjmp() not compiled!" +#endif /* CONFIG_ARCH_RH850... */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int setjmp(jmp_buf env); +void longjmp(jmp_buf env, int val); + +#endif /* __ARCH_RH850_INCLUDE_SETJUMP_H */ diff --git a/arch/rh850/include/sh1Plimits.h b/arch/rh850/include/sh1Plimits.h new file mode 100644 index 0000000000000000000000000000000000000000..eb3b46e5a31fe62cca96de2754f3539b619bd5c0 --- /dev/null +++ b/arch/rh850/include/sh1Plimits.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/renesas/include/sh1Plimits.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_SH1_PLIMITS_H +#define __ARCH_RH850_INCLUDE_SH1_PLIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +# define CHAR_MIN 0 +# define CHAR_MAX UCHAR_MAX +#else +# define CHAR_MIN SCHAR_MIN +# define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +/* On SH-1, type 'int' is 32-bits */ + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* On SH-1, type 'long' is the same size as type 'int', 32-bits */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#if !defined(__WCHAR_TYPE__) +# define WCHAR_MIN INT_MIN +# define WCHAR_MAX INT_MAX +#elif defined(__WCHAR_UNSIGNED__) +# define WCHAR_MIN 0 +# define WCHAR_MAX __WCHAR_MAX__ +#else +# define WCHAR_MIN (-__WCHAR_MAX__ - 1) +# define WCHAR_MAX __WCHAR_MAX__ +#endif + +#endif /* __ARCH_RH850_INCLUDE_SH1_PLIMITS_H */ diff --git a/arch/rh850/include/sh1Ptypes.h b/arch/rh850/include/sh1Ptypes.h new file mode 100644 index 0000000000000000000000000000000000000000..1ea1e77aa23174ad8153211094dcea2ac04c571a --- /dev/null +++ b/arch/rh850/include/sh1Ptypes.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/renesas/include/sh1Ptypes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly\ + * through sys/types.h + */ + +#ifndef __ARCH_RH850_INCLUDE_SH1_PTYPES_H +#define __ARCH_RH850_INCLUDE_SH1_PTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* This is the size of the interrupt state save returned by + * up_irq_save() + */ + +typedef unsigned long irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RENESAS_INCLUDE_SH1_PTYPES_H */ diff --git a/arch/rh850/include/syscall.h b/arch/rh850/include/syscall.h new file mode 100644 index 0000000000000000000000000000000000000000..89593f82603ff2515a1aced80f03b5265cf9150c --- /dev/null +++ b/arch/rh850/include/syscall.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/renesas/include/syscall.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_RH850_INCLUDE_SYSCALL_H +#define __ARCH_RH850_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_RH850_INCLUDE_SYSCALL_H */ diff --git a/arch/rh850/include/types.h b/arch/rh850/include/types.h new file mode 100644 index 0000000000000000000000000000000000000000..446988c3a191b2b672ae0ab41f1721f79f3d0d47 --- /dev/null +++ b/arch/rh850/include/types.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/renesas/include/types.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through sys/types.h + */ + +#ifndef __ARCH_RH850_INCLUDE_TYPES_H +#define __ARCH_RH850_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +typedef unsigned int irqlevel_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RH850_INCLUDE_TYPES_H */ diff --git a/arch/rh850/include/u2bx/arch.h b/arch/rh850/include/u2bx/arch.h new file mode 100644 index 0000000000000000000000000000000000000000..5fd95cad2aeabe57d079b4cba337cc2d10fb3f45 --- /dev/null +++ b/arch/rh850/include/u2bx/arch.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/arch.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/arch.h + */ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_ARCH_H +#define __ARCH_RH850_INCLUDE_U2BX_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RH850_INCLUDE_U2BX_ARCH_H */ diff --git a/arch/rh850/include/u2bx/atomic.h b/arch/rh850/include/u2bx/atomic.h new file mode 100644 index 0000000000000000000000000000000000000000..99064db6414b0c212ef799183d8692c8e6e8b4eb --- /dev/null +++ b/arch/rh850/include/u2bx/atomic.h @@ -0,0 +1,26 @@ +#ifndef __ARCH_RH850_INCLUDE_U2BX_RTFW_ATOMIC_H +#define __ARCH_RH850_INCLUDE_U2BX_RTFW_ATOMIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "atomic.h" + +#pragma ghs nowarning 301 + +typedef volatile int32_t Atomic; + +#pragma ghs endnowarning 301 + +static inline Atomic Os_AtomicOr(Atomic *ptr, int32_t orVal) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_RH850_INCLUDE_U2BX_RTFW_ATOMIC_H */ diff --git a/arch/rh850/include/u2bx/inttypes.h b/arch/rh850/include/u2bx/inttypes.h new file mode 100644 index 0000000000000000000000000000000000000000..5787e87802e165474ec3c7cefdda06cbf772b77a --- /dev/null +++ b/arch/rh850/include/u2bx/inttypes.h @@ -0,0 +1,115 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/inttypes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_INTTYPES_H +#define __ARCH_RH850_INCLUDE_U2BX_INTTYPES_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" +#define PRId64 "lld" + +#define PRIdPTR "ld" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" +#define PRIi64 "lli" + +#define PRIiPTR "li" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" +#define PRIo64 "llo" + +#define PRIoPTR "lo" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" +#define PRIu64 "llu" + +#define PRIuPTR "lu" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" +#define PRIx64 "llx" + +#define PRIxPTR "lx" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" +#define PRIX64 "llX" + +#define PRIXPTR "lX" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "ld" +#define SCNd64 "lld" + +#define SCNdPTR "ld" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "li" +#define SCNi64 "lli" + +#define SCNiPTR "li" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "lo" +#define SCNo64 "llo" + +#define SCNoPTR "lo" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "lu" +#define SCNu64 "llu" + +#define SCNuPTR "lu" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "lx" +#define SCNx64 "llx" + +#define SCNxPTR "lx" + +#define INT8_C(x) x +#define INT16_C(x) x +#define INT32_C(x) x ## l +#define INT64_C(x) x ## ll + +#define UINT8_C(x) x +#define UINT16_C(x) x +#define UINT32_C(x) x ## ul +#define UINT64_C(x) x ## ull + +#endif /* __ARCH_RH850_INCLUDE_U2BX_INTTYPES_H */ diff --git a/arch/rh850/include/u2bx/iodefine.h b/arch/rh850/include/u2bx/iodefine.h new file mode 100644 index 0000000000000000000000000000000000000000..35b364d37565180e8d19ac9ab220b0040720158c --- /dev/null +++ b/arch/rh850/include/u2bx/iodefine.h @@ -0,0 +1,38101 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/iodefine.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_IODEFINE_H +#define __ARCH_RH850_INCLUDE_U2BX_IODEFINE_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_RIIC1_RXI1 IEN2 +#define IEN_RIIC1_TXI1 IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCI8_RXI8 IEN4 +#define IEN_SCI8_TXI8 IEN5 +#define IEN_SCI9_RXI9 IEN6 +#define IEN_SCI9_TXI9 IEN7 +#define IEN_SCI10_RXI10 IEN0 +#define IEN_SCI10_TXI10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_RSPI2_SPRI2 IEN4 +#define IEN_RSPI2_SPTI2 IEN5 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCI11_RXI11 IEN2 +#define IEN_SCI11_TXI11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_RIIC1_RXI1 50 +#define VECT_RIIC1_TXI1 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCI8_RXI8 100 +#define VECT_SCI8_TXI8 101 +#define VECT_SCI9_RXI9 102 +#define VECT_SCI9_TXI9 103 +#define VECT_SCI10_RXI10 104 +#define VECT_SCI10_TXI10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL2 107 +#define VECT_RSPI2_SPRI2 108 +#define VECT_RSPI2_SPTI2 109 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCI11_RXI11 114 +#define VECT_SCI11_TXI11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#ifndef __ASSEMBLER__ + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPUA SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ETHERC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_GLCDC SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_DRW2D SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_RAM2 SYSTEM.MSTPCRC.BIT.MSTPC2 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SDSI SYSTEM.MSTPCRD.BIT.MSTPD13 + +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI7_TEI7 IS14 +#define IS_SCI7_ERI7 IS15 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_SCI8_TEI8 IS24 +#define IS_SCI8_ERI8 IS25 +#define IS_SCI9_TEI9 IS26 +#define IS_SCI9_ERI9 IS27 +#define IS_RIIC1_TEI1 IS28 +#define IS_RIIC1_EEI1 IS29 +#define IS_SDSI_SDIOI IS0 +#define IS_SCI10_TEI10 IS8 +#define IS_SCI10_ERI10 IS9 +#define IS_SCI11_TEI11 IS12 +#define IS_SCI11_ERI11 IS13 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_RSPI2_SPII2 IS20 +#define IS_RSPI2_SPEI2 IS21 +#define IS_EDMAC0_EINT0 IS4 +#define IS_GLCDC_VPOS IS8 +#define IS_GLCDC_GR1UF IS9 +#define IS_GLCDC_GR2UF IS10 +#define IS_DRW2D_DRWIRQ IS11 + +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI7_TEI7 EN14 +#define EN_SCI7_ERI7 EN15 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_SCI8_TEI8 EN24 +#define EN_SCI8_ERI8 EN25 +#define EN_SCI9_TEI9 EN26 +#define EN_SCI9_ERI9 EN27 +#define EN_RIIC1_TEI1 EN28 +#define EN_RIIC1_EEI1 EN29 +#define EN_SDSI_SDIOI EN0 +#define EN_SCI10_TEI10 EN8 +#define EN_SCI10_ERI10 EN9 +#define EN_SCI11_TEI11 EN12 +#define EN_SCI11_ERI11 EN13 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_RSPI2_SPII2 EN20 +#define EN_RSPI2_SPEI2 EN21 +#define EN_EDMAC0_EINT0 EN4 +#define EN_GLCDC_VPOS EN8 +#define EN_GLCDC_GR1UF EN9 +#define EN_GLCDC_GR2UF EN10 +#define EN_DRW2D_DRWIRQ EN11 + +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 + +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI7_TEI7 GENBL0 +#define GEN_SCI7_ERI7 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_SCI8_TEI8 GENBL1 +#define GEN_SCI8_ERI8 GENBL1 +#define GEN_SCI9_TEI9 GENBL1 +#define GEN_SCI9_ERI9 GENBL1 +#define GEN_RIIC1_TEI1 GENBL1 +#define GEN_RIIC1_EEI1 GENBL1 +#define GEN_SDSI_SDIOI GENBL2 +#define GEN_SCI10_TEI10 GENAL0 +#define GEN_SCI10_ERI10 GENAL0 +#define GEN_SCI11_TEI11 GENAL0 +#define GEN_SCI11_ERI11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_RSPI2_SPII2 GENAL0 +#define GEN_RSPI2_SPEI2 GENAL0 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_GLCDC_VPOS GENAL1 +#define GEN_GLCDC_GR1UF GENAL1 +#define GEN_GLCDC_GR2UF GENAL1 +#define GEN_DRW2D_DRWIRQ GENAL1 + +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI7_TEI7 GRPBL0 +#define GRP_SCI7_ERI7 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_SCI8_TEI8 GRPBL1 +#define GRP_SCI8_ERI8 GRPBL1 +#define GRP_SCI9_TEI9 GRPBL1 +#define GRP_SCI9_ERI9 GRPBL1 +#define GRP_RIIC1_TEI1 GRPBL1 +#define GRP_RIIC1_EEI1 GRPBL1 +#define GRP_SDSI_SDIOI GRPBL2 +#define GRP_SCI10_TEI10 GRPAL0 +#define GRP_SCI10_ERI10 GRPAL0 +#define GRP_SCI11_TEI11 GRPAL0 +#define GRP_SCI11_ERI11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_RSPI2_SPII2 GRPAL0 +#define GRP_RSPI2_SPEI2 GRPAL0 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_GLCDC_VPOS GRPAL1 +#define GRP_GLCDC_GR1UF GRPAL1 +#define GRP_GLCDC_GR2UF GRPAL1 +#define GRP_DRW2D_DRWIRQ GRPAL1 + +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8b000) +#define CAN0 (*(volatile struct st_can *)0x90200) +#define CAN1 (*(volatile struct st_can *)0x91200) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw *)0x94200) +#define CMTW1 (*(volatile struct st_cmtw *)0x94280) +#define CRC (*(volatile struct st_crc *)0x88280) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820c0) +#define DMAC4 (*(volatile struct st_dmac1 *)0x82100) +#define DMAC5 (*(volatile struct st_dmac1 *)0x82140) +#define DMAC6 (*(volatile struct st_dmac1 *)0x82180) +#define DMAC7 (*(volatile struct st_dmac1 *)0x821c0) +#define DOC (*(volatile struct st_doc *)0x8b080) +#define DRW2D (*(volatile struct st_drw2d *)0xe3000) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define EDMAC0 (*(volatile struct st_edmac *)0xc0000) +#define ELC (*(volatile struct st_elc *)0x8b100) +#define ETHERC0 (*(volatile struct st_etherc *)0xc0100) +#define EXDMAC (*(volatile struct st_exdmac *)0x82a00) +#define EXDMAC0 (*(volatile struct st_exdmac0 *)0x82800) +#define EXDMAC1 (*(volatile struct st_exdmac1 *)0x82840) +#define FLASH (*(volatile struct st_flash *)0x81000) +#define GLCDC (*(volatile struct st_glcdc *)0xe0000) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define MMCIF (*(volatile struct st_mmcif *)0x88500) +#define MPC (*(volatile struct st_mpc *)0x8c100) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xc120a) +#define MTU0 (*(volatile struct st_mtu0 *)0xc1290) +#define MTU1 (*(volatile struct st_mtu1 *)0xc1290) +#define MTU2 (*(volatile struct st_mtu2 *)0xc1292) +#define MTU3 (*(volatile struct st_mtu3 *)0xc1200) +#define MTU4 (*(volatile struct st_mtu4 *)0xc1200) +#define MTU5 (*(volatile struct st_mtu5 *)0xc1a94) +#define MTU6 (*(volatile struct st_mtu6 *)0xc1a00) +#define MTU7 (*(volatile struct st_mtu7 *)0xc1a00) +#define MTU8 (*(volatile struct st_mtu8 *)0xc1298) +#define PDC (*(volatile struct st_pdc *)0xa0500) +#define POE3 (*(volatile struct st_poe *)0x8c4c0) +#define PORT0 (*(volatile struct st_port0 *)0x8c000) +#define PORT1 (*(volatile struct st_port1 *)0x8c001) +#define PORT2 (*(volatile struct st_port2 *)0x8c002) +#define PORT3 (*(volatile struct st_port3 *)0x8c003) +#define PORT4 (*(volatile struct st_port4 *)0x8c004) +#define PORT5 (*(volatile struct st_port5 *)0x8c005) +#define PORT6 (*(volatile struct st_port6 *)0x8c006) +#define PORT7 (*(volatile struct st_port7 *)0x8c007) +#define PORT8 (*(volatile struct st_port8 *)0x8c008) +#define PORT9 (*(volatile struct st_port9 *)0x8c009) +#define PORTA (*(volatile struct st_porta *)0x8c00a) +#define PORTB (*(volatile struct st_portb *)0x8c00b) +#define PORTC (*(volatile struct st_portc *)0x8c00c) +#define PORTD (*(volatile struct st_portd *)0x8c00d) +#define PORTE (*(volatile struct st_porte *)0x8c00e) +#define PORTF (*(volatile struct st_portf *)0x8c00f) +#define PORTG (*(volatile struct st_portg *)0x8c010) +#define PORTJ (*(volatile struct st_portj *)0x8c012) +#define PPG0 (*(volatile struct st_ppg0 *)0x881e6) +#define PPG1 (*(volatile struct st_ppg1 *)0x881f0) +#define QSPI (*(volatile struct st_qspi *)0x89e00) +#define RAM (*(volatile struct st_ram *)0x81200) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RIIC1 (*(volatile struct st_riic *)0x88320) +#define RIIC2 (*(volatile struct st_riic *)0x88340) +#define RSPI0 (*(volatile struct st_rspi *)0xd0100) +#define RSPI1 (*(volatile struct st_rspi *)0xd0140) +#define RSPI2 (*(volatile struct st_rspi *)0xd0300) +#define RTC (*(volatile struct st_rtc *)0x8c400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define S12AD1 (*(volatile struct st_s12ad1 *)0x89100) +#define SCI0 (*(volatile struct st_sci0 *)0x8a000) +#define SCI1 (*(volatile struct st_sci0 *)0x8a020) +#define SCI2 (*(volatile struct st_sci0 *)0x8a040) +#define SCI3 (*(volatile struct st_sci0 *)0x8a060) +#define SCI4 (*(volatile struct st_sci0 *)0x8a080) +#define SCI5 (*(volatile struct st_sci0 *)0x8a0a0) +#define SCI6 (*(volatile struct st_sci0 *)0x8a0c0) +#define SCI7 (*(volatile struct st_sci0 *)0x8a0e0) +#define SCI8 (*(volatile struct st_sci0 *)0x8a100) +#define SCI9 (*(volatile struct st_sci0 *)0x8a120) +#define SCI10 (*(volatile struct st_sci10 *)0xd0040) +#define SCI11 (*(volatile struct st_sci10 *)0xd0060) +#define SCI12 (*(volatile struct st_sci12 *)0x8b300) +#define SDHI (*(volatile struct st_sdhi *)0x8ac00) +#define SDSI (*(volatile struct st_sdsi *)0x95000) +#define SMCI0 (*(volatile struct st_smci0 *)0x8a000) +#define SMCI1 (*(volatile struct st_smci0 *)0x8a020) +#define SMCI2 (*(volatile struct st_smci0 *)0x8a040) +#define SMCI3 (*(volatile struct st_smci0 *)0x8a060) +#define SMCI4 (*(volatile struct st_smci0 *)0x8a080) +#define SMCI5 (*(volatile struct st_smci0 *)0x8a0a0) +#define SMCI6 (*(volatile struct st_smci0 *)0x8a0c0) +#define SMCI7 (*(volatile struct st_smci0 *)0x8a0e0) +#define SMCI8 (*(volatile struct st_smci0 *)0x8a100) +#define SMCI9 (*(volatile struct st_smci0 *)0x8a120) +#define SMCI10 (*(volatile struct st_smci10 *)0xd0040) +#define SMCI11 (*(volatile struct st_smci10 *)0xd0060) +#define SMCI12 (*(volatile struct st_smci0 *)0x8b300) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x8c500) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TPU0 (*(volatile struct st_tpu0 *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 *)0x8810a) +#define TPU3 (*(volatile struct st_tpu3 *)0x8810a) +#define TPU4 (*(volatile struct st_tpu4 *)0x8810c) +#define TPU5 (*(volatile struct st_tpu5 *)0x8810c) +#define TPUA (*(volatile struct st_tpua *)0x88100) +#define USB (*(volatile struct st_usb *)0xa0400) +#define USB0 (*(volatile struct st_usb0 *)0xa0000) +#define WDT (*(volatile struct st_wdt *)0x88020) +#define FLASHCONST (*(volatile struct st_flashconst *)0xfe7f7d90) +#define TEMPSCONST (*(volatile struct st_tempsconst *)0xfe7f7d7c) + +#undef B0 /* Avoid the conflicted macro in termios.h */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef enum enum_ir +{ + IR_BSC_BUSERR = 16, + IR_RAM_RAMERR = 18, + IR_FCU_FIFERR = 21, + IR_FCU_FRDYI = 23, + IR_ICU_SWINT2 = 26, + IR_ICU_SWINT, + IR_CMT0_CMI0, + IR_CMT1_CMI1, + IR_CMTW0_CMWI0, + IR_CMTW1_CMWI1, + IR_USB0_D0FIFO0 = 34, + IR_USB0_D1FIFO0, + IR_RSPI0_SPRI0 = 38, + IR_RSPI0_SPTI0, + IR_RSPI1_SPRI1, + IR_RSPI1_SPTI1, + IR_QSPI_SPRI, + IR_QSPI_SPTI, + IR_SDHI_SBFAI, + IR_MMCIF_MBFAI, + IR_RIIC1_RXI1 = 50, + IR_RIIC1_TXI1, + IR_RIIC0_RXI0, + IR_RIIC0_TXI0, + IR_RIIC2_RXI2, + IR_RIIC2_TXI2, + IR_SCI0_RXI0 = 58, + IR_SCI0_TXI0, + IR_SCI1_RXI1, + IR_SCI1_TXI1, + IR_SCI2_RXI2, + IR_SCI2_TXI2, + IR_ICU_IRQ0, + IR_ICU_IRQ1, + IR_ICU_IRQ2, + IR_ICU_IRQ3, + IR_ICU_IRQ4, + IR_ICU_IRQ5, + IR_ICU_IRQ6, + IR_ICU_IRQ7, + IR_ICU_IRQ8, + IR_ICU_IRQ9, + IR_ICU_IRQ10, + IR_ICU_IRQ11, + IR_ICU_IRQ12, + IR_ICU_IRQ13, + IR_ICU_IRQ14, + IR_ICU_IRQ15, + IR_SCI3_RXI3, + IR_SCI3_TXI3, + IR_SCI4_RXI4, + IR_SCI4_TXI4, + IR_SCI5_RXI5, + IR_SCI5_TXI5, + IR_SCI6_RXI6, + IR_SCI6_TXI6, + IR_LVD1_LVD1, + IR_LVD2_LVD2, + IR_USB0_USBR0, + IR_RTC_ALM = 92, + IR_RTC_PRD, + IR_IWDT_IWUNI = 95, + IR_WDT_WUNI, + IR_PDC_PCDFI, + IR_SCI7_RXI7, + IR_SCI7_TXI7, + IR_SCI8_RXI8, + IR_SCI8_TXI8, + IR_SCI9_RXI9, + IR_SCI9_TXI9, + IR_SCI10_RXI10, + IR_SCI10_TXI10, + IR_ICU_GROUPBE0, + IR_ICU_GROUPBL2, + IR_RSPI2_SPRI2, + IR_RSPI2_SPTI2, + IR_ICU_GROUPBL0, + IR_ICU_GROUPBL1, + IR_ICU_GROUPAL0, + IR_ICU_GROUPAL1, + IR_SCI11_RXI11, + IR_SCI11_TXI11, + IR_SCI12_RXI12, + IR_SCI12_TXI12, + IR_DMAC_DMAC0I = 120, + IR_DMAC_DMAC1I, + IR_DMAC_DMAC2I, + IR_DMAC_DMAC3I, + IR_DMAC_DMAC74I, + IR_OST_OSTDI, + IR_EXDMAC_EXDMAC0I, + IR_EXDMAC_EXDMAC1I, + IR_PERIB_INTB128, + IR_PERIB_INTB129, + IR_PERIB_INTB130, + IR_PERIB_INTB131, + IR_PERIB_INTB132, + IR_PERIB_INTB133, + IR_PERIB_INTB134, + IR_PERIB_INTB135, + IR_PERIB_INTB136, + IR_PERIB_INTB137, + IR_PERIB_INTB138, + IR_PERIB_INTB139, + IR_PERIB_INTB140, + IR_PERIB_INTB141, + IR_PERIB_INTB142, + IR_PERIB_INTB143, + IR_PERIB_INTB144, + IR_PERIB_INTB145, + IR_PERIB_INTB146, + IR_PERIB_INTB147, + IR_PERIB_INTB148, + IR_PERIB_INTB149, + IR_PERIB_INTB150, + IR_PERIB_INTB151, + IR_PERIB_INTB152, + IR_PERIB_INTB153, + IR_PERIB_INTB154, + IR_PERIB_INTB155, + IR_PERIB_INTB156, + IR_PERIB_INTB157, + IR_PERIB_INTB158, + IR_PERIB_INTB159, + IR_PERIB_INTB160, + IR_PERIB_INTB161, + IR_PERIB_INTB162, + IR_PERIB_INTB163, + IR_PERIB_INTB164, + IR_PERIB_INTB165, + IR_PERIB_INTB166, + IR_PERIB_INTB167, + IR_PERIB_INTB168, + IR_PERIB_INTB169, + IR_PERIB_INTB170, + IR_PERIB_INTB171, + IR_PERIB_INTB172, + IR_PERIB_INTB173, + IR_PERIB_INTB174, + IR_PERIB_INTB175, + IR_PERIB_INTB176, + IR_PERIB_INTB177, + IR_PERIB_INTB178, + IR_PERIB_INTB179, + IR_PERIB_INTB180, + IR_PERIB_INTB181, + IR_PERIB_INTB182, + IR_PERIB_INTB183, + IR_PERIB_INTB184, + IR_PERIB_INTB185, + IR_PERIB_INTB186, + IR_PERIB_INTB187, + IR_PERIB_INTB188, + IR_PERIB_INTB189, + IR_PERIB_INTB190, + IR_PERIB_INTB191, + IR_PERIB_INTB192, + IR_PERIB_INTB193, + IR_PERIB_INTB194, + IR_PERIB_INTB195, + IR_PERIB_INTB196, + IR_PERIB_INTB197, + IR_PERIB_INTB198, + IR_PERIB_INTB199, + IR_PERIB_INTB200, + IR_PERIB_INTB201, + IR_PERIB_INTB202, + IR_PERIB_INTB203, + IR_PERIB_INTB204, + IR_PERIB_INTB205, + IR_PERIB_INTB206, + IR_PERIB_INTB207, + IR_PERIA_INTA208, + IR_PERIA_INTA209, + IR_PERIA_INTA210, + IR_PERIA_INTA211, + IR_PERIA_INTA212, + IR_PERIA_INTA213, + IR_PERIA_INTA214, + IR_PERIA_INTA215, + IR_PERIA_INTA216, + IR_PERIA_INTA217, + IR_PERIA_INTA218, + IR_PERIA_INTA219, + IR_PERIA_INTA220, + IR_PERIA_INTA221, + IR_PERIA_INTA222, + IR_PERIA_INTA223, + IR_PERIA_INTA224, + IR_PERIA_INTA225, + IR_PERIA_INTA226, + IR_PERIA_INTA227, + IR_PERIA_INTA228, + IR_PERIA_INTA229, + IR_PERIA_INTA230, + IR_PERIA_INTA231, + IR_PERIA_INTA232, + IR_PERIA_INTA233, + IR_PERIA_INTA234, + IR_PERIA_INTA235, + IR_PERIA_INTA236, + IR_PERIA_INTA237, + IR_PERIA_INTA238, + IR_PERIA_INTA239, + IR_PERIA_INTA240, + IR_PERIA_INTA241, + IR_PERIA_INTA242, + IR_PERIA_INTA243, + IR_PERIA_INTA244, + IR_PERIA_INTA245, + IR_PERIA_INTA246, + IR_PERIA_INTA247, + IR_PERIA_INTA248, + IR_PERIA_INTA249, + IR_PERIA_INTA250, + IR_PERIA_INTA251, + IR_PERIA_INTA252, + IR_PERIA_INTA253, + IR_PERIA_INTA254, + IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce +{ + DTCE_ICU_SWINT2 = 26, + DTCE_ICU_SWINT, + DTCE_CMT0_CMI0, + DTCE_CMT1_CMI1, + DTCE_CMTW0_CMWI0, + DTCE_CMTW1_CMWI1, + DTCE_USB0_D0FIFO0 = 34, + DTCE_USB0_D1FIFO0, + DTCE_RSPI0_SPRI0 = 38, + DTCE_RSPI0_SPTI0, + DTCE_RSPI1_SPRI1, + DTCE_RSPI1_SPTI1, + DTCE_QSPI_SPRI, + DTCE_QSPI_SPTI, + DTCE_SDHI_SBFAI, + DTCE_MMCIF_MBFAI, + DTCE_RIIC1_RXI1 = 50, + DTCE_RIIC1_TXI1, + DTCE_RIIC0_RXI0, + DTCE_RIIC0_TXI0, + DTCE_RIIC2_RXI2, + DTCE_RIIC2_TXI2, + DTCE_SCI0_RXI0 = 58, + DTCE_SCI0_TXI0, + DTCE_SCI1_RXI1, + DTCE_SCI1_TXI1, + DTCE_SCI2_RXI2, + DTCE_SCI2_TXI2, + DTCE_ICU_IRQ0, + DTCE_ICU_IRQ1, + DTCE_ICU_IRQ2, + DTCE_ICU_IRQ3, + DTCE_ICU_IRQ4, + DTCE_ICU_IRQ5, + DTCE_ICU_IRQ6, + DTCE_ICU_IRQ7, + DTCE_ICU_IRQ8, + DTCE_ICU_IRQ9, + DTCE_ICU_IRQ10, + DTCE_ICU_IRQ11, + DTCE_ICU_IRQ12, + DTCE_ICU_IRQ13, + DTCE_ICU_IRQ14, + DTCE_ICU_IRQ15, + DTCE_SCI3_RXI3, + DTCE_SCI3_TXI3, + DTCE_SCI4_RXI4, + DTCE_SCI4_TXI4, + DTCE_SCI5_RXI5, + DTCE_SCI5_TXI5, + DTCE_SCI6_RXI6, + DTCE_SCI6_TXI6, + DTCE_PDC_PCDFI = 97, + DTCE_SCI7_RXI7, + DTCE_SCI7_TXI7, + DTCE_SCI8_RXI8, + DTCE_SCI8_TXI8, + DTCE_SCI9_RXI9, + DTCE_SCI9_TXI9, + DTCE_SCI10_RXI10, + DTCE_SCI10_TXI10, + DTCE_RSPI2_SPRI2 = 108, + DTCE_RSPI2_SPTI2, + DTCE_SCI11_RXI11 = 114, + DTCE_SCI11_TXI11, + DTCE_SCI12_RXI12, + DTCE_SCI12_TXI12, + DTCE_DMAC_DMAC0I = 120, + DTCE_DMAC_DMAC1I, + DTCE_DMAC_DMAC2I, + DTCE_DMAC_DMAC3I, + DTCE_EXDMAC_EXDMAC0I = 126, + DTCE_EXDMAC_EXDMAC1I, + DTCE_PERIB_INTB128, + DTCE_PERIB_INTB129, + DTCE_PERIB_INTB130, + DTCE_PERIB_INTB131, + DTCE_PERIB_INTB132, + DTCE_PERIB_INTB133, + DTCE_PERIB_INTB134, + DTCE_PERIB_INTB135, + DTCE_PERIB_INTB136, + DTCE_PERIB_INTB137, + DTCE_PERIB_INTB138, + DTCE_PERIB_INTB139, + DTCE_PERIB_INTB140, + DTCE_PERIB_INTB141, + DTCE_PERIB_INTB142, + DTCE_PERIB_INTB143, + DTCE_PERIB_INTB144, + DTCE_PERIB_INTB145, + DTCE_PERIB_INTB146, + DTCE_PERIB_INTB147, + DTCE_PERIB_INTB148, + DTCE_PERIB_INTB149, + DTCE_PERIB_INTB150, + DTCE_PERIB_INTB151, + DTCE_PERIB_INTB152, + DTCE_PERIB_INTB153, + DTCE_PERIB_INTB154, + DTCE_PERIB_INTB155, + DTCE_PERIB_INTB156, + DTCE_PERIB_INTB157, + DTCE_PERIB_INTB158, + DTCE_PERIB_INTB159, + DTCE_PERIB_INTB160, + DTCE_PERIB_INTB161, + DTCE_PERIB_INTB162, + DTCE_PERIB_INTB163, + DTCE_PERIB_INTB164, + DTCE_PERIB_INTB165, + DTCE_PERIB_INTB166, + DTCE_PERIB_INTB167, + DTCE_PERIB_INTB168, + DTCE_PERIB_INTB169, + DTCE_PERIB_INTB170, + DTCE_PERIB_INTB171, + DTCE_PERIB_INTB172, + DTCE_PERIB_INTB173, + DTCE_PERIB_INTB174, + DTCE_PERIB_INTB175, + DTCE_PERIB_INTB176, + DTCE_PERIB_INTB177, + DTCE_PERIB_INTB178, + DTCE_PERIB_INTB179, + DTCE_PERIB_INTB180, + DTCE_PERIB_INTB181, + DTCE_PERIB_INTB182, + DTCE_PERIB_INTB183, + DTCE_PERIB_INTB184, + DTCE_PERIB_INTB185, + DTCE_PERIB_INTB186, + DTCE_PERIB_INTB187, + DTCE_PERIB_INTB188, + DTCE_PERIB_INTB189, + DTCE_PERIB_INTB190, + DTCE_PERIB_INTB191, + DTCE_PERIB_INTB192, + DTCE_PERIB_INTB193, + DTCE_PERIB_INTB194, + DTCE_PERIB_INTB195, + DTCE_PERIB_INTB196, + DTCE_PERIB_INTB197, + DTCE_PERIB_INTB198, + DTCE_PERIB_INTB199, + DTCE_PERIB_INTB200, + DTCE_PERIB_INTB201, + DTCE_PERIB_INTB202, + DTCE_PERIB_INTB203, + DTCE_PERIB_INTB204, + DTCE_PERIB_INTB205, + DTCE_PERIB_INTB206, + DTCE_PERIB_INTB207, + DTCE_PERIA_INTA208, + DTCE_PERIA_INTA209, + DTCE_PERIA_INTA210, + DTCE_PERIA_INTA211, + DTCE_PERIA_INTA212, + DTCE_PERIA_INTA213, + DTCE_PERIA_INTA214, + DTCE_PERIA_INTA215, + DTCE_PERIA_INTA216, + DTCE_PERIA_INTA217, + DTCE_PERIA_INTA218, + DTCE_PERIA_INTA219, + DTCE_PERIA_INTA220, + DTCE_PERIA_INTA221, + DTCE_PERIA_INTA222, + DTCE_PERIA_INTA223, + DTCE_PERIA_INTA224, + DTCE_PERIA_INTA225, + DTCE_PERIA_INTA226, + DTCE_PERIA_INTA227, + DTCE_PERIA_INTA228, + DTCE_PERIA_INTA229, + DTCE_PERIA_INTA230, + DTCE_PERIA_INTA231, + DTCE_PERIA_INTA232, + DTCE_PERIA_INTA233, + DTCE_PERIA_INTA234, + DTCE_PERIA_INTA235, + DTCE_PERIA_INTA236, + DTCE_PERIA_INTA237, + DTCE_PERIA_INTA238, + DTCE_PERIA_INTA239, + DTCE_PERIA_INTA240, + DTCE_PERIA_INTA241, + DTCE_PERIA_INTA242, + DTCE_PERIA_INTA243, + DTCE_PERIA_INTA244, + DTCE_PERIA_INTA245, + DTCE_PERIA_INTA246, + DTCE_PERIA_INTA247, + DTCE_PERIA_INTA248, + DTCE_PERIA_INTA249, + DTCE_PERIA_INTA250, + DTCE_PERIA_INTA251, + DTCE_PERIA_INTA252, + DTCE_PERIA_INTA253, + DTCE_PERIA_INTA254, + DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier +{ + IER_BSC_BUSERR = 0x02, + IER_RAM_RAMERR = 0x02, + IER_FCU_FIFERR = 0x02, + IER_FCU_FRDYI = 0x02, + IER_ICU_SWINT2 = 0x03, + IER_ICU_SWINT = 0x03, + IER_CMT0_CMI0 = 0x03, + IER_CMT1_CMI1 = 0x03, + IER_CMTW0_CMWI0 = 0x03, + IER_CMTW1_CMWI1 = 0x03, + IER_USB0_D0FIFO0 = 0x04, + IER_USB0_D1FIFO0 = 0x04, + IER_RSPI0_SPRI0 = 0x04, + IER_RSPI0_SPTI0 = 0x04, + IER_RSPI1_SPRI1 = 0x05, + IER_RSPI1_SPTI1 = 0x05, + IER_QSPI_SPRI = 0x05, + IER_QSPI_SPTI = 0x05, + IER_SDHI_SBFAI = 0x05, + IER_MMCIF_MBFAI = 0x05, + IER_RIIC1_RXI1 = 0x06, + IER_RIIC1_TXI1 = 0x06, + IER_RIIC0_RXI0 = 0x06, + IER_RIIC0_TXI0 = 0x06, + IER_RIIC2_RXI2 = 0x06, + IER_RIIC2_TXI2 = 0x06, + IER_SCI0_RXI0 = 0x07, + IER_SCI0_TXI0 = 0x07, + IER_SCI1_RXI1 = 0x07, + IER_SCI1_TXI1 = 0x07, + IER_SCI2_RXI2 = 0x07, + IER_SCI2_TXI2 = 0x07, + IER_ICU_IRQ0 = 0x08, + IER_ICU_IRQ1 = 0x08, + IER_ICU_IRQ2 = 0x08, + IER_ICU_IRQ3 = 0x08, + IER_ICU_IRQ4 = 0x08, + IER_ICU_IRQ5 = 0x08, + IER_ICU_IRQ6 = 0x08, + IER_ICU_IRQ7 = 0x08, + IER_ICU_IRQ8 = 0x09, + IER_ICU_IRQ9 = 0x09, + IER_ICU_IRQ10 = 0x09, + IER_ICU_IRQ11 = 0x09, + IER_ICU_IRQ12 = 0x09, + IER_ICU_IRQ13 = 0x09, + IER_ICU_IRQ14 = 0x09, + IER_ICU_IRQ15 = 0x09, + IER_SCI3_RXI3 = 0x0a, + IER_SCI3_TXI3 = 0x0a, + IER_SCI4_RXI4 = 0x0a, + IER_SCI4_TXI4 = 0x0a, + IER_SCI5_RXI5 = 0x0a, + IER_SCI5_TXI5 = 0x0a, + IER_SCI6_RXI6 = 0x0a, + IER_SCI6_TXI6 = 0x0a, + IER_LVD1_LVD1 = 0x0b, + IER_LVD2_LVD2 = 0x0b, + IER_USB0_USBR0 = 0x0b, + IER_RTC_ALM = 0x0b, + IER_RTC_PRD = 0x0b, + IER_IWDT_IWUNI = 0x0b, + IER_WDT_WUNI = 0x0c, + IER_PDC_PCDFI = 0x0c, + IER_SCI7_RXI7 = 0x0c, + IER_SCI7_TXI7 = 0x0c, + IER_SCI8_RXI8 = 0x0c, + IER_SCI8_TXI8 = 0x0c, + IER_SCI9_RXI9 = 0x0c, + IER_SCI9_TXI9 = 0x0c, + IER_SCI10_RXI10 = 0x0d, + IER_SCI10_TXI10 = 0x0d, + IER_ICU_GROUPBE0 = 0x0d, + IER_ICU_GROUPBL2 = 0x0d, + IER_RSPI2_SPRI2 = 0x0d, + IER_RSPI2_SPTI2 = 0x0d, + IER_ICU_GROUPBL0 = 0x0d, + IER_ICU_GROUPBL1 = 0x0d, + IER_ICU_GROUPAL0 = 0x0e, + IER_ICU_GROUPAL1 = 0x0e, + IER_SCI11_RXI11 = 0x0e, + IER_SCI11_TXI11 = 0x0e, + IER_SCI12_RXI12 = 0x0e, + IER_SCI12_TXI12 = 0x0e, + IER_DMAC_DMAC0I = 0x0f, + IER_DMAC_DMAC1I = 0x0f, + IER_DMAC_DMAC2I = 0x0f, + IER_DMAC_DMAC3I = 0x0f, + IER_DMAC_DMAC74I = 0x0f, + IER_OST_OSTDI = 0x0f, + IER_EXDMAC_EXDMAC0I = 0x0f, + IER_EXDMAC_EXDMAC1I = 0x0f, + IER_PERIB_INTB128 = 0x10, + IER_PERIB_INTB129 = 0x10, + IER_PERIB_INTB130 = 0x10, + IER_PERIB_INTB131 = 0x10, + IER_PERIB_INTB132 = 0x10, + IER_PERIB_INTB133 = 0x10, + IER_PERIB_INTB134 = 0x10, + IER_PERIB_INTB135 = 0x10, + IER_PERIB_INTB136 = 0x11, + IER_PERIB_INTB137 = 0x11, + IER_PERIB_INTB138 = 0x11, + IER_PERIB_INTB139 = 0x11, + IER_PERIB_INTB140 = 0x11, + IER_PERIB_INTB141 = 0x11, + IER_PERIB_INTB142 = 0x11, + IER_PERIB_INTB143 = 0x11, + IER_PERIB_INTB144 = 0x12, + IER_PERIB_INTB145 = 0x12, + IER_PERIB_INTB146 = 0x12, + IER_PERIB_INTB147 = 0x12, + IER_PERIB_INTB148 = 0x12, + IER_PERIB_INTB149 = 0x12, + IER_PERIB_INTB150 = 0x12, + IER_PERIB_INTB151 = 0x12, + IER_PERIB_INTB152 = 0x13, + IER_PERIB_INTB153 = 0x13, + IER_PERIB_INTB154 = 0x13, + IER_PERIB_INTB155 = 0x13, + IER_PERIB_INTB156 = 0x13, + IER_PERIB_INTB157 = 0x13, + IER_PERIB_INTB158 = 0x13, + IER_PERIB_INTB159 = 0x13, + IER_PERIB_INTB160 = 0x14, + IER_PERIB_INTB161 = 0x14, + IER_PERIB_INTB162 = 0x14, + IER_PERIB_INTB163 = 0x14, + IER_PERIB_INTB164 = 0x14, + IER_PERIB_INTB165 = 0x14, + IER_PERIB_INTB166 = 0x14, + IER_PERIB_INTB167 = 0x14, + IER_PERIB_INTB168 = 0x15, + IER_PERIB_INTB169 = 0x15, + IER_PERIB_INTB170 = 0x15, + IER_PERIB_INTB171 = 0x15, + IER_PERIB_INTB172 = 0x15, + IER_PERIB_INTB173 = 0x15, + IER_PERIB_INTB174 = 0x15, + IER_PERIB_INTB175 = 0x15, + IER_PERIB_INTB176 = 0x16, + IER_PERIB_INTB177 = 0x16, + IER_PERIB_INTB178 = 0x16, + IER_PERIB_INTB179 = 0x16, + IER_PERIB_INTB180 = 0x16, + IER_PERIB_INTB181 = 0x16, + IER_PERIB_INTB182 = 0x16, + IER_PERIB_INTB183 = 0x16, + IER_PERIB_INTB184 = 0x17, + IER_PERIB_INTB185 = 0x17, + IER_PERIB_INTB186 = 0x17, + IER_PERIB_INTB187 = 0x17, + IER_PERIB_INTB188 = 0x17, + IER_PERIB_INTB189 = 0x17, + IER_PERIB_INTB190 = 0x17, + IER_PERIB_INTB191 = 0x17, + IER_PERIB_INTB192 = 0x18, + IER_PERIB_INTB193 = 0x18, + IER_PERIB_INTB194 = 0x18, + IER_PERIB_INTB195 = 0x18, + IER_PERIB_INTB196 = 0x18, + IER_PERIB_INTB197 = 0x18, + IER_PERIB_INTB198 = 0x18, + IER_PERIB_INTB199 = 0x18, + IER_PERIB_INTB200 = 0x19, + IER_PERIB_INTB201 = 0x19, + IER_PERIB_INTB202 = 0x19, + IER_PERIB_INTB203 = 0x19, + IER_PERIB_INTB204 = 0x19, + IER_PERIB_INTB205 = 0x19, + IER_PERIB_INTB206 = 0x19, + IER_PERIB_INTB207 = 0x19, + IER_PERIA_INTA208 = 0x1a, + IER_PERIA_INTA209 = 0x1a, + IER_PERIA_INTA210 = 0x1a, + IER_PERIA_INTA211 = 0x1a, + IER_PERIA_INTA212 = 0x1a, + IER_PERIA_INTA213 = 0x1a, + IER_PERIA_INTA214 = 0x1a, + IER_PERIA_INTA215 = 0x1a, + IER_PERIA_INTA216 = 0x1b, + IER_PERIA_INTA217 = 0x1b, + IER_PERIA_INTA218 = 0x1b, + IER_PERIA_INTA219 = 0x1b, + IER_PERIA_INTA220 = 0x1b, + IER_PERIA_INTA221 = 0x1b, + IER_PERIA_INTA222 = 0x1b, + IER_PERIA_INTA223 = 0x1b, + IER_PERIA_INTA224 = 0x1c, + IER_PERIA_INTA225 = 0x1c, + IER_PERIA_INTA226 = 0x1c, + IER_PERIA_INTA227 = 0x1c, + IER_PERIA_INTA228 = 0x1c, + IER_PERIA_INTA229 = 0x1c, + IER_PERIA_INTA230 = 0x1c, + IER_PERIA_INTA231 = 0x1c, + IER_PERIA_INTA232 = 0x1d, + IER_PERIA_INTA233 = 0x1d, + IER_PERIA_INTA234 = 0x1d, + IER_PERIA_INTA235 = 0x1d, + IER_PERIA_INTA236 = 0x1d, + IER_PERIA_INTA237 = 0x1d, + IER_PERIA_INTA238 = 0x1d, + IER_PERIA_INTA239 = 0x1d, + IER_PERIA_INTA240 = 0x1e, + IER_PERIA_INTA241 = 0x1e, + IER_PERIA_INTA242 = 0x1e, + IER_PERIA_INTA243 = 0x1e, + IER_PERIA_INTA244 = 0x1e, + IER_PERIA_INTA245 = 0x1e, + IER_PERIA_INTA246 = 0x1e, + IER_PERIA_INTA247 = 0x1e, + IER_PERIA_INTA248 = 0x1f, + IER_PERIA_INTA249 = 0x1f, + IER_PERIA_INTA250 = 0x1f, + IER_PERIA_INTA251 = 0x1f, + IER_PERIA_INTA252 = 0x1f, + IER_PERIA_INTA253 = 0x1f, + IER_PERIA_INTA254 = 0x1f, + IER_PERIA_INTA255 = 0x1f +} enum_ier_t; + +typedef enum enum_ipr +{ + IPR_BSC_BUSERR = 0, + IPR_RAM_RAMERR = 0, + IPR_FCU_FIFERR = 1, + IPR_FCU_FRDYI = 2, + IPR_ICU_SWINT2 = 3, + IPR_ICU_SWINT = 3, + IPR_CMT0_CMI0 = 4, + IPR_CMT1_CMI1 = 5, + IPR_CMTW0_CMWI0 = 6, + IPR_CMTW1_CMWI1 = 7, + IPR_USB0_D0FIFO0 = 34, + IPR_USB0_D1FIFO0 = 35, + IPR_RSPI0_SPRI0 = 38, + IPR_RSPI0_SPTI0 = 39, + IPR_RSPI1_SPRI1 = 40, + IPR_RSPI1_SPTI1 = 41, + IPR_QSPI_SPRI = 42, + IPR_QSPI_SPTI = 43, + IPR_SDHI_SBFAI = 44, + IPR_MMCIF_MBFAI = 45, + IPR_RIIC1_RXI1 = 50, + IPR_RIIC1_TXI1 = 51, + IPR_RIIC0_RXI0 = 52, + IPR_RIIC0_TXI0 = 53, + IPR_RIIC2_RXI2 = 54, + IPR_RIIC2_TXI2 = 55, + IPR_SCI0_RXI0 = 58, + IPR_SCI0_TXI0 = 59, + IPR_SCI1_RXI1 = 60, + IPR_SCI1_TXI1 = 61, + IPR_SCI2_RXI2 = 62, + IPR_SCI2_TXI2 = 63, + IPR_ICU_IRQ0 = 64, + IPR_ICU_IRQ1 = 65, + IPR_ICU_IRQ2 = 66, + IPR_ICU_IRQ3 = 67, + IPR_ICU_IRQ4 = 68, + IPR_ICU_IRQ5 = 69, + IPR_ICU_IRQ6 = 70, + IPR_ICU_IRQ7 = 71, + IPR_ICU_IRQ8 = 72, + IPR_ICU_IRQ9 = 73, + IPR_ICU_IRQ10 = 74, + IPR_ICU_IRQ11 = 75, + IPR_ICU_IRQ12 = 76, + IPR_ICU_IRQ13 = 77, + IPR_ICU_IRQ14 = 78, + IPR_ICU_IRQ15 = 79, + IPR_SCI3_RXI3 = 80, + IPR_SCI3_TXI3 = 81, + IPR_SCI4_RXI4 = 82, + IPR_SCI4_TXI4 = 83, + IPR_SCI5_RXI5 = 84, + IPR_SCI5_TXI5 = 85, + IPR_SCI6_RXI6 = 86, + IPR_SCI6_TXI6 = 87, + IPR_LVD1_LVD1 = 88, + IPR_LVD2_LVD2 = 89, + IPR_USB0_USBR0 = 90, + IPR_RTC_ALM = 92, + IPR_RTC_PRD = 93, + IPR_IWDT_IWUNI = 95, + IPR_WDT_WUNI = 96, + IPR_PDC_PCDFI = 97, + IPR_SCI7_RXI7 = 98, + IPR_SCI7_TXI7 = 99, + IPR_SCI8_RXI8 = 100, + IPR_SCI8_TXI8 = 101, + IPR_SCI9_RXI9 = 102, + IPR_SCI9_TXI9 = 103, + IPR_SCI10_RXI10 = 104, + IPR_SCI10_TXI10 = 105, + IPR_ICU_GROUPBE0 = 106, + IPR_ICU_GROUPBL2 = 107, + IPR_RSPI2_SPRI2 = 108, + IPR_RSPI2_SPTI2 = 109, + IPR_ICU_GROUPBL0 = 110, + IPR_ICU_GROUPBL1 = 111, + IPR_ICU_GROUPAL0 = 112, + IPR_ICU_GROUPAL1 = 113, + IPR_SCI11_RXI11 = 114, + IPR_SCI11_TXI11 = 115, + IPR_SCI12_RXI12 = 116, + IPR_SCI12_TXI12 = 117, + IPR_DMAC_DMAC0I = 120, + IPR_DMAC_DMAC1I = 121, + IPR_DMAC_DMAC2I = 122, + IPR_DMAC_DMAC3I = 123, + IPR_DMAC_DMAC74I = 124, + IPR_OST_OSTDI = 125, + IPR_EXDMAC_EXDMAC0I = 126, + IPR_EXDMAC_EXDMAC1I = 127, + IPR_PERIB_INTB128 = 128, + IPR_PERIB_INTB129 = 129, + IPR_PERIB_INTB130 = 130, + IPR_PERIB_INTB131 = 131, + IPR_PERIB_INTB132 = 132, + IPR_PERIB_INTB133 = 133, + IPR_PERIB_INTB134 = 134, + IPR_PERIB_INTB135 = 135, + IPR_PERIB_INTB136 = 136, + IPR_PERIB_INTB137 = 137, + IPR_PERIB_INTB138 = 138, + IPR_PERIB_INTB139 = 139, + IPR_PERIB_INTB140 = 140, + IPR_PERIB_INTB141 = 141, + IPR_PERIB_INTB142 = 142, + IPR_PERIB_INTB143 = 143, + IPR_PERIB_INTB144 = 144, + IPR_PERIB_INTB145 = 145, + IPR_PERIB_INTB146 = 146, + IPR_PERIB_INTB147 = 147, + IPR_PERIB_INTB148 = 148, + IPR_PERIB_INTB149 = 149, + IPR_PERIB_INTB150 = 150, + IPR_PERIB_INTB151 = 151, + IPR_PERIB_INTB152 = 152, + IPR_PERIB_INTB153 = 153, + IPR_PERIB_INTB154 = 154, + IPR_PERIB_INTB155 = 155, + IPR_PERIB_INTB156 = 156, + IPR_PERIB_INTB157 = 157, + IPR_PERIB_INTB158 = 158, + IPR_PERIB_INTB159 = 159, + IPR_PERIB_INTB160 = 160, + IPR_PERIB_INTB161 = 161, + IPR_PERIB_INTB162 = 162, + IPR_PERIB_INTB163 = 163, + IPR_PERIB_INTB164 = 164, + IPR_PERIB_INTB165 = 165, + IPR_PERIB_INTB166 = 166, + IPR_PERIB_INTB167 = 167, + IPR_PERIB_INTB168 = 168, + IPR_PERIB_INTB169 = 169, + IPR_PERIB_INTB170 = 170, + IPR_PERIB_INTB171 = 171, + IPR_PERIB_INTB172 = 172, + IPR_PERIB_INTB173 = 173, + IPR_PERIB_INTB174 = 174, + IPR_PERIB_INTB175 = 175, + IPR_PERIB_INTB176 = 176, + IPR_PERIB_INTB177 = 177, + IPR_PERIB_INTB178 = 178, + IPR_PERIB_INTB179 = 179, + IPR_PERIB_INTB180 = 180, + IPR_PERIB_INTB181 = 181, + IPR_PERIB_INTB182 = 182, + IPR_PERIB_INTB183 = 183, + IPR_PERIB_INTB184 = 184, + IPR_PERIB_INTB185 = 185, + IPR_PERIB_INTB186 = 186, + IPR_PERIB_INTB187 = 187, + IPR_PERIB_INTB188 = 188, + IPR_PERIB_INTB189 = 189, + IPR_PERIB_INTB190 = 190, + IPR_PERIB_INTB191 = 191, + IPR_PERIB_INTB192 = 192, + IPR_PERIB_INTB193 = 193, + IPR_PERIB_INTB194 = 194, + IPR_PERIB_INTB195 = 195, + IPR_PERIB_INTB196 = 196, + IPR_PERIB_INTB197 = 197, + IPR_PERIB_INTB198 = 198, + IPR_PERIB_INTB199 = 199, + IPR_PERIB_INTB200 = 200, + IPR_PERIB_INTB201 = 201, + IPR_PERIB_INTB202 = 202, + IPR_PERIB_INTB203 = 203, + IPR_PERIB_INTB204 = 204, + IPR_PERIB_INTB205 = 205, + IPR_PERIB_INTB206 = 206, + IPR_PERIB_INTB207 = 207, + IPR_PERIA_INTA208 = 208, + IPR_PERIA_INTA209 = 209, + IPR_PERIA_INTA210 = 210, + IPR_PERIA_INTA211 = 211, + IPR_PERIA_INTA212 = 212, + IPR_PERIA_INTA213 = 213, + IPR_PERIA_INTA214 = 214, + IPR_PERIA_INTA215 = 215, + IPR_PERIA_INTA216 = 216, + IPR_PERIA_INTA217 = 217, + IPR_PERIA_INTA218 = 218, + IPR_PERIA_INTA219 = 219, + IPR_PERIA_INTA220 = 220, + IPR_PERIA_INTA221 = 221, + IPR_PERIA_INTA222 = 222, + IPR_PERIA_INTA223 = 223, + IPR_PERIA_INTA224 = 224, + IPR_PERIA_INTA225 = 225, + IPR_PERIA_INTA226 = 226, + IPR_PERIA_INTA227 = 227, + IPR_PERIA_INTA228 = 228, + IPR_PERIA_INTA229 = 229, + IPR_PERIA_INTA230 = 230, + IPR_PERIA_INTA231 = 231, + IPR_PERIA_INTA232 = 232, + IPR_PERIA_INTA233 = 233, + IPR_PERIA_INTA234 = 234, + IPR_PERIA_INTA235 = 235, + IPR_PERIA_INTA236 = 236, + IPR_PERIA_INTA237 = 237, + IPR_PERIA_INTA238 = 238, + IPR_PERIA_INTA239 = 239, + IPR_PERIA_INTA240 = 240, + IPR_PERIA_INTA241 = 241, + IPR_PERIA_INTA242 = 242, + IPR_PERIA_INTA243 = 243, + IPR_PERIA_INTA244 = 244, + IPR_PERIA_INTA245 = 245, + IPR_PERIA_INTA246 = 246, + IPR_PERIA_INTA247 = 247, + IPR_PERIA_INTA248 = 248, + IPR_PERIA_INTA249 = 249, + IPR_PERIA_INTA250 = 250, + IPR_PERIA_INTA251 = 251, + IPR_PERIA_INTA252 = 252, + IPR_PERIA_INTA253 = 253, + IPR_PERIA_INTA254 = 254, + IPR_PERIA_INTA255 = 255, + IPR_ICU_SWI = 3, + IPR_CMT0_ = 4, + IPR_CMT1_ = 5, + IPR_CMTW0_ = 6, + IPR_CMTW1_ = 7, + IPR_SDHI_ = 44, + IPR_MMCIF_ = 45, + IPR_LVD1_ = 88, + IPR_LVD2_ = 89, + IPR_IWDT_ = 95, + IPR_WDT_ = 96, + IPR_PDC_ = 97, + IPR_OST_ = 125 +} enum_ipr_t; + +#pragma pack(4) + +struct st_bsc_berclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif +}; + +union un_bsc_berclr +{ + unsigned char BYTE; + struct st_bsc_berclr_bit BIT; +}; + +struct st_bsc_beren_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif +}; + +union un_bsc_beren +{ + unsigned char BYTE; + struct st_bsc_beren_bit BIT; +}; + +struct st_bsc_bersr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif +}; + +union un_bsc_bersr1 +{ + unsigned char BYTE; + struct st_bsc_bersr1_bit BIT; +}; + +struct st_bsc_bersr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif +}; + +union un_bsc_bersr2 +{ + unsigned short WORD; + struct st_bsc_bersr2_bit BIT; +}; + +struct st_bsc_buspri_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif +}; + +union un_bsc_buspri +{ + unsigned short WORD; + struct st_bsc_buspri_bit BIT; +}; + +struct st_bsc_cs0mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs0mod +{ + unsigned short WORD; + struct st_bsc_cs0mod_bit BIT; +}; + +struct st_bsc_cs0wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs0wcr1 +{ + unsigned long LONG; + struct st_bsc_cs0wcr1_bit BIT; +}; + +struct st_bsc_cs0wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs0wcr2 +{ + unsigned long LONG; + struct st_bsc_cs0wcr2_bit BIT; +}; + +struct st_bsc_cs1mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs1mod +{ + unsigned short WORD; + struct st_bsc_cs1mod_bit BIT; +}; + +struct st_bsc_cs1wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs1wcr1 +{ + unsigned long LONG; + struct st_bsc_cs1wcr1_bit BIT; +}; + +struct st_bsc_cs1wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs1wcr2 +{ + unsigned long LONG; + struct st_bsc_cs1wcr2_bit BIT; +}; + +struct st_bsc_cs2mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs2mod +{ + unsigned short WORD; + struct st_bsc_cs2mod_bit BIT; +}; + +struct st_bsc_cs2wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs2wcr1 +{ + unsigned long LONG; + struct st_bsc_cs2wcr1_bit BIT; +}; + +struct st_bsc_cs2wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs2wcr2 +{ + unsigned long LONG; + struct st_bsc_cs2wcr2_bit BIT; +}; + +struct st_bsc_cs3mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs3mod +{ + unsigned short WORD; + struct st_bsc_cs3mod_bit BIT; +}; + +struct st_bsc_cs3wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs3wcr1 +{ + unsigned long LONG; + struct st_bsc_cs3wcr1_bit BIT; +}; + +struct st_bsc_cs3wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs3wcr2 +{ + unsigned long LONG; + struct st_bsc_cs3wcr2_bit BIT; +}; + +struct st_bsc_cs4mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs4mod +{ + unsigned short WORD; + struct st_bsc_cs4mod_bit BIT; +}; + +struct st_bsc_cs4wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs4wcr1 +{ + unsigned long LONG; + struct st_bsc_cs4wcr1_bit BIT; +}; + +struct st_bsc_cs4wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs4wcr2 +{ + unsigned long LONG; + struct st_bsc_cs4wcr2_bit BIT; +}; + +struct st_bsc_cs5mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs5mod +{ + unsigned short WORD; + struct st_bsc_cs5mod_bit BIT; +}; + +struct st_bsc_cs5wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs5wcr1 +{ + unsigned long LONG; + struct st_bsc_cs5wcr1_bit BIT; +}; + +struct st_bsc_cs5wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs5wcr2 +{ + unsigned long LONG; + struct st_bsc_cs5wcr2_bit BIT; +}; + +struct st_bsc_cs6mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs6mod +{ + unsigned short WORD; + struct st_bsc_cs6mod_bit BIT; +}; + +struct st_bsc_cs6wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs6wcr1 +{ + unsigned long LONG; + struct st_bsc_cs6wcr1_bit BIT; +}; + +struct st_bsc_cs6wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs6wcr2 +{ + unsigned long LONG; + struct st_bsc_cs6wcr2_bit BIT; +}; + +struct st_bsc_cs7mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_bsc_cs7mod +{ + unsigned short WORD; + struct st_bsc_cs7mod_bit BIT; +}; + +struct st_bsc_cs7wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_bsc_cs7wcr1 +{ + unsigned long LONG; + struct st_bsc_cs7wcr1_bit BIT; +}; + +struct st_bsc_cs7wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_bsc_cs7wcr2 +{ + unsigned long LONG; + struct st_bsc_cs7wcr2_bit BIT; +}; + +struct st_bsc_cs0cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs0cr +{ + unsigned short WORD; + struct st_bsc_cs0cr_bit BIT; +}; + +struct st_bsc_cs0rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs0rec +{ + unsigned short WORD; + struct st_bsc_cs0rec_bit BIT; +}; + +struct st_bsc_cs1cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs1cr +{ + unsigned short WORD; + struct st_bsc_cs1cr_bit BIT; +}; + +struct st_bsc_cs1rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs1rec +{ + unsigned short WORD; + struct st_bsc_cs1rec_bit BIT; +}; + +struct st_bsc_cs2cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs2cr +{ + unsigned short WORD; + struct st_bsc_cs2cr_bit BIT; +}; + +struct st_bsc_cs2rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs2rec +{ + unsigned short WORD; + struct st_bsc_cs2rec_bit BIT; +}; + +struct st_bsc_cs3cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs3cr +{ + unsigned short WORD; + struct st_bsc_cs3cr_bit BIT; +}; + +struct st_bsc_cs3rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs3rec +{ + unsigned short WORD; + struct st_bsc_cs3rec_bit BIT; +}; + +struct st_bsc_cs4cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs4cr +{ + unsigned short WORD; + struct st_bsc_cs4cr_bit BIT; +}; + +struct st_bsc_cs4rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs4rec +{ + unsigned short WORD; + struct st_bsc_cs4rec_bit BIT; +}; + +struct st_bsc_cs5cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs5cr +{ + unsigned short WORD; + struct st_bsc_cs5cr_bit BIT; +}; + +struct st_bsc_cs5rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs5rec +{ + unsigned short WORD; + struct st_bsc_cs5rec_bit BIT; +}; + +struct st_bsc_cs6cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs6cr +{ + unsigned short WORD; + struct st_bsc_cs6cr_bit BIT; +}; + +struct st_bsc_cs6rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs6rec +{ + unsigned short WORD; + struct st_bsc_cs6rec_bit BIT; +}; + +struct st_bsc_cs7cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_bsc_cs7cr +{ + unsigned short WORD; + struct st_bsc_cs7cr_bit BIT; +}; + +struct st_bsc_cs7rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_bsc_cs7rec +{ + unsigned short WORD; + struct st_bsc_cs7rec_bit BIT; +}; + +struct st_bsc_csrecen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif +}; + +union un_bsc_csrecen +{ + unsigned short WORD; + struct st_bsc_csrecen_bit BIT; +}; + +struct st_bsc_sdccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXENB : 1; + unsigned char : 3; + unsigned char BSIZE : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BSIZE : 2; + unsigned char : 3; + unsigned char EXENB : 1; +#endif +}; + +union un_bsc_sdccr +{ + unsigned char BYTE; + struct st_bsc_sdccr_bit BIT; +}; + +struct st_bsc_sdcmod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EMODE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EMODE : 1; +#endif +}; + +union un_bsc_sdcmod +{ + unsigned char BYTE; + struct st_bsc_sdcmod_bit BIT; +}; + +struct st_bsc_sdamod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BE : 1; +#endif +}; + +union un_bsc_sdamod +{ + unsigned char BYTE; + struct st_bsc_sdamod_bit BIT; +}; + +struct st_bsc_sdself_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SFEN : 1; +#endif +}; + +union un_bsc_sdself +{ + unsigned char BYTE; + struct st_bsc_sdself_bit BIT; +}; + +struct st_bsc_sdrfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 12; + unsigned short REFW : 4; +#else + unsigned short REFW : 4; + unsigned short RFC : 12; +#endif +}; + +union un_bsc_sdrfcr +{ + unsigned short WORD; + struct st_bsc_sdrfcr_bit BIT; +}; + +struct st_bsc_sdrfen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RFEN : 1; +#endif +}; + +union un_bsc_sdrfen +{ + unsigned char BYTE; + struct st_bsc_sdrfen_bit BIT; +}; + +struct st_bsc_sdicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INIRQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char INIRQ : 1; +#endif +}; + +union un_bsc_sdicr +{ + unsigned char BYTE; + struct st_bsc_sdicr_bit BIT; +}; + +struct st_bsc_sdir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ARFI : 4; + unsigned short ARFC : 4; + unsigned short PRC : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short PRC : 3; + unsigned short ARFC : 4; + unsigned short ARFI : 4; +#endif +}; + +union un_bsc_sdir +{ + unsigned short WORD; + struct st_bsc_sdir_bit BIT; +}; + +struct st_bsc_sdadr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MXC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MXC : 2; +#endif +}; + +union un_bsc_sdadr +{ + unsigned char BYTE; + struct st_bsc_sdadr_bit BIT; +}; + +struct st_bsc_sdtr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CL : 3; + unsigned long : 5; + unsigned long WR : 1; + unsigned long RP : 3; + unsigned long RCD : 2; + unsigned long : 2; + unsigned long RAS : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RAS : 3; + unsigned long : 2; + unsigned long RCD : 2; + unsigned long RP : 3; + unsigned long WR : 1; + unsigned long : 5; + unsigned long CL : 3; +#endif +}; + +union un_bsc_sdtr +{ + unsigned long LONG; + struct st_bsc_sdtr_bit BIT; +}; + +struct st_bsc_sdmod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MR : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short MR : 15; +#endif +}; + +union un_bsc_sdmod +{ + unsigned short WORD; + struct st_bsc_sdmod_bit BIT; +}; + +struct st_bsc_sdsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MRSST : 1; + unsigned char : 2; + unsigned char INIST : 1; + unsigned char SRFST : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SRFST : 1; + unsigned char INIST : 1; + unsigned char : 2; + unsigned char MRSST : 1; +#endif +}; + +union un_bsc_sdsr +{ + unsigned char BYTE; + struct st_bsc_sdsr_bit BIT; +}; + +struct st_bsc_ebmapcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PR1SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR5SEL : 3; + unsigned long : 10; + unsigned long RPSTOP : 1; + unsigned long : 1; + unsigned long PRERR : 1; +#else + unsigned long PRERR : 1; + unsigned long : 1; + unsigned long RPSTOP : 1; + unsigned long : 10; + unsigned long PR5SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR1SEL : 3; +#endif +}; + +union un_bsc_ebmapcr +{ + unsigned long LONG; + struct st_bsc_ebmapcr_bit BIT; +}; + +struct st_cac_cacr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif +}; + +union un_cac_cacr0 +{ + unsigned char BYTE; + struct st_cac_cacr0_bit BIT; +}; + +struct st_cac_cacr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif +}; + +union un_cac_cacr1 +{ + unsigned char BYTE; + struct st_cac_cacr1_bit BIT; +}; + +struct st_cac_cacr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif +}; + +union un_cac_cacr2 +{ + unsigned char BYTE; + struct st_cac_cacr2_bit BIT; +}; + +struct st_cac_caicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif +}; + +union un_cac_caicr +{ + unsigned char BYTE; + struct st_cac_caicr_bit BIT; +}; + +struct st_cac_castr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif +}; + +union un_cac_castr +{ + unsigned char BYTE; + struct st_cac_castr_bit BIT; +}; + +struct st_cmt_cmstr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif +}; + +union un_cmt_cmstr0 +{ + unsigned short WORD; + struct st_cmt_cmstr0_bit BIT; +}; + +struct st_cmt_cmstr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif +}; + +union un_cmt_cmstr1 +{ + unsigned short WORD; + struct st_cmt_cmstr1_bit BIT; +}; + +struct st_cmt0_cmcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif +}; + +union un_cmt0_cmcr +{ + unsigned short WORD; + struct st_cmt0_cmcr_bit BIT; +}; + +struct st_cmtw_cmwstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short STR : 1; +#endif +}; + +union un_cmtw_cmwstr +{ + unsigned short WORD; + struct st_cmtw_cmwstr_bit BIT; +}; + +struct st_cmtw_cmwcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short CMWIE : 1; + unsigned short IC0IE : 1; + unsigned short IC1IE : 1; + unsigned short OC0IE : 1; + unsigned short OC1IE : 1; + unsigned short : 1; + unsigned short CMS : 1; + unsigned short : 3; + unsigned short CCLR : 3; +#else + unsigned short CCLR : 3; + unsigned short : 3; + unsigned short CMS : 1; + unsigned short : 1; + unsigned short OC1IE : 1; + unsigned short OC0IE : 1; + unsigned short IC1IE : 1; + unsigned short IC0IE : 1; + unsigned short CMWIE : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif +}; + +union un_cmtw_cmwcr +{ + unsigned short WORD; + struct st_cmtw_cmwcr_bit BIT; +}; + +struct st_cmtw_cmwior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IC0 : 2; + unsigned short IC1 : 2; + unsigned short IC0E : 1; + unsigned short IC1E : 1; + unsigned short : 2; + unsigned short OC0 : 2; + unsigned short OC1 : 2; + unsigned short OC0E : 1; + unsigned short OC1E : 1; + unsigned short : 1; + unsigned short CMWE : 1; +#else + unsigned short CMWE : 1; + unsigned short : 1; + unsigned short OC1E : 1; + unsigned short OC0E : 1; + unsigned short OC1 : 2; + unsigned short OC0 : 2; + unsigned short : 2; + unsigned short IC1E : 1; + unsigned short IC0E : 1; + unsigned short IC1 : 2; + unsigned short IC0 : 2; +#endif +}; + +union un_cmtw_cmwior +{ + unsigned short WORD; + struct st_cmtw_cmwior_bit BIT; +}; + +struct st_icu_ier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif +}; + +union un_icu_ier32 +{ + unsigned char BYTE; + struct st_icu_ier_bit BIT; +}; + +struct st_icu_irqcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif +}; + +union un_icu_irqcr16 +{ + unsigned char BYTE; + struct st_icu_irqcr_bit BIT; +}; + +struct st_icu_swintr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif +}; + +union un_icu_swintr +{ + unsigned char BYTE; + struct st_icu_swintr_bit BIT; +}; + +struct st_icu_swint2r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT2 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT2 : 1; +#endif +}; + +union un_icu_swint2r +{ + unsigned char BYTE; + struct st_icu_swint2r_bit BIT; +}; + +struct st_icu_grpbl0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbl0 +{ + unsigned long LONG; + struct st_icu_grpbl0_bit BIT; +}; + +struct st_icu_genbl0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbl0 +{ + unsigned long LONG; + struct st_icu_genbl0_bit BIT; +}; + +struct st_mpc_pwpr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif +}; + +struct st_icu_grpbl1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbl1 +{ + unsigned long LONG; + struct st_icu_grpbl1_bit BIT; +}; + +struct st_icu_genbl1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbl1 +{ + unsigned long LONG; + struct st_icu_genbl1_bit BIT; +}; + +struct st_icu_grpal0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpal0 +{ + unsigned long LONG; + struct st_icu_grpal0_bit BIT; +}; + +struct st_icu_genal0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genal0 +{ + unsigned long LONG; + struct st_icu_genal0_bit BIT; +}; + +struct st_icu_grpal1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpal1 +{ + unsigned long LONG; + struct st_icu_grpal1_bit BIT; +}; + +struct st_icu_genal1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genal1 +{ + unsigned long LONG; + struct st_icu_genal1_bit BIT; +}; + +union un_mpc_pwpr +{ + unsigned char BYTE; + struct st_mpc_pwpr_bit BIT; +}; + +struct st_icu_ir256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif +}; + +union un_icu_ir256 +{ + unsigned char BYTE; + struct st_icu_ir256_bit BIT; +}; + +struct st_icu_dtcer256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif +}; + +union un_icu_dtcer256 +{ + unsigned char BYTE; + struct st_icu_dtcer256_bit BIT; +}; + +struct st_icu_fir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif +}; + +union un_icu_fir +{ + unsigned short WORD; + struct st_icu_fir_bit BIT; +}; + +struct st_icu_ipr256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif +}; + +union un_icu_ipr256 +{ + unsigned char BYTE; + struct st_icu_ipr256_bit BIT; +}; + +struct st_icu_irqflte0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif +}; + +union un_icu_irqflte0 +{ + unsigned char BYTE; + struct st_icu_irqflte0_bit BIT; +}; + +struct st_icu_irqflte1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN8 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN15 : 1; +#else + unsigned char FLTEN15 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN8 : 1; +#endif +}; + +union un_icu_irqflte1 +{ + unsigned char BYTE; + struct st_icu_irqflte1_bit BIT; +}; + +struct st_icu_irqfltc0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif +}; + +union un_icu_irqfltc0 +{ + unsigned short WORD; + struct st_icu_irqfltc0_bit BIT; +}; + +struct st_icu_irqfltc1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL8 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL15 : 2; +#else + unsigned short FCLKSEL15 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL8 : 2; +#endif +}; + +union un_icu_irqfltc1 +{ + unsigned short WORD; + struct st_icu_irqfltc1_bit BIT; +}; + +struct st_icu_nmisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char RAMST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif +}; + +union un_icu_nmisr +{ + unsigned char BYTE; + struct st_icu_nmisr_bit BIT; +}; + +struct st_icu_nmier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char RAMEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif +}; + +union un_icu_nmier +{ + unsigned char BYTE; + struct st_icu_nmier_bit BIT; +}; + +struct st_icu_nmiclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif +}; + +union un_icu_nmiclr +{ + unsigned char BYTE; + struct st_icu_nmiclr_bit BIT; +}; + +struct st_icu_nmicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif +}; + +union un_icu_nmicr +{ + unsigned char BYTE; + struct st_icu_nmicr_bit BIT; +}; + +struct st_icu_nmiflte_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif +}; + +union un_icu_nmiflte +{ + unsigned char BYTE; + struct st_icu_nmiflte_bit BIT; +}; + +struct st_icu_nmifltc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif +}; + +union un_icu_nmifltc +{ + unsigned char BYTE; + struct st_icu_nmifltc_bit BIT; +}; + +struct st_icu_grpbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbe0 +{ + unsigned long LONG; + struct st_icu_grpbe0_bit BIT; +}; + +struct st_icu_grpbl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbl2 +{ + unsigned long LONG; + struct st_icu_grpbl2_bit BIT; +}; + +struct st_icu_genbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbe0 +{ + unsigned long LONG; + struct st_icu_genbe0_bit BIT; +}; + +struct st_icu_genbl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbl2 +{ + unsigned long LONG; + struct st_icu_genbl2_bit BIT; +}; + +struct st_icu_gcrbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR0 : 1; + unsigned long CLR1 : 1; + unsigned long CLR2 : 1; + unsigned long CLR3 : 1; + unsigned long CLR4 : 1; + unsigned long CLR5 : 1; + unsigned long CLR6 : 1; + unsigned long CLR7 : 1; + unsigned long CLR8 : 1; + unsigned long CLR9 : 1; + unsigned long CLR10 : 1; + unsigned long CLR11 : 1; + unsigned long CLR12 : 1; + unsigned long CLR13 : 1; + unsigned long CLR14 : 1; + unsigned long CLR15 : 1; + unsigned long CLR16 : 1; + unsigned long CLR17 : 1; + unsigned long CLR18 : 1; + unsigned long CLR19 : 1; + unsigned long CLR20 : 1; + unsigned long CLR21 : 1; + unsigned long CLR22 : 1; + unsigned long CLR23 : 1; + unsigned long CLR24 : 1; + unsigned long CLR25 : 1; + unsigned long CLR26 : 1; + unsigned long CLR27 : 1; + unsigned long CLR28 : 1; + unsigned long CLR29 : 1; + unsigned long CLR30 : 1; + unsigned long CLR31 : 1; +#else + unsigned long CLR31 : 1; + unsigned long CLR30 : 1; + unsigned long CLR29 : 1; + unsigned long CLR28 : 1; + unsigned long CLR27 : 1; + unsigned long CLR26 : 1; + unsigned long CLR25 : 1; + unsigned long CLR24 : 1; + unsigned long CLR23 : 1; + unsigned long CLR22 : 1; + unsigned long CLR21 : 1; + unsigned long CLR20 : 1; + unsigned long CLR19 : 1; + unsigned long CLR18 : 1; + unsigned long CLR17 : 1; + unsigned long CLR16 : 1; + unsigned long CLR15 : 1; + unsigned long CLR14 : 1; + unsigned long CLR13 : 1; + unsigned long CLR12 : 1; + unsigned long CLR11 : 1; + unsigned long CLR10 : 1; + unsigned long CLR9 : 1; + unsigned long CLR8 : 1; + unsigned long CLR7 : 1; + unsigned long CLR6 : 1; + unsigned long CLR5 : 1; + unsigned long CLR4 : 1; + unsigned long CLR3 : 1; + unsigned long CLR2 : 1; + unsigned long CLR1 : 1; + unsigned long CLR0 : 1; +#endif +}; + +union un_icu_gcrbe0 +{ + unsigned long LONG; + struct st_icu_gcrbe0_bit BIT; +}; + +struct st_icu_pibr0_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr0 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr0_bit BIT; +#endif +}; + +struct st_icu_pibr1_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr1 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr1_bit BIT; +#endif +}; + +struct st_icu_pibr2_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr2 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr2_bit BIT; +#endif +}; + +struct st_icu_pibr3_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr3 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr3_bit BIT; +#endif +}; + +struct st_icu_pibr4_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr4 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr4_bit BIT; +#endif +}; + +struct st_icu_pibr5_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr5 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr5_bit BIT; +#endif +}; + +struct st_icu_pibr6_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr6 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_prib6_bit BIT; +#endif +}; + +struct st_icu_pibr7_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr7 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr7_bit BIT; +#endif +}; + +struct st_icu_pibr8_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr8 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr8_bit BIT; +#endif +}; + +struct st_icu_pibr9_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr9 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr9_bit BIT; +#endif +}; + +struct st_icu_pibra_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibra +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibra_bit BIT; +#endif +}; + +struct st_icu_pibrb_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibrb +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibrb_bit BIT; +#endif +}; + +struct st_icu_slibxr128_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr128 +{ + unsigned char BYTE; + struct st_icu_slibxr128_bit BIT; +}; + +struct st_icu_slibxr129_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr129 +{ + unsigned char BYTE; + struct st_icu_slibxr129_bit BIT; +}; + +struct st_icu_slibxr130_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr130 +{ + unsigned char BYTE; + struct st_icu_slibxr130_bit BIT; +}; + +struct st_icu_slibxr131_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr131 +{ + unsigned char BYTE; + struct st_icu_slibxr131_bit BIT; +}; + +struct st_icu_slibxr132_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr132 +{ + unsigned char BYTE; + struct st_icu_slibxr132_bit BIT; +}; + +struct st_icu_slibxr133_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr133 +{ + unsigned char BYTE; + struct st_icu_slibxr133_bit BIT; +}; + +struct st_icu_slibxr134_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr134 +{ + unsigned char BYTE; + struct st_icu_slibxr134_bit BIT; +}; + +struct st_icu_slibxr135_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr135 +{ + unsigned char BYTE; + struct st_icu_slibxr135_bit BIT; +}; + +struct st_icu_slibxr136_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr136 +{ + unsigned char BYTE; + struct st_icu_slibxr136_bit BIT; +}; + +struct st_icu_slibxr137_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr137 +{ + unsigned char BYTE; + struct st_icu_slibxr137_bit BIT; +}; + +struct st_icu_slibxr138_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr138 +{ + unsigned char BYTE; + struct st_icu_slibxr138_bit BIT; +}; + +struct st_icu_slibxr139_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr139 +{ + unsigned char BYTE; + struct st_icu_slibxr139_bit BIT; +}; + +struct st_icu_slibxr140_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr140 +{ + unsigned char BYTE; + struct st_icu_slibxr140_bit BIT; +}; + +struct st_icu_slibxr141_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr141 +{ + unsigned char BYTE; + struct st_icu_slibxr141_bit BIT; +}; + +struct st_icu_slibxr142_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr142 +{ + unsigned char BYTE; + struct st_icu_slibxr142_bit BIT; +}; + +struct st_icu_slibxr143_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr143 +{ + unsigned char BYTE; + struct st_icu_slibxr143_bit BIT; +}; + +struct st_icu_slibr144_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr144 +{ + unsigned char BYTE; + struct st_icu_slibr144_bit BIT; +}; + +struct st_icu_slibr145_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr145 +{ + unsigned char BYTE; + struct st_icu_slibr145_bit BIT; +}; + +struct st_icu_slibr146_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr146 +{ + unsigned char BYTE; + struct st_icu_slibr146_bit BIT; +}; + +struct st_icu_slibr147_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr147 +{ + unsigned char BYTE; + struct st_icu_slibr147_bit BIT; +}; + +struct st_icu_slibr148_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr148 +{ + unsigned char BYTE; + struct st_icu_slibr148_bit BIT; +}; + +struct st_icu_slibr149_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr149 +{ + unsigned char BYTE; + struct st_icu_slibr149_bit BIT; +}; + +struct st_icu_slibr150_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr150 +{ + unsigned char BYTE; + struct st_icu_slibr150_bit BIT; +}; + +struct st_icu_slibr151_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr151 +{ + unsigned char BYTE; + struct st_icu_slibr151_bit BIT; +}; + +struct st_icu_slibr152_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr152 +{ + unsigned char BYTE; + struct st_icu_slibr152_bit BIT; +}; + +struct st_icu_slibr153_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr153 +{ + unsigned char BYTE; + struct st_icu_slibr153_bit BIT; +}; + +struct st_icu_slibr154_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr154 +{ + unsigned char BYTE; + struct st_icu_slibr154_bit BIT; +}; + +struct st_icu_slibr155_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr155 +{ + unsigned char BYTE; + struct st_icu_slibr155_bit BIT; +}; + +struct st_icu_slibr156_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr156 +{ + unsigned char BYTE; + struct st_icu_slibr156_bit BIT; +}; + +struct st_icu_slibr157_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr157 +{ + unsigned char BYTE; + struct st_icu_slibr157_bit BIT; +}; + +struct st_icu_slibr158_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr158 +{ + unsigned char BYTE; + struct st_icu_slibr158_bit BIT; +}; + +struct st_icu_slibr159_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr159 +{ + unsigned char BYTE; + struct st_icu_slibr159_bit BIT; +}; + +struct st_icu_slibr160_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr160 +{ + unsigned char BYTE; + struct st_icu_slibr160_bit BIT; +}; + +struct st_icu_slibr161_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr161 +{ + unsigned char BYTE; + struct st_icu_slibr161_bit BIT; +}; + +struct st_icu_slibr162_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr162 +{ + unsigned char BYTE; + struct st_icu_slibr162_bit BIT; +}; + +struct st_icu_slibr163_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr163 +{ + unsigned char BYTE; + struct st_icu_slibr163_bit BIT; +}; + +struct st_icu_slibr164_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr164 +{ + unsigned char BYTE; + struct st_icu_slibr164_bit BIT; +}; + +struct st_icu_slibr165_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr165 +{ + unsigned char BYTE; + struct st_icu_slibr165_bit BIT; +}; + +struct st_icu_slibr166_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr166 +{ + unsigned char BYTE; + struct st_icu_slibr166_bit BIT; +}; + +struct st_icu_slibr167_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr167 +{ + unsigned char BYTE; + struct st_icu_slibr167_bit BIT; +}; + +struct st_icu_slibr168_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr168 +{ + unsigned char BYTE; + struct st_icu_slibr168_bit BIT; +}; + +struct st_icu_slibr169_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr169 +{ + unsigned char BYTE; + struct st_icu_slibr169_bit BIT; +}; + +struct st_icu_slibr170_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr170 +{ + unsigned char BYTE; + struct st_icu_slibr170_bit BIT; +}; + +struct st_icu_slibr171_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr171 +{ + unsigned char BYTE; + struct st_icu_slibr171_bit BIT; +}; + +struct st_icu_slibr172_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr172 +{ + unsigned char BYTE; + struct st_icu_slibr172_bit BIT; +}; + +struct st_icu_slibr173_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr173 +{ + unsigned char BYTE; + struct st_icu_slibr173_bit BIT; +}; + +struct st_icu_slibr174_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr174 +{ + unsigned char BYTE; + struct st_icu_slibr174_bit BIT; +}; + +struct st_icu_slibr175_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr175 +{ + unsigned char BYTE; + struct st_icu_slibr175_bit BIT; +}; + +struct st_icu_slibr176_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr176 +{ + unsigned char BYTE; + struct st_icu_slibr176_bit BIT; +}; + +struct st_icu_slibr177_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr177 +{ + unsigned char BYTE; + struct st_icu_slibr177_bit BIT; +}; + +struct st_icu_slibr178_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr178 +{ + unsigned char BYTE; + struct st_icu_slibr178_bit BIT; +}; + +struct st_icu_slibr179_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr179 +{ + unsigned char BYTE; + struct st_icu_slibr179_bit BIT; +}; + +struct st_icu_slibr180_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr180 +{ + unsigned char BYTE; + struct st_icu_slibr180_bit BIT; +}; + +struct st_icu_slibr181_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr181 +{ + unsigned char BYTE; + struct st_icu_slibr181_bit BIT; +}; + +struct st_icu_slibr182_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr182 +{ + unsigned char BYTE; + struct st_icu_slibr182_bit BIT; +}; + +struct st_icu_slibr183_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr183 +{ + unsigned char BYTE; + struct st_icu_slibr183_bit BIT; +}; + +struct st_icu_slibr184_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr184 +{ + unsigned char BYTE; + struct st_icu_slibr184_bit BIT; +}; + +struct st_icu_slibr185_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr185 +{ + unsigned char BYTE; + struct st_icu_slibr185_bit BIT; +}; + +struct st_icu_slibr186_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr186 +{ + unsigned char BYTE; + struct st_icu_slibr186_bit BIT; +}; + +struct st_icu_slibr187_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr187 +{ + unsigned char BYTE; + struct st_icu_slibr187_bit BIT; +}; + +struct st_icu_slibr188_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr188 +{ + unsigned char BYTE; + struct st_icu_slibr188_bit BIT; +}; + +struct st_icu_slibr189_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr189 +{ + unsigned char BYTE; + struct st_icu_slibr189_bit BIT; +}; + +struct st_icu_slibr190_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr190 +{ + unsigned char BYTE; + struct st_icu_slibr190_bit BIT; +}; + +struct st_icu_slibr191_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr191 +{ + unsigned char BYTE; + struct st_icu_slibr191_bit BIT; +}; + +struct st_icu_slibr192_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr192 +{ + unsigned char BYTE; + struct st_icu_slibr192_bit BIT; +}; + +struct st_icu_slibr193_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr193 +{ + unsigned char BYTE; + struct st_icu_slibr193_bit BIT; +}; + +struct st_icu_slibr194_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr194 +{ + unsigned char BYTE; + struct st_icu_slibr194_bit BIT; +}; + +struct st_icu_slibr195_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr195 +{ + unsigned char BYTE; + struct st_icu_slibr195_bit BIT; +}; + +struct st_icu_slibr196_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr196 +{ + unsigned char BYTE; + struct st_icu_slibr196_bit BIT; +}; + +struct st_icu_slibr197_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr197 +{ + unsigned char BYTE; + struct st_icu_slibr197_bit BIT; +}; + +struct st_icu_slibr198_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr198 +{ + unsigned char BYTE; + struct st_icu_slibr198_bit BIT; +}; + +struct st_icu_slibr199_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr199 +{ + unsigned char BYTE; + struct st_icu_slibr199_bit BIT; +}; + +struct st_icu_slibr200_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr200 +{ + unsigned char BYTE; + struct st_icu_slibr200_bit BIT; +}; + +struct st_icu_slibr201_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr201 +{ + unsigned char BYTE; + struct st_icu_slibr201_bit BIT; +}; + +struct st_icu_slibr202_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr202 +{ + unsigned char BYTE; + struct st_icu_slibr202_bit BIT; +}; + +struct st_icu_slibr203_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr203 +{ + unsigned char BYTE; + struct st_icu_slibr203_bit BIT; +}; + +struct st_icu_slibr204_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr204 +{ + unsigned char BYTE; + struct st_icu_slibr204_bit BIT; +}; + +struct st_icu_slibr205_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr205 +{ + unsigned char BYTE; + struct st_icu_slibr205_bit BIT; +}; + +struct st_icu_slibr206_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr206 +{ + unsigned char BYTE; + struct st_icu_slibr206_bit BIT; +}; + +struct st_icu_slibr207_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr207 +{ + unsigned char BYTE; + struct st_icu_slibr207_bit BIT; +}; + +struct st_icu_piar0_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar0 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar0_bit BIT; +#endif +}; + +struct st_icu_piar1_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar1 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar1_bit BIT; +#endif +}; + +struct st_icu_piar2_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar2 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar2_bit BIT; +#endif +}; + +struct st_icu_piar3_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar3 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar3_bit BIT; +#endif +}; + +struct st_icu_piar4_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar4 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar4_bit BIT; +#endif +}; + +struct st_icu_piar5_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar5 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar5_bit BIT; +#endif +}; + +struct st_icu_piarb_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piarb +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piarb_bit BIT; +#endif +}; + +union un_icu_sliar208 +{ + unsigned char BYTE; +}; + +union un_icu_sliar209 +{ + unsigned char BYTE; +}; + +union un_icu_sliar210 +{ + unsigned char BYTE; +}; + +union un_icu_sliar211 +{ + unsigned char BYTE; +}; + +union un_icu_sliar212 +{ + unsigned char BYTE; +}; + +union un_icu_sliar213 +{ + unsigned char BYTE; +}; + +union un_icu_sliar214 +{ + unsigned char BYTE; +}; + +union un_icu_sliar215 +{ + unsigned char BYTE; +}; + +union un_icu_sliar216 +{ + unsigned char BYTE; +}; + +union un_icu_sliar217 +{ + unsigned char BYTE; +}; + +union un_icu_sliar218 +{ + unsigned char BYTE; +}; + +union un_icu_sliar219 +{ + unsigned char BYTE; +}; + +union un_icu_sliar220 +{ + unsigned char BYTE; +}; + +union un_icu_sliar221 +{ + unsigned char BYTE; +}; + +union un_icu_sliar222 +{ + unsigned char BYTE; +}; + +union un_icu_sliar223 +{ + unsigned char BYTE; +}; + +union un_icu_sliar224 +{ + unsigned char BYTE; +}; + +union un_icu_sliar225 +{ + unsigned char BYTE; +}; + +union un_icu_sliar226 +{ + unsigned char BYTE; +}; + +union un_icu_sliar227 +{ + unsigned char BYTE; +}; + +union un_icu_sliar228 +{ + unsigned char BYTE; +}; + +union un_icu_sliar229 +{ + unsigned char BYTE; +}; + +union un_icu_sliar230 +{ + unsigned char BYTE; +}; + +union un_icu_sliar231 +{ + unsigned char BYTE; +}; + +union un_icu_sliar232 +{ + unsigned char BYTE; +}; + +union un_icu_sliar233 +{ + unsigned char BYTE; +}; + +union un_icu_sliar234 +{ + unsigned char BYTE; +}; + +union un_icu_sliar235 +{ + unsigned char BYTE; +}; + +union un_icu_sliar236 +{ + unsigned char BYTE; +}; + +union un_icu_sliar237 +{ + unsigned char BYTE; +}; + +union un_icu_sliar238 +{ + unsigned char BYTE; +}; + +union un_icu_sliar239 +{ + unsigned char BYTE; +}; + +union un_icu_sliar240 +{ + unsigned char BYTE; +}; + +union un_icu_sliar241 +{ + unsigned char BYTE; +}; + +union un_icu_sliar242 +{ + unsigned char BYTE; +}; + +union un_icu_sliar243 +{ + unsigned char BYTE; +}; + +union un_icu_sliar244 +{ + unsigned char BYTE; +}; + +union un_icu_sliar245 +{ + unsigned char BYTE; +}; + +union un_icu_sliar246 +{ + unsigned char BYTE; +}; + +union un_icu_sliar247 +{ + unsigned char BYTE; +}; + +union un_icu_sliar248 +{ + unsigned char BYTE; +}; + +union un_icu_sliar249 +{ + unsigned char BYTE; +}; + +union un_icu_sliar250 +{ + unsigned char BYTE; +}; + +union un_icu_sliar251 +{ + unsigned char BYTE; +}; + +union un_icu_sliar252 +{ + unsigned char BYTE; +}; + +union un_icu_sliar253 +{ + unsigned char BYTE; +}; + +union un_icu_sliar254 +{ + unsigned char BYTE; +}; + +union un_icu_sliar255 +{ + unsigned char BYTE; +}; + +struct st_icu_sliprcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WPRC : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char WPRC : 1; +#endif +}; + +union un_icu_sliprcr +{ + unsigned char BYTE; + struct st_icu_sliprcr_bit BIT; +}; + +struct st_icu_slexdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SELEXD0 : 1; + unsigned char SELEXD1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SELEXD1 : 1; + unsigned char SELEXD0 : 1; +#endif +}; + +union un_icu_slexdr +{ + unsigned char BYTE; + struct st_icu_slexdr_bit BIT; +}; + +struct st_rtc_r64cnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif +}; + +union un_rtc_r64cnt +{ + unsigned char BYTE; + struct st_rtc_r64cnt_bit BIT; +}; + +struct st_rtc_rseccnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccnt +{ + unsigned char BYTE; + struct st_rtc_rseccnt_bit BIT; +}; + +struct st_rtc_bcnt0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt0 +{ + unsigned char BYTE; + struct st_rtc_bcnt0_bit BIT; +}; + +struct st_rtc_rmincnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincnt +{ + unsigned char BYTE; + struct st_rtc_rmincnt_bit BIT; +}; + +struct st_rtc_bcnt1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt1 +{ + unsigned char BYTE; + struct st_rtc_bcnt1_bit BIT; +}; + +struct st_rtc_rhrcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcnt +{ + unsigned char BYTE; + struct st_rtc_rhrcnt_bit BIT; +}; + +struct st_rtc_bcnt2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt2 +{ + unsigned char BYTE; + struct st_rtc_bcnt2_bit BIT; +}; + +struct st_rtc_rwkcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif +}; + +union un_rtc_rwkcnt +{ + unsigned char BYTE; + struct st_rtc_rwkcnt_bit BIT; +}; + +struct st_rtc_bcnt3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt3 +{ + unsigned char BYTE; + struct st_rtc_bcnt3_bit BIT; +}; + +struct st_rtc_rdaycnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycnt +{ + unsigned char BYTE; + struct st_rtc_rdaycnt_bit BIT; +}; + +struct st_rtc_rmoncnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncnt +{ + unsigned char BYTE; + struct st_rtc_rmoncnt_bit BIT; +}; + +struct st_rtc_ryrcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif +}; + +union un_rtc_ryrcnt +{ + unsigned short WORD; + struct st_rtc_ryrcnt_bit BIT; +}; + +struct st_rtc_rsecar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rsecar +{ + unsigned char BYTE; + struct st_rtc_rsecar_bit BIT; +}; + +struct st_rtc_bcnt0ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt0ar +{ + unsigned char BYTE; + struct st_rtc_bcnt0ar_bit BIT; +}; + +struct st_rtc_rminar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rminar +{ + unsigned char BYTE; + struct st_rtc_rminar_bit BIT; +}; + +struct st_rtc_bcnt1ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt1ar +{ + unsigned char BYTE; + struct st_rtc_bcnt1ar_bit BIT; +}; + +struct st_rtc_rhrar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrar +{ + unsigned char BYTE; + struct st_rtc_rhrar_bit BIT; +}; + +struct st_rtc_bcnt2ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt2ar +{ + unsigned char BYTE; + struct st_rtc_bcnt2ar_bit BIT; +}; + +struct st_rtc_rwkar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif +}; + +union un_rtc_rwkar +{ + unsigned char BYTE; + struct st_rtc_rwkar_bit BIT; +}; + +struct st_rtc_bcnt3ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt3ar +{ + unsigned char BYTE; + struct st_rtc_bcnt3ar_bit BIT; +}; + +struct st_rtc_rdayar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdayar +{ + unsigned char BYTE; + struct st_rtc_rdayar_bit BIT; +}; + +struct st_rtc_bcnt0aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt0aer +{ + unsigned char BYTE; + struct st_rtc_bcnt0aer_bit BIT; +}; + +struct st_rtc_rmonar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmonar +{ + unsigned char BYTE; + struct st_rtc_rmonar_bit BIT; +}; + +struct st_rtc_bcnt1aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt1aer +{ + unsigned char BYTE; + struct st_rtc_bcnt1aer_bit BIT; +}; + +struct st_rtc_ryrar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif +}; + +union un_rtc_ryrar +{ + unsigned short WORD; + struct st_rtc_ryrar_bit BIT; +}; + +struct st_rtc_bcnt2aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif +}; + +union un_rtc_bcnt2aer +{ + unsigned short WORD; + struct st_rtc_bcnt2aer_bit BIT; +}; + +struct st_rtc_bcnt3aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt3aer +{ + unsigned char BYTE; + struct st_rtc_bcnt3aer_bit BIT; +}; + +struct st_rtc_ryraren_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif +}; + +union un_rtc_ryraren +{ + unsigned char BYTE; + struct st_rtc_ryraren_bit BIT; +}; + +struct st_rtc_rcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif +}; + +union un_rtc_rcr1 +{ + unsigned char BYTE; + struct st_rtc_rcr1_bit BIT; +}; + +struct st_rtc_rcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif +}; + +union un_rtc_rcr2 +{ + unsigned char BYTE; + struct st_rtc_rcr2_bit BIT; +}; + +struct st_rtc_rcr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RCKSEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RCKSEL : 1; +#endif +}; + +union un_rtc_rcr4 +{ + unsigned char BYTE; + struct st_rtc_rcr4_bit BIT; +}; + +struct st_rtc_rfrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RFC : 1; +#endif +}; + +union un_rtc_rfrh +{ + unsigned short WORD; + struct st_rtc_rfrh_bit BIT; +}; + +struct st_rtc_rfrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 16; +#else + unsigned short RFC : 16; +#endif +}; + +union un_rtc_rfrl +{ + unsigned short WORD; + struct st_rtc_rfrl_bit BIT; +}; + +struct st_rtc_radj_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif +}; + +union un_rtc_radj +{ + unsigned char BYTE; + struct st_rtc_radj_bit BIT; +}; + +struct st_rtc_rtccr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr0 +{ + unsigned char BYTE; + struct st_rtc_rtccr0_bit BIT; +}; + +struct st_rtc_rtccr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr1 +{ + unsigned char BYTE; + struct st_rtc_rtccr1_bit BIT; +}; + +struct st_rtc_rtccr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr2 +{ + unsigned char BYTE; + struct st_rtc_rtccr2_bit BIT; +}; + +struct st_rtc_rseccp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp0 +{ + unsigned char BYTE; + struct st_rtc_rseccp0_bit BIT; +}; + +struct st_rtc_bcnt0cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt0cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp0_bit BIT; +}; + +struct st_rtc_rmincp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp0 +{ + unsigned char BYTE; + struct st_rtc_rmincp0_bit BIT; +}; + +struct st_rtc_bcnt1cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt1cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp0_bit BIT; +}; + +struct st_rtc_rhrcp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp0 +{ + unsigned char BYTE; + struct st_rtc_rhrcp0_bit BIT; +}; + +struct st_rtc_bcnt2cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt2cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp0_bit BIT; +}; + +struct st_rtc_rdaycp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp0 +{ + unsigned char BYTE; + struct st_rtc_rdaycp0_bit BIT; +}; + +struct st_rtc_bcnt3cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt3cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp0_bit BIT; +}; + +struct st_rtc_rmoncp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp0 +{ + unsigned char BYTE; + struct st_rtc_rmoncp0_bit BIT; +}; + +struct st_rtc_rseccp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp1 +{ + unsigned char BYTE; + struct st_rtc_rseccp1_bit BIT; +}; + +struct st_rtc_bcnt0cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt0cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp1_bit BIT; +}; + +struct st_rtc_rmincp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp1 +{ + unsigned char BYTE; + struct st_rtc_rmincp1_bit BIT; +}; + +struct st_rtc_bcnt1cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt1cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp1_bit BIT; +}; + +struct st_rtc_rhrcp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp1 +{ + unsigned char BYTE; + struct st_rtc_rhrcp1_bit BIT; +}; + +struct st_rtc_bcnt2cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt2cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp1_bit BIT; +}; + +struct st_rtc_rdaycp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp1 +{ + unsigned char BYTE; + struct st_rtc_rdaycp1_bit BIT; +}; + +struct st_rtc_bcnt3cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt3cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp1_bit BIT; +}; + +struct st_rtc_rmoncp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp1 +{ + unsigned char BYTE; + struct st_rtc_rmoncp1_bit BIT; +}; + +struct st_rtc_rseccp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp2 +{ + unsigned char BYTE; + struct st_rtc_rseccp2_bit BIT; +}; + +struct st_rtc_bcnt0cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt0cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp2_bit BIT; +}; + +struct st_rtc_rmincp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp2 +{ + unsigned char BYTE; + struct st_rtc_rmincp2_bit BIT; +}; + +struct st_rtc_bcnt1cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt1cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp2_bit BIT; +}; + +struct st_rtc_rhrcp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp2 +{ + unsigned char BYTE; + struct st_rtc_rhrcp2_bit BIT; +}; + +struct st_rtc_bcnt2cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt2cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp2_bit BIT; +}; + +struct st_rtc_rdaycp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp2 +{ + unsigned char BYTE; + struct st_rtc_rdaycp2_bit BIT; +}; + +struct st_rtc_bcnt3cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt3cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp2_bit BIT; +}; + +struct st_rtc_rmoncp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp2 +{ + unsigned char BYTE; + struct st_rtc_rmoncp2_bit BIT; +}; + +struct st_mpc_p00pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p00pfs +{ + unsigned char BYTE; + struct st_mpc_p00pfs_bit BIT; +}; + +struct st_mpc_p01pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p01pfs +{ + unsigned char BYTE; + struct st_mpc_p01pfs_bit BIT; +}; + +struct st_mpc_pfcse_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif +}; + +union un_mpc_pfcse +{ + unsigned char BYTE; + struct st_mpc_pfcse_bit BIT; +}; + +struct st_mpc_pfcss0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0S : 1; + unsigned char : 1; + unsigned char CS1S : 2; + unsigned char CS2S : 2; + unsigned char CS3S : 2; +#else + unsigned char CS3S : 2; + unsigned char CS2S : 2; + unsigned char CS1S : 2; + unsigned char : 1; + unsigned char CS0S : 1; +#endif +}; + +union un_mpc_pfcss0 +{ + unsigned char BYTE; + struct st_mpc_pfcss0_bit BIT; +}; + +struct st_mpc_pfcss1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS4S : 2; + unsigned char CS5S : 2; + unsigned char CS6S : 2; + unsigned char CS7S : 2; +#else + unsigned char CS7S : 2; + unsigned char CS6S : 2; + unsigned char CS5S : 2; + unsigned char CS4S : 2; +#endif +}; + +union un_mpc_pfcss1 +{ + unsigned char BYTE; + struct st_mpc_pfcss1_bit BIT; +}; + +struct st_mpc_pfa0e0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif +}; + +union un_mpc_pfa0e0 +{ + unsigned char BYTE; + struct st_mpc_pfa0e0_bit BIT; +}; + +struct st_mpc_pfa0e1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif +}; + +union un_mpc_pfa0e1 +{ + unsigned char BYTE; + struct st_mpc_pfa0e1_bit BIT; +}; + +struct st_mpc_pfbcr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char ADRHMS : 1; + unsigned char ADRHMS2 : 1; + unsigned char BCLKO : 1; + unsigned char DHE : 1; + unsigned char DH32E : 1; + unsigned char WR1BC1E : 1; + unsigned char WR32BC32E : 1; +#else + unsigned char WR32BC32E : 1; + unsigned char WR1BC1E : 1; + unsigned char DH32E : 1; + unsigned char DHE : 1; + unsigned char BCLKO : 1; + unsigned char ADRHMS2 : 1; + unsigned char ADRHMS : 1; + unsigned char ADRLE : 1; +#endif +}; + +union un_mpc_pfbcr0 +{ + unsigned char BYTE; + struct st_mpc_pfbcr0_bit BIT; +}; + +struct st_mpc_pfbcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char ALES : 1; + unsigned char MDSDE : 1; + unsigned char : 1; + unsigned char DQM1E : 1; + unsigned char SDCLKE : 1; +#else + unsigned char SDCLKE : 1; + unsigned char DQM1E : 1; + unsigned char : 1; + unsigned char MDSDE : 1; + unsigned char ALES : 1; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif +}; + +union un_mpc_pfbcr1 +{ + unsigned char BYTE; + struct st_mpc_pfbcr1_bit BIT; +}; + +struct st_mpc_pfbcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D0S : 2; + unsigned char D1S : 2; + unsigned char D2S : 2; + unsigned char D3S : 2; +#else + unsigned char D3S : 2; + unsigned char D2S : 2; + unsigned char D1S : 2; + unsigned char D0S : 2; +#endif +}; + +union un_mpc_pfbcr2 +{ + unsigned char BYTE; + struct st_mpc_pfbcr2_bit BIT; +}; + +struct st_mpc_pfbcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLHS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DLHS : 1; +#endif +}; + +union un_mpc_pfbcr3 +{ + unsigned char BYTE; + struct st_mpc_pfbcr3_bit BIT; +}; + +struct st_mpc_pfenet_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char PHYMODE0 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PHYMODE0 : 1; + unsigned char : 4; +#endif +}; + +union un_mpc_pfenet +{ + unsigned char BYTE; + struct st_mpc_pfenet_bit BIT; +}; + +struct st_mpc_p02pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p02pfs +{ + unsigned char BYTE; + struct st_mpc_p02pfs_bit BIT; +}; + +struct st_mpc_p03pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p03pfs +{ + unsigned char BYTE; + struct st_mpc_p03pfs_bit BIT; +}; + +struct st_mpc_p05pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p05pfs +{ + unsigned char BYTE; + struct st_mpc_p05pfs_bit BIT; +}; + +struct st_mpc_p07pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p07pfs +{ + unsigned char BYTE; + struct st_mpc_p07pfs_bit BIT; +}; + +struct st_mpc_p10pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p10pfs +{ + unsigned char BYTE; + struct st_mpc_p10pfs_bit BIT; +}; + +struct st_mpc_p11pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p11pfs +{ + unsigned char BYTE; + struct st_mpc_p11pfs_bit BIT; +}; + +struct st_system_mdmonr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif +}; + +struct st_mpc_p12pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p12pfs +{ + unsigned char BYTE; + struct st_mpc_p12pfs_bit BIT; +}; + +struct st_mpc_p13pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p13pfs +{ + unsigned char BYTE; + struct st_mpc_p13pfs_bit BIT; +}; + +struct st_mpc_p14pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p14pfs +{ + unsigned char BYTE; + struct st_mpc_p14pfs_bit BIT; +}; + +struct st_mpc_p15pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p15pfs +{ + unsigned char BYTE; + struct st_mpc_p15pfs_bit BIT; +}; + +struct st_mpc_p16pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p16pfs +{ + unsigned char BYTE; + struct st_mpc_p16pfs_bit BIT; +}; + +struct st_mpc_p17pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p17pfs +{ + unsigned char BYTE; + struct st_mpc_p17pfs_bit BIT; +}; + +struct st_mpc_p20pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p20pfs +{ + unsigned char BYTE; + struct st_mpc_p20pfs_bit BIT; +}; + +struct st_mpc_p21pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p21pfs +{ + unsigned char BYTE; + struct st_mpc_p21pfs_bit BIT; +}; + +struct st_mpc_p22pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p22pfs +{ + unsigned char BYTE; + struct st_mpc_p22pfs_bit BIT; +}; + +struct st_mpc_p23pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p23pfs +{ + unsigned char BYTE; + struct st_mpc_p23pfs_bit BIT; +}; + +struct st_mpc_p24pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p24pfs +{ + unsigned char BYTE; + struct st_mpc_p24pfs_bit BIT; +}; + +struct st_mpc_p25pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p25pfs +{ + unsigned char BYTE; + struct st_mpc_p25pfs_bit BIT; +}; + +struct st_mpc_p26pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p26pfs +{ + unsigned char BYTE; + struct st_mpc_p26pfs_bit BIT; +}; + +struct st_mpc_p27pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p27pfs +{ + unsigned char BYTE; + struct st_mpc_p27pfs_bit BIT; +}; + +struct st_mpc_p30pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p30pfs +{ + unsigned char BYTE; + struct st_mpc_p30pfs_bit BIT; +}; + +struct st_mpc_p31pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p31pfs +{ + unsigned char BYTE; + struct st_mpc_p31pfs_bit BIT; +}; + +struct st_mpc_p32pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p32pfs +{ + unsigned char BYTE; + struct st_mpc_p32pfs_bit BIT; +}; + +struct st_mpc_p33pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p33pfs +{ + unsigned char BYTE; + struct st_mpc_p33pfs_bit BIT; +}; + +struct st_mpc_p34pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p34pfs +{ + unsigned char BYTE; + struct st_mpc_p34pfs_bit BIT; +}; + +struct st_mpc_p40pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p40pfs +{ + unsigned char BYTE; + struct st_mpc_p40pfs_bit BIT; +}; + +struct st_mpc_p41pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p41pfs +{ + unsigned char BYTE; + struct st_mpc_p41pfs_bit BIT; +}; + +struct st_mpc_p42pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p42pfs +{ + unsigned char BYTE; + struct st_mpc_p42pfs_bit BIT; +}; + +struct st_mpc_p43pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p43pfs +{ + unsigned char BYTE; + struct st_mpc_p43pfs_bit BIT; +}; + +struct st_mpc_p44pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p44pfs +{ + unsigned char BYTE; + struct st_mpc_p44pfs_bit BIT; +}; + +struct st_mpc_p45pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p45pfs +{ + unsigned char BYTE; + struct st_mpc_p45pfs_bit BIT; +}; + +struct st_mpc_p46pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p46pfs +{ + unsigned char BYTE; + struct st_mpc_p46pfs_bit BIT; +}; + +struct st_mpc_p47pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p47pfs +{ + unsigned char BYTE; + struct st_mpc_p47pfs_bit BIT; +}; + +struct st_mpc_p50pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p50pfs +{ + unsigned char BYTE; + struct st_mpc_p50pfs_bit BIT; +}; + +struct st_mpc_p51pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p51pfs +{ + unsigned char BYTE; + struct st_mpc_p51pfs_bit BIT; +}; + +struct st_mpc_p52pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p52pfs +{ + unsigned char BYTE; + struct st_mpc_p52pfs_bit BIT; +}; + +struct st_mpc_p54pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p54pfs +{ + unsigned char BYTE; + struct st_mpc_p54pfs_bit BIT; +}; + +struct st_mpc_p55pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p55pfs +{ + unsigned char BYTE; + struct st_mpc_p55pfs_bit BIT; +}; + +struct st_mpc_p56pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p56pfs +{ + unsigned char BYTE; + struct st_mpc_p56pfs_bit BIT; +}; + +struct st_mpc_p57pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p57pfs +{ + unsigned char BYTE; + struct st_mpc_p57pfs_bit BIT; +}; + +struct st_mpc_p66pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p66pfs +{ + unsigned char BYTE; + struct st_mpc_p66pfs_bit BIT; +}; + +struct st_mpc_p67pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p67pfs +{ + unsigned char BYTE; + struct st_mpc_p67pfs_bit BIT; +}; + +struct st_mpc_p71pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p71pfs +{ + unsigned char BYTE; + struct st_mpc_p71pfs_bit BIT; +}; + +struct st_mpc_p72pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p72pfs +{ + unsigned char BYTE; + struct st_mpc_p72pfs_bit BIT; +}; + +struct st_mpc_p73pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p73pfs +{ + unsigned char BYTE; + struct st_mpc_p73pfs_bit BIT; +}; + +struct st_mpc_p74pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p74pfs +{ + unsigned char BYTE; + struct st_mpc_p74pfs_bit BIT; +}; + +struct st_mpc_p75pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p75pfs +{ + unsigned char BYTE; + struct st_mpc_p75pfs_bit BIT; +}; + +struct st_mpc_p76pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p76pfs +{ + unsigned char BYTE; + struct st_mpc_p76pfs_bit BIT; +}; + +struct st_mpc_p77pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p77pfs +{ + unsigned char BYTE; + struct st_mpc_p77pfs_bit BIT; +}; + +struct st_mpc_p80pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p80pfs +{ + unsigned char BYTE; + struct st_mpc_p80pfs_bit BIT; +}; + +struct st_mpc_p81pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p81pfs +{ + unsigned char BYTE; + struct st_mpc_p81pfs_bit BIT; +}; + +struct st_mpc_p82pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p82pfs +{ + unsigned char BYTE; + struct st_mpc_p82pfs_bit BIT; +}; + +struct st_mpc_p83pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p83pfs +{ + unsigned char BYTE; + struct st_mpc_p83pfs_bit BIT; +}; + +struct st_mpc_p84pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p84pfs +{ + unsigned char BYTE; + struct st_mpc_p84pfs_bit BIT; +}; + +struct st_mpc_p85pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p85pfs +{ + unsigned char BYTE; + struct st_mpc_p85pfs_bit BIT; +}; + +struct st_mpc_p86pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p86pfs +{ + unsigned char BYTE; + struct st_mpc_p86pfs_bit BIT; +}; + +struct st_mpc_p87pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p87pfs +{ + unsigned char BYTE; + struct st_mpc_p87pfs_bit BIT; +}; + +struct st_mpc_p90pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p90pfs +{ + unsigned char BYTE; + struct st_mpc_p90pfs_bit BIT; +}; + +struct st_mpc_p91pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p91pfs +{ + unsigned char BYTE; + struct st_mpc_p91pfs_bit BIT; +}; + +struct st_mpc_p92pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p92pfs +{ + unsigned char BYTE; + struct st_mpc_p92pfs_bit BIT; +}; + +struct st_mpc_p93pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p93pfs +{ + unsigned char BYTE; + struct st_mpc_p93pfs_bit BIT; +}; + +struct st_mpc_pa0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa0pfs +{ + unsigned char BYTE; + struct st_mpc_pa0pfs_bit BIT; +}; + +struct st_mpc_pa1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa1pfs +{ + unsigned char BYTE; + struct st_mpc_pa1pfs_bit BIT; +}; + +struct st_mpc_pa2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa2pfs +{ + unsigned char BYTE; + struct st_mpc_pa2pfs_bit BIT; +}; + +struct st_mpc_pa3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa3pfs +{ + unsigned char BYTE; + struct st_mpc_pa3pfs_bit BIT; +}; + +struct st_mpc_pa4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa4pfs +{ + unsigned char BYTE; + struct st_mpc_pa4pfs_bit BIT; +}; + +struct st_mpc_pa5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa5pfs +{ + unsigned char BYTE; + struct st_mpc_pa5pfs_bit BIT; +}; + +struct st_mpc_pa6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; +union un_mpc_pa6pfs +{ + unsigned char BYTE; + struct st_mpc_pa6pfs_bit BIT; +}; + +struct st_mpc_pa7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa7pfs +{ + unsigned char BYTE; + struct st_mpc_pa7pfs_bit BIT; +}; + +struct st_mpc_pb0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb0pfs +{ + unsigned char BYTE; + struct st_mpc_pb0pfs_bit BIT; +}; + +struct st_mpc_pb1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb1pfs +{ + unsigned char BYTE; + struct st_mpc_pb1pfs_bit BIT; +}; + +struct st_mpc_pb2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb2pfs +{ + unsigned char BYTE; + struct st_mpc_pb2pfs_bit BIT; +}; + +struct st_mpc_pb3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb3pfs +{ + unsigned char BYTE; + struct st_mpc_pb3pfs_bit BIT; +}; + +struct st_mpc_pb4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb4pfs +{ + unsigned char BYTE; + struct st_mpc_pb4pfs_bit BIT; +}; + +struct st_mpc_pb5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb5pfs +{ + unsigned char BYTE; + struct st_mpc_pb5pfs_bit BIT; +}; + +struct st_mpc_pb6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb6pfs +{ + unsigned char BYTE; + struct st_mpc_pb6pfs_bit BIT; +}; + +struct st_mpc_pb7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb7pfs +{ + unsigned char BYTE; + struct st_mpc_pb7pfs_bit BIT; +}; + +struct st_mpc_pc0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc0pfs +{ + unsigned char BYTE; + struct st_mpc_pc0pfs_bit BIT; +}; + +struct st_mpc_pc1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc1pfs +{ + unsigned char BYTE; + struct st_mpc_pc1pfs_bit BIT; +}; + +struct st_mpc_pc2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc2pfs +{ + unsigned char BYTE; + struct st_mpc_pc2pfs_bit BIT; +}; + +struct st_mpc_pc3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc3pfs +{ + unsigned char BYTE; + struct st_mpc_pc3pfs_bit BIT; +}; + +struct st_mpc_pc4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc4pfs +{ + unsigned char BYTE; + struct st_mpc_pc4pfs_bit BIT; +}; + +struct st_mpc_pc5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc5pfs +{ + unsigned char BYTE; + struct st_mpc_pc5pfs_bit BIT; +}; + +struct st_mpc_pc6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc6pfs +{ + unsigned char BYTE; + struct st_mpc_pc6pfs_bit BIT; +}; + +struct st_mpc_pc7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc7pfs +{ + unsigned char BYTE; + struct st_mpc_pc7pfs_bit BIT; +}; + +struct st_mpc_pd0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd0pfs +{ + unsigned char BYTE; + struct st_mpc_pd0pfs_bit BIT; +}; + +struct st_mpc_pd1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd1pfs +{ + unsigned char BYTE; + struct st_mpc_pd1pfs_bit BIT; +}; + +struct st_mpc_pd2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd2pfs +{ + unsigned char BYTE; + struct st_mpc_pd2pfs_bit BIT; +}; + +struct st_mpc_pd3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd3pfs +{ + unsigned char BYTE; + struct st_mpc_pd3pfs_bit BIT; +}; + +struct st_mpc_pd4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd4pfs +{ + unsigned char BYTE; + struct st_mpc_pd4pfs_bit BIT; +}; + +struct st_mpc_pd5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd5pfs +{ + unsigned char BYTE; + struct st_mpc_pd5pfs_bit BIT; +}; + +struct st_mpc_pd6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd6pfs +{ + unsigned char BYTE; + struct st_mpc_pd6pfs_bit BIT; +}; + +struct st_mpc_pd7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd7pfs +{ + unsigned char BYTE; + struct st_mpc_pd7pfs_bit BIT; +}; + +struct st_mpc_pe0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe0pfs +{ + unsigned char BYTE; + struct st_mpc_pe0pfs_bit BIT; +}; + +struct st_mpc_pe1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe1pfs +{ + unsigned char BYTE; + struct st_mpc_pe1pfs_bit BIT; +}; + +struct st_mpc_pe2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe2pfs +{ + unsigned char BYTE; + struct st_mpc_pe2pfs_bit BIT; +}; + +struct st_mpc_pe3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe3pfs +{ + unsigned char BYTE; + struct st_mpc_pe3pfs_bit BIT; +}; + +struct st_mpc_pe4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe4pfs +{ + unsigned char BYTE; + struct st_mpc_pe4pfs_bit BIT; +}; + +struct st_mpc_pe5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe5pfs +{ + unsigned char BYTE; + struct st_mpc_pe5pfs_bit BIT; +}; + +struct st_mpc_pe6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe6pfs +{ + unsigned char BYTE; + struct st_mpc_pe6pfs_bit BIT; +}; + +struct st_mpc_pe7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe7pfs +{ + unsigned char BYTE; + struct st_mpc_pe7pfs_bit BIT; +}; + +struct st_mpc_pf0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf0pfs +{ + unsigned char BYTE; + struct st_mpc_pf0pfs_bit BIT; +}; + +struct st_mpc_pf1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf1pfs +{ + unsigned char BYTE; + struct st_mpc_pf1pfs_bit BIT; +}; + +struct st_mpc_pf2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf2pfs +{ + unsigned char BYTE; + struct st_mpc_pf2pfs_bit BIT; +}; + +struct st_mpc_pf5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_pf5pfs +{ + unsigned char BYTE; + struct st_mpc_pf5pfs_bit BIT; +}; + +struct st_mpc_pj0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj0pfs +{ + unsigned char BYTE; + struct st_mpc_pj0pfs_bit BIT; +}; + +struct st_mpc_pj1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj1pfs +{ + unsigned char BYTE; + struct st_mpc_pj1pfs_bit BIT; +}; + +struct st_mpc_pj2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj2pfs +{ + unsigned char BYTE; + struct st_mpc_pj2pfs_bit BIT; +}; + +struct st_mpc_pj3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj3pfs +{ + unsigned char BYTE; + struct st_mpc_pj3pfs_bit BIT; +}; + +struct st_mpc_pj5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj5pfs +{ + unsigned char BYTE; + struct st_mpc_pj5pfs_bit BIT; +}; + +union un_system_mdmonr +{ + unsigned short WORD; + struct st_system_mdmonr_bit BIT; +}; + +struct st_system_syscr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif +}; + +union un_system_syscr0 +{ + unsigned short WORD; + struct st_system_syscr0_bit BIT; +}; + +struct st_system_syscr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 6; + unsigned short SBYRAME : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SBYRAME : 1; + unsigned short : 6; + unsigned short RAME : 1; +#endif +}; + +union un_system_syscr1 +{ + unsigned short WORD; + struct st_system_syscr1_bit BIT; +}; + +struct st_system_sbycr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif +}; + +union un_system_sbycr +{ + unsigned short WORD; + struct st_system_sbycr_bit BIT; +}; + +struct st_system_mstpcra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPA0 : 1; + unsigned long MSTPA1 : 1; + unsigned long : 2; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA11 : 1; + unsigned long : 1; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 4; + unsigned long MSTPA24 : 1; + unsigned long : 2; + unsigned long MSTPA27 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA29 : 1; + unsigned long : 1; + unsigned long ACSE : 1; +#else + unsigned long ACSE : 1; + unsigned long : 1; + unsigned long MSTPA29 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA27 : 1; + unsigned long : 2; + unsigned long MSTPA24 : 1; + unsigned long : 4; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 1; + unsigned long MSTPA11 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 2; + unsigned long MSTPA1 : 1; + unsigned long MSTPA0 : 1; +#endif +}; + +union un_system_mstpcra +{ + unsigned long LONG; + struct st_system_mstpcra_bit BIT; +}; + +struct st_system_mstpcrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long MSTPB1 : 1; + unsigned long : 2; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB8 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 5; + unsigned long MSTPB15 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB15 : 1; + unsigned long : 5; + unsigned long MSTPB9 : 1; + unsigned long MSTPB8 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 2; + unsigned long MSTPB1 : 1; + unsigned long MSTPB0 : 1; +#endif +}; + +union un_system_mstpcrb +{ + unsigned long LONG; + struct st_system_mstpcrb_bit BIT; +}; + +struct st_system_mstpcrc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 1; + unsigned long MSTPC2 : 1; + unsigned long : 4; + unsigned long MSTPC7 : 1; + unsigned long : 9; + unsigned long MSTPC17 : 1; + unsigned long : 1; + unsigned long MSTPC19 : 1; + unsigned long : 2; + unsigned long MSTPC22 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC22 : 1; + unsigned long : 2; + unsigned long MSTPC19 : 1; + unsigned long : 1; + unsigned long MSTPC17 : 1; + unsigned long : 9; + unsigned long MSTPC7 : 1; + unsigned long : 4; + unsigned long MSTPC2 : 1; + unsigned long : 1; + unsigned long MSTPC0 : 1; +#endif +}; + +union un_system_mstpcrc +{ + unsigned long LONG; + struct st_system_mstpcrc_bit BIT; +}; + +struct st_system_mstpcrd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPD0 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD7 : 1; + unsigned long : 5; + unsigned long MSTPD13 : 1; + unsigned long : 5; + unsigned long MSTPD19 : 1; + unsigned long : 1; + unsigned long MSTPD21 : 1; + unsigned long : 5; + unsigned long MSTPD27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPD27 : 1; + unsigned long : 5; + unsigned long MSTPD21 : 1; + unsigned long : 1; + unsigned long MSTPD19 : 1; + unsigned long : 5; + unsigned long MSTPD13 : 1; + unsigned long : 5; + unsigned long MSTPD7 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD0 : 1; +#endif +}; + +union un_system_mstpcrd +{ + unsigned long LONG; + struct st_system_mstpcrd_bit BIT; +}; + +struct st_system_sckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long PCKC : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 2; + unsigned long PSTOP0 : 1; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long PSTOP0 : 1; + unsigned long : 2; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long PCKC : 4; + unsigned long PCKD : 4; +#endif +}; + +union un_system_sckcr +{ + unsigned long LONG; + struct st_system_sckcr_bit BIT; +}; + +struct st_system_sckcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short UCK : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short UCK : 4; + unsigned short : 4; +#endif +}; + +union un_system_sckcr2 +{ + unsigned short WORD; + struct st_system_sckcr2_bit BIT; +}; + +struct st_system_sckcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif +}; + +union un_system_sckcr3 +{ + unsigned short WORD; + struct st_system_sckcr3_bit BIT; +}; + +struct st_system_pllcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 2; + unsigned short PLLSRCSEL : 1; + unsigned short : 3; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 3; + unsigned short PLLSRCSEL : 1; + unsigned short : 2; + unsigned short PLIDIV : 2; +#endif +}; + +union un_system_pllcr +{ + unsigned short WORD; + struct st_system_pllcr_bit BIT; +}; + +struct st_system_pllcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif +}; + +union un_system_pllcr2 +{ + unsigned char BYTE; + struct st_system_pllcr2_bit BIT; +}; + +struct st_system_bckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif +}; + +union un_system_bckcr +{ + unsigned char BYTE; + struct st_system_bckcr_bit BIT; +}; + +struct st_system_mosccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif +}; + +union un_system_mosccr +{ + unsigned char BYTE; + struct st_system_mosccr_bit BIT; +}; + +struct st_system_sosccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif +}; + +union un_system_sosccr +{ + unsigned char BYTE; + struct st_system_sosccr_bit BIT; +}; + +struct st_system_lococcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif +}; + +union un_system_lococr +{ + unsigned char BYTE; + struct st_system_lococcr_bit BIT; +}; + +struct st_system_ilococr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif +}; + +union un_system_ilococr +{ + unsigned char BYTE; + struct st_system_ilococr_bit BIT; +}; + +struct st_system_hococr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif +}; + +union un_system_hococr +{ + unsigned char BYTE; + struct st_system_hococr_bit BIT; +}; + +struct st_system_hococr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif +}; + +union un_system_hococr2 +{ + unsigned char BYTE; + struct st_system_hococr2_bit BIT; +}; + +struct st_system_oscovfsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char SOOVF : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char ILCOVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILCOVF : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char SOOVF : 1; + unsigned char MOOVF : 1; +#endif +}; + +union un_system_oscovfsr +{ + unsigned char BYTE; + struct st_system_oscovfsr_bit BIT; +}; + +struct st_system_ostdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif +}; + +union un_system_ostdcr +{ + unsigned char BYTE; + struct st_system_ostdcr_bit BIT; +}; + +struct st_system_ostdsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif +}; + +union un_system_ostdsr +{ + unsigned char BYTE; + struct st_system_ostdsr_bit BIT; +}; + +struct st_system_opccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif +}; + +struct st_system_rstckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif +}; + +union un_system_rstckcr +{ + unsigned char BYTE; + struct st_system_rstckcr_bit BIT; +}; + +union un_system_opccr +{ + unsigned char BYTE; + struct st_system_opccr_bit BIT; +}; + +struct st_system_moscwtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 8; +#else + unsigned char MSTS : 8; +#endif +}; + +union un_system_moscwtcr +{ + unsigned char BYTE; + struct st_system_moscwtcr_bit BIT; +}; + +struct st_system_soscwtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSTS : 8; +#else + unsigned char SSTS : 8; +#endif +}; + +union un_system_soscwtcr +{ + unsigned char BYTE; + struct st_system_soscwtcr_bit BIT; +}; + +struct st_system_rstsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif +}; + +union un_system_rstsr2 +{ + unsigned char BYTE; + struct st_system_rstsr2_bit BIT; +}; + +struct st_system_lvd1cr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif +}; + +union un_system_lvd1cr1 +{ + unsigned char BYTE; + struct st_system_lvd1cr1_bit BIT; +}; + +struct st_system_lvd1sr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif +}; + +union un_system_lvd1sr +{ + unsigned char BYTE; + struct st_system_lvd1sr_bit BIT; +}; + +struct st_system_lvd2cr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif +}; + +union un_system_lvd2cr1 +{ + unsigned char BYTE; + struct st_system_lvd2cr1_bit BIT; +}; + +struct st_system_lvd2sr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif +}; + +union un_system_lvd2sr +{ + unsigned char BYTE; + struct st_system_lvd2sr_bit BIT; +}; + +struct st_system_prcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif +}; + +union un_system_prcr +{ + unsigned short WORD; + struct st_system_prcr_bit BIT; +}; + +struct st_system_romwt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ROMWT : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ROMWT : 2; +#endif +}; + +union un_system_romwt +{ + unsigned char BYTE; + struct st_system_romwt_bit BIT; +}; + +struct st_system_dpsbycr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEEPCUT : 2; + unsigned char : 4; + unsigned char IOKEEP : 1; + unsigned char DPSBY : 1; +#else + unsigned char DPSBY : 1; + unsigned char IOKEEP : 1; + unsigned char : 4; + unsigned char DEEPCUT : 2; +#endif +}; + +union un_system_dpsbycr +{ + unsigned char BYTE; + struct st_system_dpsbycr_bit BIT; +}; + +struct st_system_dpsier0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ7E : 1; +#else + unsigned char DIRQ7E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ0E : 1; +#endif +}; + +union un_system_dpsier0 +{ + unsigned char BYTE; + struct st_system_dpsier0_bit BIT; +}; + +struct st_system_dpsier1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ15E : 1; +#else + unsigned char DIRQ15E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ8E : 1; +#endif +}; + +union un_system_dpsier1 +{ + unsigned char BYTE; + struct st_system_dpsier1_bit BIT; +}; + +struct st_system_dpsier2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IE : 1; + unsigned char DLVD2IE : 1; + unsigned char DRTCIIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DNMIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DUSBIE : 1; +#else + unsigned char DUSBIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DNMIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DRTCIIE : 1; + unsigned char DLVD2IE : 1; + unsigned char DLVD1IE : 1; +#endif +}; + +union un_system_dpsier2 +{ + unsigned char BYTE; + struct st_system_dpsier2_bit BIT; +}; + +struct st_system_dpsier3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIE : 1; +#endif +}; + +union un_system_dpsier3 +{ + unsigned char BYTE; + struct st_system_dpsier3_bit BIT; +}; + +struct st_system_dpsifr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ7F : 1; +#else + unsigned char DIRQ7F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ0F : 1; +#endif +}; + +union un_system_dpsifr0 +{ + unsigned char BYTE; + struct st_system_dpsifr0_bit BIT; +}; + +struct st_system_dpsifr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ15F : 1; +#else + unsigned char DIRQ15F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ8F : 1; +#endif +}; + +union un_system_dpsifr1 +{ + unsigned char BYTE; + struct st_system_dpsifr1_bit BIT; +}; + +struct st_system_dpsifr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IF : 1; + unsigned char DLVD2IF : 1; + unsigned char DRTCIIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DNMIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DUSBIF : 1; +#else + unsigned char DUSBIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DNMIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DRTCIIF : 1; + unsigned char DLVD2IF : 1; + unsigned char DLVD1IF : 1; +#endif +}; + +union un_system_dpsifr2 +{ + unsigned char BYTE; + struct st_system_dpsifr2_bit BIT; +}; + +struct st_system_dpsifr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIF : 1; +#endif +}; + +union un_system_dpsifr3 +{ + unsigned char BYTE; + struct st_system_dpsifr3_bit BIT; +}; + +struct st_system_dpsiegr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ7EG : 1; +#else + unsigned char DIRQ7EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ0EG : 1; +#endif +}; + +union un_system_dpsiegr0 +{ + unsigned char BYTE; + struct st_system_dpsiegr0_bit BIT; +}; + +struct st_system_dpsiegr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ15EG : 1; +#else + unsigned char DIRQ15EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ8EG : 1; +#endif +}; + +union un_system_dpsiegr1 +{ + unsigned char BYTE; + struct st_system_dpsiegr1_bit BIT; +}; + +struct st_system_dpsiegr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1EG : 1; + unsigned char DLVD2EG : 1; + unsigned char : 2; + unsigned char DNMIEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DRIICCEG : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DRIICCEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DNMIEG : 1; + unsigned char : 2; + unsigned char DLVD2EG : 1; + unsigned char DLVD1EG : 1; +#endif +}; + +union un_system_dpsiegr2 +{ + unsigned char BYTE; + struct st_system_dpsiegr2_bit BIT; +}; + +struct st_system_dpsiegr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIEG : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIEG : 1; +#endif +}; + +union un_system_dpsiegr3 +{ + unsigned char BYTE; + struct st_system_dpsiegr3_bit BIT; +}; + +struct st_system_rstsr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 3; + unsigned char DPSRSTF : 1; +#else + unsigned char DPSRSTF : 1; + unsigned char : 3; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif +}; + +union un_system_rstsr0 +{ + unsigned char BYTE; + struct st_system_rstsr0_bit BIT; +}; + +struct st_system_rstr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif +}; + +union un_system_rstsr1 +{ + unsigned char BYTE; + struct st_system_rstr1_bit BIT; +}; + +struct st_system_mofcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOFXIN : 1; + unsigned char : 3; + unsigned char MODRV2 : 2; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV2 : 2; + unsigned char : 3; + unsigned char MOFXIN : 1; +#endif +}; + +union un_system_mofcr +{ + unsigned char BYTE; + struct st_system_mofcr_bit BIT; +}; + +struct st_system_hocopcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOPCNT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOCOPCNT : 1; +#endif +}; + +union un_system_hocopcr +{ + unsigned char BYTE; + struct st_system_hocopcr_bit BIT; +}; + +struct st_system_lvcmpcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 5; +#endif +}; + +union un_system_lvcmpcr +{ + unsigned char BYTE; + struct st_system_lvcmpcr_bit BIT; +}; + +struct st_system_lvdlvlr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 4; +#else + unsigned char LVD2LVL : 4; + unsigned char LVD1LVL : 4; +#endif +}; + +union un_system_lvdlvlr +{ + unsigned char BYTE; + struct st_system_lvdlvlr_bit BIT; +}; + +struct st_system_lvd1cr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1FSAMP : 2; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char LVD1FSAMP : 2; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1RIE : 1; +#endif +}; + +union un_system_lvd1cr0 +{ + unsigned char BYTE; + struct st_system_lvd1cr0_bit BIT; +}; + +struct st_system_lvd2cr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2FSAMP : 2; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char LVD2FSAMP : 2; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2RIE : 1; +#endif +}; + +union un_system_lvd2cr0 +{ + unsigned char BYTE; + struct st_system_lvd2cr0_bit BIT; +}; + +struct st_rtc_rcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif +}; + +union un_rtc_rcr3 +{ + unsigned char BYTE; + struct st_rtc_rcr3_bit BIT; +}; + +struct st_port0_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_pdr +{ + unsigned char BYTE; + struct st_port0_pdr_bit BIT; +}; + +struct st_port0_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_podr +{ + unsigned char BYTE; + struct st_port0_podr_bit BIT; +}; + +struct st_port0_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_pidr +{ + unsigned char BYTE; + struct st_port0_pidr_bit BIT; +}; + +struct st_port0_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_pmr +{ + unsigned char BYTE; + struct st_port0_pmr_bit BIT; +}; + +struct st_port0_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_odr0 +{ + unsigned char BYTE; + struct st_port0_odr0_bit BIT; +}; + +struct st_port0_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_port0_odr1 +{ + unsigned char BYTE; + struct st_port0_odr1_bit BIT; +}; + +struct st_port0_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_pcr +{ + unsigned char BYTE; + struct st_port0_pcr_bit BIT; +}; + +struct st_port0_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_dscr +{ + unsigned char BYTE; + struct st_port0_dscr_bit BIT; +}; + +struct st_port0_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port0_dscr2 +{ + unsigned char BYTE; + struct st_port0_dscr2_bit BIT; +}; + +struct st_port1_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pdr +{ + unsigned char BYTE; + struct st_port1_pdr_bit BIT; +}; + +struct st_port1_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_podr +{ + unsigned char BYTE; + struct st_port1_podr_bit BIT; +}; + +struct st_port1_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pidr +{ + unsigned char BYTE; + struct st_port1_pidr_bit BIT; +}; + +struct st_port1_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pmr +{ + unsigned char BYTE; + struct st_port1_pmr_bit BIT; +}; + +struct st_port1_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_odr0 +{ + unsigned char BYTE; + struct st_port1_odr0_bit BIT; +}; + +struct st_port1_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_odr1 +{ + unsigned char BYTE; + struct st_port1_odr1_bit BIT; +}; + +struct st_port1_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pcr +{ + unsigned char BYTE; + struct st_port1_pcr_bit BIT; +}; + +struct st_port1_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif +}; + +union un_port1_dscr +{ + unsigned char BYTE; + struct st_port1_dscr_bit BIT; +}; + +struct st_port1_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif +}; + +union un_port1_dscr2 +{ + unsigned char BYTE; + struct st_port1_dscr2_bit BIT; +}; + +struct st_port2_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pdr +{ + unsigned char BYTE; + struct st_port2_pdr_bit BIT; +}; + +struct st_port2_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_podr +{ + unsigned char BYTE; + struct st_port2_podr_bit BIT; +}; + +struct st_port2_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pidr +{ + unsigned char BYTE; + struct st_port2_pidr_bit BIT; +}; + +struct st_port2_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pmr +{ + unsigned char BYTE; + struct st_port2_pmr_bit BIT; +}; + +struct st_port2_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_odr0 +{ + unsigned char BYTE; + struct st_port2_odr0_bit BIT; +}; + +struct st_port2_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_odr1 +{ + unsigned char BYTE; + struct st_port2_odr1_bit BIT; +}; + +struct st_port2_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pcr +{ + unsigned char BYTE; + struct st_port2_pcr_bit BIT; +}; + +struct st_port2_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif +}; + +union un_port2_dscr +{ + unsigned char BYTE; + struct st_port2_dscr_bit BIT; +}; + +struct st_port2_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 3; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_dscr2 +{ + unsigned char BYTE; + struct st_port2_dscr2_bit BIT; +}; + +struct st_port3_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pdr +{ + unsigned char BYTE; + struct st_port3_pdr_bit BIT; +}; + +struct st_port3_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_podr +{ + unsigned char BYTE; + struct st_port3_podr_bit BIT; +}; + +struct st_port3_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pidr +{ + unsigned char BYTE; + struct st_port3_pidr_bit BIT; +}; + +struct st_port3_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pmr +{ + unsigned char BYTE; + struct st_port3_pmr_bit BIT; +}; + +struct st_port3_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_odr0 +{ + unsigned char BYTE; + struct st_port3_odr0_bit BIT; +}; + +struct st_port3_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_odr1 +{ + unsigned char BYTE; + struct st_port3_odr1_bit BIT; +}; + +struct st_port3_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pcr +{ + unsigned char BYTE; + struct st_port3_pcr_bit BIT; +}; + +struct st_port3_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_dscr2 +{ + unsigned char BYTE; + struct st_port3_dscr2_bit BIT; +}; + +struct st_port4_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_pdr +{ + unsigned char BYTE; + struct st_port4_pdr_bit BIT; +}; + +struct st_port4_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_podr +{ + unsigned char BYTE; + struct st_port4_podr_bit BIT; +}; + +struct st_port4_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_pidr +{ + unsigned char BYTE; + struct st_port4_pidr_bit BIT; +}; + +struct st_port4_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_pmr +{ + unsigned char BYTE; + struct st_port4_pmr_bit BIT; +}; + +struct st_port4_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_odr0 +{ + unsigned char BYTE; + struct st_port4_odr0_bit BIT; +}; + +struct st_port4_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_odr1 +{ + unsigned char BYTE; + struct st_port4_odr1_bit BIT; +}; + +struct st_port4_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port4_pcr +{ + unsigned char BYTE; + struct st_port4_pcr_bit BIT; +}; + +typedef struct st_port4 +{ + union un_port4_pdr PDR; + char wk0[31]; + union un_port4_podr PODR; + char wk1[31]; + union un_port4_pidr PIDR; + char wk2[31]; + union un_port4_pmr PMR; + char wk3[35]; + union un_port4_odr0 ORD0; + union un_port4_odr1 ORD1; + char wk4[58]; + union un_port4_pcr PCR; +} st_port4_t; + +struct st_port5_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pdr +{ + unsigned char BYTE; + struct st_port5_pdr_bit BIT; +}; + +struct st_port5_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_podr +{ + unsigned char BYTE; + struct st_port5_podr_bit BIT; +}; + +struct st_port5_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pidr +{ + unsigned char BYTE; + struct st_port5_pidr_bit BIT; +}; + +struct st_port5_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pmr +{ + unsigned char BYTE; + struct st_port5_pmr_bit BIT; +}; + +struct st_port5_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_odr0 +{ + unsigned char BYTE; + struct st_port5_odr0_bit BIT; +}; + +struct st_port5_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_odr1 +{ + unsigned char BYTE; + struct st_port5_odr1_bit BIT; +}; + +struct st_port5_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pcr +{ + unsigned char BYTE; + struct st_port5_pcr_bit BIT; +}; + +struct st_port5_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_dscr +{ + unsigned char BYTE; + struct st_port5_dscr_bit BIT; +}; + +struct st_port5_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_dscr2 +{ + unsigned char BYTE; + struct st_port5_dscr2_bit BIT; +}; + +struct st_port7_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pdr +{ + unsigned char BYTE; + struct st_port7_pdr_bit BIT; +}; + +struct st_port7_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_podr +{ + unsigned char BYTE; + struct st_port7_podr_bit BIT; +}; + +struct st_port7_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pidr +{ + unsigned char BYTE; + struct st_port7_pidr_bit BIT; +}; + +struct st_port7_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pmr +{ + unsigned char BYTE; + struct st_port7_pmr_bit BIT; +}; + +struct st_port7_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_odr0 +{ + unsigned char BYTE; + struct st_port7_odr0_bit BIT; +}; + +struct st_port7_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_odr1 +{ + unsigned char BYTE; + struct st_port7_odr1_bit BIT; +}; + +struct st_port7_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pcr +{ + unsigned char BYTE; + struct st_port7_pcr_bit BIT; +}; + +struct st_port7_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_port7_dscr +{ + unsigned char BYTE; + struct st_port7_dscr_bit BIT; +}; + +struct st_port7_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_dscr2 +{ + unsigned char BYTE; + struct st_port7_dscr2_bit BIT; +}; + +struct st_port8_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pdr +{ + unsigned char BYTE; + struct st_port8_pdr_bit BIT; +}; + +struct st_port8_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_podr +{ + unsigned char BYTE; + struct st_port8_podr_bit BIT; +}; + +struct st_port8_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pidr +{ + unsigned char BYTE; + struct st_port8_pidr_bit BIT; +}; + +struct st_port8_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pmr +{ + unsigned char BYTE; + struct st_port8_pmr_bit BIT; +}; + +struct st_port8_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_odr0 +{ + unsigned char BYTE; + struct st_port8_odr0_bit BIT; +}; + +struct st_port8_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_odr1 +{ + unsigned char BYTE; + struct st_port8_odr1_bit BIT; +}; + +struct st_port8_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pcr +{ + unsigned char BYTE; + struct st_port8_pcr_bit BIT; +}; + +struct st_port8_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_dscr +{ + unsigned char BYTE; + struct st_port8_dscr_bit BIT; +}; + +struct st_port8_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_dscr2 +{ + unsigned char BYTE; + struct st_port8_dscr2_bit BIT; +}; + +struct st_port9_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pdr +{ + unsigned char BYTE; + struct st_port9_pdr_bit BIT; +}; + +struct st_port9_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_podr +{ + unsigned char BYTE; + struct st_port9_podr_bit BIT; +}; + +struct st_port9_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pidr +{ + unsigned char BYTE; + struct st_port9_pidr_bit BIT; +}; + +struct st_port9_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pmr +{ + unsigned char BYTE; + struct st_port9_pmr_bit BIT; +}; + +struct st_port9_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_odr0 +{ + unsigned char BYTE; + struct st_port9_odr0_bit BIT; +}; + +struct st_port9_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_odr1 +{ + unsigned char BYTE; + struct st_port9_odr1_bit BIT; +}; + +struct st_port9_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pcr +{ + unsigned char BYTE; + struct st_port9_pcr_bit BIT; +}; + +struct st_port9_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_dscr +{ + unsigned char BYTE; + struct st_port9_dscr_bit BIT; +}; + +struct st_port9_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_dscr2 +{ + unsigned char BYTE; + struct st_port9_dscr2_bit BIT; +}; + +struct st_porta_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pdr +{ + unsigned char BYTE; + struct st_porta_pdr_bit BIT; +}; + +struct st_porta_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_podr +{ + unsigned char BYTE; + struct st_porta_podr_bit BIT; +}; + +struct st_porta_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pidr +{ + unsigned char BYTE; + struct st_porta_pidr_bit BIT; +}; + +struct st_porta_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pmr +{ + unsigned char BYTE; + struct st_porta_pmr_bit BIT; +}; + +struct st_porta_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_odr0 +{ + unsigned char BYTE; + struct st_porta_odr0_bit BIT; +}; + +struct st_porta_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_odr1 +{ + unsigned char BYTE; + struct st_porta_odr1_bit BIT; +}; + +struct st_porta_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pcr +{ + unsigned char BYTE; + struct st_porta_pcr_bit BIT; +}; + +struct st_porta_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_dscr +{ + unsigned char BYTE; + struct st_porta_dscr_bit BIT; +}; + +struct st_porta_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_dscr2 +{ + unsigned char BYTE; + struct st_porta_dscr2_bit BIT; +}; + +struct st_portb_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pdr +{ + unsigned char BYTE; + struct st_portb_pdr_bit BIT; +}; + +struct st_portb_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_podr +{ + unsigned char BYTE; + struct st_portb_podr_bit BIT; +}; + +struct st_portb_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pidr +{ + unsigned char BYTE; + struct st_portb_pidr_bit BIT; +}; + +struct st_portb_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pmr +{ + unsigned char BYTE; + struct st_portb_pmr_bit BIT; +}; + +struct st_portb_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_odr0 +{ + unsigned char BYTE; + struct st_portb_odr0_bit BIT; +}; + +struct st_portb_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_odr1 +{ + unsigned char BYTE; + struct st_portb_odr1_bit BIT; +}; + +struct st_portb_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pcr +{ + unsigned char BYTE; + struct st_portb_pcr_bit BIT; +}; + +struct st_portb_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_dscr +{ + unsigned char BYTE; + struct st_portb_dscr_bit BIT; +}; + +struct st_portb_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_dscr2 +{ + unsigned char BYTE; + struct st_portb_dscr2_bit BIT; +}; + +struct st_portc_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pdr +{ + unsigned char BYTE; + struct st_portc_pdr_bit BIT; +}; + +struct st_portc_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_podr +{ + unsigned char BYTE; + struct st_portc_podr_bit BIT; +}; + +struct st_portc_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pidr +{ + unsigned char BYTE; + struct st_portc_pidr_bit BIT; +}; + +struct st_portc_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pmr +{ + unsigned char BYTE; + struct st_portc_pmr_bit BIT; +}; + +struct st_portc_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_odr0 +{ + unsigned char BYTE; + struct st_portc_odr0_bit BIT; +}; + +struct st_portc_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_odr1 +{ + unsigned char BYTE; + struct st_portc_odr1_bit BIT; +}; + +struct st_portc_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pcr +{ + unsigned char BYTE; + struct st_portc_pcr_bit BIT; +}; + +struct st_portc_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_dscr +{ + unsigned char BYTE; + struct st_portc_dscr_bit BIT; +}; + +struct st_portc_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_dscr2 +{ + unsigned char BYTE; + struct st_portc_dscr2_bit BIT; +}; + +struct st_porte_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pdr +{ + unsigned char BYTE; + struct st_porte_pdr_bit BIT; +}; + +struct st_porte_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_podr +{ + unsigned char BYTE; + struct st_porte_podr_bit BIT; +}; + +struct st_porte_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pidr +{ + unsigned char BYTE; + struct st_porte_pidr_bit BIT; +}; + +struct st_porte_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pmr +{ + unsigned char BYTE; + struct st_porte_pmr_bit BIT; +}; + +struct st_porte_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_odr0 +{ + unsigned char BYTE; + struct st_porte_odr0_bit BIT; +}; + +struct st_porte_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_odr1 +{ + unsigned char BYTE; + struct st_porte_odr1_bit BIT; +}; + +struct st_porte_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pcr +{ + unsigned char BYTE; + struct st_porte_pcr_bit BIT; +}; + +struct st_porte_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_dscr +{ + unsigned char BYTE; + struct st_porte_dscr_bit BIT; +}; + +struct st_porte_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +struct st_portf_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_dscr2 +{ + unsigned char BYTE; + struct st_porte_dscr2_bit BIT; +}; + +union un_portf_pdr +{ + unsigned char BYTE; + struct st_portf_pdr_bit BIT; +}; + +struct st_portf_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_podr +{ + unsigned char BYTE; + struct st_portf_podr_bit BIT; +}; + +struct st_portf_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pidr +{ + unsigned char BYTE; + struct st_portf_pidr_bit BIT; +}; + +struct st_portf_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pmr +{ + unsigned char BYTE; + struct st_portf_pmr_bit BIT; +}; + +struct st_portf_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_odr0 +{ + unsigned char BYTE; + struct st_portf_odr0_bit BIT; +}; + +struct st_portf_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_odr1 +{ + unsigned char BYTE; + struct st_portf_odr1_bit BIT; +}; + +struct st_portf_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pcr +{ + unsigned char BYTE; + struct st_portf_pcr_bit BIT; +}; + +struct st_portg_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pdr +{ + unsigned char BYTE; + struct st_portg_pdr_bit BIT; +}; + +struct st_portg_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_podr +{ + unsigned char BYTE; + struct st_portg_podr_bit BIT; +}; + +struct st_portg_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pidr +{ + unsigned char BYTE; + struct st_portg_pidr_bit BIT; +}; + +struct st_portg_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pmr +{ + unsigned char BYTE; + struct st_portg_pmr_bit BIT; +}; + +struct st_portg_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_odr0 +{ + unsigned char BYTE; + struct st_portg_odr0_bit BIT; +}; + +struct st_portg_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_odr1 +{ + unsigned char BYTE; + struct st_portg_odr1_bit BIT; +}; + +struct st_portg_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pcr +{ + unsigned char BYTE; + struct st_portg_pcr_bit BIT; +}; + +struct st_portg_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_dscr +{ + unsigned char BYTE; + struct st_portg_dscr_bit BIT; +}; + +struct st_portg_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_dscr2 +{ + unsigned char BYTE; + struct st_portg_dscr2_bit BIT; +}; + +struct st_portj_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pdr +{ + unsigned char BYTE; + struct st_portj_pdr_bit BIT; +}; + +struct st_portj_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_podr +{ + unsigned char BYTE; + struct st_portj_podr_bit BIT; +}; + +struct st_portj_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pidr +{ + unsigned char BYTE; + struct st_portj_pidr_bit BIT; +}; + +struct st_portj_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pmr +{ + unsigned char BYTE; + struct st_portj_pmr_bit BIT; +}; + +struct st_portj_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_odr0 +{ + unsigned char BYTE; + struct st_portj_odr0_bit BIT; +}; + +struct st_portj_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_portj_odr1 +{ + unsigned char BYTE; + struct st_portj_odr1_bit BIT; +}; + +struct st_portj_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pcr +{ + unsigned char BYTE; + struct st_portj_pcr_bit BIT; +}; + +struct st_portj_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_dscr +{ + unsigned char BYTE; + struct st_portj_dscr_bit BIT; +}; + +struct st_portj_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_dscr2 +{ + unsigned char BYTE; + struct st_portj_dscr2_bit BIT; +}; + +struct st_sci0_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci0_smr +{ + unsigned char BYTE; + struct st_sci0_smr_bit BIT; +}; + +struct st_sci0_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci0_scr +{ + unsigned char BYTE; + struct st_sci0_scr_bit BIT; +}; + +struct st_sci0_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci0_ssr +{ + unsigned char BYTE; + struct st_sci0_ssr_bit BIT; +}; + +struct st_sci0_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci0_scmr +{ + unsigned char BYTE; + struct st_sci0_scmr_bit BIT; +}; + +struct st_sci0_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci0_semr +{ + unsigned char BYTE; + struct st_sci0_semr_bit BIT; +}; + +struct st_sci0_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci0_snfr +{ + unsigned char BYTE; + struct st_sci0_snfr_bit BIT; +}; + +struct st_sci0_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci0_simr1 +{ + unsigned char BYTE; + struct st_sci0_simr1_bit BIT; +}; + +struct st_sci0_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci0_simr2 +{ + unsigned char BYTE; + struct st_sci0_simr2_bit BIT; +}; + +struct st_sci0_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci0_simr3 +{ + unsigned char BYTE; + struct st_sci0_simr3_bit BIT; +}; + +struct st_sci0_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci0_sisr +{ + unsigned char BYTE; + struct st_sci0_sisr_bit BIT; +}; + +struct st_sci0_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci0_spmr +{ + unsigned char BYTE; + struct st_sci0_spmr_bit BIT; +}; + +struct st_sci0_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci0_tdrhl +{ + unsigned short WORD; + struct st_sci0_tdrhl_byte BYTE; +}; + +struct st_sci0_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci0_rdrhl +{ + unsigned short WORD; + struct st_sci0_rdrhl_byte BYTE; +}; + +struct st_sci10_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci10_smr +{ + unsigned char BYTE; + struct st_sci10_smr_bit BIT; +}; + +struct st_sci10_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci10_scr +{ + unsigned char BYTE; + struct st_sci10_scr_bit BIT; +}; + +struct st_sci10_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci10_ssr +{ + unsigned char BYTE; + struct st_sci10_ssr_bit BIT; +}; + +struct st_sci10_ssrfifo_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DR : 1; + unsigned char : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDF : 1; + unsigned char TDFE : 1; +#else + unsigned char TDFE : 1; + unsigned char RDF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char : 1; + unsigned char DR : 1; +#endif +}; + +union un_sci10_ssrfifo +{ + unsigned char BYTE; + struct st_sci10_ssrfifo_bit BIT; +}; + +struct st_sci10_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci10_scmr +{ + unsigned char BYTE; + struct st_sci10_scmr_bit BIT; +}; + +struct st_sci10_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci10_semr +{ + unsigned char BYTE; + struct st_sci10_semr_bit BIT; +}; + +struct st_sci10_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci10_snfr +{ + unsigned char BYTE; + struct st_sci10_snfr_bit BIT; +}; + +struct st_sci10_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci10_simr1 +{ + unsigned char BYTE; + struct st_sci10_simr1_bit BIT; +}; + +struct st_sci10_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci10_simr2 +{ + unsigned char BYTE; + struct st_sci10_simr2_bit BIT; +}; + +struct st_sci10_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci10_simr3 +{ + unsigned char BYTE; + struct st_sci10_simr3_bit BIT; +}; + +struct st_sci10_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci10_sisr +{ + unsigned char BYTE; + struct st_sci10_sisr_bit BIT; +}; + +struct st_sci10_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci10_spmr +{ + unsigned char BYTE; + struct st_sci10_spmr_bit BIT; +}; + +struct st_sci10_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci10_tdrhl +{ + unsigned short WORD; + struct st_sci10_tdrhl_byte BYTE; +}; + +struct st_sci10_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_ftdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TDAT : 9; + unsigned short MPBT : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short MPBT : 1; + unsigned short TDAT : 9; +#endif +}; + +union un_sci10_ftdr_bit_byte +{ + unsigned short WORD; + struct st_sci10_byte BYTE; + struct st_sci10_ftdr_bit BIT; +}; + +struct st_sci10_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci10_rdrhl_byte +{ + unsigned short WORD; + struct st_sci10_rdrhl_byte BYTE; +}; + +struct st_sci10_frdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_frdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDAT : 9; + unsigned short MPB : 1; + unsigned short DR : 1; + unsigned short PER : 1; + unsigned short FER : 1; + unsigned short ORER : 1; + unsigned short RDF : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RDF : 1; + unsigned short ORER : 1; + unsigned short FER : 1; + unsigned short PER : 1; + unsigned short DR : 1; + unsigned short MPB : 1; + unsigned short RDAT : 9; +#endif +}; + +union un_sci10_frdr_bit_byte +{ + unsigned short WORD; + struct st_sci10_frdr_bit_byte BYTE; + struct st_sci10_frdr_bit BIT; +}; + +struct st_sci10_dccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif +}; + +union un_sci10_dccr +{ + unsigned char BYTE; + struct st_sci10_dccr_bit BIT; +}; + +struct st_sci10_fcr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_fcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FM : 1; + unsigned short RFRST : 1; + unsigned short TFRST : 1; + unsigned short DRES : 1; + unsigned short TTRG : 4; + unsigned short RTRG : 4; + unsigned short RSTRG : 4; +#else + unsigned short RSTRG : 4; + unsigned short RTRG : 4; + unsigned short TTRG : 4; + unsigned short DRES : 1; + unsigned short TFRST : 1; + unsigned short RFRST : 1; + unsigned short FM : 1; +#endif +}; + +union un_sci10_fcr +{ + unsigned short WORD; + struct st_sci10_fcr_bit_byte BYTE; + struct st_sci10_fcr_bit BIT; +}; + +struct st_sci10_fdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_fdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short R : 5; + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; + unsigned short R : 5; +#endif +}; + +union un_sci10_fdr +{ + unsigned short WORD; + struct st_sci10_fdr_bit_byte BYTE; + struct st_sci10_fdr_bit BIT; +}; + +struct st_sci10_lsr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_lsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ORER : 1; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short PNUM : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short PNUM : 5; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short ORER : 1; +#endif +}; + +union un_sci10_lsr +{ + unsigned short WORD; + struct st_sci10_lsr_bit_byte BYTE; + struct st_sci10_lsr_bit BIT; +}; + +struct st_sci10_cdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_cdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif +}; + +union un_sci10_cdr +{ + unsigned short WORD; + struct st_sci10_cdr_bit_byte BYTE; + struct st_sci10_cdr_bit BIT; +}; + +struct st_sci10_sptr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif +}; + +union st_sci10_sptr +{ + unsigned char BYTE; + struct st_sci10_sptr_bit BIT; +}; + +struct st_sci12_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci12_smr +{ + unsigned char BYTE; + struct st_sci12_smr_bit BIT; +}; + +struct st_sci12_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci12_scr +{ + unsigned char BYTE; + struct st_sci12_scr_bit BIT; +}; + +struct st_sci12_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci12_ssr +{ + unsigned char BYTE; + struct st_sci12_ssr_bit BIT; +}; + +struct st_sci12_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci12_scmr +{ + unsigned char BYTE; + struct st_sci12_scmr_bit BIT; +}; + +struct st_sci12_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci12_semr +{ + unsigned char BYTE; + struct st_sci12_semr_bit BIT; +}; + +struct st_sci12_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci12_snfr +{ + unsigned char BYTE; + struct st_sci12_snfr_bit BIT; +}; + +struct st_sci12_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci12_simr1 +{ + unsigned char BYTE; + struct st_sci12_simr1_bit BIT; +}; + +struct st_sci12_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci12_simr2 +{ + unsigned char BYTE; + struct st_sci12_simr2_bit BIT; +}; + +struct st_sci12_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci12_simr3 +{ + unsigned char BYTE; + struct st_sci12_simr3_bit BIT; +}; + +struct st_sci12_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci12_sisr +{ + unsigned char BYTE; + struct st_sci12_sisr_bit BIT; +}; + +struct st_sci12_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci12_spmr +{ + unsigned char BYTE; + struct st_sci12_spmr_bit BIT; +}; + +struct st_sci12_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci12_tdrhl +{ + unsigned short WORD; + struct st_sci12_tdrhl_byte BYTE; +}; + +struct st_sci12_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci12_rdrhl +{ + unsigned short WORD; + struct st_sci12_rdrhl_byte BYTE; +}; + +struct st_sci12_esmer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif +}; + +union un_sci12_esmer +{ + unsigned char BYTE; + struct st_sci12_esmer_bit BIT; +}; + +struct st_sci12_ctr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif +}; + +union un_sci12_ctr0 +{ + unsigned char BYTE; + struct st_sci12_ctr0_bit BIT; +}; + +struct st_sci12_ctr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif +}; + +union un_sci12_ctr1 +{ + unsigned char BYTE; + struct st_sci12_ctr1_bit BIT; +}; + +struct st_sci12_ctr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif +}; + +union un_sci12_ctr2 +{ + unsigned char BYTE; + struct st_sci12_ctr2_bit BIT; +}; + +struct st_sci12_ctr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif +}; + +union un_sci12_ctr3 +{ + unsigned char BYTE; + struct st_sci12_ctr3_bit BIT; +}; + +struct st_sci12_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif +}; + +union un_sci12_pcr +{ + unsigned char BYTE; + struct st_sci12_pcr_bit BIT; +}; + +struct st_sci12_icr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif +}; + +union un_sci12_icr +{ + unsigned char BYTE; + struct st_sci12_icr_bit BIT; +}; + +struct st_sci12_str_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif +}; + +union un_sci12_str +{ + unsigned char BYTE; + struct st_sci12_str_bit BIT; +}; + +struct un_sci12_stcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif +}; + +union un_sci12_stcr +{ + unsigned char BYTE; + struct un_sci12_stcr_bit BIT; +}; + +struct st_sci12_cf0cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif +}; + +union un_sci12_cf0cr +{ + unsigned char BYTE; + struct st_sci12_cf0cr_bit BIT; +}; + +struct st_sci12_cf1cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif +}; + +union un_sci12_cf1cr +{ + unsigned char BYTE; + struct st_sci12_cf1cr_bit BIT; +}; + +struct st_sci12_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif +}; + +union un_sci12_tcr +{ + unsigned char BYTE; + struct st_sci12_tcr_bit BIT; +}; + +struct st_sci12_tmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif +}; + +union un_sci12_tmr +{ + unsigned char BYTE; + struct st_sci12_tmr_bit BIT; +}; + +struct st_temps_tscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char TSOE : 1; + unsigned char : 2; + unsigned char TSEN : 1; +#else + unsigned char TSEN : 1; + unsigned char : 2; + unsigned char TSOE : 1; + unsigned char : 4; +#endif +}; + +union un_temps_tscr +{ + unsigned char BYTE; + struct st_temps_tscr_bit BIT; +}; + +struct st_tmr0_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif +}; + +union un_tmr0_tcr +{ + unsigned char BYTE; + struct st_tmr0_tcr_bit BIT; +}; + +struct st_tmr0_tcsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char ADTE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADTE : 1; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif +}; + +union un_tmr0_tcsr +{ + unsigned char BYTE; + struct st_tmr0_tcsr_bit BIT; +}; + +struct st_tmr0_tccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif +}; + +union un_tmr0_tccr +{ + unsigned char BYTE; + struct st_tmr0_tccr_bit BIT; +}; + +struct st_tmr0_tcstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif +}; + +union un_tmr0_tcstr +{ + unsigned char BYTE; + struct st_tmr0_tcstr_bit BIT; +}; + +struct st_tmr1_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif +}; + +union un_tmr1_tcr +{ + unsigned char BYTE; + struct st_tmr1_tcr_bit BIT; +}; + +struct st_tmr1_tcsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif +}; + +union un_tmr1_tcsr +{ + unsigned char BYTE; + struct st_tmr1_tcsr_bit BIT; +}; + +struct st_tmr1_tccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif +}; + +union un_tmr1_tccr +{ + unsigned char BYTE; + struct st_tmr1_tccr_bit BIT; +}; + +struct st_tmr1_tcstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif +}; + +union un_tmr1_tcstr +{ + unsigned char BYTE; + struct st_tmr1_tcstr_bit BIT; +}; + +struct st_tpu0_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu0_nfcr +{ + unsigned char BYTE; + struct st_tpu0_nfcr_bit BIT; +}; + +struct st_tpu0_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu0_tcr +{ + unsigned char BYTE; + struct st_tpu0_tcr_bit BIT; +}; + +struct st_tpu0_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_tpu0_tmdr +{ + unsigned char BYTE; + struct st_tpu0_tmdr_bit BIT; +}; + +struct st_tpu0_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu0_tiorh +{ + unsigned char BYTE; + struct st_tpu0_tiorh_bit BIT; +}; + +struct st_tpu0_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_tpu0_tiorl +{ + unsigned char BYTE; + struct st_tpu0_tiorl_bit BIT; +}; + +struct st_tpu0_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu0_tier +{ + unsigned char BYTE; + struct st_tpu0_tier_bit BIT; +}; + +struct un_tpu0_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu0_tsr +{ + unsigned char BYTE; + struct un_tpu0_tsr_bit BIT; +}; + +struct st_tpu1_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu1_nfcr +{ + unsigned char BYTE; + struct st_tpu1_nfcr_bit BIT; +}; + +struct st_tpu1_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu1_tcr +{ + unsigned char BYTE; + struct st_tpu1_tcr_bit BIT; +}; + +struct st_tpu1_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif +}; + +union un_tpu1_tmdr +{ + unsigned char BYTE; + struct st_tpu1_tmdr_bit BIT; +}; + +struct st_tpu1_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu1_tior +{ + unsigned char BYTE; + struct st_tpu1_tior_bit BIT; +}; + +struct st_tpu1_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu1_tier +{ + unsigned char BYTE; + struct st_tpu1_tier_bit BIT; +}; + +struct st_tpu1_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu1_tsr +{ + unsigned char BYTE; + struct st_tpu1_tsr_bit BIT; +}; + +struct st_tpu2_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu2_nfcr +{ + unsigned char BYTE; + struct st_tpu2_nfcr_bit BIT; +}; + +struct st_tpu2_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu2_tcr +{ + unsigned char BYTE; + struct st_tpu2_tcr_bit BIT; +}; + +struct st_tpu2_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif +}; + +union un_tpu2_tmdr +{ + unsigned char BYTE; + struct st_tpu2_tmdr_bit BIT; +}; + +struct st_tpu2_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu2_tior +{ + unsigned char BYTE; + struct st_tpu2_tior_bit BIT; +}; + +struct st_tpu2_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu2_tier +{ + unsigned char BYTE; + struct st_tpu2_tier_bit BIT; +}; + +struct st_tpu2_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu2_tsr +{ + unsigned char BYTE; + struct st_tpu2_tsr_bit BIT; +}; + +struct st_tpu3_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu3_nfcr +{ + unsigned char BYTE; + struct st_tpu3_nfcr_bit BIT; +}; + +struct st_tpu3_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu3_tcr +{ + unsigned char BYTE; + struct st_tpu3_tcr_bit BIT; +}; + +struct st_tpu3_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_tpu3_tmdr +{ + unsigned char BYTE; + struct st_tpu3_tmdr_bit BIT; +}; + +struct st_tpu3_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu3_tiorh +{ + unsigned char BYTE; + struct st_tpu3_tiorh_bit BIT; +}; + +struct st_tpu3_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_tpu3_tiorl +{ + unsigned char BYTE; + struct st_tpu3_tiorl_bit BIT; +}; + +struct st_tpu3_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu3_tier +{ + unsigned char BYTE; + struct st_tpu3_tier_bit BIT; +}; + +struct st_tpu3_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu3_tsr +{ + unsigned char BYTE; + struct st_tpu3_tsr_bit BIT; +}; + +struct st_tpu4_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu4_nfcr +{ + unsigned char BYTE; + struct st_tpu4_nfcr_bit BIT; +}; + +struct st_tpu4_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu4_tcr +{ + unsigned char BYTE; + struct st_tpu4_tcr_bit BIT; +}; + +struct st_tpu4_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif +}; + +union un_tpu4_tmdr +{ + unsigned char BYTE; + struct st_tpu4_tmdr_bit BIT; +}; + +struct un_tpu4_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu4_tior +{ + unsigned char BYTE; + struct un_tpu4_tior_bit BIT; +}; + +struct st_tpu4_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu4_tier +{ + unsigned char BYTE; + struct st_tpu4_tier_bit BIT; +}; + +struct st_tpu4_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu4_tsr +{ + unsigned char BYTE; + struct st_tpu4_tsr_bit BIT; +}; + +struct st_tpu5_nfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 2; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_tpu5_nfcr +{ + unsigned char BYTE; + struct st_tpu5_nfcr_bit BIT; +}; + +struct st_tpu5_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_tpu5_tcr +{ + unsigned char BYTE; + struct st_tpu5_tcr_bit BIT; +}; + +struct st_tpu5_tmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 2; + unsigned char ICSELB : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ICSELB : 1; + unsigned char : 2; + unsigned char MD : 4; +#endif +}; + +union un_tpu5_tmdr +{ + unsigned char BYTE; + struct st_tpu5_tmdr_bit BIT; +}; + +struct st_tpu5_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_tpu5_tior +{ + unsigned char BYTE; + struct st_tpu5_tior_bit BIT; +}; + +struct st_tpu5_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_tpu5_tier +{ + unsigned char BYTE; + struct st_tpu5_tier_bit BIT; +}; + +struct st_tpu5_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char : 2; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char : 2; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif +}; + +union un_tpu5_tsr +{ + unsigned char BYTE; + struct st_tpu5_tsr_bit BIT; +}; + +struct st_tpua_tstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; + unsigned char CST5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CST5 : 1; + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif +}; + +union un_tpua_tstr +{ + unsigned char BYTE; + struct st_tpua_tstr_bit BIT; +}; + +struct st_tpua_tsyr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SYNC5 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif +}; + +union un_tpua_tsyr +{ + unsigned char BYTE; + struct st_tpua_tsyr_bit BIT; +}; + +struct st_usb_dpusr0r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRPC0 : 1; + unsigned long RPUE0 : 1; + unsigned long : 1; + unsigned long DRPD0 : 1; + unsigned long FIXPHY0 : 1; + unsigned long : 11; + unsigned long DP0 : 1; + unsigned long DM0 : 1; + unsigned long : 2; + unsigned long DOVCA0 : 1; + unsigned long DOVCB0 : 1; + unsigned long : 1; + unsigned long DVBSTS0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBSTS0 : 1; + unsigned long : 1; + unsigned long DOVCB0 : 1; + unsigned long DOVCA0 : 1; + unsigned long : 2; + unsigned long DM0 : 1; + unsigned long DP0 : 1; + unsigned long : 11; + unsigned long FIXPHY0 : 1; + unsigned long DRPD0 : 1; + unsigned long : 1; + unsigned long RPUE0 : 1; + unsigned long SRPC0 : 1; +#endif +}; + +union un_usb_dpusr0r +{ + unsigned long LONG; + struct st_usb_dpusr0r_bit BIT; +}; + +struct st_usb_dpusr1r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DPINTE0 : 1; + unsigned long DMINTE0 : 1; + unsigned long : 2; + unsigned long DOVRCRAE0 : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long : 1; + unsigned long DVBSE0 : 1; + unsigned long : 8; + unsigned long DPINT0 : 1; + unsigned long DMINT0 : 1; + unsigned long : 2; + unsigned long DOVRCRA0 : 1; + unsigned long DOVRCRB0 : 1; + unsigned long : 1; + unsigned long DVBINT0 : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long DVBINT0 : 1; + unsigned long : 1; + unsigned long DOVRCRB0 : 1; + unsigned long DOVRCRA0 : 1; + unsigned long : 2; + unsigned long DMINT0 : 1; + unsigned long DPINT0 : 1; + unsigned long : 8; + unsigned long DVBSE0 : 1; + unsigned long : 1; + unsigned long DOVRCRBE0 : 1; + unsigned long DOVRCRAE0 : 1; + unsigned long : 2; + unsigned long DMINTE0 : 1; + unsigned long DPINTE0 : 1; +#endif +}; + +union un_usb_dpusr1r +{ + unsigned long LONG; + struct st_usb_dpusr1r_bit BIT; +}; + +struct st_usb0_syscfg_bit +{ + unsigned short :5; + unsigned short SCKE:1; + unsigned short :3; + unsigned short DCFM:1; + unsigned short DRPD:1; + unsigned short DPRPU:1; + unsigned short :3; + unsigned short USBE:1; +}; + +union un_usb0_syscfg +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_syscfg_bit BIT; +#endif +}; + +struct st_usb0_syssts0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 2; + unsigned short SOFEA : 1; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short SOFEA : 1; + unsigned short : 2; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif +}; + +union un_usb0_syssts0 +{ + unsigned short WORD; + struct st_usb0_syssts0_bit BIT; +}; + +struct st_usb0_dvstctr0_bit +{ + unsigned short :4; + unsigned short HNPBTOA:1; + unsigned short EXICEN:1; + unsigned short VBUSEN:1; + unsigned short WKUP:1; + unsigned short RWUPE:1; + unsigned short USBRST:1; + unsigned short RESUME:1; + unsigned short UACT:1; + unsigned short :1; + unsigned short RHST:3; +}; + +union un_usb0_dvstctr0 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_dvstctr0_bit BIT; +#endif +}; + +struct st_usb0_cfifo_byte +{ + unsigned char L; + unsigned char H; +}; + +union un_usb0_cfifo +{ + unsigned short WORD; + struct st_usb0_cfifo_byte BYTE; +}; + +struct st_usb0_d0fifo_byte +{ + unsigned char L; + unsigned char H; +}; + +union un_usb0_d0fifo +{ + unsigned short WORD; + struct st_usb0_d0fifo_byte BYTE; +}; + +struct st_usb0_d1fifo_byte +{ + unsigned char L; + unsigned char H; +}; + +union un_usb0_d1fifo +{ + unsigned short WORD; + struct st_usb0_d1fifo_byte BYTE; +}; + +struct st_usb0_cfifosel_bit +{ + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short :3; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :2; + unsigned short ISEL:1; + unsigned short :1; + unsigned short CURPIPE:4; +}; + +union un_usb0_cfifosel +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_cfifosel_bit BIT; +#endif +}; + +struct st_usb0_cfifoctr_bit +{ + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; +}; + +union un_usb0_cfifoctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_cfifoctr_bit BIT; +#endif +}; + +struct st_usb0_d0fifosel_bit +{ + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; +}; + +union un_usb0_d0fifosel +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_d0fifosel_bit BIT; +#endif +}; + +struct st_usb0_d0fifoctr_bit +{ + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; +}; + +union un_usb0_d0fifoctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_d0fifoctr_bit BIT; +#endif +}; + +struct st_usb0_d1fifosel_bit +{ + unsigned short RCNT:1; + unsigned short REW:1; + unsigned short DCLRM:1; + unsigned short DREQE:1; + unsigned short :1; + unsigned short MBW:1; + unsigned short :1; + unsigned short BIGEND:1; + unsigned short :4; + unsigned short CURPIPE:4; +}; + +union un_usb0_d1fifosel +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_d1fifosel_bit BIT; +#endif +}; + +struct st_usb0_d1fifoctr_bit +{ + unsigned short BVAL:1; + unsigned short BCLR:1; + unsigned short FRDY:1; + unsigned short :4; + unsigned short DTLN:9; +}; + +union un_usb0_d1fifoctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_d1fifoctr_bit BIT; +#endif +}; + +struct st_usb0_intenb0_bit +{ + unsigned short VBSE:1; + unsigned short RSME:1; + unsigned short SOFE:1; + unsigned short DVSE:1; + unsigned short CTRE:1; + unsigned short BEMPE:1; + unsigned short NRDYE:1; + unsigned short BRDYE:1; + unsigned short :8; +}; + +union un_usb0_intenb0 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_intenb0_bit BIT; +#endif +}; + +struct st_usb0_intenb1_bit +{ + unsigned short OVRCRE:1; + unsigned short BCHGE:1; + unsigned short :1; + unsigned short DTCHE:1; + unsigned short ATTCHE:1; + unsigned short :4; + unsigned short EOFERRE:1; + unsigned short SIGNE:1; + unsigned short SACKE:1; + unsigned short :4; +}; + +union un_usb0_intenb1 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_intenb1_bit BIT; +#endif +}; + +struct st_usb0_brdyenb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif +}; + +union un_usb0_brdyenb +{ + unsigned short WORD; + struct st_usb0_brdyenb_bit BIT; +}; + +struct st_usb0_nrdyenb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif +}; + +union un_usb0_nrdyenb +{ + unsigned short WORD; + struct st_usb0_nrdyenb_bit BIT; +}; + +struct st_usb0_bempenb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif +}; + +union un_usb0_bempenb +{ + unsigned short WORD; + struct st_usb0_bempenb_bit BIT; +}; + +struct st_usb0_sofcfg_bit +{ + unsigned short :7; + unsigned short TRNENSEL:1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :1; + unsigned short EDGESTS:1; + unsigned short :4; +}; + +union un_usb0_sofcfg +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_sofcfg_bit BIT; +#endif +}; + +struct st_usb0_intsts0_bit +{ + unsigned short VBINT:1; + unsigned short RESM:1; + unsigned short SOFR:1; + unsigned short DVST:1; + unsigned short CTRT:1; + unsigned short BEMP:1; + unsigned short NRDY:1; + unsigned short BRDY:1; + unsigned short VBSTS:1; + unsigned short DVSQ:3; + unsigned short VALID:1; + unsigned short CTSQ:3; +}; + +union un_usb0_intsts0 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_intsts0_bit BIT; +#endif +}; + +struct st_usb0_intsts1_bit +{ + unsigned short OVRCR:1; + unsigned short BCHG:1; + unsigned short :1; + unsigned short DTCH:1; + unsigned short ATTCH:1; + unsigned short :4; + unsigned short EOFERR:1; + unsigned short SIGN:1; + unsigned short SACK:1; + unsigned short :4; +}; + +union un_usb0_intsts1 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_intsts1_bit BIT; +#endif +}; + +struct st_usb0_brdysts_bit +{ + unsigned short :6; + unsigned short PIPE9BRDY:1; + unsigned short PIPE8BRDY:1; + unsigned short PIPE7BRDY:1; + unsigned short PIPE6BRDY:1; + unsigned short PIPE5BRDY:1; + unsigned short PIPE4BRDY:1; + unsigned short PIPE3BRDY:1; + unsigned short PIPE2BRDY:1; + unsigned short PIPE1BRDY:1; + unsigned short PIPE0BRDY:1; +}; + +union un_usb0_brdysts +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_brdysts_bit BIT; +#endif +}; + +struct st_usb0_nrdysts_bit +{ + unsigned short :6; + unsigned short PIPE9NRDY:1; + unsigned short PIPE8NRDY:1; + unsigned short PIPE7NRDY:1; + unsigned short PIPE6NRDY:1; + unsigned short PIPE5NRDY:1; + unsigned short PIPE4NRDY:1; + unsigned short PIPE3NRDY:1; + unsigned short PIPE2NRDY:1; + unsigned short PIPE1NRDY:1; + unsigned short PIPE0NRDY:1; +}; + +union un_usb0_nrdysts +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_nrdysts_bit BIT; +#endif +}; + +struct st_usb0_bempsts_bit +{ + unsigned short :6; + unsigned short PIPE9BEMP:1; + unsigned short PIPE8BEMP:1; + unsigned short PIPE7BEMP:1; + unsigned short PIPE6BEMP:1; + unsigned short PIPE5BEMP:1; + unsigned short PIPE4BEMP:1; + unsigned short PIPE3BEMP:1; + unsigned short PIPE2BEMP:1; + unsigned short PIPE1BEMP:1; + unsigned short PIPE0BEMP:1; +}; + +union un_usb0_bempsts +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_bempsts_bit BIT; +#endif +}; + +struct st_usb0_frmnum_bit +{ + unsigned short OVRN:1; + unsigned short CRCE:1; + unsigned short :3; + unsigned short FRNM:11; +}; + +union un_usb0_frmnum +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_frmnum_bit BIT; +#endif +}; + +struct st_usb0_dvchgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short DVCHG : 1; +#else + unsigned short DVCHG : 1; + unsigned short : 15; +#endif +}; + +union un_usb0_dvchgr +{ + unsigned short WORD; + struct st_usb0_dvchgr_bit BIT; +}; + +struct st_usb0_usbaddr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short USBADDR : 7; + unsigned short : 1; + unsigned short STSRECOV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short STSRECOV : 4; + unsigned short : 1; + unsigned short USBADDR : 7; +#endif +}; + +union un_usb0_usbaddr +{ + unsigned short WORD; + struct st_usb0_usbaddr_bit BIT; +}; + +struct st_usb0_usbreq_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif +}; + +union un_usb0_usbreq +{ + unsigned short WORD; + struct st_usb0_usbreq_bit BIT; +}; + +struct st_usb0_dcpcfg_bit +{ + unsigned short :8; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short :4; +}; + +union un_usb0_dcpcfg +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_dcpcfg_bit BIT; +#endif +}; + +struct st_usb0_dcpmaxp_bit +{ + unsigned short DEVSEL:4; + unsigned short :5; + unsigned short MXPS:7; +}; + +union un_usb0_dcpmaxp +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_dcpmaxp_bit BIT; +#endif +}; + +struct st_usb0_dcpctr_bit +{ + unsigned short BSTS:1; + unsigned short SUREQ:1; + unsigned short :2; + unsigned short SUREQCLR:1; + unsigned short :2; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :2; + unsigned short CCPL:1; + unsigned short PID:2; +}; + +union un_usb0_dcpctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_dcpctr_bit BIT; +#endif +}; + +struct st_usb0_pipesel_bit +{ + unsigned short :12; + unsigned short PIPESEL:4; +}; + +union un_usb0_pipesel +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipesel_bit BIT; +#endif +}; + +struct st_usb0_pipecfg_bit +{ + unsigned short TYPE:2; + unsigned short :3; + unsigned short BFRE:1; + unsigned short DBLB:1; + unsigned short :1; + unsigned short SHTNAK:1; + unsigned short :2; + unsigned short DIR:1; + unsigned short EPNUM:4; +}; + +union un_usb0_pipecfg +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipecfg_bit BIT; +#endif +}; + +struct st_usb0_pipemaxp_bit +{ + unsigned short DEVSEL:4; + unsigned short :3; + unsigned short MXPS:9; +}; + +union un_usb0_pipemaxp +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipemaxp_bit BIT; +#endif +}; + +struct st_usb0_pipeperi_bit +{ + unsigned short :3; + unsigned short IFIS:1; + unsigned short :9; + unsigned short IITV:3; +}; + +union un_usb0_pipeperi +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipeperi_bit BIT; +#endif +}; + +struct st_usb0_pipe1ctr_bit +{ + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe1ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe1ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe2ctr_bit +{ + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe2ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe2ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe3ctr_bit +{ + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe3ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe3ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe4ctr_bit +{ + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe4ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe4ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe5ctr_bit +{ + unsigned short BSTS:1; + unsigned short INBUFM:1; + unsigned short :3; + unsigned short ATREPM:1; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe5ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe5ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe6ctr_bit +{ + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe6ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe6ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe7ctr_bit +{ + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe7ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe7ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe8ctr_bit +{ + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe8ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe8ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe9ctr_bit +{ + unsigned short BSTS:1; + unsigned short :5; + unsigned short ACLRM:1; + unsigned short SQCLR:1; + unsigned short SQSET:1; + unsigned short SQMON:1; + unsigned short PBUSY:1; + unsigned short :3; + unsigned short PID:2; +}; + +union un_usb0_pipe9ctr +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe9ctr_bit BIT; +#endif +}; + +struct st_usb0_pipe1tre_bit +{ + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; +}; + +union un_usb0_pipe1tre +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe1tre_bit BIT; +#endif +}; + +struct st_usb0_pipe2tre_bit +{ + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; +}; + +union un_usb0_pipe2tre +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe2tre_bit BIT; +#endif +}; + +struct st_usb0_pipe3tre_bit +{ + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; +}; + +union un_usb0_pipe3tre +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe3tre_bit BIT; +#endif +}; + +struct st_usb0_pipe4tre_bit +{ + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; +}; + +union un_usb0_pipe4tre +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe4tre_bit BIT; +#endif +}; + +struct st_usb0_pipe5tre_bit +{ + unsigned short :6; + unsigned short TRENB:1; + unsigned short TRCLR:1; + unsigned short :8; +}; + +union un_usb0_pipe5tre +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_pipe5tre_bit BIT; +#endif +}; + +struct st_usb0_devadd0_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd0 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd0_bit BIT; +#endif +}; + +struct st_usb0_devadd1_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd1 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd1_bit BIT; +#endif +}; + +struct st_usb0_devadd2_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd2 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd2_bit BIT; +#endif +}; + +struct st_usb0_devadd3_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd3 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd3_bit BIT; +#endif +}; + +struct st_usb0_devadd4_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd4 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd4_bit BIT; +#endif +}; + +struct st_usb0_devadd5_bit +{ + unsigned short :8; + unsigned short USBSPD:2; + unsigned short :6; +}; + +union un_usb0_devadd5 +{ + unsigned short WORD; +#ifdef IODEFINE_H_HISTORY + struct st_usb0_devadd5_bit BIT; +#endif +}; + +struct st_usb0_physlew_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SLEWR00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWF01 : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long SLEWF01 : 1; + unsigned long SLEWF00 : 1; + unsigned long SLEWR01 : 1; + unsigned long SLEWR00 : 1; +#endif +}; + +union un_usb0_physlew +{ + unsigned long LONG; + struct st_usb0_physlew_bit BIT; +}; + +struct st_wdt_wdtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif +}; + +union un_wdt_wdtcr +{ + unsigned short WORD; + struct st_wdt_wdtcr_bit BIT; +}; + +struct st_wdt_wdtsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif +}; + +union un_wdt_wdtsr +{ + unsigned short WORD; + struct st_wdt_wdtsr_bit BIT; +}; + +struct st_wdt_wdtrcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif +}; + +union un_wdt_wdtrcr +{ + unsigned char BYTE; + struct st_wdt_wdtrcr_bit BIT; +}; + +struct st_crc_crccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 3; + unsigned char : 3; + unsigned char LMS : 1; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char LMS : 1; + unsigned char : 3; + unsigned char GPS : 3; +#endif +}; + +union un_crc_crccr +{ + unsigned char BYTE; + struct st_crc_crccr_bit BIT; +}; + +union un_crc_crcdir +{ + unsigned long LONG; + unsigned char BYTE; +}; + +union un_crc_crcdor +{ + unsigned long LONG; + unsigned short WORD; + unsigned char BYTE; +}; + +struct st_da_dacr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char DAE : 1; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char DAE : 1; + unsigned char : 5; +#endif +}; + +union un_da_dacr +{ + unsigned char BYTE; + struct st_da_dacr_bit BIT; +}; + +struct st_da_dadpr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif +}; + +union un_da_dadpr +{ + unsigned char BYTE; + struct st_da_dadpr_bit BIT; +}; + +struct st_da_daadscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif +}; + +union un_da_daadscr +{ + unsigned char BYTE; + struct st_da_daadscr_bit BIT; +}; + +struct st_da_daampcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAAMP0 : 1; + unsigned char DAAMP1 : 1; +#else + unsigned char DAAMP1 : 1; + unsigned char DAAMP0 : 1; + unsigned char : 6; +#endif +}; + +union un_da_daampcr +{ + unsigned char BYTE; + struct st_da_daampcr_bit BIT; +}; + +struct st_da_daaswcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAASW0 : 1; + unsigned char DAASW1 : 1; +#else + unsigned char DAASW1 : 1; + unsigned char DAASW0 : 1; + unsigned char : 6; +#endif +}; + +union un_da_daaswcr +{ + unsigned char BYTE; + struct st_da_daaswcr_bit BIT; +}; + +struct st_da_daadusr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char AMADSEL1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char AMADSEL1 : 1; + unsigned char : 1; +#endif +}; + +union un_da_daadusr +{ + unsigned char BYTE; + struct st_da_daadusr_bit BIT; +}; + +struct st_doc_docr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif +}; + +union un_doc_docr +{ + unsigned char BYTE; + struct st_doc_docr_bit BIT; +}; + +struct st_mtu_toera_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif +}; + +union un_mtu_toera +{ + unsigned char BYTE; + struct st_mtu_toera_bit BIT; +}; + +struct st_mtu_tgcra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif +}; + +union un_mtu_tgcra +{ + unsigned char BYTE; + struct st_mtu_tgcra_bit BIT; +}; + +struct st_mtu_tocr1a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif +}; + +union un_mtu_tocr1a +{ + unsigned char BYTE; + struct st_mtu_tocr1a_bit BIT; +}; + +struct st_mtu_tocr2a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif +}; + +union un_mtu_tocr2a +{ + unsigned char BYTE; + struct st_mtu_tocr2a_bit BIT; +}; + +struct st_mtu_titcr1a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif +}; + +union un_mtu_titcr1a +{ + unsigned char BYTE; + struct st_mtu_titcr1a_bit BIT; +}; + +struct st_mtu_titcnt1a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif +}; + +union un_mtu_titcnt1a +{ + unsigned char BYTE; + struct st_mtu_titcnt1a_bit BIT; +}; + +struct st_mtu_tbtera_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif +}; + +union un_mtu_tbtera +{ + unsigned char BYTE; + struct st_mtu_tbtera_bit BIT; +}; + +struct st_mtu_tdera_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif +}; + +union un_mtu_tdera +{ + unsigned char BYTE; + struct st_mtu_tdera_bit BIT; +}; + +struct st_mtu_tolbra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif +}; + +union un_mtu_tolbra +{ + unsigned char BYTE; + struct st_mtu_tolbra_bit BIT; +}; + +struct st_mtu_titmra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif +}; + +union un_mtu_titmra +{ + unsigned char BYTE; + struct st_mtu_titmra_bit BIT; +}; + +struct st_mtu_titcr2a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4COR : 3; + unsigned char : 5; + #else + unsigned char : 5; + unsigned char TRG4COR : 3; +#endif +}; + +union un_mtu_titcr2a +{ + unsigned char BYTE; + struct st_mtu_titcr2a_bit BIT; +}; + +struct st_mtu_titcnt2a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG4CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG4CNT : 3; +#endif +}; + +union un_mtu_titcnt2a +{ + unsigned char BYTE; + struct st_mtu_titcnt2a_bit BIT; +}; + +struct st_mtu_twcra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif +}; + +union un_mtu_twcra +{ + unsigned char BYTE; + struct st_mtu_twcra_bit BIT; +}; + +struct st_mtu_tmdr2a_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif +}; + +union un_mtu_tmdr2a +{ + unsigned char BYTE; + struct st_mtu_tmdr2a_bit BIT; +}; + +struct st_mtu_tstra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST8 : 1; + unsigned char : 2; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 2; + unsigned char CST8 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif +}; + +union un_mtu_tstra +{ + unsigned char BYTE; + struct st_mtu_tstra_bit BIT; +}; + +struct st_mtu_tsyra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif +}; + +union un_mtu_tsyra +{ + unsigned char BYTE; + struct st_mtu_tsyra_bit BIT; +}; + +struct st_mtu_tcsystr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCH7 : 1; + unsigned char SCH6 : 1; + unsigned char : 1; + unsigned char SCH4 : 1; + unsigned char SCH3 : 1; + unsigned char SCH2 : 1; + unsigned char SCH1 : 1; + unsigned char SCH0 : 1; +#else + unsigned char SCH0 : 1; + unsigned char SCH1 : 1; + unsigned char SCH2 : 1; + unsigned char SCH3 : 1; + unsigned char SCH4 : 1; + unsigned char : 1; + unsigned char SCH6 : 1; + unsigned char SCH7 : 1; +#endif +}; + +union un_mtu_tcsystr +{ + unsigned char BYTE; + struct st_mtu_tcsystr_bit BIT; +}; + +struct st_mtu_trwera_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif +}; + +union un_mtu_trwera +{ + unsigned char BYTE; + struct st_mtu_trwera_bit BIT; +}; + +struct st_mtu_toerb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE6B : 1; + unsigned char OE7A : 1; + unsigned char OE7B : 1; + unsigned char OE6D : 1; + unsigned char OE7C : 1; + unsigned char OE7D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE7D : 1; + unsigned char OE7C : 1; + unsigned char OE6D : 1; + unsigned char OE7B : 1; + unsigned char OE7A : 1; + unsigned char OE6B : 1; +#endif +}; + +union un_mtu_toerb +{ + unsigned char BYTE; + struct st_mtu_toerb_bit BIT; +}; + +struct st_mtu_tocr1b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif +}; + +union un_mtu_tocr1b +{ + unsigned char BYTE; + struct st_mtu_tocr1b_bit BIT; +}; + +struct st_mtu_tocr2b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif +}; + +union un_mtu_tocr2b +{ + unsigned char BYTE; + struct st_mtu_tocr2b_bit BIT; +}; + +struct st_mtu_titcr1b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCOR : 3; + unsigned char T7VEN : 1; + unsigned char T6ACOR : 3; + unsigned char T6AEN : 1; +#else + unsigned char T6AEN : 1; + unsigned char T6ACOR : 3; + unsigned char T7VEN : 1; + unsigned char T7VCOR : 3; +#endif +}; + +union un_mtu_titcr1b +{ + unsigned char BYTE; + struct st_mtu_titcr1b_bit BIT; +}; + +struct st_mtu_titcnt1b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T7VCNT : 3; + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T6ACNT : 3; + unsigned char : 1; + unsigned char T7VCNT : 3; +#endif +}; + +union un_mtu_titcnt1b +{ + unsigned char BYTE; + struct st_mtu_titcnt1b_bit BIT; +}; + +struct st_mtu_tbterb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif +}; + +union un_mtu_tbterb +{ + unsigned char BYTE; + struct st_mtu_tbterb_bit BIT; +}; + +struct st_mtu_tderb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif +}; + +union un_mtu_tderb +{ + unsigned char BYTE; + struct st_mtu_tderb_bit BIT; +}; + +struct st_mtu_tolbrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif +}; + +union un_mtu_tolbrb +{ + unsigned char BYTE; + struct st_mtu_tolbrb_bit BIT; +}; + +struct st_mtu_titmrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TITM : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TITM : 1; +#endif +}; + +union un_mtu_titmrb +{ + unsigned char BYTE; + struct st_mtu_titmrb_bit BIT; +}; + +struct st_mtu_titcr2b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7COR : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7COR : 3; +#endif +}; + +union un_mtu_titcr2b +{ + unsigned char BYTE; + struct st_mtu_titcr2b_bit BIT; +}; + +struct st_mtu_titcnt2b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRG7CNT : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TRG7CNT : 3; +#endif +}; + +union un_mtu_titcnt2b +{ + unsigned char BYTE; + struct st_mtu_titcnt2b_bit BIT; +}; + +struct st_mtu_twcrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char SCC : 1; + unsigned char : 5; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 5; + unsigned char SCC : 1; + unsigned char WRE : 1; +#endif +}; + +union un_mtu_twcrb +{ + unsigned char BYTE; + struct st_mtu_twcrb_bit BIT; +}; + +struct st_mtu_tmdr2b_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DRS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DRS : 1; +#endif +}; + +union un_mtu_twdr2b +{ + unsigned char BYTE; + struct st_mtu_tmdr2b_bit BIT; +}; + +struct st_mtu_tstrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char CST6 : 1; + unsigned char CST7 : 1; +#else + unsigned char CST7 : 1; + unsigned char CST6 : 1; + unsigned char : 6; +#endif +}; + +union un_mtu_tstrb +{ + unsigned char BYTE; + struct st_mtu_tstrb_bit BIT; +}; + +struct st_mtu_tsyrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char SYNC6 : 1; + unsigned char SYNC7 : 1; +#else + unsigned char SYNC7 : 1; + unsigned char SYNC6 : 1; + unsigned char : 6; +#endif +}; + +union un_mtu_tsyrb +{ + unsigned char BYTE; + struct st_mtu_tsyrb_bit BIT; +}; + +struct st_mtu_trwerb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif +}; + +union un_mtu_trwerb +{ + unsigned char BYTE; + struct st_mtu_trwerb_bit BIT; +}; + +struct st_mtu0_nfcro_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu0_nfcro +{ + unsigned char BYTE; + struct st_mtu0_nfcro_bit BIT; +}; + +struct st_mtu0_nfcrc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu0_nfcrc +{ + unsigned char BYTE; + struct st_mtu0_nfcrc_bit BIT; +}; + +struct st_mtu0_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu0_tcr +{ + unsigned char BYTE; + struct st_mtu0_tcr_bit BIT; +}; + +struct st_mtu0_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu0_tmdr1 +{ + unsigned char BYTE; + struct st_mtu0_tmdr1_bit BIT; +}; + +struct st_mtu0_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu0_tiorh +{ + unsigned char BYTE; + struct st_mtu0_tiorh_bit BIT; +}; + +struct st_mtu0_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu0_tiorl +{ + unsigned char BYTE; + struct st_mtu0_tiorl_bit BIT; +}; + +struct st_mtu0_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu0_tier +{ + unsigned char BYTE; + struct st_mtu0_tier_bit BIT; +}; + +struct st_mtu0_tier2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 5; + unsigned char TTGE2 : 1; +#else + unsigned char TTGE2 : 1; + unsigned char : 5; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif +}; + +union un_mtu0_tier2 +{ + unsigned char BYTE; + struct st_mtu0_tier2_bit BIT; +}; + +struct st_mtu0_tbtm_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif +}; + +union un_mtu0_tbtm +{ + unsigned char BYTE; + struct st_mtu0_tbtm_bit BIT; +}; + +struct st_mtu0_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu0_tcr2 +{ + unsigned char BYTE; + struct st_mtu0_tcr2_bit BIT; +}; + +struct st_mtu1_nfcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu1_nfcr1 +{ + unsigned char BYTE; + struct st_mtu1_nfcr1_bit BIT; +}; + +struct st_mtu1_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu1_tcr +{ + unsigned char BYTE; + struct st_mtu1_tcr_bit BIT; +}; + +struct st_mtu1_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif +}; + +union un_mtu1_tmdr1 +{ + unsigned char BYTE; + struct st_mtu1_tmdr1_bit BIT; +}; + +struct st_mtu1_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; + #else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu1_tior +{ + unsigned char BYTE; + struct st_mtu1_tior_bit BIT; +}; + +struct st_mtu1_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu1_tier +{ + unsigned char BYTE; + struct st_mtu1_tier_bit BIT; +}; + +struct st_mtu1_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; +union un_mtu1_tsr +{ + unsigned char BYTE; + struct st_mtu1_tsr_bit BIT; +}; + +struct st_mtu1_ticcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif +}; + +union un_mtu1_ticcr +{ + unsigned char BYTE; + struct st_mtu1_ticcr_bit BIT; +}; + +struct st_mtu1_tmdr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LWA : 1; + unsigned char PHCKSEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PHCKSEL : 1; + unsigned char LWA : 1; +#endif +}; + +union un_mtu1_tmdr3 +{ + unsigned char BYTE; + struct st_mtu1_tmdr3_bit BIT; +}; + +struct st_mtu1_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu1_tcr2 +{ + unsigned char BYTE; + struct st_mtu1_tcr2_bit BIT; +}; +struct st_mtu2_nfcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu2_nfcr2 +{ + unsigned char BYTE; + struct st_mtu2_nfcr2_bit BIT; +}; + +struct st_mtu2_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu2_tcr +{ + unsigned char BYTE; + struct st_mtu2_tcr_bit BIT; +}; + +struct st_mtu2_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif +}; + +union un_mtu2_tmdr1 +{ + unsigned char BYTE; + struct st_mtu2_tmdr1_bit BIT; +}; + +struct st_mtu2_tior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu2_tior +{ + unsigned char BYTE; + struct st_mtu2_tior_bit BIT; +}; + +struct st_mtu2_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu2_tier +{ + unsigned char BYTE; + struct st_mtu2_tier_bit BIT; +}; + +struct st_mtu2_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; + +union un_mtu2_tsr +{ + unsigned char BYTE; + struct st_mtu2_tsr_bit BIT; +}; + +struct st_mtu2_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char PCB : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PCB : 2; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu2_tcr2 +{ + unsigned char BYTE; + struct st_mtu2_tcr2_bit BIT; +}; + +struct st_mtu3_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu3_tcr +{ + unsigned char BYTE; + struct st_mtu3_tcr_bit BIT; +}; + +struct st_mtu3_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu3_tmdr1 +{ + unsigned char BYTE; + struct st_mtu3_tmdr1_bit BIT; +}; + +struct st_mtu3_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu3_tiorh +{ + unsigned char BYTE; + struct st_mtu3_tiorh_bit BIT; +}; + +struct st_mtu3_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu3_tiorl +{ + unsigned char BYTE; + struct st_mtu3_tiorl_bit BIT; +}; + +struct st_mtu3_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu3_tier +{ + unsigned char BYTE; + struct st_mtu3_tier_bit BIT; +}; + +struct st_mtu3_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; + +union un_mtu3_tsr +{ + unsigned char BYTE; + struct st_mtu3_tsr_bit BIT; +}; + +struct st_mtu3_tbtm_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif +}; + +union un_mtu3_tbtm +{ + unsigned char BYTE; + struct st_mtu3_tbtm_bit BIT; +}; + +struct st_mtu3_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu3_tcr2 +{ + unsigned char BYTE; + struct st_mtu3_tcr2_bit BIT; +}; + +struct st_mtu3_nfcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu3_nfcr3 +{ + unsigned char BYTE; + struct st_mtu3_nfcr3_bit BIT; +}; + +struct st_iwdt_iwdtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif +}; + +union un_iwdt_iwdtcr +{ + unsigned short WORD; + struct st_iwdt_iwdtcr_bit BIT; +}; + +struct st_iwdt_iwdtsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif +}; + +union un_iwdt_iwdtsr +{ + unsigned short WORD; + struct st_iwdt_iwdtsr_bit BIT; +}; + +struct st_iwdt_iwdtrcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif +}; + +union un_iwdt_iwdtrcr +{ + unsigned char BYTE; + struct st_iwdt_iwdtrcr_bit BIT; +}; + +struct st_iwdt_iwdtcstpr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif +}; + +union un_iwdt_iwdtcstpr +{ + unsigned char BYTE; + struct st_iwdt_iwdtcstpr_bit BIT; +}; + +struct st_mpu_rspage0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage0 +{ + unsigned long LONG; + struct st_mpu_rspage0_bit BIT; +}; + +struct st_mpu_repage0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage0 +{ + unsigned long LONG; + struct st_mpu_repage0_bit BIT; +}; + +struct st_mpu_rspage1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage1 +{ + unsigned long LONG; + struct st_mpu_rspage1_bit BIT; +}; + +struct st_mpu_repage1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; +union un_mpu_repage1 +{ + unsigned long LONG; + struct st_mpu_repage1_bit BIT; +}; + +struct st_mpu_rspage2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage2 +{ + unsigned long LONG; + struct st_mpu_rspage2_bit BIT; +}; + +struct st_mpu_repage2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage2 +{ + unsigned long LONG; + struct st_mpu_repage2_bit BIT; +}; + +struct st_mpu_rspage3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage3 +{ + unsigned long LONG; + struct st_mpu_rspage3_bit BIT; +}; + +struct st_mpu_repage3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage3 +{ + unsigned long LONG; + struct st_mpu_repage3_bit BIT; +}; + +struct st_mpu_rspage4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage4 +{ + unsigned long LONG; + struct st_mpu_rspage4_bit BIT; +}; + +struct st_mpu_repage4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage4 +{ + unsigned long LONG; + struct st_mpu_repage4_bit BIT; +}; + +struct st_mpu_rspage5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage5 +{ + unsigned long LONG; + struct st_mpu_rspage5_bit BIT; +}; + +struct st_mpu_repage5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage5 +{ + unsigned long LONG; + struct st_mpu_repage5_bit BIT; +}; + +struct st_mpu_rspage6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage6 +{ + unsigned long LONG; + struct st_mpu_rspage6_bit BIT; +}; + +struct st_mpu_repage6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage6 +{ + unsigned long LONG; + struct st_mpu_repage6_bit BIT; +}; + +struct st_mpu_rspage7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif +}; + +union un_mpu_rspage7 +{ + unsigned long LONG; + struct st_mpu_rspage7_bit BIT; +}; + +struct st_mpu_repage7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif +}; + +union un_mpu_repage7 +{ + unsigned long LONG; + struct st_mpu_repage7_bit BIT; +}; + +struct st_mpu_mpen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif +}; + +union un_mpu_mpen +{ + unsigned long LONG; + struct st_mpu_mpen_bit BIT; +}; + +struct st_mpu_mpbac_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif +}; + +union un_mpu_mpbac +{ + unsigned long LONG; + struct st_mpu_mpbac_bit BIT; +}; + +struct st_mpu_mpeclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif +}; + +union un_mpu_mpeclr +{ + unsigned long LONG; + struct st_mpu_mpeclr_bit BIT; +}; + +struct st_mpu_mpests_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif +}; + +union un_mpu_mpests +{ + unsigned long LONG; + struct st_mpu_mpests_bit BIT; +}; + +struct st_mpu_mpdea_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif +}; + +union un_mpu_mpdea +{ + unsigned long LONG; + struct st_mpu_mpdea_bit BIT; +}; + +struct st_mpu_mpsa_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif +}; + +union un_mpu_mpsa +{ + unsigned long LONG; + struct st_mpu_mpsa_bit BIT; +}; + +struct st_mpu_mpops_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif +}; + +union un_mpu_mpops +{ + unsigned short WORD; + struct st_mpu_mpops_bit BIT; +}; + +struct st_mpu_mpopi_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif +}; + +union un_mpu_mpopi +{ + unsigned short WORD; + struct st_mpu_mpopi_bit BIT; +}; + +struct st_mpu_mhiti_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif +}; + +union un_mpu_mhiti +{ + unsigned long LONG; + struct st_mpu_mhiti_bit BIT; +}; + +struct st_mpu_mhitd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif +}; + +union un_mpu_mhitd +{ + unsigned long LONG; + struct st_mpu_mhitd_bit BIT; +}; + +struct st_mmcif_cecmdset_bit +{ + unsigned long :1; + unsigned long BOOT:1; + unsigned long CMD:6; + unsigned long RTYP:2; + unsigned long RBSY:1; + unsigned long :1; + unsigned long WDAT:1; + unsigned long DWEN:1; + unsigned long CMLTE:1; + unsigned long CMD12EN:1; + unsigned long RIDXC:2; + unsigned long RCRC7C:2; + unsigned long :1; + unsigned long CRC16C:1; + unsigned long BOOTACK:1; + unsigned long CRCSTE:1; + unsigned long TBIT:1; + unsigned long OPDM:1; + unsigned long :2; + unsigned long SBIT:1; + unsigned long :1; + unsigned long DATW:2; +}; + +union un_mmcif_cecmdset +{ + unsigned long LONG; + struct st_mmcif_cecmdset_bit BIT; +}; + +union un_mmcif_cearg +{ + unsigned long LONG; +}; + +struct st_mmcif_ceargcmd12_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long C12ARG : 32; +#else + unsigned long C12ARG : 32; +#endif +}; + +union un_mmcif_ceargcmd12 +{ + unsigned long LONG; + struct st_mmcif_ceargcmd12_bit BIT; +}; + +struct st_mmcif_cecmdctrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BREAK : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long BREAK : 1; +#endif +}; + +union un_mmcif_cecmdctrl +{ + unsigned long LONG; + struct st_mmcif_cecmdctrl_bit BIT; +}; + +struct st_mmcif_ceblockset_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BLKSIZ : 16; + unsigned long BLKCNT : 16; +#else + unsigned long BLKCNT : 16; + unsigned long BLKSIZ : 16; +#endif +}; + +union un_mmcif_ceblockset +{ + unsigned long LONG; + struct st_mmcif_ceblockset_bit BIT; +}; + +struct st_mmcif_ceclkctrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long SRWDTO : 4; + unsigned long SRBSYTO : 4; + unsigned long SRSPTO : 2; + unsigned long : 2; + unsigned long CLKDIV : 4; + unsigned long : 4; + unsigned long CLKEN : 1; + unsigned long : 6; + unsigned long MMCBUSBSY : 1; +#else + unsigned long MMCBUSBSY : 1; + unsigned long : 6; + unsigned long CLKEN : 1; + unsigned long : 4; + unsigned long CLKDIV : 4; + unsigned long : 2; + unsigned long SRSPTO : 2; + unsigned long SRBSYTO : 4; + unsigned long SRWDTO : 4; + unsigned long : 4; +#endif +}; + +union un_mmcif_ceclkctrl +{ + unsigned long LONG; + struct st_mmcif_ceclkctrl_bit BIT; +}; + +struct st_mmcif_cebufacc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long ATYP : 1; + unsigned long : 7; + unsigned long DMAREN : 1; + unsigned long DMAWEN : 1; + unsigned long DMATYP : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long DMATYP : 1; + unsigned long DMAWEN : 1; + unsigned long DMAREN : 1; + unsigned long : 7; + unsigned long ATYP : 1; + unsigned long : 16; +#endif +}; + +union un_mmcif_cebufacc +{ + unsigned long LONG; + struct st_mmcif_cebufacc_bit BIT; +}; + +struct st_mmcif_cerespcmd12_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSP12 : 32; +#else + unsigned long RSP12 : 32; +#endif +}; + +union un_mmcif_cerespcmd12 +{ + unsigned long LONG; + struct st_mmcif_cerespcmd12_bit BIT; +}; + +struct st_mmcif_cedata_bit +{ + unsigned long DATA:32; +}; + +union un_mmcif_cedata +{ + unsigned long LONG; + struct st_mmcif_cedata_bit BIT; +}; + +struct st_mmcif_ceboot_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long SBTDATTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTACKTO : 4; + unsigned long SBTCLKDIV : 4; +#else + unsigned long SBTCLKDIV : 4; + unsigned long SBTACKTO : 4; + unsigned long SFSTBTDATTO : 4; + unsigned long SBTDATTO : 4; + unsigned long : 16; +#endif +}; + +union un_mmcif_ceboot +{ + unsigned long LONG; + struct st_mmcif_ceboot_bit BIT; +}; + +struct st_mmcif_ceint_bit +{ + unsigned long :5; + unsigned long CMD12DRE:1; + unsigned long CMD12RBE:1; + unsigned long CMD12CRE:1; + unsigned long DTRANE:1; + unsigned long BUFRE:1; + unsigned long BUFWEN:1; + unsigned long BUFREN:1; + unsigned long :2; + unsigned long RBSYE:1; + unsigned long CRSPE:1; + unsigned long CMDVIO:1; + unsigned long BUFVIO:1; + unsigned long :2; + unsigned long WDATERR:1; + unsigned long RDATERR:1; + unsigned long RIDXERR:1; + unsigned long RSPERR:1; + unsigned long :3; + unsigned long CRCSTO:1; + unsigned long WDATTO:1; + unsigned long RDATTO:1; + unsigned long RBSYTO:1; + unsigned long RSPTO:1; +}; + +union un_mmcif_ceint +{ + unsigned long LONG; + struct st_mmcif_ceint_bit BIT; +}; + +struct st_mmcif_ceinten_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MRSPTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRDATTO : 1; + unsigned long MWDATTO : 1; + unsigned long MCRCSTO : 1; + unsigned long : 3; + unsigned long MRSPERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRDATERR : 1; + unsigned long MWDATERR : 1; + unsigned long : 2; + unsigned long MBUFVIO : 1; + unsigned long MCMDVIO : 1; + unsigned long MCRSPE : 1; + unsigned long MRBSYE : 1; + unsigned long : 2; + unsigned long MBUFREN : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFRE : 1; + unsigned long MDTRANE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12DRE : 1; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long MCMD12DRE : 1; + unsigned long MCMD12RBE : 1; + unsigned long MCMD12CRE : 1; + unsigned long MDTRANE : 1; + unsigned long MBUFRE : 1; + unsigned long MBUFWEN : 1; + unsigned long MBUFREN : 1; + unsigned long : 2; + unsigned long MRBSYE : 1; + unsigned long MCRSPE : 1; + unsigned long MCMDVIO : 1; + unsigned long MBUFVIO : 1; + unsigned long : 2; + unsigned long MWDATERR : 1; + unsigned long MRDATERR : 1; + unsigned long MRIDXERR : 1; + unsigned long MRSPERR : 1; + unsigned long : 3; + unsigned long MCRCSTO : 1; + unsigned long MWDATTO : 1; + unsigned long MRDATTO : 1; + unsigned long MRBSYTO : 1; + unsigned long MRSPTO : 1; +#endif +}; + +union un_mmcif_ceinten +{ + unsigned long LONG; + struct st_mmcif_ceinten_bit BIT; +}; + +struct st_mmcif_cehoststs1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RCVBLK : 16; + unsigned long DATSIG : 8; + unsigned long RSPIDX : 6; + unsigned long CMDSIG : 1; + unsigned long CMDSEQ : 1; +#else + unsigned long CMDSEQ : 1; + unsigned long CMDSIG : 1; + unsigned long RSPIDX : 6; + unsigned long DATSIG : 8; + unsigned long RCVBLK : 16; +#endif +}; + +union un_mmcif_cehoststs1 +{ + unsigned long LONG; + struct st_mmcif_cehoststs1_bit BIT; +}; + +struct st_mmcif_cehoststs2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 5; + unsigned long BTDATTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTACKTO : 1; + unsigned long STRSPTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long DATBSYTO : 1; + unsigned long STRDATTO : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long BTACKEBE : 1; + unsigned long BTACKPATE : 1; + unsigned long RSPIDXE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RDATEBE : 1; + unsigned long CRCSTEBE : 1; + unsigned long RSPCRC7E : 1; + unsigned long AC12CRCE : 1; + unsigned long CRC16E : 1; + unsigned long CRCSTE : 1; +#else + unsigned long CRCSTE : 1; + unsigned long CRC16E : 1; + unsigned long AC12CRCE : 1; + unsigned long RSPCRC7E : 1; + unsigned long CRCSTEBE : 1; + unsigned long RDATEBE : 1; + unsigned long AC12REBE : 1; + unsigned long RSPEBE : 1; + unsigned long AC12IDXE : 1; + unsigned long RSPIDXE : 1; + unsigned long BTACKPATE : 1; + unsigned long BTACKEBE : 1; + unsigned long : 1; + unsigned long CRCST : 3; + unsigned long : 1; + unsigned long STRDATTO : 1; + unsigned long DATBSYTO : 1; + unsigned long CRCSTTO : 1; + unsigned long AC12BSYTO : 1; + unsigned long RSPBSYTO : 1; + unsigned long AC12RSPTO : 1; + unsigned long STRSPTO : 1; + unsigned long BTACKTO : 1; + unsigned long FSTBTDATTO : 1; + unsigned long BTDATTO : 1; + unsigned long : 5; +#endif +}; + +union un_mmcif_cehoststs2 +{ + unsigned long LONG; + struct st_mmcif_cehoststs2_bit BIT; +}; + +struct st_mmcif_cedetect_bit +{ + unsigned long :17; + unsigned long CDSIG:1; + unsigned long CDRISE:1; + unsigned long CDFALL:1; + unsigned long :6; + unsigned long MCDRISE:1; + unsigned long MCDFALL:1; + unsigned long :4; +}; + +union un_mmcif_cedetect +{ + unsigned long LONG; + struct st_mmcif_cedetect_bit BIT; +}; + +struct st_mmcif_ceaddmode_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 19; + unsigned long CLKMAIN : 1; + unsigned long : 1; + unsigned long RESNOUT : 1; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long RESNOUT : 1; + unsigned long : 1; + unsigned long CLKMAIN : 1; + unsigned long : 19; +#endif +}; + +union un_mmcif_ceaddmode +{ + unsigned long LONG; + struct st_mmcif_ceaddmode_bit BIT; +}; + +struct st_mmcif_ceversion_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VERSION : 16; + unsigned long : 15; + unsigned long SWRST : 1; +#else + unsigned long SWRST : 1; + unsigned long : 15; + unsigned long VERSION : 16; +#endif +}; + +union un_mmcif_ceversion +{ + unsigned long LONG; + struct st_mmcif_ceversion_bit BIT; +}; + +struct st_glcdc_gr1clut0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_glcdc_gr1clut0 +{ + unsigned long LONG; + struct st_glcdc_gr1clut0_bit BIT; +}; + +struct st_glcdc_gr1clut1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_glcdc_gr1clut1 +{ + unsigned long LONG; + struct st_glcdc_gr1clut1_bit BIT; +}; + +struct st_glcdc_gr2clut0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_glcdc_gr2clut0 +{ + unsigned long LONG; + struct st_glcdc_gr2clut0_bit BIT; +}; + +struct st_glcdc_gr2clut1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long A : 8; +#else + unsigned long A : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_glcdc_gr2clut1 +{ + unsigned long LONG; + struct st_glcdc_gr2clut1_bit BIT; +}; + +struct st_glcdc_bgen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long SWRST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SWRST : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long EN : 1; +#endif +}; + +union un_glcdc_bgen +{ + unsigned long LONG; + struct st_glcdc_bgen_bit BIT; +}; + +struct st_glcdc_bgperi_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FH : 11; + unsigned long : 5; + unsigned long FV : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long FV : 11; + unsigned long : 5; + unsigned long FH : 11; +#endif +}; + +union un_glcdc_bgperi +{ + unsigned long LONG; + struct st_glcdc_bgperi_bit BIT; +}; + +struct st_glcdc_bgsync_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HP : 4; + unsigned long : 12; + unsigned long VP : 4; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long VP : 4; + unsigned long : 12; + unsigned long HP : 4; +#endif +}; + +union un_glcdc_bgsync +{ + unsigned long LONG; + struct st_glcdc_bgsync_bit BIT; +}; + +struct st_glcdc_bgvsize_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VP : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VP : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif +}; + +union un_glcdc_bgvsize +{ + unsigned long LONG; + struct st_glcdc_bgvsize_bit BIT; +}; + +struct st_glcdc_bghsize_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HP : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HP : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif +}; + +union un_glcdc_bghsize +{ + unsigned long LONG; + struct st_glcdc_bghsize_bit BIT; +}; + +struct st_glcdc_bgcolor_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_glcdc_bgcolor +{ + unsigned long LONG; + struct st_glcdc_bgcolor_bit BIT; +}; + +struct st_glcdc_bgmon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long SWRST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SWRST : 1; + unsigned long : 7; + unsigned long VEN : 1; + unsigned long : 7; + unsigned long EN : 1; +#endif +}; + +union un_glcdc_bgmon +{ + unsigned long LONG; + struct st_glcdc_bgmon_bit BIT; +}; + +struct st_glcdc_gr1ven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_gr1ven +{ + unsigned long LONG; + struct st_glcdc_gr1ven_bit BIT; +}; + +struct st_glcdc_grlflmrd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RENB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RENB : 1; +#endif +}; + +union un_glcdc_grlflmrd +{ + unsigned long LONG; + struct st_glcdc_grlflmrd_bit BIT; +}; + +struct st_glcdc_grlflm3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long LNOFF : 16; +#else + unsigned long LNOFF : 16; + unsigned long : 16; +#endif +}; + +union un_glcdc_gr1flm3 +{ + unsigned long LONG; + struct st_glcdc_grlflm3_bit BIT; +}; + +struct st_glcdc_grlflm5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DATANUM : 16; + unsigned long LNNUM : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long LNNUM : 11; + unsigned long DATANUM : 16; +#endif +}; + +union un_glcdc_gr1flm5 +{ + unsigned long LONG; + struct st_glcdc_grlflm5_bit BIT; +}; + +struct st_glcdc_grlflm6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 28; + unsigned long FORMAT : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long FORMAT : 3; + unsigned long : 28; +#endif +}; + +union un_glcdc_gr1flm6 +{ + unsigned long LONG; + struct st_glcdc_grlflm6_bit BIT; +}; + +struct st_glcdc_gr1ab1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DISPSEL : 2; + unsigned long : 2; + unsigned long GRCDISPON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long ARCON : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long ARCON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long GRCDISPON : 1; + unsigned long : 2; + unsigned long DISPSEL : 2; +#endif +}; + +union un_glcdc_gr1ab1 +{ + unsigned long LONG; + struct st_glcdc_gr1ab1_bit BIT; +}; + +struct st_glcdc_gr1ab2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCVW : 11; + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; + unsigned long GRCVW : 11; +#endif +}; +union un_glcdc_gr1ab2 +{ + unsigned long LONG; + struct st_glcdc_gr1ab2_bit BIT; +}; + +struct st_glcdc_gr1ab3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCHW : 11; + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; + unsigned long GRCHW : 11; +#endif +}; + +union un_glcdc_gr1ab3 +{ + unsigned long LONG; + struct st_glcdc_gr1ab3_bit BIT; +}; + +struct st_glcdc_gr1ab4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCVW : 11; + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; + unsigned long ARCVW : 11; +#endif +}; + +union un_glcdc_gr1ab4 +{ + unsigned long LONG; + struct st_glcdc_gr1ab4_bit BIT; +}; + +struct st_glcdc_gr1ab5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCHW : 11; + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; + unsigned long ARCHW : 11; +#endif +}; + +union un_glcdc_gr1ab5 +{ + unsigned long LONG; + struct st_glcdc_gr1ab5_bit BIT; +}; + +struct st_glcdc_gr1ab6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCRATE : 8; + unsigned long : 8; + unsigned long ARCCOEF : 9; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ARCCOEF : 9; + unsigned long : 8; + unsigned long ARCRATE : 8; +#endif +}; + +union un_glcdc_gr1ab6 +{ + unsigned long LONG; + struct st_glcdc_gr1ab6_bit BIT; +}; + +struct st_glcdc_gr1ab7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKON : 1; + unsigned long : 15; + unsigned long ARCDEF : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ARCDEF : 8; + unsigned long : 15; + unsigned long CKON : 1; +#endif +}; + +union un_glcdc_gr1ab7 +{ + unsigned long LONG; + struct st_glcdc_gr1ab7_bit BIT; +}; + +struct st_glcdc_gr1ab8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKKR : 8; + unsigned long CKKB : 8; + unsigned long CKKG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CKKG : 8; + unsigned long CKKB : 8; + unsigned long CKKR : 8; +#endif +}; + +union un_glcdc_gr1ab8 +{ + unsigned long LONG; + struct st_glcdc_gr1ab8_bit BIT; +}; + +struct st_glcdc_gr1ab9_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKR : 8; + unsigned long CKB : 8; + unsigned long CKG : 8; + unsigned long CKA : 8; +#else + unsigned long CKA : 8; + unsigned long CKG : 8; + unsigned long CKB : 8; + unsigned long CKR : 8; +#endif +}; + +union un_glcdc_gr1ab9 +{ + unsigned long LONG; + struct st_glcdc_gr1ab9_bit BIT; +}; + +struct st_glcdc_gr1base_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long R : 8; + unsigned long B : 8; + unsigned long G : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long G : 8; + unsigned long B : 8; + unsigned long R : 8; +#endif +}; + +union un_glcdc_gr1base +{ + unsigned long LONG; + struct st_glcdc_gr1base_bit BIT; +}; + +struct st_glcdc_gr1clutint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LINE : 11; + unsigned long : 5; + unsigned long SEL : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SEL : 1; + unsigned long : 5; + unsigned long LINE : 11; +#endif +}; + +union un_glcdc_gr1clutint +{ + unsigned long LONG; + struct st_glcdc_gr1clutint_bit BIT; +}; + +struct st_glcdc_gr1mon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCST : 1; + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; + unsigned long ARCST : 1; +#endif +}; + +union un_glcdc_gr1mon +{ + unsigned long LONG; + struct st_glcdc_gr1mon_bit BIT; +}; + +struct st_glcdc_gr2ven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_gr2ven +{ + unsigned long LONG; + struct st_glcdc_gr2ven_bit BIT; +}; + +struct st_glcdc_gr2flmrd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RENB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RENB : 1; +#endif +}; + +union un_glcdc_gr2flmrd +{ + unsigned long LONG; + struct st_glcdc_gr2flmrd_bit BIT; +}; + +struct st_glcdc_gr2flm3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long LNOFF : 16; +#else + unsigned long LNOFF : 16; + unsigned long : 16; +#endif +}; + +union un_glcdc_gr2flm3 +{ + unsigned long LONG; + struct st_glcdc_gr2flm3_bit BIT; +}; + +struct st_glcdc_gr2flm5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DATANUM : 16; + unsigned long LNNUM : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long LNNUM : 11; + unsigned long DATANUM : 16; +#endif +}; + +union un_glcdc_gr2flm5 +{ + unsigned long LONG; + struct st_glcdc_gr2flm5_bit BIT; +}; + +struct st_glcdc_gr2flm6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 28; + unsigned long FORMAT : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long FORMAT : 3; + unsigned long : 28; +#endif +}; + +union un_glcdc_gr2flm6 +{ + unsigned long LONG; + struct st_glcdc_gr2flm6_bit BIT; +}; + +struct st_glcdc_gr2ab1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DISPSEL : 2; + unsigned long : 2; + unsigned long GRCDISPON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long ARCON : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long ARCON : 1; + unsigned long : 3; + unsigned long ARCDISPON : 1; + unsigned long : 3; + unsigned long GRCDISPON : 1; + unsigned long : 2; + unsigned long DISPSEL : 2; +#endif +}; + +union un_glcdc_gr2ab1 +{ + unsigned long LONG; + struct st_glcdc_gr2ab1_bit BIT; +}; + +struct st_glcdc_gr2ab2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCVW : 11; + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCVS : 11; + unsigned long : 5; + unsigned long GRCVW : 11; +#endif +}; + +union un_glcdc_gr2ab2 +{ + unsigned long LONG; + struct st_glcdc_gr2ab2_bit BIT; +}; + +struct st_glcdc_gr2ab3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GRCHW : 11; + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GRCHS : 11; + unsigned long : 5; + unsigned long GRCHW : 11; +#endif +}; + +union un_glcdc_gr2ab3 +{ + unsigned long LONG; + struct st_glcdc_gr2ab3_bit BIT; +}; + +struct st_glcdc_gr2ab4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCVW : 11; + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCVS : 11; + unsigned long : 5; + unsigned long ARCVW : 11; +#endif +}; + +union un_glcdc_gr2ab4 +{ + unsigned long LONG; + struct st_glcdc_gr2ab4_bit BIT; +}; + +struct st_glcdc_gr2ab5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCHW : 11; + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long ARCHS : 11; + unsigned long : 5; + unsigned long ARCHW : 11; +#endif +}; + +union un_glcdc_gr2ab5 +{ + unsigned long LONG; + struct st_glcdc_gr2ab5_bit BIT; +}; + +struct st_glcdc_gr2ab6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCRATE : 8; + unsigned long : 8; + unsigned long ARCCOEF : 9; + unsigned long : 7; +#else + unsigned long : 7; + unsigned long ARCCOEF : 9; + unsigned long : 8; + unsigned long ARCRATE : 8; +#endif +}; + +union un_glcdc_gr2ab6 +{ + unsigned long LONG; + struct st_glcdc_gr2ab6_bit BIT; +}; + +struct st_glcdc_gr2ab7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKON : 1; + unsigned long : 15; + unsigned long ARCDEF : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ARCDEF : 8; + unsigned long : 15; + unsigned long CKON : 1; +#endif +}; + +union un_glcdc_gr2ab7 +{ + unsigned long LONG; + struct st_glcdc_gr2ab7_bit BIT; +}; + +struct st_glcdc_gr2ab8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKKR : 8; + unsigned long CKKB : 8; + unsigned long CKKG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CKKG : 8; + unsigned long CKKB : 8; + unsigned long CKKR : 8; +#endif +}; + +union un_glcdc_gr2ab8 +{ + unsigned long LONG; + struct st_glcdc_gr2ab8_bit BIT; +}; + +struct st_glcdc_gr2ab9_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CKR : 8; + unsigned long CKB : 8; + unsigned long CKG : 8; + unsigned long CKA : 8; +#else + unsigned long CKA : 8; + unsigned long CKG : 8; + unsigned long CKB : 8; + unsigned long CKR : 8; +#endif +}; + +union un_glcdc_gr2ab9 +{ + unsigned long LONG; + struct st_glcdc_gr2ab9_bit BIT; +}; + +struct st_glcdc_gr2base_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long R : 8; + unsigned long B : 8; + unsigned long G : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long G : 8; + unsigned long B : 8; + unsigned long R : 8; +#endif +}; + +union un_glcdc_gr2base +{ + unsigned long LONG; + struct st_glcdc_gr2base_bit BIT; +}; + +struct st_glcdc_gr2clutint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LINE : 11; + unsigned long : 5; + unsigned long SEL : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long SEL : 1; + unsigned long : 5; + unsigned long LINE : 11; +#endif +}; + +union un_glcdc_gr2clutint +{ + unsigned long LONG; + struct st_glcdc_gr2clutint_bit BIT; +}; + +struct st_glcdc_gr2mon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ARCST : 1; + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; +#else + unsigned long : 15; + unsigned long UFST : 1; + unsigned long : 15; + unsigned long ARCST : 1; +#endif +}; + +union un_glcdc_gr2mon +{ + unsigned long LONG; + struct st_glcdc_gr2mon_bit BIT; +}; + +struct st_glcdc_gamgven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_gamgven +{ + unsigned long LONG; + struct st_glcdc_gamgven_bit BIT; +}; + +struct st_glcdc_gamsw_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAMON : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long GAMON : 1; +#endif +}; + +union un_glcdc_gamsw +{ + unsigned long LONG; + struct st_glcdc_gamsw_bit BIT; +}; + +struct st_glcdc_gamglut1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif +}; + +union un_glcdc_gamglut1 +{ + unsigned long LONG; + struct st_glcdc_gamglut1_bit BIT; +}; + +struct st_glcdc_gamglut2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif +}; + +union un_glcdc_gamglut2 +{ + unsigned long LONG; + struct st_glcdc_gamglut2_bit BIT; +}; + +struct st_glcdc_gamglut3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif +}; + +union un_glcdc_gamglut3 +{ + unsigned long LONG; + struct st_glcdc_gamglut3_bit BIT; +}; + +struct st_glcdc_gamglut4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif +}; + +union un_glcdc_gamglut4 +{ + unsigned long LONG; + struct st_glcdc_gamglut4_bit BIT; +}; + +struct st_glcdc_gamglut5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif +}; + +union un_glcdc_gamglut5 +{ + unsigned long LONG; + struct st_glcdc_gamglut5_bit BIT; +}; + +struct st_glcdc_gamglut6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif +}; + +union un_glcdc_gamglut6 +{ + unsigned long LONG; + struct st_glcdc_gamglut6_bit BIT; +}; + +struct st_glcdc_gamglut7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif +}; + +union un_glcdc_gamglut7 +{ + unsigned long LONG; + struct st_glcdc_gamglut7_bit BIT; +}; + +struct st_glcdc_gamglut8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif +}; + +union un_glcdc_gamglut8 +{ + unsigned long LONG; + struct st_glcdc_gamglut8_bit BIT; +}; + +struct st_glcdc_gamgarea1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif +}; + +union un_glcdc_gamgarea1 +{ + unsigned long LONG; + struct st_glcdc_gamgarea1_bit BIT; +}; + +struct st_glcdc_gamgarea2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif +}; + +union un_glcdc_gamgarea2 +{ + unsigned long LONG; + struct st_glcdc_gamgarea2_bit BIT; +}; + +struct st_glcdc_gamgarea3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif +}; + +union un_glcdc_gamgarea3 +{ + unsigned long LONG; + struct st_glcdc_gamgarea3_bit BIT; +}; + +struct st_glcdc_gamgarea4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif +}; + +union un_glcdc_gamgarea4 +{ + unsigned long LONG; + struct st_glcdc_gamgarea4_bit BIT; +}; + +struct st_glcdc_gamgarea5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif +}; + +union un_glcdc_gamgarea5 +{ + unsigned long LONG; + struct st_glcdc_gamgarea5_bit BIT; +}; + +struct st_glcdc_gambven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_gambven +{ + unsigned long LONG; + struct st_glcdc_gambven_bit BIT; +}; + +struct st_glcdc_gamblut1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif +}; + +union un_glcdc_gamblut1 +{ + unsigned long LONG; + struct st_glcdc_gamblut1_bit BIT; +}; + +struct st_glcdc_gamblut2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif +}; + +union un_glcdc_gamblut2 +{ + unsigned long LONG; + struct st_glcdc_gamblut2_bit BIT; +}; + +struct st_glcdc_gamblut3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif +}; + +union un_glcdc_gamblut3 +{ + unsigned long LONG; + struct st_glcdc_gamblut3_bit BIT; +}; + +struct st_glcdc_gamblut4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif +}; + +union un_glcdc_gamblut4 +{ + unsigned long LONG; + struct st_glcdc_gamblut4_bit BIT; +}; + +struct st_glcdc_gamblut5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif +}; + +union un_glcdc_gamblut5 +{ + unsigned long LONG; + struct st_glcdc_gamblut5_bit BIT; +}; + +struct st_glcdc_gamblut6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif +}; + +union un_glcdc_gamblut6 +{ + unsigned long LONG; + struct st_glcdc_gamblut6_bit BIT; +}; + +struct st_glcdc_gamblut7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif +}; + +union un_glcdc_gamblut7 +{ + unsigned long LONG; + struct st_glcdc_gamblut7_bit BIT; +}; + +struct st_glcdc_gamblut8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif +}; + +union un_glcdc_gamblut8 +{ + unsigned long LONG; + struct st_glcdc_gamblut8_bit BIT; +}; + +struct st_glcdc_gambarea1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif +}; + +union un_glcdc_gambarea1 +{ + unsigned long LONG; + struct st_glcdc_gambarea1_bit BIT; +}; + +struct st_glcdc_gambarea2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif +}; + +union un_glcdc_gambarea2 +{ + unsigned long LONG; + struct st_glcdc_gambarea2_bit BIT; +}; + +struct st_glcdc_gambarea3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif +}; + +union un_glcdc_gambarea3 +{ + unsigned long LONG; + struct st_glcdc_gambarea3_bit BIT; +}; + +struct st_glcdc_gambarea4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif +}; + +union un_glcdc_gambarea4 +{ + unsigned long LONG; + struct st_glcdc_gambarea4_bit BIT; +}; + +struct st_glcdc_gambarea5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif +}; + +union un_glcdc_gambarea5 +{ + unsigned long LONG; + struct st_glcdc_gambarea5_bit BIT; +}; + +struct st_glcdc_gamrven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_gamrven +{ + unsigned long LONG; + struct st_glcdc_gamrven_bit BIT; +}; + +struct st_glcdc_gamrlut1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN01 : 11; + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN00 : 11; + unsigned long : 5; + unsigned long GAIN01 : 11; +#endif +}; + +union un_glcdc_gamrlut1 +{ + unsigned long LONG; + struct st_glcdc_gamrlut1_bit BIT; +}; + +struct st_glcdc_gamrlut2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN03 : 11; + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN02 : 11; + unsigned long : 5; + unsigned long GAIN03 : 11; +#endif +}; + +union un_glcdc_gamrlut2 +{ + unsigned long LONG; + struct st_glcdc_gamrlut2_bit BIT; +}; +struct st_glcdc_gamrlut3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN05 : 11; + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN04 : 11; + unsigned long : 5; + unsigned long GAIN05 : 11; +#endif +}; + +union un_glcdc_gamrlut3 +{ + unsigned long LONG; + struct st_glcdc_gamrlut3_bit BIT; +}; + +struct st_glcdc_gamrlut4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN07 : 11; + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN06 : 11; + unsigned long : 5; + unsigned long GAIN07 : 11; +#endif +}; + +union un_glcdc_gamrlut4 +{ + unsigned long LONG; + struct st_glcdc_gamrlut4_bit BIT; +}; +struct st_glcdc_gamrlut5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN09 : 11; + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN08 : 11; + unsigned long : 5; + unsigned long GAIN09 : 11; +#endif +}; + +union un_glcdc_gamrlut5 +{ + unsigned long LONG; + struct st_glcdc_gamrlut5_bit BIT; +}; + +struct st_glcdc_gamrlut6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN11 : 11; + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN10 : 11; + unsigned long : 5; + unsigned long GAIN11 : 11; +#endif +}; + +union un_glcdc_gamrlut6 +{ + unsigned long LONG; + struct st_glcdc_gamrlut6_bit BIT; +}; + +struct st_glcdc_gamrlut7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN13 : 11; + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN12 : 11; + unsigned long : 5; + unsigned long GAIN13 : 11; +#endif +}; + +union un_glcdc_gamrlut7 +{ + unsigned long LONG; + struct st_glcdc_gamrlut7_bit BIT; +}; + +struct st_glcdc_gamrlut8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long GAIN15 : 11; + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long GAIN14 : 11; + unsigned long : 5; + unsigned long GAIN15 : 11; +#endif +}; + +union un_glcdc_gamrlut8 +{ + unsigned long LONG; + struct st_glcdc_gamrlut8_bit BIT; +}; + +struct st_glcdc_gamrarea1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH03 : 10; + unsigned long TH02 : 10; + unsigned long TH01 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH01 : 10; + unsigned long TH02 : 10; + unsigned long TH03 : 10; +#endif +}; + +union un_glcdc_gamrarea1 +{ + unsigned long LONG; + struct st_glcdc_gamrarea1_bit BIT; +}; + +struct st_glcdc_gamrarea2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH06 : 10; + unsigned long TH05 : 10; + unsigned long TH04 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH04 : 10; + unsigned long TH05 : 10; + unsigned long TH06 : 10; +#endif +}; + +union un_glcdc_gamrarea2 +{ + unsigned long LONG; + struct st_glcdc_gamrarea2_bit BIT; +}; + +struct st_glcdc_gamrarea3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH09 : 10; + unsigned long TH08 : 10; + unsigned long TH07 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH07 : 10; + unsigned long TH08 : 10; + unsigned long TH09 : 10; +#endif +}; + +union un_glcdc_gamrarea3 +{ + unsigned long LONG; + struct st_glcdc_gamrarea3_bit BIT; +}; + +struct st_glcdc_gamrarea4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH12 : 10; + unsigned long TH11 : 10; + unsigned long TH10 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH10 : 10; + unsigned long TH11 : 10; + unsigned long TH12 : 10; +#endif +}; + +union un_glcdc_gamrarea4 +{ + unsigned long LONG; + struct st_glcdc_gamrarea4_bit BIT; +}; + +struct st_glcdc_gamrarea5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TH15 : 10; + unsigned long TH14 : 10; + unsigned long TH13 : 10; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TH13 : 10; + unsigned long TH14 : 10; + unsigned long TH15 : 10; +#endif +}; + +union un_glcdc_gamrarea5 +{ + unsigned long LONG; + struct st_glcdc_gamrarea5_bit BIT; +}; + +struct st_glcdc_outven_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long VEN : 1; +#endif +}; + +union un_glcdc_outven +{ + unsigned long LONG; + struct st_glcdc_outven_bit BIT; +}; + +struct st_glcdc_outset_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PHASE : 2; + unsigned long : 2; + unsigned long DIRSEL : 1; + unsigned long : 4; + unsigned long FRQSEL : 1; + unsigned long : 2; + unsigned long FORMAT : 2; + unsigned long : 10; + unsigned long SWAPON : 1; + unsigned long : 3; + unsigned long ENDIANON : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long ENDIANON : 1; + unsigned long : 3; + unsigned long SWAPON : 1; + unsigned long : 10; + unsigned long FORMAT : 2; + unsigned long : 2; + unsigned long FRQSEL : 1; + unsigned long : 4; + unsigned long DIRSEL : 1; + unsigned long : 2; + unsigned long PHASE : 2; +#endif +}; + +union un_glcdc_outset +{ + unsigned long LONG; + struct st_glcdc_outset_bit BIT; +}; + +struct st_glcdc_bright1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRTG : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long BRTG : 10; +#endif +}; + +union un_glcdc_bright1 +{ + unsigned long LONG; + struct st_glcdc_bright1_bit BIT; +}; + +struct st_glcdc_bright2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BRTR : 10; + unsigned long : 6; + unsigned long BRTB : 10; + unsigned long : 6; +#else + unsigned long : 6; + unsigned long BRTB : 10; + unsigned long : 6; + unsigned long BRTR : 10; +#endif +}; + +union un_glcdc_bright2 +{ + unsigned long LONG; + struct st_glcdc_bright2_bit BIT; +}; + +struct st_glcdc_contrast_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CONTR : 8; + unsigned long CONTB : 8; + unsigned long CONTG : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long CONTG : 8; + unsigned long CONTB : 8; + unsigned long CONTR : 8; +#endif +}; + +union un_glcdc_contrast +{ + unsigned long LONG; + struct st_glcdc_contrast_bit BIT; +}; + +struct st_glcdc_paneldtha_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PD : 2; + unsigned long : 2; + unsigned long PC : 2; + unsigned long : 2; + unsigned long PB : 2; + unsigned long : 2; + unsigned long PA : 2; + unsigned long : 2; + unsigned long FORM : 2; + unsigned long : 2; + unsigned long SEL : 2; + unsigned long : 10; +#else + unsigned long : 10; + unsigned long SEL : 2; + unsigned long : 2; + unsigned long FORM : 2; + unsigned long : 2; + unsigned long PA : 2; + unsigned long : 2; + unsigned long PB : 2; + unsigned long : 2; + unsigned long PC : 2; + unsigned long : 2; + unsigned long PD : 2; +#endif +}; + +union un_glcdc_paneldtha +{ + unsigned long LONG; + struct st_glcdc_paneldtha_bit BIT; +}; + +struct st_glcdc_clkphase_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long TCON3EDG : 1; + unsigned long TCON2EDG : 1; + unsigned long TCON1EDG : 1; + unsigned long TCON0EDG : 1; + unsigned long : 1; + unsigned long LCDEDG : 1; + unsigned long : 3; + unsigned long FRONTGAM : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long FRONTGAM : 1; + unsigned long : 3; + unsigned long LCDEDG : 1; + unsigned long : 1; + unsigned long TCON0EDG : 1; + unsigned long TCON1EDG : 1; + unsigned long TCON2EDG : 1; + unsigned long TCON3EDG : 1; + unsigned long : 3; +#endif +}; + +union un_glcdc_clkphase +{ + unsigned long LONG; + struct st_glcdc_clkphase_bit BIT; +}; + +struct st_glcdc_tcontim_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OFFSET : 11; + unsigned long : 5; + unsigned long HALF : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HALF : 11; + unsigned long : 5; + unsigned long OFFSET : 11; +#endif +}; + +union un_glcdc_tcontim +{ + unsigned long LONG; + struct st_glcdc_tcontim_bit BIT; +}; + +struct st_glcdc_tconstva1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif +}; + +union un_glcdc_tconstva1 +{ + unsigned long LONG; + struct st_glcdc_tconstva1_bit BIT; +}; + +struct st_glcdc_tconstvat2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif +}; + +union un_glcdc_tconstvat2 +{ + unsigned long LONG; + struct st_glcdc_tconstvat2_bit BIT; +}; + +struct st_glcdc_tconstvb1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VW : 11; + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long VS : 11; + unsigned long : 5; + unsigned long VW : 11; +#endif +}; + +union un_glcdc_tconstvb1 +{ + unsigned long LONG; + struct st_glcdc_tconstvb1_bit BIT; +}; + +struct st_glcdc_tconstvb2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif +}; + +union un_glcdc_tconstvb2 +{ + unsigned long LONG; + struct st_glcdc_tconstvb2_bit BIT; +}; + +struct st_glcdc_tconstha1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif +}; + +union un_glcdc_tconstha1 +{ + unsigned long LONG; + struct st_glcdc_tconstha1_bit BIT; +}; + +struct st_glcdc_tconstha2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 3; + unsigned long HSSEL : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HSSEL : 1; + unsigned long : 3; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif +}; + +union un_glcdc_tconstha2 +{ + unsigned long LONG; + struct st_glcdc_tconstha2_bit BIT; +}; + +struct st_glcdc_tconsthb1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HW : 11; + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; +#else + unsigned long : 5; + unsigned long HS : 11; + unsigned long : 5; + unsigned long HW : 11; +#endif +}; + +union un_glcdc_tconsthb1 +{ + unsigned long LONG; + struct st_glcdc_tconsthb1_bit BIT; +}; + +struct st_glcdc_tconsthb2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SEL : 3; + unsigned long : 1; + unsigned long INV : 1; + unsigned long : 3; + unsigned long HSSEL : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long HSSEL : 1; + unsigned long : 3; + unsigned long INV : 1; + unsigned long : 1; + unsigned long SEL : 3; +#endif +}; + +union un_glcdc_tconsthb2 +{ + unsigned long LONG; + struct st_glcdc_tconsthb2_bit BIT; +}; + +struct st_glcdc_tconde_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INV : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long INV : 1; +#endif +}; + +union un_glcdc_tconde +{ + unsigned long LONG; + struct st_glcdc_tconde_bit BIT; +}; + +struct st_glcdc_dtcten_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSDTC : 1; + unsigned long GR1UFDTC : 1; + unsigned long GR2UFDTC : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFDTC : 1; + unsigned long GR1UFDTC : 1; + unsigned long VPOSDTC : 1; +#endif +}; + +union un_glcdc_dtcten +{ + unsigned long LONG; + struct st_glcdc_dtcten_bit BIT; +}; + +struct st_glcdc_inten_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSINTEN : 1; + unsigned long GR1UFINTEN : 1; + unsigned long GR2UFINTEN : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFINTEN : 1; + unsigned long GR1UFINTEN : 1; + unsigned long VPOSINTEN : 1; +#endif +}; + +union un_glcdc_inten +{ + unsigned long LONG; + struct st_glcdc_inten_bit BIT; +}; + +struct st_glcdc_stclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOSCLR : 1; + unsigned long GR1UFCLR : 1; + unsigned long GR2UFCLR : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UFCLR : 1; + unsigned long GR1UFCLR : 1; + unsigned long VPOSCLR : 1; +#endif +}; + +union un_glcdc_stclr +{ + unsigned long LONG; + struct st_glcdc_stclr_bit BIT; +}; + +struct st_glcdc_stmon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VPOS : 1; + unsigned long GR1UF : 1; + unsigned long GR2UF : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long GR2UF : 1; + unsigned long GR1UF : 1; + unsigned long VPOS : 1; +#endif +}; + +union un_glcdc_stmon +{ + unsigned long LONG; + struct st_glcdc_stmon_bit BIT; +}; + +struct st_glcdc_panelclk_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DCDR : 6; + unsigned long CLKEN : 1; + unsigned long : 1; + unsigned long CLKSEL : 1; + unsigned long : 3; + unsigned long PIXSEL : 1; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long PIXSEL : 1; + unsigned long : 3; + unsigned long CLKSEL : 1; + unsigned long : 1; + unsigned long CLKEN : 1; + unsigned long DCDR : 6; +#endif +}; + +union un_glcdc_panelclk +{ + unsigned long LONG; + struct st_glcdc_panelclk_bit BIT; +}; + +struct st_mtu4_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu4_tcr +{ + unsigned char BYTE; + struct st_mtu4_tcr_bit BIT; +}; + +struct st_mtu4_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu4_tmdr1 +{ + unsigned char BYTE; + struct st_mtu4_tmdr1_bit BIT; +}; + +struct st_mtu4_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu4_tiorh +{ + unsigned char BYTE; + struct st_mtu4_tiorh_bit BIT; +}; + +struct st_mtu4_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu4_tiorl +{ + unsigned char BYTE; + struct st_mtu4_tiorl_bit BIT; +}; + +struct st_mtu4_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu4_tier +{ + unsigned char BYTE; + struct st_mtu4_tier_bit BIT; +}; + +struct st_mtu4_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; + +union un_mtu4_tsr +{ + unsigned char BYTE; + struct st_mtu4_tsr_bit BIT; +}; + +struct st_mtu4_tbtm_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif +}; + +union un_mtu4_tbtm +{ + unsigned char BYTE; + struct st_mtu4_tbtm_bit BIT; +}; + +struct st_mtu4_tadcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif +}; + +union un_mtu4_tadcr +{ + unsigned char BYTE; + struct st_mtu4_tadcr_bit BIT; +}; + +struct st_mtu4_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu4_tcr2 +{ + unsigned char BYTE; + struct st_mtu4_tcr2_bit BIT; +}; + +struct st_mtu4_nfcr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu4_nfcr4 +{ + unsigned char BYTE; + struct st_mtu4_nfcr4_bit BIT; +}; + +struct st_mtu5_nfcr5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif +}; + +union un_mtu5_nfcr5 +{ + unsigned char BYTE; + struct st_mtu5_nfcr5_bit BIT; +}; + +struct st_mtu5_tcru_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif +}; + +union un_mtu5_tcru +{ + unsigned char BYTE; + struct st_mtu5_tcru_bit BIT; +}; + +struct st_mtu5_tcr2u_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu5_tcr2u +{ + unsigned char BYTE; + struct st_mtu5_tcr2u_bit BIT; +}; + +struct st_mtu5_tioru_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif +}; + +union un_mtu5_tioru +{ + unsigned char BYTE; + struct st_mtu5_tioru_bit BIT; +}; + +struct st_mtu5_tcrv_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif +}; + +union un_mtu5_tcrv +{ + unsigned char BYTE; + struct st_mtu5_tcrv_bit BIT; +}; + +struct st_mtu5_tcr2v_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu5_tcr2v +{ + unsigned char BYTE; + struct st_mtu5_tcr2v_bit BIT; +}; + +struct st_mtu5_tiorv_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif +}; + +union un_mtu5_tiorv +{ + unsigned char BYTE; + struct st_mtu5_tiorv_bit BIT; +}; + +struct st_mtu5_tcrw_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif +}; + +union un_mtu5_tcrw +{ + unsigned char BYTE; + struct st_mtu5_tcrw_bit BIT; +}; + +struct st_mtu5_tcr2w_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char CKEG : 2; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CKEG : 2; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu5_tcr2w +{ + unsigned char BYTE; + struct st_mtu5_tcr2w_bit BIT; +}; + +struct st_mtu5_tiorw_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif +}; + +union un_mtu5_tiorw +{ + unsigned char BYTE; + struct st_mtu5_tiorw_bit BIT; +}; + +struct st_mtu5_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif +}; + +union un_mtu5_tier +{ + unsigned char BYTE; + struct st_mtu5_tier_bit BIT; +}; + +struct st_mtu5_tstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif +}; + +union un_mtu5_tstr +{ + unsigned char BYTE; + struct st_mtu5_tstr_bit BIT; +}; + +struct st_mtu5_tcntcmpclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif +}; + +union un_mtu5_tcntcmpclr +{ + unsigned char BYTE; + struct st_mtu5_tcntcmpclr_bit BIT; +}; + +struct st_smci0_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif +}; + +union un_smcio_smr +{ + unsigned char BYTE; + struct st_smci0_smr_bit BIT; +}; + +struct st_smci0_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_smcio_scr +{ + unsigned char BYTE; + struct st_smci0_scr_bit BIT; +}; +struct st_smci0_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_smcio_ssr +{ + unsigned char BYTE; + struct st_smci0_ssr_bit BIT; +}; + +struct st_smci0_smcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_smcio_smcr +{ + unsigned char BYTE; + struct st_smci0_smcr_bit BIT; +}; + +struct st_riic_iccr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif +}; + +union un_riic_iccr1 +{ + unsigned char BYTE; + struct st_riic_iccr1_bit BIT; +}; + +struct st_riic_iccr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif +}; + +union un_riic_iccr2 +{ + unsigned char BYTE; + struct st_riic_iccr2_bit BIT; +}; + +struct st_riic_icmr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif +}; + +union un_riic_icmr1 +{ + unsigned char BYTE; + struct st_riic_icmr1_bit BIT; +}; + +struct st_riic_icmr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif +}; + +union un_riic_icmr2 +{ + unsigned char BYTE; + struct st_riic_icmr2_bit BIT; +}; + +struct st_riic_icmr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif +}; + +union un_riic_icmr3 +{ + unsigned char BYTE; + struct st_riic_icmr3_bit BIT; +}; + +struct st_riic_icfer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char FMPE : 1; +#else + unsigned char FMPE : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif +}; + +union un_riic_icfer +{ + unsigned char BYTE; + struct st_riic_icfer_bit BIT; +}; + +struct st_riic_icser_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif +}; + +union un_riic_icser +{ + unsigned char BYTE; + struct st_riic_icser_bit BIT; +}; + +struct st_riic_icier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif +}; + +union un_riic_icier +{ + unsigned char BYTE; + struct st_riic_icier_bit BIT; +}; + +struct st_riic_icsr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif +}; + +union un_riic_icsr1 +{ + unsigned char BYTE; + struct st_riic_icsr1_bit BIT; +}; + +struct st_riic_icsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif +}; + +union un_riic_icsr2 +{ + unsigned char BYTE; + struct st_riic_icsr2_bit BIT; +}; + +struct st_riic_sarl0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif +}; + +union un_riic_sarl0 +{ + unsigned char BYTE; + struct st_riic_sarl0_bit BIT; +}; + +struct st_riic_saru0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif +}; + +union un_riic_saru0 +{ + unsigned char BYTE; + struct st_riic_saru0_bit BIT; +}; + +struct st_riic_sarl1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif +}; + +union un_riic_sarl1 +{ + unsigned char BYTE; + struct st_riic_sarl1_bit BIT; +}; + +struct st_riic_saru1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif +}; + +union un_riic_saru1 +{ + unsigned char BYTE; + struct st_riic_saru1_bit BIT; +}; + +struct st_riic_sarl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif +}; + +union un_riic_sarl2 +{ + unsigned char BYTE; + struct st_riic_sarl2_bit BIT; +}; + +struct st_riic_saru2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif +}; + +union un_riic_saru2 +{ + unsigned char BYTE; + struct st_riic_saru2_bit BIT; +}; + +struct st_riic_icbrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif +}; + +union un_riic_icbrl +{ + unsigned char BYTE; + struct st_riic_icbrl_bit BIT; +}; + +struct st_riic_icbrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif +}; + +union un_riic_icbrh +{ + unsigned char BYTE; + struct st_riic_icbrh_bit BIT; +}; + +struct st_rspi_spcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif +}; + +union un_rspi_spcr +{ + unsigned char BYTE; + struct st_rspi_spcr_bit BIT; +}; + +struct st_rspi_sslp_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif +}; + +union un_rspi_sslp +{ + unsigned char BYTE; + struct st_rspi_sslp_bit BIT; +}; + +struct st_rspi_sppcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif +}; + +union un_rspi_sppcr +{ + unsigned char BYTE; + struct st_rspi_sppcr_bit BIT; +}; + +struct st_rspi_spsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char UDRF : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char UDRF : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif +}; + +union un_rspi_spsr +{ + unsigned char BYTE; + struct st_rspi_spsr_bit BIT; +}; + +struct st_rspi_spdr_word +{ + unsigned short H; +}; + +struct st_rspi_spdr_byte +{ + unsigned char HH; +}; + +union un_rspi_spdr +{ + unsigned long LONG; + struct st_rspi_spdr_word WORD; +}; + +struct st_rspi_spscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif +}; + +union un_rspi_spscr +{ + unsigned char BYTE; + struct st_rspi_spscr_bit BIT; +}; + +struct st_rspi_spssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif +}; + +union un_rspi_spssr +{ + unsigned char BYTE; + struct st_rspi_spssr_bit BIT; +}; + +struct st_rspi_spdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char SPBYT : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPBYT : 1; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif +}; + +union un_rspi_spdcr +{ + unsigned char BYTE; + struct st_rspi_spdcr_bit BIT; +}; + +struct st_rspi_spckd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif +}; + +union un_rspi_spckd +{ + unsigned char BYTE; + struct st_rspi_spckd_bit BIT; +}; + +struct st_rspi_sslnd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif +}; + +union un_rspi_sslnd +{ + unsigned char BYTE; + struct st_rspi_sslnd_bit BIT; +}; + +struct st_rspi_spnd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif +}; + +union un_rspi_spnd +{ + unsigned char BYTE; + struct st_rspi_spnd_bit BIT; +}; + +struct st_rspi_spcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif +}; + +union un_rspi_spcr2 +{ + unsigned char BYTE; + struct st_rspi_spcr2_bit BIT; +}; + +struct st_rspi_spcmd0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd0 +{ + unsigned char BYTE; + struct st_rspi_spcmd0_bit BIT; +}; + +struct st_rspi_spcmd1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd1 +{ + unsigned char BYTE; + struct st_rspi_spcmd1_bit BIT; +}; + +struct st_rspi_spcmd2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd2 +{ + unsigned char BYTE; + struct st_rspi_spcmd2_bit BIT; +}; + +struct st_rspi_spcmd3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd3 +{ + unsigned char BYTE; + struct st_rspi_spcmd3_bit BIT; +}; + +struct st_rspi_spcmd4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd4 +{ + unsigned char BYTE; + struct st_rspi_spcmd4_bit BIT; +}; + +struct st_rspi_spcmd5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd5 +{ + unsigned char BYTE; + struct st_rspi_spcmd5_bit BIT; +}; + +struct st_rspi_spcmd6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd6 +{ + unsigned char BYTE; + struct st_rspi_spcmd6_bit BIT; +}; + +struct st_rspi_spcmd7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_rspi_spcmd7 +{ + unsigned char BYTE; + struct st_rspi_spcmd7_bit BIT; +}; + +struct st_rspi_spdcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BYSW : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BYSW : 1; +#endif +}; + +union un_rspi_spdcr2 +{ + unsigned char BYTE; + struct st_rspi_spdcr2_bit BIT; +}; + +struct st_sdhi_spcmd_bit +{ + unsigned long :16; + unsigned long CMD12AT:2; + unsigned long TRSTP:1; + unsigned long CMDRW:1; + unsigned long CMDTP:1; + unsigned long RSPTP:3; + unsigned long ACMD:2; + unsigned long CMDIDX:6; +}; + +union un_sdhi_spcmd +{ + unsigned long LONG; + struct st_sdhi_spcmd_bit BIT; +}; + +struct st_sdhi_sdstop_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STP : 1; + unsigned long : 7; + unsigned long SDBLKCNTEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long SDBLKCNTEN : 1; + unsigned long : 7; + unsigned long STP : 1; +#endif +}; + +union un_sdhi_sdstop +{ + unsigned long LONG; + struct st_sdhi_sdstop_bit BIT; +}; + +struct st_sdhi_sdsts1_bit +{ + unsigned long :21; + unsigned long SDD3MON:1; + unsigned long SDD3IN:1; + unsigned long SDD3RM:1; + unsigned long SDWPMON:1; + unsigned long :1; + unsigned long SDCDMON:1; + unsigned long SDCDIN:1; + unsigned long SDCDRM:1; + unsigned long ACEND:1; + unsigned long :1; + unsigned long RSPEND:1; +}; + +union un_sdhi_sdsts1 +{ + unsigned long LONG; + struct st_sdhi_sdsts1_bit BIT; +}; + +struct st_sdhi_sdsts2_bit +{ + unsigned long :16; + unsigned long ILA:1; + unsigned long CBSY:1; + unsigned long SDCLKCREN:1; + unsigned long :3; + unsigned long BWE:1; + unsigned long BRE:1; + unsigned long SDD0MON:1; + unsigned long RSPTO:1; + unsigned long ILR:1; + unsigned long ILW:1; + unsigned long DTO:1; + unsigned long ENDE:1; + unsigned long CRCE:1; + unsigned long CMDE:1; +}; + +union un_sdhi_sdsts2 +{ + unsigned long LONG; + struct st_sdhi_sdsts2_bit BIT; +}; + +struct st_sdhi_sdimsk1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPENDM : 1; + unsigned long : 1; + unsigned long ACENDM : 1; + unsigned long SDCDRMM : 1; + unsigned long SDCDINM : 1; + unsigned long : 3; + unsigned long SDD3RMM : 1; + unsigned long SDD3INM : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long SDD3INM : 1; + unsigned long SDD3RMM : 1; + unsigned long : 3; + unsigned long SDCDINM : 1; + unsigned long SDCDRMM : 1; + unsigned long ACENDM : 1; + unsigned long : 1; + unsigned long RSPENDM : 1; +#endif +}; + +union un_sdhi_sdimsk1 +{ + unsigned long LONG; + struct st_sdhi_sdimsk1_bit BIT; +}; + +struct st_sdhi_sdimsk2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDEM : 1; + unsigned long CRCEM : 1; + unsigned long ENDEM : 1; + unsigned long DTTOM : 1; + unsigned long ILWM : 1; + unsigned long ILRM : 1; + unsigned long RSPTOM : 1; + unsigned long : 1; + unsigned long BREM : 1; + unsigned long BWEM : 1; + unsigned long : 5; + unsigned long ILAM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILAM : 1; + unsigned long : 5; + unsigned long BWEM : 1; + unsigned long BREM : 1; + unsigned long : 1; + unsigned long RSPTOM : 1; + unsigned long ILRM : 1; + unsigned long ILWM : 1; + unsigned long DTTOM : 1; + unsigned long ENDEM : 1; + unsigned long CRCEM : 1; + unsigned long CMDEM : 1; +#endif +}; + +union un_sdhi_sdimsk2 +{ + unsigned long LONG; + struct st_sdhi_sdimsk2_bit BIT; +}; + +struct st_sdhi_sdclkcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLKSEL : 8; + unsigned long CLKEN : 1; + unsigned long CLKCTRLEN : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long CLKCTRLEN : 1; + unsigned long CLKEN : 1; + unsigned long CLKSEL : 8; +#endif +}; + +union un_sdhi_sdclkcr +{ + unsigned long LONG; + struct st_sdhi_sdclkcr_bit BIT; +}; + +struct st_sdhi_sdsize_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LEN : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long LEN : 10; +#endif +}; + +union un_sdhi_sdsize +{ + unsigned long LONG; + struct st_sdhi_sdsize_bit BIT; +}; + +struct st_sdhi_sdopt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTOP : 4; + unsigned long TOP : 4; + unsigned long : 7; + unsigned long WIDTH : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long WIDTH : 1; + unsigned long : 7; + unsigned long TOP : 4; + unsigned long CTOP : 4; +#endif +}; + +union un_sdhi_sdopt +{ + unsigned long LONG; + struct st_sdhi_sdopt_bit BIT; +}; + +struct st_sdhi_sdersts1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE0 : 1; + unsigned long CMDE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long RSPLENE1 : 1; + unsigned long RDLENE : 1; + unsigned long CRCLENE : 1; + unsigned long : 2; + unsigned long RSPCRCE0 : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RDCRCE : 1; + unsigned long CRCTKE : 1; + unsigned long CRCTK : 3; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CRCTK : 3; + unsigned long CRCTKE : 1; + unsigned long RDCRCE : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RSPCRCE0 : 1; + unsigned long : 2; + unsigned long CRCLENE : 1; + unsigned long RDLENE : 1; + unsigned long RSPLENE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long CMDE1 : 1; + unsigned long CMDE0 : 1; +#endif +}; + +union un_sdhi_sdersts1 +{ + unsigned long LONG; + struct st_sdhi_sdersts1_bit BIT; +}; + +struct st_sdhi_sdersts2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long BSYTO1 : 1; + unsigned long RDTO : 1; + unsigned long CRCTO : 1; + unsigned long CRCBSYTO : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long CRCBSYTO : 1; + unsigned long CRCTO : 1; + unsigned long RDTO : 1; + unsigned long BSYTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long RSPTO0 : 1; +#endif +}; + +union un_sdhi_sdersts2 +{ + unsigned long LONG; + struct st_sdhi_sdersts2_bit BIT; +}; + +struct st_sdhi_sdiomd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INTEN : 1; + unsigned long : 1; + unsigned long RWREQ : 1; + unsigned long : 5; + unsigned long IOABT : 1; + unsigned long C52PUB : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long C52PUB : 1; + unsigned long IOABT : 1; + unsigned long : 5; + unsigned long RWREQ : 1; + unsigned long : 1; + unsigned long INTEN : 1; +#endif +}; + +union un_sdhi_sdiomd +{ + unsigned long LONG; + struct st_sdhi_sdiomd_bit BIT; +}; + +struct st_sdhi_sdiosts_bit +{ + unsigned long :16; + unsigned long EXWT:1; + unsigned long EXPUB52:1; + unsigned long :13; + unsigned long IOIRQ:1; +}; + +union un_sdhi_sdiosts +{ + unsigned long LONG; + struct st_sdhi_sdiosts_bit BIT; +}; + +struct st_sdhi_sdioimsk_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQM : 1; + unsigned long : 13; + unsigned long EXPUB52M : 1; + unsigned long EXWTM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWTM : 1; + unsigned long EXPUB52M : 1; + unsigned long : 13; + unsigned long IOIRQM : 1; +#endif +}; + +union un_sdhi_sdioimsk +{ + unsigned long LONG; + struct st_sdhi_sdioimsk_bit BIT; +}; + +struct st_sdhi_sddmaen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long DMAEN : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long DMAEN : 1; + unsigned long : 1; +#endif +}; + +union un_sdhi_sddmaen +{ + unsigned long LONG; + struct st_sdhi_sddmaen_bit BIT; +}; + +struct st_sdhi_sdrst_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDRST : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SDRST : 1; +#endif +}; + +union un_sdhi_sdrst +{ + unsigned long LONG; + struct st_sdhi_sdrst_bit BIT; +}; + +struct st_sdhi_sdver_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IP1 : 8; + unsigned long IP2 : 4; + unsigned long : 2; + unsigned long CLKRAT : 1; + unsigned long CPRM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long CPRM : 1; + unsigned long CLKRAT : 1; + unsigned long : 2; + unsigned long IP2 : 4; + unsigned long IP1 : 8; +#endif +}; + +union un_sdhi_sdver +{ + unsigned long LONG; + struct st_sdhi_sdver_bit BIT; +}; + +struct st_sdhi_sdswap_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long BWSWP : 1; + unsigned long BRSWP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long BRSWP : 1; + unsigned long BWSWP : 1; + unsigned long : 6; +#endif +}; + +union un_sdhi_sdswap +{ + unsigned long LONG; + struct st_sdhi_sdswap_bit BIT; +}; + +struct st_sdsi_fn1accr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 11; + unsigned long FN1ACC : 1; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long FN1ACC : 1; + unsigned long : 11; +#endif +}; + +union un_sdsi_fn1accr +{ + unsigned long LONG; + struct st_sdsi_fn1accr_bit BIT; +}; + +struct st_sdsi_intencr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD52WIREN : 1; + unsigned char CMD53WIREN : 1; + unsigned char CMD53RIREN : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMD53RIREN : 1; + unsigned char CMD53WIREN : 1; + unsigned char CMD52WIREN : 1; +#endif +}; + +union un_sdsi_intencr1 +{ + unsigned char BYTE; + struct st_sdsi_intencr1_bit BIT; +}; + +struct st_sdsi_intsr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD52W : 1; + unsigned char CMD53W : 1; + unsigned char CMD53R : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMD53R : 1; + unsigned char CMD53W : 1; + unsigned char CMD52W : 1; +#endif +}; + +union un_sdsi_intsr1 +{ + unsigned char BYTE; + struct st_sdsi_intsr1_bit BIT; +}; + +struct st_sdsi_sdcmdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDCMDINDEX : 1; + unsigned char SDWNRFLG : 1; + unsigned char SDRAWFLG : 1; + unsigned char SDBMODE : 1; + unsigned char SDOPCODE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SDOPCODE : 1; + unsigned char SDBMODE : 1; + unsigned char SDRAWFLG : 1; + unsigned char SDWNRFLG : 1; + unsigned char SDCMDINDEX : 1; +#endif +}; + +union un_sdsi_sdcmdcr +{ + unsigned char BYTE; + struct st_sdsi_sdcmdcr_bit BIT; +}; + +struct st_sdsi_sdcadd0r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDCMDACCADD : 8; +#else + unsigned char SDCMDACCADD : 8; +#endif +}; + +union un_sdsi_sdcadd0r +{ + unsigned char BYTE; + struct st_sdsi_sdcadd0r_bit BIT; +}; + +struct st_sdsi_sdcadd1r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDCMDACCADD : 8; +#else + unsigned char SDCMDACCADD : 8; +#endif +}; + +union un_sdsi_sdcadd1r +{ + unsigned char BYTE; + struct st_sdsi_sdcadd1r_bit BIT; +}; + +struct st_sdsi_sdcadd2r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDCMDACCADD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDCMDACCADD : 1; +#endif +}; + +union un_sdsi_sdcadd2r +{ + unsigned char BYTE; + struct st_sdsi_sdcadd2r_bit BIT; +}; + +struct st_sdsi_sdsicr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOE1IOR1 : 1; + unsigned char EPS : 1; + unsigned char EMPC : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char EMPC : 1; + unsigned char EPS : 1; + unsigned char IOE1IOR1 : 1; +#endif +}; + +union un_sdsi_sdsicr1 +{ + unsigned char BYTE; + struct st_sdsi_sdsicr1_bit BIT; +}; + +struct st_sdsi_dmacr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMAEN : 1; + unsigned char DMALOCKEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DMALOCKEN : 1; + unsigned char DMAEN : 1; +#endif +}; + +union un_sdsi_dmacr1 +{ + unsigned char BYTE; + struct st_sdsi_dmacr1_bit BIT; +}; + +struct st_sdsi_blkcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMD53BLK : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMD53BLK : 9; +#endif +}; + +union un_sdsi_blkcnt +{ + unsigned short WORD; + struct st_sdsi_blkcnt_bit BIT; +}; + +struct st_sdsi_bytcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMD53BYT : 12; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CMD53BYT : 12; +#endif +}; + +union un_sdsi_bytcnt +{ + unsigned short WORD; + struct st_sdsi_bytcnt_bit BIT; +}; + +struct st_sdsi_dmatraddr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DMAADD : 32; +#else + unsigned long DMAADD : 32; +#endif +}; + +union un_sdsi_dmatraddr +{ + unsigned long LONG; + struct st_sdsi_dmatraddr_bit BIT; +}; + +struct st_sdsi_sdsicr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSWAP : 1; + unsigned long : 1; + unsigned long WSWAP : 1; + unsigned long : 1; + unsigned long REG5EN : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long REG5EN : 1; + unsigned long : 1; + unsigned long WSWAP : 1; + unsigned long : 1; + unsigned long RSWAP : 1; +#endif +}; + +union un_sdsi_sdsicr2 +{ + unsigned long LONG; + struct st_sdsi_sdsicr2_bit BIT; +}; + +struct st_sdsi_sdsicr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SRST : 1; + unsigned long : 1; + unsigned long IOR0 : 1; + unsigned long CEN : 1; + unsigned long : 14; + unsigned long SPS : 1; + unsigned long SMPC : 1; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long SMPC : 1; + unsigned long SPS : 1; + unsigned long : 14; + unsigned long CEN : 1; + unsigned long IOR0 : 1; + unsigned long : 1; + unsigned long SRST : 1; +#endif +}; + +union un_sdsi_sdsicr3 +{ + unsigned long LONG; + struct st_sdsi_sdsicr3_bit BIT; +}; + +struct st_sdsi_intencr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CDFEN : 1; + unsigned long CDREN : 1; + unsigned long DTEEN : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DTEEN : 1; + unsigned long CDREN : 1; + unsigned long CDFEN : 1; +#endif +}; + +union un_sdsi_intencr2 +{ + unsigned long LONG; + struct st_sdsi_intencr2_bit BIT; +}; + +struct st_sdsi_intsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CDF : 1; + unsigned long CDR : 1; + unsigned long DTE : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DTE : 1; + unsigned long CDR : 1; + unsigned long CDF : 1; +#endif +}; + +union un_sdsi_intsr2 +{ + unsigned long LONG; + struct st_sdsi_intsr2_bit BIT; +}; + +struct st_sdsi_dmacr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DMARSWAP : 2; + unsigned long DMAWSWAP : 2; + unsigned long : 4; + unsigned long DMASDSEL : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long DMASDSEL : 1; + unsigned long : 4; + unsigned long DMAWSWAP : 2; + unsigned long DMARSWAP : 2; +#endif +}; + +union un_sdsi_dmacr2 +{ + unsigned long LONG; + struct st_sdsi_dmacr2_bit BIT; +}; + +struct st_sdsi_fbr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBR1L : 4; + unsigned long : 4; + unsigned long FBR1U : 8; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FBR1U : 8; + unsigned long : 4; + unsigned long FBR1L : 4; +#endif +}; + +union un_sdsi_fbr1 +{ + unsigned long LONG; + struct st_sdsi_fbr1_bit BIT; +}; + +struct st_sdsi_fbr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBR2 : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long FBR2 : 8; +#endif +}; + +union un_sdsi_fbr2 +{ + unsigned long LONG; + struct st_sdsi_fbr2_bit BIT; +}; + +struct st_sdsi_fbr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBR3 : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FBR3 : 16; +#endif +}; + +union un_sdsi_fbr3 +{ + unsigned long LONG; + struct st_sdsi_fbr3_bit BIT; +}; + +struct st_sdsi_fbr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBR4 : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long FBR4 : 16; +#endif +}; + +union un_sdsi_fbr4 +{ + unsigned long LONG; + struct st_sdsi_fbr4_bit BIT; +}; + +struct st_sdsi_fbr5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBR5 : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long FBR5 : 8; +#endif +}; + +union un_sdsi_fbr5 +{ + unsigned long LONG; + struct st_sdsi_fbr5_bit BIT; +}; + +struct st_sdsi_fn1datar1_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +union un_sdsi_fn1datar1 +{ + unsigned long LONG; + struct st_sdsi_fn1datar1_byte BYTE; +}; + +struct st_sdsi_fn1datar2_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +union un_sdsi_fn1datar2 +{ + unsigned long LONG; + struct st_sdsi_fn1datar2_byte BYTE; +}; + +struct st_sdsi_fn1datar3_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +union un_sdsi_fn1datar3 +{ + unsigned long LONG; + struct st_sdsi_fn1datar3_byte BYTE; +}; + +struct st_sdsi_fn1intvecr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INTVEC : 8; +#else + unsigned char INTVEC : 8; +#endif +}; + +union un_sdsi_fn1intvecr +{ + unsigned char BYTE; + struct st_sdsi_fn1intvecr_bit BIT; +}; + +struct st_sdsi_fn1intclrr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INTCTR : 8; +#else + unsigned char INTCTR : 8; +#endif +}; + +union un_sdsi_fn1intclrr +{ + unsigned char BYTE; + struct st_sdsi_fn1intclrr_bit BIT; +}; + +struct st_sdsi_fn1datar5_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +union un_sdsi_fn1datar5 +{ + unsigned long LONG; + struct st_sdsi_fn1datar5_byte BYTE; +}; + +struct st_mtu6_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu6_tcr +{ + unsigned char BYTE; + struct st_mtu6_tcr_bit BIT; +}; + +struct st_mtu6_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu6_tmdr1 +{ + unsigned char BYTE; + struct st_mtu6_tmdr1_bit BIT; +}; + +struct st_mtu6_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu6_tiorh +{ + unsigned char BYTE; + struct st_mtu6_tiorh_bit BIT; +}; + +struct st_mtu6_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu6_tiorl +{ + unsigned char BYTE; + struct st_mtu6_tiorl_bit BIT; +}; + +struct st_mtu6_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu6_tier +{ + unsigned char BYTE; + struct st_mtu6_tier_bit BIT; +}; + +struct st_mtu6_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; + +union un_mtu6_tsr +{ + unsigned char BYTE; + struct st_mtu6_tsr_bit BIT; +}; + +struct st_mtu6_tbtm_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif +}; + +union un_mtu6_tbtm +{ + unsigned char BYTE; + struct st_mtu6_tbtm_bit BIT; +}; + +struct st_mtu6_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu6_tcr2 +{ + unsigned char BYTE; + struct st_mtu6_tcr2_bit BIT; +}; + +struct st_mtu6_tsycr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CE2B : 1; + unsigned char CE2A : 1; + unsigned char CE1B : 1; + unsigned char CE1A : 1; + unsigned char CE0D : 1; + unsigned char CE0C : 1; + unsigned char CE0B : 1; + unsigned char CE0A : 1; +#else + unsigned char CE0A : 1; + unsigned char CE0B : 1; + unsigned char CE0C : 1; + unsigned char CE0D : 1; + unsigned char CE1A : 1; + unsigned char CE1B : 1; + unsigned char CE2A : 1; + unsigned char CE2B : 1; +#endif +}; + +union un_mtu6_tsycr +{ + unsigned char BYTE; + struct st_mtu6_tsycr_bit BIT; +}; + +struct st_mtu7_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu7_tcr +{ + unsigned char BYTE; + struct st_mtu7_tcr_bit BIT; +}; + +struct st_mtu7_tmdr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu7_tmdr1 +{ + unsigned char BYTE; + struct st_mtu7_tmdr1_bit BIT; +}; + +struct st_mtu7_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu7_tiorh +{ + unsigned char BYTE; + struct st_mtu7_tiorh_bit BIT; +}; + +struct st_mtu7_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu7_tiorl +{ + unsigned char BYTE; + struct st_mtu7_tiorl_bit BIT; +}; + +struct st_mtu7_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu7_tier +{ + unsigned char BYTE; + struct st_mtu7_tier_bit BIT; +}; + +struct st_mtu7_tsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif +}; + +union un_mtu7_tsr +{ + unsigned char BYTE; + struct st_mtu7_tsr_bit BIT; +}; + +struct st_mtu7_tbtm_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif +}; + +union un_mtu7_tbtm +{ + unsigned char BYTE; + struct st_mtu7_tbtm_bit BIT; +}; + +struct st_mtu7_tadcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITA6AE : 1; + unsigned short DT7BE : 1; + unsigned short UT7BE : 1; + unsigned short DT7AE : 1; + unsigned short UT7AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT7AE : 1; + unsigned short DT7AE : 1; + unsigned short UT7BE : 1; + unsigned short DT7BE : 1; + unsigned short ITA6AE : 1; + unsigned short ITA7VE : 1; + unsigned short ITB6AE : 1; + unsigned short ITB7VE : 1; +#endif +}; + +union un_mtu7_tadcr +{ + unsigned char BYTE; + struct st_mtu7_tadcr_bit BIT; +}; +struct st_mtu7_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu7_tcr2 +{ + unsigned char BYTE; + struct st_mtu7_tcr2_bit BIT; +}; + +struct st_mtu7_nfcr7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu7_nfcr7 +{ + unsigned char BYTE; + struct st_mtu7_nfcr7_bit BIT; +}; + +struct st_mtu8_nfcr8_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif +}; + +union un_mtu8_nfcr8 +{ + unsigned char BYTE; + struct st_mtu8_nfcr8_bit BIT; +}; +struct st_mtu8_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif +}; + +union un_mtu8_tcr +{ + unsigned char BYTE; + struct st_mtu8_tcr_bit BIT; +}; + +struct st_mtu8_tmdr1_bit +{ + #ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif +}; + +union un_mtu8_tmdr1 +{ + unsigned char BYTE; + struct st_mtu8_tmdr1_bit BIT; +}; + +struct st_mtu8_tiorh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif +}; + +union un_mtu8_tiorh +{ + unsigned char BYTE; + struct st_mtu8_tiorh_bit BIT; +}; + +struct st_mtu8_tiorl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif +}; + +union un_mtu8_tiorl +{ + unsigned char BYTE; + struct st_mtu8_tiorl_bit BIT; +}; + +struct st_mtu8_tier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif +}; + +union un_mtu8_tier +{ + unsigned char BYTE; + struct st_mtu8_tier_bit BIT; +}; + +struct st_mtu8_tcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC2 : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TPSC2 : 3; +#endif +}; + +union un_mtu8_tcr2 +{ + unsigned char BYTE; + struct st_mtu8_tcr2_bit BIT; +}; + +struct st_port6_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_pdr +{ + unsigned char BYTE; + struct st_port6_pdr_bit BIT; +}; + +struct st_port6_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_podr +{ + unsigned char BYTE; + struct st_port6_podr_bit BIT; +}; + +struct st_port6_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_pidr +{ + unsigned char BYTE; + struct st_port6_pidr_bit BIT; +}; + +struct st_port6_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_pmr +{ + unsigned char BYTE; + struct st_port6_pmr_bit BIT; +}; + +struct st_port6_ord0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_ord0 +{ + unsigned char BYTE; + struct st_port6_ord0_bit BIT; +}; + +struct st_port6_ord1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_ord1 +{ + unsigned char BYTE; + struct st_port6_ord1_bit BIT; +}; + +struct st_port6_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_port6_pcr +{ + unsigned char BYTE; + struct st_port6_pcr_bit BIT; +}; + +struct st_can_mb_id_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_mb_id_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_mb_id_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif +}; + +union un_can_id +{ + unsigned long LONG; + struct st_can_mb_id_word WORD; + struct st_can_mb_id_byte BYTE; + struct st_can_mb_id_bit BIT; +}; + +struct st_can_mb +{ + union un_can_id ID; + unsigned short DLC; + unsigned char DATA[8]; + unsigned short TS; +}; + +struct st_can_mkr_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_mkr_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_mkr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long SID : 11; + unsigned long EID : 18; +#endif +}; + +union un_can_mkr +{ + unsigned long LONG; + struct st_can_mkr_word WORD; + struct st_can_mkr_byte BYTE; + struct st_can_mkr_bit BIT; +}; + +struct st_can_fidcr0_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_fidcr0_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_fidcr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif +}; + +union un_can_fidcr0 +{ + unsigned long LONG; + struct st_can_fidcr0_word WORD; + struct st_can_fidcr0_byte BYTE; + struct st_can_fidcr0_bit BIT; +}; + +struct st_can_fidcr1_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_fidcr1_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_fidcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EID : 18; + unsigned long SID : 11; + unsigned long : 1; + unsigned long RTR : 1; + unsigned long IDE : 1; +#else + unsigned long IDE : 1; + unsigned long RTR : 1; + unsigned long : 1; + unsigned long SID : 11; + unsigned long EID : 18; +#endif +}; + +union un_can_fidcr1 +{ + unsigned long LONG; + struct st_can_fidcr1_word WORD; + struct st_can_fidcr1_byte BYTE; + struct st_can_fidcr1_bit BIT; +}; + +struct st_can_mkivlr_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_mkivlr_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_mkivlr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif +}; + +union un_can_mkivlr +{ + unsigned long LONG; + struct st_can_mkivlr_word WORD; + struct st_can_mkivlr_byte BYTE; + struct st_can_mkivlr_bit BIT; +}; + +struct st_can_mier_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_mier_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_mier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MB0 : 1; + unsigned long MB1 : 1; + unsigned long MB2 : 1; + unsigned long MB3 : 1; + unsigned long MB4 : 1; + unsigned long MB5 : 1; + unsigned long MB6 : 1; + unsigned long MB7 : 1; + unsigned long MB8 : 1; + unsigned long MB9 : 1; + unsigned long MB10 : 1; + unsigned long MB11 : 1; + unsigned long MB12 : 1; + unsigned long MB13 : 1; + unsigned long MB14 : 1; + unsigned long MB15 : 1; + unsigned long MB16 : 1; + unsigned long MB17 : 1; + unsigned long MB18 : 1; + unsigned long MB19 : 1; + unsigned long MB20 : 1; + unsigned long MB21 : 1; + unsigned long MB22 : 1; + unsigned long MB23 : 1; + unsigned long MB24 : 1; + unsigned long MB25 : 1; + unsigned long MB26 : 1; + unsigned long MB27 : 1; + unsigned long MB28 : 1; + unsigned long MB29 : 1; + unsigned long MB30 : 1; + unsigned long MB31 : 1; +#else + unsigned long MB31 : 1; + unsigned long MB30 : 1; + unsigned long MB29 : 1; + unsigned long MB28 : 1; + unsigned long MB27 : 1; + unsigned long MB26 : 1; + unsigned long MB25 : 1; + unsigned long MB24 : 1; + unsigned long MB23 : 1; + unsigned long MB22 : 1; + unsigned long MB21 : 1; + unsigned long MB20 : 1; + unsigned long MB19 : 1; + unsigned long MB18 : 1; + unsigned long MB17 : 1; + unsigned long MB16 : 1; + unsigned long MB15 : 1; + unsigned long MB14 : 1; + unsigned long MB13 : 1; + unsigned long MB12 : 1; + unsigned long MB11 : 1; + unsigned long MB10 : 1; + unsigned long MB9 : 1; + unsigned long MB8 : 1; + unsigned long MB7 : 1; + unsigned long MB6 : 1; + unsigned long MB5 : 1; + unsigned long MB4 : 1; + unsigned long MB3 : 1; + unsigned long MB2 : 1; + unsigned long MB1 : 1; + unsigned long MB0 : 1; +#endif +}; + +union un_can_mier +{ + unsigned long LONG; + struct st_can_mier_word WORD; + struct st_can_mier_byte BYTE; + struct st_can_mier_bit BIT; +}; + +struct st_can_mctl_bit_tx +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SENTDATA : 1; + unsigned char TRMACTIVE : 1; + unsigned char TRMABT : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char TRMABT : 1; + unsigned char TRMACTIVE : 1; + unsigned char SENTDATA : 1; +#endif +}; + +struct st_can_mctl_bit_rx +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NEWDATA : 1; + unsigned char INVALDATA : 1; + unsigned char MSGLOST : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char RECREQ : 1; + unsigned char TRMREQ : 1; +#else + unsigned char TRMREQ : 1; + unsigned char RECREQ : 1; + unsigned char : 1; + unsigned char ONESHOT : 1; + unsigned char : 1; + unsigned char MSGLOST : 1; + unsigned char INVALDATA : 1; + unsigned char NEWDATA : 1; +#endif +}; + +union un_can_mctl_bit +{ + struct st_can_mctl_bit_tx TX; + struct st_can_mctl_bit_rx RX; +}; + +union un_can_mctl +{ + unsigned char BYTE; +}; + +struct st_can_ctlr_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_can_ctlr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MBM : 1; + unsigned short IDFM : 2; + unsigned short MLM : 1; + unsigned short TPM : 1; + unsigned short TSRC : 1; + unsigned short TSPS : 2; + unsigned short CANM : 2; + unsigned short SLPM : 1; + unsigned short BOM : 2; + unsigned short RBOC : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RBOC : 1; + unsigned short BOM : 2; + unsigned short SLPM : 1; + unsigned short CANM : 2; + unsigned short TSPS : 2; + unsigned short TSRC : 1; + unsigned short TPM : 1; + unsigned short MLM : 1; + unsigned short IDFM : 2; + unsigned short MBM : 1; +#endif +}; + +union un_can_ctlr +{ + unsigned short WORD; + struct st_can_ctlr_byte BYTE; + struct st_can_ctlr_bit BIT; +}; + +struct st_can_str_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_can_str_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NDST : 1; + unsigned short SDST : 1; + unsigned short RFST : 1; + unsigned short TFST : 1; + unsigned short NMLST : 1; + unsigned short FMLST : 1; + unsigned short TABST : 1; + unsigned short EST : 1; + unsigned short RSTST : 1; + unsigned short HLTST : 1; + unsigned short SLPST : 1; + unsigned short EPST : 1; + unsigned short BOST : 1; + unsigned short TRMST : 1; + unsigned short RECST : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RECST : 1; + unsigned short TRMST : 1; + unsigned short BOST : 1; + unsigned short EPST : 1; + unsigned short SLPST : 1; + unsigned short HLTST : 1; + unsigned short RSTST : 1; + unsigned short EST : 1; + unsigned short TABST : 1; + unsigned short FMLST : 1; + unsigned short NMLST : 1; + unsigned short TFST : 1; + unsigned short RFST : 1; + unsigned short SDST : 1; + unsigned short NDST : 1; +#endif +}; + +union un_can_str +{ + unsigned short WORD; + struct st_can_str_byte BYTE; + struct st_can_str_bit BIT; +}; + +struct st_can_bcr_word +{ + unsigned short H; + unsigned short L; +}; + +struct st_can_bcr_byte +{ + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; +}; + +struct st_can_bcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CCLKS : 1; + unsigned long : 7; + unsigned long TSEG2 : 3; + unsigned long : 1; + unsigned long SJW : 2; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long TSEG1 : 4; +#else + unsigned long TSEG1 : 4; + unsigned long : 2; + unsigned long BRP : 10; + unsigned long : 2; + unsigned long SJW : 2; + unsigned long : 1; + unsigned long TSEG2 : 3; + unsigned long : 7; + unsigned long CCLKS : 1; +#endif +}; + +union un_can_bcr +{ + unsigned long LONG; + struct st_can_bcr_word WORD; + struct st_can_bcr_byte BYTE; + struct st_can_bcr_bit BIT; +}; + +struct st_can_rfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFE : 1; + unsigned char RFUST : 3; + unsigned char RFMLF : 1; + unsigned char RFFST : 1; + unsigned char RFWST : 1; + unsigned char RFEST : 1; +#else + unsigned char RFEST : 1; + unsigned char RFWST : 1; + unsigned char RFFST : 1; + unsigned char RFMLF : 1; + unsigned char RFUST : 3; + unsigned char RFE : 1; +#endif +}; + +union un_can_rfcr +{ + unsigned char BYTE; + struct st_can_rfcr_bit BIT; +}; + +struct st_can_tfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TFE : 1; + unsigned char TFUST : 3; + unsigned char : 2; + unsigned char TFFST : 1; + unsigned char TFEST : 1; +#else + unsigned char TFEST : 1; + unsigned char TFFST : 1; + unsigned char : 2; + unsigned char TFUST : 3; + unsigned char TFE : 1; +#endif +}; + +union un_can_tfcr +{ + unsigned char BYTE; + struct st_can_tfcr_bit BIT; +}; + +struct st_can_eier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIE : 1; + unsigned char EWIE : 1; + unsigned char EPIE : 1; + unsigned char BOEIE : 1; + unsigned char BORIE : 1; + unsigned char ORIE : 1; + unsigned char OLIE : 1; + unsigned char BLIE : 1; +#else + unsigned char BLIE : 1; + unsigned char OLIE : 1; + unsigned char ORIE : 1; + unsigned char BORIE : 1; + unsigned char BOEIE : 1; + unsigned char EPIE : 1; + unsigned char EWIE : 1; + unsigned char BEIE : 1; +#endif +}; + +union un_can_eier +{ + unsigned char BYTE; + struct st_can_eier_bit BIT; +}; + +struct st_can_eifr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BEIF : 1; + unsigned char EWIF : 1; + unsigned char EPIF : 1; + unsigned char BOEIF : 1; + unsigned char BORIF : 1; + unsigned char ORIF : 1; + unsigned char OLIF : 1; + unsigned char BLIF : 1; +#else + unsigned char BLIF : 1; + unsigned char OLIF : 1; + unsigned char ORIF : 1; + unsigned char BORIF : 1; + unsigned char BOEIF : 1; + unsigned char EPIF : 1; + unsigned char EWIF : 1; + unsigned char BEIF : 1; +#endif +}; + +union un_can_eifr +{ + unsigned char BYTE; + struct st_can_eifr_bit BIT; +}; + +struct st_can_ecsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEF : 1; + unsigned char FEF : 1; + unsigned char AEF : 1; + unsigned char CEF : 1; + unsigned char BE1F : 1; + unsigned char BE0F : 1; + unsigned char ADEF : 1; + unsigned char EDPM : 1; +#else + unsigned char EDPM : 1; + unsigned char ADEF : 1; + unsigned char BE0F : 1; + unsigned char BE1F : 1; + unsigned char CEF : 1; + unsigned char AEF : 1; + unsigned char FEF : 1; + unsigned char SEF : 1; +#endif +}; + +union un_can_ecsr +{ + unsigned char BYTE; + struct st_can_ecsr_bit BIT; +}; + +struct st_can_mssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBNST : 5; + unsigned char : 2; + unsigned char SEST : 1; +#else + unsigned char SEST : 1; + unsigned char : 2; + unsigned char MBNST : 5; +#endif +}; + +union un_can_mssr +{ + unsigned char BYTE; + struct st_can_mssr_bit BIT; +}; + +struct st_can_msmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MBSM : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MBSM : 2; +#endif +}; + +union un_can_msmr +{ + unsigned char BYTE; + struct st_can_msmr_bit BIT; +}; + +struct st_can_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSTE : 1; + unsigned char TSTM : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TSTM : 2; + unsigned char TSTE : 1; +#endif +}; + +union un_can_tcr +{ + unsigned char BYTE; + struct st_can_tcr_bit BIT; +}; + +struct st_dmac_dmast_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif +}; + +union un_dmac_dmast +{ + unsigned char BYTE; + struct st_dmac_dmast_bit BIT; +}; + +struct st_dmac_dmist_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char DMIS4 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS7 : 1; +#else + unsigned char DMIS7 : 1; + unsigned char DMIS6 : 1; + unsigned char DMIS5 : 1; + unsigned char DMIS4 : 1; + unsigned char : 4; +#endif +}; + +union un_dmac_dmist +{ + unsigned char BYTE; + struct st_dmac_dmist_bit BIT; +}; + +struct st_dmac0_dmtmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif +}; + +union un_dmac0_dmtmd +{ + unsigned short WORD; + struct st_dmac0_dmtmd_bit BIT; +}; + +struct st_dmac0_dmint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif +}; + +union un_dmac0_dmint +{ + unsigned char BYTE; + struct st_dmac0_dmint_bit BIT; +}; + +struct un_dmac0_dmamd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif +}; + +union un_dmac0_dmamd +{ + unsigned short WORD; + struct un_dmac0_dmamd_bit BIT; +}; + +struct st_dmac0_dmcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif +}; + +union un_dmac0_dmcnt +{ + unsigned char BYTE; + struct st_dmac0_dmcnt_bit BIT; +}; + +struct st_dmac0_dmreq_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif +}; + +union un_dmac0_dmreq +{ + unsigned char BYTE; + struct st_dmac0_dmreq_bit BIT; +}; + +struct st_dmac0_dmsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif +}; + +union un_dmac0_dmsts +{ + unsigned char BYTE; + struct st_dmac0_dmsts_bit BIT; +}; + +struct st_dmac0_dmcsl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif +}; + +union un_dmac0_dmcsl +{ + unsigned char BYTE; + struct st_dmac0_dmcsl_bit BIT; +}; + +struct st_dmac1_dmtmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif +}; + +union un_dmac1_dmtmd +{ + unsigned short WORD; + struct st_dmac1_dmtmd_bit BIT; +}; + +struct st_dmac1_dmint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif +}; + +union un_dmac1_dmint +{ + unsigned char BYTE; + struct st_dmac1_dmint_bit BIT; +}; + +struct st_dmac1_dmamd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif +}; + +union un_dmac1_dmamd +{ + unsigned short WORD; + struct st_dmac1_dmamd_bit BIT; +}; + +struct st_dmac1_dmcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif +}; + +union un_dmac1_dmcnt +{ + unsigned char BYTE; + struct st_dmac1_dmcnt_bit BIT; +}; + +struct st_dmac1_dmreq_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif +}; + +union un_dmac1_dmreq +{ + unsigned char BYTE; + struct st_dmac1_dmreq_bit BIT; +}; + +struct st_dmac1_dmsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif +}; + +union un_dmac1_dmsts +{ + unsigned char BYTE; + struct st_dmac1_dmsts_bit BIT; +}; + +struct st_dmac1_dmcsl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif +}; + +union un_dmac1_dmcsl +{ + unsigned char BYTE; + struct st_dmac1_dmcsl_bit BIT; +}; + +struct st_drw2d_control_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LIM1EN : 1; + unsigned long LIM2EN : 1; + unsigned long LIM3EN : 1; + unsigned long LIM4EN : 1; + unsigned long LIM5EN : 1; + unsigned long LIM6EN : 1; + unsigned long QUAD1EN : 1; + unsigned long QUAD2EN : 1; + unsigned long QUAD3EN : 1; + unsigned long LIM1TH : 1; + unsigned long LIM2TH : 1; + unsigned long LIM3TH : 1; + unsigned long LIM4TH : 1; + unsigned long LIM5TH : 1; + unsigned long LIM6TH : 1; + unsigned long BAND1EN : 1; + unsigned long BAND2EN : 1; + unsigned long UNION12 : 1; + unsigned long UNION34 : 1; + unsigned long UNION56 : 1; + unsigned long UNIONAB : 1; + unsigned long UNIONCD : 1; + unsigned long SPANABT : 1; + unsigned long SPANSTR : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long SPANSTR : 1; + unsigned long SPANABT : 1; + unsigned long UNIONCD : 1; + unsigned long UNIONAB : 1; + unsigned long UNION56 : 1; + unsigned long UNION34 : 1; + unsigned long UNION12 : 1; + unsigned long BAND2EN : 1; + unsigned long BAND1EN : 1; + unsigned long LIM6TH : 1; + unsigned long LIM5TH : 1; + unsigned long LIM4TH : 1; + unsigned long LIM3TH : 1; + unsigned long LIM2TH : 1; + unsigned long LIM1TH : 1; + unsigned long QUAD3EN : 1; + unsigned long QUAD2EN : 1; + unsigned long QUAD1EN : 1; + unsigned long LIM6EN : 1; + unsigned long LIM5EN : 1; + unsigned long LIM4EN : 1; + unsigned long LIM3EN : 1; + unsigned long LIM2EN : 1; + unsigned long LIM1EN : 1; +#endif +}; + +union un_drw2d_control +{ + unsigned long LONG; + struct st_drw2d_control_bit BIT; +}; + +struct st_drw2d_status_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BSYENUM : 1; + unsigned long BSYWR : 1; + unsigned long CACHEDTY : 1; + unsigned long DLSTACT : 1; + unsigned long ENUIR : 1; + unsigned long DLIR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long DLIR : 1; + unsigned long ENUIR : 1; + unsigned long DLSTACT : 1; + unsigned long CACHEDTY : 1; + unsigned long BSYWR : 1; + unsigned long BSYENUM : 1; +#endif +}; + +union un_drw2d_status +{ + unsigned long LONG; + struct st_drw2d_status_bit BIT; +}; + +struct st_drw2d_control2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PTNEN : 1; + unsigned long TEXENA : 1; + unsigned long PTNSRCL5 : 1; + unsigned long USEACB : 1; + unsigned long RDFMT2 : 2; + unsigned long BSFA : 1; + unsigned long BDFA : 1; + unsigned long WRFMT2 : 1; + unsigned long BSF : 1; + unsigned long BDF : 1; + unsigned long BSI : 1; + unsigned long BDI : 1; + unsigned long BC2 : 1; + unsigned long TEXCLPX : 1; + unsigned long TEXCLPY : 1; + unsigned long TEXFILTX : 1; + unsigned long TEXFILTY : 1; + unsigned long RDFMT : 2; + unsigned long WRFMT : 2; + unsigned long WRALPHA : 2; + unsigned long RLEEN : 1; + unsigned long CLUTEN : 1; + unsigned long COLKEYEN : 1; + unsigned long CLUTFORM : 1; + unsigned long BSIA : 1; + unsigned long BDIA : 1; + unsigned long RLEPIXW : 2; +#else + unsigned long RLEPIXW : 2; + unsigned long BDIA : 1; + unsigned long BSIA : 1; + unsigned long CLUTFORM : 1; + unsigned long COLKEYEN : 1; + unsigned long CLUTEN : 1; + unsigned long RLEEN : 1; + unsigned long WRALPHA : 2; + unsigned long WRFMT : 2; + unsigned long RDFMT : 2; + unsigned long TEXFILTY : 1; + unsigned long TEXFILTX : 1; + unsigned long TEXCLPY : 1; + unsigned long TEXCLPX : 1; + unsigned long BC2 : 1; + unsigned long BDI : 1; + unsigned long BSI : 1; + unsigned long BDF : 1; + unsigned long BSF : 1; + unsigned long WRFMT2 : 1; + unsigned long BDFA : 1; + unsigned long BSFA : 1; + unsigned long RDFMT2 : 2; + unsigned long USEACB : 1; + unsigned long PTNSRCL5 : 1; + unsigned long TEXENA : 1; + unsigned long PTNEN : 1; +#endif +}; + +union un_drw2d_control2 +{ + unsigned long LONG; + struct st_drw2d_control2_bit BIT; +}; + +struct st_drw2d_hwver_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REV : 12; + unsigned long : 5; + unsigned long DLR : 1; + unsigned long FBCACHE : 1; + unsigned long TXCACHE : 1; + unsigned long PERFCNT : 1; + unsigned long TEXCLUT : 1; + unsigned long : 1; + unsigned long RLEUNIT : 1; + unsigned long TEXCLUT256 : 1; + unsigned long COLKEY : 1; + unsigned long : 1; + unsigned long ACBLD : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long ACBLD : 1; + unsigned long : 1; + unsigned long COLKEY : 1; + unsigned long TEXCLUT256 : 1; + unsigned long RLEUNIT : 1; + unsigned long : 1; + unsigned long TEXCLUT : 1; + unsigned long PERFCNT : 1; + unsigned long TXCACHE : 1; + unsigned long FBCACHE : 1; + unsigned long DLR : 1; + unsigned long : 5; + unsigned long REV : 12; +#endif +}; + +union un_drw2d_hwver +{ + unsigned long LONG; + struct st_drw2d_hwver_bit BIT; +}; + +struct st_drw2d_color1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long COL1B : 8; + unsigned long COL1G : 8; + unsigned long COL1R : 8; + unsigned long COL1A : 8; +#else + unsigned long COL1A : 8; + unsigned long COL1R : 8; + unsigned long COL1G : 8; + unsigned long COL1B : 8; +#endif +}; + +union un_drw2d_color1 +{ + unsigned long LONG; + struct st_drw2d_color1_bit BIT; +}; + +struct st_drw2d_color2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long COL2B : 8; + unsigned long COL2G : 8; + unsigned long COL2R : 8; + unsigned long COL2A : 8; +#else + unsigned long COL2A : 8; + unsigned long COL2R : 8; + unsigned long COL2G : 8; + unsigned long COL2B : 8; +#endif +}; + +union un_drw2d_color2 +{ + unsigned long LONG; + struct st_drw2d_color2_bit BIT; +}; + +struct st_drw2d_size_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long X : 16; + unsigned long Y : 16; +#else + unsigned long Y : 16; + unsigned long X : 16; +#endif +}; + +union un_drw2d_size +{ + unsigned long LONG; + struct st_drw2d_size_bit BIT; +}; + +struct st_drw2d_pitch_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PITCH : 16; + unsigned long SSD : 16; +#else + unsigned long SSD : 16; + unsigned long PITCH : 16; +#endif +}; + +union un_drw2d_pitch +{ + unsigned long LONG; + struct st_drw2d_pitch_bit BIT; +}; + +struct st_drw2d_lvyxaddf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LVXADDF : 16; + unsigned long LVYADDF : 16; +#else + unsigned long LVYADDF : 16; + unsigned long LVXADDF : 16; +#endif +}; + +union un_drw2d_lvyxaddf +{ + unsigned long LONG; + struct st_drw2d_lvyxaddf_bit BIT; +}; + +struct st_drw2d_texmsk_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TEXUMSK : 11; + unsigned long TEXVMSK : 21; +#else + unsigned long TEXVMSK : 21; + unsigned long TEXUMSK : 11; +#endif +}; + +union un_drw2d_texmsk +{ + unsigned long LONG; + struct st_drw2d_texmsk_bit BIT; +}; + +struct st_drw2d_irqctl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ENUIREN : 1; + unsigned long DLIREN : 1; + unsigned long ENUIRCLR : 1; + unsigned long DLIRCLR : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long DLIRCLR : 1; + unsigned long ENUIRCLR : 1; + unsigned long DLIREN : 1; + unsigned long ENUIREN : 1; +#endif +}; + +union un_drw2d_irqctl +{ + unsigned long LONG; + struct st_drw2d_irqctl_bit BIT; +}; + +struct st_drw2d_cachectl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CENFX : 1; + unsigned long CFLUFX : 1; + unsigned long CENTX : 1; + unsigned long CFLUTX : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long CFLUTX : 1; + unsigned long CENTX : 1; + unsigned long CFLUFX : 1; + unsigned long CENFX : 1; +#endif +}; + +union un_drw2d_cachectl +{ + unsigned long LONG; + struct st_drw2d_cachectl_bit BIT; +}; + +struct st_drw2d_perftrg_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TRG1 : 16; + unsigned long TRG2 : 16; +#else + unsigned long TRG2 : 16; + unsigned long TRG1 : 16; +#endif +}; + +union un_drw2d_perftrg +{ + unsigned long LONG; + struct st_drw2d_perftrg_bit BIT; +}; + +struct st_drw2d_colkey_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long B : 8; + unsigned long G : 8; + unsigned long R : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long R : 8; + unsigned long G : 8; + unsigned long B : 8; +#endif +}; + +union un_drw2d_colkey +{ + unsigned long LONG; + struct st_drw2d_colkey_bit BIT; +}; + +struct st_dtc_dtccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif +}; + +union un_dtc_dtccr +{ + unsigned char BYTE; + struct st_dtc_dtccr_bit BIT; +}; + +struct st_dtc_dtcadmod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif +}; + +union un_dtc_dtcadmod +{ + unsigned char BYTE; + struct st_dtc_dtcadmod_bit BIT; +}; + +struct st_dtc_dtcst_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif +}; + +union un_dtc_dtcst +{ + unsigned char BYTE; + struct st_dtc_dtcst_bit BIT; +}; + +struct st_dtc_dtcsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif +}; + +union un_dtc_dtcsts +{ + unsigned short WORD; + struct st_dtc_dtcsts_bit BIT; +}; + +struct st_dtc_dtcor_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SQTFRL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SQTFRL : 1; +#endif +}; + +union un_dtc_dtcor +{ + unsigned char BYTE; + struct st_dtc_dtcor_bit BIT; +}; + +struct st_dtc_dtcsqe_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ESPSEL : 1; +#else + unsigned short ESPSEL : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif +}; + +union un_dtc_dtcsqe +{ + unsigned short WORD; + struct st_dtc_dtcsqe_bit BIT; +}; + +struct st_edmac_edmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SWR : 1; + unsigned long : 3; + unsigned long DL : 2; + unsigned long DE : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long DE : 1; + unsigned long DL : 2; + unsigned long : 3; + unsigned long SWR : 1; +#endif +}; + +union un_edmac_edmr +{ + unsigned long LONG; + struct st_edmac_edmr_bit BIT; +}; + +struct st_edmac_edtrr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long TR : 1; +#endif +}; + +union un_edmac_edtrr +{ + unsigned long LONG; + struct st_edmac_edtrr_bit BIT; +}; + +struct st_edmac_edrrr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RR : 1; +#endif +}; + +union un_edmac_edrrr +{ + unsigned long LONG; + struct st_edmac_edrrr_bit BIT; +}; + +struct st_edmac_eesr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERF : 1; + unsigned long PRE : 1; + unsigned long RTSF : 1; + unsigned long RTLF : 1; + unsigned long RRF : 1; + unsigned long : 2; + unsigned long RMAF : 1; + unsigned long TRO : 1; + unsigned long CD : 1; + unsigned long DLC : 1; + unsigned long CND : 1; + unsigned long : 4; + unsigned long RFOF : 1; + unsigned long RDE : 1; + unsigned long FR : 1; + unsigned long TFUF : 1; + unsigned long TDE : 1; + unsigned long TC : 1; + unsigned long ECI : 1; + unsigned long : 1; + unsigned long RFCOF : 1; + unsigned long RABT : 1; + unsigned long TABT : 1; + unsigned long : 3; + unsigned long TWB : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWB : 1; + unsigned long : 3; + unsigned long TABT : 1; + unsigned long RABT : 1; + unsigned long RFCOF : 1; + unsigned long : 1; + unsigned long ECI : 1; + unsigned long TC : 1; + unsigned long TDE : 1; + unsigned long TFUF : 1; + unsigned long FR : 1; + unsigned long RDE : 1; + unsigned long RFOF : 1; + unsigned long : 4; + unsigned long CND : 1; + unsigned long DLC : 1; + unsigned long CD : 1; + unsigned long TRO : 1; + unsigned long RMAF : 1; + unsigned long : 2; + unsigned long RRF : 1; + unsigned long RTLF : 1; + unsigned long RTSF : 1; + unsigned long PRE : 1; + unsigned long CERF : 1; +#endif +}; + +union un_edmac_eesr +{ + unsigned long LONG; + struct st_edmac_eesr_bit BIT; +}; + +struct st_edmac_eesipr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CERFIP : 1; + unsigned long PREIP : 1; + unsigned long RTSFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RRFIP : 1; + unsigned long : 2; + unsigned long RMAFIP : 1; + unsigned long TROIP : 1; + unsigned long CDIP : 1; + unsigned long DLCIP : 1; + unsigned long CNDIP : 1; + unsigned long : 4; + unsigned long RFOFIP : 1; + unsigned long RDEIP : 1; + unsigned long FRIP : 1; + unsigned long TFUFIP : 1; + unsigned long TDEIP : 1; + unsigned long TCIP : 1; + unsigned long ECIIP : 1; + unsigned long : 1; + unsigned long RFCOFIP : 1; + unsigned long RABTIP : 1; + unsigned long TABTIP : 1; + unsigned long : 3; + unsigned long TWBIP : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long TWBIP : 1; + unsigned long : 3; + unsigned long TABTIP : 1; + unsigned long RABTIP : 1; + unsigned long RFCOFIP : 1; + unsigned long : 1; + unsigned long ECIIP : 1; + unsigned long TCIP : 1; + unsigned long TDEIP : 1; + unsigned long TFUFIP : 1; + unsigned long FRIP : 1; + unsigned long RDEIP : 1; + unsigned long RFOFIP : 1; + unsigned long : 4; + unsigned long CNDIP : 1; + unsigned long DLCIP : 1; + unsigned long CDIP : 1; + unsigned long TROIP : 1; + unsigned long RMAFIP : 1; + unsigned long : 2; + unsigned long RRFIP : 1; + unsigned long RTLFIP : 1; + unsigned long RTSFIP : 1; + unsigned long PREIP : 1; + unsigned long CERFIP : 1; +#endif +}; + +union un_edmac_eesipr +{ + unsigned long LONG; + struct st_edmac_eesipr_bit BIT; +}; + +struct st_edmac_trscer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RRFCE : 1; + unsigned long : 2; + unsigned long RMAFCE : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RMAFCE : 1; + unsigned long : 2; + unsigned long RRFCE : 1; + unsigned long : 4; +#endif +}; + +union un_edmac_trscer +{ + unsigned long LONG; + struct st_edmac_trscer_bit BIT; +}; + +struct st_edmac_rmfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MFC : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MFC : 16; +#endif +}; + +union un_edmac_rmfcr +{ + unsigned long LONG; + struct st_edmac_rmfcr_bit BIT; +}; + +struct st_edmac_tftr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TFT : 11; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long TFT : 11; +#endif +}; + +union un_edmac_tftr +{ + unsigned long LONG; + struct st_edmac_tftr_bit BIT; +}; + +struct st_edamc_fdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFD : 5; + unsigned long : 3; + unsigned long TFD : 5; + unsigned long : 19; +#else + unsigned long : 19; + unsigned long TFD : 5; + unsigned long : 3; + unsigned long RFD : 5; +#endif +}; + +union un_edmac_fdr +{ + unsigned long LONG; + struct st_edamc_fdr_bit BIT; +}; + +struct st_edmac_rmcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RNR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long RNR : 1; +#endif +}; + +union un_edmac_rmcr +{ + unsigned long LONG; + struct st_edmac_rmcr_bit BIT; +}; + +struct st_edmac_tfucr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long UNDER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long UNDER : 16; +#endif +}; + +union un_edmac_tfucr +{ + unsigned long LONG; + struct st_edmac_tfucr_bit BIT; +}; + +struct st_edmac_rfocr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long OVER : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long OVER : 16; +#endif +}; + +union un_edmac_rfocr +{ + unsigned long LONG; + struct st_edmac_rfocr_bit BIT; +}; + +struct st_edmac_iosr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ELB : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long ELB : 1; +#endif +}; + +union un_edmac_iosr +{ + unsigned long LONG; + struct st_edmac_iosr_bit BIT; +}; + +struct st_edmac_fcftr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFDO : 3; + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RFFO : 3; + unsigned long : 13; + unsigned long RFDO : 3; +#endif +}; + +union un_edmac_fcftr +{ + unsigned long LONG; + struct st_edmac_fcftr_bit BIT; +}; + +struct st_edmac_rpadir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PADR : 6; + unsigned long : 10; + unsigned long PADS : 2; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long PADS : 2; + unsigned long : 10; + unsigned long PADR : 6; +#endif +}; + +union un_edmac_rpadir +{ + unsigned long LONG; + struct st_edmac_rpadir_bit BIT; +}; + +struct st_edmac_trmid_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TIS : 1; + unsigned long : 3; + unsigned long TIM : 1; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long TIM : 1; + unsigned long : 3; + unsigned long TIS : 1; +#endif +}; + +union un_edmac_trimd +{ + unsigned long LONG; + struct st_edmac_trmid_bit BIT; +}; + +struct st_elc_elcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif +}; + +union un_elc_elcr +{ + unsigned char BYTE; + struct st_elc_elcr_bit BIT; +}; + +struct st_elc_elsr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr0 +{ + unsigned char BYTE; + struct st_elc_elsr0_bit BIT; +}; + +struct st_elc_elsr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr3 +{ + unsigned char BYTE; + struct st_elc_elsr3_bit BIT; +}; + +struct st_elc_elsr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr4 +{ + unsigned char BYTE; + struct st_elc_elsr4_bit BIT; +}; + +struct st_elc_elsr7_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr7 +{ + unsigned char BYTE; + struct st_elc_elsr7_bit BIT; +}; + +struct st_elc_elsr10_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr10 +{ + unsigned char BYTE; + struct st_elc_elsr10_bit BIT; +}; + +struct st_elc_elsr11_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr11 +{ + unsigned char BYTE; + struct st_elc_elsr11_bit BIT; +}; + +struct st_elc_elsr12_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr12 +{ + unsigned char BYTE; + struct st_elc_elsr12_bit BIT; +}; + +struct st_elc_elsr13_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr13 +{ + unsigned char BYTE; + struct st_elc_elsr13_bit BIT; +}; + +struct st_elc_elsr15_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr15 +{ + unsigned char BYTE; + struct st_elc_elsr15_bit BIT; +}; + +struct st_elc_elsr16_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr16 +{ + unsigned char BYTE; + struct st_elc_elsr16_bit BIT; +}; + +struct st_elc_elsr18_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr18 +{ + unsigned char BYTE; + struct st_elc_elsr18_bit BIT; +}; + +struct st_elc_elsr19_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr19 +{ + unsigned char BYTE; + struct st_elc_elsr19_bit BIT; +}; + +struct st_elc_elsr20_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr20 +{ + unsigned char BYTE; + struct st_elc_elsr20_bit BIT; +}; + +struct st_elc_elsr21_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr21 +{ + unsigned char BYTE; + struct st_elc_elsr21_bit BIT; +}; + +struct st_elc_elsr22_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr22 +{ + unsigned char BYTE; + struct st_elc_elsr22_bit BIT; +}; + +struct st_elc_elsr23_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr23 +{ + unsigned char BYTE; + struct st_elc_elsr23_bit BIT; +}; + +struct st_elc_elsr24_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr24 +{ + unsigned char BYTE; + struct st_elc_elsr24_bit BIT; +}; + +struct st_elc_elsr25_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr25 +{ + unsigned char BYTE; + struct st_elc_elsr25_bit BIT; +}; + +struct st_elc_elsr26_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr26 +{ + unsigned char BYTE; + struct st_elc_elsr26_bit BIT; +}; + +struct st_elc_elsr27_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr27 +{ + unsigned char BYTE; + struct st_elc_elsr27_bit BIT; +}; + +struct st_elc_elsr28_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr28 +{ + unsigned char BYTE; + struct st_elc_elsr28_bit BIT; +}; + +struct st_elc_elopa_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0MD : 2; + unsigned char : 4; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char : 4; + unsigned char MTU0MD : 2; +#endif +}; + +union un_elc_elopa +{ + unsigned char BYTE; + struct st_elc_elopa_bit BIT; +}; + +struct st_elc_elopb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif +}; + +union un_elc_elopb +{ + unsigned char BYTE; + struct st_elc_elopb_bit BIT; +}; + +struct st_elc_elopc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif +}; + +union un_elc_elopc +{ + unsigned char BYTE; + struct st_elc_elopc_bit BIT; +}; + +struct st_elc_elopd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR3MD : 2; +#else + unsigned char TMR3MD : 2; + unsigned char TMR2MD : 2; + unsigned char TMR1MD : 2; + unsigned char TMR0MD : 2; +#endif +}; + +union un_elc_elopd +{ + unsigned char BYTE; + struct st_elc_elopd_bit BIT; +}; + +struct st_elc_pgr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif +}; + +union un_elc_pgr1 +{ + unsigned char BYTE; + struct st_elc_pgr1_bit BIT; +}; + +struct st_elc_pgr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif +}; + +union un_elc_pgr2 +{ + unsigned char BYTE; + struct st_elc_pgr2_bit BIT; +}; + +struct st_elc_pgc1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif +}; + +union un_elc_pgc1 +{ + unsigned char BYTE; + struct st_elc_pgc1_bit BIT; +}; + +struct st_elc_pgc2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif +}; + +union un_elc_pgc2 +{ + unsigned char BYTE; + struct st_elc_pgc2_bit BIT; +}; + +struct st_elc_pdbf1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif +}; + +union un_elc_pdbf1 +{ + unsigned char BYTE; + struct st_elc_pdbf1_bit BIT; +}; + +struct st_elc_pdbf2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif +}; + +union un_elc_pdbf2 +{ + unsigned char BYTE; + struct st_elc_pdbf2_bit BIT; +}; + +struct st_elc_pel0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif +}; + +union un_elc_pel0 +{ + unsigned char BYTE; + struct st_elc_pel0_bit BIT; +}; + +struct st_elc_pel1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif +}; + +union un_elc_pel1 +{ + unsigned char BYTE; + struct st_elc_pel1_bit BIT; +}; + +struct st_elc_pel2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif +}; + +union un_elc_pel2 +{ + unsigned char BYTE; + struct st_elc_pel2_bit BIT; +}; + +struct un_elc_pel3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif +}; + +union un_elc_pel3 +{ + unsigned char BYTE; + struct un_elc_pel3_bit BIT; +}; + +struct st_elc_elsegr_bit +{ + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; +}; + +union un_elc_elsegr +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_elc_elsegr_bit BIT; +#endif +}; + +struct st_elc_elsr33_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr33 +{ + unsigned char BYTE; + struct st_elc_elsr33_bit BIT; +}; + +struct st_elc_elsr35_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr35 +{ + unsigned char BYTE; + struct st_elc_elsr35_bit BIT; +}; + +struct st_elc_elsr36_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr36 +{ + unsigned char BYTE; + struct st_elc_elsr36_bit BIT; +}; + +struct st_elc_elsr37_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr37 +{ + unsigned char BYTE; + struct st_elc_elsr37_bit BIT; +}; + +struct st_elc_elsr38_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr38 +{ + unsigned char BYTE; + struct st_elc_elsr38_bit BIT; +}; + +struct st_elc_elsr45_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif +}; + +union un_elc_elsr45 +{ + unsigned char BYTE; + struct st_elc_elsr45_bit BIT; +}; + +struct st_elc_elopf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPU0MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU3MD : 2; +#else + unsigned char TPU3MD : 2; + unsigned char TPU2MD : 2; + unsigned char TPU1MD : 2; + unsigned char TPU0MD : 2; +#endif +}; + +union un_elc_elopf +{ + unsigned char BYTE; + struct st_elc_elopf_bit BIT; +}; + +struct st_elc_eloph_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMTW0MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMTW0MD : 2; +#endif +}; + +union un_elc_eloph +{ + unsigned char BYTE; + struct st_elc_eloph_bit BIT; +}; + +struct st_etherc_ecmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PRM : 1; + unsigned long DM : 1; + unsigned long RTM : 1; + unsigned long ILB : 1; + unsigned long : 1; + unsigned long TE : 1; + unsigned long RE : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long PRCEF : 1; + unsigned long : 3; + unsigned long TXF : 1; + unsigned long RXF : 1; + unsigned long PFR : 1; + unsigned long ZPF : 1; + unsigned long TPC : 1; + unsigned long : 11; +#else + unsigned long : 11; + unsigned long TPC : 1; + unsigned long ZPF : 1; + unsigned long PFR : 1; + unsigned long RXF : 1; + unsigned long TXF : 1; + unsigned long : 3; + unsigned long PRCEF : 1; + unsigned long : 2; + unsigned long MPDE : 1; + unsigned long : 2; + unsigned long RE : 1; + unsigned long TE : 1; + unsigned long : 1; + unsigned long ILB : 1; + unsigned long RTM : 1; + unsigned long DM : 1; + unsigned long PRM : 1; +#endif +}; + +union un_etherc_ecmr +{ + unsigned long LONG; + struct st_etherc_ecmr_bit BIT; +}; + +struct st_etherc_rflr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFL : 12; + unsigned long : 20; +#else + unsigned long : 20; + unsigned long RFL : 12; +#endif +}; + +union un_etherc_rflr +{ + unsigned long LONG; + struct st_etherc_rflr_bit BIT; +}; + +struct st_etherc_ecsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICD : 1; + unsigned long MPD : 1; + unsigned long LCHNG : 1; + unsigned long : 1; + unsigned long PSRTO : 1; + unsigned long BFR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFR : 1; + unsigned long PSRTO : 1; + unsigned long : 1; + unsigned long LCHNG : 1; + unsigned long MPD : 1; + unsigned long ICD : 1; +#endif +}; + +union un_etherc_ecsr +{ + unsigned long LONG; + struct st_etherc_ecsr_bit BIT; +}; + +struct st_etherc_ecsipr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long ICDIP : 1; + unsigned long MPDIP : 1; + unsigned long LCHNGIP : 1; + unsigned long : 1; + unsigned long PSRTOIP : 1; + unsigned long BFSIPR : 1; + unsigned long : 26; +#else + unsigned long : 26; + unsigned long BFSIPR : 1; + unsigned long PSRTOIP : 1; + unsigned long : 1; + unsigned long LCHNGIP : 1; + unsigned long MPDIP : 1; + unsigned long ICDIP : 1; +#endif +}; + +union un_etherc_ecsipr +{ + unsigned long LONG; + struct st_etherc_ecsipr_bit BIT; +}; + +struct st_etherc_pir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MDC : 1; + unsigned long MMD : 1; + unsigned long MDO : 1; + unsigned long MDI : 1; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long MDI : 1; + unsigned long MDO : 1; + unsigned long MMD : 1; + unsigned long MDC : 1; +#endif +}; + +union un_etherc_pir +{ + unsigned long LONG; + struct st_etherc_pir_bit BIT; +}; + +struct st_etherc_psr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LMON : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long LMON : 1; +#endif +}; + +union un_etherc_psr +{ + unsigned long LONG; + struct st_etherc_psr_bit BIT; +}; + +struct st_etherc_rdmlr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RMD : 20; + unsigned long : 12; +#else + unsigned long : 12; + unsigned long RMD : 20; +#endif +}; + +union un_etherc_rdmlr +{ + unsigned long LONG; + struct st_etherc_rdmlr_bit BIT; +}; + +struct st_etherc_ipgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IPG : 5; + unsigned long : 27; +#else + unsigned long : 27; + unsigned long IPG : 5; +#endif +}; + +union un_etherc_ipgr +{ + unsigned long LONG; + struct st_etherc_ipgr_bit BIT; +}; + +struct st_etherc_apr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long AP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long AP : 16; +#endif +}; + +union un_etherc_apr +{ + unsigned long LONG; + struct st_etherc_apr_bit BIT; +}; + +struct st_etherc_mpr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MP : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MP : 16; +#endif +}; + +union un_etherc_mpr +{ + unsigned long LONG; + struct st_etherc_mpr_bit BIT; +}; + +struct st_etherc_rfcf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RPAUSE : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long RPAUSE : 8; +#endif +}; + +union un_etherc_rfcf +{ + unsigned long LONG; + struct st_etherc_rfcf_bit BIT; +}; + +struct st_etherc_tpauser_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TPAUSE : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long TPAUSE : 16; +#endif +}; + +union un_etherc_tpauser +{ + unsigned long LONG; + struct st_etherc_tpauser_bit BIT; +}; + +struct st_etherc_tpausecr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long TXP : 8; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long TXP : 8; +#endif +}; + +union un_etherc_tpausecr +{ + unsigned long LONG; + struct st_etherc_tpausecr_bit BIT; +}; + +struct st_etherc_bcfrr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long BCF : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long BCF : 16; +#endif +}; + +union un_etherc_bcfrr +{ + unsigned long LONG; + struct st_etherc_bcfrr_bit BIT; +}; + +struct st_etherc_malr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MA : 16; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long MA : 16; +#endif +}; + +union un_etherc_malr +{ + unsigned long LONG; + struct st_etherc_malr_bit BIT; +}; + +struct st_exdmac_edmast_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif +}; + +union un_exdmac_edmast +{ + unsigned char BYTE; + struct st_exdmac_edmast_bit BIT; +}; + +struct st_exdmac0_edmtmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif +}; + +union un_exdmac0_edmtmd +{ + unsigned short WORD; + struct st_exdmac0_edmtmd_bit BIT; +}; + +struct st_exdamc0_edmomd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif +}; + +union un_exdmac0_edmomd +{ + unsigned char BYTE; + struct st_exdamc0_edmomd_bit BIT; +}; + +struct st_exdmac0_edmint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif +}; + +union un_exdmac0_edmint +{ + unsigned char BYTE; + struct st_exdmac0_edmint_bit BIT; +}; + +struct st_exdmac0_edmamd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif +}; + +union un_exdmac0_edmamd +{ + unsigned long LONG; + struct st_exdmac0_edmamd_bit BIT; +}; + +struct st_exdmac0_edmcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif +}; + +union un_exdmac0_edmcnt +{ + unsigned char BYTE; + struct st_exdmac0_edmcnt_bit BIT; +}; + +struct st_exdmac0_edmreq_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif +}; + +union un_exdmac0_edmreq +{ + unsigned char BYTE; + struct st_exdmac0_edmreq_bit BIT; +}; + +struct st_exdmac0_edmsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif +}; + +union un_exdmac0_edmsts +{ + unsigned char BYTE; + struct st_exdmac0_edmsts_bit BIT; +}; + +struct st_exdmac0_edmrmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif +}; + +union un_exdmac0_edmrmd +{ + unsigned char BYTE; + struct st_exdmac0_edmrmd_bit BIT; +}; + +struct st_exdmac0_edmerf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif +}; + +union un_exdmac0_edmerf +{ + unsigned char BYTE; + struct st_exdmac0_edmerf_bit BIT; +}; + +struct st_exdmac0_edmprf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif +}; + +union un_exdmac0_edmprf +{ + unsigned char BYTE; + struct st_exdmac0_edmprf_bit BIT; +}; + +struct st_exdmac1_edmtmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif +}; + +union un_exdmac1_edmtmd +{ + unsigned short WORD; + struct st_exdmac1_edmtmd_bit BIT; +}; + +struct st_exdmac1_edmomd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DACKSEL : 1; + unsigned char DACKW : 1; + unsigned char DACKE : 1; + unsigned char DACKS : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char DACKS : 1; + unsigned char DACKE : 1; + unsigned char DACKW : 1; + unsigned char DACKSEL : 1; +#endif +}; + +union un_exdmac1_edmomd +{ + unsigned char BYTE; + struct st_exdmac1_edmomd_bit BIT; +}; + +struct st_exdmac1_edmint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif +}; + +union un_exdmac1_edmint +{ + unsigned char BYTE; + struct st_exdmac1_edmint_bit BIT; +}; + +struct st_exdmac1_edmamd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DARA : 5; + unsigned long : 1; + unsigned long DM : 2; + unsigned long SARA : 5; + unsigned long : 1; + unsigned long SM : 2; + unsigned long DIR : 1; + unsigned long AMS : 1; + unsigned long : 14; +#else + unsigned long : 14; + unsigned long AMS : 1; + unsigned long DIR : 1; + unsigned long SM : 2; + unsigned long : 1; + unsigned long SARA : 5; + unsigned long DM : 2; + unsigned long : 1; + unsigned long DARA : 5; +#endif +}; + +union un_exdmac1_edmamd +{ + unsigned long LONG; + struct st_exdmac1_edmamd_bit BIT; +}; + +struct st_exdmac1_edmcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif +}; + +union un_exdmac1_edmcnt +{ + unsigned char BYTE; + struct st_exdmac1_edmcnt_bit BIT; +}; + +struct st_exdmac1_edmreq_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif +}; + +union un_exdmac1_edmreq +{ + unsigned char BYTE; + struct st_exdmac1_edmreq_bit BIT; +}; + +struct st_exdmac1_edmsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif +}; + +union un_exdmac1_edmsts +{ + unsigned char BYTE; + struct st_exdmac1_edmsts_bit BIT; +}; + +struct st_exdmac1_edmrmd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DREQS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DREQS : 2; +#endif +}; + +union un_exdmac1_edmrmd +{ + unsigned char BYTE; + struct st_exdmac1_edmrmd_bit BIT; +}; + +struct st_exdmac1_edmerf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EREQ : 1; +#endif +}; + +union un_exdmac1_edmerf +{ + unsigned char BYTE; + struct st_exdmac1_edmerf_bit BIT; +}; + +struct st_exdmac1_edmprf_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PREQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PREQ : 1; +#endif +}; + +union un_exdmac1_edmprf +{ + unsigned char BYTE; + struct st_exdmac1_edmprf_bit BIT; +}; + +struct st_flash_romce_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROMCEN : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ROMCEN : 1; +#endif +}; + +union un_flash_romce +{ + unsigned short WORD; + struct st_flash_romce_bit BIT; +}; + +struct st_flash_romciv_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROMCIV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ROMCIV : 1; +#endif +}; + +union un_flash_romciv +{ + unsigned short WORD; + struct st_flash_romciv_bit BIT; +}; + +struct st_flash_fwepror_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLWE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char FLWE : 2; +#endif +}; + +union un_flash_fwepror +{ + unsigned char BYTE; + struct st_flash_fwepror_bit BIT; +}; + +struct st_flash_fastat_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAE : 1; + unsigned char CMDLK : 1; + unsigned char : 2; + unsigned char CFAE : 1; +#else + unsigned char CFAE : 1; + unsigned char : 2; + unsigned char CMDLK : 1; + unsigned char DFAE : 1; + unsigned char : 3; +#endif +}; + +union un_flash_fastat +{ + unsigned char BYTE; + struct st_flash_fastat_bit BIT; +}; + +struct st_flash_faeint_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char DFAEIE : 1; + unsigned char CMDLKIE : 1; + unsigned char : 2; + unsigned char CFAEIE : 1; +#else + unsigned char CFAEIE : 1; + unsigned char : 2; + unsigned char CMDLKIE : 1; + unsigned char DFAEIE : 1; + unsigned char : 3; +#endif +}; + +union un_flash_faeint +{ + unsigned char BYTE; + struct st_flash_faeint_bit BIT; +}; + +struct st_flash_frdyie_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRDYIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRDYIE : 1; +#endif +}; + +union un_flash_frdyie +{ + unsigned char BYTE; + struct st_flash_frdyie_bit BIT; +}; + +struct st_flash_fsaddr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FSADDR : 32; +#else + unsigned long FSADDR : 32; +#endif +}; + +union un_flash_fsaddr +{ + unsigned long LONG; + struct st_flash_fsaddr_bit BIT; +}; + +struct st_flash_feaddr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FEADDR : 32; +#else + unsigned long FEADDR : 32; +#endif +}; + +union un_flash_feaddr +{ + unsigned long LONG; + struct st_flash_feaddr_bit BIT; +}; + +struct st_flash_fstsatr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long FLWEERR : 1; + unsigned long : 1; + unsigned long PRGSPD : 1; + unsigned long ERSSPD : 1; + unsigned long DBFULL : 1; + unsigned long SUSRDY : 1; + unsigned long PRGERR : 1; + unsigned long ERSERR : 1; + unsigned long ILGLERR : 1; + unsigned long FRDY : 1; + unsigned long : 4; + unsigned long OTERR : 1; + unsigned long SECERR : 1; + unsigned long FESETERR : 1; + unsigned long ILGCOMERR : 1; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long ILGCOMERR : 1; + unsigned long FESETERR : 1; + unsigned long SECERR : 1; + unsigned long OTERR : 1; + unsigned long : 4; + unsigned long FRDY : 1; + unsigned long ILGLERR : 1; + unsigned long ERSERR : 1; + unsigned long PRGERR : 1; + unsigned long SUSRDY : 1; + unsigned long DBFULL : 1; + unsigned long ERSSPD : 1; + unsigned long PRGSPD : 1; + unsigned long : 1; + unsigned long FLWEERR : 1; + unsigned long : 6; +#endif +}; + +union un_flash_fstatr +{ + unsigned long LONG; + struct st_flash_fstsatr_bit BIT; +}; + +struct st_flash_fentryr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRYC : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRYC : 1; +#endif +}; + +union un_flash_fentryr +{ + unsigned short WORD; + struct st_flash_fentryr_bit BIT; +}; + +struct st_flash_fsunitr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SUINIT : 1; + unsigned short : 7; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 7; + unsigned short SUINIT : 1; +#endif +}; + +union un_flash_fsunitr +{ + unsigned short WORD; + struct st_flash_fsunitr_bit BIT; +}; + +struct st_flash_fcmdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCMDR : 8; + unsigned short CMDR : 8; +#else + unsigned short CMDR : 8; + unsigned short PCMDR : 8; +#endif +}; + +union un_flash_fcmdr +{ + unsigned short WORD; + struct st_flash_fcmdr_bit BIT; +}; + +struct st_flash_fbccnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCDIR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCDIR : 1; +#endif +}; + +union un_flash_fbccnt +{ + unsigned char BYTE; + struct st_flash_fbccnt_bit BIT; +}; + +struct st_flash_fbcstat_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCST : 1; +#endif +}; + +union un_flash_fbcstat +{ + unsigned char BYTE; + struct st_flash_fbcstat_bit BIT; +}; + +struct st_flash_fpsaddr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PSADR : 19; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long PSADR : 19; +#endif +}; + +union un_flash_fpsaddr +{ + unsigned long LONG; + struct st_flash_fpsaddr_bit BIT; +}; + +struct st_flash_fawmon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FAWS : 12; + unsigned long : 3; + unsigned long FSPR : 1; + unsigned long FAWE : 12; + unsigned long : 3; + unsigned long BTFLG : 1; +#else + unsigned long BTFLG : 1; + unsigned long : 3; + unsigned long FAWE : 12; + unsigned long FSPR : 1; + unsigned long : 3; + unsigned long FAWS : 12; +#endif +}; + +union un_flash_fawmon +{ + unsigned long LONG; + struct st_flash_fawmon_bit BIT; +}; + +struct st_flash_fcpsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ESUSPMD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short ESUSPMD : 1; +#endif +}; + +union un_flash_fcpsr +{ + unsigned short WORD; + struct st_flash_fcpsr_bit BIT; +}; + +struct st_flash_fpckar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PCKA : 8; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short PCKA : 8; +#endif +}; + +union un_flash_fpckar +{ + unsigned short WORD; + struct st_flash_fpckar_bit BIT; +}; + +struct st_flash_fsuacr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SAS : 2; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short SAS : 2; +#endif + }; + +union un_flash_fsuacr +{ + unsigned short WORD; + struct st_flash_fsuacr_bit BIT; +}; + +struct st_pdc_pccr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKE : 1; + unsigned long VPS : 1; + unsigned long HPS : 1; + unsigned long PRST : 1; + unsigned long DFIE : 1; + unsigned long FEIE : 1; + unsigned long OVIE : 1; + unsigned long UDRIE : 1; + unsigned long VERIE : 1; + unsigned long HERIE : 1; + unsigned long PCKOE : 1; + unsigned long PCKDIV : 3; + unsigned long EDS : 1; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long EDS : 1; + unsigned long PCKDIV : 3; + unsigned long PCKOE : 1; + unsigned long HERIE : 1; + unsigned long VERIE : 1; + unsigned long UDRIE : 1; + unsigned long OVIE : 1; + unsigned long FEIE : 1; + unsigned long DFIE : 1; + unsigned long PRST : 1; + unsigned long HPS : 1; + unsigned long VPS : 1; + unsigned long PCKE : 1; +#endif +}; + +union un_pdc_pccr0 +{ + unsigned long LONG; + struct st_pdc_pccr0_bit BIT; +}; + +struct st_pdc_pccr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCE : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long PCE : 1; +#endif +}; + +union un_pdc_pccr1 +{ + unsigned long LONG; + struct st_pdc_pccr1_bit BIT; +}; + +struct st_pdc_pcsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long FBSY : 1; + unsigned long FEMPF : 1; + unsigned long FEF : 1; + unsigned long OVRF : 1; + unsigned long UDRF : 1; + unsigned long VERF : 1; + unsigned long HERF : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long HERF : 1; + unsigned long VERF : 1; + unsigned long UDRF : 1; + unsigned long OVRF : 1; + unsigned long FEF : 1; + unsigned long FEMPF : 1; + unsigned long FBSY : 1; +#endif +}; + +union un_pdc_pcsr +{ + unsigned long LONG; + struct st_pdc_pcsr_bit BIT; +}; + +struct st_pdc_pcmonr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VSYNC : 1; + unsigned long HSYNC : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long HSYNC : 1; + unsigned long VSYNC : 1; +#endif +}; + +union un_pdc_pcmonr +{ + unsigned long LONG; + struct st_pdc_pcmonr_bit BIT; +}; + +union un_pdc_pcdr +{ + unsigned long LONG; +}; + +struct st_pdc_vcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long VST : 12; + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long VSZ : 12; + unsigned long : 4; + unsigned long VST : 12; +#endif +}; + +union un_pdc_vcr +{ + unsigned long LONG; + struct st_pdc_vcr_bit BIT; +}; + +struct st_pdc_hcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long HST : 12; + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long HSZ : 12; + unsigned long : 4; + unsigned long HST : 12; +#endif +}; + +union un_pdc_hcr +{ + unsigned long LONG; + struct st_pdc_hcr_bit BIT; +}; + +struct st_poe_icsr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short : 6; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short : 6; + unsigned short POE0M : 2; +#endif +}; + +union un_poe_icsr1 +{ + unsigned short WORD; + struct st_poe_icsr1_bit BIT; +}; + +struct st_poe_ocsr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif +}; + +union un_poe_ocsr1 +{ + unsigned short WORD; + struct st_poe_ocsr1_bit BIT; +}; + +struct st_poe_icsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE4M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE4F : 1; + unsigned short : 3; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE4M : 2; +#endif +}; + +union un_poe_icsr2 +{ + unsigned short WORD; + struct st_poe_icsr2_bit BIT; +}; + +struct st_poe_ocsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE2 : 1; + unsigned short OCE2 : 1; + unsigned short : 5; + unsigned short OSF2 : 1; +#else + unsigned short OSF2 : 1; + unsigned short : 5; + unsigned short OCE2 : 1; + unsigned short OIE2 : 1; + unsigned short : 8; +#endif +}; + +union un_poe_ocsr2 +{ + unsigned short WORD; + struct st_poe_ocsr2_bit BIT; +}; + +struct st_poe_icsr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE3 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE3 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif +}; + +union un_poe_icsr3 +{ + unsigned short WORD; + struct st_poe_icsr3_bit BIT; +}; + +struct st_poe_spoer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTUCH34HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH0HIZ : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char MTUCH0HIZ : 1; + unsigned char MTUCH67HIZ : 1; + unsigned char MTUCH34HIZ : 1; +#endif +}; + +union un_poe_spoer +{ + unsigned char BYTE; + struct st_poe_spoer_bit BIT; +}; + +struct st_poe_poecr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU0AZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0DZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MTU0DZE : 1; + unsigned char MTU0CZE : 1; + unsigned char MTU0BZE : 1; + unsigned char MTU0AZE : 1; +#endif +}; + +union un_poe_poecr1 +{ + unsigned char BYTE; + struct st_poe_poecr1_bit BIT; +}; + +struct st_poe_poecr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MTU7BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU6BDZE : 1; + unsigned short : 5; + unsigned short MTU4BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU3BDZE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short MTU3BDZE : 1; + unsigned short MTU4ACZE : 1; + unsigned short MTU4BDZE : 1; + unsigned short : 5; + unsigned short MTU6BDZE : 1; + unsigned short MTU7ACZE : 1; + unsigned short MTU7BDZE : 1; +#endif +}; + +union un_poe_poecr2 +{ + unsigned short WORD; + struct st_poe_poecr2_bit BIT; +}; + +struct st_poe_poecr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 2; + unsigned short IC2ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC5ADDMT34ZE : 1; + unsigned short : 3; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC5ADDMT67ZE : 1; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short IC5ADDMT67ZE : 1; + unsigned short IC4ADDMT67ZE : 1; + unsigned short IC3ADDMT67ZE : 1; + unsigned short : 1; + unsigned short IC1ADDMT67ZE : 1; + unsigned short : 3; + unsigned short IC5ADDMT34ZE : 1; + unsigned short IC4ADDMT34ZE : 1; + unsigned short IC3ADDMT34ZE : 1; + unsigned short IC2ADDMT34ZE : 1; + unsigned short : 2; +#endif +}; + +union un_poe_poecr4 +{ + unsigned short WORD; + struct st_poe_poecr4_bit BIT; +}; + +struct st_poe_poecr5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short IC5ADDMT0ZE : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short IC5ADDMT0ZE : 1; + unsigned short IC4ADDMT0ZE : 1; + unsigned short : 1; + unsigned short IC2ADDMT0ZE : 1; + unsigned short IC1ADDMT0ZE : 1; + unsigned short : 1; +#endif +}; + +union un_poe_poecr5 +{ + unsigned short WORD; + struct st_poe_poecr5_bit BIT; +}; + +struct st_poe_icsr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE10M : 2; + unsigned short : 6; + unsigned short PIE4 : 1; + unsigned short POE10E : 1; + unsigned short : 2; + unsigned short POE10F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE10F : 1; + unsigned short : 2; + unsigned short POE10E : 1; + unsigned short PIE4 : 1; + unsigned short : 6; + unsigned short POE10M : 2; +#endif +}; + +union un_poe_icsr4 +{ + unsigned short WORD; + struct st_poe_icsr4_bit BIT; +}; + +struct st_poe_icsr5_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE11M : 2; + unsigned short : 6; + unsigned short PIE5 : 1; + unsigned short POE11E : 1; + unsigned short : 2; + unsigned short POE11F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE11F : 1; + unsigned short : 2; + unsigned short POE11E : 1; + unsigned short PIE5 : 1; + unsigned short : 6; + unsigned short POE11M : 2; +#endif +}; + +union un_poe_icsr5 +{ + unsigned short WORD; + struct st_poe_icsr5_bit BIT; +}; + +struct st_poe_alr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short OLSG0A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG2B : 1; + unsigned short : 1; + unsigned short OLSEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short OLSEN : 1; + unsigned short : 1; + unsigned short OLSG2B : 1; + unsigned short OLSG2A : 1; + unsigned short OLSG1B : 1; + unsigned short OLSG1A : 1; + unsigned short OLSG0B : 1; + unsigned short OLSG0A : 1; +#endif +}; + +union un_poe_alr1 +{ + unsigned short WORD; + struct st_poe_alr1_bit BIT; +}; + +struct st_poe_icsr6_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 9; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 9; +#endif +}; + +union un_poe_icsr6 +{ + unsigned short WORD; + struct st_poe_icsr6_bit BIT; +}; + +struct st_poe_m0selr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0ASEL : 4; + unsigned char M0BSEL : 4; +#else + unsigned char M0BSEL : 4; + unsigned char M0ASEL : 4; +#endif +}; + +union un_poe_m0selr1 +{ + unsigned char BYTE; + struct st_poe_m0selr1_bit BIT; +}; + +struct st_poe_m0selr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M0CSEL : 4; + unsigned char M0DSEL : 4; +#else + unsigned char M0DSEL : 4; + unsigned char M0CSEL : 4; +#endif +}; + +union un_poe_m0selr2 +{ + unsigned char BYTE; + struct st_poe_m0selr2_bit BIT; +}; + +struct st_poe_m3selr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M3BSEL : 4; + unsigned char M3DSEL : 4; +#else + unsigned char M3DSEL : 4; + unsigned char M3BSEL : 4; +#endif +}; + +union un_poe_m3selr +{ + unsigned char BYTE; + struct st_poe_m3selr_bit BIT; +}; + +struct st_poe_m4selr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4ASEL : 4; + unsigned char M4CSEL : 4; +#else + unsigned char M4CSEL : 4; + unsigned char M4ASEL : 4; +#endif +}; + +union un_poe_m4selr1 +{ + unsigned char BYTE; + struct st_poe_m4selr1_bit BIT; +}; + +struct un_poe_m4selr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M4BSEL : 4; + unsigned char M4DSEL : 4; +#else + unsigned char M4DSEL : 4; + unsigned char M4BSEL : 4; +#endif +}; + +union un_poe_m4selr2 +{ + unsigned char BYTE; + struct un_poe_m4selr2_bit BIT; +}; + +struct st_poe_m6selr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char M6BSEL : 4; + unsigned char M6DSEL : 4; +#else + unsigned char M6DSEL : 4; + unsigned char M6BSEL : 4; +#endif +}; + +union un_poe_m6selr +{ + unsigned char BYTE; + struct st_poe_m6selr_bit BIT; +}; + +struct st_portd_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_pdr +{ + unsigned char BYTE; + struct st_portd_pdr_bit BIT; +}; + +struct st_portd_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_podr +{ + unsigned char BYTE; + struct st_portd_podr_bit BIT; +}; + +struct st_portd_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_pidr +{ + unsigned char BYTE; + struct st_portd_pidr_bit BIT; +}; + +struct st_portd_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_pmr +{ + unsigned char BYTE; + struct st_portd_pmr_bit BIT; +}; + +struct st_portd_ord0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_ord0 +{ + unsigned char BYTE; + struct st_portd_ord0_bit BIT; +}; + +struct st_portd_ord1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_ord1 +{ + unsigned char BYTE; + struct st_portd_ord1_bit BIT; +}; + +struct st_portd_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_pcr +{ + unsigned char BYTE; + struct st_portd_pcr_bit BIT; +}; + +struct st_portd_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_dscr +{ + unsigned char BYTE; + struct st_portd_dscr_bit BIT; +}; + +struct st_portd_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif +}; + +union un_portd_dscr2 +{ + unsigned char BYTE; + struct st_portd_dscr2_bit BIT; +}; + +struct st_ppg0_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif +}; + +union un_ppg0_pcr +{ + unsigned char BYTE; + struct st_ppg0_pcr_bit BIT; +}; + +struct st_ppg0_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif +}; + +union un_ppg0_pmr +{ + unsigned char BYTE; + struct st_ppg0_pmr_bit BIT; +}; + +struct st_ppg0_nderh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER8 : 1; + unsigned char NDER9 : 1; + unsigned char NDER10 : 1; + unsigned char NDER11 : 1; + unsigned char NDER12 : 1; + unsigned char NDER13 : 1; + unsigned char NDER14 : 1; + unsigned char NDER15 : 1; +#else + unsigned char NDER15 : 1; + unsigned char NDER14 : 1; + unsigned char NDER13 : 1; + unsigned char NDER12 : 1; + unsigned char NDER11 : 1; + unsigned char NDER10 : 1; + unsigned char NDER9 : 1; + unsigned char NDER8 : 1; +#endif +}; + +union un_ppg0_nderh +{ + unsigned char BYTE; + struct st_ppg0_nderh_bit BIT; +}; + +struct st_ppg0_nderl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER0 : 1; + unsigned char NDER1 : 1; + unsigned char NDER2 : 1; + unsigned char NDER3 : 1; + unsigned char NDER4 : 1; + unsigned char NDER5 : 1; + unsigned char NDER6 : 1; + unsigned char NDER7 : 1; +#else + unsigned char NDER7 : 1; + unsigned char NDER6 : 1; + unsigned char NDER5 : 1; + unsigned char NDER4 : 1; + unsigned char NDER3 : 1; + unsigned char NDER2 : 1; + unsigned char NDER1 : 1; + unsigned char NDER0 : 1; +#endif +}; + +union un_ppg0_nderl +{ + unsigned char BYTE; + struct st_ppg0_nderl_bit BIT; +}; + +struct st_ppg0_podrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD8 : 1; + unsigned char POD9 : 1; + unsigned char POD10 : 1; + unsigned char POD11 : 1; + unsigned char POD12 : 1; + unsigned char POD13 : 1; + unsigned char POD14 : 1; + unsigned char POD15 : 1; +#else + unsigned char POD15 : 1; + unsigned char POD14 : 1; + unsigned char POD13 : 1; + unsigned char POD12 : 1; + unsigned char POD11 : 1; + unsigned char POD10 : 1; + unsigned char POD9 : 1; + unsigned char POD8 : 1; +#endif +}; + +union un_ppg0_podrh +{ + unsigned char BYTE; + struct st_ppg0_podrh_bit BIT; +}; + +struct st_ppg0_podrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD0 : 1; + unsigned char POD1 : 1; + unsigned char POD2 : 1; + unsigned char POD3 : 1; + unsigned char POD4 : 1; + unsigned char POD5 : 1; + unsigned char POD6 : 1; + unsigned char POD7 : 1; +#else + unsigned char POD7 : 1; + unsigned char POD6 : 1; + unsigned char POD5 : 1; + unsigned char POD4 : 1; + unsigned char POD3 : 1; + unsigned char POD2 : 1; + unsigned char POD1 : 1; + unsigned char POD0 : 1; +#endif +}; + +union un_ppg0_podrl +{ + unsigned char BYTE; + struct st_ppg0_podrl_bit BIT; +}; + +struct st_ppg0_ndrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char NDR12 : 1; + unsigned char NDR13 : 1; + unsigned char NDR14 : 1; + unsigned char NDR15 : 1; +#else + unsigned char NDR15 : 1; + unsigned char NDR14 : 1; + unsigned char NDR13 : 1; + unsigned char NDR12 : 1; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif +}; + +union un_ppg0_ndrh +{ + unsigned char BYTE; + struct st_ppg0_ndrh_bit BIT; +}; + +struct st_ppg0_ndrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char NDR4 : 1; + unsigned char NDR5 : 1; + unsigned char NDR6 : 1; + unsigned char NDR7 : 1; +#else + unsigned char NDR7 : 1; + unsigned char NDR6 : 1; + unsigned char NDR5 : 1; + unsigned char NDR4 : 1; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif +}; + +union un_ppg0_ndrl +{ + unsigned char BYTE; + struct st_ppg0_ndrl_bit BIT; +}; + +struct st_ppg0_ndrh2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR8 : 1; + unsigned char NDR9 : 1; + unsigned char NDR10 : 1; + unsigned char NDR11 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR11 : 1; + unsigned char NDR10 : 1; + unsigned char NDR9 : 1; + unsigned char NDR8 : 1; +#endif +}; + +union un_ppg0_ndrh2 +{ + unsigned char BYTE; + struct st_ppg0_ndrh2_bit BIT; +}; + +struct st_ppg0_ndrl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR0 : 1; + unsigned char NDR1 : 1; + unsigned char NDR2 : 1; + unsigned char NDR3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR3 : 1; + unsigned char NDR2 : 1; + unsigned char NDR1 : 1; + unsigned char NDR0 : 1; +#endif +}; + +union un_ppg0_ndrl2 +{ + unsigned char BYTE; + struct st_ppg0_ndrl2_bit BIT; +}; + +struct st_ppg1_ptrslr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PTRSL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PTRSL : 1; +#endif +}; + +union un_ppg1_ptrslr +{ + unsigned char BYTE; + struct st_ppg1_ptrslr_bit BIT; +}; + +struct st_ppg1_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0CMS : 2; + unsigned char G1CMS : 2; + unsigned char G2CMS : 2; + unsigned char G3CMS : 2; +#else + unsigned char G3CMS : 2; + unsigned char G2CMS : 2; + unsigned char G1CMS : 2; + unsigned char G0CMS : 2; +#endif +}; + +union un_ppg1_pcr +{ + unsigned char BYTE; + struct st_ppg1_pcr_bit BIT; +}; + +struct st_ppg1_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char G0NOV : 1; + unsigned char G1NOV : 1; + unsigned char G2NOV : 1; + unsigned char G3NOV : 1; + unsigned char G0INV : 1; + unsigned char G1INV : 1; + unsigned char G2INV : 1; + unsigned char G3INV : 1; +#else + unsigned char G3INV : 1; + unsigned char G2INV : 1; + unsigned char G1INV : 1; + unsigned char G0INV : 1; + unsigned char G3NOV : 1; + unsigned char G2NOV : 1; + unsigned char G1NOV : 1; + unsigned char G0NOV : 1; +#endif +}; + +union un_ppg1_pmr +{ + unsigned char BYTE; + struct st_ppg1_pmr_bit BIT; +}; + +struct st_ppg1_nderh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER24 : 1; + unsigned char NDER25 : 1; + unsigned char NDER26 : 1; + unsigned char NDER27 : 1; + unsigned char NDER28 : 1; + unsigned char NDER29 : 1; + unsigned char NDER30 : 1; + unsigned char NDER31 : 1; +#else + unsigned char NDER31 : 1; + unsigned char NDER30 : 1; + unsigned char NDER29 : 1; + unsigned char NDER28 : 1; + unsigned char NDER27 : 1; + unsigned char NDER26 : 1; + unsigned char NDER25 : 1; + unsigned char NDER24 : 1; +#endif +}; + +union un_ppg1_nderh +{ + unsigned char BYTE; + struct st_ppg1_nderh_bit BIT; +}; + +struct st_ppg1_nerl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDER16 : 1; + unsigned char NDER17 : 1; + unsigned char NDER18 : 1; + unsigned char NDER19 : 1; + unsigned char NDER20 : 1; + unsigned char NDER21 : 1; + unsigned char NDER22 : 1; + unsigned char NDER23 : 1; +#else + unsigned char NDER23 : 1; + unsigned char NDER22 : 1; + unsigned char NDER21 : 1; + unsigned char NDER20 : 1; + unsigned char NDER19 : 1; + unsigned char NDER18 : 1; + unsigned char NDER17 : 1; + unsigned char NDER16 : 1; +#endif +}; + +union un_ppg1_nderl +{ + unsigned char BYTE; + struct st_ppg1_nerl_bit BIT; +}; + +struct st_ppg1_podrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD24 : 1; + unsigned char POD25 : 1; + unsigned char POD26 : 1; + unsigned char POD27 : 1; + unsigned char POD28 : 1; + unsigned char POD29 : 1; + unsigned char POD30 : 1; + unsigned char POD31 : 1; +#else + unsigned char POD31 : 1; + unsigned char POD30 : 1; + unsigned char POD29 : 1; + unsigned char POD28 : 1; + unsigned char POD27 : 1; + unsigned char POD26 : 1; + unsigned char POD25 : 1; + unsigned char POD24 : 1; +#endif +}; + +union un_ppg1_podrh +{ + unsigned char BYTE; + struct st_ppg1_podrh_bit BIT; +}; + +struct st_ppg1_podrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char POD16 : 1; + unsigned char POD17 : 1; + unsigned char POD18 : 1; + unsigned char POD19 : 1; + unsigned char POD20 : 1; + unsigned char POD21 : 1; + unsigned char POD22 : 1; + unsigned char POD23 : 1; +#else + unsigned char POD23 : 1; + unsigned char POD22 : 1; + unsigned char POD21 : 1; + unsigned char POD20 : 1; + unsigned char POD19 : 1; + unsigned char POD18 : 1; + unsigned char POD17 : 1; + unsigned char POD16 : 1; +#endif +}; + +union un_ppg1_podrl +{ + unsigned char BYTE; + struct st_ppg1_podrl_bit BIT; +}; + +struct st_ppg1_ndrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char NDR28 : 1; + unsigned char NDR29 : 1; + unsigned char NDR30 : 1; + unsigned char NDR31 : 1; +#else + unsigned char NDR31 : 1; + unsigned char NDR30 : 1; + unsigned char NDR29 : 1; + unsigned char NDR28 : 1; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif +}; + +union un_ppg1_ndrh +{ + unsigned char BYTE; + struct st_ppg1_ndrh_bit BIT; +}; + +struct st_ppg1_ndrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char NDR20 : 1; + unsigned char NDR21 : 1; + unsigned char NDR22 : 1; + unsigned char NDR23 : 1; +#else + unsigned char NDR23 : 1; + unsigned char NDR22 : 1; + unsigned char NDR21 : 1; + unsigned char NDR20 : 1; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif +}; + +union un_ppg1_ndrl +{ + unsigned char BYTE; + struct st_ppg1_ndrl_bit BIT; +}; + +struct st_ppg1_ndrh2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR24 : 1; + unsigned char NDR25 : 1; + unsigned char NDR26 : 1; + unsigned char NDR27 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR27 : 1; + unsigned char NDR26 : 1; + unsigned char NDR25 : 1; + unsigned char NDR24 : 1; +#endif +}; + +union un_ppg1_ndrh2 +{ + unsigned char BYTE; + struct st_ppg1_ndrh2_bit BIT; +}; + +struct st_ppg1_ndrl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NDR16 : 1; + unsigned char NDR17 : 1; + unsigned char NDR18 : 1; + unsigned char NDR19 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NDR19 : 1; + unsigned char NDR18 : 1; + unsigned char NDR17 : 1; + unsigned char NDR16 : 1; +#endif +}; + +union un_ppg1_ndrl2 +{ + unsigned char BYTE; + struct st_ppg1_ndrl2_bit BIT; +}; + +struct st_qspi_spcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char : 1; + unsigned char MSTR : 1; + unsigned char : 1; + unsigned char SPSSLIE : 1; + unsigned char : 1; +#endif +}; + +union un_qspi_spcr +{ + unsigned char BYTE; + struct st_qspi_spcr_bit BIT; +}; + +struct st_qspi_sslp_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSLP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SSLP : 1; +#endif +}; + +union un_qspi_sslp +{ + unsigned char BYTE; + struct st_qspi_sslp_bit BIT; +}; + +struct st_qspi_sppcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char IO2FV : 1; + unsigned char IO3FV : 1; + unsigned char : 1; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 1; + unsigned char IO3FV : 1; + unsigned char IO2FV : 1; + unsigned char SPLP : 1; +#endif +}; + +union un_qspi_sppcr +{ + unsigned char BYTE; + struct st_qspi_sppcr_bit BIT; +}; + +struct st_qspi_spsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char SPSSLF : 1; + unsigned char SPTEF : 1; + unsigned char TREND : 1; + unsigned char SPRFF : 1; +#else + unsigned char SPRFF : 1; + unsigned char TREND : 1; + unsigned char SPTEF : 1; + unsigned char SPSSLF : 1; + unsigned char : 4; +#endif +}; + +union un_qspi_spsr +{ + unsigned char BYTE; + struct st_qspi_spsr_bit BIT; +}; + +struct st_qspi_spdr_word +{ + unsigned short H; +}; + +struct st_qspi_spsr_byte +{ + unsigned char HH; +}; + +union un_qspi_spdr +{ + unsigned long LONG; + struct st_qspi_spdr_word WOED; + struct st_qspi_spsr_byte BYTE; +}; + +struct st_qspi_spscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSC : 2; +#endif +}; + +union un_qspi_spscr +{ + unsigned char BYTE; + struct st_qspi_spscr_bit BIT; +}; + +struct st_qspi_spssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSS : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SPSS : 2; +#endif +}; + +union un_qspi_spssr +{ + unsigned char BYTE; + struct st_qspi_spssr_bit BIT; +}; + +struct st_qspi_spbr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPBR0 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR7 : 1; +#else + unsigned char SPBR7 : 1; + unsigned char SPBR6 : 1; + unsigned char SPBR5 : 1; + unsigned char SPBR4 : 1; + unsigned char SPBR3 : 1; + unsigned char SPBR2 : 1; + unsigned char SPBR1 : 1; + unsigned char SPBR0 : 1; +#endif +}; + +union un_qspi_spbr +{ + unsigned char BYTE; + struct st_qspi_spbr_bit BIT; +}; + +struct st_qspi_spdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TXDMY : 1; +#else + unsigned char TXDMY : 1; + unsigned char : 7; +#endif +}; + +union un_qspi_spdcr +{ + unsigned char BYTE; + struct st_qspi_spdcr_bit BIT; +}; + +struct st_qspi_spckd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif +}; + +union un_qspi_spckd +{ + unsigned char BYTE; + struct st_qspi_spckd_bit BIT; +}; + +struct st_qspi_sslnd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif +}; + +union un_qspi_sslnd +{ + unsigned char BYTE; + struct st_qspi_sslnd_bit BIT; +}; + +struct st_qspi_spnd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif +}; + +union un_qspi_spnd +{ + unsigned char BYTE; + struct st_qspi_spnd_bit BIT; +}; + +struct st_qspi_spcmd0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_qspi_spcmd0 +{ + unsigned short WORD; + struct st_qspi_spcmd0_bit BIT; +}; + +struct st_qspi_spcmd1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_qspi_spcmd1 +{ + unsigned short WORD; + struct st_qspi_spcmd1_bit BIT; +}; + +struct st_qspi_spcmd2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_qspi_spcmd2 +{ + unsigned short WORD; + struct st_qspi_spcmd2_bit BIT; +}; + +struct st_qspi_spcmd3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SPRW : 1; + unsigned short SPIMOD : 2; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SPIMOD : 2; + unsigned short SPRW : 1; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif +}; + +union un_qspi_spcmd3 +{ + unsigned short WORD; + struct st_qspi_spcmd3_bit BIT; +}; + +struct st_qspi_spbfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXTRG : 3; + unsigned char TXTRGEX : 1; + unsigned char TXTRG : 2; + unsigned char RXRST : 1; + unsigned char TXRST : 1; +#else + unsigned char TXRST : 1; + unsigned char RXRST : 1; + unsigned char TXTRG : 2; + unsigned char TXTRGEX : 1; + unsigned char RXTRG : 3; +#endif +}; + +union un_qspi_spbfcr +{ + unsigned char BYTE; + struct st_qspi_spbfcr_bit BIT; +}; + +struct st_qspi_spbdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RXBC : 6; + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TXBC : 6; + unsigned short : 2; + unsigned short RXBC : 6; +#endif +}; + +union un_qspi_spbdcr +{ + unsigned short WORD; + struct st_qspi_spbdcr_bit BIT; +}; + +struct st_ram_rammode_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RAMMODE : 2; +#endif +}; + +union un_ram_rammode +{ + unsigned char BYTE; + struct st_ram_rammode_bit BIT; +}; + +struct st_ram_ramsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RAMERR : 1; +#endif +}; + +union un_ram_ramsts +{ + unsigned char BYTE; + struct st_ram_ramsts_bit BIT; +}; + +struct st_ram_ramprcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RAMPRCR : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char RAMPRCR : 1; +#endif +}; + +union un_ram_ramprcr +{ + unsigned char BYTE; + struct st_ram_ramprcr_bit BIT; +}; + +struct st_ram_ramecad_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif +}; + +union un_ram_ramecad +{ + unsigned long LONG; + struct st_ram_ramecad_bit BIT; +}; + +struct st_ram_exrammode_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMMODE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char EXRAMMODE : 2; +#endif +}; + +union un_ram_exrammode +{ + unsigned char BYTE; + struct st_ram_exrammode_bit BIT; +}; + +struct srt_ram_exramsts_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXRAMERR : 1; +#endif +}; + +union un_ram_exramsts +{ + unsigned char BYTE; + struct srt_ram_exramsts_bit BIT; +}; + +struct st_ram_exramprcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXRAMPRCR1 : 1; + unsigned char KW : 7; +#else + unsigned char KW : 7; + unsigned char EXRAMPRCR2 : 1; +#endif +}; + +union un_ram_exramprcr +{ + unsigned char BYTE; + struct st_ram_exramprcr_bit BIT; +}; + +struct st_ram_exramecad_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 3; + unsigned long READ : 16; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long READ : 16; + unsigned long : 3; +#endif +}; + +union un_ram_exramecad +{ + unsigned long LONG; + struct st_ram_exramecad_bit BIT; +}; + +struct st_s12ad_adcsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif +}; + +union un_s12ad_adcsr +{ + unsigned short WORD; + struct st_s12ad_adcsr_bit BIT; +}; + +struct st_s12ad_adansa0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif +}; + +union un_s12ad_adansa0 +{ + unsigned short WORD; + struct st_s12ad_adansa0_bit BIT; +}; + +struct st_s12ad_adads0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif +}; + +union un_s12ad_adads0 +{ + unsigned short WORD; + struct st_s12ad_adads0_bit BIT; +}; + +struct st_s12ad_adadc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif +}; + +union un_s12ad_adadc +{ + unsigned char BYTE; + struct st_s12ad_adadc_bit BIT; +}; + +struct st_s12ad_adcer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif +}; + +union un_s12ad_adcer +{ + unsigned short WORD; + struct st_s12ad_adcer_bit BIT; +}; + +struct st_s12ad_adstrgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif +}; + +union un_s12ad_adstrgr +{ + unsigned short WORD; + struct st_s12ad_adstrgr_bit BIT; +}; + +struct st_s12ad_adansb0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif +}; + +union un_s12ad_adansb0 +{ + unsigned short WORD; + struct st_s12ad_adansb0_bit BIT; +}; + +union un_s12ad_addbldr +{ + unsigned short WORD; +}; + +struct st_s12ad_adrd_bit_right +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif +}; + +struct st_s12ad_adrd_bit_left +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif +}; + +union un_s12ad_adrd_bit +{ + struct st_s12ad_adrd_bit_right RIGHT; + struct st_s12ad_adrd_bit_left LEFT; +}; + +union un_s12ad_adrd +{ + unsigned short WORD; +}; + +struct st_s12ad_adsampr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRO : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PRO : 2; +#endif +}; + +union un_s12ad_adsampr +{ + unsigned char BYTE; + struct st_s12ad_adsampr_bit BIT; +}; + +struct st_s12ad_adshcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SSTSH : 8; + unsigned short SHANS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SHANS : 3; + unsigned short SSTSH : 8; +#endif +}; + +union un_s12ad_adshcr +{ + unsigned short WORD; + struct st_s12ad_adshcr_bit BIT; +}; + +struct st_s12ad_adsam_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short SAM : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short SAM : 1; + unsigned short : 5; +#endif +}; + +union un_s12ad_adsam +{ + unsigned short WORD; + struct st_s12ad_adsam_bit BIT; +}; + +struct st_s12ad_addiscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif +}; + +union un_s12ad_addiscr +{ + unsigned char BYTE; + struct st_s12ad_addiscr_bit BIT; +}; + +struct st_s12ad_adshmsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHMD : 1; +#endif +}; + +union un_s12ad_adshmsr +{ + unsigned char BYTE; + struct st_s12ad_adshmsr_bit BIT; +}; + +struct st_s12ad_adgspcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif +}; + +union un_s12ad_adgspcr +{ + unsigned short WORD; + struct st_s12ad_adgspcr_bit BIT; +}; + +struct st_s12ad_adwinmon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif +}; + +union un_s12ad_adwinmon +{ + unsigned char BYTE; + struct st_s12ad_adwinmon_bit BIT; +}; + +struct st_s12ad_adcmpcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif +}; + +union un_s12ad_adcmpcr +{ + unsigned short WORD; + struct st_s12ad_adcmpcr_bit BIT; +}; + +struct st_s12ad_adcmpansr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif +}; + +union un_s12ad_adcmpansr0 +{ + unsigned short WORD; + struct st_s12ad_adcmpansr0_bit BIT; +}; + +struct st_s12ad_adcmplr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif +}; + +union un_s12ad_adcmplr0 +{ + unsigned short WORD; + struct st_s12ad_adcmplr0_bit BIT; +}; + +struct st_s12ad_adcmpsr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif +}; + +union un_s12ad_adcmpsr0 +{ + unsigned short WORD; + struct st_s12ad_adcmpsr0_bit BIT; +}; + +struct st_s12ad_adcmpbnsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif +}; + +union un_s12ad_adcmpbnsr +{ + unsigned char BYTE; + struct st_s12ad_adcmpbnsr_bit BIT; +}; + +struct st_s12ad_adcmpbsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif +}; + +union un_s12ad_adcmpbsr +{ + unsigned char BYTE; + struct st_s12ad_adcmpbsr_bit BIT; +}; + +struct st_s12ad_adansc0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSC007 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif +}; + +union un_s12ad_adansc0 +{ + unsigned short WORD; + struct st_s12ad_adansc0_bit BIT; +}; + +struct st_s12ad_adgctrgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif +}; + +union un_s12ad_adgctrgr +{ + unsigned char BYTE; + struct st_s12ad_adgctrgr_bit BIT; +}; + +struct st_s12ad1_adcsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short : 2; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 2; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif +}; + +union un_s12ad1_adcsr +{ + unsigned short WORD; + struct st_s12ad1_adcsr_bit BIT; +}; + +struct st_s12ad1_adansa0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA011 : 1; + unsigned short ANSA012 : 1; + unsigned short ANSA013 : 1; + unsigned short ANSA014 : 1; + unsigned short ANSA015 : 1; +#else + unsigned short ANSA015 : 1; + unsigned short ANSA014 : 1; + unsigned short ANSA013 : 1; + unsigned short ANSA012 : 1; + unsigned short ANSA011 : 1; + unsigned short ANSA010 : 1; + unsigned short ANSA009 : 1; + unsigned short ANSA008 : 1; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif +}; + +union un_s12ad1_adansa0 +{ + unsigned short WORD; + struct st_s12ad1_adansa0_bit BIT; +}; + +struct st_s12ad1_adansa1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif +}; + +union un_s12ad1_adansa1 +{ + unsigned short WORD; + struct st_s12ad1_adansa1_bit BIT; +}; + +struct st_s12ad1_adads0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short ADS008 : 1; + unsigned short ADS009 : 1; + unsigned short ADS010 : 1; + unsigned short ADS011 : 1; + unsigned short ADS012 : 1; + unsigned short ADS013 : 1; + unsigned short ADS014 : 1; + unsigned short ADS015 : 1; +#else + unsigned short ADS015 : 1; + unsigned short ADS014 : 1; + unsigned short ADS013 : 1; + unsigned short ADS012 : 1; + unsigned short ADS011 : 1; + unsigned short ADS010 : 1; + unsigned short ADS009 : 1; + unsigned short ADS008 : 1; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif +}; + +union un_s12ad1_adads0 +{ + unsigned short WORD; + struct st_s12ad1_adads0_bit BIT; +}; + +struct st_s12ad1_adads1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif +}; + +union un_s12ad1_adads1 +{ + unsigned short WORD; + struct st_s12ad1_adads1_bit BIT; +}; + +struct st_s12ad1_adadc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif +}; + +union un_s12ad1_adadc +{ + unsigned char BYTE; + struct st_s12ad1_adadc_bit BIT; +}; + +struct st_s12ad1_adcer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short ADPRC : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short ADPRC : 2; + unsigned short : 1; +#endif +}; + +union un_s12ad1_adcer +{ + unsigned short WORD; + struct st_s12ad1_adcer_bit BIT; +}; + +struct st_s12ad1_adstrgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif +}; + +union un_s12ad1_adstrgr +{ + unsigned short WORD; + struct st_s12ad1_adstrgr_bit BIT; +}; + +struct st_s12ad1_adexicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short TSSB : 1; + unsigned short OCSB : 1; + unsigned short : 1; + unsigned short EXSEL : 2; + unsigned short EXOEN : 1; +#else + unsigned short EXOEN : 1; + unsigned short EXSEL : 2; + unsigned short : 1; + unsigned short OCSB : 1; + unsigned short TSSB : 1; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif +}; + +union un_s12ad1_adexicr +{ + unsigned short WORD; + struct st_s12ad1_adexicr_bit BIT; +}; + +struct st_s12ad1_adansb0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB011 : 1; + unsigned short ANSB012 : 1; + unsigned short ANSB013 : 1; + unsigned short ANSB014 : 1; + unsigned short ANSB015 : 1; +#else + unsigned short ANSB015 : 1; + unsigned short ANSB014 : 1; + unsigned short ANSB013 : 1; + unsigned short ANSB012 : 1; + unsigned short ANSB011 : 1; + unsigned short ANSB010 : 1; + unsigned short ANSB009 : 1; + unsigned short ANSB008 : 1; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif +}; + +union un_s12ad1_adansb0 +{ + unsigned short WORD; + struct st_s12ad1_adansb0_bit BIT; +}; + +struct st_s12ad1_adansb1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif +}; + +union un_s12ad1_adansb1 +{ + unsigned short WORD; + struct st_s12ad1_adansb1_bit BIT; +}; + +struct st_s12ad1_adrd_bit_right +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif +}; + +struct st_s12ad1_adrd_bit_left +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif +}; + +union un_s12ad1_adrd_bit +{ + struct st_s12ad1_adrd_bit_right RIGHT; + struct st_s12ad1_adrd_bit_left LEFT; +}; + +union un_s12ad1_adrd +{ + unsigned short WORD; +}; + +struct st_s12ad1_adsampr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PRO : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char PRO : 2; +#endif +}; + +union un_s12ad1_adsampr +{ + unsigned char BYTE; + struct st_s12ad1_adsampr_bit BIT; +}; + +struct st_s12ad1_adsam_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short SAM : 1; + unsigned short : 10; +#else + unsigned short : 10; + unsigned short SAM : 1; + unsigned short : 5; +#endif +}; + +union un_s12ad1_adsam +{ + unsigned short WORD; + struct st_s12ad1_adsam_bit BIT; +}; + +struct st_s12ad1_addiscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif +}; + +union un_s12ad1_addiscr +{ + unsigned char BYTE; + struct st_s12ad1_addiscr_bit BIT; +}; + +struct st_s12ad1_adgspcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 12; + unsigned short LGRRS : 1; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short LGRRS : 1; + unsigned short : 12; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif +}; + +union un_s12ad1_adgspcr +{ + unsigned short WORD; + struct st_s12ad1_adgspcr_bit BIT; +}; + +struct st_s12ad1_adwinmon_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif +}; + +union un_s12ad1_adwinmon +{ + unsigned char BYTE; + struct st_s12ad1_adwinmon_bit BIT; +}; + +struct st_s12ad1_adcmpcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPAIE : 1; +#else + unsigned short CMPAIE : 1; + unsigned short WCMPE : 1; + unsigned short CMPBIE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif +}; + +union un_s12ad1_adcmpcr +{ + unsigned short WORD; + struct st_s12ad1_adcmpcr_bit BIT; +}; + +struct st_s12ad1_adcmpanser_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTS : 1; + unsigned char CMPSOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSOC : 1; + unsigned char CMPSTS : 1; +#endif +}; + +union un_s12ad1_adcmpanser +{ + unsigned char BYTE; + struct st_s12ad1_adcmpanser_bit BIT; +}; + +struct st_s12ad1_adcmpler_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTS : 1; + unsigned char CMPLOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOC : 1; + unsigned char CMPLTS : 1; +#endif +}; + +union un_s12ad1_adcmpler +{ + unsigned char BYTE; + struct st_s12ad1_adcmpler_bit BIT; +}; + +struct st_s12ad1_adcmpansr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA011 : 1; + unsigned short CMPCHA012 : 1; + unsigned short CMPCHA013 : 1; + unsigned short CMPCHA014 : 1; + unsigned short CMPCHA015 : 1; +#else + unsigned short CMPCHA015 : 1; + unsigned short CMPCHA014 : 1; + unsigned short CMPCHA013 : 1; + unsigned short CMPCHA012 : 1; + unsigned short CMPCHA011 : 1; + unsigned short CMPCHA010 : 1; + unsigned short CMPCHA009 : 1; + unsigned short CMPCHA008 : 1; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif +}; + +union un_s12ad1_adcmpansr0 +{ + unsigned short WORD; + struct st_s12ad1_adcmpansr0_bit BIT; +}; + +struct st_s12ad1_adcmpansr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif +}; + +union un_s12ad1_adcmpansr1 +{ + unsigned short WORD; + struct st_s12ad1_adcmpansr1_bit BIT; +}; + +struct st_s12ad1_adcmplr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA011 : 1; + unsigned short CMPLCHA012 : 1; + unsigned short CMPLCHA013 : 1; + unsigned short CMPLCHA014 : 1; + unsigned short CMPLCHA015 : 1; +#else + unsigned short CMPLCHA015 : 1; + unsigned short CMPLCHA014 : 1; + unsigned short CMPLCHA013 : 1; + unsigned short CMPLCHA012 : 1; + unsigned short CMPLCHA011 : 1; + unsigned short CMPLCHA010 : 1; + unsigned short CMPLCHA009 : 1; + unsigned short CMPLCHA008 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif +}; + +union un_s12ad1_adcmplr0 +{ + unsigned short WORD; + struct st_s12ad1_adcmplr0_bit BIT; +}; + +struct st_s12ad1_adcmplr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif +}; + +union un_s12ad1_adcmplr1 +{ + unsigned short WORD; + struct st_s12ad1_adcmplr1_bit BIT; +}; + +struct st_s12ad1_adcmpsr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA011 : 1; + unsigned short CMPSTCHA012 : 1; + unsigned short CMPSTCHA013 : 1; + unsigned short CMPSTCHA014 : 1; + unsigned short CMPSTCHA015 : 1; +#else + unsigned short CMPSTCHA015 : 1; + unsigned short CMPSTCHA014 : 1; + unsigned short CMPSTCHA013 : 1; + unsigned short CMPSTCHA012 : 1; + unsigned short CMPSTCHA011 : 1; + unsigned short CMPSTCHA010 : 1; + unsigned short CMPSTCHA009 : 1; + unsigned short CMPSTCHA008 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif +}; + +union un_s12ad1_adcmpsr0 +{ + unsigned short WORD; + struct st_s12ad1_adcmpsr0_bit BIT; +}; + +struct st_s12ad1_adcmpsr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif +}; + +union un_s12ad1_adcmpsr1 +{ + unsigned short WORD; + struct st_s12ad1_adcmpsr1_bit BIT; +}; + +struct st_s12ad1_adcmpser_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPFTS : 1; + unsigned char CMPFOC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPFOC : 1; + unsigned char CMPFTS : 1; +#endif +}; + +union un_s12ad1_adcmpser +{ + unsigned char BYTE; + struct st_s12ad1_adcmpser_bit BIT; +}; + +struct st_s12ad1_adcmpbnsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif +}; + +union un_s12ad1_adcmpbnsr +{ + unsigned char BYTE; + struct st_s12ad1_adcmpbnsr_bit BIT; +}; + +struct st_s12ad1_adcmpbsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif +}; + +union un_s12ad1_adcmpbsr +{ + unsigned char BYTE; + struct st_s12ad1_adcmpbsr_bit BIT; +}; + +struct st_s12ad1_adansc0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC000 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC011 : 1; + unsigned short ANSC012 : 1; + unsigned short ANSC013 : 1; + unsigned short ANSC014 : 1; + unsigned short ANSC015 : 1; +#else + unsigned short ANSC015 : 1; + unsigned short ANSC014 : 1; + unsigned short ANSC013 : 1; + unsigned short ANSC012 : 1; + unsigned short ANSC011 : 1; + unsigned short ANSC010 : 1; + unsigned short ANSC009 : 1; + unsigned short ANSC008 : 1; + unsigned short ANSC007 : 1; + unsigned short ANSC006 : 1; + unsigned short ANSC005 : 1; + unsigned short ANSC004 : 1; + unsigned short ANSC003 : 1; + unsigned short ANSC002 : 1; + unsigned short ANSC001 : 1; + unsigned short ANSC000 : 1; +#endif +}; + +union un_s12ad1_adansc0 +{ + unsigned short WORD; + struct st_s12ad1_adansc0_bit BIT; +}; + +struct st_s12ad1_adansc1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSC100 : 1; + unsigned short ANSC101 : 1; + unsigned short ANSC102 : 1; + unsigned short ANSC103 : 1; + unsigned short ANSC104 : 1; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short ANSC104 : 1; + unsigned short ANSC103 : 1; + unsigned short ANSC102 : 1; + unsigned short ANSC101 : 1; + unsigned short ANSC100 : 1; +#endif +}; + +union un_s12ad1_adansc1 +{ + unsigned short WORD; + struct st_s12ad1_adansc1_bit BIT; +}; + +struct st_s12ad1_adgcexcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TSSC : 1; + unsigned char OCSC : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char OCSC : 1; + unsigned char TSSC : 1; +#endif +}; + +union un_s12ad1_adgcexcr +{ + unsigned char BYTE; + struct st_s12ad1_adgcexcr_bit BIT; +}; + +struct st_s12ad1_adgctrgr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TRSC : 6; + unsigned char GCADIE : 1; + unsigned char GRCE : 1; +#else + unsigned char GRCE : 1; + unsigned char GCADIE : 1; + unsigned char TRSC : 6; +#endif +}; + +union un_s12ad1_adgctrgr +{ + unsigned char BYTE; + struct st_s12ad1_adgctrgr_bit BIT; +}; + +struct st_smci10_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif +}; + +union un_smci10_smr +{ + unsigned char BYTE; + struct st_smci10_smr_bit BIT; +}; + +struct st_smci_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_smci10_scr +{ + unsigned char BYTE; + struct st_smci_scr_bit BIT; +}; + +struct st_smci10_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_smci10_ssr +{ + unsigned char BYTE; + struct st_smci10_ssr_bit BIT; +}; + +struct st_smci10_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_smci10_scmr +{ + unsigned char BYTE; + struct st_smci10_scmr_bit BIT; +}; + +typedef struct st_smci10 +{ + union un_smci10_smr SMR; + char wk0[1]; + union un_smci10_scr SCR; + char wk1[1]; + union un_smci10_ssr SSR; + char wk2[1]; + union un_smci10_scmr SCMR; +} st_smci10_t; + +typedef struct st_bsc +{ + union un_bsc_berclr BERCLR; + char wk0[3]; + union un_bsc_beren BEREN; + char wk1[3]; + union un_bsc_bersr1 BERSR1; + char wk2[1]; + union un_bsc_bersr2 BERSR2; + char wk3[4]; + union un_bsc_buspri BUSPRI; + char wk4[7408]; + union un_bsc_cs0mod CS0MOD; + union un_bsc_cs0wcr1 CS0WCR1; + union un_bsc_cs0wcr2 CS0WCR2; + char wk5[6]; + union un_bsc_cs1mod CS1MOD; + union un_bsc_cs1wcr1 CS1WCR1; + union un_bsc_cs1wcr2 CS1WCR2; + char wk6[6]; + union un_bsc_cs2mod CS2MOD; + union un_bsc_cs2wcr1 CS2WCR1; + union un_bsc_cs2wcr2 CS2WCR2; + char wk7[6]; + union un_bsc_cs3mod CS3MOD; + union un_bsc_cs3wcr1 CS3WCR1; + union un_bsc_cs3wcr2 CS3WCR2; + char wk8[6]; + union un_bsc_cs4mod CS4MOD; + union un_bsc_cs4wcr1 CS4WCR1; + union un_bsc_cs4wcr2 CS4WCR2; + char wk9[6]; + union un_bsc_cs5mod CS5MOD; + union un_bsc_cs5wcr1 CS5WCR1; + union un_bsc_cs5wcr2 CS5WCR2; + char wk10[6]; + union un_bsc_cs6mod CS6MOD; + union un_bsc_cs6wcr1 CS6WCR1; + union un_bsc_cs6wcr2 CS6WCR2; + char wk11[6]; + union un_bsc_cs7mod CS7MOD; + union un_bsc_cs7wcr1 CS7WCR1; + union un_bsc_cs7wcr2 CS7WCR2; + char wk12[1926]; + union un_bsc_cs0cr CS0CR; + char wk13[6]; + union un_bsc_cs0rec CS0REC; + char wk14[6]; + union un_bsc_cs1cr CS1CR; + char wk15[6]; + union un_bsc_cs1rec CS1REC; + char wk16[6]; + union un_bsc_cs2cr CS2CR; + char wk17[6]; + union un_bsc_cs2rec CS2REC; + char wk18[6]; + union un_bsc_cs3cr CS3CR; + char wk19[6]; + union un_bsc_cs3rec CS3REC; + char wk20[6]; + union un_bsc_cs4cr CS4CR; + char wk21[6]; + union un_bsc_cs4rec CS4REC; + char wk22[6]; + union un_bsc_cs5cr CS5CR; + char wk23[6]; + union un_bsc_cs5rec CS5REC; + char wk24[6]; + union un_bsc_cs6cr CS6CR; + char wk25[6]; + union un_bsc_cs6rec CS6REC; + char wk26[6]; + union un_bsc_cs7cr CS7CR; + char wk27[6]; + union un_bsc_cs7rec CS7REC; + char wk28[4]; + union un_bsc_csrecen CSRECEN; + char wk29[894]; + union un_bsc_sdccr SDCCR; + union un_bsc_sdcmod SDCMOD; + union un_bsc_sdamod SDAMOD; + char wk30[13]; + union un_bsc_sdself SDSELF; + char wk31[3]; + union un_bsc_sdrfcr SDRFCR; + union un_bsc_sdrfen SDRFEN; + char wk32[9]; + union un_bsc_sdicr SDICR; + char wk33[3]; + union un_bsc_sdir SDIR; + char wk34[26]; + union un_bsc_sdadr SDADR; + char wk35[3]; + union un_bsc_sdtr SDTR; + union un_bsc_sdmod SDMOD; + char wk36[6]; + union un_bsc_sdsr SDSR; + char wk37[269231]; + union un_bsc_ebmapcr EBMAPCR; +} st_bsc_t; + +typedef struct st_cac +{ + union un_cac_cacr0 CACR0; + union un_cac_cacr1 CACR1; + union un_cac_cacr2 CACR2; + union un_cac_caicr CAICR; + union un_cac_castr CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_can +{ + struct st_can_mb MB[32]; + union un_can_mkr MKR[8]; + union un_can_fidcr0 FIDCR0; + union un_can_fidcr1 FIDCR1; + union un_can_mkivlr MKIVLR; + union un_can_mier MIER; + char wk0[1008]; + union un_can_mctl MCTL[32]; + union un_can_ctlr CTLR; + union un_can_str STR; + union un_can_bcr BCR; + union un_can_rfcr RFCR; + unsigned char RFPCR; + union un_can_tfcr TFCR; + unsigned char TFPCR; + union un_can_eier EIER; + union un_can_eifr EIFR; + unsigned char RECR; + unsigned char TECR; + union un_can_ecsr ECSR; + unsigned char CSSR; + union un_can_mssr MSSR; + union un_can_msmr MSMR; + unsigned short TSR; + unsigned short AFSR; + union un_can_tcr TCR; +} st_can_t; + +typedef struct st_cmt +{ + union un_cmt_cmstr0 CMSTR0; + char wk0[14]; + union un_cmt_cmstr1 CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 +{ + union un_cmt0_cmcr CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_icu +{ + union un_icu_ir256 IR[256]; + union un_icu_dtcer256 DTCER[256]; + union un_icu_ier32 IER[32]; + char wk0[192]; + union un_icu_swintr SWINTR; + union un_icu_swint2r SWINT2R; + char wk1[14]; + union un_icu_fir FIR; + char wk2[14]; + union un_icu_ipr256 IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union un_icu_irqcr16 IRQCR[16]; + char wk11[16]; + union un_icu_irqflte0 IRQFLTE0; + union un_icu_irqflte1 IRQFLTE1; + char wk12[6]; + union un_icu_irqfltc0 IRQFLTC0; + union un_icu_irqfltc1 IRQFLCT1; + char wk13[84]; + union un_icu_nmisr NMISR; + union un_icu_nmier NMIER; + union un_icu_nmiclr NMICLR; + union un_icu_nmicr NMICR; + char wk14[12]; + union un_icu_nmiflte NMIFLTE; + char wk15[3]; + union un_icu_nmifltc NMIFLTC; + char wk16[107]; + union un_icu_grpbe0 GRPBE0; + char wk17[44]; + union un_icu_grpbl0 GRPBL0; + union un_icu_grpbl1 GRPBL1; + union un_icu_grpbl2 GRPBL2; + char wk18[4]; + union un_icu_genbe0 GENBE0; + char wk19[44]; + union un_icu_genbl0 GENBL0; + union un_icu_genbl1 GENBL1; + union un_icu_genbl2 GENBL2; + char wk20[4]; + union un_icu_gcrbe0 GCRBE0; + char wk21[124]; + union un_icu_pibr0 PIBR0; + union un_icu_pibr1 PIBR1; + union un_icu_pibr2 PIBR2; + union un_icu_pibr3 PIBR3; + union un_icu_pibr4 PIBR4; + union un_icu_pibr5 PIBR5; + union un_icu_pibr6 PIBR6; + union un_icu_pibr7 PIBR7; + union un_icu_pibr8 PIBR8; + union un_icu_pibr9 PIBR9; + union un_icu_pibra PIBRA; + union un_icu_pibrb PIBRB; + char wk22[116]; + union un_icu_slibxr128 SLIBXR128; + union un_icu_slibxr129 SLIBXR129; + union un_icu_slibxr130 SLIBXR130; + union un_icu_slibxr131 SLIBXR131; + union un_icu_slibxr132 SLIBXR132; + union un_icu_slibxr133 SLIBXR133; + union un_icu_slibxr134 SLIBXR134; + union un_icu_slibxr135 SLIBXR135; + union un_icu_slibxr136 SLIBXR136; + union un_icu_slibxr137 SLIBXR137; + union un_icu_slibxr138 SLIBXR138; + union un_icu_slibxr139 SLIBXR139; + union un_icu_slibxr140 SLIBXR140; + union un_icu_slibxr141 SLIBXR141; + union un_icu_slibxr142 SLIBXR142; + union un_icu_slibxr143 SLIBXR143; + union un_icu_slibr144 SLIBR144; + union un_icu_slibr145 SLIBR145; + union un_icu_slibr146 SLIBR146; + union un_icu_slibr147 SLIBR147; + union un_icu_slibr148 SLIBR148; + union un_icu_slibr149 SLIBR149; + union un_icu_slibr150 SLIBR150; + union un_icu_slibr151 SLIBR151; + union un_icu_slibr152 SLIBR152; + union un_icu_slibr153 SLIBR153; + union un_icu_slibr154 SLIBR154; + union un_icu_slibr155 SLIBR155; + union un_icu_slibr156 SLIBR156; + union un_icu_slibr157 SLIBR157; + union un_icu_slibr158 SLIBR158; + union un_icu_slibr159 SLIBR159; + union un_icu_slibr160 SLIBR160; + union un_icu_slibr161 SLIBR161; + union un_icu_slibr162 SLIBR162; + union un_icu_slibr163 SLIBR163; + union un_icu_slibr164 SLIBR164; + union un_icu_slibr165 SLIBR165; + union un_icu_slibr166 SLIBR166; + union un_icu_slibr167 SLIBR167; + union un_icu_slibr168 SLIBR168; + union un_icu_slibr169 SLIBR169; + union un_icu_slibr170 SLIBR170; + union un_icu_slibr171 SLIBR171; + union un_icu_slibr172 SLIBR172; + union un_icu_slibr173 SLIBR173; + union un_icu_slibr174 SLIBR174; + union un_icu_slibr175 SLIBR175; + union un_icu_slibr176 SLIBR176; + union un_icu_slibr177 SLIBR177; + union un_icu_slibr178 SLIBR178; + union un_icu_slibr179 SLIBR179; + union un_icu_slibr180 SLIBR180; + union un_icu_slibr181 SLIBR181; + union un_icu_slibr182 SLIBR182; + union un_icu_slibr183 SLIBR183; + union un_icu_slibr184 SLIBR184; + union un_icu_slibr185 SLIBR185; + union un_icu_slibr186 SLIBR186; + union un_icu_slibr187 SLIBR187; + union un_icu_slibr188 SLIBR188; + union un_icu_slibr189 SLIBR189; + union un_icu_slibr190 SLIBR190; + union un_icu_slibr191 SLIBR191; + union un_icu_slibr192 SLIBR192; + union un_icu_slibr193 SLIBR193; + union un_icu_slibr194 SLIBR194; + union un_icu_slibr195 SLIBR195; + union un_icu_slibr196 SLIBR196; + union un_icu_slibr197 SLIBR197; + union un_icu_slibr198 SLIBR198; + union un_icu_slibr199 SLIBR199; + union un_icu_slibr200 SLIBR200; + union un_icu_slibr201 SLIBR201; + union un_icu_slibr202 SLIBR202; + union un_icu_slibr203 SLIBR203; + union un_icu_slibr204 SLIBR204; + union un_icu_slibr205 SLIBR205; + union un_icu_slibr206 SLIBR206; + union un_icu_slibr207 SLIBR207; + char wk23[96]; + union un_icu_grpal0 GRPAL0; + union un_icu_grpal1 GRPAL1; + char wk24[56]; + union un_icu_genal0 GENAL0; + union un_icu_genal1 GENAL1; + char wk25[136]; + union un_icu_piar0 PIAR0; + union un_icu_piar1 PIAR1; + union un_icu_piar2 PIAR2; + union un_icu_piar3 PIAR3; + union un_icu_piar4 PIAR4; + union un_icu_piar5 PIAR5; + char wk26[5]; + union un_icu_piarb PIARB; + char wk27[196]; + union un_icu_sliar208 SLIAR208; + union un_icu_sliar209 SLIAR209; + union un_icu_sliar210 SLIAR210; + union un_icu_sliar211 SLIAR211; + union un_icu_sliar212 SLIAR212; + union un_icu_sliar213 SLIAR213; + union un_icu_sliar214 SLIAR214; + union un_icu_sliar215 SLIAR215; + union un_icu_sliar216 SLIAR216; + union un_icu_sliar217 SLIAR217; + union un_icu_sliar218 SLIAR218; + union un_icu_sliar219 SLIAR219; + union un_icu_sliar220 SLIAR220; + union un_icu_sliar221 SLIAR221; + union un_icu_sliar222 SLIAR222; + union un_icu_sliar223 SLIAR223; + union un_icu_sliar224 SLIAR224; + union un_icu_sliar225 SLIAR225; + union un_icu_sliar226 SLIAR226; + union un_icu_sliar227 SLIAR227; + union un_icu_sliar228 SLIAR228; + union un_icu_sliar229 SLIAR229; + union un_icu_sliar230 SLIAR230; + union un_icu_sliar231 SLIAR231; + union un_icu_sliar232 SLIAR232; + union un_icu_sliar233 SLIAR233; + union un_icu_sliar234 SLIAR234; + union un_icu_sliar235 SLIAR235; + union un_icu_sliar236 SLIAR236; + union un_icu_sliar236 SLIAR237; + union un_icu_sliar237 SLIAR238; + union un_icu_sliar239 SLIAR239; + union un_icu_sliar240 SLIAR240; + union un_icu_sliar241 SLIAR241; + union un_icu_sliar242 SLIAR242; + union un_icu_sliar243 SLIAR243; + union un_icu_sliar244 SLIAR244; + union un_icu_sliar245 SLIAR245; + union un_icu_sliar246 SLIAR246; + union un_icu_sliar247 SLIAR247; + union un_icu_sliar248 SLIAR248; + union un_icu_sliar249 SLIAR249; + union un_icu_sliar250 SLIAR250; + union un_icu_sliar251 SLIAR251; + union un_icu_sliar252 SLIAR252; + union un_icu_sliar253 SLIAR253; + union un_icu_sliar254 SLIAR254; + union un_icu_sliar255 SLIAR255; + union un_icu_sliprcr SLIPRCR; + union un_icu_slexdr SLEXDR; +} st_icu_t; + +typedef struct st_mpc +{ + union un_mpc_pfcse PFCSE; + char wk0[1]; + union un_mpc_pfcss0 PFCSS0; + union un_mpc_pfcss1 PFCSS1; + union un_mpc_pfa0e0 PFA0E0; + union un_mpc_pfa0e1 PFA0E1; + union un_mpc_pfbcr0 PFBCR0; + union un_mpc_pfbcr1 PFBCR1; + union un_mpc_pfbcr2 PFBCR2; + union un_mpc_pfbcr3 PFBCR3; + char wk1[4]; + union un_mpc_pfenet PFENET; + char wk2[16]; + union un_mpc_pwpr PWPR; + char wk3[32]; + union un_mpc_p00pfs P00PFS; + union un_mpc_p01pfs P01PFS; + union un_mpc_p02pfs P02PFS; + union un_mpc_p03pfs P03PFS; + char wk4[1]; + union un_mpc_p05pfs P05PFS; + char wk5[1]; + union un_mpc_p07pfs P07PFS; + union un_mpc_p10pfs P10PFS; + union un_mpc_p11pfs P11PFS; + union un_mpc_p12pfs P12PFS; + union un_mpc_p13pfs P13PFS; + union un_mpc_p14pfs P14PFS; + union un_mpc_p15pfs P15PFS; + union un_mpc_p16pfs P16PFS; + union un_mpc_p17pfs P17PFS; + union un_mpc_p20pfs P20PFS; + union un_mpc_p21pfs P21PFS; + union un_mpc_p22pfs P22PFS; + union un_mpc_p23pfs P23PFS; + union un_mpc_p24pfs P24PFS; + union un_mpc_p25pfs P25PFS; + union un_mpc_p26pfs P26PFS; + union un_mpc_p27pfs P27PFS; + union un_mpc_p30pfs P30PFS; + union un_mpc_p31pfs P31PFS; + union un_mpc_p32pfs P32PFS; + union un_mpc_p33pfs P33PFS; + union un_mpc_p34pfs P34PFS; + char wk6[3]; + union un_mpc_p40pfs P40PFS; + union un_mpc_p41pfs P41PFS; + union un_mpc_p42pfs P42PFS; + union un_mpc_p43pfs P43PFS; + union un_mpc_p44pfs P44PFS; + union un_mpc_p45pfs P45PFS; + union un_mpc_p46pfs P46PFS; + union un_mpc_p47pfs P47PFS; + union un_mpc_p50pfs P50PFS; + union un_mpc_p51pfs P51PFS; + union un_mpc_p52pfs P52PFS; + char wk7[1]; + union un_mpc_p54pfs P54PFS; + union un_mpc_p55pfs P55PFS; + union un_mpc_p56pfs P56PFS; + union un_mpc_p57pfs P57PFS; + char wk8[6]; + union un_mpc_p66pfs P66PFS; + union un_mpc_p67pfs P67PFS; + char wk9[1]; + union un_mpc_p71pfs P71PFS; + union un_mpc_p72pfs P72PFS; + union un_mpc_p73pfs P73PFS; + union un_mpc_p74pfs P74PFS; + union un_mpc_p75pfs P75PFS; + union un_mpc_p76pfs P76PFS; + union un_mpc_p77pfs P77PFS; + union un_mpc_p80pfs P80PFS; + union un_mpc_p81pfs P81PFS; + union un_mpc_p82pfs P82PFS; + union un_mpc_p83pfs P83PFS; + union un_mpc_p84pfs P84PFS; + union un_mpc_p85pfs P85PFS; + union un_mpc_p86pfs P86PFS; + union un_mpc_p87pfs P87PFS; + union un_mpc_p90pfs P90PFS; + union un_mpc_p91pfs P91PFS; + union un_mpc_p92pfs P92PFS; + union un_mpc_p93pfs P93PFS; + char wk10[4]; + union un_mpc_pa0pfs PA0PFS; + union un_mpc_pa1pfs PA1PFS; + union un_mpc_pa2pfs PA2PFS; + union un_mpc_pa3pfs PA3PFS; + union un_mpc_pa4pfs PA4PFS; + union un_mpc_pa5pfs PA5PFS; + union un_mpc_pa6pfs PA6PFS; + union un_mpc_pa7pfs PA7PFS; + union un_mpc_pb0pfs PB0PFS; + union un_mpc_pb1pfs PB1PFS; + union un_mpc_pb2pfs PB2PFS; + union un_mpc_pb3pfs PB3PFS; + union un_mpc_pb4pfs PB4PFS; + union un_mpc_pb5pfs PB5PFS; + union un_mpc_pb6pfs PB6PFS; + union un_mpc_pb7pfs PB7PFS; + union un_mpc_pc0pfs PC0PFS; + union un_mpc_pc1pfs PC1PFS; + union un_mpc_pc2pfs PC2PFS; + union un_mpc_pc3pfs PC3PFS; + union un_mpc_pc4pfs PC4PFS; + union un_mpc_pc5pfs PC5PFS; + union un_mpc_pc6pfs PC6PFS; + union un_mpc_pc7pfs PC7PFS; + union un_mpc_pd0pfs PD0PFS; + union un_mpc_pd1pfs PD1PFS; + union un_mpc_pd2pfs PD2PFS; + union un_mpc_pd3pfs PD3PFS; + union un_mpc_pd4pfs PD4PFS; + union un_mpc_pd5pfs PD5PFS; + union un_mpc_pd6pfs PD6PFS; + union un_mpc_pd7pfs PD7PFS; + union un_mpc_pe0pfs PE0PFS; + union un_mpc_pe1pfs PE1PFS; + union un_mpc_pe2pfs PE2PFS; + union un_mpc_pe3pfs PE3PFS; + union un_mpc_pe4pfs PE4PFS; + union un_mpc_pe5pfs PE5PFS; + union un_mpc_pe6pfs PE6PFS; + union un_mpc_pe7pfs PE7PFS; + union un_mpc_pf0pfs PF0PFS; + union un_mpc_pf1pfs PF1PFS; + union un_mpc_pf2pfs PF2PFS; + char wk11[2]; + union un_mpc_pf5pfs PF5PFS; + char wk12[18]; + union un_mpc_pj0pfs PJ0PFS; + union un_mpc_pj1pfs PJ1PFS; + union un_mpc_pj2pfs PJ2PFS; + union un_mpc_pj3pfs PJ3PFS; + char wk13[1]; + union un_mpc_pj5pfs PJ5PFS; +} st_mpc_t; + +typedef struct st_port0 +{ + union un_port0_pdr PDR; + char wk0[31]; + union un_port0_podr PODR; + char wk1[31]; + union un_port0_pidr PIDR; + char wk2[31]; + union un_port0_pmr PMR; + char wk3[31]; + union un_port0_odr0 ODR0; + union un_port0_odr1 ODR1; + char wk4[62]; + union un_port0_pcr PCR; + char wk5[31]; + union un_port0_dscr DSCR; + char wk6[71]; + union un_port0_dscr2 DSCR2; +} st_port0_t; + +typedef struct st_port1 +{ + union un_port1_pdr PDR; + char wk0[31]; + union un_port1_podr PODR; + char wk1[31]; + union un_port1_pidr PIDR; + char wk2[31]; + union un_port1_pmr PMR; + char wk3[32]; + union un_port1_odr0 ODR0; + union un_port1_odr1 ODR1; + char wk4[61]; + union un_port1_pcr PCR; + char wk5[31]; + union un_port1_dscr DSCR; + char wk6[71]; + union un_port1_dscr2 DSCR2; +} st_port1_t; + +typedef struct st_port2 +{ + union un_port2_pdr PDR; + char wk0[31]; + union un_port2_podr PODR; + char wk1[31]; + union un_port2_pidr PIDR; + char wk2[31]; + union un_port2_pmr PMR; + char wk3[33]; + union un_port2_odr0 ODR0; + union un_port2_odr1 ODR1; + char wk4[60]; + union un_port2_pcr PCR; + char wk5[31]; + union un_port2_dscr DSCR; + char wk6[71]; + union un_port2_dscr2 DSCR2; +} st_port2_t; + +typedef struct st_port3 +{ + union un_port3_pdr PDR; + char wk0[31]; + union un_port3_podr PODR; + char wk1[31]; + union un_port3_pidr PIDR; + char wk2[31]; + union un_port3_pmr PMR; + char wk3[34]; + union un_port3_odr0 ODR0; + union un_port3_odr1 ODR1; + char wk4[59]; + union un_port3_pcr PCR; + char wk5[103]; + union un_port3_dscr2 DSCR2; +} st_port3_t; + +typedef struct st_port5 +{ + union un_port5_pdr PDR; + char wk0[31]; + union un_port5_podr PODR; + char wk1[31]; + union un_port5_pidr PIDR; + char wk2[31]; + union un_port5_pmr PMR; + char wk3[36]; + union un_port5_odr0 ODR0; + union un_port5_odr1 ODR1; + char wk4[57]; + union un_port5_pcr PCR; + char wk5[31]; + union un_port5_dscr DSCR; + char wk6[71]; + union un_port5_dscr2 DSCR2; +} st_port5_t; + +typedef struct st_port7 +{ + union un_port7_pdr PDR; + char wk0[31]; + union un_port7_podr PODR; + char wk1[31]; + union un_port7_pidr PIDR; + char wk2[31]; + union un_port7_pmr PMR; + char wk3[38]; + union un_port7_odr0 ODR0; + union un_port7_odr1 ODR1; + char wk4[55]; + union un_port7_pcr PCR; + char wk5[31]; + union un_port7_dscr DSCR; + char wk6[71]; + union un_port7_dscr2 DSCR2; +} st_port7_t; + +typedef struct st_port8 +{ + union un_port8_pdr PDR; + char wk0[31]; + union un_port8_podr PODR; + char wk1[31]; + union un_port8_pidr PIDR; + char wk2[31]; + union un_port8_pmr PMR; + char wk3[39]; + union un_port8_odr0 ODR0; + union un_port8_odr1 ODR1; + char wk4[54]; + union un_port8_pcr PCR; + char wk5[31]; + union un_port8_dscr DSCR; + char wk6[71]; + union un_port8_dscr2 DSCR2; +} st_port8_t; + +typedef struct st_port9 +{ + union un_port9_pdr PDR; + char wk0[31]; + union un_port9_podr PODR; + char wk1[31]; + union un_port9_pidr PIDR; + char wk2[31]; + union un_port9_pmr PMR; + char wk3[40]; + union un_port9_odr0 ODR0; + union un_port9_odr1 ODR1; + char wk4[53]; + union un_port9_pcr PCR; + char wk5[31]; + union un_port9_dscr DSCR; + char wk6[71]; + union un_port9_dscr2 DSCR2; +} st_port9_t; + +typedef struct st_porta +{ + union un_porta_pdr PDR; + char wk0[31]; + union un_porta_podr PODR; + char wk1[31]; + union un_porta_pidr PIDR; + char wk2[31]; + union un_porta_pmr PMR; + char wk3[41]; + union un_porta_odr0 ODR0; + union un_porta_odr1 ODR1; + char wk4[52]; + union un_porta_pcr PCR; + char wk5[31]; + union un_porta_dscr DSCR; + char wk6[71]; + union un_porta_dscr2 DSCR2; +} st_porta_t; + +typedef struct st_portb +{ + union un_portb_pdr PDR; + char wk0[31]; + union un_portb_podr PODR; + char wk1[31]; + union un_portb_pidr PIDR; + char wk2[31]; + union un_portb_pmr PMR; + char wk3[42]; + union un_portb_odr0 ODR0; + union un_portb_odr1 ODR1; + char wk4[51]; + union un_portb_pcr PCR; + char wk5[31]; + union un_portb_dscr DSCR; + char wk6[71]; + union un_portb_dscr2 DSCR2; +} st_portb_t; + +typedef struct st_portc +{ + union un_portc_pdr PDR; + char wk0[31]; + union un_portc_podr PODR; + char wk1[31]; + union un_portc_pidr PIDR; + char wk2[31]; + union un_portc_pmr PMR; + char wk3[43]; + union un_portc_odr0 ODR0; + union un_portc_odr1 ODR1; + char wk4[50]; + union un_portc_pcr PCR; + char wk5[31]; + union un_portc_dscr DSCR; + char wk6[71]; + union un_portc_dscr2 DSCR2; +} st_portc_t; + +typedef struct st_porte +{ + union un_porte_pdr PDR; + char wk0[31]; + union un_porte_podr PODR; + char wk1[31]; + union un_porte_pidr PIDR; + char wk2[31]; + union un_porte_pmr PMR; + char wk3[45]; + union un_porte_odr0 ODR0; + union un_porte_odr1 ODR1; + char wk4[48]; + union un_porte_pcr PCR; + char wk5[31]; + union un_porte_dscr DSCR; + char wk6[71]; + union un_porte_dscr2 DSCR2; +} st_porte_t; + +typedef struct st_portf +{ + union un_portf_pdr PDR; + char wk0[31]; + union un_portf_podr PODR; + char wk1[31]; + union un_portf_pidr PIDR; + char wk2[31]; + union un_portf_pmr PMR; + char wk3[46]; + union un_portf_odr0 ODR0; + union un_portf_odr1 ODR1; + char wk4[47]; + union un_portf_pcr PCR; +} st_portf_t; + +typedef struct st_portg +{ + union un_portg_pdr PDR; + char wk0[31]; + union un_portg_podr PODR; + char wk1[31]; + union un_portg_pidr PIDR; + char wk2[31]; + union un_portg_pmr PMR; + char wk3[47]; + union un_portg_odr0 ODR0; + union un_portg_odr1 ODR1; + char wk4[46]; + union un_portg_pcr PCR; + char wk5[31]; + union un_portg_dscr DSCR; + char wk6[71]; + union un_portg_dscr2 DSCR2; +} st_portg_t; + +typedef struct st_portj +{ + union un_portj_pdr PDR; + char wk0[31]; + union un_portj_podr PODR; + char wk1[31]; + union un_portj_pidr PIDR; + char wk2[31]; + union un_portj_pmr PMR; + char wk3[49]; + union un_portj_odr0 ODR0; + union un_portj_odr1 ODR1; + char wk4[44]; + union un_portj_pcr PCR; + char wk5[31]; + union un_portj_dscr DSCR; + char wk6[71]; + union un_portj_dscr2 DSCR2; +} st_portj_t; + +typedef struct st_rtc +{ + union un_rtc_r64cnt R64CNT; + char wk0[1]; + union + { + union un_rtc_rseccnt RSECCNT; + union un_rtc_bcnt0 BCNT0; + }; + char wk1[1]; + union + { + union un_rtc_rmincnt RMINCNT; + union un_rtc_bcnt1 BCNT1; + }; + char wk2[1]; + union + { + union un_rtc_rhrcnt RHRCNT; + union un_rtc_bcnt2 BCNT2; + }; + char wk3[1]; + union + { + union un_rtc_rwkcnt RWKCNT; + union un_rtc_bcnt3 BCNT3; + }; + char wk4[1]; + union un_rtc_rdaycnt RDAYCNT; + char wk5[1]; + union un_rtc_rmoncnt RMONCNT; + char wk6[1]; + union un_rtc_ryrcnt RYRCNT; + union + { + union un_rtc_rsecar RSECAR; + union un_rtc_bcnt0ar BCNT0AR; + }; + char wk7[1]; + union + { + union un_rtc_rminar RMINAR; + union un_rtc_bcnt1ar BCNT1AR; + }; + char wk8[1]; + union + { + union un_rtc_rhrar RHRAR; + union un_rtc_bcnt2ar BCNT2AR; + }; + char wk9[1]; + union + { + union un_rtc_rwkar RWKAR; + union un_rtc_bcnt3ar BCNT3AR; + }; + char wk10[1]; + union + { + union un_rtc_rdayar RDAYAR; + union un_rtc_bcnt0aer BCNT0AER; + }; + char wk11[1]; + union + { + union un_rtc_rmonar RMONAR; + union un_rtc_bcnt1aer BCNT1AER; + }; + char wk12[1]; + union + { + union un_rtc_ryrar RYRAR; + union un_rtc_bcnt2aer BCNT2AER; + }; + union + { + union un_rtc_ryraren RYRAREN; + union un_rtc_bcnt3aer BCNT3AER; + }; + char wk13[3]; + union un_rtc_rcr1 RCR1; + char wk14[1]; + union un_rtc_rcr2 RCR2; + char wk15[1]; + union un_rtc_rcr3 RCR3; + char wk16[1]; + union un_rtc_rcr4 RCR4; + char wk17[1]; + union un_rtc_rfrh RFRH; + union un_rtc_rfrl RFRL; + union un_rtc_radj RADJ; + char wk18[17]; + union un_rtc_rtccr0 RTCCR0; + char wk19[1]; + union un_rtc_rtccr1 RTCCR1; + char wk20[1]; + union un_rtc_rtccr2 RTCCR2; + char wk21[13]; + union + { + union un_rtc_rseccp0 RSECCP0; + union un_rtc_bcnt0cp0 BCNT0PC0; + }; + char wk22[1]; + union + { + union un_rtc_rmincp0 RMINCP0; + union un_rtc_bcnt1cp0 BCNT1CP0; + }; + char wk23[1]; + union + { + union un_rtc_rhrcp0 RHRCP0; + union un_rtc_bcnt2cp0 BCNT2CP0; + }; + char wk24[3]; + union + { + union un_rtc_rdaycp0 RDAYCP0; + union un_rtc_bcnt3cp0 BCNT3CP0; + }; + char wk25[1]; + union un_rtc_rmoncp0 RMONCP0; + char wk26[5]; + union + { + union un_rtc_rseccp1 RSECCP1; + union un_rtc_bcnt0cp1 BCNT0CP1; + }; + char wk27[1]; + union + { + union un_rtc_rmincp1 RMINCP1; + union un_rtc_bcnt1cp1 BCNT1CP1; + }; + char wk28[1]; + union + { + union un_rtc_rhrcp1 RHRCP1; + union un_rtc_bcnt2cp1 BCNT2CP1; + }; + char wk29[3]; + union + { + union un_rtc_rdaycp1 RDAYCP1; + union un_rtc_bcnt3cp1 BCNT3CP1; + }; + char wk30[1]; + union un_rtc_rmoncp1 RMONCP1; + char wk31[5]; + union + { + union un_rtc_rseccp2 RSECCP2; + union un_rtc_bcnt0cp2 BCNT0CP2; + }; + char wk32[1]; + union + { + union un_rtc_rmincp2 RMINCP2; + union un_rtc_bcnt1cp2 BCNT1CP2; + }; + char wk33[1]; + union + { + union un_rtc_rhrcp2 RHRCP2; + union un_rtc_bcnt2cp2 BCNT2CP2; + }; + char wk34[3]; + union + { + union un_rtc_rdaycp2 RDAYCP2; + union un_rtc_bcnt3cp2 BCNT3CP2; + }; + char wk35[1]; + union un_rtc_rmoncp2 RMONCP2; +} st_rtc_t; + +typedef struct st_sci0 +{ + union un_sci0_smr SMR; + unsigned char BRR; + union un_sci0_scr SCR; + unsigned char TDR; + union un_sci0_ssr SSR; + unsigned char RDR; + union un_sci0_scmr SCMR; + union un_sci0_semr SEMR; + union un_sci0_snfr SNFR; + union un_sci0_simr1 SIMR1; + union un_sci0_simr2 SIMR2; + union un_sci0_simr3 SIMR3; + union un_sci0_sisr SISR; + union un_sci0_spmr SPMR; + union un_sci0_tdrhl TDRHL; + union un_sci0_rdrhl RDRHL; + unsigned char MDDR; +} st_sci0_t; + +typedef struct st_system +{ + union un_system_mdmonr MDMONR; + char wk0[4]; + union un_system_syscr0 SYSCR0; + union un_system_syscr1 SYSCR1; + char wk1[2]; + union un_system_sbycr SBYCR; + char wk2[2]; + union un_system_mstpcra MSTPCRA; + union un_system_mstpcrb MSTPCRB; + union un_system_mstpcrc MSTPCRC; + union un_system_mstpcrd MSTPCRD; + union un_system_sckcr SCKCR; + union un_system_sckcr2 SCKCR2; + union un_system_sckcr3 SCKCR3; + union un_system_pllcr PLLCR; + union un_system_pllcr2 PLLCR2; + char wk3[5]; + union un_system_bckcr BCKCR; + char wk4[1]; + union un_system_mosccr MOSCCR; + union un_system_sosccr SOSCCR; + union un_system_lococr LOCOCR; + union un_system_ilococr ILOCOCR; + union un_system_hococr HOCOCR; + union un_system_hococr2 HOCOCR2; + char wk5[4]; + union un_system_oscovfsr OSCOVFSR; + char wk6[3]; + union un_system_ostdcr OSTDCR; + union un_system_ostdsr OSTDSR; + char wk7[94]; + union un_system_opccr OPCCR; + union un_system_rstckcr RSTCKCR; + union un_system_moscwtcr MOSCWTCR; + union un_system_soscwtcr SOSCWTCR; + char wk8[28]; + union un_system_rstsr2 RSTSR2; + char wk9[1]; + unsigned short SWRR; + char wk10[28]; + union un_system_lvd1cr1 LVD1CR1; + union un_system_lvd1sr LVD1SR; + union un_system_lvd2cr1 LVD2CR1; + union un_system_lvd2sr LVD2SR; + char wk11[794]; + union un_system_prcr PRCR; + char wk12[3100]; + union un_system_romwt ROMWT; + char wk13[45667]; + union un_system_dpsbycr DPSBYCR; + char wk14[1]; + union un_system_dpsier0 DPSIER0; + union un_system_dpsier1 DPSIER1; + union un_system_dpsier2 DPSIER2; + union un_system_dpsier3 DPSIER3; + union un_system_dpsifr0 DPSIFR0; + union un_system_dpsifr1 DPSIFR1; + union un_system_dpsifr2 DPSIFR2; + union un_system_dpsifr3 DPSIFR3; + union un_system_dpsiegr0 DPSIEGR0; + union un_system_dpsiegr1 DPSIEGR1; + union un_system_dpsiegr2 DPSIEGR2; + union un_system_dpsiegr3 DPSIEGR3; + char wk15[2]; + union un_system_rstsr0 RSTSR0; + union un_system_rstsr1 RSTSR1; + char wk16[1]; + union un_system_mofcr MOFCR; + union un_system_hocopcr HOCOPCR; + char wk17[2]; + union un_system_lvcmpcr LVCMPCR; + union un_system_lvdlvlr LVDLVLR; + char wk18[1]; + union un_system_lvd1cr0 LVD1CR0; + union un_system_lvd2cr0 LVD2CR0; + char wk19[4]; + unsigned char DPSBKR[32]; +} st_system_t; + +typedef struct st_sci10 +{ + union un_sci10_smr SMR; + unsigned char BRR; + union un_sci10_scr SCR; + unsigned char TDR; + union + { + union un_sci10_ssr SSR; + union un_sci10_ssrfifo SSRFIFO; + }; + unsigned char RDR; + union un_sci10_scmr SCMR; + union un_sci10_semr SEMR; + union un_sci10_snfr SNFR; + union un_sci10_simr1 SIMR1; + union un_sci10_simr2 SIMR2; + union un_sci10_simr3 SIMR3; + union un_sci10_sisr SISR; + union un_sci10_spmr SPMR; + union + { + union un_sci10_tdrhl TDRHL; + union un_sci10_ftdr_bit_byte FTDR; + }; + union + { + union un_sci10_rdrhl_byte RDRHL; + union un_sci10_frdr_bit_byte FRDR; + }; + unsigned char MDDR; + union un_sci10_dccr DCCR; + union un_sci10_fcr FCR; + union un_sci10_fdr FDR; + union un_sci10_lsr LSR; + union un_sci10_cdr CDR; + union st_sci10_sptr SPTR; +} st_sci10_t; + +typedef struct st_sci12 +{ + union un_sci12_smr SMR; + unsigned char BRR; + union un_sci12_scr SCR; + unsigned char TDR; + union un_sci12_ssr SSR; + unsigned char RDR; + union un_sci12_scmr SCMR; + union un_sci12_semr SEMR; + union un_sci12_snfr SNFR; + union un_sci12_simr1 SIMR1; + union un_sci12_simr2 SIMR2; + union un_sci12_simr3 SIMR3; + union un_sci12_sisr SISR; + union un_sci12_spmr SPMR; + union un_sci12_tdrhl TDRHL; + union un_sci12_rdrhl RDRHL; + unsigned char MDDR; + char wk0[13]; + union un_sci12_esmer ESMER; + union un_sci12_ctr0 CTR0; + union un_sci12_ctr1 CTR1; + union un_sci12_ctr2 CTR2; + union un_sci12_ctr3 CTR3; + union un_sci12_pcr PCR; + union un_sci12_icr ICR; + union un_sci12_str STR; + union un_sci12_stcr STCR; + unsigned char CF0DR; + union un_sci12_cf0cr CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union un_sci12_cf1cr CF1CR; + unsigned char CF1RR; + union un_sci12_tcr TCR; + union un_sci12_tmr TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_cmtw +{ + union un_cmtw_cmwstr CMWSTR; + char wk0[2]; + union un_cmtw_cmwcr CMWCR; + char wk1[2]; + union un_cmtw_cmwior CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +typedef struct st_temps +{ + union un_temps_tscr TSCR; +} st_temps_t; + +typedef struct st_tmr0 +{ + union un_tmr0_tcr TCR; + char wk0[1]; + union un_tmr0_tcsr TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union un_tmr0_tccr TCCR; + char wk5[1]; + union un_tmr0_tcstr TCSTR; +} st_tmr0_t; + +typedef struct st_tmr1 +{ + union un_tmr1_tcr TCR; + char wk0[1]; + union un_tmr1_tcsr TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union un_tmr1_tccr TCCR; + char wk5[1]; + union un_tmr1_tcstr TCSTR; +} st_tmr1_t; + +typedef struct st_tmr01 +{ + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +} st_tmr01_t; + +typedef struct st_tpu0 +{ + union un_tpu0_nfcr NFCR; + char wk0[7]; + union un_tpu0_tcr TCR; + union un_tpu0_tmdr TMDR; + union un_tpu0_tiorh TIORH; + union un_tpu0_tiorl TIORL; + union un_tpu0_tier TIER; + union un_tpu0_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu0_t; + +typedef struct st_tpu1 +{ + char wk0[1]; + union un_tpu1_nfcr NFCR; + char wk1[22]; + union un_tpu1_tcr TCR; + union un_tpu1_tmdr TMDR; + union un_tpu1_tior TIOR; + char wk2[1]; + union un_tpu1_tier TIER; + union un_tpu1_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu1_t; + +typedef struct st_tpu2 +{ + union un_tpu2_nfcr NFCR; + char wk0[37]; + union un_tpu2_tcr TCR; + union un_tpu2_tmdr TMDR; + union un_tpu2_tior TIOR; + char wk1[1]; + union un_tpu2_tier TIER; + union un_tpu2_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu2_t; + +typedef struct st_tpu3 +{ + char wk0[1]; + union un_tpu3_nfcr NFCR; + char wk1[52]; + union un_tpu3_tcr TCR; + union un_tpu3_tmdr TMDR; + union un_tpu3_tiorh TIORH; + union un_tpu3_tiorl TIORL; + union un_tpu3_tier TIER; + union un_tpu3_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +} st_tpu3_t; + +typedef struct st_tpu4 +{ + union un_tpu4_nfcr NFCR; + char wk0[67]; + union un_tpu4_tcr TCR; + union un_tpu4_tmdr TMDR; + union un_tpu4_tior TIOR; + char wk1[1]; + union un_tpu4_tier TIER; + union un_tpu4_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu4_t; + +typedef struct st_tpu5 +{ + char wk0[1]; + union un_tpu5_nfcr NFCR; + char wk1[82]; + union un_tpu5_tcr TCR; + union un_tpu5_tmdr TMDR; + union un_tpu5_tior TIOR; + char wk2[1]; + union un_tpu5_tier TIER; + union un_tpu5_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +} st_tpu5_t; + +typedef struct st_tpua +{ + union un_tpua_tstr TSTR; + union un_tpua_tsyr TSYR; +} st_tpua_t; + +typedef struct st_usb +{ + union un_usb_dpusr0r DPUSR0R; + union un_usb_dpusr1r DPUSR1R; +} st_usb_t; + +typedef struct st_usb0 +{ + union un_usb0_syscfg SYSCFG; + char wk0[2]; + union un_usb0_syssts0 SYSSTS0; + char wk1[2]; + union un_usb0_dvstctr0 DVSTCTR0; + char wk2[10]; + union un_usb0_cfifo CFIFO; + char wk3[2]; + union un_usb0_d0fifo D0FIFO; + char wk4[2]; + union un_usb0_d1fifo D1FIFO; + char wk5[2]; + union un_usb0_cfifosel CFIFOSEL; + union un_usb0_cfifoctr CFIFOCTR; + char wk6[4]; + union un_usb0_d0fifosel D0FIFOSEL; + union un_usb0_d0fifoctr D0FIFOCTR; + union un_usb0_d1fifosel D1FIFOSEL; + union un_usb0_d1fifoctr D1FIFOCTR; + union un_usb0_intenb0 INTENB0; + union un_usb0_intenb1 INTENB1; + char wk7[2]; + union un_usb0_brdyenb BRDYENB; + union un_usb0_nrdyenb NRDYENB; + union un_usb0_bempenb BEMPENB; + union un_usb0_sofcfg SOFCFG; + char wk8[2]; + union un_usb0_intsts0 INTSTS0; + union un_usb0_intsts1 INTSTS1; + char wk9[2]; + union un_usb0_brdysts BRDYSTS; + union un_usb0_nrdysts NRDYSTS; + union un_usb0_bempsts BEMPSTS; + union un_usb0_frmnum FRMNUM; + union un_usb0_dvchgr DVCHGR; + union un_usb0_usbaddr USBADDR; + char wk10[2]; + union un_usb0_usbreq USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union un_usb0_dcpcfg DCPCFG; + union un_usb0_dcpmaxp DCPMAXP; + union un_usb0_dcpctr DCPCTR; + char wk11[2]; + union un_usb0_pipesel PIPESEL; + char wk12[2]; + union un_usb0_pipecfg PIPECFG; + char wk13[2]; + union un_usb0_pipemaxp PIPEMAXP; + union un_usb0_pipeperi PIPEPERI; + union un_usb0_pipe1ctr PIPE1CTR; + union un_usb0_pipe2ctr PIPE2CTR; + union un_usb0_pipe3ctr PIPE3CTR; + union un_usb0_pipe4ctr PIPE4CTR; + union un_usb0_pipe5ctr PIPE5CTR; + union un_usb0_pipe6ctr PIPE6CTR; + union un_usb0_pipe7ctr PIPE7CTR; + union un_usb0_pipe8ctr PIPE8CTR; + union un_usb0_pipe9ctr PIPE9CTR; + char wk14[14]; + union un_usb0_pipe1tre PIPE1TRE; + unsigned short PIPE1TRN; + union un_usb0_pipe2tre PIPE2TRE; + unsigned short PIPE2TRN; + union un_usb0_pipe3tre PIPE3TRE; + unsigned short PIPE3TRN; + union un_usb0_pipe4tre PIPE4TRE; + unsigned short PIPE4TRN; + union un_usb0_pipe5tre PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[44]; + union un_usb0_devadd0 DEVADD0; + union un_usb0_devadd1 DEVADD1; + union un_usb0_devadd2 DEVADD2; + union un_usb0_devadd3 DEVADD3; + union un_usb0_devadd4 DEVADD4; + union un_usb0_devadd5 DEVADD5; + char wk16[20]; + union un_usb0_physlew PHYSLEW; +} st_usb0_t; + +typedef struct st_wdt +{ + unsigned char WDTRR; + char wk0[1]; + union un_wdt_wdtcr WDTCR; + union un_wdt_wdtsr WDTSR; + union un_wdt_wdtrcr WDTRCR; +} st_wdt_t; + +typedef struct st_flashconst +{ + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +} st_flashconst_t; + +typedef struct st_tempsconst +{ + unsigned long TSCDR; +} st_tempsconst_t; + +typedef struct st_crc +{ + union un_crc_crccr CRCCR; + char wk0[3]; + union un_crc_crcdir CRCDIR; + union un_crc_crcdor CRCDOR; +} st_crc_t; + +typedef struct st_da +{ + unsigned short DADR0; + unsigned short DADR1; + union un_da_dacr DACR; + union un_da_dadpr DADPR; + union un_da_daadscr DAADSCR; + char wk0[1]; + union un_da_daampcr DAAMPCR; + char wk1[19]; + union un_da_daaswcr DAASWCR; + char wk2[17763]; + union un_da_daadusr DAADUSR; +} st_da_t; + +typedef struct st_doc +{ + union un_doc_docr DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +} st_doc_t; + +typedef struct st_mtu +{ + union un_mtu_toera TOERA; + char wk0[2]; + union un_mtu_tgcra TGCRA; + union un_mtu_tocr1a TOCR1A; + union un_mtu_tocr2a TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union un_mtu_titcr1a TITCR1A; + union un_mtu_titcnt1a TITCNT1A; + union un_mtu_tbtera TBTERA; + char wk4[1]; + union un_mtu_tdera TDERA; + char wk5[1]; + union un_mtu_tolbra TOLBRA; + char wk6[3]; + union un_mtu_titmra TITMRA; + union un_mtu_titcr2a TITCR2A; + union un_mtu_titcnt2a TITCNT2A; + char wk7[35]; + union un_mtu_twcra TWCRA; + char wk8[15]; + union un_mtu_tmdr2a TMDR2A; + char wk9[15]; + union un_mtu_tstra TSTRA; + union un_mtu_tsyra TSYRA; + union un_mtu_tcsystr TCSYSTR; + char wk10[1]; + union un_mtu_trwera TRWERA; + char wk11[1925]; + union un_mtu_toerb TOERB; + char wk12[3]; + union un_mtu_tocr1b TOCR1B; + union un_mtu_tocr2b TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union un_mtu_titcr1b TITCR1B; + union un_mtu_titcnt1b TITCNT1B; + union un_mtu_tbterb TBTERB; + char wk16[1]; + union un_mtu_tderb TDERB; + char wk17[1]; + union un_mtu_tolbrb TOLBRB; + char wk18[3]; + union un_mtu_titmrb TITMRB; + union un_mtu_titcr2b TITCR2B; + union un_mtu_titcnt2b TITCNT2B; + char wk19[35]; + union un_mtu_twcrb TWCRB; + char wk20[15]; + union un_mtu_twdr2b TMDR2B; + char wk21[15]; + union un_mtu_tstrb TSTRB; + union un_mtu_tsyrb TSYRB; + char wk22[2]; + union un_mtu_trwerb TRWERB; +} st_mtu_t; + +typedef struct st_mtu0 +{ + union un_mtu0_nfcro NFCRO; + char wk0[8]; + union un_mtu0_nfcrc NFCRC; + char wk1[102]; + union un_mtu0_tcr TCR; + union un_mtu0_tmdr1 TMDR1; + union un_mtu0_tiorh TIORH; + union un_mtu0_tiorl TIOR1; + union un_mtu0_tier TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union un_mtu0_tier2 TIER2; + char wk4[1]; + union un_mtu0_tbtm TBTM; + char wk5[1]; + union un_mtu0_tcr2 TCR2; +} st_mtu0_t; + +typedef struct st_mtu1 +{ + char wk0[1]; + union un_mtu1_nfcr1 NFCR1; + char wk1[238]; + union un_mtu1_tcr TCR; + union un_mtu1_tmdr1 TMDR1; + union un_mtu1_tior TIOR; + char wk2[1]; + union un_mtu1_tier TIER; + union un_mtu1_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union un_mtu1_ticcr TICCR; + union un_mtu1_tmdr3 TMDR3; + char wk4[2]; + union un_mtu1_tcr2 TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +} st_mtu1_t; + +typedef struct st_mtu2 +{ + union un_mtu2_nfcr2 NFCR2; + char wk0[365]; + union un_mtu2_tcr TCR; + union un_mtu2_tmdr1 TMDR1; + union un_mtu2_tior TIOR; + char wk1[1]; + union un_mtu2_tier TIER; + union un_mtu2_tsr TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union un_mtu2_tcr2 TCR2; +} st_mtu2_t; + +typedef struct st_mtu3 +{ + union un_mtu3_tcr TCR; + char wk0[1]; + union un_mtu3_tmdr1 TMDR1; + char wk1[1]; + union un_mtu3_tiorh TIORH; + union un_mtu3_tiorl TIORL; + char wk2[2]; + union un_mtu3_tier TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union un_mtu3_tsr TSR; + char wk7[11]; + union un_mtu3_tbtm TBTM; + char wk8[19]; + union un_mtu3_tcr2 TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union un_mtu3_nfcr3 NFCR3; +} st_mtu3_t; + +typedef struct st_iwdt +{ + unsigned char IWDTRR; + char wk0[1]; + union un_iwdt_iwdtcr IWDTCR; + union un_iwdt_iwdtsr IWDTSR; + union un_iwdt_iwdtrcr IWDTRCR; + char wk1[1]; + union un_iwdt_iwdtcstpr IWDTCSTPR; +} st_iwdt_t; + +typedef struct st_mpu +{ + union un_mpu_rspage0 RSPAGE0; + union un_mpu_repage0 REPAGE0; + union un_mpu_rspage1 RSPAGE1; + union un_mpu_repage1 REPAGE1; + union un_mpu_rspage2 RSPAGE2; + union un_mpu_repage2 REPAGE2; + union un_mpu_rspage3 RSPAGE3; + union un_mpu_repage3 REPAGE3; + union un_mpu_rspage4 RSPAGE4; + union un_mpu_repage4 REPAGE4; + union un_mpu_rspage5 RSPAGE5; + union un_mpu_repage5 REPAGE5; + union un_mpu_rspage6 RSPAGE6; + union un_mpu_repage6 REPAGE6; + union un_mpu_rspage7 RSPAGE7; + union un_mpu_repage7 REPAGE7; + char wk0[192]; + union un_mpu_mpen MPEN; + union un_mpu_mpbac MPBAC; + union un_mpu_mpeclr MPECLR; + union un_mpu_mpests MPESTS; + char wk1[4]; + union un_mpu_mpdea MPDEA; + char wk2[8]; + union un_mpu_mpsa MPSA; + union un_mpu_mpops MPOPS; + union un_mpu_mpopi MPOPI; + union un_mpu_mhiti MHITI; + union un_mpu_mhitd MHITD; +} st_mpu_t; + +typedef struct st_mmcif +{ + union un_mmcif_cecmdset CECMDSET; + char wk0[4]; + union un_mmcif_cearg CEARG; + union un_mmcif_ceargcmd12 CEARGCMD12; + union un_mmcif_cecmdctrl CECMDCTR1; + union un_mmcif_ceblockset CEBLOCKSET; + union un_mmcif_ceclkctrl CECLKCTRL; + union un_mmcif_cebufacc CEBUFACC; + unsigned long CERESP3; + unsigned long CERESP2; + unsigned long CERESP1; + unsigned long CERESP0; + union un_mmcif_cerespcmd12 CERESPCMD12; + union un_mmcif_cedata CEDATA; + char wk1[4]; + union un_mmcif_ceboot CEBOOT; + union un_mmcif_ceint CEINT; + union un_mmcif_ceinten CEINTEN; + union un_mmcif_cehoststs1 CEHOSTSTS1; + union un_mmcif_cehoststs2 CEHOSTSTS2; + char wk2[32]; + union un_mmcif_cedetect CEDETECT; + union un_mmcif_ceaddmode CEADDMODE; + char wk3[4]; + union un_mmcif_ceversion CEVERSION; +} st_mmcif_t; + +typedef struct st_glcdc +{ + union un_glcdc_gr1clut0 GR1CLUT0[256]; + union un_glcdc_gr1clut1 GR1CLUT1[256]; + union un_glcdc_gr2clut0 GR2CLUT0[256]; + union un_glcdc_gr2clut1 GR2CLUT1[256]; + union un_glcdc_bgen BGEN; + union un_glcdc_bgperi BGPERI; + union un_glcdc_bgsync BGSYNC; + union un_glcdc_bgvsize BGVSIZE; + union un_glcdc_bghsize BGHSIZE; + union un_glcdc_bgcolor BGCOLOR; + union un_glcdc_bgmon BGMON; + char wk0[228]; + union un_glcdc_gr1ven GR1VEN; + union un_glcdc_grlflmrd GR1FLMRD; + char wk1[4]; + unsigned long GR1FLM2; + union un_glcdc_gr1flm3 GR1FLM3; + char wk2[4]; + union un_glcdc_gr1flm5 GR1FLM5; + union un_glcdc_gr1flm6 GR1FLM6; + union un_glcdc_gr1ab1 GR1AB1; + union un_glcdc_gr1ab2 GR1AB2; + union un_glcdc_gr1ab3 GR1AB3; + union un_glcdc_gr1ab4 GR1AB4; + union un_glcdc_gr1ab5 GR1AB5; + union un_glcdc_gr1ab6 GR1AB6; + union un_glcdc_gr1ab7 GR1AB7; + union un_glcdc_gr1ab8 GR1AB8; + union un_glcdc_gr1ab9 GR1AB9; + char wk3[8]; + union un_glcdc_gr1base GRBASE; + union un_glcdc_gr1clutint GR1CLUTINT; + union un_glcdc_gr1mon GR1MON; + char wk4[168]; + union un_glcdc_gr2ven GR2VEN; + union un_glcdc_gr2flmrd GR2FLMRD; + char wk5[4]; + unsigned long GR2FLM2; + union un_glcdc_gr2flm3 GR2FLM3; + char wk6[4]; + union un_glcdc_gr2flm5 GR2FLM5; + union un_glcdc_gr2flm6 GR2FLM6; + union un_glcdc_gr2ab1 GR2AB1; + union un_glcdc_gr2ab2 GR2AB2; + union un_glcdc_gr2ab3 GR2AB3; + union un_glcdc_gr2ab4 GR2AB4; + union un_glcdc_gr2ab5 GR2AB5; + union un_glcdc_gr2ab6 GR2AB6; + union un_glcdc_gr2ab7 GR2AB7; + union un_glcdc_gr2ab8 GR2AB8; + union un_glcdc_gr2ab9 GR2AB9; + char wk7[8]; + union un_glcdc_gr2base GR2BASE; + union un_glcdc_gr2clutint GR2CLUTINT; + union un_glcdc_gr2mon GR2MON; + char wk8[168]; + union un_glcdc_gamgven GAMGVEN; + union un_glcdc_gamsw GAMSW; + union un_glcdc_gamglut1 GAMGLUT1; + union un_glcdc_gamglut2 GAMGLUT2; + union un_glcdc_gamglut3 GAMGLUT3; + union un_glcdc_gamglut4 GAMGLUT4; + union un_glcdc_gamglut5 GAMGLUT5; + union un_glcdc_gamglut6 GAMGLUT6; + union un_glcdc_gamglut7 GAMGLUT7; + union un_glcdc_gamglut8 GAMGLUT8; + union un_glcdc_gamgarea1 GAMGAREA1; + union un_glcdc_gamgarea2 GAMGAREA2; + union un_glcdc_gamgarea3 GAMGAREA3; + union un_glcdc_gamgarea4 GAMGAREA4; + union un_glcdc_gamgarea5 GAMGAREA5; + char wk9[4]; + union un_glcdc_gambven GAMBVEN; + char wk10[4]; + union un_glcdc_gamblut1 GAMBLUT1; + union un_glcdc_gamblut2 GAMBLUT2; + union un_glcdc_gamblut3 GAMBLUT3; + union un_glcdc_gamblut4 GAMBLUT4; + union un_glcdc_gamblut5 GAMBLUT5; + union un_glcdc_gamblut6 GAMBLUT6; + union un_glcdc_gamblut7 GAMBLUT7; + union un_glcdc_gamblut8 GAMBLUT8; + union un_glcdc_gambarea1 GAMBAREA1; + union un_glcdc_gambarea2 GAMBAREA2; + union un_glcdc_gambarea3 GAMBAREA3; + union un_glcdc_gambarea4 GAMBAREA4; + union un_glcdc_gambarea5 GAMBAREA5; + char wk11[4]; + union un_glcdc_gamrven GAMRVEN; + char wk12[4]; + union un_glcdc_gamrlut1 GAMRLUT1; + union un_glcdc_gamrlut2 GAMRLUT2; + union un_glcdc_gamrlut3 GAMRLUT3; + union un_glcdc_gamrlut4 GAMRLUT4; + union un_glcdc_gamrlut5 GAMRLUT5; + union un_glcdc_gamrlut6 GAMRLUT6; + union un_glcdc_gamrlut7 GAMRLUT7; + union un_glcdc_gamrlut8 GAMRLUT8; + union un_glcdc_gamrarea1 GAMRAREA1; + union un_glcdc_gamrarea2 GAMRAREA2; + union un_glcdc_gamrarea3 GAMRAREA3; + union un_glcdc_gamrarea4 GAMRAREA4; + union un_glcdc_gamrarea5 GAMRAREA5; + char wk13[4]; + union un_glcdc_outven OUTVEN; + union un_glcdc_outset OUTSET; + union un_glcdc_bright1 BRIGHT1; + union un_glcdc_bright2 BRIGHT2; + union un_glcdc_contrast CONTRAST; + union un_glcdc_paneldtha PANELDTHA; + char wk14[12]; + union un_glcdc_clkphase CLKPHASE; + char wk15[28]; + union un_glcdc_tcontim TCONTIM; + union un_glcdc_tconstva1 TCONSTVA1; + union un_glcdc_tconstvat2 TCONSTVAT2; + union un_glcdc_tconstvb1 TCONSTVB1; + union un_glcdc_tconstvb2 TCONSTVB2; + union un_glcdc_tconstha1 TCONSTHA1; + union un_glcdc_tconstha2 TCONSTHA2; + union un_glcdc_tconsthb1 TCONSTHB1; + union un_glcdc_tconsthb2 TCONSTHB2; + union un_glcdc_tconde TCONDE; + char wk16[20]; + union un_glcdc_dtcten DTCTEN; + union un_glcdc_inten INTEN; + union un_glcdc_stclr STCLR; + union un_glcdc_stmon STMON; + union un_glcdc_panelclk PANELCLK; +} st_glcdc_t; + +typedef struct st_mtu4 +{ + char wk0[1]; + union un_mtu4_tcr TCR; + char wk1[1]; + union un_mtu4_tmdr1 TMDR1; + char wk2[2]; + union un_mtu4_tiorh TIORH; + union un_mtu4_tiorl TIORL; + char wk3[1]; + union un_mtu4_tier TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union un_mtu4_tsr TSR; + char wk8[11]; + union un_mtu4_tbtm TBTM; + char wk9[6]; + union un_mtu4_tadcr TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union un_mtu4_tcr2 TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union un_mtu4_nfcr4 NFCR4; +} st_mtu4_t; + +typedef struct st_mtu5 +{ + char wk0[1]; + union un_mtu5_nfcr5 NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union un_mtu5_tcru TCRU; + union un_mtu5_tcr2u TCR2U; + union un_mtu5_tioru TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union un_mtu5_tcrv TCRV; + union un_mtu5_tcr2v TCR2V; + union un_mtu5_tiorv TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union un_mtu5_tcrw TCRW; + union un_mtu5_tcr2w TCR2W; + union un_mtu5_tiorw TIORW; + char wk4[11]; + union un_mtu5_tier TIER; + char wk5[1]; + union un_mtu5_tstr TSTR; + char wk6[1]; + union un_mtu5_tcntcmpclr TCNTCMPCLR; +} st_mtu5_t; + +typedef struct st_smci0 +{ + union un_smcio_smr SMR; + unsigned char BRR; + union un_smcio_scr SCR; + unsigned char TDR; + union un_smcio_ssr SSR; + unsigned char RDR; + union un_smcio_smcr SMCR; +} st_smci0_t; + +typedef struct st_riic +{ + union un_riic_iccr1 ICCR1; + union un_riic_iccr2 ICCR2; + union un_riic_icmr1 ICMR1; + union un_riic_icmr2 ICMR2; + union un_riic_icmr3 ICMR3; + union un_riic_icfer ICFER; + union un_riic_icser ICSER; + union un_riic_icier ICIER; + union un_riic_icsr1 ICSR1; + union un_riic_icsr2 ICSR2; + union un_riic_sarl0 SARL0; + union un_riic_saru0 SARU0; + union un_riic_sarl1 SARL1; + union un_riic_saru1 SARU1; + union un_riic_sarl2 SARL2; + union un_riic_saru2 SARU2; + union un_riic_icbrl ICBRL; + union un_riic_icbrh ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +} st_riic_t; + +typedef struct st_rspi +{ + union un_rspi_spcr SPCR; + union un_rspi_sslp SSLP; + union un_rspi_sppcr SPPCR; + union un_rspi_spsr SPSR; + union un_rspi_spdr SPDR; + union un_rspi_spscr SPSCR; + union un_rspi_spssr SPSSR; + unsigned char SPBR; + union un_rspi_spdcr SPDCR; + union un_rspi_spckd SPCKD; + union un_rspi_sslnd SSLND; + union un_rspi_spnd SPND; + union un_rspi_spcr2 SPCR2; + union un_rspi_spcmd0 SPCMD0; + union un_rspi_spcmd1 SPCMD1; + union un_rspi_spcmd2 SPCMD2; + union un_rspi_spcmd3 SPCMD3; + union un_rspi_spcmd4 SPCMD4; + union un_rspi_spcmd5 SPCMD5; + union un_rspi_spcmd6 SPCMD6; + union un_rspi_spcmd7 SPCMD7; + union un_rspi_spdcr2 SPDCR2; +} st_rspi_t; + +typedef struct st_sdhi +{ + union un_sdhi_spcmd SPCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union un_sdhi_sdstop SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union un_sdhi_sdsts1 SDSTS1; + union un_sdhi_sdsts2 SDSTS2; + union un_sdhi_sdimsk1 SDIMSK1; + union un_sdhi_sdimsk2 SDIMSK2; + union un_sdhi_sdclkcr SDCLKCR; + union un_sdhi_sdsize SDSIZE; + union un_sdhi_sdopt SDOPT; + char wk6[4]; + union un_sdhi_sdersts1 SDERSTS1; + union un_sdhi_sdersts2 SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union un_sdhi_sdiomd SDIOMD; + union un_sdhi_sdiosts SDIOSTS; + union un_sdhi_sdioimsk SDIOIMSK; + char wk8[316]; + union un_sdhi_sddmaen SDDMAEN; + char wk9[12]; + union un_sdhi_sdrst SDRST; + union un_sdhi_sdver SDVER; + char wk10[24]; + union un_sdhi_sdswap SDSWAP; +} st_sdhi_t; + +typedef struct st_sdsi +{ + union un_sdsi_fn1accr FN1ACCR; + union un_sdsi_intencr1 INTENCR1; + union un_sdsi_intsr1 INTSR1; + union un_sdsi_sdcmdcr SDCMDCR; + union un_sdsi_sdcadd0r SDCADD0R; + union un_sdsi_sdcadd1r SDCADD1R; + union un_sdsi_sdcadd2r SDCADD2R; + union un_sdsi_sdsicr1 SDSICR1; + union un_sdsi_dmacr1 DMACR1; + union un_sdsi_blkcnt BLKCNT; + union un_sdsi_bytcnt BYTCNT; + union un_sdsi_dmatraddr DMATRADDR; + char wk0[236]; + union un_sdsi_sdsicr2 SDICR2; + union un_sdsi_sdsicr3 SDICR3; + union un_sdsi_intencr2 INTENCR2; + union un_sdsi_intsr2 INTSR2; + union un_sdsi_dmacr2 DMACR2; + char wk1[236]; + unsigned long CISDATAR[27]; + char wk2[4]; + union un_sdsi_fbr1 FBR1; + union un_sdsi_fbr2 FBR2; + union un_sdsi_fbr3 FBR3; + union un_sdsi_fbr4 FBR4; + union un_sdsi_fbr5 FBR5; + char wk3[1404]; + union un_sdsi_fn1datar1 FN1DATAR1[64]; + union un_sdsi_fn1datar2 FN1DATAR2[64]; + union un_sdsi_fn1datar3 FN1DATAR3[64]; + union un_sdsi_fn1intvecr FN1INTVECR; + union un_sdsi_fn1intclrr FN1INTCLRR; + char wk4[254]; + union un_sdsi_fn1datar5 FN1DATAR5[256]; +} st_sdsi_t; + +typedef struct st_mtu6 +{ + union un_mtu6_tcr TCR; + char wk0[1]; + union un_mtu6_tmdr1 TMDR1; + char wk1[1]; + union un_mtu6_tiorh TIORH; + union un_mtu6_tiorl TIORL; + char wk2[2]; + union un_mtu6_tier TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union un_mtu6_tsr TSR; + char wk7[11]; + union un_mtu6_tbtm TBTM; + char wk8[19]; + union un_mtu6_tcr2 TCR2; + char wk9[3]; + union un_mtu6_tsycr TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; +} st_mtu6_t; + +typedef struct st_mtu7 +{ + char wk0[1]; + union un_mtu7_tcr TCR; + char wk1[1]; + union un_mtu7_tmdr1 TMDR1; + char wk2[2]; + union un_mtu7_tiorh TIORH; + union un_mtu7_tiorl TIORL; + char wk3[1]; + union un_mtu7_tier TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union un_mtu7_tsr TSR; + char wk8[11]; + union un_mtu7_tbtm TBTM; + char wk9[6]; + union un_mtu7_tadcr TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union un_mtu7_tcr2 TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union un_mtu7_nfcr7 NFCR7; +} st_mtu7_t; + +typedef struct st_mtu8 +{ + union un_mtu8_nfcr8 NFCR8; + char wk0[871]; + union un_mtu8_tcr TCR; + union un_mtu8_tmdr1 TMDR1; + union un_mtu8_tiorh TIORH; + union un_mtu8_tiorl TIORL; + union un_mtu8_tier TIER; + char wk1[1]; + union un_mtu8_tcr2 TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +} st_mtu8_t; + +typedef struct st_port6 +{ + union un_port6_pdr PDR; + char wk0[31]; + union un_port6_podr PODR; + char wk1[31]; + union un_port6_pidr PIDR; + char wk2[31]; + union un_port6_pmr PMR; + char wk3[37]; + union un_port6_ord0 ORD0; + union un_port6_ord1 ORD1; + char wk4[56]; + union un_port6_pcr PCR; +} st_port6_t; + +typedef struct st_dmac +{ + union un_dmac_dmast DMAST; + char wk0[3]; + union un_dmac_dmist DMIST; +} st_dmac_t; + +typedef struct st_dmac0 +{ + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union un_dmac0_dmtmd DMTMD; + char wk1[1]; + union un_dmac0_dmint DMINT; + union un_dmac0_dmamd DMAMD; + char wk2[2]; + unsigned long DMOFR; + union un_dmac0_dmcnt DMCNT; + union un_dmac0_dmreq DMREQ; + union un_dmac0_dmsts DMSTS; + union un_dmac0_dmcsl DMCSL; +} st_dmac0_t; + +typedef struct st_dmac1 +{ + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union un_dmac1_dmtmd DMTMD; + char wk1[1]; + union un_dmac1_dmint DMINT; + union un_dmac1_dmamd DMAMD; + char wk2[6]; + union un_dmac1_dmcnt DMCNT; + union un_dmac1_dmreq DMREQ; + union un_dmac1_dmsts DMSTS; + union un_dmac1_dmcsl DMCSL; +} st_dmac1_t; + +typedef struct st_drw2d +{ + union + { + union un_drw2d_control CONTROL; + union un_drw2d_status STATUS; + }; + union + { + union un_drw2d_control2 CONTROL2; + union un_drw2d_hwver HWVER; + }; + char wk0[8]; + unsigned long L1START; + unsigned long L2START; + unsigned long L3START; + unsigned long L4START; + unsigned long L5START; + unsigned long L6START; + unsigned long L1XADD; + unsigned long L2XADD; + unsigned long L3XADD; + unsigned long L4XADD; + unsigned long L5XADD; + unsigned long L6XADD; + unsigned long L1YADD; + unsigned long L2YADD; + unsigned long L3YADD; + unsigned long L4YADD; + unsigned long L5YADD; + unsigned long L6YADD; + unsigned long L1BAND; + unsigned long L2BAND; + char wk1[4]; + union un_drw2d_color1 COLOR1; + union un_drw2d_color2 COLOR2; + char wk2[8]; + unsigned long PATTERN; + union un_drw2d_size SIZE; + union un_drw2d_pitch PITCH; + unsigned long ORIGIN; + char wk3[12]; + unsigned long LUST; + unsigned long LUXADD; + unsigned long LUYADD; + unsigned long LVSTI; + unsigned long LVSTF; + unsigned long LVXADDI; + unsigned long LVYADDI; + union un_drw2d_lvyxaddf LVYXADDF; + char wk4[4]; + unsigned long TEXPITCH; + union un_drw2d_texmsk TEXMSK; + unsigned long TEXORG; + union un_drw2d_irqctl IRQCTL; + union un_drw2d_cachectl CACHECTL; + unsigned long DLISTST; + unsigned long PERFCNT1; + unsigned long PERFCNT2; + union un_drw2d_perftrg PERFTRG; + char wk5[4]; + unsigned long TEXCLADDR; + unsigned long TEXCLDATA; + unsigned long TEXCLOFST; + union un_drw2d_colkey COLKEY; +} st_drw2d_t; + +typedef struct st_dtc +{ + union un_dtc_dtccr DTCCR; + char wk0[3]; + void *DTCVBR; + union un_dtc_dtcadmod DTCADMOD; + char wk1[3]; + union un_dtc_dtcst DTCST; + char wk2[1]; + union un_dtc_dtcsts DTCSTS; + void *DTCIBR; + union un_dtc_dtcor DTCOR; + char wk3[1]; + union un_dtc_dtcsqe DTCSQE; + unsigned long DTCDISP; +} st_dtc_t; + +typedef struct st_edmac +{ + union un_edmac_edmr EMDR; + char wk0[4]; + union un_edmac_edtrr EDTRR; + char wk1[4]; + union un_edmac_edrrr EDRRR; + char wk2[4]; + void *TDLAR; + char wk3[4]; + void *RDLAR; + char wk4[4]; + union un_edmac_eesr EESR; + char wk5[4]; + union un_edmac_eesipr EESIPR; + char wk6[4]; + union un_edmac_trscer TRSCER; + char wk7[4]; + union un_edmac_rmfcr RMFCR; + char wk8[4]; + union un_edmac_tftr TFTR; + char wk9[4]; + union un_edmac_fdr FDR; + char wk10[4]; + union un_edmac_rmcr RMCR; + char wk11[8]; + union un_edmac_tfucr TFUCR; + union un_edmac_rfocr RFOCR; + union un_edmac_iosr IOSR; + union un_edmac_fcftr FCFTR; + char wk12[4]; + union un_edmac_rpadir RPADIR; + union un_edmac_trimd TRIMD; + char wk13[72]; + void *RBWAR; + void *RDFAR; + char wk14[4]; + void *TBRAR; + void *TDFAR; +} st_edmac_t; + +typedef struct st_elc +{ + union un_elc_elcr ELCR; + union un_elc_elsr0 ELSR0; + char wk0[2]; + union un_elc_elsr3 ELSR3; + union un_elc_elsr4 ELSR4; + char wk1[2]; + union un_elc_elsr7 ELSR7; + char wk2[2]; + union un_elc_elsr10 ELSR10; + union un_elc_elsr11 ELSR11; + union un_elc_elsr12 ELSR12; + union un_elc_elsr13 ELSR13; + char wk3[1]; + union un_elc_elsr15 ELSR15; + union un_elc_elsr16 ELSR16; + char wk4[1]; + union un_elc_elsr18 ELSR18; + union un_elc_elsr19 ELSR19; + union un_elc_elsr20 ELSR20; + union un_elc_elsr21 ELSR21; + union un_elc_elsr22 ELSR22; + union un_elc_elsr23 ELSR23; + union un_elc_elsr24 ELSR24; + union un_elc_elsr25 ELSR25; + union un_elc_elsr26 ELSR26; + union un_elc_elsr27 ELSR27; + union un_elc_elsr28 ELSR28; + char wk5[1]; + union un_elc_elopa ELOPA; + union un_elc_elopb ELOPB; + union un_elc_elopc ELOPC; + union un_elc_elopd ELOPD; + union un_elc_pgr1 PGR1; + union un_elc_pgr2 PGR2; + union un_elc_pgc1 PGC1; + union un_elc_pgc2 PGC2; + union un_elc_pdbf1 PDBF1; + union un_elc_pdbf2 PDBF2; + union un_elc_pel0 PEL0; + union un_elc_pel1 PEL1; + union un_elc_pel2 PEL2; + union un_elc_pel3 PEL3; + union un_elc_elsegr ELSEGR; + char wk6[3]; + union un_elc_elsr33 ELSR33; + char wk7[1]; + union un_elc_elsr35 ELSR35; + union un_elc_elsr36 ELSR36; + union un_elc_elsr37 ELSR37; + union un_elc_elsr38 ELSR38; + char wk8[6]; + union un_elc_elsr45 ELSR45; + char wk9[1]; + union un_elc_elopf ELOPF; + char wk10[1]; + union un_elc_eloph ELOPH; +} st_elc_t; + +typedef struct st_etherc +{ + union un_etherc_ecmr EMCR; + char wk0[4]; + union un_etherc_rflr RFLR; + char wk1[4]; + union un_etherc_ecsr ECSR; + char wk2[4]; + union un_etherc_ecsipr ECSIPR; + char wk3[4]; + union un_etherc_pir PIR; + char wk4[4]; + union un_etherc_psr PSR; + char wk5[20]; + union un_etherc_rdmlr RDMLR; + char wk6[12]; + union un_etherc_ipgr IPGR; + union un_etherc_apr APR; + union un_etherc_mpr MPR; + char wk7[4]; + union un_etherc_rfcf RFCF; + union un_etherc_tpauser TPAUSER; + union un_etherc_tpausecr TPAUSECR; + union un_etherc_bcfrr BCFRR; + char wk8[80]; + unsigned long MAHR; + char wk9[4]; + union un_etherc_malr MALR; + char wk10[4]; + unsigned long TROCR; + unsigned long CDCR; + unsigned long LCCR; + unsigned long CNDCR; + char wk11[4]; + unsigned long CEFCR; + unsigned long FRECR; + unsigned long TSFRCR; + unsigned long TLFRCR; + unsigned long RFCR; + unsigned long MAFCR; +} st_etherc_t; + +typedef struct st_exdmac +{ + union un_exdmac_edmast EDMAST; + char wk0[479]; + unsigned long CLSBR0; + unsigned long CLSBR1; + unsigned long CLSBR2; + unsigned long CLSBR3; + unsigned long CLSBR4; + unsigned long CLSBR5; + unsigned long CLSBR6; + unsigned long CLSBR7; +} st_exdmac_t; + +typedef struct st_exdmac0 +{ + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union un_exdmac0_edmtmd EDMTMD; + union un_exdmac0_edmomd EDMOMD; + union un_exdmac0_edmint EDMINT; + union un_exdmac0_edmamd EDMAMD; + unsigned long EDMOFR; + union un_exdmac0_edmcnt EDMCNT; + union un_exdmac0_edmreq EDMREQ; + union un_exdmac0_edmsts EDMSTS; + char wk1[1]; + union un_exdmac0_edmrmd EDMRMD; + union un_exdmac0_edmerf EDMERF; + union un_exdmac0_edmprf EDMPRF; +} st_exdmac0_t; + +typedef struct st_exdmac1 +{ + void *EDMSAR; + void *EDMDAR; + unsigned long EDMCRA; + unsigned short EDMCRB; + char wk0[2]; + union un_exdmac1_edmtmd EDMTMD; + union un_exdmac1_edmomd EDMOMD; + union un_exdmac1_edmint EDMINT; + union un_exdmac1_edmamd EDMAMD; + char wk1[4]; + union un_exdmac1_edmcnt EDMCNT; + union un_exdmac1_edmreq EDMREQ; + union un_exdmac1_edmsts EDMSTS; + char wk2[1]; + union un_exdmac1_edmrmd EDMRMD; + union un_exdmac1_edmerf EDMERF; + union un_exdmac1_edmprf EDMPRF; +} st_exdmac1_t; + +typedef struct st_flash +{ + union un_flash_romce ROMCE; + char wk0[2]; + union un_flash_romciv ROMCIV; + char wk1[45712]; + union un_flash_fwepror FWEPROR; + char wk2[7798185]; + unsigned char EEPFCLK; + char wk3[8143]; + union un_flash_fastat FASTAT; + char wk4[3]; + union un_flash_faeint FAEINT; + char wk5[3]; + union un_flash_frdyie FRDYIE; + char wk6[23]; + union un_flash_fsaddr FSADDR; + union un_flash_feaddr FEADDR; + char wk7[72]; + union un_flash_fstatr FSTATR; + union un_flash_fentryr FENTRYR; + char wk8[6]; + union un_flash_fsunitr FSUNITR; + char wk9[18]; + union un_flash_fcmdr FCMDR; + char wk10[46]; + union un_flash_fbccnt FBCCNT; + char wk11[3]; + union un_flash_fbcstat FBCSTAT; + char wk12[3]; + union un_flash_fpsaddr FPSADDR; + union un_flash_fawmon FAWMON; + union un_flash_fcpsr FCPSR; + char wk13[2]; + union un_flash_fpckar FPCKAR; + char wk14[2]; + union un_flash_fsuacr FSUACR; +} st_flash_t; + +typedef struct st_pdc +{ + union un_pdc_pccr0 PCCR0; + union un_pdc_pccr1 PCCR1; + union un_pdc_pcsr PCSR; + union un_pdc_pcmonr PCMONR; + union un_pdc_pcdr PCDR; + union un_pdc_vcr VCR; + union un_pdc_hcr HCR; +} st_pdc_t; + +typedef struct st_poe +{ + union un_poe_icsr1 ICSR1; + union un_poe_ocsr1 OCSR1; + union un_poe_icsr2 ICSR2; + union un_poe_ocsr2 OCSR2; + union un_poe_icsr3 ICSR3; + union un_poe_spoer SPOER; + union un_poe_poecr1 POECR1; + union un_poe_poecr2 POECR2; + char wk0[2]; + union un_poe_poecr4 POECR4; + union un_poe_poecr5 POECR5; + char wk1[2]; + union un_poe_icsr4 ICSR4; + union un_poe_icsr5 ICSR5; + union un_poe_alr1 ALR1; + union un_poe_icsr6 ICSR6; + char wk2[6]; + union un_poe_m0selr1 M0SELR1; + union un_poe_m0selr2 M0SELR2; + union un_poe_m3selr M3SELR; + union un_poe_m4selr1 M4SELR1; + union un_poe_m4selr2 M4SELR2; + char wk3[1]; + union un_poe_m6selr M6SELR; +} st_poe_t; + +typedef struct st_portd +{ + union un_portd_pdr PDR; + union un_portd_podr PODR; + union un_portd_pidr PIDR; + union un_portd_pmr PMR; + union un_portd_ord0 ORD0; + union un_portd_ord1 ORD1; + union un_portd_pcr PCR; + union un_portd_dscr DSCR; + union un_portd_dscr2 DSCR2; + char wk0[31]; + char wk1[31]; + char wk2[31]; + char wk3[44]; + char wk4[49]; + char wk5[31]; + char wk6[71]; +} st_portd_t; + +typedef struct st_ppg0 +{ + union un_ppg0_pcr PCR; + union un_ppg0_pmr OMR; + union un_ppg0_nderh NDERH; + union un_ppg0_nderl NDERL; + union un_ppg0_podrh PODRH; + union un_ppg0_podrl PODRL; + union un_ppg0_ndrh NDRH; + union un_ppg0_ndrl NDRL; + union un_ppg0_ndrh2 NDRH2; + union un_ppg0_ndrl2 NDRL2; +} st_ppg0_t; + +typedef struct st_ppg1 +{ + union un_ppg1_ptrslr PTRSLR; + char wk0[5]; + union un_ppg1_pcr PCR; + union un_ppg1_pmr PMR; + union un_ppg1_nderh NDERH; + union un_ppg1_nderl NDERL; + union un_ppg1_podrh PODRH; + union un_ppg1_podrl PODRL; + union un_ppg1_ndrh NDRH; + union un_ppg1_ndrl NDRL; + union un_ppg1_ndrh2 NDRH2; + union un_ppg1_ndrl2 NDRL2; +} st_ppg1_t; + +typedef struct st_qspi +{ + union un_qspi_spcr SPCR; + union un_qspi_sslp SSLP; + union un_qspi_sppcr SPPCR; + union un_qspi_spsr SPSR; + union un_qspi_spdr SPDR; + union un_qspi_spscr SPSCR; + union un_qspi_spssr SPSSR; + union un_qspi_spbr SPBR; + union un_qspi_spdcr SPDCR; + union un_qspi_spckd SPCKD; + union un_qspi_sslnd SSLND; + union un_qspi_spnd SPND; + char wk0[1]; + union un_qspi_spcmd0 SPCMD0; + union un_qspi_spcmd1 SPCMD1; + union un_qspi_spcmd2 SPCMD2; + union un_qspi_spcmd3 SPCMD3; + union un_qspi_spbfcr SPBFCR; + char wk1[1]; + union un_qspi_spbdcr SPBDCR; + unsigned long SPBMUL0; + unsigned long SPBMUL1; + unsigned long SPBMUL2; + unsigned long SPBMUL3; +} st_qspi_t; + +typedef struct st_ram +{ + union un_ram_rammode RAMMODE; + union un_ram_ramsts RAMSTS; + char wk0[2]; + union un_ram_ramprcr RAMPRCR; + char wk1[3]; + union un_ram_ramecad RAMECAD; + char wk2[52]; + union un_ram_exrammode EXRAMMODE; + union un_ram_exramsts EXRAMSTS; + char wk3[2]; + union un_ram_exramprcr EXRAMPRCR; + char wk4[3]; + union un_ram_exramecad EXRAMECAD; +} st_ram_t; + +typedef struct st_s12ad +{ + union un_s12ad_adcsr ADCSR; + char wk0[2]; + union un_s12ad_adansa0 ADANSA0; + char wk1[2]; + union un_s12ad_adads0 ADADS0; + char wk2[2]; + union un_s12ad_adadc ADADC; + char wk3[1]; + union un_s12ad_adcer ADCER; + union un_s12ad_adstrgr ADSTRGR; + char wk4[2]; + union un_s12ad_adansb0 ADANSB0; + char wk5[2]; + union un_s12ad_addbldr ADDBLDR; + char wk6[4]; + union un_s12ad_adrd ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk7[51]; + union un_s12ad_adsampr ADSAMPR; + char wk8[2]; + union un_s12ad_adshcr ADSHCR; + char wk9[6]; + union un_s12ad_adsam ADSAM; + char wk10[10]; + union un_s12ad_addiscr ADDISCR; + char wk11[1]; + union un_s12ad_adshmsr ADSHMSR; + char wk12[3]; + union un_s12ad_adgspcr ADGSPCR; + char wk13[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk14[4]; + union un_s12ad_adwinmon ADWINMON; + char wk15[3]; + union un_s12ad_adcmpcr ADCMPCR; + char wk16[2]; + union un_s12ad_adcmpansr0 ADCMPANSR0; + char wk17[2]; + union un_s12ad_adcmplr0 ADCMPLR0; + char wk18[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union un_s12ad_adcmpsr0 ADCMPSR0; + char wk19[4]; + union un_s12ad_adcmpbnsr ADCMPBNSR; + char wk20[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union un_s12ad_adcmpbsr ADCMPBSR; + char wk21[39]; + union un_s12ad_adansc0 ADANSC0; + char wk22[3]; + union un_s12ad_adgctrgr ADGCTRGR; + char wk23[6]; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +} st_s12ad_t; + +typedef struct st_s12ad1 +{ + union un_s12ad1_adcsr ADCSR; + char wk0[2]; + union un_s12ad1_adansa0 ADANSA0; + union un_s12ad1_adansa1 ADANSA1; + union un_s12ad1_adads0 ADADSO; + union un_s12ad1_adads1 ADADS1; + union un_s12ad1_adadc ADADC; + char wk1[1]; + union un_s12ad1_adcer ADCER; + union un_s12ad1_adstrgr ADSTRGR; + union un_s12ad1_adexicr ADEXICR; + union un_s12ad1_adansb0 ADANSB0; + union un_s12ad1_adansb1 ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union un_s12ad1_adrd ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + char wk2[25]; + union un_s12ad1_adsampr ADSAMPR; + char wk3[10]; + union un_s12ad1_adsam ADSAM; + char wk4[10]; + union un_s12ad1_addiscr ADDISCR; + char wk5[5]; + union un_s12ad1_adgspcr ADGSPCR; + char wk6[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk7[4]; + union un_s12ad1_adwinmon ADWINMON; + char wk8[3]; + union un_s12ad1_adcmpcr ADCMPCR; + union un_s12ad1_adcmpanser ADCMPANSER; + union un_s12ad1_adcmpler ADCMPLER; + union un_s12ad1_adcmpansr0 ADCMPANSR0; + union un_s12ad1_adcmpansr1 ADCMPANSR1; + union un_s12ad1_adcmplr0 ADCMPLR0; + union un_s12ad1_adcmplr1 ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union un_s12ad1_adcmpsr0 ADCMPSR0; + union un_s12ad1_adcmpsr1 ADCMPSR1; + union un_s12ad1_adcmpser ADCMPSER; + char wk9[1]; + union un_s12ad1_adcmpbnsr ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union un_s12ad1_adcmpbsr ADCMPBSR; + char wk11[39]; + union un_s12ad1_adansc0 ADANSC0; + union un_s12ad1_adansc1 ADANSC1; + union un_s12ad1_adgcexcr ADGCEXCR; + union un_s12ad1_adgctrgr ADGCTRGR; + char wk12[3]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; + unsigned char ADSSTR8; + unsigned char ADSSTR9; + unsigned char ADSSTR10; + unsigned char ADSSTR11; + unsigned char ADSSTR12; + unsigned char ADSSTR13; + unsigned char ADSSTR14; + unsigned char ADSSTR15; +} st_s12ad1_t; + +#pragma pack() + +#endif /* __ASSEMBLER__ */ +#endif /* __ARCH_RH850_INCLUDE_U2BX_IODEFINE_H */ diff --git a/arch/rh850/include/u2bx/irq.h b/arch/rh850/include/u2bx/irq.h new file mode 100644 index 0000000000000000000000000000000000000000..897e7555441cac18867e15b03dafe6d5fd153e92 --- /dev/null +++ b/arch/rh850/include/u2bx/irq.h @@ -0,0 +1,171 @@ +/**************************************************************************** + * arch/renesas/include/u2bx/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_IRQ_H +#define __ARCH_RH850_INCLUDE_U2BX_IRQ_H + +#include +#include +#include + + + +#define RH850_NVECTORS (1024) +#define NR_IRQS (1024) + +#define RH850_PSW_ID_MASK (1<<5) + + +/* Register information */ +// RH850 G4MH +#define REG_FPEPC (0) +#define REG_FPSR (1) +#define REG_CTPC (2) +#define REG_CTPSW (3) +#define REG_EIIC (4) +#define REG_EIPC (5) +#define REG_EIPSW (6) +#define REG_LP (7) // << REG_R31 +#define REG_R2 (8) +#define REG_R1 (9) +#define REG_R30 (10) +#define REG_R29 (11) +#define REG_R28 (12) +#define REG_R27 (13) +#define REG_R26 (14) +#define REG_R25 (15) +#define REG_R24 (16) +#define REG_R23 (17) +#define REG_R22 (18) +#define REG_R21 (19) +#define REG_R20 (20) +#define REG_R19 (21) +#define REG_R18 (22) +#define REG_R17 (23) +#define REG_R16 (24) +#define REG_R15 (25) +#define REG_R14 (26) +#define REG_R13 (27) +#define REG_R12 (28) +#define REG_R11 (29) +#define REG_R10 (30) +#define REG_R9 (31) +#define REG_R8 (32) +#define REG_R7 (33) +#define REG_R6 (34) + + +#define REG_PC REG_EIPC + + +#define XCPTCONTEXT_REGS (35) +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + + +#ifndef __ASSEMBLY__ +struct xcptcontext +{ + /* Register save area */ + uint32_t * regs; +}; + +/* Name: up_irq_save, up_irq_restore, and friends. + * + * NOTE: This function should never be called from application code and, + * as a general rule unless you really know what you are doing, this + * function should not be called directly from operation system code either: + * Typically, the wrapper functions, enter_critical_section() and + * leave_critical section(), are probably what you really want. + */ + + +/* Return the current interrupt enable state and disable IRQs */ +int up_timer_value(clock_t *ticks); + +/* Return the current value of the stack pointer */ + +static inline uint32_t up_getsp(void) +{ + uint32_t sp; + + __asm__ volatile ( + "mov r3, %0" + : "=r"(sp) + : + : "memory" + ); + + return sp; +} + +/* Disable interrupts */ + +static inline void up_irq_disable(void) +{ + __DI(); +} + +/* Enable interrupts */ + +static inline void up_irq_enable(void) +{ + __EI(); +} + +/* Return the current interrupt enable state and disable interrupts */ +static inline uint32_t __getPSW() +{ + uint32_t result; + __asm__ volatile ("stsr 5, %0, 0" : "=r" (result) :: "memory"); + return result; +} +static inline irqstate_t up_irq_save(void) +{ + irqstate_t ret = (irqstate_t) (__getPSW() & RH850_PSW_ID_MASK); + ret = (ret >> 5); + up_irq_disable(); + return ret; +} + +/* Restore saved interrupt state */ +static inline void up_irq_restore(irqstate_t flags) +{ + if (0 == (flags)) + { + up_irq_enable(); + } + else + { + up_irq_disable(); + } +} +#endif /* __ASSEMBLY__ */ + +int up_timer_value(clock_t *ticks); + + +/**************************************************************************** + * Name: up_getusrpc + ****************************************************************************/ + +#define up_getusrpc(regs) \ + (((uint32_t *)((regs) ? (regs) : up_current_regs()))[REG_PC]) + +#endif /* __ARCH_RH850_INCLUDE_U2BX_IRQ_H */ \ No newline at end of file diff --git a/arch/rh850/include/u2bx/limits.h b/arch/rh850/include/u2bx/limits.h new file mode 100644 index 0000000000000000000000000000000000000000..06bde71f6441f07adaec5e0c16fed32fad6dcdef --- /dev/null +++ b/arch/rh850/include/u2bx/limits.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/limits.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_LIMITS_H +#define __ARCH_RH850_INCLUDE_U2BX_LIMITS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +# define CHAR_MIN 0 +# define CHAR_MAX UCHAR_MAX +#else +# define CHAR_MIN SCHAR_MIN +# define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +/* On SH-1, type 'int' is 32-bits */ + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* On SH-1, type 'long' is the same size as type 'int', 32-bits */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#if !defined(__WCHAR_TYPE__) +# define WCHAR_MIN INT_MIN +# define WCHAR_MAX INT_MAX +#elif defined(__WCHAR_UNSIGNED__) +# define WCHAR_MIN 0 +# define WCHAR_MAX __WCHAR_MAX__ +#else +# define WCHAR_MIN (-__WCHAR_MAX__ - 1) +# define WCHAR_MAX __WCHAR_MAX__ +#endif + +#endif /* __ARCH_RH850_INCLUDE_U2BX_LIMITS_H */ diff --git a/arch/rh850/include/u2bx/types.h b/arch/rh850/include/u2bx/types.h new file mode 100644 index 0000000000000000000000000000000000000000..38cbeaf12eb5189aef24d53408513adeb80596e5 --- /dev/null +++ b/arch/rh850/include/u2bx/types.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/types.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through sys/types.h + */ + +#ifndef __ARCH_RH850_INCLUDE_U2BX_TYPES_H +#define __ARCH_RH850_INCLUDE_U2BX_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed long _int32_t; +typedef unsigned long _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + +#if defined(__WCHAR_TYPE__) +typedef __WCHAR_TYPE__ _wchar_t; +#else +typedef int _wchar_t; +#endif + +typedef int _wint_t; +typedef int _wctype_t; + +/* A size is 4 bytes */ + +#if defined(__SIZE_TYPE__) +/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t. + * We simply change "unsigned" to "signed" for this single definition + * to make sure ssize_t and size_t only differ by their signedness. + */ + +#define unsigned signed +typedef __SIZE_TYPE__ _ssize_t; +#undef unsigned +typedef __SIZE_TYPE__ _size_t; +#elif defined(CONFIG_ARCH_SIZET_LONG) +typedef signed long _ssize_t; +typedef unsigned long _size_t; +#else +typedef signed int _ssize_t; +typedef unsigned int _size_t; +#endif + +/* This is the size of the interrupt state save returned by + * up_irq_save() + */ + +typedef unsigned long irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RH850_INCLUDE_U2BX_TYPES_H */ diff --git a/arch/rh850/src/CMakeLists.txt b/arch/rh850/src/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..4bd53058127da3f32463d562f927ae76869912f0 --- /dev/null +++ b/arch/rh850/src/CMakeLists.txt @@ -0,0 +1,33 @@ +# ############################################################################## +# arch/arm/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${ARCH_SUBDIR}) +add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) +add_subdirectory(common) + +# Include directories (before system ones) as PUBLIC so that it can be exposed +# to libboard +target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common + ${ARCH_SUBDIR} + ${ARCH_SUBDIR}/Core/Include/G4-profile + ${ARCH_SUBDIR}/Core/Include + ${ARCH_SUBDIR}/Core/Template/RH850/Include + ${ARCH_SUBDIR}/Core/Template/RH850/Config + ) \ No newline at end of file diff --git a/arch/rh850/src/Makefile b/arch/rh850/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..4f01aade57c73d8ea8147e7448106a68bb2d9cc9 --- /dev/null +++ b/arch/rh850/src/Makefile @@ -0,0 +1,168 @@ +############################################################################ +# arch/rh850/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/tools/Make.defs +include chip/Make.defs + +ifeq ($(CONFIG_ARCH_CHIP_U2B24E),y) # g4x +ARCH_SUBDIR = g4x +endif +ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR) +INCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)sched + +CPPFLAGS += $(INCLUDES) +CFLAGS += $(INCLUDES) +CXXFLAGS += $(INCLUDES) +AFLAGS += $(INCLUDES) + +NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT)) + +HEAD_OBJ = $(HEAD_ASRC:.850=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_OBJ) + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) + +ifeq ($(CONFIG_ARCH_CHIP_RH850),y) +AOBJS = $(CHIP_ASRCS:.850=$(OBJEXT)) +else +AOBJS = $(CHIP_ASRCS:.850=$(OBJEXT)) +endif + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + + +# Override in Make.defs if linker is not 'ld' + +LDSTARTGROUP ?= --start-group +LDENDGROUP ?= --end-group +LDFLAGS += $(addprefix -T,$(call CONVERT_PATH,$(ARCHSCRIPT))) + +BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) + +LIBPATHS += -L $(call CONVERT_PATH,$(TOPDIR)$(DELIM)staging) +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L $(call CONVERT_PATH,$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board) +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif +# Add the builtin library + +EXTRA_LIBS += ${shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name} + +ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) + EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a}} +endif + +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) + EXTRA_LIBS += ${wildcard ${shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a}} +endif + +VPATH = chip:common +VPATH += $(ARCH_SUBDIR) +all: $(HEAD_OBJ) libarch$(LIBEXT) + +.PHONY: board/libboard$(LIBEXT) + +ifeq ($(CONFIG_ARCH_CHIP_RH850),y) +$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.850 + $(call ASSEMBLE, $<, $@) +else +$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) +endif + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libarch$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" + +nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) $(ARCHSCRIPT) + @echo "LD: nuttx" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target + +export_startup: $(STARTUP_OBJS) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup"; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi + +# Dependencies +ifeq ($(CONFIG_ARCH_CHIP_RH850),y) +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.850=.dds) $(HEAD_ASRC:.850=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) +else +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) $(HEAD_ASRC:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) +endif + +.depend: Makefile chip/Make.defs $(SRCS) $(TOPDIR)$(DELIM).config +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board depend +endif + $(Q) $(MAKE) makedepfile DEPPATH="--dep-path chip --dep-path common" + $(Q) touch $@ + +depend: .depend + +context:: + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board clean +endif + $(call DELFILE, libarch$(LIBEXT)) + $(call CLEAN) + +distclean:: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/arch/rh850/src/cmake/Toolchain.cmake b/arch/rh850/src/cmake/Toolchain.cmake new file mode 100644 index 0000000000000000000000000000000000000000..e55bb5076be5337491544bfff02acf71c67adca3 --- /dev/null +++ b/arch/rh850/src/cmake/Toolchain.cmake @@ -0,0 +1,52 @@ +# ############################################################################## +# arch/rh850/src/cmake/Toolchain.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# Toolchain + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) + +set(ARCH_SUBDIR) +set(COREPROFILE) + +if(CONFIG_ARCH_RH850G4MH) # RH850G4MH + set(COREPROFILE rh850g4mh) + set(ARCH_SUBDIR g4x) +elseif(CONFIG_ARCH_RH850G4KH) # RH850G4KH + set(COREPROFILE rh850g4kh) + set(ARCH_SUBDIR g4x) +endif() + +include(${COREPROFILE}) + +set(TOOLCHAIN_FILE) + +if(CONFIG_ARCH_TOOLCHAIN_CLANG) # clang + set(TOOLCHAIN_FILE clang) +elseif(CONFIG_ARCH_TOOLCHAIN_GHS) # greenhills + set(TOOLCHAIN_FILE ghs) +elseif(CONFIG_ARCH_TOOLCHAIN_HIGHTEC) # HighTec + set(TOOLCHAIN_FILE HighTec) +else() # gcc + set(TOOLCHAIN_FILE gcc) +endif() + +include(${TOOLCHAIN_FILE}) + diff --git a/arch/rh850/src/cmake/gcc.cmake b/arch/rh850/src/cmake/gcc.cmake new file mode 100644 index 0000000000000000000000000000000000000000..a7b0bd338163107e4704884228f425e1358e2921 --- /dev/null +++ b/arch/rh850/src/cmake/gcc.cmake @@ -0,0 +1,207 @@ +# ############################################################################## +# arch/arm/src/cmake/gcc.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# Toolchain + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) + +set(TOOLCHAIN_PREFIX arm-none-eabi) +set(CMAKE_LIBRARY_ARCHITECTURE ${TOOLCHAIN_PREFIX}) +set(CMAKE_C_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) +set(CMAKE_CXX_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) + +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) +set(CMAKE_PREPROCESSOR ${TOOLCHAIN_PREFIX}-gcc -E -P -x c) +set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-strip --strip-unneeded) +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-objcopy) +set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}-objdump) + +if(NOT CONFIG_LTO_NONE AND CONFIG_ARM_TOOLCHAIN_GNU_EABI) + set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_LD ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_AR ${TOOLCHAIN_PREFIX}-gcc-ar) + set(CMAKE_NM ${TOOLCHAIN_PREFIX}-gcc-nm) + set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-gcc-ranlib) + add_compile_options(-fno-builtin) +else() + set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_LD ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_AR ${TOOLCHAIN_PREFIX}-ar) + set(CMAKE_NM ${TOOLCHAIN_PREFIX}-nm) + set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-ranlib) +endif() + +set(NO_LTO "-fno-lto") + +# Workaround to skip -Warray-bounds check due to bug of GCC-12: Wrong warning +# array subscript [0] is outside array bounds: +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523 + +if(CONFIG_ARCH_TOOLCHAIN_GNU) + execute_process(COMMAND ${CMAKE_C_COMPILER} --version + OUTPUT_VARIABLE GCC_VERSION_OUTPUT) + string(REGEX MATCH "([0-9]+)\\.[0-9]+" GCC_VERSION_REGEX + "${GCC_VERSION_OUTPUT}") + set(GCCVER ${CMAKE_MATCH_1}) + + if(GCCVER GREATER_EQUAL 12) + add_compile_options(--param=min-pagesize=0) + if(CONFIG_ARCH_RAMFUNCS OR NOT CONFIG_BOOT_RUNFROMFLASH) + add_link_options(-Wl,--no-warn-rwx-segments) + endif() + endif() +endif() + +# override the ARCHIVE command + +set(CMAKE_ARCHIVE_COMMAND " rcs ") +set(CMAKE_RANLIB_COMMAND " ") +set(CMAKE_C_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_CXX_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_ASM_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) + +set(CMAKE_C_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_CXX_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_ASM_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) + +set(CMAKE_C_ARCHIVE_FINISH ${CMAKE_RANLIB_COMMAND}) +set(CMAKE_CXX_ARCHIVE_FINISH ${CMAKE_RANLIB_COMMAND}) +set(CMAKE_ASM_ARCHIVE_FINISH ${CMAKE_RANLIB_COMMAND}) + +if(CONFIG_ENDIAN_BIG) + add_compile_options(-mbig-endian) +endif() + +# Architecture flags + +add_link_options(-nostdlib) +add_compile_options(-fno-common -Wall -Wshadow -nostdlib) + +if(CONFIG_DEBUG_CUSTOMOPT) + add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) +elseif(CONFIG_DEBUG_FULLOPT) + add_compile_options(-Os) +endif() + +if(NOT CONFIG_DEBUG_NOOPT) + add_compile_options(-fno-strict-aliasing) +endif() + +if(CONFIG_STACK_CANARIES) + add_compile_options(-fstack-protector-all) +endif() + +if(CONFIG_SCHED_GCOV) + add_compile_options(-fprofile-generate -ftest-coverage) +endif() + +if(CONFIG_SCHED_GPROF_ALL) + add_compile_options(-pg) +endif() + +if(CONFIG_MM_UBSAN_ALL) + add_compile_options(${CONFIG_MM_UBSAN_OPTION}) +endif() + +if(CONFIG_MM_UBSAN_TRAP_ON_ERROR) + add_compile_options(-fsanitize-undefined-trap-on-error) +endif() + +if(CONFIG_MM_KASAN_ALL) + add_compile_options(-fsanitize=kernel-address) +endif() + +if(CONFIG_MM_KASAN_GLOBAL) + add_compile_options(--param=asan-globals=1) +endif() + +if(CONFIG_MM_KASAN_DISABLE_READS_CHECK) + add_compile_options(--param=asan-instrument-reads=0) +endif() + +if(CONFIG_MM_KASAN_DISABLE_WRITES_CHECK) + add_compile_options(--param=asan-instrument-writes=0) +endif() + +# Instrumentation options + +if(CONFIG_ARCH_INSTRUMENT_ALL) + add_compile_options(-finstrument-functions) +endif() + +if(CONFIG_SCHED_GPROF_ALL) + add_compile_options(-pg) +endif() + +# Link Time Optimization + +if(CONFIG_LTO_THIN) + add_compile_options(-flto=thin) +elseif(CONFIG_LTO_FULL) + add_compile_options(-flto) + add_compile_options(-fuse-linker-plugin) +elseif(CONFIG_LTO_FAT) + add_compile_options(-flto -ffat-lto-objects) +endif() + +# The arm clang toolchain requires to pass the linker option will gcc tool chain +# can automatically perform lto at linking time if it found any object files are +# compiled with flto + + +# Optimization of unused sections + +if(CONFIG_DEBUG_OPT_UNUSED_SECTIONS) + add_link_options(-Wl,--gc-sections) + add_compile_options(-ffunction-sections -fdata-sections) +endif() + +# Debug --whole-archive + +if(CONFIG_DEBUG_LINK_WHOLE_ARCHIVE) + add_link_options(-Wl,--whole-archive) +endif() + +# Debug link map + +if(CONFIG_DEBUG_LINK_MAP) + add_link_options(-Wl,--cref -Wl,-Map=nuttx.map) +endif() + + +if(CONFIG_DEBUG_SYMBOLS) + add_compile_options(${CONFIG_DEBUG_SYMBOLS_LEVEL}) +endif() + +add_compile_options( + -Wno-attributes -Wno-unknown-pragmas + $<$:-Wstrict-prototypes> + $<$:-nostdinc++>) + +# When all C++ code is built using GCC 7.1 or a higher version, we can safely +# disregard warnings of the type "parameter passing for X changed in GCC 7.1." +# Refer to : +# https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m + + +set(PREPROCESS ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/rh850/src/cmake/ghs.cmake b/arch/rh850/src/cmake/ghs.cmake new file mode 100644 index 0000000000000000000000000000000000000000..21ade0d2c1e7d5124fdc23923466837cb09bfffb --- /dev/null +++ b/arch/rh850/src/cmake/ghs.cmake @@ -0,0 +1,218 @@ +# ############################################################################## +# arch/rh850/src/cmake/ghs.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# Toolchain +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) + +# Cross compile: don't try to run executables during try-compile +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +# Disable Compiler tests +set(CMAKE_C_COMPILER_WORKS TRUE) # make CMake happy with GHS RH850 +set(CMAKE_CXX_COMPILER_WORKS TRUE) # make CMake happy with GHS RH850 +set(CMAKE_C_ABI_COMPILED TRUE) # make CMake happy with GHS RH850 +set(CMAKE_CXX_ABI_COMPILED TRUE) # make CMake happy with GHS RH850 +set(CMAKE_C_COMPILER_ID_RUN TRUE) +set(CMAKE_CXX_COMPILER_ID_RUN TRUE) +# ------------------------------------------------------------------------------ +# Compilers +# ------------------------------------------------------------------------------ +set(CMAKE_ASM_COMPILER ccrh850) +set(CMAKE_C_COMPILER ccrh850) +set(CMAKE_CXX_COMPILER ccrh850) +set(CMAKE_STRIP gstrip) +set(CMAKE_OBJCOPY gmemfile) +set(CMAKE_OBJDUMP gdump) +set(CMAKE_LINKER ccrh850) +set(CMAKE_LD ccrh850) +set(CMAKE_AR ccrh850) +set(CMAKE_GMEMFILE gmemfile) +set(CMAKE_NM gnm) +set(CMAKE_RANLIB echo) +set(CMAKE_PREPROCESSOR ccrh850 -E -P) +set(CMAKE_ASM_SOURCE_FILE_EXTENSIONS 850;S;s) + +# override the ARCHIVE command + +set(CMAKE_ARCHIVE_COMMAND + " -archive -o ") +set(CMAKE_C_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_CXX_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_ASM_ARCHIVE_CREATE ${CMAKE_ARCHIVE_COMMAND}) + +set(CMAKE_C_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_CXX_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) +set(CMAKE_ASM_ARCHIVE_APPEND ${CMAKE_ARCHIVE_COMMAND}) + +# Architecture flags +# Ensure target CPU is applied to both compile and link. +set(GHS_COMMON_FLAGS + -bsp=generic + --preprocess_linker_directive + -no_callt + -sda=0 + -reserve_r2 + -large_sda + -single_tda + --no_commons + -shorten_loads + -shorten_moves + -ignore_callt_state_in_interrupts + -additional_sda_reg=0 + -rh850_abi=ghs2014 + --prototype_errors + --diag_suppress=826 # remove warning 826-D + --diag_suppress=236 # remove warning 236-D + --diag_suppress=68 # remove warning 68-D + --diag_suppress=111 # remove warning 111-D + --diag_suppress=174 # remove warning 174-D + --diag_suppress=193 # remove warning 193-D + --diag_suppress=1721 # remove warning 1721-D + --diag_suppress=222 # remove warning 222-D + --diag_suppress=257 # remove warning 257-D + --diag_suppress=167 # remove warning 167-D + --diag_suppress=1547 # remove warning 1547-D + --diag_suppress=47 # remove warning 47-D + --diag_suppress=1143 # remove warning 1143 + --diag_suppress=177 # remove warning 177 + --diag_suppress=170 # remove warning 170 + --diag_suppress=550 # remove warning 50 + --diag_suppress=59 # remove warning 59 + --diag_suppress=186 # remove warning 186 + --diag_suppress=301 # remove warning 301 +) + +set(GHS_COMPILE_FLAGS + -Onone -w -g + -prepare_dispose + -inline_prologue + -passsource + --short_enum + -dwarf2 + -Wshadow + -delete + -MMD + -gnu99 + -nostdlib +) + +# Keep link step clean: no -c / -MMD +set(GHS_LINK_FLAGS + -map=nuttx.map +) + +add_compile_options(${GHS_COMMON_FLAGS} ${GHS_COMPILE_FLAGS}) +add_link_options(${GHS_COMMON_FLAGS} ${GHS_LINK_FLAGS}) + + +# Endian +if(CONFIG_ENDIAN_BIG) + add_compile_options(-mbig-endian) + add_link_options(-mbig-endian) +endif() + +# Entry symbol: must be passed as linker option "-e " +# (like your command line: -e _Reset_Handler) +if(CONFIG_USE_START_SYMBOL) + add_link_options(-e __start) +else() + add_link_options(-entry=_Reset_Handler) +endif() + +# Extra opts +if(CONFIG_DEBUG_CUSTOMOPT) + add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) +endif() + +if(CONFIG_DEBUG_SYMBOLS) + add_compile_options(-dual_debug) +endif() + + +if(CONFIG_BSP_FSP_SUPPORT) + add_compile_options(-DCONFIG_BSP_FSP_SUPPORT=1) +endif() + +set(PREPROCESS ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P) + + +# override nuttx_generate_preproces_target + +set(NUTTX_TOOLCHAIN_PREPROCES_DEFINED true) + +function(nuttx_generate_preproces_target) + + set(PREPROCESS_INCLUDE_FLAGS "-I${CMAKE_BINARY_DIR}/include" + "-I${NUTTX_CHIP_ABS_DIR}") + + if(CONFIG_RT_FRAMEWORK) + LIST(APPEND PREPROCESS_INCLUDE_FLAGS "-I${GENDATA_DIR}/scripts") + endif() + + # parse arguments into variables + + nuttx_parse_function_args( + FUNC + nuttx_generate_preproces_target + ONE_VALUE + SOURCE_FILE + TARGET_FILE + MULTI_VALUE + DEPENDS + REQUIRED + SOURCE_FILE + TARGET_FILE + ARGN + ${ARGN}) + + add_custom_command( + OUTPUT ${TARGET_FILE} + COMMAND ${PREPROCESS} ${PREPROCESS_INCLUDE_FLAGS} -filetype.cpp + ${SOURCE_FILE} -o ${TARGET_FILE} + DEPENDS ${SOURCE_FILE} ${DEPENDS}) + +endfunction() + +# override nuttx_find_toolchain_lib + +set(NUTTX_FIND_TOOLCHAIN_LIB_DEFINED true) + +function(nuttx_find_toolchain_lib) + find_program(COMPILER_EXE "${CMAKE_C_COMPILER}") + get_filename_component(GHS_ROOT_PATH "${COMPILER_EXE}" DIRECTORY) + string(STRIP "${GHS_ROOT_PATH}" GHS_ROOT_PATH) + if(NOT ARGN) + nuttx_add_extra_library(${GHS_ROOT_PATH}/lib/rh850_compat/libarch.a) + if(CONFIG_ARCH_FPU) + if(CONFIG_ARM_FPU_ABI_SOFT) + nuttx_add_extra_library(${GHS_ROOT_PATH}/lib/rh850_compat/libind_sf.a) + elseif(CONFIG_ARCH_DPFPU) + nuttx_add_extra_library(${GHS_ROOT_PATH}/lib/rh850_compat/libind_fp.a) + else() + nuttx_add_extra_library(${GHS_ROOT_PATH}/lib/rh850_compat/libind_sd.a) + endif() + else() + nuttx_add_extra_library(${GHS_ROOT_PATH}/lib/rh850_compat/libind_sd.a) + endif() + endif() +endfunction() + +# disable nuttx cmake link group otption +set(DISABLE_LINK_GROUP true) \ No newline at end of file diff --git a/arch/rh850/src/cmake/platform.cmake b/arch/rh850/src/cmake/platform.cmake new file mode 100644 index 0000000000000000000000000000000000000000..3e5071f6e293af92dc0fe39375eb69196c861ec5 --- /dev/null +++ b/arch/rh850/src/cmake/platform.cmake @@ -0,0 +1,74 @@ +# ############################################################################## +# arch/arm/src/cmake/platform.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# configure target processor + +if(CONFIG_ARCH_RH850G4MH) + set(CMAKE_SYSTEM_PROCESSOR rh850g4mh) +elseif(CONFIG_ARCH_RH850G4KH) + set(CMAKE_SYSTEM_PROCESSOR rh850g4kh) +else() + message(FATAL_ERROR "CMAKE_SYSTEM_PROCESSOR not set") +endif() + +get_directory_property(TOOLCHAIN_DIR_FLAGS DIRECTORY ${CMAKE_SOURCE_DIR} + COMPILE_OPTIONS) + +set(NUTTX_EXTRA_FLAGS "") +foreach(FLAG ${TOOLCHAIN_DIR_FLAGS}) + if(NOT FLAG MATCHES "^\\$<.*>$") + list(APPEND NUTTX_EXTRA_FLAGS ${FLAG}) + else() + string(REGEX MATCH "\\$<\\$:(.*)>" matched ${FLAG}) + if(matched) + list(APPEND NUTTX_EXTRA_FLAGS ${CMAKE_MATCH_1}) + endif() + endif() +endforeach() + +separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) + +if(NOT CONFIG_ARCH_TOOLCHAIN_HIGHTEC) + nuttx_find_toolchain_lib() + + if(NOT CONFIG_LIBM) + nuttx_find_toolchain_lib(libm.a) + endif() + + if(CONFIG_LIBSUPCXX_TOOLCHAIN) + nuttx_find_toolchain_lib(libsupc++.a) + endif() + + if(CONFIG_SCHED_GCOV) + nuttx_find_toolchain_lib(libgcov.a) + endif() +else() + if(NOT CONFIG_LIBM) + nuttx_find_toolchain_lib(libm.a) + endif() + + if(NOT CONFIG_LIBC) + nuttx_find_toolchain_lib(libc.a) + endif() + + if(NOT CONFIG_LIBG) + nuttx_find_toolchain_lib(libg.a) + endif() +endif() \ No newline at end of file diff --git a/arch/rh850/src/cmake/rh850.cmake b/arch/rh850/src/cmake/rh850.cmake new file mode 100644 index 0000000000000000000000000000000000000000..dc8bcae69c8d1bef8c879ba024cab999c3700732 --- /dev/null +++ b/arch/rh850/src/cmake/rh850.cmake @@ -0,0 +1,19 @@ +# ############################################################################## +# arch/arm/src/cmake/arm.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## diff --git a/arch/rh850/src/cmake/rh850g4kh.cmake b/arch/rh850/src/cmake/rh850g4kh.cmake new file mode 100644 index 0000000000000000000000000000000000000000..bce9840faf9ae68e8bbca934ced13eff9157d4ad --- /dev/null +++ b/arch/rh850/src/cmake/rh850g4kh.cmake @@ -0,0 +1,30 @@ +# ############################################################################## +# arch/arm/src/cmake/armv8-r.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(PLATFORM_FLAGS) + +if(CONFIG_ARCH_RH850G4KH) + if(CONFIG_RH850_TOOLCHAIN_GHS) + list(APPEND PLATFORM_FLAGS -cpu=rh850g4kh -D__RH850_G4KH__=1) + endif() +endif() + +add_compile_options(${PLATFORM_FLAGS}) + diff --git a/arch/rh850/src/cmake/rh850g4mh.cmake b/arch/rh850/src/cmake/rh850g4mh.cmake new file mode 100644 index 0000000000000000000000000000000000000000..f613dabec5f43db24615fad21321179e63f64c38 --- /dev/null +++ b/arch/rh850/src/cmake/rh850g4mh.cmake @@ -0,0 +1,31 @@ +# ############################################################################## +# arch/arm/src/cmake/armv8-r.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(PLATFORM_FLAGS) + +if(CONFIG_ARCH_RH850G4MH) + if(CONFIG_RH850_TOOLCHAIN_GHS) + list(APPEND PLATFORM_FLAGS -cpu=rh850g4mh -D__RH850_G4MH__=1) + endif() +endif() + +add_compile_options(${PLATFORM_FLAGS}) + + diff --git a/arch/rh850/src/common/CMakeLists.txt b/arch/rh850/src/common/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..418798d6292f0350086821928e19fd0c47e8f35b --- /dev/null +++ b/arch/rh850/src/common/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# arch/rh850/src/common/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_TOOLCHAIN_IAR) + set(ARCH_TOOLCHAIN_PATH iar) +elseif(CONFIG_ARCH_TOOLCHAIN_GNU) + set(ARCH_TOOLCHAIN_PATH gnu) +elseif(CONFIG_ARCH_TOOLCHAIN_GHS) + set(ARCH_TOOLCHAIN_PATH ghs) +else() + message("This compiler did not support ") +endif() + +# ------------ Loop *.c in Current Cmake ---------- +FILE(GLOB_RECURSE SRCS + ${CMAKE_CURRENT_SOURCE_DIR}/*.c +) +target_sources(arch PRIVATE ${SRCS}) + +# ------------ Loop *.850 in Current Cmake ---------- +FILE(GLOB_RECURSE ASRCS + ${CMAKE_CURRENT_SOURCE_DIR}/*.850 +) +# enable_language(ASM) +foreach(X IN ITEMS ${ASRCS}) + set_source_files_properties(${X} PROPERTIES LANGUAGE ASM) +endforeach() +target_sources(arch PRIVATE ${ASRCS}) \ No newline at end of file diff --git a/arch/rh850/src/common/Kconfig b/arch/rh850/src/common/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5052d3ae4d6c924b045b73fce043ce17a2484af3 --- /dev/null +++ b/arch/rh850/src/common/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RH850 +endif diff --git a/arch/rh850/src/common/Make.defs b/arch/rh850/src/common/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..63ae6826ef015580966a6353a882e53f702c9d22 --- /dev/null +++ b/arch/rh850/src/common/Make.defs @@ -0,0 +1,21 @@ +############################################################################ +# arch/rh850/src/common/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Common RH850 files diff --git a/arch/rh850/src/common/Toolchain.defs b/arch/rh850/src/common/Toolchain.defs new file mode 100644 index 0000000000000000000000000000000000000000..ea754775d5a2f293e9f8b48c2fb72a1579a133f5 --- /dev/null +++ b/arch/rh850/src/common/Toolchain.defs @@ -0,0 +1,560 @@ +############################################################################ +# arch/rh850/src/common/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# ARCHOPTIMIZATION The optimization level that results in +# reliable code generation. +# + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) +else ifeq ($(CONFIG_DEBUG_FULLOPT),y) + ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ARCHOPTIMIZATION += -Oz + else ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHOPTIMIZATION += -Osize + else + ARCHOPTIMIZATION += -Os + endif +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -fno-strict-aliasing +endif + +ifeq ($(CONFIG_FRAME_POINTER),y) + ifeq ($(CONFIG_ARCH_TOOLCHAIN_GHS),y) + ARCHOPTIMIZATION += -ga + else + ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls + endif +else + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHOPTIMIZATION += -noga + else + ARCHOPTIMIZATION += -fomit-frame-pointer + endif +endif + +ifeq ($(CONFIG_STACK_CANARIES),y) + ARCHOPTIMIZATION += -fstack-protector-all +endif + +ifeq ($(CONFIG_STACK_USAGE),y) + ARCHOPTIMIZATION += -fstack-usage +endif + +ifneq ($(CONFIG_STACK_USAGE_WARNING),0) + ARCHOPTIMIZATION += -Wstack-usage=$(CONFIG_STACK_USAGE_WARNING) +endif + +ifeq ($(CONFIG_SCHED_GPROF_ALL),y) + ARCHOPTIMIZATION += -pg +endif + +ifeq ($(CONFIG_MM_UBSAN_ALL),y) + ARCHOPTIMIZATION += $(CONFIG_MM_UBSAN_OPTION) +endif + +ifeq ($(CONFIG_MM_UBSAN_TRAP_ON_ERROR),y) + ARCHOPTIMIZATION += -fsanitize-undefined-trap-on-error +endif + +ifeq ($(CONFIG_MM_KASAN_ALL),y) + ARCHOPTIMIZATION += -fsanitize=kernel-address +endif + +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + ARCHOPTIMIZATION += --param asan-globals=1 +endif + +ifeq ($(CONFIG_MM_KASAN_DISABLE_READS_CHECK),y) + ARCHOPTIMIZATION += --param asan-instrument-reads=0 +endif + +ifeq ($(CONFIG_MM_KASAN_DISABLE_WRITES_CHECK),y) + ARCHOPTIMIZATION += --param asan-instrument-writes=0 +endif + +# Instrumentation options + +ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) + ARCHOPTIMIZATION += -finstrument-functions +endif + +ifeq ($(CONFIG_UNWINDER_ARM),y) + ifeq ($(CONFIG_ARCH_TOOLCHAIN_GHS),y) + ARCHOPTIMIZATION += -gtws + else + ARCHOPTIMIZATION += -funwind-tables -fasynchronous-unwind-tables + endif +endif + +# Link Time Optimization + +ifeq ($(CONFIG_LTO_THIN),y) + ARCHOPTIMIZATION += -flto=thin + ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y) + LDFLAGS += --lto + endif +else ifeq ($(CONFIG_LTO_FULL),y) + ARCHOPTIMIZATION += -flto + ifeq ($(CONFIG_ARM_TOOLCHAIN_GNU_EABI),y) + ARCHOPTIMIZATION += -fuse-linker-plugin + endif + ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y) + LDFLAGS += --lto + endif +endif + +# NuttX buildroot under Linux or Cygwin + +ifeq ($(CONFIG_ARM_TOOLCHAIN_BUILDROOT),y) + TARGET_TOOL := -nuttx-eabi- +else ifeq ($(CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI),y) + TARGET_TOOL := -nuttx-elf- +else ifeq ($(CONFIG_ARM_TOOLCHAIN_GNU_EABI),y) + TARGET_TOOL := -none-eabi- +endif + +ifneq ($(TARGET_TOOL),) + ifeq ($(CONFIG_ENDIAN_BIG),y) + + # Fallback to common toolchain if "armeb" is unavailable + + ifeq ($(shell command -v armeb$(TARGET_TOOL)gcc 2> /dev/null),) + TARGET_ARCH := arm + ARCHCPUFLAGS += -mlittle-endian + else + TARGET_ARCH := armeb + ARCHCPUFLAGS += -mbig-endian + endif + else + ARCHCPUFLAGS += -mlittle-endian + TARGET_ARCH := arm + endif + + CROSSDEV ?= $(TARGET_ARCH)$(TARGET_TOOL) +endif + +ARCHCPUFLAGS += $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT) + +ifeq ($(CONFIG_ARM_THUMB),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHCPUFLAGS += -thumb + else + ARCHCPUFLAGS += -mthumb + + # GCC Manual: + # -mthumb + # ... If you want to force assembler files to be interpreted as Thumb + # code, either add a `.thumb' directive to the source or pass the + # -mthumb option directly to the assembler by prefixing it with -Wa. + + ARCHCPUFLAGS += -Wa,-mthumb + + # Outputs an implicit IT block when there is a conditional instruction + # without an enclosing IT block. + + ARCHCPUFLAGS += -Wa,-mimplicit-it=always + endif +endif + +# Clang toolchain + +ifeq ($(CONFIG_ARM_TOOLCHAIN_CLANG),y) + + CC = clang + CXX = clang++ + CPP = clang -E -P -x c + LD = ld.lld -m armelf + STRIP = llvm-strip --strip-unneeded + AR = llvm-ar rcs + NM = llvm-nm + OBJCOPY = llvm-objcopy + OBJDUMP = llvm-objdump + + # Since the no_builtin attribute is not fully supported on Clang + # disable the built-in functions, refer: + # https://github.com/apache/nuttx/pull/5971 + + ARCHOPTIMIZATION += -fno-builtin + + ifneq ($(TOOLCHAIN_CLANG_CONFIG),) + ifeq ($(CLANGVER),) + export CLANGVER := $(shell $(CC) --version | grep "clang version" | sed -E "s/.* ([0-9]+\.[0-9]+).*/\1/") + endif + + ifeq ($(CLANGVER),14.0) + TOOLCHAIN_CLANG_CONFIG := $(TOOLCHAIN_CLANG_CONFIG)_nosys + endif + + ifeq "17.0" "$(word 1, $(sort 17.0 $(CLANGVER)))" + TOOLCHAIN_CLANG_OPTION = -target + ARCHCPUFLAGS += --target=arm-none-eabi + else + TOOLCHAIN_CLANG_OPTION = --config + endif + + ARCHCPUFLAGS := $(TOOLCHAIN_CLANG_OPTION) $(TOOLCHAIN_CLANG_CONFIG).cfg $(ARCHCPUFLAGS) + endif + + LDFLAGS += --entry=__start + +# ARM Compiler Clang toolchain + +else ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y) + + CC = armclang + CXX = armclang + CPP = armclang -E -P -x c + LD = armlink + STRIP = llvm-strip --strip-unneeded + AR = armar -rcs + NM = llvm-nm + OBJCOPY = llvm-objcopy + OBJDUMP = llvm-objdump + + # Since the no_builtin attribute is not fully supported on Clang + # disable the built-in functions, refer: + # https://github.com/apache/nuttx/pull/5971 + + ARCHOPTIMIZATION += -fno-builtin + ARCHOPTIMIZATION += --target=arm-arm-none-eabi + + # Suppress license warning + + ARCHCPUFLAGS += -Wno-license-management + LDFLAGS += --diag_suppress=9931 + + # Input sections are specified even though there will be no such + # sections found in the libraries linked. + # Warning: L6314W: No section matches pattern *(xxx). + + LDFLAGS += --diag_suppress=6314 + + # Allow Empty Execution region declared on scatter + # Warning: L6312W: Empty Execution region description for region xxx + + LDFLAGS += --diag_suppress=6312 + + # Match pattern for an unused section that is being removed. + # Warning: L6329W: Pattern xxx only matches removed unused sections. + + LDFLAGS += --diag_suppress=6329 + + LDFLAGS += --entry=__start + +else ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + CC = ccarm + CXX = cxarm + CPP = ccarm -E -P + LD = cxarm + STRIP = gstrip + AR = cxarm + NM = gnm + OBJCOPY = objcopy + GMEMFILE = gmemfile + OBJDUMP = gdump + + LDFLAGS += -entry=__start + +# Default toolchain + +else + CC = $(CROSSDEV)gcc + CXX = $(CROSSDEV)g++ + CPP = $(CROSSDEV)gcc -E -P -x c + LD = $(CROSSDEV)ld + STRIP = $(CROSSDEV)strip --strip-unneeded + AR = $(CROSSDEV)ar rcs + NM = $(CROSSDEV)nm + OBJCOPY = $(CROSSDEV)objcopy + OBJDUMP = $(CROSSDEV)objdump + + ifeq ($(CONFIG_LTO_FULL),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GNU_EABI),y) + LD := $(CROSSDEV)gcc + AR := $(CROSSDEV)gcc-ar rcs + NM := $(CROSSDEV)gcc-nm + ARCHOPTIMIZATION += -fno-builtin + endif + endif + + # Workaround to skip -Warray-bounds check due to bug of GCC-12: + # Wrong warning array subscript [0] is outside array bounds: + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523 + + ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) + ifeq ($(GCCVER),) + export GCCVER := $(shell $(CC) --version | grep gcc | sed -E "s/.* ([0-9]+\.[0-9]+).*/\1/" | cut -d'.' -f1) + endif + ifeq ($(shell expr "$(GCCVER)" \>= 12), 1) + ARCHOPTIMIZATION += --param=min-pagesize=0 + ifeq ($(CONFIG_ARCH_RAMFUNCS),y) + LDFLAGS += --no-warn-rwx-segments + else ifeq ($(CONFIG_BOOT_RUNFROMFLASH),) + LDFLAGS += --no-warn-rwx-segments + endif + endif + endif + + LDFLAGS += --entry=__start + LDFLAGS += --print-memory-usage + +endif + +ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ARCHOPTIMIZATION += -fshort-enums + ARCHCFLAGS += -Wno-atomic-alignment + ARCHCXXFLAGS += -Wno-atomic-alignment +endif + +# Architecture flags + +ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHCFLAGS += -gcc -gnu99 -preprocess_assembly_files --diag_suppress=68,111,174,222,236,257,826,1143,1721 + ARCHCXXFLAGS += --gnu_asm --diag_suppress=540,826 +else + ARCHCFLAGS += -Wstrict-prototypes -Wno-attributes -Wno-unknown-pragmas + ARCHCXXFLAGS += -Wno-attributes -Wno-unknown-pragmas +endif + +# When all C++ code is built using GCC 7.1 or a higher version, +# we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." +# Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m + +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + +ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ifneq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHCFLAGS += -Wno-psabi + ARCHCXXFLAGS += -Wno-psabi + endif +endif + +ifneq ($(CONFIG_CXX_STANDARD),) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHCXXFLAGS += --$(CONFIG_CXX_STANDARD) + else + ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) + endif +endif + +ifneq ($(CONFIG_CXX_EXCEPTION),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ARCHCXXFLAGS += --no_exceptions -check=alloc + else + ARCHCXXFLAGS += -fno-exceptions -fcheck-new + endif +endif + +ifneq ($(CONFIG_CXX_RTTI),y) + ARCHCXXFLAGS += -fno-rtti +endif +ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) +ARCHOPTIMIZATION += --no_commons +else +ARCHOPTIMIZATION += -fno-common +endif +ARCHOPTIMIZATION += -Wall -Wshadow -Wundef + +ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y) + ARCHOPTIMIZATION += -nostdlib +else + LDFLAGS += -nostdlib +endif + +ifeq ($(CONFIG_ARM_THUMB),y) + ZARCH := thumb +else + ZARCH := arm +endif + +ifeq ($(CONFIG_ARCH_FPU),y) + ZEABI := gnueabihf +else + ZEABI := gnueabi +endif + +ZIGFLAGS = -target $(ZARCH)-freestanding-$(ZEABI) $(ZARCHCPUFLAGS) + +# Optimization of unused sections + +ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),) + ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y) + ifeq ($(CONFIG_ARCH_TOOLCHAIN_GHS),) + LDFLAGS += --gc-sections + ARCHOPTIMIZATION += -ffunction-sections -fdata-sections + endif + endif +endif + +# Debug --whole-archive + +ifeq ($(CONFIG_DEBUG_LINK_WHOLE_ARCHIVE),y) + LDFLAGS += --whole-archive +endif + +# Debug link map + +ifeq ($(CONFIG_DEBUG_LINK_MAP),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + LDFLAGS += -map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map) + else ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),) + LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map) + else + LDFLAGS += --strict --map --xref --symbols --info=unused --info=veneers + LDFLAGS += --info=summarysizes --info=summarystack + endif +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_SYMBOLS_LEVEL) + ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y) + LDFLAGS += --debug + endif + else + ARCHOPTIMIZATION += -G -gdwarf-2 + endif +endif + +# Add the builtin library + +COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name) +ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ifeq ($(wildcard $(COMPILER_RT_LIB)),) + # if "--print-libgcc-file-name" unable to find the correct libgcc PATH + # then go ahead and try "--print-file-name" + COMPILER_RT_LIB := $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name $(notdir $(COMPILER_RT_LIB)))) + endif +else ifeq ($(CONFIG_ARCH_TOOLCHAIN_GHS),y) + GHS_ROOT_PATH = $(shell which $(CC) | awk -F '/[^/]*$$' '{print $$1}') + COMPILER_RT_LIB := -l$(GHS_ROOT_PATH)/lib/thumb2/libarch + ifeq ($(CONFIG_ARCH_FPU),y) + ifeq ($(CONFIG_ARM_FPU_ABI_SOFT),y) + COMPILER_RT_LIB += -l$(GHS_ROOT_PATH)/lib/thumb2/libind_sf + else ifeq ($(CONFIG_ARCH_DPFPU),y) + COMPILER_RT_LIB += -l$(GHS_ROOT_PATH)/lib/thumb2/libind_fp + else + COMPILER_RT_LIB += -l$(GHS_ROOT_PATH)/lib/thumb2/libind_sd + endif + else + COMPILER_RT_LIB += -l$(GHS_ROOT_PATH)/lib/thumb2/libind_sf + endif +endif + +EXTRA_LIBS += $(COMPILER_RT_LIB) + +ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) + ifeq ($(CONFIG_ARM_TOOLCHAIN_GHS),y) + ifeq ($(CONFIG_ARCH_FPU),y) + ifeq ($(CONFIG_ARM_FPU_ABI_SOFT),y) + EXTRA_LIBS += -l$(GHS_ROOT_PATH)/lib/thumb2/libmath_sf + else ifeq ($(CONFIG_ARCH_DPFPU),y) + EXTRA_LIBS += -l$(GHS_ROOT_PATH)/lib/thumb2/libmath_fp + else + EXTRA_LIBS += -l$(GHS_ROOT_PATH)/lib/thumb2/libmath_sd + endif + else + EXTRA_LIBS += -l$(GHS_ROOT_PATH)/lib/thumb2/libmath_sf + endif + else + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) + endif +endif + +ifeq ($(CONFIG_LIBSUPCXX_TOOLCHAIN),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a)) +endif + +ifeq ($(CONFIG_SCHED_GCOV),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcov.a)) +endif + +ifeq ($(CONFIG_LIBCXXTOOLCHAIN),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libstdc++.a)) +endif + +PICFLAGS = -fpic -fPIE -mno-pic-data-is-text-relative -msingle-pic-base + +ifneq ($(CONFIG_BUILD_PIC),) + ARCHCFLAGS += $(PICFLAGS) -mpic-register=r9 + ARCHCXXFLAGS += $(PICFLAGS) -mpic-register=r9 + LDFLAGS += --emit-relocs +endif + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -fvisibility=hidden -mlong-calls # --target1-abs +LDMODULEFLAGS = -r -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -fvisibility=hidden -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS)-fvisibility=hidden + +ifeq ($(CONFIG_PIC),y) + CFLAGS += --fixed-r10 + CELFFLAGS += $(PICFLAGS) -mpic-register=r10 + CXXELFFLAGS += $(PICFLAGS) -mpic-register=r10 + + # Generate an executable elf, need to ignore undefined symbols + LDELFFLAGS += --unresolved-symbols=ignore-in-object-files --emit-relocs +else + LDELFFLAGS += -r +endif + +LDELFFLAGS += -e main -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)libs$(DELIM)libc$(DELIM)modlib$(DELIM)gnu-elf.ld) + +# Zig toolchain + +include $(TOPDIR)/tools/Zig.defs + +# Rust toolchain + +include $(TOPDIR)/tools/Rust.defs + +# LDC (LLVM D Compiler) toolchain + +include $(TOPDIR)/tools/D.defs + +# Swift 6 toolchain + +include $(TOPDIR)/tools/Swift.defs + +# Shared library build flags + +SHCCFLAGS = -fPIC -fPIE -fvisibility=default +SHLDFLAGS = -shared -Bsymbolic -Bdynamic -G + +ifeq ($(CONFIG_SIM_M32),y) + SHLDFLAGS += -melf_i386 +endif diff --git a/arch/rh850/src/common/renesas_internal.h b/arch/rh850/src/common/renesas_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..2001a00f7f635a2daeb5897cffc60d0833c12fb0 --- /dev/null +++ b/arch/rh850/src/common/renesas_internal.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/renesas/src/common/renesas_internal.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H +#define ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Determine which (if any) console driver to use. NOTE that the naming + * implies that the console is a serial driver. That is usually the case, + * however, if no UARTs are enabled, the console could also be provided + * through some other device, such as an LCD. Architecture-specific logic + * will have to detect that case. + * + * If a console is enabled and no other console device is specified, then + * a serial console is assumed. + */ + +#ifndef CONFIG_DEV_CONSOLE +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +#else +# if defined(CONFIG_CONSOLE_SYSLOG) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* If some other device is used as the console, then the serial driver may + * still be needed. Let's assume that if the upper half serial driver is + * built, then the lower half will also be needed. There is no need for + * the early serial initialization in this case. + */ + +#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) +# define USE_SERIALDRIVER 1 +#endif + +/* Check if an interrupt stack size is configured */ + +#ifndef CONFIG_ARCH_INTERRUPTSTACK +# define CONFIG_ARCH_INTERRUPTSTACK 0 +#endif + +/* The SH stack must be aligned at word (4 byte) boundaries. If necessary + * frame_size must be rounded up to the next boundary + */ + +// todo, check the alignment requirement of rh850 stack +#define STACK_ALIGNMENT 4 + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT - 1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +#define renesas_savestate(regs) renesas_copystate(regs, up_current_regs()) + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*up_vector_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* This is the beginning of heap as provided from up_head.S. + * This is the first address in DRAM after the loaded + * program+bss+idle stack. The end of the heap is + * CONFIG_RAM_END + */ + +// extern uint32_t g_idle_topstack; +#endif + +/* Address of the saved user stack pointer */ + +#ifndef __ASSEMBLY__ +# if CONFIG_ARCH_INTERRUPTSTACK > 3 + extern uint8_t g_intstackalloc[]; + extern uint8_t g_intstacktop[]; +# endif +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Defined in files with the same name as the function */ + +void renesas_copystate(uint32_t *dest, uint32_t *src); +void renesas_dataabort(uint32_t *regs); +void renesas_decodeirq(uint32_t *regs); +uint32_t *renesas_doirq(int irq, uint32_t *regs); +void renesas_fullcontextrestore(uint32_t *regs) noreturn_function; +void renesas_prefetchabort(uint32_t *regs); +void renesas_sigdeliver(void); +void renesas_syscall(uint32_t *regs); +void renesas_lowputc(char ch); +void renesas_lowputs(const char *str); + +/* Defined in xyz_vectors.S */ + +void renesas_vectorundefinsn(void); +void renesas_vectorswi(void); +void renesas_vectorprefetch(void); +void renesas_vectordata(void); +void renesas_vectoraddrexcptn(void); +void renesas_vectorirq(void); +void renesas_vectorfiq(void); + +/* Defined in xyz_serial.c */ + +#ifdef USE_EARLYSERIALINIT +void renesas_earlyconsoleinit(void); +#endif + +#ifdef USE_SERIALDRIVER +void renesas_consoleinit(void); +void renesas_serialinit(void); +#endif + +void renesas_lowputc(char ch); + +/* Defined in board/xyz_lcd.c */ + +#ifdef CONFIG_SLCD_CONSOLE +void renesas_lcdinit(void); +void renesas_lcdputc(char ch); +#else +# define renesas_lcdinit() +# define renesas_lcdputc(ch) +#endif + +/* Defined in board/xyz_network.c */ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void renesas_netinitialize(void); +#else +# define renesas_netinitialize() +#endif + +/* USB */ + +#ifdef CONFIG_USBDEV +void renesas_usbinitialize(void); +void renesas_usbuninitialize(void); +#else +# define renesas_usbinitialize() +# define renesas_usbuninitialize() +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* ___ARCH_RENESAS_SRC_COMMON_UP_INTERNAL_H */ diff --git a/arch/rh850/src/common/rh850_allocateheap.c b/arch/rh850/src/common/rh850_allocateheap.c new file mode 100644 index 0000000000000000000000000000000000000000..859b7afdf11a661531a064349e804ecab634dd7a --- /dev/null +++ b/arch/rh850/src/common/rh850_allocateheap.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_allocateheap.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +/* Heap boundaries provided by the linker script */ +extern uint32_t __ghsbegin_heap; +extern uint32_t __ghsend_heap; +extern uint32_t __ghsbegin_kheap; +extern uint32_t __ghsend_kheap; + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ +char * pvar; +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = &__ghsbegin_heap; + *heap_size = (&__ghsend_heap - &__ghsbegin_heap); +} + + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +#if defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + *heap_start = &__ghsbegin_kheap; + *heap_size = (&__ghsend_kheap - &__ghsbegin_kheap); +} +#endif \ No newline at end of file diff --git a/arch/rh850/src/common/rh850_copystate.c b/arch/rh850/src/common/rh850_copystate.c new file mode 100644 index 0000000000000000000000000000000000000000..4a0061e6a27c0c19ea4322e0a9263ce3ab679447 --- /dev/null +++ b/arch/rh850/src/common/rh850_copystate.c @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/rh850/src/sh1/sh1_copystate.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "renesas_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: renesas_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void rh850_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } +} diff --git a/arch/rh850/src/common/rh850_createstack.c b/arch/rh850/src/common/rh850_createstack.c new file mode 100644 index 0000000000000000000000000000000000000000..0029f6b21e7de0681632e24f0c91c1a67f5e4b18 --- /dev/null +++ b/arch/rh850/src/common/rh850_createstack.c @@ -0,0 +1,196 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_createstack.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ +#ifdef CONFIG_TLS_ALIGNED + /* The allocated stack size must not exceed the maximum possible for the + * TLS feature. + */ + + DEBUGASSERT(stack_size <= TLS_MAXSTACK); + if (stack_size >= TLS_MAXSTACK) + { + stack_size = TLS_MAXSTACK; + } +#endif + + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + * If TLS is enabled, then we must allocate aligned stacks. + */ + +#ifdef CONFIG_TLS_ALIGNED +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = kmm_memalign(TLS_STACK_ALIGN, stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = kumm_memalign(TLS_STACK_ALIGN, stack_size); + } + +#else /* CONFIG_TLS_ALIGNED */ +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = kumm_malloc(stack_size); + } +#endif /* CONFIG_TLS_ALIGNED */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %zd\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + uintptr_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* The SH family uses a push-down stack: the stack grows + * toward loweraddresses in memory. The stack pointer + * register, points to the lowest, valid work address + * (the "top" of the stack). Items on the stack are + * referenced as positive word offsets from sp. + */ + + top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size; + + /* The SH stack must be aligned at word (4 byte) + * boundaries. If necessary top_of_stack must be rounded + * down to the next boundary + */ + + top_of_stack &= ~3; + size_of_stack = top_of_stack - (uintptr_t)tcb->stack_alloc_ptr; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = size_of_stack; + tcb->flags |= TCB_FLAG_FREE_STACK; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/rh850/src/common/rh850_doirq.c b/arch/rh850/src/common/rh850_doirq.c new file mode 100644 index 0000000000000000000000000000000000000000..17d94f1115fb6f85a4aa4beedbf6f84348427035 --- /dev/null +++ b/arch/rh850/src/common/rh850_doirq.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_doirq.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "rh850_internal.h" +#include "group/group.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +uint32_t g_nestlevel = 0; +uint32_t *rh850_doirq(int irq, uint32_t * regs) +{ + irqstate_t flags; + /* Current regs non-zero indicates that we are processing an interrupt; + * regs holds the state of the interrupted logic; current_regs holds the + * state of the interrupted user task. current_regs should, therefore, + * only be modified for outermost interrupt handler (when g_nestlevel == 0) + */ + flags = up_irq_save(); + if (g_nestlevel == 0) + { + up_set_current_regs(regs); + g_running_tasks[this_cpu()] = this_task(); + } + g_nestlevel++; + up_irq_restore(flags); + + + + /* Deliver the IRQ */ + irq_dispatch(irq, regs); + + /* Context switches are indicated by the returned value of this function. + * If a context switch occurred while processing the interrupt then + * current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. Context switching should + * only be performed when the outermost interrupt handler returns. + */ + __asm__ volatile ("synce"); + flags = up_irq_save(); + g_nestlevel--; + if (g_nestlevel == 0) + { + regs = up_current_regs(); + up_set_current_regs(NULL); + + up_set_contexthdl(this_task()->contexthdl); + } + + /* If a context switch occurred while processing the interrupt then + * current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + board_autoled_off(LED_INIRQ); + + return regs; +} + + +uint32_t *rh850_switch_context(uint32_t * oldregs) +{ + /* Yes, then we have to do things differently. + * Just copy the current_regs into the OLD rtcb. + */ + + g_running_tasks[this_cpu()]->xcp.regs = oldregs; + nxsched_suspend_scheduler(g_running_tasks[this_cpu()]); + + /* Update scheduler parameters */ + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + nxsched_resume_scheduler(this_task()); + + g_running_tasks[this_cpu()] = this_task(); + up_set_contexthdl(this_task()->contexthdl); + + return this_task()->xcp.regs; +} + +uint32_t *up_regs(void) +{ + return this_task()->xcp.regs; +} diff --git a/arch/rh850/src/common/rh850_exception.850 b/arch/rh850/src/common/rh850_exception.850 new file mode 100644 index 0000000000000000000000000000000000000000..53195f5365a3f6d627fcd802e44938ed7d49a75d --- /dev/null +++ b/arch/rh850/src/common/rh850_exception.850 @@ -0,0 +1,175 @@ +.extern rh850_doirq +.extern _up_current_regs +.extern _uxInterruptStack + +.global _Irq_Handler +.global _TRAP0_Handler +.global _rh850_fullcontextrestore +.global _up_saveusercontext + +-------------------------------------------------------------------------------- +-- Macro definitions. +-------------------------------------------------------------------------------- +.set EIPC, 0 +.set EIPSW, 1 +.set PSW, 5 +.set FPSR, 6 +.set FPEPC, 7 +.set FXSR, 6 +.set FXXP, 13 +.set EIIC, 13 +.set CTPC, 16 +.set CTPSW, 17 +.set EIIC_MSK, 0x00000FFF +.set FPU_MSK, 0x00010000 +.set FXU_MSK, 0x00020000 + + +-------------------------------------------------------------------------------- +-- Restore used registers. +-------------------------------------------------------------------------------- +.macro RESTORE_REGISTER + popsp r18-r19 + ldsr r19, FPEPC + ldsr r18, FPSR + + popsp r13-r19 + ldsr r13, CTPC + ldsr r14, CTPSW + mov r15, ep + mov r16, lp + ldsr r17, EIIC + ldsr r18, EIPC + ldsr r19, EIPSW + + popsp r1-r2 + popsp r6-r19 +.endm + +-------------------------------------------------------------------------------- +-- Save used registers. +-------------------------------------------------------------------------------- +.macro SAVE_REGISTER + pushsp r6-r19 + pushsp r1-r2 + + stsr EIPSW, r19 + stsr EIPC, r18 + stsr EIIC, r17 + mov lp, r16 + mov ep, r15 + stsr CTPSW, r14 + stsr CTPC, r13 + pushsp r13-r19 + + stsr FPSR, r18 + stsr FPEPC, r19 + pushsp r18-r19 +.endm + +-------------------------------------------------------------------------------- +-- Save used context. +-------------------------------------------------------------------------------- +.macro RESTORE_CONTEXT + -- Restore FPU registers if FPU is enabled + popsp r18-r19 + ldsr r19, FPEPC + ldsr r18, FPSR + + --Restore general-purpose registers and EIPSW, EIPC, EIIC, CTPSW, CTPC + popsp r14-r19 + ldsr r19, CTPC + ldsr r18, CTPSW + ldsr r17, EIIC + ldsr r16, EIPC + ldsr r15, EIPSW + mov r14, lp + + popsp r1-r2 + popsp r6-r30 + +.endm + +-------------------------------------------------------------------------------- +-- Save used context. +-------------------------------------------------------------------------------- +.macro SAVE_CONTEXT + pushsp r6-r30 + pushsp r1-r2 + + mov lp, r14 + stsr EIPSW, r15 + stsr EIPC, r16 + stsr EIIC, r17 + stsr CTPSW, r18 + stsr CTPC, r19 + pushsp r14-r19 + + stsr FPSR, r18 + stsr FPEPC, r19 + pushsp r18-r19 +.endm + +-------------------------------------------------------------------------------- +-- Irq_Hanlder to process sw interrupt mapping +-------------------------------------------------------------------------------- +_Irq_Handler: + SAVE_REGISTER + + jarl _up_regs, lp + mov r10, r7 + pushsp r7 + + -- Call the interrupt handler. + stsr EIIC, r6 + andi EIIC_MSK, r6, r6 /* Interrupt Number */ + + /* uint32_t *rh850_doirq(int irq, uint32_t *regs) */ + /* Invoke irq = r6 and regs = r7 */ + jarl _rh850_doirq, lp + + popsp r7 -- Old regs + + cmp r7, r10 -- If old regs != current regs + -- then it needs to be switched new context + bne _RH850_InterruptDrivenSwitchContext + +_RH850_InterruptDrivenNotSwitchContext: + RESTORE_REGISTER -- <-- Stack Pointer already popped enough + eiret + +_RH850_InterruptDrivenSwitchContext: + RESTORE_REGISTER -- <-- Stack Pointer already popped enough + SAVE_CONTEXT -- Save old regs, to switch next context + mov sp, r6 + + jarl _rh850_switch_context, lp -- To get this_task for switch context + mov r10, sp + RESTORE_CONTEXT + + eiret + + +-------------------------------------------------------------------------------- +-- PortYield handler. This is installed as the TRAP exception handler. +-------------------------------------------------------------------------------- +_TRAP0_Handler: + SAVE_CONTEXT + mov sp, r6 + jarl _rh850_switch_context, lp -- To get this_task for switch context + mov r10, sp -- Return new stack pointer for new context + RESTORE_CONTEXT + eiret + +_rh850_fullcontextrestore: + jmp [lp] + +_up_saveusercontext: + SAVE_CONTEXT + -- Backup save stackpoint + mov sp, r10 -- Return new stack pointer for new context + + --- Need to backup new stack pointer for rtcb->xcp.regs + jmp [lp] + + diff --git a/arch/rh850/src/common/rh850_exit.c b/arch/rh850/src/common/rh850_exit.c new file mode 100644 index 0000000000000000000000000000000000000000..9454b911a618ce43e30551c5cbadacb801415e8c --- /dev/null +++ b/arch/rh850/src/common/rh850_exit.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "rh850_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void up_exit(int status) +{ + struct tcb_s *tcb = this_task(); + + /* Destroy the task at the head of the ready to run list. */ + + nxtask_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + + /* Adjusts time slice for SCHED_RR & SCHED_SPORADIC cases */ + + nxsched_resume_scheduler(tcb); + g_running_tasks[this_cpu()] = tcb; + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + addrenv_switch(tcb); +#endif + + /* Then switch contexts */ + + rh850_fullcontextrestore(tcb->xcp.regs); +} diff --git a/arch/rh850/src/common/rh850_idle.c b/arch/rh850/src/common/rh850_idle.c new file mode 100644 index 0000000000000000000000000000000000000000..118d8732585eaff2703f0c26eec868731b9b9fe1 --- /dev/null +++ b/arch/rh850/src/common/rh850_idle.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their + * is no other ready-to-run task. This is processor idle + * time and will continue until some interrupt occurs to + * cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., + * this is where power management operations might be + * performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + +#if 1 + asm("nop"); /* For example */ +#endif + +#ifdef CONFIG_CPULOAD_MONITOR_IN_IDLE + + /* This function provides a mechanism for detecting the accurate CPU load + * rate in the idle task + */ + + nxsched_cpuload_idletask_infiniteloop(); + +#endif + +#endif +} diff --git a/arch/rh850/src/common/rh850_initialize.c b/arch/rh850/src/common/rh850_initialize.c new file mode 100644 index 0000000000000000000000000000000000000000..131746744446ee7d59d706aa9b2e464585753127 --- /dev/null +++ b/arch/rh850/src/common/rh850_initialize.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_initialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + + +#include "rh850_internal.h" +#include "bsp_api.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_color_intstack + * + * Description: + * Set the interrupt stack to a value so that later we can determine how + * much stack space was used by interrupt handling logic + * + ****************************************************************************/ +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + // To develop for new feature +#else +# define up_color_intstack() +#endif + + + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ + up_color_intstack(); + + rh850_ioportinit(); + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + rh850_serialinit(); +#endif + +} + +void up_init_irq(int irq, int irq_prio) +{ + /* Setup interrupt and enable */ + RH850_IRQ_SetPriority((uint32_t) irq, (uint32_t) irq_prio); +} + diff --git a/arch/rh850/src/common/rh850_initialstate.c b/arch/rh850/src/common/rh850_initialstate.c new file mode 100644 index 0000000000000000000000000000000000000000..f2076d80b9d61f01507bfabb38f2f2efbb19fbf4 --- /dev/null +++ b/arch/rh850/src/common/rh850_initialstate.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/arm/src/arm/arm_initialstate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + + +#if CONFIG_BSP_FSP_SUPPORT +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + /* Macros required to set up the initial stack. */ +#define STACK_INITIAL_VALUE_R1 ((uint32_t) 0x01010101) +#define STACK_INITIAL_VALUE_R2 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x02) +#define STACK_INITIAL_VALUE_R3 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x03) +#define STACK_INITIAL_VALUE_R4 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x04) +#define STACK_INITIAL_VALUE_R5 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x05) +#define STACK_INITIAL_VALUE_R6 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x06) +#define STACK_INITIAL_VALUE_R7 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x07) +#define STACK_INITIAL_VALUE_R8 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x08) +#define STACK_INITIAL_VALUE_R9 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x09) +#define STACK_INITIAL_VALUE_R10 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x10) +#define STACK_INITIAL_VALUE_R11 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x11) +#define STACK_INITIAL_VALUE_R12 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x12) +#define STACK_INITIAL_VALUE_R13 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x13) +#define STACK_INITIAL_VALUE_R14 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x14) +#define STACK_INITIAL_VALUE_R15 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x15) +#define STACK_INITIAL_VALUE_R16 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x16) +#define STACK_INITIAL_VALUE_R17 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x17) +#define STACK_INITIAL_VALUE_R18 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x18) +#define STACK_INITIAL_VALUE_R19 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x19) +#define STACK_INITIAL_VALUE_R20 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x20) +#define STACK_INITIAL_VALUE_R21 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x21) +#define STACK_INITIAL_VALUE_R22 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x22) +#define STACK_INITIAL_VALUE_R23 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x23) +#define STACK_INITIAL_VALUE_R24 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x24) +#define STACK_INITIAL_VALUE_R25 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x25) +#define STACK_INITIAL_VALUE_R26 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x26) +#define STACK_INITIAL_VALUE_R27 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x27) +#define STACK_INITIAL_VALUE_R28 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x28) +#define STACK_INITIAL_VALUE_R29 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x29) +#define STACK_INITIAL_VALUE_R30 ((uint32_t) STACK_INITIAL_VALUE_R1 * 0x30) +#define INITIAL_PSW_MASK (0x00078000) +/* Hardware specific macros */ +#define REGISTER_SEL_0 0 +#define PSW_REGISTER_ID (5) +#define FPSR_REGISTER_ID (6) +#define FXSR_REGISTER_ID (6) +#define FXSR_REGISTER_SEL (10) + +#define CURRENT_PSW_VALUE (__STSR(PSW_REGISTER_ID, REGISTER_SEL_0)) + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the initial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +static uint8_t g_idle_stack_buffer[CONFIG_IDLETHREAD_STACKSIZE]; +const uintptr_t g_idle_topstack = + (uintptr_t)(g_idle_stack_buffer + CONFIG_IDLETHREAD_STACKSIZE); + void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + if (tcb->pid == IDLE_PROCESS_ID) + { + char *stack_ptr = (char *)(g_idle_topstack); +#ifdef CONFIG_STACK_COLORATION + char *stack_end = (char *)up_getsp(); + + /* If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + + while (stack_ptr < stack_end) + { + *--stack_end = 0xaa; + } +#endif /* CONFIG_STACK_COLORATION */ + + tcb->stack_alloc_ptr = stack_ptr; + tcb->stack_base_ptr = stack_ptr; + tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; + } + + /* Initialize the context registers to stack top */ + + xcp->regs = (void *)((uint32_t)tcb->stack_base_ptr + + tcb->adj_stack_size - + XCPTCONTEXT_SIZE); + /* Initialize the initial exception register context structure */ + xcp->regs[REG_R6] = STACK_INITIAL_VALUE_R6; + xcp->regs[REG_R7] = STACK_INITIAL_VALUE_R7; + xcp->regs[REG_R8] = STACK_INITIAL_VALUE_R8; + xcp->regs[REG_R9] = STACK_INITIAL_VALUE_R9; + xcp->regs[REG_R10] = STACK_INITIAL_VALUE_R10; + xcp->regs[REG_R11] = STACK_INITIAL_VALUE_R11; + xcp->regs[REG_R12] = STACK_INITIAL_VALUE_R12; + xcp->regs[REG_R13] = STACK_INITIAL_VALUE_R13; + xcp->regs[REG_R14] = STACK_INITIAL_VALUE_R14; + xcp->regs[REG_R15] = STACK_INITIAL_VALUE_R15; + xcp->regs[REG_R16] = STACK_INITIAL_VALUE_R16; + xcp->regs[REG_R17] = STACK_INITIAL_VALUE_R17; + xcp->regs[REG_R18] = STACK_INITIAL_VALUE_R18; + xcp->regs[REG_R19] = STACK_INITIAL_VALUE_R19; + xcp->regs[REG_R20] = STACK_INITIAL_VALUE_R20; + xcp->regs[REG_R21] = STACK_INITIAL_VALUE_R21; + xcp->regs[REG_R22] = STACK_INITIAL_VALUE_R22; + xcp->regs[REG_R23] = STACK_INITIAL_VALUE_R23; + xcp->regs[REG_R24] = STACK_INITIAL_VALUE_R24; + xcp->regs[REG_R25] = STACK_INITIAL_VALUE_R25; + xcp->regs[REG_R26] = STACK_INITIAL_VALUE_R26; + xcp->regs[REG_R27] = STACK_INITIAL_VALUE_R27; + xcp->regs[REG_R28] = STACK_INITIAL_VALUE_R28; + xcp->regs[REG_R29] = STACK_INITIAL_VALUE_R29; + xcp->regs[REG_R30] = STACK_INITIAL_VALUE_R30; + xcp->regs[REG_R1] = STACK_INITIAL_VALUE_R1; + xcp->regs[REG_R2] = STACK_INITIAL_VALUE_R2; + xcp->regs[REG_LP] = 0x00000000; + + /* Keep System pre-configuration (HV, CUx, EBV) as current setting in PSW register */ + xcp->regs[REG_EIPSW] = (CURRENT_PSW_VALUE & INITIAL_PSW_MASK); + xcp->regs[REG_EIPC] = (uint32_t)tcb->start; + xcp->regs[REG_EIIC] = 0x00000000; + xcp->regs[REG_CTPSW] = (CURRENT_PSW_VALUE & INITIAL_PSW_MASK); + xcp->regs[REG_CTPC] = 0x00000000; + xcp->regs[REG_FPSR] = 0x00000000; + xcp->regs[REG_FPEPC] = 0x00000000; +} diff --git a/arch/rh850/src/common/rh850_internal.h b/arch/rh850/src/common/rh850_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..48efb67f58c4e6c75efe68060a91a4e8ddfe4620 --- /dev/null +++ b/arch/rh850/src/common/rh850_internal.h @@ -0,0 +1,190 @@ +/**************************************************************************** + * arch/renesas/src/common/rh850_internal.h + ****************************************************************************/ + +#ifndef ___ARCH_RH850_SRC_COMMON_UP_INTERNAL_H +#define ___ARCH_RH850_SRC_COMMON_UP_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Determine which (if any) console driver to use. NOTE that the naming + * implies that the console is a serial driver. That is usually the case, + * however, if no UARTs are enabled, the console could also be provided + * through some other device, such as an LCD. Architecture-specific logic + * will have to detect that case. + * + * If a console is enabled and no other console device is specified, then + * a serial console is assumed. + */ + +#ifndef CONFIG_DEV_CONSOLE +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +#else +# if defined(CONFIG_CONSOLE_SYSLOG) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* If some other device is used as the console, then the serial driver may + * still be needed. Let's assume that if the upper half serial driver is + * built, then the lower half will also be needed. There is no need for + * the early serial initialization in this case. + */ + +#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) +# define USE_SERIALDRIVER 1 +#endif + +/* Check if an interrupt stack size is configured */ + +#ifndef CONFIG_ARCH_INTERRUPTSTACK +# define CONFIG_ARCH_INTERRUPTSTACK 0 +#endif + +/* The SH stack must be aligned at word (4 byte) boundaries. If necessary + * frame_size must be rounded up to the next boundary + */ + +#define STACK_ALIGNMENT 4 + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT - 1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +#define rh850_savestate(regs) rh850_copystate(regs, up_current_regs()) + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*up_vector_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* This is the beginning of heap as provided from up_head.S. + * This is the first address in DRAM after the loaded + * program+bss+idle stack. The end of the heap is + * CONFIG_RAM_END + */ + +#endif + +/* Address of the saved user stack pointer */ + +#ifndef __ASSEMBLY__ +# if CONFIG_ARCH_INTERRUPTSTACK > 3 + extern uint8_t g_intstackalloc[]; + extern uint8_t g_intstacktop[]; +# endif +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Defined in files with the same name as the function */ + +void rh850_copystate(uint32_t *dest, uint32_t *src); +void rh850_dataabort(uint32_t *regs); +void rh850_decodeirq(uint32_t *regs); +uint32_t *rh850_doirq(int irq, uint32_t *regs); +void rh850_fullcontextrestore(uint32_t *regs) noreturn_function; +void rh850_syscall0(uint32_t *regs,uint32_t *saveregs) noreturn_function; +void rh850_prefetchabort(uint32_t *regs); +void rh850_sigdeliver(void); +// void rh850_syscall(uint32_t *regs); +void rh850_lowputc(char ch); +void rh850_lowputs(const char *str); + +/* Defined in xyz_vectors.S */ + +void rh850_vectorundefinsn(void); +void rh850_vectorswi(void); +void rh850_vectorprefetch(void); +void rh850_vectordata(void); +void rh850_vectoraddrexcptn(void); +void rh850_vectorirq(void); +void rh850_vectorfiq(void); + +/* Defined in xyz_serial.c */ + +#ifdef USE_EARLYSERIALINIT +void rh850_earlyconsoleinit(void); +#endif + +#ifdef USE_SERIALDRIVER +void rh850_serialinit(void); +#endif + +void rh850_ioportinit(void); + +void rh850_lowputc(char ch); + +/* Defined in board/xyz_lcd.c */ + +#ifdef CONFIG_SLCD_CONSOLE +void rh850_lcdinit(void); +void rh850_lcdputc(char ch); +#else +# define rh850_lcdinit() +# define rh850_lcdputc(ch) +#endif + +/* Defined in board/xyz_network.c */ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void rh850_netinitialize(void); +#else +# define rh850_netinitialize() +#endif + +/* USB */ + +#ifdef CONFIG_USBDEV +void rh850_usbinitialize(void); +void rh850_usbuninitialize(void); +#else +# define rh850_usbinitialize() +# define rh850_usbuninitialize() +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* ___ARCH_RH850_SRC_COMMON_UP_INTERNAL_H */ diff --git a/arch/rh850/src/common/rh850_ioport.c b/arch/rh850/src/common/rh850_ioport.c new file mode 100644 index 0000000000000000000000000000000000000000..9ac5eef5d1b267d56fb79618691fda9df667fc22 --- /dev/null +++ b/arch/rh850/src/common/rh850_ioport.c @@ -0,0 +1,1982 @@ +#include "bsp_api.h" +#include "r_ioport_api.h" +#include "r_ioport.h" + + +const ioport_extend_cfg_t g_ioport_cfg_extend = + { + .nf_cfg = + { + .nf_enable_cfg = + { + .noise_filter_enable_rlin = (0ULL), + .noise_filter_enable_rscan = (0ULL), + .noise_filter_enable_flxa = (0ULL), + .noise_filter_enable_sent0 = (0ULL), + .noise_filter_enable_sent1 = (0ULL), + .noise_filter_enable_psi5 = (0ULL), + .noise_filter_enable_pic_tapa = (0ULL), + .noise_filter_enable_adcj0 = (0ULL), + .noise_filter_enable_adcj1 = (0ULL), + .noise_filter_enable_adcj2 = (0ULL), + .noise_filter_enable_adck0 = (0ULL), + .noise_filter_enable_adck1 = (0ULL), + .noise_filter_enable_adck2 = (0ULL), + .noise_filter_enable_adck3 = (0ULL), + .noise_filter_enable_adcka = (0ULL), + .noise_filter_enable_rhsb = (0ULL), + .noise_filter_enable_enca = (0ULL), + .noise_filter_enable_taud0 = (0ULL), + .noise_filter_enable_taud1 = (0ULL), + .noise_filter_enable_taud2 = (0ULL), + .noise_filter_enable_taud3 = (0ULL), + .noise_filter_enable_tsg3 = (0ULL), + .noise_filter_enable_ecm = (0ULL), + .noise_filter_enable_tauj0 = (0ULL), + .noise_filter_enable_tauj1 = (0ULL), + .noise_filter_enable_tauj2 = (0ULL), + .noise_filter_enable_tauj3 = (0ULL), + .noise_filter_enable_pic_tsg = (0ULL), + .noise_filter_enable_emu = (0ULL), + .noise_filter_enable_ssif = (0ULL), + .noise_filter_enable_ospi0 = (0ULL), + .noise_filter_enable_esr0_irq0 = (0ULL), + .noise_filter_enable_esr0_nmi = (0ULL), + .noise_filter_enable_esr1_nmi = (0ULL), + }, + .nf_filter_cfg = + { + +#if BSP_FEATURE_IOPORT_NF_RLIN30 + [IOPORT_FILTER_SIGNAL_RLIN30RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RLIN31 + [IOPORT_FILTER_SIGNAL_RLIN31RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSCAN + [IOPORT_FILTER_SIGNAL_CAN0RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_CAN1RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_FLXA0 + [IOPORT_FILTER_SIGNAL_FLXA0RXDA] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_FLXA1 + [IOPORT_FILTER_SIGNAL_FLXA1RXDA] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT0 + [IOPORT_FILTER_SIGNAL_SENT0RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT1 + [IOPORT_FILTER_SIGNAL_SENT1RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT2 + [IOPORT_FILTER_SIGNAL_SENT2RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT3 + [IOPORT_FILTER_SIGNAL_SENT3RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT4 + [IOPORT_FILTER_SIGNAL_SENT4RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT5 + [IOPORT_FILTER_SIGNAL_SENT5RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT6 + [IOPORT_FILTER_SIGNAL_SENT6RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT7 + [IOPORT_FILTER_SIGNAL_SENT7RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT8 + [IOPORT_FILTER_SIGNAL_SENT8RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT9 + [IOPORT_FILTER_SIGNAL_SENT9RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT10 + [IOPORT_FILTER_SIGNAL_SENT10RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT11 + [IOPORT_FILTER_SIGNAL_SENT11RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT12 + [IOPORT_FILTER_SIGNAL_SENT12RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT13 + [IOPORT_FILTER_SIGNAL_SENT13RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT14 + [IOPORT_FILTER_SIGNAL_SENT14RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT15 + [IOPORT_FILTER_SIGNAL_SENT15RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT16 + [IOPORT_FILTER_SIGNAL_SENT16RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT17 + [IOPORT_FILTER_SIGNAL_SENT17RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT18 + [IOPORT_FILTER_SIGNAL_SENT18RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT19 + [IOPORT_FILTER_SIGNAL_SENT19RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT20 + [IOPORT_FILTER_SIGNAL_SENT20RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT21 + [IOPORT_FILTER_SIGNAL_SENT21RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT22 + [IOPORT_FILTER_SIGNAL_SENT22RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT23 + [IOPORT_FILTER_SIGNAL_SENT23RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT24 + [IOPORT_FILTER_SIGNAL_SENT24RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT25 + [IOPORT_FILTER_SIGNAL_SENT25RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT26 + [IOPORT_FILTER_SIGNAL_SENT26RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT27 + [IOPORT_FILTER_SIGNAL_SENT27RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT28 + [IOPORT_FILTER_SIGNAL_SENT28RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RSENT29 + [IOPORT_FILTER_SIGNAL_SENT29RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PSI50 + [IOPORT_FILTER_SIGNAL_PSI50RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PSI51 + [IOPORT_FILTER_SIGNAL_PSI51RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PSI52 + [IOPORT_FILTER_SIGNAL_PSI52RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PSI53 + [IOPORT_FILTER_SIGNAL_PSI53RX] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA0 + [IOPORT_FILTER_SIGNAL_INTTAPA0ESO_TAPA0ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA1 + [IOPORT_FILTER_SIGNAL_INTTAPA1ESO_TAPA1ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA2 + [IOPORT_FILTER_SIGNAL_INTTAPA2ESO_TAPA2ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA3 + [IOPORT_FILTER_SIGNAL_INTTAPA3ESO_TAPA3ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA4 + [IOPORT_FILTER_SIGNAL_INTTAPA4ESO_TAPA4ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TAPA5 + [IOPORT_FILTER_SIGNAL_INTTAPA5ESO_TAPA5ESO] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCJ0 + [IOPORT_FILTER_SIGNAL_ADCJ0TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ0TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ0TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ0TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ0TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCJ1 + [IOPORT_FILTER_SIGNAL_ADCJ1TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ1TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ1TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ1TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCJ1TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCJ2 + [IOPORT_FILTER_SIGNAL_ADCJ2TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCJ2TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCJ2TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCJ2TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCJ2TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCK0 + [IOPORT_FILTER_SIGNAL_ADCK0TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK0TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK0TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK0TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK0TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCK1 + [IOPORT_FILTER_SIGNAL_ADCK1TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK1TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK1TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK1TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK1TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCK2 + [IOPORT_FILTER_SIGNAL_ADCK2TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK2TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK2TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK2TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK2TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCK3 + [IOPORT_FILTER_SIGNAL_ADCK3TRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK3TRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK3TRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK3TRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, + [IOPORT_FILTER_SIGNAL_ADCK3TRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ADCKA + [IOPORT_FILTER_SIGNAL_ADCKATRG0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCKATRG1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCKATRG2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCKATRG3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_ADCKATRG4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_RHSB0 + [IOPORT_FILTER_SIGNAL_RHSB0EMRG] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_RHSB1 + [IOPORT_FILTER_SIGNAL_RHSB1EMRG] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_RHSB2 + [IOPORT_FILTER_SIGNAL_RHSB2EMRG] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_RHSB3 + [IOPORT_FILTER_SIGNAL_RHSB3EMRG] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1}, +#endif +#if BSP_FEATURE_IOPORT_NF_ENCA0 + [IOPORT_FILTER_SIGNAL_ENCA0TIN0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_ENCA0TIN1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ENCA1 + [IOPORT_FILTER_SIGNAL_ENCA1TIN0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_ENCA1TIN1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM0 + [IOPORT_FILTER_SIGNAL_ERRORIN0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM1 + [IOPORT_FILTER_SIGNAL_ERRORIN1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM2 + [IOPORT_FILTER_SIGNAL_ERRORIN2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM3 + [IOPORT_FILTER_SIGNAL_ERRORIN3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM4 + [IOPORT_FILTER_SIGNAL_ERRORIN4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM5 + [IOPORT_FILTER_SIGNAL_ERRORIN5] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM6 + [IOPORT_FILTER_SIGNAL_ERRORIN6] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_ECM7 + [IOPORT_FILTER_SIGNAL_ERRORIN7] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUD0 + [IOPORT_FILTER_SIGNAL_TAUD0I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I5] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I6] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I7] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I8] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I9] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I10] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I11] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I12] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I13] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I14] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD0I15] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUD1 + [IOPORT_FILTER_SIGNAL_TAUD1I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I5] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I6] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I7] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I8] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I9] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I10] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I11] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I12] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I13] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I14] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD1I15] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUD2 + [IOPORT_FILTER_SIGNAL_TAUD2I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I5] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I6] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I7] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I8] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I9] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I10] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I11] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I12] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I13] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I14] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD2I15] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUD3 + [IOPORT_FILTER_SIGNAL_TAUD3I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I4] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I5] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I6] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I7] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I8] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I9] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I10] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I11] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I12] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I13] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I14] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TAUD3I15] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUJ0 + [IOPORT_FILTER_SIGNAL_TAUJ0I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ0I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ0I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ0I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUJ1 + [IOPORT_FILTER_SIGNAL_TAUJ1I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ1I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ1I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ1I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUJ2 + [IOPORT_FILTER_SIGNAL_TAUJ2I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ2I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ2I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ2I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_TAUJ3 + [IOPORT_FILTER_SIGNAL_TAUJ3I0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ3I1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ3I2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, + [IOPORT_FILTER_SIGNAL_TAUJ3I3] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL}, +#endif +#if BSP_FEATURE_IOPORT_NF_PIC_TSG + [IOPORT_FILTER_SIGNAL_TSGTRG] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_EMU0 + [IOPORT_FILTER_SIGNAL_EM00_IN_A] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_EM00_IN_B] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_EM00_IN_Z] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_EMU1 + [IOPORT_FILTER_SIGNAL_EM10_IN_A] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_EM10_IN_B] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_EM10_IN_Z] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_OSPI0 + [IOPORT_FILTER_SIGNAL_OSPI0INT0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_OSPI0INT1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_OSPI0ECS0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_OSPI0ECS1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TSG30 + [IOPORT_FILTER_SIGNAL_TSG30PTSI0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG30PTSI1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG30PTSI2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG30CLKI] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TSG31 + [IOPORT_FILTER_SIGNAL_TSG31PTSI0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG31PTSI1] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG31PTSI2] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_TSG31CLKI] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_TSG32 + [IOPORT_FILTER_SIGNAL_TSG32CLKI] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_SSIF + [IOPORT_FILTER_SIGNAL_SSIF0BCK] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIF0LRCK_FS] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIF0RXD] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIFACK] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIF1BCK] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIF1LRCK_FS] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, + [IOPORT_FILTER_SIGNAL_SSIF1RXD] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ0 + [IOPORT_FILTER_SIGNAL_IRQ0] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ1 + [IOPORT_FILTER_SIGNAL_IRQ1] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ2 + [IOPORT_FILTER_SIGNAL_IRQ2] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ3 + [IOPORT_FILTER_SIGNAL_IRQ3] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ4 + [IOPORT_FILTER_SIGNAL_IRQ4] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ5 + [IOPORT_FILTER_SIGNAL_IRQ5] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ6 + [IOPORT_FILTER_SIGNAL_IRQ6] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ7 + [IOPORT_FILTER_SIGNAL_IRQ7] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ8 + [IOPORT_FILTER_SIGNAL_IRQ8] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ9 + [IOPORT_FILTER_SIGNAL_IRQ9] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ10 + [IOPORT_FILTER_SIGNAL_IRQ10] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ11 + [IOPORT_FILTER_SIGNAL_IRQ11] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ12 + [IOPORT_FILTER_SIGNAL_IRQ12] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ13 + [IOPORT_FILTER_SIGNAL_IRQ13] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ14 + [IOPORT_FILTER_SIGNAL_IRQ14] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ15 + [IOPORT_FILTER_SIGNAL_IRQ15] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ16 + [IOPORT_FILTER_SIGNAL_IRQ16] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ17 + [IOPORT_FILTER_SIGNAL_IRQ17] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ18 + [IOPORT_FILTER_SIGNAL_IRQ18] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ19 + [IOPORT_FILTER_SIGNAL_IRQ19] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ20 + [IOPORT_FILTER_SIGNAL_IRQ20] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ21 + [IOPORT_FILTER_SIGNAL_IRQ21] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ22 + [IOPORT_FILTER_SIGNAL_IRQ22] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ23 + [IOPORT_FILTER_SIGNAL_IRQ23] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ24 + [IOPORT_FILTER_SIGNAL_IRQ24] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ25 + [IOPORT_FILTER_SIGNAL_IRQ25] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ26 + [IOPORT_FILTER_SIGNAL_IRQ26] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ27 + [IOPORT_FILTER_SIGNAL_IRQ27] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ28 + [IOPORT_FILTER_SIGNAL_IRQ28] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ29 + [IOPORT_FILTER_SIGNAL_IRQ29] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ30 + [IOPORT_FILTER_SIGNAL_IRQ30] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ31 + [IOPORT_FILTER_SIGNAL_IRQ31] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ32 + [IOPORT_FILTER_SIGNAL_IRQ32] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ33 + [IOPORT_FILTER_SIGNAL_IRQ33] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ34 + [IOPORT_FILTER_SIGNAL_IRQ34] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ35 + [IOPORT_FILTER_SIGNAL_IRQ35] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ36 + [IOPORT_FILTER_SIGNAL_IRQ36] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ37 + [IOPORT_FILTER_SIGNAL_IRQ37] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ38 + [IOPORT_FILTER_SIGNAL_IRQ38] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ39 + [IOPORT_FILTER_SIGNAL_IRQ39] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ40 + [IOPORT_FILTER_SIGNAL_IRQ40] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ41 + [IOPORT_FILTER_SIGNAL_IRQ41] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ42 + [IOPORT_FILTER_SIGNAL_IRQ42] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ43 + [IOPORT_FILTER_SIGNAL_IRQ43] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ44 + [IOPORT_FILTER_SIGNAL_IRQ44] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ45 + [IOPORT_FILTER_SIGNAL_IRQ45] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ_NMI + [IOPORT_FILTER_SIGNAL_NMI] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_IRQ_ESR + [IOPORT_FILTER_SIGNAL_ESR0_IRQ0] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, + [IOPORT_FILTER_SIGNAL_ESR0_NMI] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, + [IOPORT_FILTER_SIGNAL_ESR1_NMI] = + { + .number_sample = IOPORT_FILTER_SAMPLE_2, + .sampling_clock = IOPORT_FILTER_CLOCK_DIV_1, + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP_NMI + [IOPORT_FILTER_SIGNAL_INTP_NMI] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP0 + [IOPORT_FILTER_SIGNAL_INTP0] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP1 + [IOPORT_FILTER_SIGNAL_INTP1] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP2 + [IOPORT_FILTER_SIGNAL_INTP2] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP3 + [IOPORT_FILTER_SIGNAL_INTP3] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP4 + [IOPORT_FILTER_SIGNAL_INTP4] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP5 + [IOPORT_FILTER_SIGNAL_INTP5] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP6 + [IOPORT_FILTER_SIGNAL_INTP6] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP7 + [IOPORT_FILTER_SIGNAL_INTP7] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP8 + [IOPORT_FILTER_SIGNAL_INTP8] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP9 + [IOPORT_FILTER_SIGNAL_INTP9] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP10 + [IOPORT_FILTER_SIGNAL_INTP10] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP11 + [IOPORT_FILTER_SIGNAL_INTP11] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP12 + [IOPORT_FILTER_SIGNAL_INTP12] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP13 + [IOPORT_FILTER_SIGNAL_INTP13] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP14 + [IOPORT_FILTER_SIGNAL_INTP14] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP15 + [IOPORT_FILTER_SIGNAL_INTP15] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP16 + [IOPORT_FILTER_SIGNAL_INTP16] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP17 + [IOPORT_FILTER_SIGNAL_INTP17] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP18 + [IOPORT_FILTER_SIGNAL_INTP18] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP19 + [IOPORT_FILTER_SIGNAL_INTP19] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP20 + [IOPORT_FILTER_SIGNAL_INTP20] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP21 + [IOPORT_FILTER_SIGNAL_INTP21] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP22 + [IOPORT_FILTER_SIGNAL_INTP22] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP23 + [IOPORT_FILTER_SIGNAL_INTP23] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP24 + [IOPORT_FILTER_SIGNAL_INTP24] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP25 + [IOPORT_FILTER_SIGNAL_INTP25] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP26 + [IOPORT_FILTER_SIGNAL_INTP26] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP27 + [IOPORT_FILTER_SIGNAL_INTP27] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP28 + [IOPORT_FILTER_SIGNAL_INTP28] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP29 + [IOPORT_FILTER_SIGNAL_INTP29] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP30 + [IOPORT_FILTER_SIGNAL_INTP30] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP31 + [IOPORT_FILTER_SIGNAL_INTP31] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP32 + [IOPORT_FILTER_SIGNAL_INTP32] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP33 + [IOPORT_FILTER_SIGNAL_INTP33] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP34 + [IOPORT_FILTER_SIGNAL_INTP34] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP35 + [IOPORT_FILTER_SIGNAL_INTP35] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP36 + [IOPORT_FILTER_SIGNAL_INTP36] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP37 + [IOPORT_FILTER_SIGNAL_INTP37] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP38 + [IOPORT_FILTER_SIGNAL_INTP38] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif +#if BSP_FEATURE_IOPORT_NF_INTP39 + [IOPORT_FILTER_SIGNAL_INTP39] = + { + .detection_mode = IOPORT_FILTER_DETECTION_DISABLE_EDGE, + .bypass_mode = IOPORT_FILTER_SELECT_SIGNAL, + }, +#endif + }, + }, + .lvds_cfg = + {.lvdsctrl_a = (0ULL), + .lvdsctrl_b = (0ULL), + .lvdsctrl_c = (0ULL), + .lvdsctrl_d = (0ULL), + .lvdsctrl_e = (0ULL), + .lvdsctrl_f = (0ULL)}, + .pulvsel5_cfg = (0ULL), +}; + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = + { + { + .pin = BSP_IO_PORT_P00_PIN_1, // led0 + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + //.pin = BSP_IO_PORT_P01_PIN_13, // RLIN30TX + //.pin_cfg = ((uint32_t)IOPORT_ALT_OUT8 | (uint32_t)IOPORT_CFG_DRIVE_MEDIUM | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN), + .pin = BSP_IO_PORT_P02_PIN_2, // RLIN30TX + .pin_cfg = ((uint32_t)IOPORT_ALT_OUT2 | (uint32_t)IOPORT_CFG_DRIVE_MEDIUM | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN), + }, + { + //.pin = BSP_IO_PORT_P01_PIN_8, // RLIN30RX + //.pin_cfg = ((uint32_t)IOPORT_ALT_IN8 | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN), + .pin = BSP_IO_PORT_P02_PIN_3, // RLIN30RX + .pin_cfg = ((uint32_t)IOPORT_ALT_IN6 | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN), + + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = + {.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + .p_extend = &g_ioport_cfg_extend}; + +ioport_instance_ctrl_t g_ioport_ctrl; + +void rh850_ioportinit(void) +{ + /* Configure pins. */ + R_IOPORT_PinsCfg(&g_ioport_ctrl, &g_bsp_pin_cfg); +} diff --git a/arch/rh850/src/common/rh850_irq.c b/arch/rh850/src/common/rh850_irq.c new file mode 100644 index 0000000000000000000000000000000000000000..c12913d14de4dee0f94a9406a16d8c162952ec6d --- /dev/null +++ b/arch/rh850/src/common/rh850_irq.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm/src/samd5e5/sam_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#if (CONFIG_BSP_FSP_SUPPORT) +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif + + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ +#define INTOSTM0TINT 360 + +#define IRQ_UNMAPPED 0xff + +static void *archctxhandle[1]; + + +void up_set_contexthdl(void *const ctxhdl) +{ + irqstate_t irq_state = up_irq_save(); + + archctxhandle[0] = ctxhdl; + up_irq_restore(irq_state); + return; +} + +void *up_get_contexthdl() +{ + return archctxhandle[0]; +} + + +void up_irqinitialize(void) +{ + #if (CONFIG_BSP_FSP_SUPPORT) + /* Initialize interrupt */ + bsp_irq_cfg(); + #endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + RH850_IRQ_DisableIRQ( irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + RH850_IRQ_EnableIRQ(irq); +} +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + + RH850_IRQ_SetPriority((uint32_t) irq, (uint32_t) priority); + return OK; +} +#endif + + + +void up_trigger_irq(int irq, cpu_set_t cpuset) +{ + +} \ No newline at end of file diff --git a/arch/rh850/src/common/rh850_lowputs.c b/arch/rh850/src/common/rh850_lowputs.c new file mode 100644 index 0000000000000000000000000000000000000000..e42d7ce33510f011527e9630ef3493a7a74709d6 --- /dev/null +++ b/arch/rh850/src/common/rh850_lowputs.c @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_lowputs.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rh850_lowputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void rh850_lowputs(const char *str) +{ + while (*str) + { + rh850_lowputc(*str++); + } +} diff --git a/arch/rh850/src/common/rh850_mdelay.c b/arch/rh850/src/common/rh850_mdelay.c new file mode 100644 index 0000000000000000000000000000000000000000..80b0644dcabc6ae6b9438fc24f2f6afc4d4a3e6f --- /dev/null +++ b/arch/rh850/src/common/rh850_mdelay.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_mdelay.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + volatile int i; + volatile int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} diff --git a/arch/rh850/src/common/rh850_nputs.c b/arch/rh850/src/common/rh850_nputs.c new file mode 100644 index 0000000000000000000000000000000000000000..cb6f17af020b887142fcc52cf7191b1cc6c63bd5 --- /dev/null +++ b/arch/rh850/src/common/rh850_nputs.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_nputs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_nputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_nputs(const char *str, size_t len) +{ + while (len-- > 0 && *str) + { + up_putc(*str++); + } +} diff --git a/arch/rh850/src/common/rh850_registerdump.c b/arch/rh850/src/common/rh850_registerdump.c new file mode 100644 index 0000000000000000000000000000000000000000..6ea1d7a6d4ebe7ab94437c2e300357a0db236673 --- /dev/null +++ b/arch/rh850/src/common/rh850_registerdump.c @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/common/arm_registerdump.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + +/**************************************************************************** + * Name: up_dump_register + ****************************************************************************/ + +void up_dump_register(void *dumpregs) +{ + volatile uint32_t *regs = dumpregs ? dumpregs : up_current_regs(); + ///< Will be further developed +} diff --git a/arch/rh850/src/common/rh850_releasestack.c b/arch/rh850/src/common/rh850_releasestack.c new file mode 100644 index 0000000000000000000000000000000000000000..2cb4f8c19b3872e88016b1a89ab24aadbd177f6a --- /dev/null +++ b/arch/rh850/src/common/rh850_releasestack.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_releasestack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parameters: + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr && (dtcb->flags & TCB_FLAG_FREE_STACK)) + { +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + kmm_free(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + kumm_free(dtcb->stack_alloc_ptr); + } + } + + /* Mark the stack freed */ + + dtcb->flags &= ~TCB_FLAG_FREE_STACK; + dtcb->stack_alloc_ptr = NULL; + dtcb->stack_base_ptr = NULL; + dtcb->adj_stack_size = 0; +} diff --git a/arch/rh850/src/common/rh850_schedulesigaction.c b/arch/rh850/src/common/rh850_schedulesigaction.c new file mode 100644 index 0000000000000000000000000000000000000000..e0df1d9a16b4a8d481b5dd953bf79020be7be55f --- /dev/null +++ b/arch/rh850/src/common/rh850_schedulesigaction.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/arm/src/armv8-m/arm_schedulesigaction.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "sched/sched.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'sigdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + * Assumptions: + * Called from critical section + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb) +{ + ///< Will be further developed + while (1); +} diff --git a/arch/rh850/src/common/rh850_serial.c b/arch/rh850/src/common/rh850_serial.c new file mode 100644 index 0000000000000000000000000000000000000000..96b0fedf852a13fd331b8cfc8a3a6c8725f14871 --- /dev/null +++ b/arch/rh850/src/common/rh850_serial.c @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2025 Li Auto Inc. and its affiliates + * Licensed under the Apache License, Version 2.0(the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "rh850_internal.h" +#include "rh850_serial.h" + +#include "r_rlin3_uart.h" +#include "r_uart_api.h" + +#undef uint32 +#define uint32 uint32_t + + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#define CONSOLE_DEV g_uart0port /* UART0 is console */ +#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); + +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +void up_uart_rx_handler(void); +#else +static int up_txiinterrupt(int irq, void *context, void *arg); +static int up_rxiinterrupt(int irq, void *context, void *arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = + { + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txready, + .recvbuf = NULL, + .sendbuf = NULL, +}; + +/* I/O buffers */ +#ifdef CONFIG_U2BX_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; + +static struct up_dev_s g_uart0priv = + { + //.uartbase = 0xFFC7C000, // LIN3/UART 0 base + .uartbase = 0xFF89B100, // LIN3/UART1 base +}; + +static __percpu_data uart_dev_t g_uart0port = + { + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = &g_uart0rxbuffer[0], + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = &g_uart0txbuffer[0], + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#define g_uart0port this_cpu_var(g_uart0port) +#endif + +static void r_rlin3_uart_callback(uart_callback_args_t *p_args) +{ + (void)p_args; +} + +baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.208% error. */ + .bit_sampling = 10, + .prescaler_clock = 0, + .prescaler = 62}; + +/** UART extended configuration for UARTonRLIN3 HAL driver */ +const rlin3_uart_extended_cfg_t g_uart0_cfg_extend = + {.operation_enable = UART_DIR_RX_TX, + .enb_bit_err = 0, + .enb_overrun_err = 0, + .enb_frame_err = 0, + .inter_byte_space = 0, + .noise_cancel = RLIN3_UART_NOISE_CANCELLATION_DISABLE, + .p_baud_setting = &g_uart0_baud_setting, + .expansion_bit_enable = RLIN3_UART_EXPANSION_BIT_DISABLE, + .expansion_bit_comparison = RLIN3_UART_EXPANSION_BIT_COMPARISON_DISABLE, + .timing_select = UART_COMPLETION, + .transfer_order = UART_LSB_FISRT, + .invert_input = UART_NORMAL_INPUT, + .invert_output = UART_NORMAL_OUTPUT, + .tx_buffer = 0, +#if (BSP_FEATURE_DEVICE_HAS_INTSEL_IRQ) + .intsel_irq_cfg = BSP_INTSEL_DISABLED +#endif +}; + +/** UART interface configuration */ +uart_cfg_t g_uart0_cfg = + { + .channel = 1, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .data_bits = UART_DATA_BITS_8, + .p_callback = r_rlin3_uart_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, + .p_transfer_tx = NULL, + .p_transfer_rx = NULL, + .rxi_ipl = (12), + .txi_ipl = (12), + .eri_ipl = (12), + //.rxi_irq = VECTOR_NUMBER_INTRLIN30UR1, //LIN3/UART0 + //.txi_irq = VECTOR_NUMBER_INTRLIN30UR0, + //.eri_irq = VECTOR_NUMBER_INTRLIN30UR2}; + .rxi_irq = VECTOR_NUMBER_INTRLIN31UR1, //LIN3/UART1 + .txi_irq = VECTOR_NUMBER_INTRLIN31UR0, //LIN3/UART1 + .eri_irq = VECTOR_NUMBER_INTRLIN31UR2}; //LIN3/UART1 + +rlin3_uart_instance_ctrl_t g_uart0_ctrl; + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + fsp_err_t err; + + if (g_uart0_ctrl.open) + { + return OK; + // R_RLIN3_UART_Close(&g_uart0_ctrl); + } + + err = R_RLIN3_UART_Open(&g_uart0_ctrl, &g_uart0_cfg); + + return (err == FSP_SUCCESS) ? OK : -1; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + (void)dev; + + R_RLIN3_UART_Close(&g_uart0_ctrl); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + (void)dev; + +#if !defined(CONFIG_RT_FRAMEWORK) || (CONFIG_RT_FRAMEWORK == 0) + //irq_attach(622, (xcpt_t)up_rxiinterrupt, NULL); + //up_enable_irq(622); + irq_attach(627, (xcpt_t)up_rxiinterrupt, NULL); + up_enable_irq(627); +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + (void)dev; + +#if !defined(CONFIG_RT_FRAMEWORK) || (CONFIG_RT_FRAMEWORK == 0) + //up_disable_irq(622); + //irq_detach(622); + up_disable_irq(627); + irq_detach(627); +#endif +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* get reception data */ + uint32_t lur_addr = priv->uartbase + U2BX_LIN3_UART_LURDR_OFFSET; + uint16_t lur_value = (uint16_t)getreg16(lur_addr); + + /* get error status */ + uint32_t lest_addr = priv->uartbase + U2BX_LIN3_UART_LEST_OFFSET; + uint8_t lest_value = (uint8_t)getreg8(lest_addr); + + /* clear all error flags */ + putreg8(lest_value & 0x7D, lest_addr); + + /* return actual data */ + return (int)(lur_value & 0xFF); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + if (enable) + { + // todo + } + else + { + // todo + } +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t lst_addr = priv->uartbase + U2BX_LIN3_UART_LST_OFFSET; + uint8_t lst_value = (uint8_t)getreg8(lst_addr) & R_RLN30_LST_URS_Msk; + + return lst_value != 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Wait for FIFO */ + if (dev == &CONSOLE_DEV) + { + up_putc(ch); + return; + } +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Issue a transmit when TDR is empty, to generate the first interrupt */ + if (up_txready(dev)) + { + uart_xmitchars(dev); + } +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + uint32_t lst_addr = priv->uartbase + U2BX_LIN3_UART_LST_OFFSET; + uint8_t lst_value = (uint8_t)getreg8(lst_addr) & (R_RLN30_LST_UTS_Msk | R_RLN30_LST_FTC_Msk); + + return lst_value == 0; +} + +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +void up_uart_rx_handler(void) +{ + struct uart_dev_s *dev = &g_uart0port; + uint8_t data; + + if (up_rxavailable(dev)) + { + uart_recvchars(dev); + } + + if (up_txready(dev)) + { + uart_xmitchars(dev); + } +} +#else + +/**************************************************************************** + * Name: up_txiinterrupt + * + * Description: + * This is the USART TX interrupt handler. + * + ****************************************************************************/ + +static int up_txiinterrupt(int irq, void *context, void *arg) +{ + // TBD + return OK; +} + +/**************************************************************************** + * Name: up_rxiinterrupt + * + * Description: + * This is the USART RX interrupt handler. + * + ****************************************************************************/ + +static int up_rxiinterrupt(int irq, void *context, void *arg) +{ + // todo + return OK; +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: u2bx_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that u2bx_earlyserialinit was called previously. + * + ****************************************************************************/ + +void rh850_serialinit(void) +{ + up_setup(&CONSOLE_DEV); + /* Register the console */ +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; + + while (!up_txready(&CONSOLE_DEV)) + { + // todo, handle timeout + }; + + uint32_t lut_reg = priv->uartbase + U2BX_LIN3_UART_LUTDR_OFFSET; + putreg16(ch & 0xff, lut_reg); +} diff --git a/arch/rh850/src/common/rh850_serial.h b/arch/rh850/src/common/rh850_serial.h new file mode 100644 index 0000000000000000000000000000000000000000..613dfbeaa00e36e0d96c640bc15d430eac8251a7 --- /dev/null +++ b/arch/rh850/src/common/rh850_serial.h @@ -0,0 +1,127 @@ +/* */ + +#ifndef __ARCH_ARM_SRC_U2BX_U2BX_SERIAL_H +#define __ARCH_ARM_SRC_U2BX_U2BX_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Registers offset */ +#define U2BX_LIN3_UART_LWBR_OFFSET 0x01 /* Baud Rate Select Register */ +# define U2BX_LIN3_UART_LWBR_NSPB_POS 4 +# define U2BX_LIN3_UART_LWBR_LPRS_POS 1 + +#define U2BX_LIN3_UART_LBRP_OFFSET 0x02 /* Baud Rate Prescaler Register */ + +#define U2BX_LIN3_UART_LMD_OFFSET 0x08 /* Mode Register */ +# define U2BX_LIN3_UART_LMD_LRDNFS_POS 5 /* Noise filter bit */ + +#define U2BX_LIN3_UART_LBFC_OFFSET 0x09 /* Configuration Register */ +# define U2BX_LIN3_UART_LBFC_UTPS_POS 6 /* Output Polarity bit */ +# define U2BX_LIN3_UART_LBFC_URPS_POS 5 /* Input Polarity bit */ +# define U2BX_LIN3_UART_LBFC_UPS_POS 3 /* Parity bits */ +# define U2BX_LIN3_UART_LBFC_USBLS_POS 2 /* Stop Bit Length bit */ +# define U2BX_LIN3_UART_LBFC_UBOS_POS 1 /* Transfer Format Order bit */ +# define U2BX_LIN3_UART_LBFC_UBLS_POS 0 /* Character Length bit */ + +#define U2BX_LIN3_UART_LSC_OFFSET 0x0A /* Space Configuration Register */ + +#define U2BX_LIN3_UART_LEDE_OFFSET 0x0D /* Error Detection Enable Register */ +# define U2BX_LIN3_UART_LEDE_FERE_POS 3 /* Framing Error Detection Enable bit */ +# define U2BX_LIN3_UART_LEDE_OERE_POS 2 /* Overrun Error Detection Enable bit */ +# define U2BX_LIN3_UART_LEDE_BERE_POS 0 /* Bit Error Detection Enable bit */ + +#define U2BX_LIN3_UART_LCUC_OFFSET 0x0E /* Control Register */ +#define U2BX_LIN3_UART_LTRC_OFFSET 0x10 /* Transmission Control Register */ +# define U2BX_LIN3_UART_LTRC_RTS_POS 1 /* Transmission Start bit */ + +#define U2BX_LIN3_UART_LMST_OFFSET 0x11 /* Mode Status Register */ +#define U2BX_LIN3_UART_LST_OFFSET 0x12 /* Status Register */ +#define R_RLN30_LST_UTS_Msk (0x10UL) +#define R_RLN30_LST_FTC_Msk (0x1UL) +#define R_RLN30_LST_URS_Msk (0x20UL) +# define U2BX_LIN3_UART_LST_URS_POS 5 /* Reception Status Flag bit */ +# define U2BX_LIN3_UART_LST_UTS_POS 4 /* Transmission Status Flag bit */ +# define U2BX_LIN3_UART_LST_ERR_POS 3 /* Error Detection Flag bit */ +# define U2BX_LIN3_UART_LST_FTC_POS 0 /* Successful Buffer Transmission Flag bit */ +#define U2BX_LIN3_UART_LEST_OFFSET 0x13 /* Error Status Register */ + +#define U2BX_LIN3_UART_LDFC_OFFSET 0x14 /* Data Field Configuration Register */ +# define U2BX_LIN3_UART_LDFC_UTSW_POS 5 /* Transmission Start Wait bit */ +# define U2BX_LIN3_UART_LDFC_MDL_POS 0 /* Buffer Data Length Select bit */ + +#define U2BX_LIN3_UART_LIDB_OFFSET 0x15 /* ID Buffer Register */ +#define U2BX_LIN3_UART_LUDB0_OFFSET 0x17 /* Data Buffer 0 Register */ +#define U2BX_LIN3_UART_LDBR1_OFFSET 0x18 /* Data Buffer 1 Register */ +#define U2BX_LIN3_UART_LDBR2_OFFSET 0x19 /* Data Buffer 2 Register */ +#define U2BX_LIN3_UART_LDBR3_OFFSET 0x1A /* Data Buffer 3 Register */ +#define U2BX_LIN3_UART_LDBR4_OFFSET 0x1B /* Data Buffer 4 Register */ +#define U2BX_LIN3_UART_LDBR5_OFFSET 0x1C /* Data Buffer 5 Register */ +#define U2BX_LIN3_UART_LDBR6_OFFSET 0x1D /* Data Buffer 6 Register */ +#define U2BX_LIN3_UART_LDBR7_OFFSET 0x1E /* Data Buffer 7 Register */ +#define U2BX_LIN3_UART_LDBR8_OFFSET 0x1F /* Data Buffer 8 Register */ + +#define U2BX_LIN3_UART_LUOER_OFFSET 0x20 /* Operation Enable Register */ +# define U2BX_LIN3_UART_LUOER_UROE_POS 1 /* Reception Enable bit */ +# define U2BX_LIN3_UART_LUOER_UTOE_POS 0 /* Transmission Enable bit */ + +#define U2BX_LIN3_UART_LUOR1_OFFSET 0x21 /* Option Register 1 */ +# define U2BX_LIN3_UART_LUOR1_UTIGTS_POS 3 /* TXI Timing bit */ + +#define U2BX_LIN3_UART_LUTDR_OFFSET 0x24 /* Transmission Data Register */ +#define U2BX_LIN3_UART_LURDR_OFFSET 0x26 /* Reception Data Register */ +#define U2BX_LIN3_UART_LUWTDR_OFFSET 0x28 /* Wait Transmission Data Register */ + +/* Register Preset Value */ +/* Uart control */ +#define U2BX_LCUC_LIN_RESET 0x00 +#define U2BX_LCUC_LIN_RESET_CANCELED 0x01 + +/* Parity */ +#define U2BX_PARITY_DISABLE 0x0 +#define U2BX_PARITY_EVEN 0x1 +#define U2BX_PARITY_ODD 0x3 + +/* Expansion bit */ +#define U2BX_LUOR1_EXPANSION_DISABLE 0x00 + +/* Uart Mode */ +#define U2BX_LMD_UART_MODE 0x01 + +/* Default data transmission configuration */ +#define U2BX_LDFC_1BYTE_NO_WAIT \ + (0 << U2BX_LIN3_UART_LDFC_UTSW_POS | \ + 1 << U2BX_LIN3_UART_LDFC_MDL_POS) + +/* Enable TX-RX */ +#define U2BX_UART_ENABLE_TX (1 << U2BX_LIN3_UART_LUOER_UTOE_POS) +#define U2BX_UART_ENABLE_RX (1 << U2BX_LIN3_UART_LUOER_UROE_POS) +#define U2BX_UART_ENABLE_TX_RX (U2BX_UART_ENABLE_TX | U2BX_UART_ENABLE_RX) + +/* Start transmission */ +#define U2BX_UART_TX_START (1 << U2BX_LIN3_UART_LTRC_RTS_POS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif \ No newline at end of file diff --git a/arch/rh850/src/common/rh850_stackframe.c b/arch/rh850/src/common/rh850_stackframe.c new file mode 100644 index 0000000000000000000000000000000000000000..a64bebdb4a1229017b8e883409d5a293a5ac28ba --- /dev/null +++ b/arch/rh850/src/common/rh850_stackframe.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_stackframe.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +void *up_stack_frame(struct tcb_s *tcb, size_t frame_size) +{ + void *ret; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + ret = tcb->stack_base_ptr; + memset(ret, 0, frame_size); + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = (uint8_t *)tcb->stack_base_ptr + frame_size; + tcb->adj_stack_size -= frame_size; + + /* And return a pointer to allocated memory */ + + return ret; +} diff --git a/arch/rh850/src/common/rh850_switchcontext.c b/arch/rh850/src/common/rh850_switchcontext.c new file mode 100644 index 0000000000000000000000000000000000000000..55915b742a8655637933fa0f8cf36011ea1ed680 --- /dev/null +++ b/arch/rh850/src/common/rh850_switchcontext.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_switchcontext.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "clock/clock.h" +#include "rh850_internal.h" + +/**************************************************************************** + * Static Functions + ****************************************************************************/ +static inline uint32_t __getIPSR(); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_switch_context + * + * Description: + * A task is currently in the ready-to-run list but has been prepped + * to execute. Restore its context, and start execution. + * + * Input Parameters: + * tcb: Refers to the head task of the ready-to-run list + * which will be executed. + * rtcb: Refers to the running task which will be blocked. + * + ****************************************************************************/ + +void up_switch_context(struct tcb_s *tcb, struct tcb_s *rtcb) +{ + /* Are we in an interrupt handler? */ + if (up_current_regs()) + { + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_set_current_regs(tcb->xcp.regs); // <=== Keep + + } + + /* No, then we will need to perform the user context switch */ + + /* We are not in an interrupt handler. Copy the user C context + * into the TCB of the task that was previously active. if + * up_saveusercontext returns a non-zero value, then this + * is really the previously running task restarting! + */ + + else + { + while(0 != __getIPSR()); /* Wait until all current interrupts + released before entering TRAP */ + __asm__ volatile ("trap 0"); ///< Switch context via trap + } +} + +/* Return the current interrupt priority presenting */ +static inline uint32_t __getIPSR() +{ + uint32_t result; + __asm__ volatile ("stsr 10, %0, 2" : "=r" (result) :: "memory"); + return result; +} \ No newline at end of file diff --git a/arch/rh850/src/common/rh850_timerisr.c b/arch/rh850/src/common/rh850_timerisr.c new file mode 100644 index 0000000000000000000000000000000000000000..8248c5ee5ab86b19156b68e9377d279a910dd188 --- /dev/null +++ b/arch/rh850/src/common/rh850_timerisr.c @@ -0,0 +1,302 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_initialize.c + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "rh850_internal.h" + +#if CONFIG_BSP_FSP_SUPPORT +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#define OSTM_EIC_ADDR (0xfff802d0) +#define OSTMCMP_ADDR (0xffbf0000) +#define OSTMCNT_ADDR (0xffbf0004) +#define OSTMCTL_ADDR (0xffbf0020) +#define OSTMTS_ADDR (0xffbf0014) +#define OSTMTT_ADDR (0xffbf0018) + +/* OSTM Count Start Trigger Register (OSTMnTS) */ +#define OSTM_COUNTER_START (0x01U) /* Starts the counter */ + +/* OSTM Count Stop Trigger Register (OSTMnTT) */ +#define OSTM_COUNTER_STOP (0x01U) /* Stops the counter */ + +/* OSTM Control Register (OSTMnCTL) */ +#define OSTM_MODE_INTERVAL_TIMER (0x00U) +#define OSTM_MODE_FREE_RUNNING (0x02U) + +/* Disables or Enable the interrupts when counting starts */ +#define OSTM_START_INTERRUPT_DISABLE (0x00U) +#define OSTM_START_INTERRUPT_ENABLE (0x01U) + +/* Enable OSTM Interrupt*/ +#define OSTM_INTERRUPT_ENABLE (0x80U) + +/* Interrupt vector method select (TBxxx) */ +#define INT_DIRECT_VECTOR (0x00U) +#define INT_TABLE_VECTOR (0x40U) + +#ifndef CONFIG_TIMER_INT_PRIORITY +#define CONFIG_TIMER_INT_PRIORITY (15) +#endif + +#ifndef CONFIG_TIMER_CLOCK_HZ +#define CONFIG_TIMER_CLOCK_HZ (80000000) +#endif + +#ifndef CONFIG_TICK_RATE_HZ +#define CONFIG_TICK_RATE_HZ (1000) +#endif + +#ifndef CONFIG_IRQ_OSTM +#define CONFIG_IRQ_OSTM 360 +#endif +/** + * @brief Execute dummy read and syncp for EIC register + * @details Dummy read on the register and SYNCP + * @param [in] reg Pointer to register address + */ +#define BSP_INT_IOREG_DUMMY_READ_SYNCP(reg) \ + do \ + { \ + volatile uint32_t dummy = (reg); \ + SYNCP(); \ + (void)dummy; \ + } while (0) + +struct rh850_timer_s +{ + uint32_t frequency; /* Frequency of the timer */ + uint32_t cout_per_cycle; /* Counter counts per OS tick */ + uint64_t cycles; /* Total cycles since timer start */ + uint64_t ticks; /* Total ticks since timer start */ +}; + +static struct rh850_timer_s g_timer; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint64_t current_usec(void) +{ + uint64_t ticks, us; + + // get total ticks +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) + ticks = g_timer.ticks + (uint64_t)getreg32(OSTMCNT_ADDR); +#else + ticks = ((uint64_t)g_timer.cycles * g_timer.cout_per_cycle) + (uint64_t)getreg32(OSTMCNT_ADDR); +#endif + + // compute microseconds + us = (ticks / g_timer.frequency) * USEC_PER_SEC; + + return us; +} + +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +/**************************************************************************** + * Name: up_systick_isr_handler + * + * Returned Value: + * Always returns OK + * + ****************************************************************************/ +void up_systick_isr_handler(void) +{ + g_timer.ticks += (uint64_t)getreg32(OSTMCMP_ADDR); +} +#else +/**************************************************************************** + * Function: rh850_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various ions + * of the systems. + * + ****************************************************************************/ +static int rh850_timerisr(int irq, uint32_t *regs, void *arg) +{ + g_timer.cycles++; + + /* Process timer interrupt */ + nxsched_process_timer(); + + return OK; +} + #endif + + +static clock_t rh850_hrtimer_current(struct hrtimer_queue_s *queue); +static void rh850_hrtimer_set_expire(struct hrtimer_queue_s *queue, clock_t value); +static void rh850_hrtimer_start(struct hrtimer_queue_s *queue); +static void rh850_hrtimer_trigger(struct hrtimer_queue_s *queue); + +static const struct hrtimer_ops_s g_rh850_hrtimer_ops = { + .current = rh850_hrtimer_current, + .set_expire = rh850_hrtimer_set_expire, + .start = rh850_hrtimer_start, + .trigger = rh850_hrtimer_trigger, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ +void up_timer_initialize(void) +{ + volatile uint16_t *pulOSTMIntReg; + g_timer.frequency = CONFIG_TIMER_CLOCK_HZ; + g_timer.cout_per_cycle = (CONFIG_TIMER_CLOCK_HZ / USEC_PER_SEC) * USEC_PER_TICK - 1; + + /* Set OSTM control setting + * Used as system timer and uptime source. + */ + *((volatile uint32_t *)OSTMCTL_ADDR) = + (OSTM_INTERRUPT_ENABLE | OSTM_MODE_INTERVAL_TIMER | OSTM_START_INTERRUPT_DISABLE); + *((volatile uint32_t *)OSTMCMP_ADDR) = g_timer.cout_per_cycle - 1; + + /* Interrupt configuration for OSTM Timer */ +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) + up_hrtimer_set_ops(&g_rh850_hrtimer_ops); +#else + /* Setup interrupt and enable */ + RH850_IRQ_SetPriority(CONFIG_IRQ_OSTM, CONFIG_TIMER_INT_PRIORITY); + irq_attach(CONFIG_IRQ_OSTM, (xcpt_t)rh850_timerisr, NULL); + up_enable_irq(CONFIG_IRQ_OSTM); +#endif + +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * the architecture-specific timer was initialized). This function is + * functionally equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(FAR struct timespec *ts) +{ + uint64_t usec = current_usec(); + + ts->tv_sec = usec / USEC_PER_SEC; + ts->tv_nsec = (usec % USEC_PER_SEC) * NSEC_PER_USEC; + + return OK; +} + +int up_timer_gettick(FAR clock_t *ticks) +{ + uint64_t usec = current_usec(); + + *ticks = (clock_t)(usec / USEC_PER_TICK); + + return OK; +} + +void up_timer_getmask(FAR clock_t *mask) +{ + *mask = UINT32_MAX; + return; +} + +int up_timer_value(FAR clock_t *ticks) +{ + uint64_t usec = current_usec(); + + *ticks = (clock_t)(usec / USEC_PER_TICK); + + return OK; +} + +uint32_t up_timer_freq(void) +{ + return 80000000; +} +static clock_t rh850_hrtimer_current(struct hrtimer_queue_s *queue) +{ + /* get OSTM ticks from boot */ + uint32_t cnt = getreg32(OSTMCNT_ADDR); + + return g_timer.ticks + (uint64_t)cnt; +} +static void rh850_hrtimer_set_expire(struct hrtimer_queue_s *queue, clock_t value) +{ + /* set OSTM compare value */ + uint64_t cmp = value - g_timer.ticks; + putreg32((uint32_t)cmp, OSTMCMP_ADDR); +} + +static void rh850_hrtimer_start(struct hrtimer_queue_s *queue) +{ + /* Enable OSTM operation */ + *((volatile uint32_t *)OSTMTT_ADDR) = OSTM_COUNTER_STOP; + g_timer.ticks = 0; + g_timer.cycles = 0; + *((volatile uint32_t *)OSTMTS_ADDR) = OSTM_COUNTER_START; +} + +static void rh850_hrtimer_trigger(struct hrtimer_queue_s *queue) +{ + /* Trigger OSTM interrupt */ + RH850_IRQ_GetActiveByPE((uint8_t) 0, (uint32_t) 360); +} diff --git a/arch/rh850/src/common/rh850_udelay.c b/arch/rh850/src/common/rh850_udelay.c new file mode 100644 index 0000000000000000000000000000000000000000..133b351d60354de51a796e881b2c298078fe94c0 --- /dev/null +++ b/arch/rh850/src/common/rh850_udelay.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_udelay.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "bsp_api.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay inline for the requested number of microseconds. NOTE: Because + * of all of the setup, several microseconds will be lost before the actual + * timing loop begins. Thus, the delay will always be a few microseconds + * longer than requested. + * + * *** NOT multi-tasking friendly *** + * + ****************************************************************************/ +#include +#define CPU_CLOCK_HZ 800000000UL + +static inline void sw_delay_loop(uint32_t loop) +{ + while (loop--) + { + __asm__ volatile ("nop"); + } +} + +void sw_delay_us(uint32_t us) +{ + /* Calibrate this value on real hardware */ + const uint32_t cycles_per_loop = 4U; + const uint32_t loops_per_us = + (CPU_CLOCK_HZ / 1000000UL) / cycles_per_loop; + + while (us--) + { + sw_delay_loop(loops_per_us); + } +} + +void up_udelay(useconds_t microseconds) +{ + #ifdef CONFIG_BSP_FSP_SUPPORT + R_BSP_SoftwareDelay((uint32_t)microseconds, BSP_DELAY_UNITS_MICROSECONDS); + #else + #define RH850_CPU_CYCLE_HZ 800000000 + sw_delay_us((uint32_t)microseconds) + #endif +} + + + + + + diff --git a/arch/rh850/src/common/rh850_usestack.c b/arch/rh850/src/common/rh850_usestack.c new file mode 100644 index 0000000000000000000000000000000000000000..6cfa17b2a1bf294fad632ff15b08fc810fc4e52f --- /dev/null +++ b/arch/rh850/src/common/rh850_usestack.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/rh850/src/common/rh850_usestack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "rh850_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from nxtask_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + uintptr_t top_of_stack; + size_t size_of_stack; + +#ifdef CONFIG_TLS_ALIGNED + /* Make certain that the user provided stack is properly aligned */ + + DEBUGASSERT(((uintptr_t)stack & TLS_STACK_MASK) == 0); +#endif + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* If stack debug is enabled, then fill the stack with a recognizable value + * that we can use later to test for high water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* The SH family uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register, points to the + * lowest, valid work address (the "top" of the stack). Items on the + * stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size; + + /* The SH stack must be aligned at word (4 byte) boundaries. If necessary + * top_of_stack must be rounded down to the next boundary + */ + + top_of_stack &= ~3; + size_of_stack = top_of_stack - (uintptr_t)tcb->stack_alloc_ptr; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = size_of_stack; + + return OK; +} diff --git a/arch/rh850/src/g4x/CMakeLists.txt b/arch/rh850/src/g4x/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..ecbd04bb2a087572bd7e6786e13aa4f28798a171 --- /dev/null +++ b/arch/rh850/src/g4x/CMakeLists.txt @@ -0,0 +1,44 @@ +# ############################################################################## +# arch/arm/src/armv8-m/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +if(CONFIG_ARCH_TOOLCHAIN_GHS) + list( + APPEND SRCS + ${CMAKE_CURRENT_SOURCE_DIR}/Core/Template/RH850/Source/ghs/system.c + ${CMAKE_CURRENT_SOURCE_DIR}/Core/Template/RH850/Source/Interrupt_VectorTable_PE0.c + ${CMAKE_CURRENT_SOURCE_DIR}/Core/Template/RH850/Source/Interrupt_VectorTable_PE1.c + ) +endif() + +FILE(GLOB_RECURSE ASRCS + ${CMAKE_CURRENT_SOURCE_DIR}/Core/Template/RH850/Source/ghs/*.850 +) + +enable_language(ASM) +foreach(X IN ITEMS ${ASRCS}) + set_source_files_properties(${X} PROPERTIES LANGUAGE ASM) +endforeach() + + +target_sources(arch PRIVATE ${SRCS}) +target_sources(arch PUBLIC ${ASRCS}) + diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ccrh_g4.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ccrh_g4.h new file mode 100644 index 0000000000000000000000000000000000000000..ca7a50c8786ba8f97287809255151c37ebf7530a --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ccrh_g4.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_ccrh_g4.h + * @brief RH850 G4 CCRH function + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_CCRH_G4_H +#define __RH850_CCRH_G4_H + +#ifndef __RH850_CCRH_H + #error "This file must not be included directly" +#endif + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** @defgroup RH850_Core_AtomicFunctions RH850-Core Atomic Access Functions + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850-Core Atomic Access Functions + * @{ + */ + +/** @defgroup CCRH_RH850_Core_AtomicFunctions CCRH RH850-Core Atomic Access Functions + * @brief CCRH RH850-Core Atomic Access Functions + * @ingroup RH850_Core_AtomicFunctions + * @{ + */ + +/* ######################################## Atomic Function Access ################################################ */ + +/** + * @brief Release a spinlock + * @details Clear the lock by storing 0 to the given address. + * On RH850, this uses a normal store to memory, releasing the lock held by another core/task. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @note CC-RH inline assembly function; first parameter is passed in r6. + * Implementation: \code st.w r0, [r6] \endcode + * @pre \p Addr must be aligned to word size and visible to all participating cores. + */ +#pragma inline_asm RH850_SpinlockRelease +static void RH850_SpinlockRelease (uint32_t * LpAddr) +{ + st.w r0, 0[r6] +} + +/** + * @brief Acquire a spinlock (blocking) + * @details Attempt to acquire the spinlock using LL/SC (load-linked/store-conditional) primitive: + * - Load-linked the current value at \p Addr. + * - If unlocked (0), try store-conditional of 1. + * - If SC succeeds, the lock is acquired and the function returns. + * - Otherwise, enter low-power wait (snooze) and retry. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @note CC-RH inline assembly function; first parameter is passed in r6 (ABI). + * Uses the LL/SC pair \code ldl.w \endcode and \code stc.w \endcode with a wait loop using \code snooze \endcode. + * @pre \p Addr must be aligned to word size and shared/uncached or properly coherent across cores. + */ +#pragma inline_asm RH850_SpinlockGet +static void RH850_SpinlockGet (uint32_t * LpAddr) +{ + .local Lock_loop, Lock_wait, Lock_success + +Lock_loop: + ldl.w[r6], r7; /* r7 = *LpAddr (linked) */ + cmp r0, r7; /* is *LpAddr == 0 ? */ + bnz Lock_wait; /* Lock_wait */ + mov 1, r7 + stc.w r7, [r6]; /* try to set *LpAddr = 1 (conditional) */ + cmp r0, r7; /* stc.w result (0/1) in r7 on RH850; nonzero => success */ + bnz Lock_success + +Lock_wait: + snooze + br Lock_loop + +Lock_success: +} + +/** @} */ /* end of CCRH_RH850_Core_AtomicFunctions */ +/** @} */ /* end of RH850_Core_AtomicFunctions */ + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/* ########################################## FPU Function Access ################################################# */ + +/** + * @ingroup RH850_FPU_API + * @{ + */ + +/** + * @brief Initialize the Floating Point Unit (FPU). + * @details + * This function enables the FPU and initializes its status registers. + * + * **Operation steps:** + * - Detect if FPU is present using PID register (SR6,1). + * - Enable FPU by setting the appropriate bit in PSW (SR5,0). + * - Initialize FPSR (SR6,0) and FPEPC (SR7,0) registers. + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) + * - PSW: Program Status Word (SR5,0) + * - FPSR: Floating Point Status Register (SR6,0) + * - FPEPC: Floating Point Exception Program Counter (SR7,0) + */ + #pragma inline_asm RH850_FPU_Init +static void RH850_FPU_Init (void) +{ + .local RH850_FPU_Init_L1 + ; /* enable FPU */ + stsr 6, r10, 1; /* r10 <- PID */ + shl 21, r10 + shr 30, r10 + bz RH850_FPU_Init_L1; /* detecting FPU */ + stsr 5, r10, 0; /* r10 < -PSW */ + movhi 0x0001, r0, r11 + or r11, r10 + ldsr r10, 5, 0; /* enable FPU */ + + movhi 0x0002, r0, r11 + ldsr r11, 6, 0; /* initialize FPSR */ + ldsr r0, 7, 0; /* initialize FPEPC */ +RH850_FPU_Init_L1: +} + +/** @} */ /* end of RH850_FPU_API */ +#endif /* #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) */ + +#if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) + +/* ########################################## FXU Function Access ################################################# */ + +/** + * @ingroup RH850_FXU_API + * @{ + */ + +/** + * @brief Initialize the Fixed-Point Unit (FXU). + * @details + * This function enables the FXU and initializes its configuration and status registers. + * + * **Operation steps:** + * - Detect FXU presence using the PID register (SR6,1) by checking the relevant capability bits. + * - Enable FXU by setting the appropriate bit(s) in PSW (SR5,0). + * - Initialize FXU control/status registers: FXSR, FXST, FXCFG (bank 10). + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) — capability detection + * - PSW: Program Status Word (SR5,0) — enable FXU in status word + * - FXSR: FXU Status Register (SR6,10) + * - FXST: FXU Status (SR8,10) + * - FXCFG: FXU Configuration (SR10,10) + * + * @note This function uses CC-RH inline assembly syntax and assumes the ABI/register usage as written. + */ + #pragma inline_asm RH850_FXU_Init +static void RH850_FXU_Init (void) +{ + .local RH850_FXU_Init_L2 + stsr 6, r10, 1; /* r10 <- PID */ + shl 20, r10 + shr 31, r10 + bz RH850_FXU_Init_L2; /* detecting FXU */ + stsr 5, r10, 0; /* r10 <- PSW */ + movhi 0x0002, r0, r11 + or r11, r10 + ldsr r10, 5, 0; /* enable FXU */ + + movhi 0x0002, r0, r11 + ldsr r11, 6, 10; /* initialize FXSR */ + ldsr r0, 8, 10; /* initialize FXST */ + ldsr r0, 10, 10; /* initialize FXCFG */ +RH850_FXU_Init_L2: +} + +/** @} */ /* end of RH850_FXU_API */ +#endif /* #if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) */ + +/** @} */ /* end of RH850_Core_intrinsics */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ + +#endif /* __RH850_CCRH_G4_H */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fpu.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fpu.h new file mode 100644 index 0000000000000000000000000000000000000000..777312d258884003146d8a92a6a71655d185afda --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fpu.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_fpu.h + * @brief FPU initialization function for RH850 G4 + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_FPU RH850 Floating-point Function (FPU) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850 FPU API and types + * @{ + */ + +#ifndef RH850_G4_FPU_H + #define RH850_G4_FPU_H + + #include + +/* ####################################### FPU Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_FPU_Types FPU Types and Enumerations + * @brief FPU Types and Enumerations + * @ingroup RH850_FPU + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @brief Rounding modes for FPU (FPCFG.RM[9:8]). + * @details + * - 0: Round to nearest (ties to even, per device spec) + * - 1: Round toward zero + * - 2: Round toward +infinity + * - 3: Round toward -infinity + */ +typedef enum e_rh850_fpu_round +{ + RH850_FPU_ROUND_NEAR = 0x000, /*!< Round to nearest (ties to even, per device spec) */ + RH850_FPU_ROUND_ZERO = 0x100, /*!< Round toward zero */ + RH850_FPU_ROUND_PLUS = 0x200, /*!< Round toward +infinity */ + RH850_FPU_ROUND_MINUS = 0x300 /*!< Round toward -infinity */ +} rh850_fpu_round_t; + +/** + * @brief Flush mode flags for FPSR. + * @details + * - **FN (bit 23)**: Flush-to-nearest enable + * - **FS (bit 17)**: Flush-to-sign enable + * You can OR both for composite behavior. + */ +typedef enum e_rh850_fpu_flush +{ + RH850_FPU_FLUSH_NEAR = 0x00800000, /*!< Flush-to-nearest enable */ + RH850_FPU_FLUSH_SIGN = 0x00020000, /*!< Flush-to-sign enable */ + RH850_FPU_FLUSH_ALL = 0x00820000 /*!< All */ +} rh850_fpu_flush_t; + +/** + * @brief Exception-enable bits (FPCFG.XE[4:0]). + * @details + * - XE[0]: Inexact + * - XE[1]: Underflow + * - XE[2]: Overflow + * - XE[3]: Divide-by-zero + * - XE[4]: Invalid operation + */ +typedef enum e_rh850_fpu_irq_enable +{ + RH850_FPU_IRQ_ENABLE_OFF = 0x00, /*!< None */ + RH850_FPU_IRQ_ENABLE_INEXACT = 0x01, /*!< Inexact */ + RH850_FPU_IRQ_ENABLE_UNDERFLOW = 0x02, /*!< Underflow */ + RH850_FPU_IRQ_ENABLE_OVERFLOW = 0x04, /*!< Overflow */ + RH850_FPU_IRQ_ENABLE_ZERO = 0x08, /*!< Divide-by-zero */ + RH850_FPU_IRQ_ENABLE_INVALID = 0x10, /*!< Invalid operation */ + RH850_FPU_IRQ_ENABLE_ALL = 0x1F /*!< All */ +} rh850_fpu_irq_enable_t; + +/** + * @brief FPU status bits (FPST). + * @details + * **Low status (sticky) flags:** + * - 0x0001: Inexact + * - 0x0002: Underflow + * - 0x0004: Overflow + * - 0x0008: Divide-by-zero + * - 0x0010: Invalid operation + * - 0x0020: Flush occurred + * + * **IRQ request flags:** + * - 0x0100: IRQ Inexact + * - 0x0200: IRQ Underflow + * - 0x0400: IRQ Overflow + * - 0x0800: IRQ Divide-by-zero + * - 0x1000: IRQ Invalid + * - 0x2000: IRQ Unimplemented operation + */ +typedef enum e_rh850_fpu_status +{ + RH850_FPU_STATUS_NONE = 0x0000, /*!< None */ + RH850_FPU_STATUS_INEXACT = 0x0001, /*!< Inexact */ + RH850_FPU_STATUS_UNDERFLOW = 0x0002, /*!< Underflow */ + RH850_FPU_STATUS_OVERFLOW = 0x0004, /*!< Overflow */ + RH850_FPU_STATUS_ZERO = 0x0008, /*!< Divide-by-zero */ + RH850_FPU_STATUS_INVALID = 0x0010, /*!< Invalid operation */ + RH850_FPU_STATUS_FLUSH = 0x0020, /*!< Flush occurred */ + RH850_FPU_STATUS_IRQ_INEXACT = 0x0100, /*!< IRQ Inexact */ + RH850_FPU_STATUS_IRQ_UNDERFLOW = 0x0200, /*!< IRQ Underflow */ + RH850_FPU_STATUS_IRQ_OVERFLOW = 0x0400, /*!< IRQ Overflow */ + RH850_FPU_STATUS_IRQ_ZERO = 0x0800, /*!< IRQ Divide-by-zero */ + RH850_FPU_STATUS_IRQ_INVALID = 0x1000, /*!< IRQ Invalid */ + RH850_FPU_STATUS_IRQ_UNIMPLEMENTED = 0x2000, /*!< IRQ Unimplemented operation */ + RH850_FPU_STATUS_ALL = 0x3F3F /*!< All */ +} rh850_fpu_status_t; + +/** + * @brief Floating-point Condition Code (CC) bit selector. + * @details This enumeration defines the CC bit positions (CC0..CC7) used in the FPSR register + * for floating-point comparison results. Each CC bit corresponds to one of the eight + * condition code fields located in bits [31:24] of FPSR. + * + * @note CC bits store the result of floating-point comparison instructions: + * - 0: Comparison result is FALSE + * - 1: Comparison result is TRUE + * + * @enum rh850_fpu_fcbit_cc_t + */ + +typedef enum e_rh850_fpu_fcbit_cc +{ + RH850_FPU_FCBIT_CC_0 = 0, /*!< CC0: bit 24 in FPSR */ + RH850_FPU_FCBIT_CC_1 = 1, /*!< CC1: bit 25 */ + RH850_FPU_FCBIT_CC_2 = 2, /*!< CC2: bit 26 */ + RH850_FPU_FCBIT_CC_3 = 3, /*!< CC3: bit 27 */ + RH850_FPU_FCBIT_CC_4 = 4, /*!< CC4: bit 28 */ + RH850_FPU_FCBIT_CC_5 = 5, /*!< CC5: bit 29 */ + RH850_FPU_FCBIT_CC_6 = 6, /*!< CC6: bit 30 */ + RH850_FPU_FCBIT_CC_7 = 7 /*!< CC7: bit 31 */ +} rh850_fpu_fcbit_cc_t; + +/** + * @brief FPU enable state. + */ +typedef enum e_rh850_fpu_status_enable +{ + RH850_FPU_STATUS_ENABLE_OFF = 0x0U, /*!< Counter is disabled */ + RH850_FPU_STATUS_ENABLE_ON = 0x1U /*!< Counter is enabled */ +} rh850_fpu_status_enable_t; + +/** @} */ /* end of RH850_FXU_Types */ + +/* ########################################### FPU API Functions ################################################## */ + +/** + * @defgroup RH850_FPU_API FPU API Functions + * @brief FPU API Functions + * @ingroup RH850_FPU + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief Get the floating-point comparison result from FPSR. + * @details This function reads the FPSR register and checks the condition code (CC) bit + * specified by @p LenFcbit. If the CC bit is set, the comparison result is TRUE; + * otherwise, it is FALSE. + * + * @param LenFcbit CC bit position (0–7) corresponding to the floating-point comparison result. + * + * @return bool + * - true : Comparison condition is satisfied. + * - false : Comparison condition is not satisfied. + * + * @note The CC bits (CC7..CC0) in FPSR are only modified by floating-point comparison + * instructions and LDSR instructions. + */ +__STATIC_INLINE bool __RH850_FPU_FpsrCcBitGet (rh850_fpu_fcbit_cc_t LenFcbit) +{ + bool LblReturnValue; + + /* Initalize for LblReturnValue */ + LblReturnValue = false; + + /* Get the comparation result at specific fcbit */ + if ((__get_FPSR() & R_FPU_FPSR_CC_Msk) & (LenFcbit << R_FPU_FPSR_CC_Pos)) + { + LblReturnValue = true; + } + + /* Return value */ + return LblReturnValue; +} + +/** + * @brief Set the floating-point comparison result (CCn) in FPSR. + * @details Writes the specified comparison result value to the condition code (CC) bit + * selected by @p LenFcbit within the FPSR register. The CC bits (CC7..CC0) + * store the outcome of floating-point comparison instructions (0 = false, + * 1 = true) and can also be updated via software by writing FPSR. + * + * @param LenFcbit CC bit selector (0–7) that identifies which CCn bit to update. + * The value corresponds to CC0..CC7 (mapped to FPSR bits 24..31). + * @param LblValue Comparison result to set: + * - false : condition not satisfied (0) + * - true : condition satisfied (1) + * + * @note CC bits in FPSR are only modified by floating-point comparison instructions + * and by software writes (e.g., LDSR / __set_FPSR()). Writing CC bits via + * software does not perform a comparison nor raise an exception. + */ +__STATIC_INLINE void __RH850_FPU_FpsrCcBitSet (rh850_fpu_fcbit_cc_t LenFcbit, bool LblValue) +{ + uint32_t LulFpsrRegValue; + + /* Get the FPSR value and mask for the input bit */ + LulFpsrRegValue = __get_FPSR(); + LulFpsrRegValue &= (LenFcbit << R_FPU_FPSR_CC_Pos); + + /* Setting the new value for CCn bit */ + LulFpsrRegValue |= (LblValue << R_FPU_FPSR_CC_Pos); + + /* Write back */ + (void) __set_FPSR(LulFpsrRegValue); +} + +/** + * @brief Get the flush status of input operands in floating-point operations. + * @details This function retrieves the status bit that indicates information about the flushing of input operands. + * + * @return bool + * - true : At least one operand was flushed. + * - false : No operand flushing occurred. + */ +__STATIC_INLINE bool __RH850_FPU_FpsrIfBitGet (void) +{ + return (bool) (((__get_FPSR() & R_FPU_FPSR_IF_Msk)) >> R_FPU_FPSR_IF_Pos); +} + +/** + * @brief Configure FPU flush behavior (FPSR.FN/FS). + * @details + * Reads **FPSR (SR6)**, clears FN/FS via mask, ORs provided "LenMode" bits, and writes back. + * + * **Bit fields:** + * - FPSR.FN (23): Flush-to-nearest enable + * - FPSR.FS (17): Flush-to-sign enable + * + * @param[in] LenMode Bitmask of @ref rh850_fpu_flush_t. + */ +__STATIC_INLINE void __RH850_FPU_ModeFlushSet (rh850_fpu_flush_t LenMode) +{ + uint32_t LulFpsrRegValue; + + /* Read current FPSR register and clears FN/FS via mask */ + LulFpsrRegValue = __get_FPSR(); + LulFpsrRegValue &= ((~R_FPU_FPSR_FN_Msk) & (~R_FPU_FPSR_FS_Msk)); + + /* Update the flush mode */ + LulFpsrRegValue |= (uint32_t) (LenMode & (R_FPU_FPSR_FN_Msk | R_FPU_FPSR_FS_Msk)); + + /* Update FN/FS bits */ + __set_FPSR(LulFpsrRegValue); +} + +/** + * @brief Get the current configuration of FPU flush behavior (FPSR.FN/FS). + * @details + * Reads **FPSR (SR6)** with FN/FS bits + * + * @return rh850_fpu_flush_t + * - FPSR.FN (23): Flush-to-nearest enable + * - FPSR.FS (17): Flush-to-sign enable + */ +__STATIC_INLINE rh850_fpu_flush_t __RH850_FPU_ModeFlushGet (void) +{ + return (rh850_fpu_flush_t) (__get_FPSR() & (R_FPU_FPSR_FN_Msk | R_FPU_FPSR_FS_Msk)); +} + +/** + * @brief Set FPU rounding mode (FPCFG.RM[9:8]). + * @details + * Reads **FPCFG (SR10)**, clears RM[9:8] with mask, then inserts "LenMode" and writes back. + * + * **Bit fields:** + * - FPCFG.RM[9:8]: rounding mode control (see @ref rh850_fpu_round_t). + * + * @param[in] LenMode Rounding mode value. + */ +__STATIC_INLINE void __RH850_FPU_ModeRoundingSet (rh850_fpu_round_t LenMode) +{ + uint32_t LulFpcfgRegValue; + + /* Read current FPCFG register and clear the FPCFG.RM[9:8] with mask */ + LulFpcfgRegValue = __get_FPCFG(); + LulFpcfgRegValue &= (~R_FPU_FPCFG_RM_Msk); + + /* Update the rounding mode */ + LulFpcfgRegValue |= (uint32_t) (LenMode & R_FPU_FPCFG_RM_Msk); + + /* Update rounding configuration */ + __set_FPCFG(LulFpcfgRegValue); +} + +/** + * @brief Set FPU rounding mode (FPCFG.RM[9:8]). + * @details + * Reads **FPCFG (SR10)** for RM[9:8] bits, then return the Rounding Mode. + * + * @return rh850_fpu_round_t + * - FPCFG.RM[9:8]: rounding mode control (see @ref rh850_fpu_round_t). + */ +__STATIC_INLINE rh850_fpu_round_t __RH850_FPU_ModeRoundingGet (void) +{ + return (rh850_fpu_round_t) (__get_FPCFG() & R_FPU_FPCFG_RM_Msk); +} + +/** + * @brief Enable FPU exceptions (FPCFG: XE[4:0]). + * @details + * Reads **FPCFG (SR10)**, clears XE mask, ORs desired bits from r6, and writes back. + * This helper currently sets **all** bits (XE[4:0]) enabled. + * + * @param[in] LenIrqEna FPU exceptions enable/disable of @ref rh850_fpu_irq_enable_t. + */ +__STATIC_INLINE void __RH850_FPU_ExceptionEnableSet (rh850_fpu_irq_enable_t LenIrqEna) +{ + uint32_t LulFpcfgRegValue; + + /* Read current FPCFG register and clear the FPCFG: XE[4:0] Exception enable with mask */ + LulFpcfgRegValue = __get_FPCFG(); + LulFpcfgRegValue &= (~R_FPU_FPCFG_XE_Msk); + + /* Update the rounding mode */ + LulFpcfgRegValue |= (uint32_t) (LenIrqEna & R_FPU_FPCFG_XE_Msk); + + /* Update XE bits */ + __set_FPCFG(LulFpcfgRegValue); +} + +/** + * @brief Get the enable FPU exceptions (FPCFG: XE[4:0]). + * @details + * Reads **FPCFG (SR10)** for bits (XE[4:0]). + * + * @return rh850_fpu_irq_enable_t + * - FPCFG.XE[4:0]: FPU exceptions (see @ref rh850_fpu_irq_enable_t). + */ +__STATIC_INLINE rh850_fpu_irq_enable_t __RH850_FPU_ExceptionEnableGet (void) +{ + return (rh850_fpu_irq_enable_t) (__get_FPCFG() & R_FPU_FPCFG_XE_Msk); +} + +/** + * @brief Get the Program Counter (PC) of the floating-point instruction that caused an exception. + * @details This function returns the value of the FPEPC register, which holds the PC of the + * floating-point instruction that triggered an enabled floating-point operation exception. + * The value is read using the intrinsic __get_FPEPC(). + * + * @return uint32_t Current value of the FPEPC register (Program Counter of the faulting instruction). + */ +__STATIC_INLINE uint32_t __RH850_FPU_FpepcGet (void) +{ + return (uint32_t) (__get_FPEPC()); +} + +/** + * @brief Enable the FPU (set PSW.CU0). + * @details + * Reads **PSW (SR5)** to r10, sets CU0 bit via logical OR, then writes r10 back to **PSW (SR5)** using "ldsr". + * After enabling, floating-point instructions are permitted. + */ +__STATIC_INLINE void __RH850_FPU_Enable (void) +{ + uint32_t LulPswRegValue; + + /* Read the PSW and set the PSW.CU0 to 1 to enable for FPU */ + LulPswRegValue = __get_PSW(); + LulPswRegValue |= (R_SYS_PSW_CU0_Msk); + + /* Write back to PSW register */ + __set_PSW(LulPswRegValue); +} + +/** + * @brief Disable the FPU (clear PSW.CU0) + * @details + * Reads **PSW (SR5)**, clears CU0 by AND with inverted mask, and writes back to **PSW (SR5)**. + */ +__STATIC_INLINE void __RH850_FPU_Disable (void) +{ + uint32_t LulPswRegValue; + + /* Read the PSW and clear the PSW.CU0 to 0 to disable for FPU */ + LulPswRegValue = __get_PSW(); + LulPswRegValue &= (~R_SYS_PSW_CU0_Msk); + + /* Write back to PSW register */ + __set_PSW(LulPswRegValue); +} + +/** + * @brief Get the current enable state of the FPU (Get the current state of PSW.CU0). + * @details + * Returns an enumerated state based on the CU0 bit. + * @return RH850_FPU_STATUS_ENABLE_ON/RH850_FPU_STATUS_ENABLE_OFF if enabled/disabled + */ +__STATIC_INLINE rh850_fpu_status_enable_t __RH850_FPU_EnableGet (void) +{ + /* Extract CEN bit, translate into enumeration */ + return (__get_PSW() & R_SYS_PSW_CU0_Msk) ? RH850_FPU_STATUS_ENABLE_ON : RH850_FPU_STATUS_ENABLE_OFF; +} + +/** + * @brief Read FPU status (FPST). + * @details + * Reads **FPST (SR8)**. + * + * @return Bitmask of @ref rh850_fpu_status_t. + */ +__STATIC_INLINE rh850_fpu_status_t __RH850_FPU_StatusGet (void) +{ + return (rh850_fpu_status_t) __get_FPST(); +} + +/** + * @brief Clear selected FPU status bits (FPST). + * @details + * Reads **FPST (SR8)**, clears targeted bits using "LulFpuStatus" mask, then writes back. + * + * @param[in] LulFpuStatus Bitmask of status to clear (see @ref rh850_fpu_status_t). + */ +__STATIC_INLINE void __RH850_FPU_StatusClear (rh850_fpu_status_t LulFpuStatus) +{ + uint32_t LulFpstRegValue; + + /* Read the FPST value */ + LulFpstRegValue = __get_FPST(); + + /* Clear requested bits */ + LulFpstRegValue &= ~(LulFpuStatus & (R_FPU_FPST_XC_Msk | R_FPU_FPST_IF_Msk | R_FPU_FPST_XP_Msk)); + + /* Write back */ + __set_FPST(LulFpstRegValue); +} + +/** @} */ /* end of RH850_FPU_API */ + +#endif /* RH850_G4_FPU_H */ + +/** @} */ /* end of RH850_FPU */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ + +#endif /* #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fxu.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fxu.h new file mode 100644 index 0000000000000000000000000000000000000000..c2c603f0fb3b3e70292a04737ebcd964aae19828 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_fxu.h @@ -0,0 +1,494 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_fxu.h + * @brief FXU initialization function for RH850 G4 + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_FXU RH850 Extended Floating-point Function (FXU) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850 FXU API and types + * @{ + */ + +#ifndef RH850_G4_FXU_H + #define RH850_G4_FXU_H + + #include + +/* ####################################### FXU Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_FXU_Types FXU Types and Enumerations + * @brief FXU Types and Enumerations + * @ingroup RH850_FXU + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @brief Rounding modes for FXU (FXCFG.RM[9:8]). + * @details + * - 0: Round to nearest (ties to even, per device spec) + * - 1: Round toward zero + * - 2: Round toward +infinity + * - 3: Round toward -infinity + */ +typedef enum e_rh850_fxu_round +{ + RH850_FXU_ROUND_NEAR = 0x000, /*!< Round to nearest (ties to even, per device spec) */ + RH850_FXU_ROUND_ZERO = 0x100, /*!< Round toward zero */ + RH850_FXU_ROUND_PLUS = 0x200, /*!< Round toward +infinity */ + RH850_FXU_ROUND_MINUS = 0x300 /*!< Round toward -infinity */ +} rh850_fxu_round_t; + +/** + * @brief Flush mode flags for FXSR. + * @details + * - **FN (bit 23)**: Flush-to-nearest enable + * - **FS (bit 17)**: Flush-to-sign enable + * You can OR both for composite behavior. + */ +typedef enum e_rh850_fxu_flush +{ + RH850_FXU_FLUSH_NEAR = 0x00800000, /*!< Flush-to-nearest enable */ + RH850_FXU_FLUSH_SIGN = 0x00020000, /*!< Flush-to-sign enable */ + RH850_FXU_FLUSH_ALL = 0x00820000 /*!< All */ +} rh850_fxu_flush_t; + +/** + * @brief Exception-enable bits (FXCFG.XE[4:0]). + * @details + * - XE[0]: Inexact + * - XE[1]: Underflow + * - XE[2]: Overflow + * - XE[3]: Divide-by-zero + * - XE[4]: Invalid operation + */ +typedef enum e_rh850_fxu_irq_enable +{ + RH850_FXU_IRQ_ENABLE_OFF = 0x00, /*!< Off */ + RH850_FXU_IRQ_ENABLE_INEXACT = 0x01, /*!< Inexact */ + RH850_FXU_IRQ_ENABLE_UNDERFLOW = 0x02, /*!< Underflow */ + RH850_FXU_IRQ_ENABLE_OVERFLOW = 0x04, /*!< Overflow */ + RH850_FXU_IRQ_ENABLE_ZERO = 0x08, /*!< Divide-by-zero */ + RH850_FXU_IRQ_ENABLE_INVALID = 0x10, /*!< Invalid operation */ + RH850_FXU_IRQ_ENABLE_ALL = 0x1F /*!< All */ +} rh850_fxu_irq_enable_t; + +/** + * @brief FXU status bits (FXST). + * @details + * **Low status (sticky) flags:** + * - 0x0001: Inexact + * - 0x0002: Underflow + * - 0x0004: Overflow + * - 0x0008: Divide-by-zero + * - 0x0010: Invalid operation + * - 0x0020: Flush occurred + * + * **IRQ request flags:** + * - 0x0100: IRQ Inexact + * - 0x0200: IRQ Underflow + * - 0x0400: IRQ Overflow + * - 0x0800: IRQ Divide-by-zero + * - 0x1000: IRQ Invalid + * - 0x2000: IRQ Unimplemented operation + */ +typedef enum e_rh850_fxu_status +{ + RH850_FXU_STATUS_INEXACT = 0x0001, /*!< Inexact */ + RH850_FXU_STATUS_UNDERFLOW = 0x0002, /*!< Underflow */ + RH850_FXU_STATUS_OVERFLOW = 0x0004, /*!< Overflow */ + RH850_FXU_STATUS_ZERO = 0x0008, /*!< Divide-by-zero */ + RH850_FXU_STATUS_INVALID = 0x0010, /*!< Invalid operation */ + RH850_FXU_STATUS_FLUSH = 0x0020, /*!< Flush occurred */ + RH850_FXU_STATUS_IRQ_INEXACT = 0x0100, /*!< IRQ Inexact */ + RH850_FXU_STATUS_IRQ_UNDERFLOW = 0x0200, /*!< IRQ Underflow */ + RH850_FXU_STATUS_IRQ_OVERFLOW = 0x0400, /*!< IRQ Overflow */ + RH850_FXU_STATUS_IRQ_ZERO = 0x0800, /*!< IRQ Divide-by-zero */ + RH850_FXU_STATUS_IRQ_INVALID = 0x1000, /*!< IRQ Invalid */ + RH850_FXU_STATUS_IRQ_UNIMPLEMENTED = 0x2000, /*!< IRQ Unimplemented operation */ + RH850_FXU_STATUS_ALL = 0x3F3F /*!< All */ +} rh850_fxu_status_t; + +/** + * @brief XC (Cause Bit) selector for extended floating-point operation ways. + * @details This enumeration defines the XC bit groups in the FXXC register that indicate + * the cause of floating-point exceptions for each operation way. Each group + * corresponds to a specific SIMD operation lane (way) and contains multiple + * bits representing IEEE754-defined exception causes such as Invalid Operation, + * Divide-by-Zero, Overflow, Underflow, and Inexact. + * + * @note XC bits are set when exceptions occur during floating-point operations. + * Multiple bits may be set if multiple exceptions are detected in the same + * instruction. Writing to FXXC does not affect the XC bits in FXS register. + * + * @enum rh850_fxu_xc_operation_way_t + */ +typedef enum e_rh850_fxu_xc_operation_way +{ + RH850_FXU_XC_OPERATION_WAY_0 = 0, /*!< Cause bits for operation way 0 (E0, V0, Z0, O0, U0, I0) */ + RH850_FXU_XC_OPERATION_WAY_1 = 1, /*!< Cause bits for operation way 1 (E1, V1, Z1, O1, U1, I1) */ + RH850_FXU_XC_OPERATION_WAY_2 = 2, /*!< Cause bits for operation way 2 (E2, V2, Z2, O2, U2, I2) */ + RH850_FXU_XC_OPERATION_WAY_3 = 3 /*!< Cause bits for operation way 3 (E3, V3, Z3, O3, U3, I3) */ +} rh850_fxu_xc_operation_way_t; + +/** + * @brief XP (Preservation) bit group selector for each operation way. + * @details This enumeration selects the preservation bit group in the FXXP register + * for a specific SIMD operation way: + * - XPn: Vn, Zn, On, Un, In + * + * @note XP bits indicate “preservation” behavior for IEEE754 exceptions: when set, + * the operation result is preserved even if the corresponding exception occurs. + */ +typedef enum e_rh850_fxu_xp_operation_way +{ + RH850_FXU_XP_OPERATION_WAY_0 = 0, /*!< Preservation bits for operation way 0 (V0, Z0, O0, U0, I0) */ + RH850_FXU_XP_OPERATION_WAY_1 = 1, /*!< Preservation bits for operation way 1 (V1, Z1, O1, U1, I1) */ + RH850_FXU_XP_OPERATION_WAY_2 = 2, /*!< Preservation bits for operation way 2 (V2, Z2, O2, U2, I2) */ + RH850_FXU_XP_OPERATION_WAY_3 = 3 /*!< Preservation bits for operation way 3 (V3, Z3, O3, U3, I3) */ +} rh850_fxu_xp_operation_way_t; + +/** + * @brief XC cause bits (operation way n) in the FXXC register. + * @details This structure models the six IEEE754-related exception cause flags for + * operation way 0 (lane 0). Each field corresponds to a specific exception + * cause bit in the XC0 group: + * - E : Unimplemented operation (software emulation required) + * - V : Invalid operation + * - Z : Divide-by-zero + * - O : Overflow + * - U : Underflow + * - I : Inexact + * + * @note Multiple bits can be set simultaneously if multiple exceptions were detected + * for the same instruction. This struct is a logical representation; actual bit + * positions reside in the FXXC register as defined by the hardware manual. + */ +typedef union u_rh850_fxu_xc +{ + uint8_t XC; + struct + { + uint8_t E : 1; /*!< Unimplemented operation cause */ + uint8_t V : 1; /*!< Invalid operation cause */ + uint8_t Z : 1; /*!< Divide-by-zero cause */ + uint8_t O : 1; /*!< Overflow cause */ + uint8_t U : 1; /*!< Underflow cause */ + uint8_t I : 1; /*!< Inexact cause */ + uint8_t : 2; /*!< Reserved to complete a byte (not used) */ + } XC_b; +} rh850_fxu_xc_t; + +/** + * @brief XPn preservation bits for operation way n. + * @details This union represents the preservation status bits in the FXXP register + * for operation way n. These bits indicate whether the corresponding IEEE754 + * exception conditions (Invalid, Divide-by-Zero, Overflow, Underflow, Inexact) + * should preserve the result instead of triggering an exception. + * + * @note XP bits are used to control exception behavior for SIMD operations. When set, + * the result is preserved even if the exception occurs. + * + * Fields: + * - V : Preservation for Invalid Operation + * - Z : Preservation for Divide-by-Zero + * - O : Preservation for Overflow + * - U : Preservation for Underflow + * - I : Preservation for Inexact + */ + +typedef union u_rh850_fxu_xp +{ + uint8_t XP; + struct + { + uint8_t V : 1; /*!< Preservation for Invalid Operation */ + uint8_t Z : 1; /*!< Preservation for Divide-by-Zero */ + uint8_t O : 1; /*!< Preservation for Overflow */ + uint8_t U : 1; /*!< Preservation for Underflow */ + uint8_t I : 1; /*!< Preservation for Inexact */ + uint8_t : 3; /*!< Reserved to complete a byte */ + } XP_b; +} rh850_fxu_xp_t; + +/** @} */ /* end of RH850_FXU_Types */ + +/* ########################################### FXU API Functions ################################################## */ + +/** + * @defgroup RH850_FXU_API FXU API Functions + * @brief FXU API Functions + * @ingroup RH850_FXU + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief Get the flush status of input operands in floating-point operations. + * @details This function retrieves the status bit that indicates information about the flushing of input operands. + * + * @return bool + * - true : At least one operand was flushed. + * - false : No operand flushing occurred. + */ +__STATIC_INLINE bool __RH850_FXU_FxsrIfBitGet (void) +{ + return (bool) (((__get_FXSR() & R_FXU_FXSR_IF_Msk)) >> R_FXU_FXSR_IF_Pos); +} + +/** + * @brief Configure FXU flush behavior (FXSR.FN/FS). + * @details + * Reads **FXSR (SR6)**, clears FN/FS via mask, ORs provided "LenMode" bits, and writes back. + * + * **Bit fields:** + * - FXSR.FN (23): Flush-to-nearest enable + * - FXSR.FS (17): Flush-to-sign enable + * + * @param[in] LenMode Bitmask of @ref rh850_fxu_flush_t. + */ +__STATIC_INLINE void __RH850_FXU_ModeFlushSet (rh850_fxu_flush_t LenMode) +{ + uint32_t LulFxsrRegValue; + + /* Read current FXSR register and clears FN/FS via mask */ + LulFxsrRegValue = __get_FXSR(); + LulFxsrRegValue &= ((~R_FXU_FXSR_FN_Msk) & (~R_FXU_FXSR_FS_Msk)); + + /* Update the flush mode */ + LulFxsrRegValue |= (uint32_t) (LenMode & (R_FXU_FXSR_FN_Msk | R_FXU_FXSR_FS_Msk)); + + /* Update FN/FS bits */ + __set_FXSR(LulFxsrRegValue); +} + +/** + * @brief Check if the 4-way SIMD arithmetic unit is provided. + * @details This function reads the NFPU status bit to determine whether the processor + * includes a 4-way SIMD arithmetic unit for floating-point operations. + * + * @return bool + * - true : SIMD arithmetic unit is available. + * - false : SIMD arithmetic unit is not available. + * + * @note The NFPU bit is read-only and reflects hardware capability. + */ +__STATIC_INLINE bool __RH850_FXU_SimdUnitCheck (void) +{ + return (bool) ((__get_FXINFO() & R_FXU_FXINFO_NFPU_Msk) >> R_FXU_FXINFO_NFPU_Pos); +} + +/** + * @brief Check if 32 128-bit vector registers are provided. + * @details This function reads the RSIZE status bit to determine whether the processor + * supports 32 vector registers of 128 bits each for SIMD operations. + * + * @return bool + * - true : 32 128-bit vector registers are available. + * - false : Vector register configuration is not supported. + * + * @note The RSIZE bit is read-only and reflects hardware capability. + */ +__STATIC_INLINE bool __RH850_FXU_VectorRegisterCheck (void) +{ + return (bool) ((__get_FXINFO() & R_FXU_FXINFO_RSIZE_Msk) >> R_FXU_FXINFO_RSIZE_Pos); +} + +/** + * @brief Set FXU rounding mode (FXCFG.RM[9:8]). + * @details + * Reads **FXCFG (SR10)**, clears RM[9:8] with mask, then inserts "LenMode" and writes back. + * + * **Bit fields:** + * - FXCFG.RM[9:8]: rounding mode control (see @ref rh850_fxu_round_t). + * + * @param[in] LenMode Rounding mode value. + */ +__STATIC_INLINE void __RH850_FXU_ModeRoundingSet (rh850_fxu_round_t LenMode) +{ + uint32_t LulFxcfgRegValue; + + /* Read current FXCFG register and clear the FXCFG.RM[9:8] with mask */ + LulFxcfgRegValue = __get_FXCFG(); + LulFxcfgRegValue &= (~R_FXU_FXCFG_RM_Msk); + + /* Update the rounding mode */ + LulFxcfgRegValue |= (uint32_t) (LenMode & R_FXU_FXCFG_RM_Msk); + + /* Update rounding configuration */ + __set_FXCFG(LulFxcfgRegValue); +} + +/** + * @brief Enable FXU exceptions (FXCFG: XE[4:0]). + * @details + * Reads **FXCFG (SR10)**, clears XE mask, ORs desired bits from r6, and writes back. + * This helper currently sets **all** bits (XE[4:0]) enabled. + * + * @param[in] LenIrqEna FXU exceptions enable/disable of @ref rh850_fxu_irq_enable_t. + */ +__STATIC_INLINE void __RH850_FXU_ExceptionEnableSet (rh850_fxu_irq_enable_t LenIrqEna) +{ + uint32_t LulFxcfgRegValue; + + /* Read current FXCFG register and clear the FXCFG: XE[4:0] Exception enable with mask */ + LulFxcfgRegValue = __get_FXCFG(); + LulFxcfgRegValue &= (~R_FXU_FXCFG_XE_Msk); + + /* Update the rounding mode */ + LulFxcfgRegValue |= (uint32_t) (LenIrqEna & R_FXU_FXCFG_XE_Msk); + + /* Update XE bits */ + __set_FXSR(LulFxcfgRegValue); +} + +/** + * @brief Get the cause bits for a specific operation way from the FXXC register. + * @details This function reads the FXXC register and returns the cause bits (XC) associated + * with the specified operation way. Cause bits indicate which floating-point + * exceptions occurred during operations for that way (e.g., Invalid Operation, + * Divide-by-Zero, Overflow, Underflow, Inexact). + * + * @param LenOperationWay Enumeration value of type rh850_fxu_xc_operation_way_t specifying the operation way. + * + * @return rh850_fxu_xc_t + * Bitmask representing the cause bits for the selected operation way. + */ +__STATIC_INLINE rh850_fxu_xc_t __RH850_FXU_CauseBitsGet (rh850_fxu_xc_operation_way_t LenOperationWay) +{ + rh850_fxu_xc_t LstReturnValue; + + /* Get the cause bits for a specific operation way */ + LstReturnValue.XC = (uint8_t) ((__get_FXXC() & (R_FXU_FXXC_XC0_Msk << (LenOperationWay * 8))) >> \ + (LenOperationWay * 8)); + + return LstReturnValue; +} + +/** + * @brief Get the preservation (XP) bitfield for a specific operation way. + * @details Reads the FXXP register and returns the XP bit group associated with + * @p LenOperationWay (XP0..XP3). The returned value is a bitmask composed of + * rh850_fxu_xp_mask_t flags (V, Z, O, U, I). + * + * @param LenOperationWay XP group selector. + * + * @return rh850_fxu_xp_t + * Bitmask of preservation flags for the selected way. + * + * @note Writing FXXP does not affect the XP bits of the FXSR register. XP bits indicate + * whether results are preserved under IEEE754 exceptions in the selected lane. + */ +__STATIC_INLINE rh850_fxu_xp_t __RH850_FXU_PreservationBitsGet (rh850_fxu_xp_operation_way_t LenOperationWay) +{ + rh850_fxu_xp_t LstReturnValue; + + /* Get the preservation (XP) bitfield for a specific operation way */ + LstReturnValue.XP = (uint8_t) ((__get_FXXP() & (R_FXU_FXXP_XP0_Msk << (LenOperationWay * 8))) >> \ + (LenOperationWay * 8)); + + return LstReturnValue; +} + +/** + * @brief Read FXU status (FXST). + * @details + * Reads **FXST (SR8)**. + * + * @return Bitmask of @ref rh850_fxu_status_t. + */ +__STATIC_INLINE rh850_fxu_status_t __RH850_FXU_StatusGet (void) +{ + return (rh850_fxu_status_t) __get_FXST(); +} + +/** + * @brief Clear selected FXU status bits (FXST). + * @details + * Reads **FXST (SR8)**, clears targeted bits using "LulFxuStatus" mask, then writes back. + * + * @param[in] LulFxuStatus Bitmask of status to clear (see @ref rh850_fxu_status_t). + */ +__STATIC_INLINE void __RH850_FXU_StatusClear (rh850_fxu_status_t LulFxuStatus) +{ + uint32_t LulFxstRegValue; + + /* Read the FXST value */ + LulFxstRegValue = __get_FXST(); + + /* Clear requested bits */ + LulFxstRegValue &= (~R_FXU_FXST_XC_Msk | ~R_FXU_FXST_IF_Msk | ~R_FXU_FXST_XP_Msk); + LulFxstRegValue |= (LulFxuStatus & (R_FXU_FXST_XC_Msk | R_FXU_FXST_IF_Msk | R_FXU_FXST_XP_Msk)); + + /* Write back */ + __set_FXST(LulFxstRegValue); +} + +/** + * @brief Enable the FXU (set PSW.CU1). + * @details + * Reads **PSW (SR5)**, enable the FXU by setting bit PSW.CU1 to 1. + */ +__STATIC_INLINE void __RH850_FXU_Enable (void) +{ + uint32_t LulPswRegValue; + + /* Read the value of PSW and set the PSW.CU1 to 1 */ + LulPswRegValue = __get_PSW(); + LulPswRegValue |= (R_SYS_EIPSW_CU1_Msk); + + /* Write back to the PSW */ + __set_PSW(LulPswRegValue); +} + +/** + * @brief Disable the FXU (clear PSW.CU1). + * @details + * Reads **PSW (SR5)**, clears CU1 by AND with inverted mask, and writes back to **PSW (SR5)**. + */ +__STATIC_INLINE void __RH850_FXU_Disable (void) +{ + uint32_t LulPswRegValue; + + /* Read the value of PSW and set the PSW.CU1 to 1 */ + LulPswRegValue = __get_PSW(); + LulPswRegValue &= (~R_SYS_EIPSW_CU1_Msk); + + /* Write back to the PSW */ + __set_PSW(LulPswRegValue); +} + +/** @} */ /* end of RH850_FXU_API */ + +#endif /* RH850_CCRH_G4_FXU_H */ + +/** @} */ /* end of RH850_FXU */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ +#endif /* #if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_icache.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_icache.h new file mode 100644 index 0000000000000000000000000000000000000000..a393c02d7c2db5dde0336725e797b31f00a5ebdc --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_icache.h @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_icache.h + * @brief Instruction Cache (ICACHE) control + * @version V0.0.1 + * @date 01 Jan 2026 + **********************************************************************************************************************/ + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_ICACHE RH850 Instruction Cache (ICACHE) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief ICACHE API and data types + * @{ + */ + +#ifndef RH850_G4_ICACHE_H + #define RH850_G4_ICACHE_H + + #include + +/* ##################################### ICACHE Types and Enumerations ############################################ */ + +/** + * @defgroup RH850_ICACHE_Types ICACHE Types and Enumerations + * @brief ICACHE Types and Enumerations + * @ingroup RH850_ICACHE + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @enum rh850_icache_size_t + * @brief Instruction cache size options. + * @details Represents the total capacity of the instruction cache in kilobytes. Values map directly to the + * ICCFG.ICHSIZE field mask used by hardware. + */ +typedef enum e_rh850_icache_size +{ + RH850_ICACHE_SIZE_8KB = 0x0800, /*!< ICache size 8KB */ + RH850_ICACHE_SIZE_16KB = 0x1000, /*!< ICache size 16KB */ + RH850_ICACHE_SIZE_32KB = 0x2000, /*!< ICache size 32KB */ +} rh850_icache_size_t; + +/** + * @enum rh850_icache_line_t + * @brief Number of lines per way in the instruction cache. + * @details Encodes the ICCFG.ICHLINE field. Each value expresses how many cache lines are provided per way. + * Typical configurations are 64, 128, or 256 lines per way. + */ +typedef enum e_rh850_icache_line +{ + RH850_ICACHE_LINE_64 = 0x20, /*!< ICache line 64 */ + RH850_ICACHE_LINE_128 = 0x40, /*!< ICache line 128 */ + RH850_ICACHE_LINE_256 = 0x80 /*!< ICache line 256 */ +} rh850_icache_line_t; + +/** + * @enum rh850_icache_way_t + * @brief Number of ways in the instruction cache. + * @details Encodes the ICCFG.ICHWAY field. Use this to interpret or present associativity reported by hardware. + */ +typedef enum e_rh850_icache_way +{ + RH850_ICACHE_WAY_4 = 0x4, /*!< ICache line 4 */ +} rh850_icache_way_t; + +/** + * @enum rh850_icache_error_indx_t + * @brief Cache error index values. + * @details Mirrors the ICERR.ICHEIX field. Each value selects the cache index where an error occurred. + */ +typedef enum e_rh850_icache_error_indx +{ + RH850_ICACHE_ERROR_INDX_0 = 0x000, /*!< Cache error index: 0 */ + RH850_ICACHE_ERROR_INDX_1 = 0x020, /*!< Cache error index: 1 */ + RH850_ICACHE_ERROR_INDX_2 = 0x040, /*!< Cache error index: 2 */ + RH850_ICACHE_ERROR_INDX_3 = 0x060, /*!< Cache error index: 3 */ + RH850_ICACHE_ERROR_INDX_4 = 0x080, /*!< Cache error index: 4 */ + RH850_ICACHE_ERROR_INDX_5 = 0x0A0, /*!< Cache error index: 5 */ + RH850_ICACHE_ERROR_INDX_6 = 0x0C0, /*!< Cache error index: 6 */ + RH850_ICACHE_ERROR_INDX_7 = 0x0E0, /*!< Cache error index: 7 */ + RH850_ICACHE_ERROR_INDX_8 = 0x100, /*!< Cache error index: 8 */ + RH850_ICACHE_ERROR_INDX_9 = 0x120, /*!< Cache error index: 9 */ + RH850_ICACHE_ERROR_INDX_10 = 0x140, /*!< Cache error index: 10 */ + RH850_ICACHE_ERROR_INDX_11 = 0x160, /*!< Cache error index: 11 */ + RH850_ICACHE_ERROR_INDX_12 = 0x180, /*!< Cache error index: 12 */ + RH850_ICACHE_ERROR_INDX_13 = 0x1A0, /*!< Cache error index: 13 */ + RH850_ICACHE_ERROR_INDX_14 = 0x1C0, /*!< Cache error index: 14 */ + RH850_ICACHE_ERROR_INDX_15 = 0x1E0, /*!< Cache error index: 15 */ + RH850_ICACHE_ERROR_INDX_16 = 0x200, /*!< Cache error index: 16 */ + RH850_ICACHE_ERROR_INDX_17 = 0x220, /*!< Cache error index: 17 */ + RH850_ICACHE_ERROR_INDX_18 = 0x240, /*!< Cache error index: 18 */ + RH850_ICACHE_ERROR_INDX_19 = 0x260, /*!< Cache error index: 19 */ + RH850_ICACHE_ERROR_INDX_20 = 0x280, /*!< Cache error index: 20 */ + RH850_ICACHE_ERROR_INDX_21 = 0x2A0, /*!< Cache error index: 21 */ + RH850_ICACHE_ERROR_INDX_22 = 0x2C0, /*!< Cache error index: 22 */ + RH850_ICACHE_ERROR_INDX_23 = 0x2E0, /*!< Cache error index: 23 */ + RH850_ICACHE_ERROR_INDX_24 = 0x300, /*!< Cache error index: 24 */ + RH850_ICACHE_ERROR_INDX_25 = 0x320, /*!< Cache error index: 25 */ + RH850_ICACHE_ERROR_INDX_26 = 0x340, /*!< Cache error index: 26 */ + RH850_ICACHE_ERROR_INDX_27 = 0x360, /*!< Cache error index: 27 */ + RH850_ICACHE_ERROR_INDX_28 = 0x380, /*!< Cache error index: 28 */ + RH850_ICACHE_ERROR_INDX_29 = 0x3A0, /*!< Cache error index: 29 */ + RH850_ICACHE_ERROR_INDX_30 = 0x3C0, /*!< Cache error index: 30 */ + RH850_ICACHE_ERROR_INDX_31 = 0x3E0, /*!< Cache error index: 31 */ + RH850_ICACHE_ERROR_INDX_32 = 0x400, /*!< Cache error index: 32 */ + RH850_ICACHE_ERROR_INDX_33 = 0x420, /*!< Cache error index: 33 */ + RH850_ICACHE_ERROR_INDX_34 = 0x440, /*!< Cache error index: 34 */ + RH850_ICACHE_ERROR_INDX_35 = 0x460, /*!< Cache error index: 35 */ + RH850_ICACHE_ERROR_INDX_36 = 0x480, /*!< Cache error index: 36 */ + RH850_ICACHE_ERROR_INDX_37 = 0x4A0, /*!< Cache error index: 37 */ + RH850_ICACHE_ERROR_INDX_38 = 0x4C0, /*!< Cache error index: 38 */ + RH850_ICACHE_ERROR_INDX_39 = 0x4E0, /*!< Cache error index: 39 */ + RH850_ICACHE_ERROR_INDX_40 = 0x500, /*!< Cache error index: 40 */ + RH850_ICACHE_ERROR_INDX_41 = 0x520, /*!< Cache error index: 41 */ + RH850_ICACHE_ERROR_INDX_42 = 0x540, /*!< Cache error index: 42 */ + RH850_ICACHE_ERROR_INDX_43 = 0x560, /*!< Cache error index: 43 */ + RH850_ICACHE_ERROR_INDX_44 = 0x580, /*!< Cache error index: 44 */ + RH850_ICACHE_ERROR_INDX_45 = 0x5A0, /*!< Cache error index: 45 */ + RH850_ICACHE_ERROR_INDX_46 = 0x5C0, /*!< Cache error index: 46 */ + RH850_ICACHE_ERROR_INDX_47 = 0x5E0, /*!< Cache error index: 47 */ + RH850_ICACHE_ERROR_INDX_48 = 0x600, /*!< Cache error index: 48 */ + RH850_ICACHE_ERROR_INDX_49 = 0x620, /*!< Cache error index: 49 */ + RH850_ICACHE_ERROR_INDX_50 = 0x640, /*!< Cache error index: 50 */ + RH850_ICACHE_ERROR_INDX_51 = 0x660, /*!< Cache error index: 51 */ + RH850_ICACHE_ERROR_INDX_52 = 0x680, /*!< Cache error index: 52 */ + RH850_ICACHE_ERROR_INDX_53 = 0x6A0, /*!< Cache error index: 53 */ + RH850_ICACHE_ERROR_INDX_54 = 0x6C0, /*!< Cache error index: 54 */ + RH850_ICACHE_ERROR_INDX_55 = 0x6E0, /*!< Cache error index: 55 */ + RH850_ICACHE_ERROR_INDX_56 = 0x700, /*!< Cache error index: 56 */ + RH850_ICACHE_ERROR_INDX_57 = 0x720, /*!< Cache error index: 57 */ + RH850_ICACHE_ERROR_INDX_58 = 0x740, /*!< Cache error index: 58 */ + RH850_ICACHE_ERROR_INDX_59 = 0x760, /*!< Cache error index: 59 */ + RH850_ICACHE_ERROR_INDX_60 = 0x780, /*!< Cache error index: 60 */ + RH850_ICACHE_ERROR_INDX_61 = 0x7A0, /*!< Cache error index: 61 */ + RH850_ICACHE_ERROR_INDX_62 = 0x7C0, /*!< Cache error index: 62 */ + RH850_ICACHE_ERROR_INDX_63 = 0x7E0, /*!< Cache error index: 63 */ + RH850_ICACHE_ERROR_INDX_64 = 0x800, /*!< Cache error index: 64 */ + RH850_ICACHE_ERROR_INDX_65 = 0x820, /*!< Cache error index: 65 */ + RH850_ICACHE_ERROR_INDX_66 = 0x840, /*!< Cache error index: 66 */ + RH850_ICACHE_ERROR_INDX_67 = 0x860, /*!< Cache error index: 67 */ + RH850_ICACHE_ERROR_INDX_68 = 0x880, /*!< Cache error index: 68 */ + RH850_ICACHE_ERROR_INDX_69 = 0x8A0, /*!< Cache error index: 69 */ + RH850_ICACHE_ERROR_INDX_70 = 0x8C0, /*!< Cache error index: 70 */ + RH850_ICACHE_ERROR_INDX_71 = 0x8E0, /*!< Cache error index: 71 */ + RH850_ICACHE_ERROR_INDX_72 = 0x900, /*!< Cache error index: 72 */ + RH850_ICACHE_ERROR_INDX_73 = 0x920, /*!< Cache error index: 73 */ + RH850_ICACHE_ERROR_INDX_74 = 0x940, /*!< Cache error index: 74 */ + RH850_ICACHE_ERROR_INDX_75 = 0x960, /*!< Cache error index: 75 */ + RH850_ICACHE_ERROR_INDX_76 = 0x980, /*!< Cache error index: 76 */ + RH850_ICACHE_ERROR_INDX_77 = 0x9A0, /*!< Cache error index: 77 */ + RH850_ICACHE_ERROR_INDX_78 = 0x9C0, /*!< Cache error index: 78 */ + RH850_ICACHE_ERROR_INDX_79 = 0x9E0, /*!< Cache error index: 79 */ + RH850_ICACHE_ERROR_INDX_80 = 0xA00, /*!< Cache error index: 80 */ + RH850_ICACHE_ERROR_INDX_81 = 0xA20, /*!< Cache error index: 81 */ + RH850_ICACHE_ERROR_INDX_82 = 0xA40, /*!< Cache error index: 82 */ + RH850_ICACHE_ERROR_INDX_83 = 0xA60, /*!< Cache error index: 83 */ + RH850_ICACHE_ERROR_INDX_84 = 0xA80, /*!< Cache error index: 84 */ + RH850_ICACHE_ERROR_INDX_85 = 0xAA0, /*!< Cache error index: 85 */ + RH850_ICACHE_ERROR_INDX_86 = 0xAC0, /*!< Cache error index: 86 */ + RH850_ICACHE_ERROR_INDX_87 = 0xAE0, /*!< Cache error index: 87 */ + RH850_ICACHE_ERROR_INDX_88 = 0xB00, /*!< Cache error index: 88 */ + RH850_ICACHE_ERROR_INDX_89 = 0xB20, /*!< Cache error index: 89 */ + RH850_ICACHE_ERROR_INDX_90 = 0xB40, /*!< Cache error index: 90 */ + RH850_ICACHE_ERROR_INDX_91 = 0xB60, /*!< Cache error index: 91 */ + RH850_ICACHE_ERROR_INDX_92 = 0xB80, /*!< Cache error index: 92 */ + RH850_ICACHE_ERROR_INDX_93 = 0xBA0, /*!< Cache error index: 93 */ + RH850_ICACHE_ERROR_INDX_94 = 0xBC0, /*!< Cache error index: 94 */ + RH850_ICACHE_ERROR_INDX_95 = 0xBE0, /*!< Cache error index: 95 */ + RH850_ICACHE_ERROR_INDX_96 = 0xC00, /*!< Cache error index: 96 */ + RH850_ICACHE_ERROR_INDX_97 = 0xC20, /*!< Cache error index: 97 */ + RH850_ICACHE_ERROR_INDX_98 = 0xC40, /*!< Cache error index: 98 */ + RH850_ICACHE_ERROR_INDX_99 = 0xC60, /*!< Cache error index: 99 */ + RH850_ICACHE_ERROR_INDX_100 = 0xC80, /*!< Cache error index: 100 */ + RH850_ICACHE_ERROR_INDX_101 = 0xCA0, /*!< Cache error index: 101 */ + RH850_ICACHE_ERROR_INDX_102 = 0xCC0, /*!< Cache error index: 102 */ + RH850_ICACHE_ERROR_INDX_103 = 0xCE0, /*!< Cache error index: 103 */ + RH850_ICACHE_ERROR_INDX_104 = 0xD00, /*!< Cache error index: 104 */ + RH850_ICACHE_ERROR_INDX_105 = 0xD20, /*!< Cache error index: 105 */ + RH850_ICACHE_ERROR_INDX_106 = 0xD40, /*!< Cache error index: 106 */ + RH850_ICACHE_ERROR_INDX_107 = 0xD60, /*!< Cache error index: 107 */ + RH850_ICACHE_ERROR_INDX_108 = 0xD80, /*!< Cache error index: 108 */ + RH850_ICACHE_ERROR_INDX_109 = 0xDA0, /*!< Cache error index: 109 */ + RH850_ICACHE_ERROR_INDX_110 = 0xDC0, /*!< Cache error index: 110 */ + RH850_ICACHE_ERROR_INDX_111 = 0xDE0, /*!< Cache error index: 111 */ + RH850_ICACHE_ERROR_INDX_112 = 0xE00, /*!< Cache error index: 112 */ + RH850_ICACHE_ERROR_INDX_113 = 0xE20, /*!< Cache error index: 113 */ + RH850_ICACHE_ERROR_INDX_114 = 0xE40, /*!< Cache error index: 114 */ + RH850_ICACHE_ERROR_INDX_115 = 0xE60, /*!< Cache error index: 115 */ + RH850_ICACHE_ERROR_INDX_116 = 0xE80, /*!< Cache error index: 116 */ + RH850_ICACHE_ERROR_INDX_117 = 0xEA0, /*!< Cache error index: 117 */ + RH850_ICACHE_ERROR_INDX_118 = 0xEC0, /*!< Cache error index: 118 */ + RH850_ICACHE_ERROR_INDX_119 = 0xEE0, /*!< Cache error index: 119 */ + RH850_ICACHE_ERROR_INDX_120 = 0xF00, /*!< Cache error index: 120 */ + RH850_ICACHE_ERROR_INDX_121 = 0xF20, /*!< Cache error index: 121 */ + RH850_ICACHE_ERROR_INDX_122 = 0xF40, /*!< Cache error index: 122 */ + RH850_ICACHE_ERROR_INDX_123 = 0xF60, /*!< Cache error index: 123 */ + RH850_ICACHE_ERROR_INDX_124 = 0xF80, /*!< Cache error index: 124 */ + RH850_ICACHE_ERROR_INDX_125 = 0xFA0, /*!< Cache error index: 125 */ + RH850_ICACHE_ERROR_INDX_126 = 0xFC0, /*!< Cache error index: 126 */ + RH850_ICACHE_ERROR_INDX_127 = 0xFE0, /*!< Cache error index: 127 */ + RH850_ICACHE_ERROR_INDX_128 = 0x1000, /*!< Cache error index: 128 */ + RH850_ICACHE_ERROR_INDX_129 = 0x1020, /*!< Cache error index: 129 */ + RH850_ICACHE_ERROR_INDX_130 = 0x1040, /*!< Cache error index: 130 */ + RH850_ICACHE_ERROR_INDX_131 = 0x1060, /*!< Cache error index: 131 */ + RH850_ICACHE_ERROR_INDX_132 = 0x1080, /*!< Cache error index: 132 */ + RH850_ICACHE_ERROR_INDX_133 = 0x10A0, /*!< Cache error index: 133 */ + RH850_ICACHE_ERROR_INDX_134 = 0x10C0, /*!< Cache error index: 134 */ + RH850_ICACHE_ERROR_INDX_135 = 0x10E0, /*!< Cache error index: 135 */ + RH850_ICACHE_ERROR_INDX_136 = 0x1100, /*!< Cache error index: 136 */ + RH850_ICACHE_ERROR_INDX_137 = 0x1120, /*!< Cache error index: 137 */ + RH850_ICACHE_ERROR_INDX_138 = 0x1140, /*!< Cache error index: 138 */ + RH850_ICACHE_ERROR_INDX_139 = 0x1160, /*!< Cache error index: 139 */ + RH850_ICACHE_ERROR_INDX_140 = 0x1180, /*!< Cache error index: 140 */ + RH850_ICACHE_ERROR_INDX_141 = 0x11A0, /*!< Cache error index: 141 */ + RH850_ICACHE_ERROR_INDX_142 = 0x11C0, /*!< Cache error index: 142 */ + RH850_ICACHE_ERROR_INDX_143 = 0x11E0, /*!< Cache error index: 143 */ + RH850_ICACHE_ERROR_INDX_144 = 0x1200, /*!< Cache error index: 144 */ + RH850_ICACHE_ERROR_INDX_145 = 0x1220, /*!< Cache error index: 145 */ + RH850_ICACHE_ERROR_INDX_146 = 0x1240, /*!< Cache error index: 146 */ + RH850_ICACHE_ERROR_INDX_147 = 0x1260, /*!< Cache error index: 147 */ + RH850_ICACHE_ERROR_INDX_148 = 0x1280, /*!< Cache error index: 148 */ + RH850_ICACHE_ERROR_INDX_149 = 0x12A0, /*!< Cache error index: 149 */ + RH850_ICACHE_ERROR_INDX_150 = 0x12C0, /*!< Cache error index: 150 */ + RH850_ICACHE_ERROR_INDX_151 = 0x12E0, /*!< Cache error index: 151 */ + RH850_ICACHE_ERROR_INDX_152 = 0x1300, /*!< Cache error index: 152 */ + RH850_ICACHE_ERROR_INDX_153 = 0x1320, /*!< Cache error index: 153 */ + RH850_ICACHE_ERROR_INDX_154 = 0x1340, /*!< Cache error index: 154 */ + RH850_ICACHE_ERROR_INDX_155 = 0x1360, /*!< Cache error index: 155 */ + RH850_ICACHE_ERROR_INDX_156 = 0x1380, /*!< Cache error index: 156 */ + RH850_ICACHE_ERROR_INDX_157 = 0x13A0, /*!< Cache error index: 157 */ + RH850_ICACHE_ERROR_INDX_158 = 0x13C0, /*!< Cache error index: 158 */ + RH850_ICACHE_ERROR_INDX_159 = 0x13E0, /*!< Cache error index: 159 */ + RH850_ICACHE_ERROR_INDX_160 = 0x1400, /*!< Cache error index: 160 */ + RH850_ICACHE_ERROR_INDX_161 = 0x1420, /*!< Cache error index: 161 */ + RH850_ICACHE_ERROR_INDX_162 = 0x1440, /*!< Cache error index: 162 */ + RH850_ICACHE_ERROR_INDX_163 = 0x1460, /*!< Cache error index: 163 */ + RH850_ICACHE_ERROR_INDX_164 = 0x1480, /*!< Cache error index: 164 */ + RH850_ICACHE_ERROR_INDX_165 = 0x14A0, /*!< Cache error index: 165 */ + RH850_ICACHE_ERROR_INDX_166 = 0x14C0, /*!< Cache error index: 166 */ + RH850_ICACHE_ERROR_INDX_167 = 0x14E0, /*!< Cache error index: 167 */ + RH850_ICACHE_ERROR_INDX_168 = 0x1500, /*!< Cache error index: 168 */ + RH850_ICACHE_ERROR_INDX_169 = 0x1520, /*!< Cache error index: 169 */ + RH850_ICACHE_ERROR_INDX_170 = 0x1540, /*!< Cache error index: 170 */ + RH850_ICACHE_ERROR_INDX_171 = 0x1560, /*!< Cache error index: 171 */ + RH850_ICACHE_ERROR_INDX_172 = 0x1580, /*!< Cache error index: 172 */ + RH850_ICACHE_ERROR_INDX_173 = 0x15A0, /*!< Cache error index: 173 */ + RH850_ICACHE_ERROR_INDX_174 = 0x15C0, /*!< Cache error index: 174 */ + RH850_ICACHE_ERROR_INDX_175 = 0x15E0, /*!< Cache error index: 175 */ + RH850_ICACHE_ERROR_INDX_176 = 0x1600, /*!< Cache error index: 176 */ + RH850_ICACHE_ERROR_INDX_177 = 0x1620, /*!< Cache error index: 177 */ + RH850_ICACHE_ERROR_INDX_178 = 0x1640, /*!< Cache error index: 178 */ + RH850_ICACHE_ERROR_INDX_179 = 0x1660, /*!< Cache error index: 179 */ + RH850_ICACHE_ERROR_INDX_180 = 0x1680, /*!< Cache error index: 180 */ + RH850_ICACHE_ERROR_INDX_181 = 0x16A0, /*!< Cache error index: 181 */ + RH850_ICACHE_ERROR_INDX_182 = 0x16C0, /*!< Cache error index: 182 */ + RH850_ICACHE_ERROR_INDX_183 = 0x16E0, /*!< Cache error index: 183 */ + RH850_ICACHE_ERROR_INDX_184 = 0x1700, /*!< Cache error index: 184 */ + RH850_ICACHE_ERROR_INDX_185 = 0x1720, /*!< Cache error index: 185 */ + RH850_ICACHE_ERROR_INDX_186 = 0x1740, /*!< Cache error index: 186 */ + RH850_ICACHE_ERROR_INDX_187 = 0x1760, /*!< Cache error index: 187 */ + RH850_ICACHE_ERROR_INDX_188 = 0x1780, /*!< Cache error index: 188 */ + RH850_ICACHE_ERROR_INDX_189 = 0x17A0, /*!< Cache error index: 189 */ + RH850_ICACHE_ERROR_INDX_190 = 0x17C0, /*!< Cache error index: 190 */ + RH850_ICACHE_ERROR_INDX_191 = 0x17E0, /*!< Cache error index: 191 */ + RH850_ICACHE_ERROR_INDX_192 = 0x1800, /*!< Cache error index: 192 */ + RH850_ICACHE_ERROR_INDX_193 = 0x1820, /*!< Cache error index: 193 */ + RH850_ICACHE_ERROR_INDX_194 = 0x1840, /*!< Cache error index: 194 */ + RH850_ICACHE_ERROR_INDX_195 = 0x1860, /*!< Cache error index: 195 */ + RH850_ICACHE_ERROR_INDX_196 = 0x1880, /*!< Cache error index: 196 */ + RH850_ICACHE_ERROR_INDX_197 = 0x18A0, /*!< Cache error index: 197 */ + RH850_ICACHE_ERROR_INDX_198 = 0x18C0, /*!< Cache error index: 198 */ + RH850_ICACHE_ERROR_INDX_199 = 0x18E0, /*!< Cache error index: 199 */ + RH850_ICACHE_ERROR_INDX_200 = 0x1900, /*!< Cache error index: 200 */ + RH850_ICACHE_ERROR_INDX_201 = 0x1920, /*!< Cache error index: 201 */ + RH850_ICACHE_ERROR_INDX_202 = 0x1940, /*!< Cache error index: 202 */ + RH850_ICACHE_ERROR_INDX_203 = 0x1960, /*!< Cache error index: 203 */ + RH850_ICACHE_ERROR_INDX_204 = 0x1980, /*!< Cache error index: 204 */ + RH850_ICACHE_ERROR_INDX_205 = 0x19A0, /*!< Cache error index: 205 */ + RH850_ICACHE_ERROR_INDX_206 = 0x19C0, /*!< Cache error index: 206 */ + RH850_ICACHE_ERROR_INDX_207 = 0x19E0, /*!< Cache error index: 207 */ + RH850_ICACHE_ERROR_INDX_208 = 0x1A00, /*!< Cache error index: 208 */ + RH850_ICACHE_ERROR_INDX_209 = 0x1A20, /*!< Cache error index: 209 */ + RH850_ICACHE_ERROR_INDX_210 = 0x1A40, /*!< Cache error index: 210 */ + RH850_ICACHE_ERROR_INDX_211 = 0x1A60, /*!< Cache error index: 211 */ + RH850_ICACHE_ERROR_INDX_212 = 0x1A80, /*!< Cache error index: 212 */ + RH850_ICACHE_ERROR_INDX_213 = 0x1AA0, /*!< Cache error index: 213 */ + RH850_ICACHE_ERROR_INDX_214 = 0x1AC0, /*!< Cache error index: 214 */ + RH850_ICACHE_ERROR_INDX_215 = 0x1AE0, /*!< Cache error index: 215 */ + RH850_ICACHE_ERROR_INDX_216 = 0x1B00, /*!< Cache error index: 216 */ + RH850_ICACHE_ERROR_INDX_217 = 0x1B20, /*!< Cache error index: 217 */ + RH850_ICACHE_ERROR_INDX_218 = 0x1B40, /*!< Cache error index: 218 */ + RH850_ICACHE_ERROR_INDX_219 = 0x1B60, /*!< Cache error index: 219 */ + RH850_ICACHE_ERROR_INDX_220 = 0x1B80, /*!< Cache error index: 220 */ + RH850_ICACHE_ERROR_INDX_221 = 0x1BA0, /*!< Cache error index: 221 */ + RH850_ICACHE_ERROR_INDX_222 = 0x1BC0, /*!< Cache error index: 222 */ + RH850_ICACHE_ERROR_INDX_223 = 0x1BE0, /*!< Cache error index: 223 */ + RH850_ICACHE_ERROR_INDX_224 = 0x1C00, /*!< Cache error index: 224 */ + RH850_ICACHE_ERROR_INDX_225 = 0x1C20, /*!< Cache error index: 225 */ + RH850_ICACHE_ERROR_INDX_226 = 0x1C40, /*!< Cache error index: 226 */ + RH850_ICACHE_ERROR_INDX_227 = 0x1C60, /*!< Cache error index: 227 */ + RH850_ICACHE_ERROR_INDX_228 = 0x1C80, /*!< Cache error index: 228 */ + RH850_ICACHE_ERROR_INDX_229 = 0x1CA0, /*!< Cache error index: 229 */ + RH850_ICACHE_ERROR_INDX_230 = 0x1CC0, /*!< Cache error index: 230 */ + RH850_ICACHE_ERROR_INDX_231 = 0x1CE0, /*!< Cache error index: 231 */ + RH850_ICACHE_ERROR_INDX_232 = 0x1D00, /*!< Cache error index: 232 */ + RH850_ICACHE_ERROR_INDX_233 = 0x1D20, /*!< Cache error index: 233 */ + RH850_ICACHE_ERROR_INDX_234 = 0x1D40, /*!< Cache error index: 234 */ + RH850_ICACHE_ERROR_INDX_235 = 0x1D60, /*!< Cache error index: 235 */ + RH850_ICACHE_ERROR_INDX_236 = 0x1D80, /*!< Cache error index: 236 */ + RH850_ICACHE_ERROR_INDX_237 = 0x1DA0, /*!< Cache error index: 237 */ + RH850_ICACHE_ERROR_INDX_238 = 0x1DC0, /*!< Cache error index: 238 */ + RH850_ICACHE_ERROR_INDX_239 = 0x1DE0, /*!< Cache error index: 239 */ + RH850_ICACHE_ERROR_INDX_240 = 0x1E00, /*!< Cache error index: 240 */ + RH850_ICACHE_ERROR_INDX_241 = 0x1E20, /*!< Cache error index: 241 */ + RH850_ICACHE_ERROR_INDX_242 = 0x1E40, /*!< Cache error index: 242 */ + RH850_ICACHE_ERROR_INDX_243 = 0x1E60, /*!< Cache error index: 243 */ + RH850_ICACHE_ERROR_INDX_244 = 0x1E80, /*!< Cache error index: 244 */ + RH850_ICACHE_ERROR_INDX_245 = 0x1EA0, /*!< Cache error index: 245 */ + RH850_ICACHE_ERROR_INDX_246 = 0x1EC0, /*!< Cache error index: 246 */ + RH850_ICACHE_ERROR_INDX_247 = 0x1EE0, /*!< Cache error index: 247 */ + RH850_ICACHE_ERROR_INDX_248 = 0x1F00, /*!< Cache error index: 248 */ + RH850_ICACHE_ERROR_INDX_249 = 0x1F20, /*!< Cache error index: 249 */ + RH850_ICACHE_ERROR_INDX_250 = 0x1F40, /*!< Cache error index: 250 */ + RH850_ICACHE_ERROR_INDX_251 = 0x1F60, /*!< Cache error index: 251 */ + RH850_ICACHE_ERROR_INDX_252 = 0x1F80, /*!< Cache error index: 252 */ + RH850_ICACHE_ERROR_INDX_253 = 0x1FA0, /*!< Cache error index: 253 */ + RH850_ICACHE_ERROR_INDX_254 = 0x1FC0, /*!< Cache error index: 254 */ + RH850_ICACHE_ERROR_INDX_255 = 0x1FE0 /*!< Cache error index: 255 */ +} rh850_icache_error_indx_t; + +/** + * @enum rh850_icache_error_way_t + * @brief Cache error way values. + * @details Mirrors the ICERR.ICHEWY field to indicate in which way an error occurred. Use this value along with + * the index to locate the failing cache line. + */ +typedef enum e_rh850_icache_error_way +{ + RH850_ICACHE_ERROR_WAY_0 = 0x0000, /*!< Cache error way: 0 */ + RH850_ICACHE_ERROR_WAY_1 = 0x2000, /*!< Cache error way: 1 */ + RH850_ICACHE_ERROR_WAY_2 = 0x4000, /*!< Cache error way: 2 */ + RH850_ICACHE_ERROR_WAY_3 = 0x6000 /*!< Cache error way: 3 */ +} rh850_icache_error_way_t; + +/** + * @enum rh850_icache_enable_t + * @brief Cache enable state. + * @details Indicates whether the instruction cache is enabled (ON) or disabled (OFF) as reflected by ICCTRL.ICHEN. + */ +typedef enum e_rh850_icache_enable +{ + RH850_ICACHE_ENABLE_OFF = 0x0, /*!< Cache enable: OFF */ + RH850_ICACHE_ENABLE_ON = 0x1 /*!< Cache enable: ON */ +} rh850_icache_enable_t; + +/** + * @enum rh850_icache_auto_invalidate_mode_t + * @brief Auto-invalidate on error mode. + * @details Controls automatic invalidation when a cache error occurs. When enabled, hardware clears ICHEN on error + * to prevent further fetches from corrupted lines. + */ +typedef enum e_rh850_icache_auto_invalidate_mode +{ + RH850_ICACHE_AUTO_INVALIDATE_MODE_DISABLE = 0, /*!< Auto invalidate mode: DISABLE */ + RH850_ICACHE_AUTO_INVALIDATE_MODE_ENABLE = 1 /*!< Auto invalidate mode: ENABLE */ +} rh850_icache_auto_invalidate_mode_t; + +/** + * @enum rh850_icache_notify_t + * @brief Error notification mask mode. + * @details Controls ICHEMK (mask/unmask cache error notification). + */ +typedef enum e_rh850_icache_notify +{ + RH850_ICACHE_NOTIFY_UNMASK = 0, /*!< Cache notify: UNMASK */ + RH850_ICACHE_NOTIFY_MASK = 1 /*!< Cache notify: MASK */ +} rh850_icache_notify_t; + +/** @} */ /* end of RH850_ICACHE_Types */ + +/* ########################################## ICACHE API Functions ################################################ */ + +/** + * @defgroup RH850_ICACHE_API ICACHE API Functions + * @brief ICACHE API Functions + * @ingroup RH850_ICACHE + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief Enable the instruction cache. + * @details Reads ICCTRL, sets ICHEN, writes back. Other bits are preserved. + */ +__STATIC_INLINE void __RH850_ICache_Enable (void) +{ + uint32_t LulIcctrlRegValue; + + /* Read current control */ + LulIcctrlRegValue = __get_ICCTRL(); + + /* Enable cache */ + LulIcctrlRegValue |= R_ICACHE_ICCTRL_ICHEN_Msk; + + /* Write back */ + __set_ICCTRL(LulIcctrlRegValue); +} + +/** + * @brief Disable the instruction cache. + * @details Clears ICHEN via read–modify–write. Other bits preserved. + */ +__STATIC_INLINE void __RH850_ICache_Disable (void) +{ + uint32_t LulIcctrlRegValue; + + /* Read current control */ + LulIcctrlRegValue = __get_ICCTRL(); + LulIcctrlRegValue &= (~R_ICACHE_ICCTRL_ICHEN_Msk); + + /* Write back */ + __set_ICCTRL(LulIcctrlRegValue); +} + +/** + * @brief Get the instruction cache size. + * @details Masks ICCFG.ICHSIZE and returns a rh850_icache_size_t. + * @return Cache size enumeration. + */ +__STATIC_INLINE rh850_icache_size_t __RH850_ICache_CacheSizeGet (void) +{ + /* Mask size field */ + return (rh850_icache_size_t) (__get_ICCFG() & R_ICACHE_ICCFG_ICHSIZE_Msk); +} + +/** + * @brief Get lines per way. + * @details Masks ICCFG.ICHLINE and returns a rh850_icache_line_t. + * @return Lines-per-way enumeration. + */ +__STATIC_INLINE rh850_icache_line_t __RH850_ICache_LinesPerWayGet (void) +{ + return (rh850_icache_line_t) (__get_ICCFG() & R_ICACHE_ICCFG_ICHLINE_Msk); +} + +/** + * @brief Get number of ways. + * @details Masks ICCFG.ICHWAY and returns a rh850_icache_way_t. + * @return Ways enumeration. + */ +__STATIC_INLINE rh850_icache_way_t __RH850_ICache_NumberOfWaysGet (void) +{ + return (rh850_icache_way_t) (__get_ICCFG() & R_ICACHE_ICCFG_ICHWAY_Msk); +} + +/** + * @brief Get raw error register snapshot. + * @details Returns the ICERR typed value for bitfield inspection. + * @return uint32_t snapshot. + */ +__STATIC_INLINE uint32_t __RH850_ICache_ErrorStatusGet (void) +{ + return (uint32_t) __get_ICERR(); +} + +/** + * @brief Get the error index from ICERR. + * @details Extracts ICERR.ICHEIX into rh850_icache_error_indx_t. + * @return Error index enumeration. + */ +__STATIC_INLINE rh850_icache_error_indx_t __RH850_ICache_ErrorIndexGet (void) +{ + return (rh850_icache_error_indx_t) (__get_ICERR() & R_ICACHE_ICERR_ICHEIX_Msk); +} + +/** + * @brief Get the error way from ICERR. + * @details Extracts ICERR.ICHEWY into rh850_icache_error_way_t. + * @return Error way enumeration. + */ +__STATIC_INLINE rh850_icache_error_way_t __RH850_ICache_ErrorWayGet (void) +{ + return (rh850_icache_error_way_t) (__get_ICERR() & R_ICACHE_ICERR_ICHEWY_Msk); +} + +/** + * @brief Get current cache enable state. + * @details Reads ICCTRL.ICHEN and returns ON/OFF state. + * @return rh850_icache_enable_t state. + */ +__STATIC_INLINE rh850_icache_enable_t __RH850_ICache_EnableGet (void) +{ + return (__get_ICCTRL() & R_ICACHE_ICCTRL_ICHEN_Msk) ? RH850_ICACHE_ENABLE_ON : RH850_ICACHE_ENABLE_OFF; +} + +/** + * @brief Clear the entire instruction cache. + * @details Sets ICCTRL.ICHCLR (write-only) to clear all lines and reset V/L & LRU info. + */ +__STATIC_INLINE void __RH850_ICache_Clear (void) +{ + uint32_t LulIcctrlRegValue; + + /* Set clear bit (write-only, reads as 0) */ + LulIcctrlRegValue = __get_ICCTRL(); + LulIcctrlRegValue |= R_ICACHE_ICCTRL_ICHCLR_Msk; + + /* Write back */ + __set_ICCTRL(LulIcctrlRegValue); +} + +/** + * @brief Configure auto-invalidate on cache error. + * @details Sets or clears ICCTRL.ICHEIV according to @p LenMode. + * @param LenMode See rh850_icache_auto_invalidate_mode_t. + */ +__STATIC_INLINE void __RH850_ICache_AutoInvalidateOnErrorSet (rh850_icache_auto_invalidate_mode_t LenMode) +{ + uint32_t LulIcctrlRegValue; + + /* Clear bit, then apply mode */ + LulIcctrlRegValue = __get_ICCTRL(); + LulIcctrlRegValue &= ~R_ICACHE_ICCTRL_ICHEIV_Msk; + if (LenMode == RH850_ICACHE_AUTO_INVALIDATE_MODE_ENABLE) + { + LulIcctrlRegValue |= R_ICACHE_ICCTRL_ICHEIV_Msk; + } + + __set_ICCTRL(LulIcctrlRegValue); +} + +/** + * @brief Configure error notification masking. + * @details Sets or clears ICCTRL.ICHEMK according to @p LenMode. + * @param LenMode See rh850_icache_notify_t. + */ +__STATIC_INLINE void __RH850_ICache_ErrorNotifyMaskSet (rh850_icache_notify_t LenMode) +{ + uint32_t LulIcctrlRegValue; + + /* Clear bit, then apply mode */ + LulIcctrlRegValue = __get_ICCTRL(); + LulIcctrlRegValue &= ~R_ICACHE_ICCTRL_ICHEMK_Msk; + if (LenMode == RH850_ICACHE_NOTIFY_MASK) + { + LulIcctrlRegValue |= R_ICACHE_ICCTRL_ICHEMK_Msk; + } + + __set_ICCTRL(LulIcctrlRegValue); +} + +/** + * @brief Read the Tag Low register snapshot. + * @details Returns uint32_t for V/L bits, LRU info, and LPN inspection. + * @return uint32_t value. + */ +__STATIC_INLINE uint32_t __RH850_ICache_TagLoGet (void) +{ + return (uint32_t) __get_ICTAGL(); +} + +/** + * @brief Write the Tag Low register. + * @details Writes uint32_t to ICTAGL; use correct WT semantics. + * @param LulValue Tag Low typed value to write. + */ +__STATIC_INLINE void __RH850_ICache_TagLoSet (uint32_t LulValue) +{ + (void) __set_ICTAGL(LulValue); +} + +/** + * @brief Read the Tag High register snapshot. + * @details Returns uint32_t for ECC control and related flags. + * @return uint32_t value. + */ +__STATIC_INLINE uint32_t __RH850_ICache_TagHiGet (void) +{ + return (uint32_t) __get_ICTAGH(); +} + +/** + * @brief Write the Tag High register. + * @details Writes an uint32_t value to the ICTAGH register to update ECC data or control flags. + * @param LulValue Tag High typed value to write. + */ +__STATIC_INLINE void __RH850_ICache_TagHiSet (uint32_t LulValue) +{ + (void) __set_ICTAGH(LulValue); +} + +/** + * @brief Read lower 32 bits of the cache data block. + * @details Returns the ICDATL register value which corresponds to lower half of a 64-bit instruction data word. + * @return Lower 32 bits of cache data. + */ +__STATIC_INLINE uint32_t __RH850_ICache_DataLoGet (void) +{ + return (uint32_t) __get_ICDATL(); +} + +/** + * @brief Write lower 32 bits of the cache data block. + * @details Writes to ICDATL the lower half of a 64-bit instruction data word. Ensure correct index/way selection and + * ECC handling according to ICTAGH settings. + * @param LulData Lower 32-bit payload to write. + */ +__STATIC_INLINE void __RH850_ICache_DataLoSet (uint32_t LulData) +{ + (void) __set_ICDATL(LulData); +} + +/** + * @brief Read upper 32 bits of the cache data block. + * @details Returns the ICDATH register value which corresponds to upper half of a 64-bit instruction data word. + * @return Upper 32 bits of cache data. + */ +__STATIC_INLINE uint32_t __RH850_ICache_DataHiGet (void) +{ + return (uint32_t) __get_ICDATH(); +} + +/** + * @brief Write upper 32 bits of the cache data block. + * @details Writes to ICDATH the upper half of a 64-bit instruction data word. Ensure correct index/way selection and + * ECC handling according to ICTAGH settings. + * @param LulData Upper 32-bit payload to write. + */ +__STATIC_INLINE void __RH850_ICache_DataHiSet (uint32_t LulData) +{ + (void) __set_ICDATH(LulData); +} + +/** @} */ /* end of RH850_ICACHE_API */ + +#endif /* RH850_G4_ICACHE_H */ + +/** @} */ /* end of RH850_ICACHE */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ +#endif /* #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_irq.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..40fe8da364b61a16ae5003040214d348208dd310 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_irq.h @@ -0,0 +1,951 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_irq.h + * @brief Interrupt Function for RH850 G4 + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#if defined(__IRQ_PRESENT) && (__IRQ_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_IRQ RH850 Interrupt Function (IRQ) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850 IRQ API and types + * @{ + */ + +#ifndef RH850_G4_IRQ_H + #define RH850_G4_IRQ_H + + #include + +/* ####################################### IRQ Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_IRQ_Types IRQ Types and Enumerations + * @ingroup RH850_IRQ + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Determine whether IRQ belongs to INTC1 (0..31) */ + #define RH850_IRQ_IS_INTC1(_irqn) ((int32_t) (_irqn) <= 31) + +/* EEIC address for IRQn: + * - INTC1: base + PE offset + 2*IRQn + * - INTC2: base + 2*IRQn + */ + #define RH850_EEIC_ADDR(_peid, _irqn) \ + ((RH850_IRQ_IS_INTC1(_irqn)) \ + ? ((uintptr_t) (RH850_INTC1_BASE + RH850_INTC1_EEIC_OFFSET) + \ + (uintptr_t) ((uint32_t) (_peid) * (uint32_t) (RH850_INTC1_OFFSET)) + \ + (uintptr_t) ((uint32_t) (_irqn) * 4U)) \ + : ((uintptr_t) (RH850_INTC2_BASE + RH850_INTC2_EEIC_OFFSET) + \ + (uintptr_t) ((uint32_t) (_irqn) * 4U))) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @enum rh850_isr_priority_t + * @brief Interrupt priority levels for EI interrupts on RH850. + * + * This enumeration defines the priority levels corresponding to the ISPR register bits. + * @note These values map directly to ISPR bits [15:0]. + * Lower numeric values indicate higher priority. Priority 0 is the highest, and Priority 15 is the lowest. + */ +typedef enum e_rh850_isr_priority +{ + RH850_ISR_PRIORITY_0 = 0, /*!< Priority 0 (highest) */ + RH850_ISR_PRIORITY_1 = 1, /*!< Priority 1 */ + RH850_ISR_PRIORITY_2 = 2, /*!< Priority 2 */ + RH850_ISR_PRIORITY_3 = 3, /*!< Priority 3 */ + RH850_ISR_PRIORITY_4 = 4, /*!< Priority 4 */ + RH850_ISR_PRIORITY_5 = 5, /*!< Priority 5 */ + RH850_ISR_PRIORITY_6 = 6, /*!< Priority 6 */ + RH850_ISR_PRIORITY_7 = 7, /*!< Priority 7 */ + RH850_ISR_PRIORITY_8 = 8, /*!< Priority 8 */ + RH850_ISR_PRIORITY_9 = 9, /*!< Priority 9 */ + RH850_ISR_PRIORITY_10 = 10, /*!< Priority 10 */ + RH850_ISR_PRIORITY_11 = 11, /*!< Priority 11 */ + RH850_ISR_PRIORITY_12 = 12, /*!< Priority 12 */ + RH850_ISR_PRIORITY_13 = 13, /*!< Priority 13 */ + RH850_ISR_PRIORITY_14 = 14, /*!< Priority 14 */ + RH850_ISR_PRIORITY_15 = 15 /*!< Priority 15 (lowest) */ +} rh850_isr_priority_t; + +/** + * @enum rh850_imsr_bit_t + * @brief IMSR bit positions for RH850 mask status. + * + * This enumeration defines symbolic names for the IMSR bits so code can + * reference mask sources in a readable way. + * + * @note The values equal the bit indices of IMSR. + */ +typedef enum e_rh850_imsr_bit +{ + RH850_IMSR_BIT_EEIM = 0x01, /*!< EIINT masked by ISPR.ISP/PSW.EIMASK exists */ + RH850_IMSR_BIT_EPLM = 0x02, /*!< EINT masked by PLMR.PLM exists */ + RH850_IMSR_BIT_EID = 0x04, /*!< EINT masked by PSW.ID exists */ + RH850_IMSR_BIT_ENP = 0x08, /*!< EINT masked by PSW.NP exists */ + RH850_IMSR_BIT_FNP = 0x10 /*!< FEINT masked by PSW.NP exists */ +} rh850_imsr_bit_t; + +/** + * @enum rh850_intcfg_extended_priority_level_t + * @brief Interrupt Priority Level extension enable (EPL). + * + * 0: Priority level extension function is disabled + * 1: Priority level extension function is enabled + */ +typedef enum e_rh850_intcfg_extended_priority_level +{ + RH850_INTCFG_EXTENDED_PRIORITY_LEVEL_DISABLED = 0, /*!< Function disabled */ + RH850_INTCFG_EXTENDED_PRIORITY_LEVEL_ENABLED = 1 /*!< Function enabled */ +} rh850_intcfg_extended_priority_level_t; + +/** + * @enum rh850_intcfg_update_ispc_t + * @brief ISPR write control (ISPC). + * + * 0: ISPR is auto-updated. LDSR updates are ignored. + * 1: ISPR is not auto-updated. LDSR updates are performed (software priority control). + * + * @note In normal cases, ISPC should be cleared to 0. Set 1 only when software-based + * priority control is required. + */ +typedef enum e_rh850_intcfg_update_ispc +{ + RH850_INTCFG_UPDATE_ISPC_AUTO = 0, /*!< Auto-update ISPR; ignore LDSR writes */ + RH850_INTCFG_UPDATE_ISPC_PROGRAM = 1 /*!< Program-driven ISPR updates via LDSR */ +} rh850_intcfg_update_ispc_t; + +/** + * @enum rh850_imsr_eiint_eplm_mask_t + * @brief Represents the state of EIINTn priority masking by PLMR register. + * + * This enumeration defines whether an EIINTn interrupt whose acceptance is masked + * by PLMR.PLM exists. It maps to IMSR bit EPLM: + * - 0: EIINT masked by PLMR.PLM does not exist + * - 1: EIINT masked by PLMR.PLM exists + * + * @note For details, see Section, Interrupt Exception Priority and Priority Masking. + */ +typedef enum e_rh850_imsr_eiint_eplm_mask +{ + RH850_IMSR_EIINT_EPLM_MASK_DOES_NOT_EXIST = 0, /*!< EIINT masked by PLMR.PLM does not exist */ + RH850_IMSR_EIINT_EPLM_MASK_EXISTS = 1 /*!< EIINT masked by PLMR.PLM exists */ +} rh850_imsr_eiint_eplm_mask_t; + +/** + * @enum rh850_imsr_mask_t + * @brief Represents the state of an interrupt mask in IMSR. + * + * This enumeration defines whether a specific IMSR mask condition exists. + * Each IMSR bit uses these states: + * - 0: Mask does not exist + * - 1: Mask exists + */ +typedef enum e_rh850_imsr_mask +{ + RH850_IMSR_MASK_NOT_EXIST = 0, /*!< Mask does not exist (bit = 0U) */ + RH850_IMSR_MASK_EXISTS = 1 /*!< Mask exists (bit = 1) */ +} rh850_imsr_mask_t; + +/** + * @enum rh850_plmr_priority_mask_level_t + * @brief Priority mask level for EIINTn on RH850 (PLMR.PLM = 0..63). + * + * Masking rule: + * - PLM = 0: All priorities are not acceptable (priority 0..63). + * - PLM = N: Mask interrupts with priority <= N. + * - Priority 63: Always masked (priority 0..63). + * + * @note Enum values map directly to PLMR.PLM (0..63). + */ +typedef enum e_rh850_plmr_priority_mask_level +{ + RH850_PLMR_PRIORITY_MASK_LEVEL_0 = 0, /*!< All priorities are not acceptable */ + RH850_PLMR_PRIORITY_MASK_LEVEL_1 = 1, /*!< Acceptable of priority 0 only */ + RH850_PLMR_PRIORITY_MASK_LEVEL_2 = 2, /*!< Acceptable priority is 0 to 1 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_3 = 3, /*!< Acceptable priority is 0 to 2 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_4 = 4, /*!< Acceptable priority is 0 to 3 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_5 = 5, /*!< Acceptable priority is 0 to 4 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_6 = 6, /*!< Acceptable priority is 0 to 5 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_7 = 7, /*!< Acceptable priority is 0 to 6 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_8 = 8, /*!< Acceptable priority is 0 to 7 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_9 = 9, /*!< Acceptable priority is 0 to 8 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_10 = 10, /*!< Acceptable priority is 0 to 9 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_11 = 11, /*!< Acceptable priority is 0 to 10 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_12 = 12, /*!< Acceptable priority is 0 to 11 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_13 = 13, /*!< Acceptable priority is 0 to 12 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_14 = 14, /*!< Acceptable priority is 0 to 13 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_15 = 15, /*!< Acceptable priority is 0 to 14 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_16 = 16, /*!< Acceptable priority is 0 to 15 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_17 = 17, /*!< Acceptable priority is 0 to 16 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_18 = 18, /*!< Acceptable priority is 0 to 17 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_19 = 19, /*!< Acceptable priority is 0 to 18 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_20 = 20, /*!< Acceptable priority is 0 to 19 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_21 = 21, /*!< Acceptable priority is 0 to 20 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_22 = 22, /*!< Acceptable priority is 0 to 21 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_23 = 23, /*!< Acceptable priority is 0 to 22 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_24 = 24, /*!< Acceptable priority is 0 to 23 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_25 = 25, /*!< Acceptable priority is 0 to 24 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_26 = 26, /*!< Acceptable priority is 0 to 25 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_27 = 27, /*!< Acceptable priority is 0 to 26 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_28 = 28, /*!< Acceptable priority is 0 to 27 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_29 = 29, /*!< Acceptable priority is 0 to 28 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_30 = 30, /*!< Acceptable priority is 0 to 29 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_31 = 31, /*!< Acceptable priority is 0 to 30 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_32 = 32, /*!< Acceptable priority is 0 to 31 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_33 = 33, /*!< Acceptable priority is 0 to 32 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_34 = 34, /*!< Acceptable priority is 0 to 33 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_35 = 35, /*!< Acceptable priority is 0 to 34 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_36 = 36, /*!< Acceptable priority is 0 to 35 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_37 = 37, /*!< Acceptable priority is 0 to 36 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_38 = 38, /*!< Acceptable priority is 0 to 37 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_39 = 39, /*!< Acceptable priority is 0 to 38 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_40 = 40, /*!< Acceptable priority is 0 to 39 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_41 = 41, /*!< Acceptable priority is 0 to 40 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_42 = 42, /*!< Acceptable priority is 0 to 41 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_43 = 43, /*!< Acceptable priority is 0 to 42 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_44 = 44, /*!< Acceptable priority is 0 to 43 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_45 = 45, /*!< Acceptable priority is 0 to 44 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_46 = 46, /*!< Acceptable priority is 0 to 45 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_47 = 47, /*!< Acceptable priority is 0 to 46 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_48 = 48, /*!< Acceptable priority is 0 to 47 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_49 = 49, /*!< Acceptable priority is 0 to 48 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_50 = 50, /*!< Acceptable priority is 0 to 49 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_51 = 51, /*!< Acceptable priority is 0 to 50 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_52 = 52, /*!< Acceptable priority is 0 to 51 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_53 = 53, /*!< Acceptable priority is 0 to 52 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_54 = 54, /*!< Acceptable priority is 0 to 53 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_55 = 55, /*!< Acceptable priority is 0 to 54 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_56 = 56, /*!< Acceptable priority is 0 to 55 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_57 = 57, /*!< Acceptable priority is 0 to 56 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_58 = 58, /*!< Acceptable priority is 0 to 57 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_59 = 59, /*!< Acceptable priority is 0 to 58 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_60 = 60, /*!< Acceptable priority is 0 to 59 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_61 = 61, /*!< Acceptable priority is 0 to 60 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_62 = 62, /*!< Acceptable priority is 0 to 61 */ + RH850_PLMR_PRIORITY_MASK_LEVEL_63 = 63 /*!< Acceptable priority is 0 to 62 */ +} rh850_plmr_priority_mask_level_t; + +/** @} */ /* end of RH850_IRQ_Types */ + +/* ########################################### IRQ API Functions ################################################## */ + +/** + * @defgroup RH850_IRQ_API IRQ API Functions + * @ingroup RH850_IRQ + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* ########################################## IRQ System Register ################################################# */ + +/** + * @brief Get the highest-priority EI interrupt currently being serviced. + * + * This function reads the ISPR register and returns the highest priority level + * (lowest numeric value) that is currently active. + * + * @return rh850_isr_priority_t Priority level [0..15]. + */ + +__STATIC_INLINE rh850_isr_priority_t __RH850_IRQ_InterruptPriorityGet (void) +{ + return (rh850_isr_priority_t) (__get_ISPR() & R_IRQ_ISPR_ISP_Msk); +} + +/** + * @brief Get the current mask state for a specific IMSR bit (mask source). + * + * This function reads the CPU's **IMSR (Interrupt Mask Status Register)** and + * evaluates a particular bit (e.g., EEIM, EPLM, EID, ENP, FNP) specified by @p LenMaskBit. + * The return value indicates whether the corresponding mask condition **exists** (bit = 1) + * or **does not exist** (bit = 0U). + * + * @param[in] LenMaskBit + * Bit selector for IMSR (e.g., a mask with one of the IMSR bits set). + * Typical values correspond to the IMSR mask sources: + * - EEIM: EIINT masked by ISPR.ISP or PSW.EIMASK + * - EPLM: EINT masked by PLMR.PLM + * - EID : EINT masked by PSW.ID + * - ENP : EINT masked by PSW.NP + * - FNP : FEINT masked by PSW.NP + * + * @return rh850_imsr_mask_t + * - RH850_IMSR_MASK_NOT_EXIST (0U): no mask condition present for the selected bit + * - RH850_IMSR_MASK_EXISTS (1): mask condition present for the selected bit + */ +__STATIC_INLINE rh850_imsr_mask_t __RH850_IRQ_InterruptMaskStatusGet (rh850_imsr_bit_t LenMaskBit) +{ + return (rh850_imsr_mask_t) (__get_IMSR() & LenMaskBit); +} + +/** + * @brief Report whether any EIINT currently matches the PLMR-based mask condition (ICSR.PMEI status). + * + * This function reads the **ICSR (Interrupt Control Status Register)** and returns + * whether a masked EIINT (due to **PLMR.PLM**) **exists** according to the PMEI flag. + * + * @return rh850_imsr_eiint_eplm_mask_t + */ +__STATIC_INLINE rh850_imsr_eiint_eplm_mask_t __RH850_IRQ_InterruptControlStatusGet (void) +{ + return (rh850_imsr_eiint_eplm_mask_t) (__get_ICSR() & R_IRQ_ICSR_PMEI_Msk); +} + +/** + * @brief Get EPL bit (Interrupt priority level extension enable). + * @return rh850_intcfg_extended_priority_level_t Current EPL state. + */ +__STATIC_INLINE rh850_intcfg_extended_priority_level_t __RH850_IRQ_PriorityExtensionGet (void) +{ + return (rh850_intcfg_extended_priority_level_t) ((__get_INTCFG() & R_IRQ_INTCFG_EPL_Msk) >> R_IRQ_INTCFG_EPL_Pos); +} + +/** + * @brief Set EPL bit (enable/disable priority level extension). + * @param epl RH850_INTCFG_EXTENDED_PRIORITY_LEVEL_ENABLED or RH850_INTCFG_EXTENDED_PRIORITY_LEVEL_DISABLED. + * + * @details When enabled, device supports extended priority levels (e.g., up to 64), + * affecting ISPR/IMSR/ISPC interactions per manual (see priority mask sections). + */ +__STATIC_INLINE void __RH850_IRQ_PriorityExtensionSet (rh850_intcfg_extended_priority_level_t LenMode) +{ + uint32_t LulIntcfgRegVal; + + /* Read the INTCFG value */ + LulIntcfgRegVal = __get_INTCFG(); + LulIntcfgRegVal &= (~R_IRQ_INTCFG_EPL_Msk); + LulIntcfgRegVal |= ((uint8_t) LenMode << R_IRQ_INTCFG_EPL_Pos); + + /* Write back */ + (void) __set_INTCFG(LulIntcfgRegVal); +} + +/** + * @brief Get the current ISPR update mode. + * + * @return rh850_intcfg_update_ispc_t + * - RH850_INTCFG_UPDATE_ISPC_AUTO : ISPR auto-updated by hardware + * - RH850_INTCFG_UPDATE_ISPC_PROGRAM : ISPR updated by program (LDSR) + */ +__STATIC_INLINE rh850_intcfg_update_ispc_t __RH850_IRQ_IsprUpdateModeGet (void) +{ + return (rh850_intcfg_update_ispc_t) ((__get_INTCFG() & R_IRQ_INTCFG_ISPC_Msk) >> R_IRQ_INTCFG_ISPC_Pos); +} + +/** + * @brief Set the ISPR update mode. + * @param[in] LenMode RH850_INTCFG_UPDATE_ISPC_AUTO or RH850_INTCFG_UPDATE_ISPC_PROGRAM. + * @note Use AUTO (0U) for normal operation. Use PROGRAM (1) for software-based + * priority control where ISPR is updated via LDSR instruction. + */ +__STATIC_INLINE void __RH850_IRQ_IsprUpdateModeSet (rh850_intcfg_update_ispc_t LenMode) +{ + uint32_t LulIntcfgRegVal; + + /* Read the INTCFG value and mask for ISPC bit */ + LulIntcfgRegVal = __get_INTCFG(); + LulIntcfgRegVal &= (~R_IRQ_INTCFG_ISPC_Msk); + + /* Set mode */ + LulIntcfgRegVal |= (LenMode & R_IRQ_INTCFG_ISPC_Msk); + + /* Write back */ + __set_INTCFG(LulIntcfgRegVal); +} + +/** + * @brief Get the maximum allowed register bank number (ULNR). + * @return uint32_t ULNR value (0..63). Defines upper limit for register bank usage. + * @note If RBNR.BN > ULNR or equals 63, and EIINTn uses register bank, SYSERR occurs. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_RegisterBankLimitGet (void) +{ + return (uint32_t) ((__get_INTCFG() & R_IRQ_INTCFG_ULNR_Msk) >> R_IRQ_INTCFG_ULNR_Pos); +} + +/** + * @brief Set the maximum allowed register bank number (ULNR). + * @param LulLimit ULNR value (0..63). See device manual for valid range. + * @details ULNR prevents illegal register bank usage during EIINTn handling. + * Incorrect settings may cause SYSERR and interrupt rejection. + */ +__STATIC_INLINE void __RH850_IRQ_RegisterBankLimitSet (uint32_t LulLimit) +{ + uint32_t LulIntcfgRegVal; + + /* Read the INTCFG value */ + LulIntcfgRegVal = __get_INTCFG(); + LulIntcfgRegVal &= (~R_IRQ_INTCFG_ULNR_Pos); + + /* Set the limit */ + LulIntcfgRegVal |= (LulLimit << R_IRQ_INTCFG_ULNR_Pos) & R_IRQ_INTCFG_ULNR_Msk; + + /* Write back */ + __set_INTCFG(LulIntcfgRegVal); +} + +/** + * @brief Get the current PLMR mask level (PLM). + * @return rh850_plmr_priority_mask_level_t PLM value (0..63). + */ +__STATIC_INLINE rh850_plmr_priority_mask_level_t __RH850_IRQ_PriorityMaskLevelGet (void) +{ + return (rh850_plmr_priority_mask_level_t) (__get_PLMR() & R_IRQ_PLMR_PLM_Msk); +} + +/** + * @brief Set the PLMR mask level (PLM). + * @param level rh850_plmr_priority_mask_level_t (0..63). + * @details Masks all EIINTn with priority <= @p LenLevel. + * PLM=0 masks all; priority 63 is always masked. + */ +__STATIC_INLINE void __RH850_IRQ_PriorityMaskLevelSet (rh850_plmr_priority_mask_level_t LenLevel) +{ + (void) __set_PLMR((uint32_t) LenLevel); +} + +/** + * @brief Get Interrupt Mask + * @details Returns the current state of the interrupt mask bit from the Interrupt Mask Register. + * @return Interrupt Mask value + */ +__STATIC_INLINE uint32_t __RH850_IRQ_IntMaskGet (void) +{ + return (uint32_t) ((__get_PSW() & R_SYS_PSW_ID_Msk) >> R_SYS_PSW_ID_Pos); +} + +/** + * @brief Set Interrupt Mask + * @details Assigns the given value to the Interrupt Mask Register. + * @param [in] priMask Interrupt Mask + */ +__STATIC_INLINE void __RH850_IRQ_IntMaskSet (uint32_t priMask) +{ + if (priMask) + { + __disable_irq(); + } + else + { + __enable_irq(); + } +} + +/* ########################################## IRQ EEIC (INTC1/INTC2) Register ##################################### */ + +/** + * @brief Enable Interrupt + * @details Enables a device specific interrupt in the EIC interrupt controller. + * @param [in] IRQn Device specific interrupt number. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_EnableIRQ (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Clear mask bit */ + RH850_EEIC_INTC->EEIC_b.EIMK = 0U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Enable Interrupt by PEn + * @details Enables a device specific interrupt in the EIC interrupt controller for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_EnableIRQByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Clear mask bit */ + RH850_EEIC_INTC->EEIC_b.EIMK = 0U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Disable Interrupt + * @details Disable a device specific interrupt in the EIC interrupt controller. + * @param [in] IRQn Device specific interrupt number. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_DisableIRQ (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Set mask bit */ + RH850_EEIC_INTC->EEIC_b.EIMK = 1U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Disable Interrupt by PEn + * @details Disables a device specific interrupt in the EIC interrupt controller for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_DisableIRQByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Set mask bit */ + RH850_EEIC_INTC->EEIC_b.EIMK = 1U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Get Interrupt Enable status + * @details Returns a device specific interrupt enable status from the EIC interrupt controller. + * @param [in] IRQn Device specific interrupt number. + * \return 0 Interrupt is not enabled. + * \return 1 Interrupt is enabled. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetEnableIRQ (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + return !RH850_EEIC_INTC->EEIC_b.EIMK; +} + +/** + * @brief Get Interrupt Enable status by PEn + * @details Returns a device specific interrupt enable status from the EIC interrupt controller + * for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * \return 0 Interrupt is not enabled. + * \return 1 Interrupt is enabled. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetEnableIRQByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + return !RH850_EEIC_INTC->EEIC_b.EIMK; +} + +/** + * @brief Get Pending Interrupt + * @details Reads the EIC pending register and returns the pending bit for the specified device specific interrupt. + * @param [in] IRQn Device specific interrupt number. + * \return 0 Interrupt status is not pending. + * \return 1 Interrupt status is pending. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetPendingIRQ (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + return RH850_EEIC_INTC->EEIC_b.EIRF; +} + +/** + * @brief Get Pending Interrupt + * @details Reads the EIC pending register and returns the pending bit for the specified device specific interrupt + * for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * \return 0 Interrupt status is not pending. + * \return 1 Interrupt status is pending. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetPendingIRQByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + return RH850_EEIC_INTC->EEIC_b.EIRF; +} + +/** + * @brief Clear Pending Interrupt + * @details Clears the pending bit of a device specific interrupt in the EIC pending register. + * @param [in] IRQn Device specific interrupt number. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_ClearPendingIRQ (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Decttion of the edge */ + if (RH850_EEIC_INTC->EEIC_b.EICT == 0U) + { + /* Clear the pending interrupt flag */ + RH850_EEIC_INTC->EEIC_b.EIRF = 0U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); + } +} + +/** + * @brief Clear Pending Interrupt + * @details Clears the pending bit of a device specific interrupt in the EIC pending register + * for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * @note IRQn must not be negative. + */ +__STATIC_INLINE void __RH850_IRQ_ClearPendingIRQByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Decttion of the edge */ + if (RH850_EEIC_INTC->EEIC_b.EICT == 0U) + { + /* Clear the pending interrupt flag */ + RH850_EEIC_INTC->EEIC_b.EIRF = 0U; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); + } +} + +/** + * @brief Set Interrupt Priority + * @details Sets the priority of a device specific interrupt or a processor exception. + * The interrupt number can be positive to specify a device specific interrupt, + * or negative to specify a processor exception. + * @param [in] IRQn Interrupt number. + * @param [in] priority Priority to set. + * @note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __RH850_IRQ_SetPriority (uint32_t IRQn, uint32_t priority) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Set the interurpt priority */ + RH850_EEIC_INTC->EEIC_b.EIP = priority; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Set Interrupt Priority + * @details Sets the priority of a device specific interrupt or a processor exception. + * The interrupt number can be positive to specify a device specific interrupt, + * or negative to specify a processor exception for specific core ID (INTC1 Only). + * @param [in] IRQn Interrupt number (INTC1). + * @param [in] priority Priority to set. + * @param [in] CoreID PEID of the INTC1 interrupt. + * @note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __RH850_IRQ_SetPriorityByPE (uint8_t CoreID, uint32_t IRQn, uint32_t priority) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Set the interurpt priority */ + RH850_EEIC_INTC->EEIC_b.EIP = priority; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Get Interrupt Priority + * @details Reads the priority of a device specific interrupt or a processor exception. + * The interrupt number can be positive to specify a device specific interrupt, + * or negative to specify a processor exception. + * @param [in] IRQn Interrupt number. + * \return Interrupt Priority. + * Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_GetPriority (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Get the interurpt priority */ + return RH850_EEIC_INTC->EEIC_b.EIP; +} + +/** + * @brief Get Interrupt Priority + * @details Reads the priority of a device specific interrupt or a processor exception. + * The interrupt number can be positive to specify a device specific interrupt, + * or negative to specify a processor exception for specific core ID (INTC1 Only). + * @param [in] IRQn Interrupt number (INTC1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * \return Interrupt Priority. + * Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_GetPriorityByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Get the interurpt priority */ + return RH850_EEIC_INTC->EEIC_b.EIP; +} + +/** + * @brief Set the interrupt vector method + * @details Sets the interrupt vector method specific for RH850 processor. + * @param [in] IRQn Interrupt number. + * @param [in] vector_method Interrupt Vector Method (0: Direct Vector Method/ 1: Table Reference Method) + */ +__STATIC_INLINE void __RH850_IRQ_SetIRQMethod (uint32_t IRQn, uint32_t vector_method) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Set the interrupt vector method */ + RH850_EEIC_INTC->EEIC_b.EITB = vector_method; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Set the interrupt vector method + * @details Sets the interrupt vector method specific for RH850 processor for specific core ID (INTC1 Only). + * @param [in] IRQn Interrupt number (INCT1). + * @param [in] vector_method Interrupt Vector Method (0: Direct Vector Method/ 1: Table Reference Method) + * @param [in] CoreID PEID of the INTC1 interrupt. + */ +__STATIC_INLINE void __RH850_IRQ_SetIRQMethodByPE (uint8_t CoreID, uint32_t IRQn, uint32_t vector_method) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Set the interrupt vector method */ + RH850_EEIC_INTC->EEIC_b.EITB = vector_method; + + /* Dummy read & SYNCP */ + (void) RH850_EEIC_INTC->EEIC; + __SYNCP(); +} + +/** + * @brief Get the interrupt vector method + * @details Gets the interrupt vector method specific for RH850 processor. + * @param [in] IRQn Interrupt number. + * \return Interrupt Vector Method (0: Direct Vector Method/ 1: Table Reference Method) + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetIRQMethod (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + /* Return the interrupt vector method */ + return RH850_EEIC_INTC->EEIC_b.EITB; +} + +/** + * @brief Get the interrupt vector method + * @details Gets the interrupt vector method specific for RH850 processor for specific core ID (INTC1 Only). + * @param [in] IRQn Interrupt number (INCT1). + * @param [in] CoreID PEID of the INTC1 interrupt. + * \return Interrupt Vector Method (0: Direct Vector Method/ 1: Table Reference Method) + */ +__STATIC_INLINE uint8_t __RH850_IRQ_GetIRQMethodByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + /* Return the interrupt vector method */ + return RH850_EEIC_INTC->EEIC_b.EITB; +} + +/** + * @brief Get Active Interrupt + * @details Reads the active register in the EEIC and returns the active bit for the device specific interrupt. + * @param [in] IRQn Device specific interrupt number. + * @return 0 Interrupt status is not active. + * @return 1 Interrupt status is active. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_GetActive (uint32_t IRQn) +{ + uint8_t LucCoreID = (uint8_t) __get_PEID(); + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(LucCoreID, IRQn); + + return RH850_EEIC_INTC->EEIC_b.EIRF; +} + +/** + * @brief Get Active Interrupt + * @details Reads the active register in the EEIC and returns the active bit for the device specific interrupt. + * for specific core ID (INTC1 Only). + * @param [in] IRQn Device specific interrupt number (INTC1). + * @return 0 Interrupt status is not active. + * @return 1 Interrupt status is active. + * @note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_GetActiveByPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EEIC_Type * RH850_EEIC_INTC; + + /* Get the address of the specific EIC */ + RH850_EEIC_INTC = (volatile RH850_IRQ_EEIC_Type *) RH850_EEIC_ADDR(CoreID, IRQn); + + return RH850_EEIC_INTC->EEIC_b.EIRF; +} + +/** + * @brief Set the specify the interrupt bind (request) destination. + * @details Sets the specify the interrupt bind (request) destination. + * @param [in] IRQn Interrupt number. + * @param [in] CoreID The target PE for the interrupt to be bound. + */ +__STATIC_INLINE void __RH850_IRQ_SetIRQBoundToPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EIBD_INTC2_Type * RH850_EIBD_INTC; + + /* INTC2 */ + if ((int32_t) (IRQn) > 31U) + { + RH850_EIBD_INTC = + (volatile RH850_IRQ_EIBD_INTC2_Type *) (RH850_INTC2_BASE + 4U * IRQn + RH850_INTC2_EIBD_OFFSET); + + /* Specify the interrupt bind (request) destination */ + RH850_EIBD_INTC->EIBD_b.PEID = CoreID; + + /* Dummy read & SYNCP */ + (void) RH850_EIBD_INTC->EIBD; + __SYNCP(); + } +} + +/** + * @brief Get the specify the interrupt bind (request) destination. + * @details Gets the specify the interrupt bind (request) destination. + * @param [in] IRQn Interrupt number. + * \return The specify the interrupt bind (request) destination. + */ +__STATIC_INLINE uint32_t __RH850_IRQ_GetIRQBoundToPE (uint8_t CoreID, uint32_t IRQn) +{ + volatile RH850_IRQ_EIBD_INTC1_Type * RH850_EIBD_INTC1; + volatile RH850_IRQ_EIBD_INTC2_Type * RH850_EIBD_INTC2; + + /* INTC2 */ + if ((int32_t) (IRQn) <= 31U) + { + RH850_EIBD_INTC1 = (volatile RH850_IRQ_EIBD_INTC1_Type *) (RH850_INTC1_BASE + RH850_INTC1_EIBD_OFFSET + \ + CoreID * RH850_INTC1_OFFSET + 4U * IRQn); + + /* Return the specify the interrupt bind (request) destination */ + return RH850_EIBD_INTC1->EIBD_b.PEID; + } + else + { + RH850_EIBD_INTC2 = (volatile RH850_IRQ_EIBD_INTC2_Type *) (RH850_INTC2_BASE + RH850_INTC2_EIBD_OFFSET + \ + 4U * IRQn); + + /* Return the specify the interrupt bind (request) destination */ + return RH850_EIBD_INTC2->EIBD_b.PEID; + } +} + +/** @} */ /* end of RH850_IRQ_API */ + +#endif /* RH850_G4_IRQ_H */ + +/** @} */ /* end of RH850_IRQ */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ +#endif /* #if defined(__IRQ_PRESENT) && (__IRQ_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_mpu.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_mpu.h new file mode 100644 index 0000000000000000000000000000000000000000..1af47b208cbe52cbc014596d61e34a9be0077295 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_mpu.h @@ -0,0 +1,516 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_mpu.h + * @brief MPU operation functions for RH850 G4 + * @version V0.0.1 + * @date 01 Jan 2026 + **********************************************************************************************************************/ + +#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_MPU RH850 Memory protection (MPU) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief MPU API and data types + * @{ + */ + +#ifndef RH850_G4_MPU_H + #define RH850_G4_MPU_H + + #include + +/* ####################################### MPU Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_MPU_Types MPU Types and Enumerations + * @brief MPU Types and Enumerations + * @ingroup RH850_MPU + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* MPUID Index */ + #define RH850_MPU_MPID_0 (0U) + #define RH850_MPU_MPID_1 (1U) + #define RH850_MPU_MPID_2 (2U) + #define RH850_MPU_MPID_3 (3U) + #define RH850_MPU_MPID_4 (4U) + #define RH850_MPU_MPID_5 (5U) + #define RH850_MPU_MPID_6 (6U) + #define RH850_MPU_MPID_7 (7U) + + #define RH850_MPU_MPM_ENABLE (0x01) ///< Enable MPU + #define RH850_MPU_MPAT_REGION_ENABLE (0x80) ///< Enable specific region in MPU + + #define RH850_MPU_PRIV_MODE_ACCESS_ALL (RH850_MPU_SV_MODE_ACCESS_ENABLE) ///< Enable all accesses in Privilege mode + #define RH850_MPU_PRIV_MODE_RESTRICT_ACCESS (RH850_MPU_SV_MODE_ACCESS_RESTRICT) ///< Restrict access according to the SX, SW, and SR bits in SV mode + + #define RH850_MPU_MPAT_WMPID_VALUE(spid) (spid << (24)) + #define RH850_MPU_MPAT_RMPID_VALUE(spid) (spid << (16)) + #define RH850_MPU_MPAT_UR_EN (1U << 0) ///< Reading is enabled for user mode + #define RH850_MPU_MPAT_UW_EN (1U << 1) ///< Writing is enabled for user mode + #define RH850_MPU_MPAT_UX_EN (1U << 2) ///< Executing is enabled for user mode + #define RH850_MPU_MPAT_SR_EN (1U << 3) ///< Reading is enabled for supervisor mode + #define RH850_MPU_MPAT_SW_EN (1U << 4) ///< Writing is enabled for supervisor mode + #define RH850_MPU_MPAT_SX_EN (1U << 5) ///< Executing is enabled for supervisor mode + +/** Execution and reading by any SPID is enabled regardless of the settings MPIDn */ + #define RH850_MPU_MPAT_RG_EN (1U << 14) + +/** Writing by any SPID is enabled regardless of the settings MPIDn */ + #define RH850_MPU_MPAT_WG_EN (1U << 15) + + #define RH850_MPU_PERMISSION_ENABLE (1U) + #define RH850_MPU_PERMISSION_DISABLE (0U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @enum rh850_mpu_sv_mode_access_t + * @brief Controls access behavior in Supervisor (SV) mode when PSW.UM = 0. + * + * In SV mode, this bit determines whether memory accesses are unrestricted + * or restricted according to the MPAT register's protection bits (SX, SW, SR) + * for each protection area. + * + * - 0: Enable all accesses in SV mode (no restriction). + * - 1: Restrict access according to SX, SW, and SR bits in SV mode. + * + * @note This setting applies only when PSW.UM = 0 (SV mode). + */ + +typedef enum e_rh850_mpu_sv_mode_access +{ + RH850_MPU_SV_MODE_ACCESS_ENABLE = 0x00, /*!< Enable all accesses in SV mode (no restriction) */ + RH850_MPU_SV_MODE_ACCESS_RESTRICT = 0x02, /*!< Restrict access according to SX, SW, and SR bits in SV mode */ +} rh850_mpu_sv_mode_access_t; + +/** + * @enum rh850_mpu_state_t + * @brief MPU function control bit (RH850). + * + * This bit selects/indicates whether the Memory Protection Unit (MPU) is enabled. + * + * - 0: Disable + * - 1: Enable + */ +typedef enum e_rh850_mpu_state +{ + RH850_MPU_STATE_DISABLE = 0U, /*!< Disable MPU function */ + RH850_MPU_STATE_ENABLE = 1U /*!< Enable MPU function. */ +} rh850_mpu_state_t; + +/** Region definition data structure */ +typedef struct st_rh850_mpu_region +{ + const char * name; /*!< Region's name */ + uint32_t start_address; /*!< Region's start address */ + uint32_t size; /*!< Region's size */ + union + { + uint32_t attribute; /*!< Region's attribute */ + struct + { + uint32_t user_mode_permission : 3; /*!< User mode permission */ + uint32_t supervisor_mode_permission : 3; /*!< Supervisor mode permission */ + uint32_t : 1; /*!< Reserved bit */ + uint32_t region_enable : 1; /*!< Region enable */ + uint32_t : 6; /*!< Reserved bits */ + uint32_t rg_bit : 1; /*!< Bit indicates the execution and read permissions for any SPID */ + uint32_t wg_bit : 1; /*!< Bit indicates the write permissions for any SPID */ + uint32_t rmpid : 8; /*!< Indicates the execution and read permissions for the SPID specified in the MPIDn register */ + uint32_t wmpid : 8; /*!< Indicates the write for the SPID specified in the MPIDn register */ + } attribute_b; + } region_attr; + uint8_t no_of_region; /*!< Region's index in MPU */ +} rh850_mpu_region_t; + +/** MPU Memory checking status */ +typedef struct st_rh850_mpu_mem_status +{ + union + { + uint32_t status; + struct + { + uint32_t usr_rd_en : 1; /*!< User mode read permission */ + uint32_t usr_wr_en : 1; /*!< User mode write permission */ + uint32_t usr_exe_en : 1; /*!< User mode execute permission */ + uint32_t sup_rd_en : 1; /*!< Supervisor mode read permission */ + uint32_t sup_wr_en : 1; /*!< Supervisor mode write permission */ + uint32_t sup_exe_en : 1; /*!< Supervisor mode executepermission */ + uint32_t : 2; /*!< Reserved bits */ + uint32_t ov_bit : 1; /*!< Bit indicates the specified area includes 0000 0000H or 7FFF FFFFH */ + uint32_t : 23; /*!< Reserved bits */ + } status_b; + } mpu_status; +} rh850_mpu_mem_status_t; + +/** @} */ /* end of RH850_MPU_Types */ + +/* ############################################ MPU API Functions ################################################# */ + +/** + * @defgroup RH850_MPU_API MPU API Functions + * @brief MPU API Functions + * @ingroup RH850_MPU + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief Enable the MPU. + * @details Enables the Memory Protection Unit by setting the appropriate bits in the MPM register. + * @param[in] LenSvAccessControl Access type for Privileged mode. + */ +__STATIC_INLINE void __RH850_MPU_Enable (rh850_mpu_sv_mode_access_t LenSvAccessControl) +{ + /* Setting for SVP and enable for MPE bit */ + (void) __set_MPM(LenSvAccessControl | R_MPU_MPM_MPE_Msk); +} + +/** + * @brief Disable the MPU. + * @details Disables the Memory Protection Unit by clearing enable bits in the MPM register. + */ +__STATIC_INLINE void __RH850_MPU_Disable (void) +{ + uint32_t LulMpmRegValue; + + /* Read the MPM register */ + LulMpmRegValue = __get_MPM(); + LulMpmRegValue &= (~R_MPU_MPM_MPE_Msk); + + /* Write back */ + (void) __set_MPM(LulMpmRegValue); +} + +/** + * @brief Get the current MPU state. + * @return rh850_mpu_state_t Current MPU state (enabled or disabled). + */ +__STATIC_INLINE rh850_mpu_state_t __RH850_MPU_StateGet (void) +{ + return (rh850_mpu_state_t) (__get_MPM() & R_MPU_MPM_MPE_Msk); +} + +/** + * @brief Get the current MPU state in SV mode. + * @return rh850_mpu_sv_mode_access_t Current MPU state (enabled or disabled). + */ +__STATIC_INLINE rh850_mpu_sv_mode_access_t __RH850_MPU_SvStateGet (void) +{ + return (rh850_mpu_sv_mode_access_t) (__get_MPM() & R_MPU_MPM_SVP_Msk); +} + +/** + * @brief Get the total number of MPU regions supported for this core. + * @details Reads SR2,5 and calculates the number of supported MPU regions. + * @return Total number of MPU regions. + */ +__STATIC_INLINE uint8_t __RH850_MPU_NumberofRegionsGet (void) +{ + uint8_t LucNumOfRegions; + + /* Check if MPU is supported on MCU */ + if (__get_PID() & R_MPU_PID_MPU_Msk) + { + LucNumOfRegions = (__get_MPCFG() & R_MPU_MPCFG_NMPUE_Msk) + 1U; + } + else + { + LucNumOfRegions = 0U; + } + + return LucNumOfRegions; +} + +/** + * @brief Get the number of MPU banks configured in the CPU. + * @details Reads the NBK field from the MPU configuration register. The NBK field indicates + * "number of banks - 1" for the MPU. For example, if NBK = 0, the CPU has one MPU bank. + * + * @return uint32_t + * - Value representing (number of banks - 1). + * + * @note For this CPU, NBK typically reads as 0, meaning one MPU bank is present. + */ +__STATIC_INLINE uint8_t __RH850_MPU_NumberOfBanksGet (void) +{ + return (uint8_t) ((__get_MPCFG() & R_MPU_MPCFG_NBK_Msk) >> R_MPU_MPCFG_NBK_Pos); +} + +/** + * @brief Get the MPU architecture specification version. + * @details Reads the ARCH field from the MPU configuration register. This field indicates + * the version of the MPU architecture implemented by the CPU. + * + * @return uint32_t + * - Value representing the MPU architecture version (e.g., 2 for this CPU). + * + * @note The ARCH field is read-only and reflects the hardware MPU specification level. + */ +__STATIC_INLINE uint8_t __RH850_MPU_ArchitectureVersionGet (void) +{ + return (uint8_t) ((__get_MPCFG() & R_MPU_MPCFG_ARCH_Msk) >> R_MPU_MPCFG_ARCH_Pos); +} + +/** + * @brief Execute memory protection checking. + * @details Performs memory protection check using MCA, MCS, MCI, MCC, and returns result from MCR. + * @param[in] LulSpid System protection identifier. + * @param[in] LulLowerAddr Value for MCA register. + * @param[in] LulSize Size of region. + * @param[in] LpStatus Pointer to the variable that stores the status result. + * @return Result code masked to 0x1FF. + */ +__STATIC_INLINE void __RH850_MPU_ExecMemProtectCheck (uint8_t LulSpid, + uint32_t LulLowerAddr, + uint32_t LulSize, + rh850_mpu_mem_status_t * LpStatus) +{ + uint32_t LulDummyValue; + + LulDummyValue = 0; + + /* Set parameter LulLowerAddr to SR8, 5 MCA */ + __set_MCA(LulLowerAddr); + + /* Set parameter LulSize to SR9, 5 MCS */ + __set_MCS(LulSize); + + /* Set parameter LulSpid to SR12, 5 MCI */ + __set_MCI(LulSpid); + + /* Start checking with SR10, 5 MCC by writting for any value */ + __set_MCC(LulDummyValue); + + /* Get the results from SR11, 5 MCR */ + LpStatus->mpu_status.status = __get_MCR(); +} + +/** + * @brief Set the current Memory Protection entry index (MPIDX). + * @note This value dictates which entry will be addressed by the next + * MPLA/MPUA/MPAT access using LDSR/STSR. + */ +__STATIC_INLINE void __RH850_MPU_MpuIdSet (uint8_t LucRegion) +{ + (void) __set_MPIDX(LucRegion); +} + +/** + * @brief Get the currently selected MPU bank (MPBK). + * + * Returns the BK field indicating which MPU bank is currently used for memory protection, + * the memory protection setting check function, and the LDM.MP / STM.MP instructions. + * Registers of non-selected banks have no effect and cannot be operated via LDSR/STSR. + * + * @return The current BK value (typically 0 for MPU bank 0; other values are prohibited). + * + * @note The returned BK dictates which bank’s configuration is active for protection and + * for MP-related load/store instructions. + */ +__STATIC_INLINE uint8_t __RH850_MPU_BankGet (void) +{ + return (uint8_t) (__get_MPBK() & R_MPU_MPBK_BK_Msk); +} + +/** + * @brief Set the memory attribute encoding. + * @details Configures the attribute for a specific MPU region. + * @param[in] LucRegion The region number to be set [0-31]. + * @param[in] LulAttr The attribute value to be set. + */ +__STATIC_INLINE void __RH850_MPU_AttrSet (uint8_t LucRegion, uint32_t LulAttr) +{ + /* Set register SR16, 5 MPIDX to LucRegion value */ + __set_MPIDX(LucRegion); + + /* Set register SR22, 5 MPAT to LulAttr value */ + __set_MPAT(LulAttr); +} + +/** + * @brief Get the memory attribute encoding. + * @details Reads the attribute value for a specific MPU region. + * @param[in] LucRegion The region number to be set [0-31]. + * @return Attribute value of the region. + */ +__STATIC_INLINE uint32_t __RH850_MPU_AttrGet (uint8_t LucRegion) +{ + /* Set parameter LucRegion to register SR16, 5 MPIDX */ + __set_MPIDX(LucRegion); + + /* Get attribute */ + return (uint32_t) __get_MPAT(); +} + +/** + * @brief Clear and disable the given MPU region. + * @details Clears all registers for the specified region and disables it. + * @param[in] LucRegion Region number to be cleared. + */ +__STATIC_INLINE void __RH850_MPU_RegionClear (uint8_t LucRegion) +{ + /* Set parameter LucRegion to register SR16, 5 MPIDX */ + __set_MPIDX(LucRegion); + + /* Clear register SR20, 5 MPLA + * Clear register SR21, 5 MPUA + * Clear register SR22, 5 MPAT */ + __set_MPIDX(0); + __set_MPLA(0); + __set_MPAT(0); +} + +/** + * @brief Configure the given MPU region. + * @details Sets lower and upper address for the region based on size. + * @param[in] LucRegion Region number to be configured. + * @param[in] LulLowerAddr Value for MPLA register. + * @param[in] LulSize Size of region. + */ +__STATIC_INLINE void __RH850_MPU_RegionSet (uint8_t LucRegion, uint32_t LulLowerAddr, uint32_t LulSize) +{ + /* Set parameter LucRegion to register SR16, 5 MPIDX */ + __set_MPIDX(LucRegion); + + /* Set parameter LulLowerAddr to register SR20, 5 MPLA */ + __set_MPLA(LulLowerAddr); + + /* Set upper address to register SR21, 5 MPUA */ + __set_MPUA((uint32_t) (LulLowerAddr + LulSize)); +} + +/** + * @brief Get the lower address of specific region. + * @details Reads MPLA register for the given region. + * @param[in] LucRegion The region number to be set [0-31]. + * @return Lower address of the region. + */ +__STATIC_INLINE uint32_t __RH850_MPU_LowerAddressGet (uint8_t LucRegion) +{ + /* Set parameter LucRegion to register SR16, 5 MPIDX */ + __set_MPIDX(LucRegion); + + /* Get value of SR20, 5 MPLA */ + return (uint32_t) __get_MPLA(); +} + +/** + * @brief Get the upper address of specific region. + * @details Reads MPUA register for the given region. + * @param[in] LucRegion The region number to be set [0-31]. + * @return Upper address of the region. + */ +__STATIC_INLINE uint32_t __RH850_MPU_UpperAddressGet (uint8_t LucRegion) +{ + /* Set parameter LucRegion to register SR16, 5 MPIDX */ + __set_MPIDX(LucRegion); + + /* Get value of SR21, 5 MPUA */ + return (uint32_t) __get_MPUA(); +} + +/** This function sets value for MPIDx register (x = 0 to 7). + * @param LucMpid No of MPID register. + * @param LucValue Value for MPID register. + */ +__STATIC_INLINE void __RH850_MPU_MpidSet (uint8_t LucMpid, uint8_t LucValue) +{ + /* No of MPID register */ + switch (LucMpid) + { + case RH850_MPU_MPID_0: + { + /* Load r7 into MPID0 (SR24, select = 5) */ + __set_MPID0(LucValue); + break; + } + + case RH850_MPU_MPID_1: + { + /* Load r7 into MPID1 (SR25, select = 5) */ + __set_MPID1(LucValue); + break; + } + + case RH850_MPU_MPID_2: + { + /* Load r7 into MPID2 (SR26, select = 5) */ + __set_MPID2(LucValue); + break; + } + + case RH850_MPU_MPID_3: + { + /* Load r7 into MPID3 (SR27, select = 5) */ + __set_MPID3(LucValue); + break; + } + + case RH850_MPU_MPID_4: + { + /* Load r7 into MPID4 (SR28, select = 5) */ + __set_MPID4(LucValue); + break; + } + + case RH850_MPU_MPID_5: + { + /* Load r7 into MPID5 (SR29, select = 5) */ + __set_MPID5(LucValue); + break; + } + + case RH850_MPU_MPID_6: + { + /* Load r7 into MPID6 (SR30, select = 5) */ + __set_MPID6(LucValue); + break; + } + + case RH850_MPU_MPID_7: + { + /* Load r7 into MPID7 (SR31, select = 5) */ + __set_MPID7(LucValue); + break; + } + + default: + { + break; + } + } + + /* Synchronization barrier to ensure system register write completes */ + __SYNCP(); +} + +/** @} */ /* end of RH850_MPU_API */ + +#endif /* RH850_G4_MPU_H */ + +/** @} */ /* end of RH850_MPU */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ +#endif /* #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_pmu.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_pmu.h new file mode 100644 index 0000000000000000000000000000000000000000..91b328f96a3855b06a5a83903121525767a0410d --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_pmu.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_pmu.h + * @brief Performance Measurement Function + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_PMU RH850 Performance Measurement Unit (PMU) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850 PMU API and types + * @{ + */ + +#ifndef RH850_G4_PMU_H + #define RH850_G4_PMU_H + + #include + +/* ####################################### PMU Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_PMU_Types PMU Types and Enumerations + * @brief PMU Types and Enumerations + * @ingroup RH850_PMU + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #define RH850_PMU_COUNT_CHANNEL_0 0U /*!< Performance count channel 0 */ + #define RH850_PMU_COUNT_CHANNEL_1 1U /*!< Performance count channel 1 */ + #define RH850_PMU_COUNT_CHANNEL_2 2U /*!< Performance count channel 2 */ + #define RH850_PMU_COUNT_CHANNEL_3 3U /*!< Performance count channel 3 */ + #define RH850_PMU_COUNT_CHANNEL_4 4U /*!< Performance count channel 4 */ + #define RH850_PMU_COUNT_CHANNEL_5 5U /*!< Performance count channel 5 */ + #define RH850_PMU_COUNT_CHANNEL_6 6U /*!< Performance count channel 6 */ + #define RH850_PMU_COUNT_CHANNEL_7 7U /*!< Performance count channel 7 */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @brief User-mode access control for PMU channel. + */ +typedef enum e_rh850_pmu_user_mode_access +{ + RH850_PMU_USER_MODE_ACCESS_DISABLE = 0, /*!< Disable user-mode access */ + RH850_PMU_USER_MODE_ACCESS_ENABLE = 1 /*!< Enable user-mode access */ +} rh850_pmu_user_mode_access_t; + +/** + * @brief PMU event selector. + */ +typedef enum e_rh850_pmu_number_of_event +{ + RH850_PMU_NUMBER_OF_EVENT_ALL_CLOCK_CYCLES = 0x00U, /*!< PMU event: All clock cycles */ + RH850_PMU_NUMBER_OF_EVENT_ALL_INSTRUCTIONS = 0x10U, /*!< PMU event: All instructions */ + RH850_PMU_NUMBER_OF_EVENT_BRANCH_INSTRUCTIONS = 0x18U, /*!< PMU event: Branch instructions */ + RH850_PMU_NUMBER_OF_EVENT_CONDITIONAL_BRANCH_EXECUTIONS = 0x19U, /*!< PMU event: Conditional branch executions */ + RH850_PMU_NUMBER_OF_EVENT_BRANCH_PREDICTION_MISSES = 0x1AU, /*!< PMU event: Branch prediction misses */ + RH850_PMU_NUMBER_OF_EVENT_EIINT_ACCEPTANCES = 0x20U, /*!< PMU event: EIINT acceptances */ + RH850_PMU_NUMBER_OF_EVENT_FEINT_ACCEPTANCES = 0x21U, /*!< PMU event: FEINT acceptances */ + RH850_PMU_NUMBER_OF_EVENT_TERMINATING_EXCEPTION_ACCEPTANCES = 0x22U, /*!< PMU event: Terminating exception acceptances */ + RH850_PMU_NUMBER_OF_EVENT_RESUMABLE_EXCEPTION_ACCEPTANCES = 0x23U, /*!< PMU event: Resumable exception acceptances */ + RH850_PMU_NUMBER_OF_EVENT_NO_INTERRUPT_CLOCK_CYCLES = 0x28U, /*!< PMU event: No interrupt clock cycles */ + RH850_PMU_NUMBER_OF_EVENT_NO_INTERRUPT_AND_DISABLED_CYCLES = 0x29U, /*!< PMU event: No interrupt and disabled cycles */ + RH850_PMU_NUMBER_OF_EVENT_INSTRUCTION_FETCH_REQUESTS = 0x30U, /*!< PMU event: Instruction fetch requests */ + RH850_PMU_NUMBER_OF_EVENT_INSTRUCTION_CACHE_HITS = 0x31U, /*!< PMU event: Instruction cache hits */ + RH850_PMU_NUMBER_OF_EVENT_STALL_CYCLES = 0x40U, /*!< PMU event: Stall cycles */ + RH850_PMU_NUMBER_OF_EVENT_FLASH_FETCH_REQUESTS = 0x50U, /*!< PMU event: Flash fetch requests */ + RH850_PMU_NUMBER_OF_EVENT_FLASH_DATA_READ_REQUESTS = 0x51U /*!< PMU event: Flash data read requests */ +} rh850_pmu_number_of_event_t; + +/** + * @brief Channel operation state. + */ +typedef enum e_rh850_channel_operaiton_state +{ + RH850_CHANNEL_OPERATION_STATE_DISABLE = 0, /*!< Channel disabled */ + RH850_CHANNEL_OPERATION_STATE_ENABLE = 1 /*!< Channel enabled */ +} rh850_channel_operaiton_state_t; + +/** @} */ /* end of RH850_PMU_Types */ + +/* ########################################### PMU API Functions ################################################## */ + +/** + * @defgroup RH850_PMU_API PMU API Functions + * @brief PMU API Functions + * @ingroup RH850_PMU + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* ########################################## PMU Function Access ################################################# */ + +/** + * @brief Read PMCTRL register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint32_t Raw PMCTRLn value of the selected channel. + * @note Valid range for @p channel is implementation-defined (typically 0..7). + */ +__STATIC_INLINE uint32_t __get_PMCTRL (uint8_t LucChannel) +{ + uint32_t LulReturnValue = 0; + + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + LulReturnValue = __get_PMCTRL0(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + LulReturnValue = __get_PMCTRL1(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + LulReturnValue = __get_PMCTRL2(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + LulReturnValue = __get_PMCTRL3(); + break; + } + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + case (RH850_PMU_COUNT_CHANNEL_4): + { + LulReturnValue = __get_PMCTRL4(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + LulReturnValue = __get_PMCTRL5(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + LulReturnValue = __get_PMCTRL6(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + LulReturnValue = __get_PMCTRL7(); + break; + } + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + + default: + { + break; + } + } + + /* Return value */ + return LulReturnValue; +} + +/** + * @brief Write PMCTRL register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LulValue Value to write into PMCTRLn. + * @return void + */ +__STATIC_INLINE void __set_PMCTRL (uint8_t LucChannel, uint32_t LulValue) +{ + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + (void) __set_PMCTRL0(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + (void) __set_PMCTRL1(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + (void) __set_PMCTRL2(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + (void) __set_PMCTRL3(LulValue); + break; + } + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + case (RH850_PMU_COUNT_CHANNEL_4): + { + (void) __set_PMCTRL4(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + (void) __set_PMCTRL5(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + (void) __set_PMCTRL6(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + (void) __set_PMCTRL7(LulValue); + break; + } + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + + default: + { + break; + } + } +} + +/** + * @brief Write PMCOUNT register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LulValue Initial count to load into PMCOUNTn. + * @return void + */ +__STATIC_INLINE void __set_PMCOUNT (uint8_t LucChannel, uint32_t LulValue) +{ + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + (void) __set_PMCOUNT0(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + (void) __set_PMCOUNT1(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + (void) __set_PMCOUNT2(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + (void) __set_PMCOUNT3(LulValue); + break; + } + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + case (RH850_PMU_COUNT_CHANNEL_4): + { + (void) __set_PMCOUNT4(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + (void) __set_PMCOUNT5(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + (void) __set_PMCOUNT6(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + (void) __set_PMCOUNT7(LulValue); + break; + } + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + + default: + { + break; + } + } +} + +/** + * @brief Read PMCOUNT register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint32_t Current PMCOUNTn value. + */ +__STATIC_INLINE uint32_t __get_PMCOUNT (uint8_t LucChannel) +{ + uint32_t LulReturnValue = 0; + + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + LulReturnValue = __get_PMCOUNT0(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + LulReturnValue = __get_PMCOUNT1(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + LulReturnValue = __get_PMCOUNT2(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + LulReturnValue = __get_PMCOUNT3(); + break; + } + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + case (RH850_PMU_COUNT_CHANNEL_4): + { + LulReturnValue = __get_PMCOUNT4(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + LulReturnValue = __get_PMCOUNT5(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + LulReturnValue = __get_PMCOUNT6(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + LulReturnValue = __get_PMCOUNT7(); + break; + } + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + + default: + { + break; + } + } + + /* Return value */ + return LulReturnValue; +} + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Read PMSUBCND register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint32_t Raw PMSUBCNDn value. + * @details Reads PMSUBCNDn (SRn, bank 15). The meaning of SUBCND depends on PMCTRLn.CND. + */ +__STATIC_INLINE uint32_t __get_PMSUBCND (uint8_t LucChannel) +{ + uint32_t LulReturnValue = 0; + + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + LulReturnValue = __get_PMSUBCND0(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + LulReturnValue = __get_PMSUBCND1(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + LulReturnValue = __get_PMSUBCND2(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + LulReturnValue = __get_PMSUBCND3(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_4): + { + LulReturnValue = __get_PMSUBCND4(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + LulReturnValue = __get_PMSUBCND5(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + LulReturnValue = __get_PMSUBCND6(); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + LulReturnValue = __get_PMSUBCND7(); + break; + } + + default: + { + break; + } + } + + /* Return value */ + return LulReturnValue; +} + + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + + #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Write PMSUBCND register of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LulValue SUBCND value to program. + * @return void + * @details Writes PMSUBCNDn (SRn, bank 15). Only effective for event numbers that + * define a sub-condition; otherwise the value has no effect on counting. + */ +__STATIC_INLINE void __set_PMSUBCND (uint8_t LucChannel, uint32_t LulValue) +{ + /* PMU channel index */ + switch (LucChannel) + { + case (RH850_PMU_COUNT_CHANNEL_0): + { + (void) __set_PMSUBCND0(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_1): + { + (void) __set_PMSUBCND1(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_2): + { + (void) __set_PMSUBCND2(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_3): + { + (void) __set_PMSUBCND3(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_4): + { + (void) __set_PMSUBCND4(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_5): + { + (void) __set_PMSUBCND5(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_6): + { + (void) __set_PMSUBCND6(LulValue); + break; + } + + case (RH850_PMU_COUNT_CHANNEL_7): + { + (void) __set_PMSUBCND7(LulValue); + break; + } + + default: + { + break; + } + } +} + + #endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Enable counting (CEN=1) for a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return void + * @details Sets PMCTRLn.CEN to 1. + */ +__STATIC_INLINE void __RH850_PMU_ChannelEnable (uint8_t LucChannel) +{ + uint32_t LulPmctrlRegValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Set CEN value to 1 */ + LulPmctrlRegValue |= (R_PMU_PMCTRL0_CEN_Msk); + + /* Write back updated PMCTRL */ + __set_PMCTRL(LucChannel, LulPmctrlRegValue); +} + +/** + * @brief Disable counting (CEN=0) for a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return void + * @details Clears PMCTRLn.CEN. + */ +__STATIC_INLINE void __RH850_PMU_ChannelDisable (uint8_t LucChannel) +{ + uint32_t LulPmctrlRegValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Set CEN value to 0 */ + LulPmctrlRegValue &= (~R_PMU_PMCTRL0_CEN_Msk); + + /* Write back updated PMCTRL */ + __set_PMCTRL(LucChannel, LulPmctrlRegValue); +} + +/** + * @brief Enable or disable user-mode access for a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LenMode RH850_PMU_USER_MODE_ACCESS_DISABLE/ENABLE. + * @return void + * @details Performs read–modify–write on PMUMCTRL to set/clear PMUE[channel]. + */ +__STATIC_INLINE void __RH850_PMU_ModeSet (uint8_t LucChannel, rh850_pmu_user_mode_access_t LenMode) +{ + uint32_t LulPmumctrlRegValue; + + /* Read current PMUMCTRL value for the channel */ + LulPmumctrlRegValue = __get_PMUMCTRL(); + + /* Clear the PMUE[0:7] field before setting new value */ + LulPmumctrlRegValue &= (~R_PMU_PMUMCTRL_PMUE_Msk); + + /* Set new PMUE[0:7] value */ + LulPmumctrlRegValue |= (((uint32_t) LenMode << LucChannel) & R_PMU_PMUMCTRL_PMUE_Msk); + + /* Write back updated PMUMCTRL */ + __set_PMUMCTRL(LulPmumctrlRegValue); +} + +/** + * @brief Set event number (CND) for a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LenCndBits Event selector (see rh850_pmu_number_of_event_t). + * @return void + * @details Updates PMCTRLn.CND. + */ +__STATIC_INLINE void __RH850_PMU_ControlSet (uint8_t LucChannel, rh850_pmu_number_of_event_t LenCndBits) +{ + uint32_t LulPmctrlRegValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Clear the CND field before setting new value */ + LulPmctrlRegValue &= (~R_PMU_PMCTRL0_CND_Msk); + + /* Set new CND value */ + LulPmctrlRegValue |= (((uint32_t) LenCndBits << R_PMU_PMCTRL0_CND_Pos) & R_PMU_PMCTRL0_CND_Msk); + + /* Write back updated PMCTRL */ + __set_PMCTRL(LucChannel, LulPmctrlRegValue); +} + +/** + * @brief Get enable state (CEN) of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @details Reads PMCTRLn and extracts the CEN bit. + * @return RH850_CHANNEL_OPERATION_STATE_DISABLE/RH850_CHANNEL_OPERATION_STATE_ENABLE + * (CEN=0 - counting disabled/ CEN=1 (counting enabled)). + */ +__STATIC_INLINE rh850_channel_operaiton_state_t __RH850_PMU_StatusGet (uint8_t LucChannel) +{ + uint32_t LulPmctrlRegValue; + rh850_channel_operaiton_state_t LulReturnValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Get CEN value */ + LulReturnValue = + (rh850_channel_operaiton_state_t) ((LulPmctrlRegValue & R_PMU_PMCTRL0_CEN_Msk) >> R_PMU_PMCTRL0_CEN_Pos); + + /* Return the value of CEN bit */ + return LulReturnValue; +} + +/** + * @brief Read overflow flag (OVF) of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint8_t 1 if overflow occurred; 0 otherwise. + * @details Extracts PMCTRLn.OVF. Hardware sets OVF when PMCOUNTn wraps from 0xFFFF_FFFF to 0. + */ +__STATIC_INLINE uint8_t __RH850_PMU_OverflowGet (uint8_t LucChannel) +{ + uint32_t LulPmctrlRegValue; + uint8_t LulReturnValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Get OVF value */ + LulReturnValue = (uint8_t) ((LulPmctrlRegValue & R_PMU_PMCTRL0_OVF_Msk) >> R_PMU_PMCTRL0_OVF_Pos); + + /* Return the value of OVF bit */ + return LulReturnValue; +} + +/** + * @brief Clear overflow flag (OVF) of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return void + * @details Clears PMCTRLn.OVF by writing 0 to the bit using read–modify–write. + */ +__STATIC_INLINE void __RH850_PMU_OverflowClear (uint8_t LucChannel) +{ + uint32_t LulPmctrlRegValue; + + /* Read current PMCTRL value for the channel */ + LulPmctrlRegValue = __get_PMCTRL(LucChannel); + + /* Clear OVF bit */ + LulPmctrlRegValue &= (~R_PMU_PMCTRL0_OVF_Msk); + + /* Write back updated PMCTRL */ + __set_PMCTRL(LucChannel, LulPmctrlRegValue); +} + +/** + * @brief Set the PMCOUNT of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LulCount Initial count value to write. + * @return void + * @details Writes PMCOUNTn. The counter can be primed before enabling counting. + */ +__STATIC_INLINE void __RH850_PMU_CounterSet (uint8_t LucChannel, uint32_t LulCount) +{ + /* Write back updated PMCOUNT */ + __set_PMCOUNT(LucChannel, LulCount); +} + +/** + * @brief Get the PMCOUNT of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint32_t Current PMCOUNTn value. + * @details Reads PMCOUNTn irrespective of CEN state. + */ +__STATIC_INLINE uint32_t __RH850_PMU_CounterGet (uint8_t LucChannel) +{ + /* Return the value of PMCOUNT */ + return __get_PMCOUNT(LucChannel); +} + +/** + * @brief Set the PMSUBCND of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @param[in] LulCount SUBCND value to write. + * @return void + * @details Programs PMSUBCNDn. + */ +__STATIC_INLINE void __RH850_PMU_SubCountSet (uint8_t LucChannel, uint32_t LulCount) +{ + /* Write back updated PMCOUNT */ + (void) __set_PMSUBCND(LucChannel, LulCount); +} + +/** + * @brief Get the PMSUBCND of a PMU channel. + * @param[in] LucChannel PMU channel index (0..7). + * @return uint32_t Current PMSUBCNDn value. + * @details Reads PMSUBCNDn. + */ +__STATIC_INLINE uint32_t __RH850_PMU_SubCountGet (uint8_t LucChannel) +{ + /* Return the value of PMSUBCND */ + return __get_PMSUBCND(LucChannel); +} + +/** @} */ /* end of RH850_PMU_API */ + +#endif /* #ifndef RH850_G4_PMU_H */ + +/** @} */ /* end of RH850_PMU */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ +#endif /* #if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_tsc.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_tsc.h new file mode 100644 index 0000000000000000000000000000000000000000..df142d5a87b4bba0ad2758efdf1df1a44b192376 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_g4_tsc.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_g4_tsc.h + * @brief RH850 Time-Stamp Counter (TSC) control + * @version V0.0.1 + * @date 01 Jan 2026 + **********************************************************************************************************************/ + +#if defined(__TSC_PRESENT) && (__TSC_PRESENT == 1U) + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** + * @defgroup RH850_TSC RH850 Time-Stamp Counter (TSC) + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief TSC API and data types + * @{ + */ + +#ifndef RH850_G4_TSC_H + #define RH850_G4_TSC_H + + #include + +/* ####################################### TSC Types and Enumerations ############################################# */ + +/** + * @defgroup RH850_TSC_Types TSC Types and Enumerations + * @brief TSC Types and Enumerations + * @ingroup RH850_TSC + * @{ + */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** + * @brief TSC enable state. + */ +typedef enum e_rh850_tsc_enable +{ + RH850_TSC_ENABLE_OFF = 0x0U, /*!< Counter is disabled */ + RH850_TSC_ENABLE_ON = 0x1U /*!< Counter is enabled */ +} rh850_tsc_enable_t; + +/** @} */ /* end of RH850_TSC_Types */ + +/* ########################################### TSC API Functions ################################################## */ + +/** + * @defgroup RH850_TSC_API TSC API Functions + * @brief TSC API Functions + * @ingroup RH850_TSC + * @{ + */ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** + * @brief Enable the TSC counter (set TSCTRL.CEN). + */ +__STATIC_INLINE void __RH850_TSC_Enable (void) +{ + uint32_t LulTsctrlRegValue; + + /* Read current control register */ + LulTsctrlRegValue = __get_TSCTRL(); + + /* Set CEN bit to enable counting */ + LulTsctrlRegValue |= R_TSC_TSCTRL_CEN_Msk; + + /* Write back updated control value */ + __set_TSCTRL(LulTsctrlRegValue); +} + +/** + * @brief Disable the TSC counter (clear TSCTRL.CEN). + */ +__STATIC_INLINE void __RH850_TSC_Disable (void) +{ + uint32_t LulTsctrlRegValue; + + /* Read current control register */ + LulTsctrlRegValue = __get_TSCTRL(); + + /* Clear CEN bit to disable counting */ + LulTsctrlRegValue &= (~R_TSC_TSCTRL_CEN_Msk); + + /* Write back updated control value */ + __set_TSCTRL(LulTsctrlRegValue); +} + +/** + * @brief Clear the TSC overflow flag (clear TSCTRL.OVF). + */ +__STATIC_INLINE void __RH850_TSC_OverflowClear (void) +{ + uint32_t LulTsctrlRegValue; + + /* Read current control register */ + LulTsctrlRegValue = __get_TSCTRL(); + + /* Clear OVF status bit */ + LulTsctrlRegValue &= (~R_TSC_TSCTRL_OVF_Msk); + + /* Write back updated control value */ + __set_TSCTRL(LulTsctrlRegValue); +} + +/** + * @brief Read overflow flag (OVF) of a TSC channel. + * @return uint8_t 1 if overflow occurred; 0 otherwise. + */ +__STATIC_INLINE uint8_t __RH850_TSC_OverflowGet (void) +{ + uint32_t LulTsctrlRegValue; + uint8_t LulReturnValue; + + /* Read current control register */ + LulTsctrlRegValue = __get_TSCTRL(); + + /* Clear OVF status bit */ + LulReturnValue = (uint8_t) ((LulTsctrlRegValue & R_TSC_TSCTRL_OVF_Msk) >> R_TSC_TSCTRL_OVF_Pos); + + /* Return the value of OVF bit */ + return LulReturnValue; +} + +/** + * @brief Get the current enable state of the TSC (Get the current state of TSCTRL.CEN). + * @details + * Returns an enumerated state based on the CEN bit. + * @return RH850_TSC_ENABLE_ON/RH850_TSC_ENABLE_OFF if enabled/disabled + */ +__STATIC_INLINE rh850_tsc_enable_t __RH850_TSC_EnableGet (void) +{ + /* Extract CEN bit, translate into enumeration */ + return (__get_TSCTRL() & R_TSC_TSCTRL_CEN_Msk) ? RH850_TSC_ENABLE_ON : RH850_TSC_ENABLE_OFF; +} + +/** + * @brief Read the upper 32 bits of the TSC (Read the TSCTRLH's register). + * @details + * Returns the high word of the 64-bit counter. + * @return Upper 32 bits of the counter. + */ +__STATIC_INLINE uint32_t __RH850_TSC_CounterHighGet (void) +{ + /* Read of the high word */ + return (uint32_t) __get_TSCOUNTH(); +} + +/** + * @brief Read the lower 32 bits of the TSC (Read TSCTRLL's register). + * @details + * Returns the LulLowValue word of the 64-bit counter. + * @return Lower 32 bits of the counter. + */ +__STATIC_INLINE uint32_t __RH850_TSC_CounterLowGet (void) +{ + /* Read of the LulLowValue word */ + return (uint32_t) __get_TSCOUNTL(); +} + +/** + * @brief Read the TSC control register (Read the TSCTRL's regsiter). + * @details + * Provides raw access to the control/status register. + * @return Value of the TSCTRL register. + */ +__STATIC_INLINE uint32_t __RH850_TSC_ControlRead (void) +{ + /* Return current TSCTRL register value */ + return (uint32_t) __get_TSCTRL(); +} + +/** + * @brief Write the upper 32 bits of the TSC (Write to the TSCTRLH's regitser). + * @details + * Programs the high word of the counter. + * @param LulValue Value to write. + */ +__STATIC_INLINE void __RH850_TSC_CounterHighSet (uint32_t LulValue) +{ + /* Program high word of the counter */ + (void) __set_TSCOUNTH(LulValue); +} + +/** + * @brief Write the lower 32 bits of the TSC (Write to the TSCTRLL's register). + * @details + * Programs the LulLowValue word of the counter. + * @param LulValue Value to write. + */ +__STATIC_INLINE void __RH850_TSC_CounterLowSet (uint32_t LulValue) +{ + /* Program LulLowValue word of the counter */ + (void) __set_TSCOUNTL(LulValue); +} + +/** + * @brief Write the TSC control register (write to the TSCTRL's register). + * @details + * Writes the raw control value to TSCTRL. + * @param LulValue Value to write to TSCTRL. + */ +__STATIC_INLINE void __RH850_TSC_ControlSet (uint32_t LulValue) +{ + /* Write of control/status register */ + (void) __set_TSCTRL(LulValue); +} + +/** + * @brief Read the full 64-bit TSC value in a stable way. + * @details + * Implements the high–low–high read scheme: + * 1) Read high (H1), + * 2) Read LulLowValue (L), + * 3) Read high (H2). + * If H1 != H2, the LulLowValue value is re-read implicitly by the loop to avoid tearing + * across rollover. This yields a coherent 64-bit counter value. + * @return 64-bit TSC value. + */ +__STATIC_INLINE uint64_t __RH850_TSC_CounterFullGet (void) +{ + /* Perform a coherent 64-bit read */ + uint32_t LulHigh1Value, LulLowValue, LulHigh2Value; + do + { + LulHigh1Value = __get_TSCOUNTH(); /* first high read */ + LulLowValue = __get_TSCOUNTL(); /* LulLowValue read */ + LulHigh2Value = __get_TSCOUNTH(); /* second high read */ + } while (LulHigh1Value != LulHigh2Value); /* retry if rollover occurred between reads */ + + /* Compose 64-bit value from stable high and LulLowValue parts */ + return ((uint64_t) LulHigh2Value << 32) | (uint64_t) LulLowValue; +} + +/** @} */ /* end of RH850_TSC_API */ + +#endif /* RH850_G4_TSC_H */ + +/** @} */ /* end of RH850_TSC */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ + +#endif /* #if defined(__TSC_PRESENT) && (__TSC_PRESENT == 1U) */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ghs_g4.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ghs_g4.h new file mode 100644 index 0000000000000000000000000000000000000000..7a04ea10218d72cc4a1982b7ebd3d6d2e277c514 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_ghs_g4.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_ghs_g4.h + * @brief RH850 G4 GHS function + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_GHS_G4_H +#define __RH850_GHS_G4_H + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** @defgroup RH850_Core_AtomicFunctions RH850-Core Atomic Access Functions + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850-Core Atomic Access Functions + * @{ + */ + +/** @defgroup GHS_RH850_Core_AtomicFunctions GHS RH850-Core Atomic Access Functions + * @brief GHS RH850-Core Atomic Access Functions + * @ingroup RH850_Core_AtomicFunctions + * @{ + */ + +/* ######################################## Atomic Function Access ################################################ */ + +/** + * @brief Release a spinlock + * @details Clear the lock by storing 0 to the given address. + * On RH850, this uses a normal store to memory, releasing the lock held by another core/task. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @pre \p Addr must be aligned to word size and visible to all participating cores. + */ +__STATIC_INLINE void RH850_SpinlockRelease (volatile uint32_t * LpAddr) +{ + __ASM volatile ("st.w r0, 0[%0]" : : "r" (LpAddr) : "memory"); +} + +/** + * @brief Acquire a spinlock (blocking) + * @details Attempt to acquire the spinlock using LL/SC (load-linked/store-conditional) primitive: + * - Load-linked the current value at \p Addr. + * - If unlocked (0), try store-conditional of 1. + * - If SC succeeds, the lock is acquired and the function returns. + * - Otherwise, enter low-power wait (snooze) and retry. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @pre \p Addr must be aligned to word size and shared/uncached or properly coherent across cores. + */ +__STATIC_INLINE void RH850_SpinlockGet (volatile uint32_t * LpAddr) +{ + __ASM volatile ( + "Lock_loop%=: \n" + " ldl.w [%0], r20 \n" /* LpAddr */ + " cmp r0, r20 \n" /* is *LpAddr == 0 ? */ + " bnz Lock_wait%= \n" /* Lock_wait */ + " mov 1, r20 \n" + " stc.w r20, [%0] \n" /* try to set *LpAddr = 1 (conditional) */ + " cmp r0, r20 \n" /* stc.w result (0/1); nonzero => success */ + " bnz Lock_success%= \n" + " \n" + "Lock_wait%=: \n" + " snooze \n" + " br Lock_loop%= \n" + " \n" + "Lock_success%=: \n" + : + : "r" (LpAddr) + : "memory", "r20" + ); +} + +/** @} */ /* end of GHS_RH850_Core_AtomicFunctions */ +/** @} */ /* end of RH850_Core_AtomicFunctions */ + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/* ########################################## FPU Function Access ################################################# */ + +/** + * @ingroup RH850_FPU_API + * @{ + */ + +/** + * @brief Initialize the Floating Point Unit (FPU). + * @details + * This function enables the FPU and initializes its status registers. + * + * **Operation steps:** + * - Detect if FPU is present using PID register (SR6,1). + * - Enable FPU by setting the appropriate bit in PSW (SR5,0). + * - Initialize FPSR (SR6,0) and FPEPC (SR7,0) registers. + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) + * - PSW: Program Status Word (SR5,0) + * - FPSR: Floating Point Status Register (SR6,0) + * - FPEPC: Floating Point Exception Program Counter (SR7,0) + */ +__STATIC_INLINE void RH850_FPU_Init (void) +{ + __ASM volatile ( + " stsr 6, r15, 1 \n" /* r10 <- PID */ + " shl 21, r15 \n" + " shr 30, r15 \n" + " bz RH850_FPU_Init_L1%= \n" /* detecting FPU */ + " stsr 5, r15, 0 \n" /* r10 < -PSW */ + " movhi 0x0001, r0, r16 \n" + " or r16, r15 \n" + " ldsr r15, 5, 0 \n" /* enable FPU */ + " \n" + " movhi 0x0002, r0, r16 \n" + " ldsr r16, 6, 0 \n" /* initialize FPSR */ + " ldsr r0, 7, 0 \n" /* initialize FPEPC */ + "RH850_FPU_Init_L1%=: \n" + : + : + : "r15", "r16", "memory" + ); +} + +#endif /* #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) */ + +#if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) + +/* ########################################## FXU Function Access ################################################# */ + +/** + * @ingroup RH850_FXU_API + * @{ + */ + +/** + * @brief Initialize the Fixed-Point Unit (FXU). + * @details + * This function enables the FXU and initializes its configuration and status registers. + * + * **Operation steps:** + * - Detect FXU presence using the PID register (SR6,1) by checking the relevant capability bits. + * - Enable FXU by setting the appropriate bit(s) in PSW (SR5,0). + * - Initialize FXU control/status registers: FXSR, FXST, FXCFG (bank 10). + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) — capability detection + * - PSW: Program Status Word (SR5,0) — enable FXU in status word + * - FXSR: FXU Status Register (SR6,10) + * - FXST: FXU Status (SR8,10) + * - FXCFG: FXU Configuration (SR10,10) + */ +__STATIC_INLINE void RH850_FXU_Init (void) +{ + __ASM volatile ( + " stsr 6, r15, 1 \n" /* r10 <- PID */ + " shl 20, r15 \n" + " shr 31, r15 \n" + " bz RH850_FXU_Init_L2%= \n" /* detecting FXU */ + " stsr 5, r15, 0 \n" /* r10 <- PSW */ + " movhi 0x0002, r0, r16 \n" + " or r16, r15 \n" + " ldsr r15, 5, 0 \n" /* enable FXU */ + " \n" + " movhi 0x0002, r0, r16 \n" + " ldsr r16, 6, 10 \n" /* initialize FXSR */ + " ldsr r0, 8, 10 \n" /* initialize FXST */ + " ldsr r0, 10, 10 \n" /* initialize FXCFG */ + "RH850_FXU_Init_L2%=: \n" + : + : + : "r15", "r16", "memory" + ); +} + +/** @} */ /* end of RH850_FXU_API */ +#endif /* #if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) */ + +/** @} */ /* end of RH850_Core_intrinsics */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ + +#endif /* __RH850_GHS_G4_H */ diff --git a/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_iar_g4.h b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_iar_g4.h new file mode 100644 index 0000000000000000000000000000000000000000..3a937990992d7d5ee3e5239e3e95730c28fce7e4 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/G4-profile/rh850_iar_g4.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_iar_g4.h + * @brief RH850 G4 IAR function + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_IAR_G4_H +#define __RH850_IAR_G4_H + +/** @defgroup RH850_CoreAccess_FunctionInterface RH850-Core Access Functions + * @brief Access to the dedicated core access function. + * @{ + */ + +/** @defgroup RH850_Core_AtomicFunctions RH850-Core Atomic Access Functions + * @ingroup RH850_CoreAccess_FunctionInterface + * @brief RH850-Core Atomic Access Functions + * @{ + */ + +/** @defgroup IAR_RH850_Core_AtomicFunctions IAR RH850-Core Atomic Access Functions + * @brief IAR RH850-Core Atomic Access Functions + * @ingroup RH850_Core_AtomicFunctions + * @{ + */ + +/* ######################################## Atomic Function Access ################################################ */ + +/** + * @brief Release a spinlock + * @details Clear the lock by storing 0 to the given address. + * On RH850, this uses a normal store to memory, releasing the lock held by another core/task. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @pre \p Addr must be aligned to word size and visible to all participating cores. + */ +__STATIC_INLINE void RH850_SpinlockRelease (volatile uint32_t * LpAddr) +{ + __ASM volatile ("st.w r0, 0[%0]" : : "r" (LpAddr) : "memory"); +} + +/** + * @brief Acquire a spinlock (blocking) + * @details Attempt to acquire the spinlock using LL/SC (load-linked/store-conditional) primitive: + * - Load-linked the current value at \p Addr. + * - If unlocked (0), try store-conditional of 1. + * - If SC succeeds, the lock is acquired and the function returns. + * - Otherwise, enter low-power wait (snooze) and retry. + * @param[in] LpAddr Pointer to the spinlock variable in memory. + * @pre \p Addr must be aligned to word size and shared/uncached or properly coherent across cores. + */ +__STATIC_INLINE void RH850_SpinlockGet (volatile uint32_t * LpAddr) +{ + __ASM volatile ( + "_L_Lock_loop: \n" + " ldl.w [%0], r20 \n" + " cmp r0, r20 \n" /* is *LpAddr == 0 ? */ + " bnz _L_Lock_wait \n" /* Lock_wait */ + " mov 1, r20 \n" + " stc.w r20, [%0] \n" /* try to set *LpAddr = 1 (conditional) */ + " cmp r0, r20 \n" /* stc.w result: nonzero => success */ + " bnz _L_Lock_success \n" + " \n" + "_L_Lock_wait: \n" + " snooze \n" + " br _L_Lock_loop \n" + " \n" + "_L_Lock_success: \n" + : + : "r" (LpAddr) + : "memory", "r20" + ); +} + +/** @} */ /* end of IAR_RH850_Core_AtomicFunctions */ +/** @} */ /* end of RH850_Core_AtomicFunctions */ + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/* ########################################## FPU Function Access ################################################# */ + +/** + * @ingroup RH850_FPU_API + * @{ + */ + +/** + * @brief Initialize the Floating Point Unit (FPU). + * @details + * This function enables the FPU and initializes its status registers. + * + * **Operation steps:** + * - Detect if FPU is present using PID register (SR6,1). + * - Enable FPU by setting the appropriate bit in PSW (SR5,0). + * - Initialize FPSR (SR6,0) and FPEPC (SR7,0) registers. + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) + * - PSW: Program Status Word (SR5,0) + * - FPSR: Floating Point Status Register (SR6,0) + * - FPEPC: Floating Point Exception Program Counter (SR7,0) + */ +__STATIC_INLINE void RH850_FPU_Init (void) +{ + __ASM volatile ( + " stsr 6, r15, 1 \n" /* r10 <- PID */ + " shl 21, r15 \n" + " shr 30, r15 \n" + " bz _L_FPU_Init \n" /* detecting FPU */ + " stsr 5, r15, 0 \n" /* r10 < -PSW */ + " movhi 0x0001, r0, r16 \n" + " or r16, r15 \n" + " ldsr r15, 5, 0 \n" /* enable FPU */ + " \n" + " movhi 0x0002, r0, r16 \n" + " ldsr r16, 6, 0 \n" /* initialize FPSR */ + " ldsr r0, 7, 0 \n" /* initialize FPEPC */ + "_L_FPU_Init: \n" + : + : + : "r15", "r16", "memory" + ); +} + +/** @} */ /* end of RH850_FPU_API */ +#endif /* #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) */ + +#if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) + +/* ########################################## FXU Function Access ################################################# */ + +/** + * @ingroup RH850_FXU_API + * @{ + */ + +/** + * @brief Initialize the Fixed-Point Unit (FXU). + * @details + * This function enables the FXU and initializes its configuration and status registers. + * + * **Operation steps:** + * - Detect FXU presence using the PID register (SR6,1) by checking the relevant capability bits. + * - Enable FXU by setting the appropriate bit(s) in PSW (SR5,0). + * - Initialize FXU control/status registers: FXSR, FXST, FXCFG (bank 10). + * + * **Registers used:** + * - PID: Processor Identification (SR6,1) — capability detection + * - PSW: Program Status Word (SR5,0) — enable FXU in status word + * - FXSR: FXU Status Register (SR6,10) + * - FXST: FXU Status (SR8,10) + * - FXCFG: FXU Configuration (SR10,10) + */ +__STATIC_INLINE void RH850_FXU_Init (void) +{ + __ASM volatile ( + " stsr 6, r15, 1 \n" /* r10 <- PID */ + " shl 20, r15 \n" + " shr 31, r15 \n" + " bz _L_FXU_Init_L \n" /* detecting FXU */ + " stsr 5, r15, 0 \n" /* r10 <- PSW */ + " movhi 0x0002, r0, r16 \n" + " or r16, r15 \n" + " ldsr r15, 5, 0 \n" /* enable FXU */ + " \n" + " movhi 0x0002, r0, r16 \n" + " ldsr r16, 6, 10 \n" /* initialize FXSR */ + " ldsr r0, 8, 10 \n" /* initialize FXST */ + " ldsr r0, 10, 10 \n" /* initialize FXCFG */ + "_L_FXU_Init_L: \n" + : + : + : "r15", "r16", "memory" + ); +} + +/** @} */ /* end of RH850_FXU_API */ +#endif /* #if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) */ + +/** @} */ /* end of RH850_Core_intrinsics */ +/** @} */ /* end of RH850_CoreAccess_FunctionInterface */ + +#endif /* __RH850_IAR_G4_H */ diff --git a/arch/rh850/src/g4x/Core/Include/core_g4kh.h b/arch/rh850/src/g4x/Core/Include/core_g4kh.h new file mode 100644 index 0000000000000000000000000000000000000000..cca9c57f76a6206e108f364fe43a04ac1e78c6be --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/core_g4kh.h @@ -0,0 +1,2930 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file core_g4kh.h + * @brief RH850 G4KH Core Definitions + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __CORE_RH850_G4KH_H_GENERIC + #define __CORE_RH850_G4KH_H_GENERIC + + #include + #include + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * RH850 definitions + **********************************************************************************************************************/ + +/** + * @defgroup RH850_glob_defs RH850 Global Defines + * @brief RH850 Global Defines + * @{ + */ + +/** + * @defgroup RH850_G4KH RH850 G4KH + * @ingroup RH850_glob_defs + * @brief RH850 G4KH + * @{ + */ + +/** + * @ingroup RH850_G4KH + * @defgroup RH850_G4KH_Device_Capability_Def RH850 Device capabilitiy defines + * @brief RH850 Device capabilitiy defines + * @{ + */ + + #include "rh850_version.h" + +/* RH850 RH850_G4KH definitions */ + + #define __RH850_G4KH (1) /*!< RH850 G4KH Core */ + + #if defined(__CCRH__) + +/** __FPU_USED indicates whether an FPU is used or not. + */ + #if defined(__FPU) + #define __FPU_USED 1U /*!< FPU used or not */ + #else + #define __FPU_USED 0U /*!< FPU used or not */ + #endif + +/** __FXU_USED indicates whether an FXU is used or not. + */ + #if defined(__FXU) + #define __FXU_USED 1U /*!< FXU used or not */ + #else + #define __FXU_USED 0U /*!< FXU used or not */ + #endif + #endif + + #include "rh850_compiler.h" /* RH850 compiler specific defines */ + + #ifdef __cplusplus +} + #endif + +#endif /* __CORE_RH850_G4KH_H_GENERIC */ + +#ifndef __RH850_GENERIC + + #ifndef __CORE_RH850_G4KH_H_DEPENDANT + #define __CORE_RH850_G4KH_H_DEPENDANT + + #ifdef __cplusplus +extern "C" { + #endif + +/* check device defines and use defaults */ + #if defined __CHECK_DEVICE_DEFINES + #ifndef __RH850_G4KH_REV + #define __RH850_G4KH_REV 0x08U /*!< RH850 G4KH Core revision */ + #warning "__RH850_G4KH_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U /*!< FPU present or not */ + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FXU_PRESENT + #define __FXU_PRESENT 0U /*!< FXU present or not */ + #warning "__FXU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 1U /*!< ICACHE present or not */ + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __IRQ_PRESENT + #define __IRQ_PRESENT 1U /*!< IRQ present or not */ + #warning "__IRQ_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 1U /*!< MPU present or not */ + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 1U /*!< PMU present or not */ + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TSC_PRESENT + #define __TSC_PRESENT 1U /*!< TSC present or not */ + #warning "__TSC_PRESENT not defined in device header file; using default!" + #endif + #endif + +/** @} */ /* end of RH850_Device_Capability_Def */ + +/* IO definitions (access restrictions to peripheral registers) */ + +/** + * @ingroup RH850_G4KH + * @defgroup RH850_G4KH_IO_Type_Qualifiers RH850 IO Type Qualifiers + * @brief RH850 IO Type Qualifiers + * @{ + */ + + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ + #define __IM volatile const /*!< Defines 'read only' structure member permissions */ + #define __OM volatile /*!< Defines 'write only' structure member permissions */ + #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ + +/** @} */ /* end of RH850_IO_Type_Qualifiers */ +/** @} */ /* end of RH850_G4KH */ +/** @} */ /* end of RH850_glob_defs */ + +/*********************************************************************************************************************** + * Register Abstraction + * Core Register contain: + * - Core Register + * - Core Debug Register + * - Core MPU Register + **********************************************************************************************************************/ + +/** + * @defgroup RH850_G4KH_core_register Defines and Type Definitions + * @ingroup RH850_G4KH_Core_register + * + * @brief Type definitions and defines for RH850 G4KH processor based devices. + */ + +/** + * @ingroup RH850_G4KH_core_register + * @defgroup RH850_G4KH_CORE Status and Control Registers + * @brief Core Register type definitions. Basic System Register Definitions for RH850 G4 + * This file provides symbolic names and documentation for system registers. + * @note Based on Table Basic System Registers (Renesas RH850 G4). + * @{ + */ + +/*********************************************************************************************************************** + * EI/FE Exception Registers + **********************************************************************************************************************/ + + #define SR_EIPC 0 /*!< RegID: Status save register for EI level exception (EIPC) (SR0, 0) */ + #define SL_EIPC 0 /*!< SelID: Status save register for EI level exception (EIPC) (SR0, 0) */ + #define SR_EIPSW 1 /*!< RegID: Status save register for EI level exception PSW (EIPSW) (SR1, 0) */ + #define SL_EIPSW 0 /*!< SelID: Status save register for EI level exception PSW (EIPSW) (SR1, 0) */ + #define SR_FEPC 2 /*!< RegID: Status save register for FE level exception (FEPC) (SR2, 0) */ + #define SL_FEPC 0 /*!< SelID: Status save register for FE level exception (FEPC) (SR2, 0) */ + #define SR_FEPSW 3 /*!< RegID: Status save register for FE level exception PSW (FEPSW) (SR3, 0) */ + #define SL_FEPSW 0 /*!< SelID: Status save register for FE level exception PSW (FEPSW) (SR3, 0) */ + #define SR_PSW 5 /*!< RegID: Program Status Word (PSW) (SR5, 0) */ + #define SL_PSW 0 /*!< SelID: Program Status Word (PSW) (SR5, 0) */ + +/*********************************************************************************************************************** + * FPU Registers + **********************************************************************************************************************/ + + #define SR_FPSR 6 /*!< RegID: Floating Point Status Register (FPSR) (SR6, 0) */ + #define SL_FPSR 0 /*!< SelID: Floating Point Status Register (FPSR) (SR6, 0) */ + #define SR_FPEPC 7 /*!< RegID: Floating Point Exception PC (FPEPC) (SR7, 0) */ + #define SL_FPEPC 0 /*!< SelID: Floating Point Exception PC (FPEPC) (SR7, 0) */ + #define SR_FPST 8 /*!< RegID: Floating Point Status (FPST) (SR8, 0) */ + #define SL_FPST 0 /*!< SelID: Floating Point Status (FPST) (SR8, 0) */ + #define SR_FPCC 9 /*!< RegID: Floating Point Condition Code (FPCC) (SR9, 0) */ + #define SL_FPCC 0 /*!< SelID: Floating Point Condition Code (FPCC) (SR9, 0) */ + #define SR_FPCFG 10 /*!< RegID: Floating Point Config (FPCFG) (SR10, 0) */ + #define SL_FPCFG 0 /*!< SelID: Floating Point Config (FPCFG) (SR10, 0) */ + #define SR_FPEC 11 /*!< RegID: Floating-point exception control (FPEC) (SR11, 0) */ + #define SL_FPEC 0 /*!< SelID: Floating-point exception control (FPEC) (SR11, 0) */ + +/*********************************************************************************************************************** + * Exception Cause Registers + **********************************************************************************************************************/ + + #define SR_EIIC 13 /*!< RegID: EI level exception cause (EIIC) (SR13, 0) */ + #define SL_EIIC 0 /*!< SelID: EI level exception cause (EIIC) (SR13, 0) */ + #define SR_FEIC 14 /*!< RegID: FE level exception cause (FEIC) (SR14, 0) */ + #define SL_FEIC 0 /*!< SelID: FE level exception cause (FEIC) (SR14, 0) */ + +/*********************************************************************************************************************** + * CALLT Registers + **********************************************************************************************************************/ + + #define SR_CTPC 16 /*!< RegID: CALLT execution status save register (CTPC) (SR16, 0) */ + #define SL_CTPC 0 /*!< SelID: CALLT execution status save register (CTPC) (SR16, 0) */ + #define SR_CTPSW 17 /*!< RegID: CALLT execution status save register (CTPSW) (SR17, 0) */ + #define SL_CTPSW 0 /*!< SelID: CALLT execution status save register (CTPSW) (SR17, 0) */ + #define SR_CTBP 20 /*!< RegID: CALLT base pointer (CTBP) (SR20, 0) */ + #define SL_CTBP 0 /*!< SelID: CALLT base pointer (CTBP) (SR20, 0) */ + +/*********************************************************************************************************************** + * SNOOZE Control + **********************************************************************************************************************/ + + #define SR_SNZCFG 21 /*!< RegID: SNOOZE control register (SNZCFG) (SR21, 0) */ + #define SL_SNZCFG 0 /*!< SelID: SNOOZE control register (SNZCFG) (SR21, 0) */ + +/*********************************************************************************************************************** + * Exception Registers + **********************************************************************************************************************/ + #define SR_EIWR 28 /*!< RegID: EI level exception working register (SR28, 0) */ + #define SL_EIWR 0 /*!< SelID: EI level exception working register (SR28, 0) */ + #define SR_FEWR 29 /*!< RegID: FE level exception working register (SR29, 0) */ + #define SL_FEWR 0 /*!< SelID: FE level exception working register (SR29, 0) */ + +/*********************************************************************************************************************** + * System Protection Registers + **********************************************************************************************************************/ + + #define SR_SPID 0 /*!< RegID: System protection identifier (SR0, 1) */ + #define SL_SPID 1 /*!< SelID: System protection identifier (SR0, 1) */ + #define SR_SPIDLIST 1 /*!< RegID: List of system protection identifiers (SR1, 1) */ + #define SL_SPIDLIST 1 /*!< SelID: List of system protection identifiers (SR1, 1) */ + #define SR_RBASE 2 /*!< RegID: Reset vector base address (SR2, 1) */ + #define SL_RBASE 1 /*!< SelID: Reset vector base address (SR2, 1) */ + #define SR_EBASE 3 /*!< RegID: Exception handler vector address (SR3, 1) */ + #define SL_EBASE 1 /*!< SelID: Exception handler vector address (SR3, 1) */ + #define SR_INTBP 4 /*!< RegID: Base address of interrupt handler table (SR4, 1) */ + #define SL_INTBP 1 /*!< SelID: Base address of interrupt handler table (SR4, 1) */ + #define SR_MCTL 5 /*!< RegID: CPU control (SR5, 1) */ + #define SL_MCTL 1 /*!< SelID: CPU control (SR5, 1) */ + #define SR_PID 6 /*!< RegID: Processor ID (SR6, 1) */ + #define SL_PID 1 /*!< SelID: Processor ID (SR6, 1) */ + #define SR_SVLOCK 8 /*!< RegID: Supervisor lock (SR8, 1) */ + #define SL_SVLOCK 1 /*!< SelID: Supervisor lock (SR8, 1) */ + #define SR_SCCFG 11 /*!< RegID: SYSCALL operation setting (SR11, 1) */ + #define SL_SCCFG 1 /*!< SelID: SYSCALL operation setting (SR11, 1) */ + #define SR_SCBP 12 /*!< RegID: SYSCALL base pointer (SR12, 1) */ + #define SL_SCBP 1 /*!< SelID: SYSCALL base pointer (SR12, 1) */ + +/*********************************************************************************************************************** + * Processor Element Registers + **********************************************************************************************************************/ + #define SR_PEID 0 /*!< RegID: Processor element identifier (SR0, 2) */ + #define SL_PEID 2 /*!< SelID: Processor element identifier (SR0, 2) */ + #define SR_BMID 1 /*!< RegID: Bus master identifier (SR1, 2) */ + #define SL_BMID 2 /*!< SelID: Bus master identifier (SR1, 2) */ + #define SR_MEA 6 /*!< RegID: Memory error address (SR6, 2) */ + #define SL_MEA 2 /*!< SelID: Memory error address (SR6, 2) */ + #define SR_MEI 8 /*!< RegID: Memory error information (SR8, 2) */ + #define SL_MEI 2 /*!< SelID: Memory error information (SR8, 2) */ + #define SR_RBCR0 15 /*!< RegID: Register bank control 0 (SR15, 2) */ + #define SL_RBCR0 2 /*!< SelID: Register bank control 0 (SR15, 2) */ + #define SR_RBCR1 16 /*!< RegID: Register bank control 1 (SR16, 2) */ + #define SL_RBCR1 2 /*!< SelID: Register bank control 1 (SR16, 2) */ + #define SR_RBNR 17 /*!< RegID: Register bank number (SR17, 2) */ + #define SL_RBNR 2 /*!< SelID: Register bank number (SR17, 2) */ + #define SR_RBIP 18 /*!< RegID: Register bank initial pointer (SR18, 2) */ + #define SL_RBIP 2 /*!< SelID: Register bank initial pointer (SR18, 2) */ + +/*********************************************************************************************************************** + * Interrupt Registers + **********************************************************************************************************************/ + #define SR_ISPR 10 /*!< RegID: Priority of interrupt being serviced (SR10, 2) */ + #define SL_ISPR 2 /*!< SelID: Priority of interrupt being serviced (SR10, 2) */ + #define SR_ICSR 12 /*!< RegID: Interrupt control status (SR12, 2) */ + #define SL_ICSR 2 /*!< SelID: Interrupt control status (SR12, 2) */ + #define SR_INTCFG 13 /*!< RegID: Interrupt function setting (SR13, 2) */ + #define SL_INTCFG 2 /*!< SelID: Interrupt function setting (SR13, 2) */ + #define SR_PLMR 14 /*!< RegID: Interrupt priority masking (SR14, 2) */ + #define SL_PLMR 2 /*!< SelID: Interrupt priority masking (SR14, 2) */ + +/*********************************************************************************************************************** + * FXU Registers + **********************************************************************************************************************/ + #define SR_FXSR 6 /*!< RegID: Extended floating-point operation configuration/status (SR6, 10) */ + #define SL_FXSR 10 /*!< SelID: Extended floating-point operation configuration/status (SR6, 10) */ + #define SR_FXST 8 /*!< RegID: Extended floating-point operation status (SR8, 10) */ + #define SL_FXST 10 /*!< SelID: Extended floating-point operation status (SR8, 10) */ + #define SR_FXINFO 9 /*!< RegID: FXU configuration information (SR9, 10) */ + #define SL_FXINFO 10 /*!< SelID: FXU configuration information (SR9, 10) */ + #define SR_FXCFG 10 /*!< RegID: Extended floating-point operation configuration (SR10, 10) */ + #define SL_FXCFG 10 /*!< SelID: Extended floating-point operation configuration (SR10, 10) */ + #define SR_FXXC 12 /*!< RegID: XC (cause) bits for each operation way (SR12, 10) */ + #define SL_FXXC 10 /*!< SelID: XC (cause) bits for each operation way (SR12, 10) */ + #define SR_FXXP 13 /*!< RegID: XP (preservation) bits for each operation way (SR13, 10) */ + #define SL_FXXP 10 /*!< SelID: XP (preservation) bits for each operation way (SR13, 10) */ + +/*********************************************************************************************************************** + * MPU Registers + **********************************************************************************************************************/ + #define SR_MPM 0 /*!< RegID: Memory protection operation mode setting (SR0, 5) */ + #define SL_MPM 5 /*!< SelID: Memory protection operation mode setting (SR0, 5) */ + #define SR_MPCFG 2 /*!< RegID: MPU configuration (SR2, 5) */ + #define SL_MPCFG 5 /*!< SelID: MPU configuration (SR2, 5) */ + #define SR_MCA 8 /*!< RegID: Memory protection setting check address (SR8, 5) */ + #define SL_MCA 5 /*!< SelID: Memory protection setting check address (SR8, 5) */ + #define SR_MCS 9 /*!< RegID: Memory protection setting check size (SR9, 5) */ + #define SL_MCS 5 /*!< SelID: Memory protection setting check size (SR9, 5) */ + #define SR_MCC 10 /*!< RegID: Memory protection setting check command (SR10, 5) */ + #define SL_MCC 5 /*!< SelID: Memory protection setting check command (SR10, 5) */ + #define SR_MCR 11 /*!< RegID: Memory protection setting check result (SR11, 5) */ + #define SL_MCR 5 /*!< SelID: Memory protection setting check result (SR11, 5) */ + #define SR_MCI 12 /*!< RegID: Memory protection setting check SPID (SR12, 5) */ + #define SL_MCI 5 /*!< SelID: Memory protection setting check SPID (SR12, 5) */ + #define SR_MPIDX 16 /*!< RegID: Index of memory protection setting registers to be accessed (SR16, 5) */ + #define SL_MPIDX 5 /*!< SelID: Index of memory protection setting registers to be accessed (SR16, 5) */ + #define SR_MPBK 17 /*!< RegID: MPU Bank Setting (SR17, 5) */ + #define SL_MPBK 5 /*!< SelID: MPU Bank Setting (SR17, 5) */ + #define SR_MPLA 20 /*!< RegID: Protection area minimum address (SR20, 5) */ + #define SL_MPLA 5 /*!< SelID: Protection area minimum address (SR20, 5) */ + #define SR_MPUA 21 /*!< RegID: Protection area maximum address (SR21, 5) */ + #define SL_MPUA 5 /*!< SelID: Protection area maximum address (SR21, 5) */ + #define SR_MPAT 22 /*!< RegID: Protection area attribute (SR22, 5) */ + #define SL_MPAT 5 /*!< SelID: Protection area attribute (SR22, 5) */ + #define SR_MPID0 24 /*!< RegID: SPID which can access protection area (SR24, 5) */ + #define SL_MPID0 5 /*!< SelID: SPID which can access protection area (SR24, 5) */ + #define SR_MPID1 25 /*!< RegID: SPID which can access protection area (SR25, 5) */ + #define SL_MPID1 5 /*!< SelID: SPID which can access protection area (SR25, 5) */ + #define SR_MPID2 26 /*!< RegID: SPID which can access protection area (SR26, 5) */ + #define SL_MPID2 5 /*!< SelID: SPID which can access protection area (SR25, 5) */ + #define SR_MPID3 27 /*!< RegID: SPID which can access protection area (SR27, 5) */ + #define SL_MPID3 5 /*!< SelID: SPID which can access protection area (SR27, 5) */ + #define SR_MPID4 28 /*!< RegID: SPID which can access protection area (SR28, 5) */ + #define SL_MPID4 5 /*!< SelID: SPID which can access protection area (SR28, 5) */ + #define SR_MPID5 29 /*!< RegID: SPID which can access protection area (SR29, 5) */ + #define SL_MPID5 5 /*!< SelID: SPID which can access protection area (SR29, 5) */ + #define SR_MPID6 30 /*!< RegID: SPID which can access protection area (SR30, 5) */ + #define SL_MPID6 5 /*!< SelID: SPID which can access protection area (SR30, 5) */ + #define SR_MPID7 31 /*!< RegID: SPID which can access protection area (SR31, 5) */ + #define SL_MPID7 5 /*!< SelID: SPID which can access protection area (SR31, 5) */ + +/*********************************************************************************************************************** + * ICAHCE Registers + **********************************************************************************************************************/ + #define SR_ICTAGL 16 /*!< RegID: Instruction cache tag Lo access (SR16, 4) */ + #define SL_ICTAGL 4 /*!< SelID: Instruction cache tag Lo access (SR16, 4) */ + #define SR_ICTAGH 17 /*!< RegID: Instruction cache tag Hi access (SR17, 4) */ + #define SL_ICTAGH 4 /*!< SelID: Instruction cache tag Hi access (SR17, 4) */ + #define SR_ICDATL 18 /*!< RegID: Instruction cache data Lo access (SR18, 4) */ + #define SL_ICDATL 4 /*!< SelID: Instruction cache data Lo access (SR18, 4) */ + #define SR_ICDATH 19 /*!< RegID: Instruction cache data Hi access (SR19, 4) */ + #define SL_ICDATH 4 /*!< SelID: Instruction cache data Hi access (SR19, 4) */ + #define SR_ICCTRL 24 /*!< RegID: Instruction cache control (SR24, 4) */ + #define SL_ICCTRL 4 /*!< SelID: Instruction cache control (SR24, 4) */ + #define SR_ICCFG 26 /*!< RegID: Instruction cache configuration (SR26, 4) */ + #define SL_ICCFG 4 /*!< SelID: Instruction cache configuration (SR26, 4) */ + #define SR_ICERR 28 /*!< RegID: Instruction cache error (SR28, 4) */ + #define SL_ICERR 4 /*!< SelID: Instruction cache error (SR28, 4) */ + +/*********************************************************************************************************************** + * Count Registers + **********************************************************************************************************************/ + #define SR_TSCOUNTL 0 /*!< RegID: Timestamp count L register (SR0, 11) */ + #define SL_TSCOUNTL 11 /*!< SelID: Timestamp count L register (SR0, 11) */ + #define SR_TSCOUNTH 1 /*!< RegID: Timestamp count H register (SR1, 11) */ + #define SL_TSCOUNTH 11 /*!< SelID: Timestamp count H register (SR1, 11) */ + #define SR_TSCTRL 2 /*!< RegID: Timestamp count control register (SR2, 11) */ + #define SL_TSCTRL 11 /*!< SelID: Timestamp count control register (SR2, 11) */ + #define SR_PMUMCTRL 8 /*!< RegID: Performance counter User mode control register (SR8, 11) */ + #define SL_PMUMCTRL 11 /*!< SelID: Performance counter User mode control register (SR8, 11) */ + #define SR_PMCTRL0 17 /*!< RegID: Performance count control 0 register (SR17, 11) */ + #define SL_PMCTRL0 11 /*!< SelID: Performance count control 0 register (SR17, 11) */ + #define SR_PMCTRL1 19 /*!< RegID: Performance count control 1 register (SR19, 11) */ + #define SL_PMCTRL1 11 /*!< SelID: Performance count control 1 register (SR19, 11) */ + #define SR_PMCTRL2 21 /*!< RegID: Performance count control 2 register (SR21, 11) */ + #define SL_PMCTRL2 11 /*!< SelID: Performance count control 2 register (SR21, 11) */ + #define SR_PMCTRL3 23 /*!< RegID: Performance count control 3 register (SR23, 11) */ + #define SL_PMCTRL3 11 /*!< SelID: Performance count control 3 register (SR23, 11) */ + #define SR_PMCOUNT0 16 /*!< RegID: Performance count 0 register (SR16, 11) */ + #define SL_PMCOUNT0 11 /*!< SelID: Performance count 0 register (SR16, 11) */ + #define SR_PMCOUNT1 18 /*!< RegID: Performance count 1 register (SR18, 11) */ + #define SL_PMCOUNT1 11 /*!< SelID: Performance count 1 register (SR18, 11) */ + #define SR_PMCOUNT2 20 /*!< RegID: Performance count 2 register (SR20, 11) */ + #define SL_PMCOUNT2 11 /*!< SelID: Performance count 2 register (SR20, 11) */ + #define SR_PMCOUNT3 22 /*!< RegID: Performance count 3 register (SR22, 11) */ + #define SL_PMCOUNT3 11 /*!< SelID: Performance count 3 register (SR22, 11) */ + +/*********************************************************************************************************************** + * Hardware Registers + **********************************************************************************************************************/ + #define SR_LSTEST0 0 /*!< RegID: Lock-step function self-diagnosis register 0 (SR0, 12) */ + #define SL_LSTEST0 12 /*!< SelID: Lock-step function self-diagnosis register 0 (SR0, 12) */ + #define SR_LSTEST1 1 /*!< RegID: Lock-step function self-diagnosis register 1 (SR1, 12) */ + #define SL_LSTEST1 12 /*!< SelID: Lock-step function self-diagnosis register 1 (SR1, 12) */ + +/*@} end of group RH850_CORE */ + +/** + * @ingroup RH850_G4KH_core_register + * @defgroup RH850_G4KH_core_bitfield Core register bit field macros + * @brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + * @{ + */ + +/** + * @brief Mask and shift a bit field value for use in a register bit range. + * @param[in] field Name of the register bit field. + * @param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + * @return Masked and shifted value. + */ + #define _VAL2FLD(field, value) (((uint32_t) (value) << field ## _Pos) & field ## _Msk) + +/** + * @brief Mask and shift a register value to extract a bit field value. + * @param[in] field Name of the register bit field. + * @param[in] value Value of register. This parameter is interpreted as an uint32_t type. + * @return Masked and shifted bit field value. + */ + #define _FLD2VAL(field, value) (((uint32_t) (value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group RH850_core_bitfield */ + +/*********************************************************************************************************************** + * RH850 definitions + **********************************************************************************************************************/ + +/** + * @defgroup RH850_Core_register RH850-Core Register + * @brief RH850-Core Register + * @{ + */ + +/** + * @defgroup RH850_G4KH_Core_register RH850 G4KH Core Register + * @brief RH850 G4KH Core Register + * @ingroup RH850_Core_register + * @{ + */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_SYS Basic System Register (SYS) + * @brief Type definitions for the basic sytem register (SYS) + * @{ + */ + +/** + * @brief Structure type to access the basic system register (SYS). + */ + +typedef union +{ + __IOM uint32_t EIPC; /*!< (@ 0x00000000) Status Save Register when Acknowledging EI Level + * Exception */ + + struct + { + __IOM uint32_t EIPC : 32; /*!< [31..0] These bits indicate the PC saved when an EI level exception + * isacknowledged.EIPC0:This bit indicates the PC saved when + * an EI level exception is acknowledged.Always set this bit + * to 0. Even if it is set to 1, the value transferred to + * the PCwhen the EIRET instruction is executed is 0. */ + } EIPC_b; +} RH850_SYS_EIPC_Type; + +typedef union +{ + __IOM uint32_t EIPSW; /*!< (@ 0x00000000) Status Save Register when Acknowledging EI Level + * Exception */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit stores the PSW.Z bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t S : 1; /*!< [1..1] This bit stores the PSW.S bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit stores the PSW.OV bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit stores the PSW.CY bit setting when an EI level + * exception isacknowledged. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit stores the PSW.SAT bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit stores the PSW.ID bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit stores the PSW.EP bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit stores the PSW.NP bit setting when an EI level + * exception isacknowledged */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit stores the PSW.EBV bit setting when an EI + * level exception isacknowledged */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This bit stores the PSW.EIMASK bit setting when an + * EI level exception isacknowledged */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit stores the PSW.UM bit setting when an EI level + * exception isacknowledged. */ + uint32_t : 1; + } EIPSW_b; +} RH850_SYS_EIPSW_Type; + +typedef union +{ + __IOM uint32_t FEPC; /*!< (@ 0x00000000) Status Save Register when Acknowledging FE Level + * Exception */ + + struct + { + __IOM uint32_t FEPC : 32; /*!< [31..0] This bit indicates the PC saved when an FE level exception + * isacknowledged.FEPC0: Always set this bit to 0. Even if + * it is set to 1, the value transferred to the PCwhen the + * FERET instruction is executed is 0. */ + } FEPC_b; +} RH850_SYS_FEPC_Type; + +typedef union +{ + __IOM uint32_t FEPSW; /*!< (@ 0x00000000) Status Save Register when Acknowledging FE Level + * Exception */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit stores the PSW.Z bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t S : 1; /*!< [1..1] This bit stores the PSW.S bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit stores the PSW.OV bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit stores the PSW.CY bit setting when an FE level + * exception isacknowledged. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit stores the PSW.SAT bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit stores the PSW.ID bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit stores the PSW.EP bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit stores the PSW.NP bit setting when an FE level + * exception isacknowledged */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit stores the PSW.EBV bit setting when an FE + * level exception isacknowledged */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This bit stores the PSW.EIMASK bit setting when an + * FE level exception isacknowledged */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit stores the PSW.UM bit setting when an FE level + * exception isacknowledged. */ + uint32_t : 1; + } FEPSW_b; +} RH850_SYS_FEPSW_Type; + +typedef union +{ + __IOM uint32_t PSW; /*!< (@ 0x00000000) Program Status Word */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit indicates whether or not the result of an operation + * is 0.0: Result of operation is not 0.1: Result of operation + * is 0. */ + __IOM uint32_t S : 1; /*!< [1..1] This bit indicates whether or not the result of an operation + * is negative.0: Result of operation is positive or 0.1: + * Result of operation is negative */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit indicates whether or not an overflow has occurred + * during anoperation.0: Overflow has not occurred.1: Overflow + * has occurred. */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit indicates whether a carry or borrow has occurred + * in the operationresult.0: Carry and borrow have not occurred.1: + * Carry or borrow has occurred. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit indicates that a saturation arithmetic operation + * instruction resulted inoverflow and saturation processing + * is applied to the result. This is acumulative flag, that + * is, it is set (1) once a saturation occurs and not cleared(0) + * by subsequent instructions with unsaturated results. This + * bit is cleared bythe LDSR instruction. Note that execution + * of an arithmetic operationinstruction neither set nor clear + * this flag.0: The result was not saturated1: The result + * was saturated */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit disables the acknowledgement of EI level exception. + * When an EIlevel or FE level exception is acknowledged, + * this bit is set to 1 to disable theacknowledgement of EI + * level exception. As for the exceptions which the IDbit + * disables the acknowledgment, see Table 3.103, Exception + * Cause ListThis bit is also used to disable EI level exceptions + * from being acknowledgedas a critical section while an ordinary + * program or interrupt is being serviced.It is set to 1 when + * the DI instruction is executed */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit indicates that an exception other than an interrupt + * is being serviced.It is set to 1 when the corresponding + * exception occurs. This bit does notaffect acknowledging + * an exception request even when it is set to 1.0: An exception + * other than an interrupt is not being serviced.1: An exception + * other than an interrupt is being serviced */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit disables the acknowledgement of FE level exception. + * When an FElevel exception is acknowledged, this bit is + * set to 1 to disable theacknowledgement of EI level and + * FE level exceptions. As for the exceptionswhich the NP + * bit disables the acknowledgment, see Table 3.103, ExceptionCause + * List.0: The acknowledgement of FE level exception is enabled.1: + * The acknowledgement of FE level exception is disabled. */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit indicates the reset vector and exception vector + * operation. SeeSection 3.2.3.2(16), RBASE — Reset Vector + * Base Address and Section3.2.3.2(17), EBASE — Exception + * Handler Vector Address */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This field indicates the interrupt priority boundary + * between enabling anddisabling an acknowlegement of an interrupt + * (EIINTn). For an interrupt(EIINTn) with higher priority + * than the value set in this field, theacknowlegement is + * enabled. For an interrupt (EIINTn) with priority less thanor + * equal to the value set in this field, the acknowlegement + * is disabled.0: All priorities are not acceptable.1: Acceptable + * priority is 02: Acceptable priority is 0 to 1...62: Acceptable + * priority is 0 to 61 */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit indicates that the CPU is in user mode (in + * UM mode).0: Supervisor mode1: User mode */ + uint32_t : 1; + } PSW_b; +} RH850_SYS_PSW_Type; + +typedef union +{ + __IOM uint32_t EIIC; /*!< (@ 0x00000000) EI Level Exception Cause */ + + struct + { + __IOM uint32_t EIIC : 32; /*!< [31..0] These bits store the exception cause code when an EI + * level exceptionoccurs. The EIIC15-0 field stores the exception + * cause codes shown in Table3.103, Exception Cause List. + * The EIIC31-16 field stores detailed exceptioncause codes + * defined individually for each exception. If there is no + * particulardefinition, these bits are set to 0. */ + } EIIC_b; +} RH850_SYS_EIIC_Type; + +typedef union +{ + __IOM uint32_t FEIC; /*!< (@ 0x00000000) FE Level Exception Cause */ + + struct + { + __IOM uint32_t FEIC : 32; /*!< [31..0] These bits store the exception cause code when an FE + * level exceptionoccurs. The FEIC15-0 field stores the exception + * cause codes shown inTable 3.103, Exception Cause List. + * The FEIC31-16 field stores detailedexception cause codes + * defined individually for each exception. If there is noparticular + * definition, these bits are set to 0. */ + } FEIC_b; +} RH850_SYS_FEIC_Type; + +typedef union +{ + __IOM uint32_t CTPC; /*!< (@ 0x00000000) Status Save Register when Executing CALLT */ + + struct + { + __IOM uint32_t CTPC : 32; /*!< [31..0] This bit indicates the PC of the instruction after the + * CALLT instruction.Always set this bit to 0. Even if it + * is set to 1, the value transferred to the PCwhen the CTRET + * instruction is executed is 0. */ + } CTPC_b; +} RH850_SYS_CTPC_Type; + +typedef union +{ + __IOM uint32_t CTPSW; /*!< (@ 0x00000000) Status Save Register when Executing CALLT */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit indicates whether or not the result of an operation + * is 0.0: Result of operation is not 0.1: Result of operation + * is 0. */ + __IOM uint32_t S : 1; /*!< [1..1] This bit indicates whether or not the result of an operation + * is negative.0: Result of operation is positive or 0.1: + * Result of operation is negative */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit indicates whether or not an overflow has occurred + * during anoperation.0: Overflow has not occurred.1: Overflow + * has occurred. */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit indicates whether a carry or borrow has occurred + * in the operationresult.0: Carry and borrow have not occurred.1: + * Carry or borrow has occurred. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit indicates that a saturation arithmetic operation + * instruction resulted inoverflow and saturation processing + * is applied to the result. This is acumulative flag, that + * is, it is set (1) once a saturation occurs and not cleared(0) + * by subsequent instructions with unsaturated results. This + * bit is cleared bythe LDSR instruction. Note that execution + * of an arithmetic operationinstruction neither set nor clear + * this flag.0: The result was not saturated1: The result + * was saturated */ + uint32_t : 27; + } CTPSW_b; +} RH850_SYS_CTPSW_Type; + +typedef union +{ + __IOM uint32_t CTBP; /*!< (@ 0x00000000) CALLT Base Pointer */ + + struct + { + __IM uint32_t CTBP0 : 1; /*!< [0..0] This bit indicates the base pointer address of the CALLT + * instruction.This bit indicates the start address of the + * table used by the CALLTinstruction. Always set this bit + * to 0. */ + __IOM uint32_t CTBP : 31; /*!< [31..1] This bit indicates the base pointer address of the CALLT + * instruction.This bit indicates the start address of the + * table used by the CALLTinstruction.CTBP0: Always set this + * bit to 0. */ + } CTBP_b; +} RH850_SYS_CTBP_Type; + +typedef union +{ + __IOM uint32_t SNZCFG; /*!< (@ 0x00000000) SNOOZE Configuration */ + + struct + { + __IOM uint32_t SNZCNT : 8; /*!< [7..0] These bits specify the number of clock cycles in which + * execution is to betemporarily halted by the SNOOZE instruction */ + uint32_t : 24; + } SNZCFG_b; +} RH850_SYS_SNZCFG_Type; + +typedef union +{ + __IOM uint32_t EIWR; /*!< (@ 0x00000000) EI Level Exception Working Register */ + + struct + { + __IOM uint32_t EIWR : 32; /*!< [31..0] These bits constitute a working register that can be + * used for any purposeduring the processing of an EI level + * exception. Use this register for purposessuch as storing + * the values of general-purpose registers */ + } EIWR_b; +} RH850_SYS_EIWR_Type; + +typedef union +{ + __IOM uint32_t FEWR; /*!< (@ 0x00000000) FE Level Exception Working Register */ + + struct + { + __IOM uint32_t FEWR : 32; /*!< [31..0] These bits constitute a working register that can be + * used for any purposeduring the processing of an FE level + * exception. Use this register forpurposes such as storing + * the values of general-purpose registers. */ + } FEWR_b; +} RH850_SYS_FEWR_Type; + +typedef union +{ + __IOM uint32_t SPID; /*!< (@ 0x00000000) System Protection Identifier */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits indicate the system protection identifier.The + * system protection identifier is a variable ID that is used + * for accessprotection in a product which consists of two + * or more bus masters includingthis CPU. For its uses and + * constraints on its value, see Section 3.10.7,Product information + * of initial value for G4KH register.Within this CPU, the + * SPID is used to check for area matching by the MPU. Itallows + * the system specifications defined for the product to be + * reflected in theMPU's protecti */ + uint32_t : 27; + } SPID_b; +} RH850_SYS_SPID_Type; + +typedef union +{ + __IOM uint32_t SPIDLIST; /*!< (@ 0x00000000) Legitimate System Protection Identifier List */ + + struct + { + __IM uint32_t SL : 32; /*!< [31..0] This bit indicates whether or not bit can be set as + * a system protection identifier */ + } SPIDLIST_b; +} RH850_SYS_SPIDLIST_Type; + +typedef union +{ + __IOM uint32_t RBASE; /*!< (@ 0x00000000) Reset Vector Base Address */ + + struct + { + __IM uint32_t RINT : 1; /*!< [0..0] When the RINT bit is set, the exception handler address + * for interruptprocessing is reduced. See Section 3.2.4.4(1)(a), + * Direct Vector Method.This bit is valid when PSW.EBV = 0. */ + __IM uint32_t DV : 1; /*!< [1..1] When the DV bit is set, the exception handler address + * for interrupt isdetermined by using the direct vector method. + * For details, see Section3.2.4.4(1)(b), Table Reference + * Method. This bit is valid when PSW.EBV =0. */ + uint32_t : 7; + __IM uint32_t RBASE : 23; /*!< [31..9] These bits indicate the reset vector when there is a + * reset. When PSW.EBV =0, this address is also used as the + * exception vector.The RBASE8 to RBASE0 bits are not assigned + * as names because these bitsare always 0. */ + } RBASE_b; +} RH850_SYS_RBASE_Type; + +typedef union +{ + __IOM uint32_t EBASE; /*!< (@ 0x00000000) Exception Handler Vector Address */ + + struct + { + __IOM uint32_t RINT : 1; /*!< [0..0] When the RINT bit is set, the exception handler address + * for interruptprocessing is reduced. See Section 3.2.4.4(1)(a), + * Direct Vector Method. */ + __IOM uint32_t DV : 1; /*!< [1..1] When the DV bit is set, the exception handler address + * for interrupt isdetermined by using the direct vector method. + * For details, see Section3.2.4.4(1)(b), Table Reference + * Method */ + uint32_t : 7; + __IOM uint32_t EBASE : 23; /*!< [31..9] The exception handler routine address is changed to + * the address resultingfrom adding the offset address of + * each exception to the base addressspecified for this register.The + * EBASE8 to EBASE0 bits are not assigned as names because + * these bitsare always 0. */ + } EBASE_b; +} RH850_SYS_EBASE_Type; + +typedef union +{ + __IOM uint32_t INTBP; /*!< (@ 0x00000000) Base Address of the Interrupt Handler Address + * Table */ + + struct + { + uint32_t : 9; + __IOM uint32_t INTBP : 23; /*!< [31..9] These bits indicate the base pointer address for an + * interrupt when the tablereference method is used.The value + * indicated by these bits is the first address in the table + * used todetermine the exception handler when the interrupt + * specified by the tablereference method (EIINTn) is acknowledged.The + * INTBP8 to INTBP0 bits are not assigned as names because + * these bitsare always 0. */ + } INTBP_b; +} RH850_SYS_INTBP_Type; + +typedef union +{ + __IOM uint32_t MCTL; /*!< (@ 0x00000000) Machine Control */ + + struct + { + __IOM uint32_t UIC : 1; /*!< [0..0] This bit is used to control the interrupt enable/disable + * operation in usermode. When this bit is set to 1, executing + * the EI/DI instruction in user modebecome possible */ + uint32_t : 31; + } MCTL_b; +} RH850_SYS_MCTL_Type; + +typedef union +{ + __IOM uint32_t SVLOCK; /*!< (@ 0x00000000) Supervisor Lock */ + + struct + { + __IOM uint32_t SVL : 1; /*!< [0..0] This bit specifies whether to restrict the CPU operation + * in supervisor mode.0: Does not restrict the CPU operation + * in supervisor mode.1: Restrict the CPU operation in supervisor + * mode.If the SVL bit is set to 1, the following system registers*1cannot + * be updated even when the CPU is in supervisor mode:SPID, + * MPM, MPLA, MPUA, MPAT, MPIDn, MPBK */ + uint32_t : 31; + } SVLOCK_b; +} RH850_SYS_SVLOCK_Type; + +typedef union +{ + __IOM uint32_t SCCFG; /*!< (@ 0x00000000) SYSCALL Operation Setting */ + + struct + { + __IOM uint32_t SIZE : 8; /*!< [7..0] These bits specify the maximum number of entries of a + * table that theSYSCALL instruction references. The maximum + * number of entries theSYSCALL instruction references is + * 1 if SIZE is 0, and 256 if SIZE is 255. Bysetting the maximum + * number of entries appropriately in accordance with thenumber + * of functions branched by the SYSCALL instruction, the memory + * areacan be effectively used.If a vector exceeding the maximum + * number of entries is specified for theSYSCALL instruction, + * the first entry is select */ + uint32_t : 24; + } SCCFG_b; +} RH850_SYS_SCCFG_Type; + +typedef union +{ + __IOM uint32_t SCBP; /*!< (@ 0x00000000) SYSCALL Base Pointer */ + + struct + { + __IOM uint32_t SCBP : 32; /*!< [31..0] These bits indicate the base pointer address of the + * SYSCALL instruction.These bits indicate the start address + * of the table used by the SYSCALLinstruction.SCBP[0:1]: + * Always set these bits to 0. */ + } SCBP_b; +} RH850_SYS_SCBP_Type; + +typedef union +{ + __IOM uint32_t PEID; /*!< (@ 0x00000000) Processor Element Identifier */ + + struct + { + __IM uint32_t PEID : 5; /*!< [4..0] These bits indicate the processor element identifier. */ + uint32_t : 27; + } PEID_b; +} RH850_SYS_PEID_Type; + +typedef union +{ + __IOM uint32_t BMID; /*!< (@ 0x00000000) Bus Master Identifier */ + + struct + { + __IM uint32_t BMID : 5; /*!< [4..0] These bits indicate the bus master identifier */ + uint32_t : 27; + } BMID_b; +} RH850_SYS_BMID_Type; + +typedef union +{ + __IOM uint32_t MEA; /*!< (@ 0x00000000) Memory Error Address */ + + struct + { + __IOM uint32_t MEA : 32; /*!< [31..0] These bits holds the address in which an MAE (misalignment) + * or MPUviolation occurred. */ + } MEA_b; +} RH850_SYS_MEA_Type; + +typedef union +{ + __IOM uint32_t MEI; /*!< (@ 0x00000000) Memory Error Information */ + + struct + { + __IOM uint32_t RW : 1; /*!< [0..0] This bit indicates whether the operation performed by + * the instruction thatcaused the exception is a read (Load-memory) + * or a write (Store-memory).0: Read (Load-memory)1: Write + * (Store-memory) */ + __IOM uint32_t ITYPE : 5; /*!< [5..1] These bits indicate the instruction that caused the exception */ + uint32_t : 2; + __IOM uint32_t U : 1; /*!< [8..8] This bit indicates the sign extension method of the instruction + * that causedthe exception.0: Signed1: Unsigned */ + __IOM uint32_t DS : 3; /*!< [11..9] These bits indicate the data type of the instruction + * that caused theexception*1.0: Byte (8 bits)1: Halfword + * (16 bits)2: Word (32 bits)3: Double-word (64 bits)4: Quad-word + * (128 bits) */ + uint32_t : 4; + __IOM uint32_t REG : 5; /*!< [20..16] These bits indicate the source register number or destination + * registernumber of the instruction that caused the exception */ + uint32_t : 7; + __IOM uint32_t LEN : 4; /*!< [31..28] These bits indicate the code size of the instruction + * that causes the exception.0: Non-instruction factor2: 16 + * bits4: 32 bits6: 48 bits8 :64 bits */ + } MEI_b; +} RH850_SYS_MEI_Type; + +typedef union +{ + __IOM uint32_t RBCR0; /*!< (@ 0x00000000) Register Bank Control 0 */ + + struct + { + __IOM uint32_t BE : 15; /*!< [14..0] These bits specify the priority level of the interrupt + * on which the register bankis to be used.0: Do not use the + * register bank on an interrupt of the level corresponding + * tothis bit.1: Use the register bank on an interrupt of + * the level corresponding to thisbit. */ + __IOM uint32_t BE15 : 1; /*!< [15..15] This bit specifies whether to use a register bank on + * an interrupt (EIINTn) withpriority 15 to 630: Do not use + * the register bank on an interrupt with the priority 15 + * to 631: Use the register bank on an interrupt with the + * priority 15 to 63While this bit is set to 1, if EI level + * interrupt (EIINTn) with priority 15 to 63 isacknowledged, + * the register bank function can be used. */ + __IOM uint32_t MD : 1; /*!< [16..16] This bit specifies the save mode of the register bank.0: + * Save mode 01: Save mode 1 */ + uint32_t : 15; + } RBCR0_b; +} RH850_SYS_RBCR0_Type; + +typedef union +{ + __IOM uint32_t RBCR1; /*!< (@ 0x00000000) Register Bank Control 1 */ + + struct + { + __IOM uint32_t NC : 15; /*!< [14..0] These bits specify the priority level of the interrupt + * on which the register bankis to be used.0: Do not use the + * register bank on an interrupt of the level corresponding + * tothis bit.1: Use the register bank on an interrupt of + * the level corresponding to thisbit. */ + __IOM uint32_t NC15 : 1; /*!< [15..15] This bit specifies whether to use a register bank on + * an interrupt (EIINTn) withpriority 15 to 630: Do not use + * the register bank on an interrupt with the priority 15 + * to 631: Use the register bank on an interrupt with the + * priority 15 to 63While this bit is set to 1, if EI level + * interrupt (EIINTn) with priority 15 to 63 isacknowledged, + * the register bank function can be used. */ + uint32_t : 16; + } RBCR1_b; +} RH850_SYS_RBCR1_Type; + +typedef union +{ + __IOM uint32_t RBNR; /*!< (@ 0x00000000) Register Bank Number */ + + struct + { + __IOM uint32_t BN : 6; /*!< [5..0] These bits indicate the number of the register bank to + * be used next.The value in these bits is incremented by + * 1 when an interrupt (EIINTn) thatuses a register bank is + * accepted. If the value of BN is larger thanINTCFG.ULNR, + * or if the value of BN is 63, if an interrupt (EIINTn) using + * theregister bank occurs, a SYSERR exception is generated. + * That interrupt is notaccepted, and it is put on hold.The + * value of BN is decremented by 1 when a RESBANK instruction + * isexecuted. If the RESBANK instruction i */ + uint32_t : 26; + } RBNR_b; +} RH850_SYS_RBNR_Type; + +typedef union +{ + __IOM uint32_t RBIP; /*!< (@ 0x00000000) Register Bank Initial Pointer */ + + struct + { + uint32_t : 4; + __IOM uint32_t RBIP : 28; /*!< [31..4] These bits indicate the initial pointer to the register + * bank.The values of RBCR0.MD and RBNR.BN together with this + * value determinethe memory address to which the next register + * bank to be used is allocatedas follows.• Save mode 0 + * (RBCR0.MD = 0): RBIP - RBNR.BN × 60H• Save mode 1 + * (RBCR0.MD = 1): RBIP - RBNR.BN × 90H */ + } RBIP_b; +} RH850_SYS_RBIP_Type; + +/** @brief Basic system register macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_SYS ================ */ +/* ================================================================================================================== */ + +/* ========================================================= EIPC ================================================= */ + #define R_SYS_EIPC_EIPC_Pos (0UL) /*!< EIPC (Bit 0) */ + #define R_SYS_EIPC_EIPC_Msk (0xffffffffUL) /*!< EIPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EIPSW ================================================ */ + #define R_SYS_EIPSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_EIPSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_EIPSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_EIPSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_EIPSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_EIPSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_EIPSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_EIPSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_EIPSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_EIPSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_EIPSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_EIPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_EIPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_EIPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_EIPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_EIPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= FEPC ================================================= */ + #define R_SYS_FEPC_FEPC_Pos (0UL) /*!< FEPC (Bit 0) */ + #define R_SYS_FEPC_FEPC_Msk (0xffffffffUL) /*!< FEPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEPSW ================================================ */ + #define R_SYS_FEPSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_FEPSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_FEPSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_FEPSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_FEPSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_FEPSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_FEPSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_FEPSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_FEPSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_FEPSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_FEPSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_FEPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_FEPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_FEPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_FEPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_FEPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================== PSW ================================================= */ + #define R_SYS_PSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_PSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_PSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_PSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_PSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_PSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_PSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_PSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_PSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_PSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_PSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_PSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_PSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_PSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_PSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_PSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= EIIC ================================================= */ + #define R_SYS_EIIC_EIIC_Pos (0UL) /*!< EIIC (Bit 0) */ + #define R_SYS_EIIC_EIIC_Msk (0xffffffffUL) /*!< EIIC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEIC ================================================= */ + #define R_SYS_FEIC_FEIC_Pos (0UL) /*!< FEIC (Bit 0) */ + #define R_SYS_FEIC_FEIC_Msk (0xffffffffUL) /*!< FEIC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CTPC ================================================= */ + #define R_SYS_CTPC_CTPC_Pos (0UL) /*!< CTPC (Bit 0) */ + #define R_SYS_CTPC_CTPC_Msk (0xffffffffUL) /*!< CTPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CTPSW ================================================ */ + #define R_SYS_CTPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_CTPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_CTPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_CTPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_CTPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_CTPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= CTBP ================================================= */ + #define R_SYS_CTBP_CTBP_Pos (1UL) /*!< CTBP (Bit 1) */ + #define R_SYS_CTBP_CTBP_Msk (0xfffffffeUL) /*!< CTBP (Bitfield-Mask: 0x7fffffff) */ + #define R_SYS_CTBP_CTBP0_Pos (0UL) /*!< CTBP0 (Bit 0) */ + #define R_SYS_CTBP_CTBP0_Msk (0x1UL) /*!< CTBP0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZCFG ================================================ */ + #define R_SYS_SNZCFG_SNZCNT_Pos (0UL) /*!< SNZCNT (Bit 0) */ + #define R_SYS_SNZCFG_SNZCNT_Msk (0xffUL) /*!< SNZCNT (Bitfield-Mask: 0xff) */ +/* ========================================================= EIWR ================================================= */ + #define R_SYS_EIWR_EIWR_Pos (0UL) /*!< EIWR (Bit 0) */ + #define R_SYS_EIWR_EIWR_Msk (0xffffffffUL) /*!< EIWR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEWR ================================================= */ + #define R_SYS_FEWR_FEWR_Pos (0UL) /*!< FEWR (Bit 0) */ + #define R_SYS_FEWR_FEWR_Msk (0xffffffffUL) /*!< FEWR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SPID ================================================= */ + #define R_SYS_SPID_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_SYS_SPID_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ======================================================= SPIDLIST =============================================== */ + #define R_SYS_SPIDLIST_SL_Pos (0UL) /*!< SL (Bit 0) */ + #define R_SYS_SPIDLIST_SL_Msk (0xffffffffUL) /*!< SL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RBASE ================================================ */ + #define R_SYS_RBASE_RBASE_Pos (9UL) /*!< RBASE (Bit 9) */ + #define R_SYS_RBASE_RBASE_Msk (0xfffffe00UL) /*!< RBASE (Bitfield-Mask: 0x7fffff) */ + #define R_SYS_RBASE_DV_Pos (1UL) /*!< DV (Bit 1) */ + #define R_SYS_RBASE_DV_Msk (0x2UL) /*!< DV (Bitfield-Mask: 0x01) */ + #define R_SYS_RBASE_RINT_Pos (0UL) /*!< RINT (Bit 0) */ + #define R_SYS_RBASE_RINT_Msk (0x1UL) /*!< RINT (Bitfield-Mask: 0x01) */ +/* ========================================================= EBASE ================================================ */ + #define R_SYS_EBASE_EBASE_Pos (9UL) /*!< EBASE (Bit 9) */ + #define R_SYS_EBASE_EBASE_Msk (0xfffffe00UL) /*!< EBASE (Bitfield-Mask: 0x7fffff) */ + #define R_SYS_EBASE_DV_Pos (1UL) /*!< DV (Bit 1) */ + #define R_SYS_EBASE_DV_Msk (0x2UL) /*!< DV (Bitfield-Mask: 0x01) */ + #define R_SYS_EBASE_RINT_Pos (0UL) /*!< RINT (Bit 0) */ + #define R_SYS_EBASE_RINT_Msk (0x1UL) /*!< RINT (Bitfield-Mask: 0x01) */ +/* ========================================================= INTBP ================================================ */ + #define R_SYS_INTBP_INTBP_Pos (9UL) /*!< INTBP (Bit 9) */ + #define R_SYS_INTBP_INTBP_Msk (0xfffffe00UL) /*!< INTBP (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= MCTL ================================================= */ + #define R_SYS_MCTL_UIC_Pos (0UL) /*!< UIC (Bit 0) */ + #define R_SYS_MCTL_UIC_Msk (0x1UL) /*!< UIC (Bitfield-Mask: 0x01) */ +/* ======================================================== SVLOCK ================================================ */ + #define R_SYS_SVLOCK_SVL_Pos (0UL) /*!< SVL (Bit 0) */ + #define R_SYS_SVLOCK_SVL_Msk (0x1UL) /*!< SVL (Bitfield-Mask: 0x01) */ +/* ========================================================= SCCFG ================================================ */ + #define R_SYS_SCCFG_SIZE_Pos (0UL) /*!< SIZE (Bit 0) */ + #define R_SYS_SCCFG_SIZE_Msk (0xffUL) /*!< SIZE (Bitfield-Mask: 0xff) */ +/* ========================================================= SCBP ================================================= */ + #define R_SYS_SCBP_SCBP_Pos (0UL) /*!< SCBP (Bit 0) */ + #define R_SYS_SCBP_SCBP_Msk (0xffffffffUL) /*!< SCBP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PEID ================================================= */ + #define R_SYS_PEID_PEID_Pos (0UL) /*!< PEID (Bit 0) */ + #define R_SYS_PEID_PEID_Msk (0x1fUL) /*!< PEID (Bitfield-Mask: 0x1f) */ +/* ========================================================= BMID ================================================= */ + #define R_SYS_BMID_BMID_Pos (0UL) /*!< BMID (Bit 0) */ + #define R_SYS_BMID_BMID_Msk (0x1fUL) /*!< BMID (Bitfield-Mask: 0x1f) */ +/* ========================================================== MEA ================================================= */ + #define R_SYS_MEA_MEA_Pos (0UL) /*!< MEA (Bit 0) */ + #define R_SYS_MEA_MEA_Msk (0xffffffffUL) /*!< MEA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MEI ================================================= */ + #define R_SYS_MEI_LEN_Pos (28UL) /*!< LEN (Bit 28) */ + #define R_SYS_MEI_LEN_Msk (0xf0000000UL) /*!< LEN (Bitfield-Mask: 0x0f) */ + #define R_SYS_MEI_REG_Pos (16UL) /*!< REG (Bit 16) */ + #define R_SYS_MEI_REG_Msk (0x1f0000UL) /*!< REG (Bitfield-Mask: 0x1f) */ + #define R_SYS_MEI_DS_Pos (9UL) /*!< DS (Bit 9) */ + #define R_SYS_MEI_DS_Msk (0xe00UL) /*!< DS (Bitfield-Mask: 0x07) */ + #define R_SYS_MEI_U_Pos (8UL) /*!< U (Bit 8) */ + #define R_SYS_MEI_U_Msk (0x100UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_SYS_MEI_ITYPE_Pos (1UL) /*!< ITYPE (Bit 1) */ + #define R_SYS_MEI_ITYPE_Msk (0x3eUL) /*!< ITYPE (Bitfield-Mask: 0x1f) */ + #define R_SYS_MEI_RW_Pos (0UL) /*!< RW (Bit 0) */ + #define R_SYS_MEI_RW_Msk (0x1UL) /*!< RW (Bitfield-Mask: 0x01) */ +/* ========================================================= RBCR0 ================================================ */ + #define R_SYS_RBCR0_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_SYS_RBCR0_MD_Msk (0x10000UL) /*!< MD (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR0_BE15_Pos (15UL) /*!< BE15 (Bit 15) */ + #define R_SYS_RBCR0_BE15_Msk (0x8000UL) /*!< BE15 (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR0_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_SYS_RBCR0_BE_Msk (0x7fffUL) /*!< BE (Bitfield-Mask: 0x7fff) */ +/* ========================================================= RBCR1 ================================================ */ + #define R_SYS_RBCR1_NC15_Pos (15UL) /*!< NC15 (Bit 15) */ + #define R_SYS_RBCR1_NC15_Msk (0x8000UL) /*!< NC15 (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR1_NC_Pos (0UL) /*!< NC (Bit 0) */ + #define R_SYS_RBCR1_NC_Msk (0x7fffUL) /*!< NC (Bitfield-Mask: 0x7fff) */ +/* ========================================================= RBNR ================================================= */ + #define R_SYS_RBNR_BN_Pos (0UL) /*!< BN (Bit 0) */ + #define R_SYS_RBNR_BN_Msk (0x3fUL) /*!< BN (Bitfield-Mask: 0x3f) */ +/* ========================================================= RBIP ================================================= */ + #define R_SYS_RBIP_RBIP_Pos (4UL) /*!< RBIP (Bit 4) */ + #define R_SYS_RBIP_RBIP_Msk (0xfffffff0UL) /*!< RBIP (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= PID ================================================== */ + #define R_MPU_PID_MPU_Pos (8UL) /*!< MPU (Bit 8) */ + #define R_MPU_PID_MPU_Msk (0x100UL) /*!< MPU (Bitfield-Mask: 0x7f) */ + +/*@}*/ /* end of group RH850_G4KH_SYS */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_IRQ Interrupt Function Registers (IRQ) + * @brief Type definitions for the Interrupt Function Registers (IRQ) + * @{ + */ + +/** + * @brief Structure type to access the Interrupt Function Registers (SYS). + */ + +typedef union +{ + __IOM uint32_t ISPR; /*!< (@ 0x00000000) Priority of Interrupt being Serviced */ + + struct + { + __IM uint32_t ISP : 16; /*!< [15..0] These bits indicate the acknowledgment status of an + * EIINTn interrupt with apriority*1 that corresponds to the + * relevant bit position.0: An interrupt request for an interrupt + * whose priority corresponds to therelevant bit position + * has not been acknowledged.1: An interrupt request for an + * interrupt whose priority corresponds to therelevant position + * is being serviced by the CPU core. */ + uint32_t : 16; + } ISPR_b; +} RH850_IRQ_ISPR_Type; + +typedef union +{ + __IOM uint32_t ICSR; /*!< (@ 0x00000000) Interrupt Control Status */ + + struct + { + __IM uint32_t PMEI : 1; /*!< [0..0] This bit specifies the existence of EIINT whose acceptance + * is masked byISPR.ISP when INTCFG.EPL is cleared to 0 or + * PSW.EIMASK whenINTCFG.EPL is set to 1.0: EIINT masked by + * ISPR.ISP or PSW.EIMASK does not exist1: EIINT masked by + * ISPR.ISP or PSW.EIMASK exists */ + uint32_t : 31; + } ICSR_b; +} RH850_IRQ_ICSR_Type; + +typedef union +{ + __IOM uint32_t INTCFG; /*!< (@ 0x00000000) Interrupt Function Setting */ + + struct + { + __IOM uint32_t ISPC : 1; /*!< [0..0] This bit changes how the ISPR register is written.0: + * The ISPR register is automatically updated. Updates triggered + * by theprogram (via execution of LDSR instruction) are ignored.1: + * The ISPR register is not automatically updated. Updates + * triggered by theprogram (via execution of LDSR instruction) + * are performed. */ + __IOM uint32_t EPL : 1; /*!< [1..1] For the interrupt (EIINTn), specify whether to enable + * interrupt priority levelextension function.0: Interrupt + * priority level extension function is disabled1: Interrupt + * priority level extension function is enabled */ + uint32_t : 14; + __IOM uint32_t ULNR : 6; /*!< [21..16] Specifying the maximum value of available register + * bank numbers.If the value of the RBNR.BN is bigger than + * the ULNR, or the value of theRBNR.BN is 63; and the interrupt + * (EIINTn) whose register bank function isenable occurs, + * the SYSERR exception will occur. Note that the interrupt(EIINTn) + * is not accepted and is held. */ + uint32_t : 10; + } INTCFG_b; +} RH850_IRQ_INTCFG_Type; + +typedef union +{ + __IOM uint32_t PLMR; /*!< (@ 0x00000000) Interrupt Priority Level Mask */ + + struct + { + __IOM uint32_t PLM : 6; /*!< [5..0] These bits are used to mask the interrupts (EIINTn) whose + * priority level is nothigher than the level specified by + * these bits.When an interrupt (EIINTn) is masked by this + * register, it is not accepted. */ + uint32_t : 26; + } PLMR_b; +} RH850_IRQ_PLMR_Type; + +typedef union +{ + __IOM uint32_t EEIC; /*!< (@ 0x00000200) Extended EI Level Interrupt Control Register + * [0..31] */ + + struct + { + __IOM uint32_t EIP : 6; /*!< [5..0] These bits specify 64 interrupt priority levels (0: highest + * priority, 63: lowestpriority).If two or more EI level interrupt + * requests are generated simultaneously, a sourcewith higher + * priority specified by these bits is selected and is sent + * to the CPUcore. If the priority specified by these bits + * is equal, a source of less-numberchannel is selected as + * fixed priority. Please note that the interrupt (EIINTn) + * withpriority level 63 is not acknowledged in any case. + * For details, see Section3.2.4.1(5), Interrupt Ex */ + uint32_t : 9; + __IOM uint32_t EIOV : 1; /*!< [15..15] Interrupt Overflow0: No interrupt overflow1: EIINTn + * rose in edge-detection mode (mode_Eict[n] = 0) when EEICn.EIRF= + * 1.This bit is independent of write access to EEICn.EIRF. + * If EEICn.EIRF=1,EEICn.EIOVn=0, and 1 is written to EEICn.EIRF + * by 8-bit access, EEICn.EIOV isNOT set. */ + uint32_t : 6; + __IOM uint32_t EITB : 1; /*!< [22..22] Interrupt Vector Method Select0: Direct branching method + * based on priority1: Table referencing method */ + __IOM uint32_t EIMK : 1; /*!< [23..23] Interrupt MaskIf this bit is set to 1, interrupt requests + * set in the interrupt request flag (EIRFn)are masked to + * inhibit interrupt requests from the channel to the CPU + * core.Notification of presence of unprocessed interrupts + * is not made and the PMEI bitin ICSR is not set from channels + * for which this bit is set to 1.Even when the interrupt + * request from the channel is masked with EIMKn = 1,the EIRFn + * still reflects the interrupt request for the channel and + * can be polled insoftware. When the EIMKn bit is cleare */ + uint32_t : 4; + __IOM uint32_t EIRF : 1; /*!< [28..28] Interrupt Request FlagOperation varies with the interrupt + * input interface.0: No interrupt request (Initial value)1: + * Interrupt request present• Edge detectionThis flag is + * automatically cleared to 0 when an interrupt request of + * thechannel is accepted by the CPU core.• Level detectionThis + * bit cannot be set or cleared by the software. This is a + * read-only bit. */ + uint32_t : 2; + __IM uint32_t EICT : 1; /*!< [31..31] This bit indicates the type of an interrupt detection. + * This bit is read only.0: Detection with an edge1: Detection + * of the levelWritten value to this bit must be the value + * after reset. */ + } EEIC_b; +} RH850_IRQ_EEIC_Type; + +typedef union +{ + __IOM uint32_t EIBD; /*!< (@ 0x00000100) EI Level Interrupt Bind Register [0..31]These + * registers are provided for each EI level + * interrupt source to define binding between + * interruptsources and PEs. For details on + * each of the interrupt sources, see the Interrupt + * table. */ + + struct + { + __IM uint32_t PEID : 3; /*!< [2..0] These bits specify the interrupt bind (request) destination.These + * bits are fixed in EIBD0 to EIBD31 and cannot be modified.000: + * Interrupt is bound to PE0.001: Interrupt is bound to PE1.010: + * Interrupt is bound to PE2.011: Interrupt is bound to PE3.100: + * Interrupt is bound to PE4.101: Interrupt is bound to PE5. */ + uint32_t : 29; + } EIBD_b; +} RH850_IRQ_EIBD_INTC1_Type; + +typedef union +{ + __IOM uint32_t EIBD; /*!< (@ 0x00002000) EI Level Interrupt Bind Register [32..1023]These + * registers are provided for each EI level + * interrupt source to define binding between + * interruptsources and PEs. For details on + * each of the interrupt sources, see the Interrupt + * table. */ + + struct + { + __IOM uint32_t PEID : 3; /*!< [2..0] These bits specify the interrupt bind (request) destination.These + * bits are fixed in EIBD0 to EIBD31 and cannot be modified.000: + * Interrupt is bound to PE0.001: Interrupt is bound to PE1.010: + * Interrupt is bound to PE2.011: Interrupt is bound to PE3.100: + * Interrupt is bound to PE4.101: Interrupt is bound to PE5. */ + uint32_t : 29; + } EIBD_b; +} RH850_IRQ_EIBD_INTC2_Type; + +/** @brief Interrupt Function Registers macro Definitions */ +/* ================================================================================================================== */ +/* ================ R_IRQ ================ */ +/* ================================================================================================================== */ + +/* ========================================================= ISPR ================================================= */ + #define R_IRQ_ISPR_ISP_Pos (0UL) /*!< ISP (Bit 0) */ + #define R_IRQ_ISPR_ISP_Msk (0xffffUL) /*!< ISP (Bitfield-Mask: 0xffff) */ +/* ========================================================= ICSR ================================================= */ + #define R_IRQ_ICSR_PMEI_Pos (0UL) /*!< PMEI (Bit 0) */ + #define R_IRQ_ICSR_PMEI_Msk (0x1UL) /*!< PMEI (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCFG ================================================ */ + #define R_IRQ_INTCFG_ULNR_Pos (16UL) /*!< ULNR (Bit 16) */ + #define R_IRQ_INTCFG_ULNR_Msk (0x3f0000UL) /*!< ULNR (Bitfield-Mask: 0x3f) */ + #define R_IRQ_INTCFG_EPL_Pos (1UL) /*!< EPL (Bit 1) */ + #define R_IRQ_INTCFG_EPL_Msk (0x2UL) /*!< EPL (Bitfield-Mask: 0x01) */ + #define R_IRQ_INTCFG_ISPC_Pos (0UL) /*!< ISPC (Bit 0) */ + #define R_IRQ_INTCFG_ISPC_Msk (0x1UL) /*!< ISPC (Bitfield-Mask: 0x01) */ +/* ========================================================= PLMR ================================================= */ + #define R_IRQ_PLMR_PLM_Pos (0UL) /*!< PLM (Bit 0) */ + #define R_IRQ_PLMR_PLM_Msk (0x3fUL) /*!< PLM (Bitfield-Mask: 0x3f) */ +/* ========================================================= EEIC ================================================= */ + #define R_IRQ_EEIC_EICT_Pos (31UL) /*!< EICT (Bit 31) */ + #define R_IRQ_EEIC_EICT_Msk (0x80000000UL) /*!< EICT (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIRF_Pos (28UL) /*!< EIRF (Bit 28) */ + #define R_IRQ_EEIC_EIRF_Msk (0x10000000UL) /*!< EIRF (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIMK_Pos (23UL) /*!< EIMK (Bit 23) */ + #define R_IRQ_EEIC_EIMK_Msk (0x800000UL) /*!< EIMK (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EITB_Pos (22UL) /*!< EITB (Bit 22) */ + #define R_IRQ_EEIC_EITB_Msk (0x400000UL) /*!< EITB (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIOV_Pos (15UL) /*!< EIOV (Bit 15) */ + #define R_IRQ_EEIC_EIOV_Msk (0x8000UL) /*!< EIOV (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIP_Pos (0UL) /*!< EIP (Bit 0) */ + #define R_IRQ_EEIC_EIP_Msk (0x3fUL) /*!< EIP (Bitfield-Mask: 0x3f) */ +/* ========================================================= EIBD ================================================= */ + #define R_IRQ_INCT1_EIBD_PEID_Pos (0UL) /*!< PEID (Bit 0) */ + #define R_IRQ_INCT1_EIBD_PEID_Msk (0x7UL) /*!< PEID (Bitfield-Mask: 0x07) */ + +/*@}*/ /* end of group RH850_G4KH_IRQ */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_FPU FPU Function Registers (FPU) + * @brief Type definitions for the FPU Function Registers (FPU) + * @{ + */ + +/** + * @brief Structure type to access the FPU Function Registers (SYS). + */ + +typedef union +{ + __IOM uint32_t FPSR; /*!< (@ 0x00000000) Floating-point Configuration/Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are the preservation bits. */ + __IOM uint32_t XE : 5; /*!< [9..5] These are the enable bits. */ + __IOM uint32_t XC : 6; /*!< [15..10] These are the cause bits. */ + uint32_t : 1; + __IOM uint32_t FS : 1; /*!< [17..17] This bit enables values that could not be normalized + * (subnormal numbers) tobe flushed. If the FS bit is set, + * input operands and operation results that aresubnormal + * numbers are flushed without causing an unimplemented operationexception + * (E). An input operand that is a subnormal number is flushed + * to 0with the same sign. Operation results that are subnormal + * numbers eitherbecome 0 or the minimum normalized number, + * depending on the roundingmode. */ + __IOM uint32_t RM : 2; /*!< [19..18] These are the rounding mode control bits. The RM bits + * define the roundingmode that the FPU uses for all floating-point + * instructions. */ + uint32_t : 1; + __IOM uint32_t PEM : 1; /*!< [21..21] This bit specifies whether to handle an exception as + * a precise exception. If thePEM bit is 1, exceptions that + * are caused by the execution of a floating-pointoperation + * instruction are handled as precise exceptions. */ + __IOM uint32_t IF : 1; /*!< [22..22] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section 3.2.6.1(8), Flushing Subnormal + * Numbers. */ + __IOM uint32_t FN : 1; /*!< [23..23] This bit enables flush-to-nearest mode. When the FN + * bit is set to 1, if therounding mode is RN and the operation + * result is a subnormal number, thenumber is flushed to the + * nearest number. For details, see Section 3.2.6.1 (9),Flush + * to Nearest. */ + __IOM uint32_t CC : 8; /*!< [31..24] These are the CC (condition) bits. They store the results + * of floating-pointcomparison instructions. The CC7 to CC0 + * bits are not affected by anyinstructions except the comparison + * instruction and LDSR instruction.0: Comparison result is + * false1: Comparison result is true */ + } FPSR_b; +} RH850_FPU_FPSR_Type; + +typedef union +{ + __IOM uint32_t FPEPC; /*!< (@ 0x00000000) Floating-point Exception Program Counter */ + + struct + { + __IM uint32_t FPEPC0 : 1; /*!< [0..0] This bit stores the program counter (PC) of the floating-point + * instruction thatcaused the exception when a floating-point + * operation exception that isenabled by an enable bit occurs. */ + uint32_t : 30; + __IOM uint32_t FPEPC : 1; /*!< [31..31] These bits store the program counter (PC) of the floating-point + * instruction thatcaused the exception when a floating-point + * operation exception that isenabled by an enable bit occurs. */ + } FPEPC_b; +} RH850_FPU_FPEPC_Type; + +typedef union +{ + __IOM uint32_t FPST; /*!< (@ 0x00000000) Floating-point Operation Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are preservation bits. For details, see Section + * 3.2.3.4(1),Preservation Bits (XP). Values written to these + * bits are reflected inFPSR.XP bits. */ + __IOM uint32_t IF : 1; /*!< [5..5] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section3.2.6.1 (8), Flushing Subnormal + * Numbers. Value written to this bit isreflected in FPSR.IF + * bit. */ + uint32_t : 2; + __IOM uint32_t XC : 6; /*!< [13..8] These are cause bits. For details, see Section 3.2.3.4(1), + * Cause Bits (XC).Values written to these bits are reflected + * in FPSR.XC bits. */ + uint32_t : 18; + } FPST_b; +} RH850_FPU_FPST_Type; + +typedef union +{ + __IOM uint32_t FPCC; /*!< (@ 0x00000000) Floating-point Operation Comparison Result */ + + struct + { + __IOM uint32_t CC : 8; /*!< [7..0] These are CC (condition) bits. They store the result + * of a floating-pointcomparison instruction. The CC7 to CC0 + * bits are not affected by anyinstructions except the comparison + * instruction and LDSR instruction. Valueswritten to these + * bits are reflected in the CC7 to CC0 bits of FPSR.0: Comparison + * result is false1: Comparison result is true */ + uint32_t : 24; + } FPCC_b; +} RH850_FPU_FPCC_Type; + +typedef union +{ + __IOM uint32_t FPCFG; /*!< (@ 0x00000000) Floating-point Operation Configuration */ + + struct + { + __IOM uint32_t XE : 5; /*!< [4..0] These are the enable bits. For details, see Section 3.2.3.4(1), + * Enable Bits(XE). Values written to these bits are reflected + * in the FPSR.XE bits */ + uint32_t : 3; + __IOM uint32_t RM : 2; /*!< [9..8] These are rounding mode control bits. The RM bits define + * the rounding modethat the FPU uses for all floating-point + * instructions. Values written to these bitsare reflected + * in RM bits of FPSR. */ + uint32_t : 22; + } FPCFG_b; +} RH850_FPU_FPCFG_Type; + +typedef union +{ + __IOM uint32_t FPEC; /*!< (@ 0x00000000) Floating-point Exception Program Counter */ + + struct + { + __IM uint32_t FPEC : 1; /*!< [0..0] This bit indicates the status of reporting the FPl exception. + * If this bit is set to 1, the FPl exception is reported to the CPU but is not + * acknowledged. It is automatically cleared to 0 when the CPU acknowledges + * the FPl exception. + * While this bit is set to 1, all the floating-point instructions are invalidated. + * Report of the FPl exception can be canceled by clearing (0) this bit by the + * LDSR instruction while it is set to 1. When report of the FPl exception is + * canceled, the CPU does not acknowledge the FPl exception. + * 0. FPl exception is not reported. + * 1: FPl exception is reported.. */ + uint32_t : 31; + } FPEC_b; +} RH850_FPU_FPEC_Type; + +/** @brief FPU Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_FPU ================ */ +/* ================================================================================================================== */ + +/* ========================================================= FPSR ================================================= */ + #define R_FPU_FPSR_CC_Pos (24UL) /*!< CC (Bit 24) */ + #define R_FPU_FPSR_CC_Msk (0xff000000UL) /*!< CC (Bitfield-Mask: 0xff) */ + #define R_FPU_FPSR_FN_Pos (23UL) /*!< FN (Bit 23) */ + #define R_FPU_FPSR_FN_Msk (0x800000UL) /*!< FN (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_IF_Pos (22UL) /*!< IF (Bit 22) */ + #define R_FPU_FPSR_IF_Msk (0x400000UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_PEM_Pos (21UL) /*!< PEM (Bit 21) */ + #define R_FPU_FPSR_PEM_Msk (0x200000UL) /*!< PEM (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_RM_Pos (18UL) /*!< RM (Bit 18) */ + #define R_FPU_FPSR_RM_Msk (0xc0000UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FPU_FPSR_FS_Pos (17UL) /*!< FS (Bit 17) */ + #define R_FPU_FPSR_FS_Msk (0x20000UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_XC_Pos (10UL) /*!< XC (Bit 10) */ + #define R_FPU_FPSR_XC_Msk (0xfc00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FPU_FPSR_XE_Pos (5UL) /*!< XE (Bit 5) */ + #define R_FPU_FPSR_XE_Msk (0x3e0UL) /*!< XE (Bitfield-Mask: 0x1f) */ + #define R_FPU_FPSR_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FPU_FPSR_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ========================================================= FPEPC ================================================ */ + #define R_FPU_FPEPC_FPEPC_Pos (31UL) /*!< FPEPC (Bit 31) */ + #define R_FPU_FPEPC_FPEPC_Msk (0x80000000UL) /*!< FPEPC (Bitfield-Mask: 0x01) */ + #define R_FPU_FPEPC_FPEPC0_Pos (0UL) /*!< FPEPC0 (Bit 0) */ + #define R_FPU_FPEPC_FPEPC0_Msk (0x1UL) /*!< FPEPC0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FPST ================================================= */ + #define R_FPU_FPST_XC_Pos (8UL) /*!< XC (Bit 8) */ + #define R_FPU_FPST_XC_Msk (0x3f00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FPU_FPST_IF_Pos (5UL) /*!< IF (Bit 5) */ + #define R_FPU_FPST_IF_Msk (0x20UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FPU_FPST_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FPU_FPST_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ========================================================= FPCC ================================================= */ + #define R_FPU_FPCC_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_FPU_FPCC_CC_Msk (0xffUL) /*!< CC (Bitfield-Mask: 0xff) */ +/* ========================================================= FPCFG ================================================ */ + #define R_FPU_FPCFG_RM_Pos (8UL) /*!< RM (Bit 8) */ + #define R_FPU_FPCFG_RM_Msk (0x300UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FPU_FPCFG_XE_Pos (0UL) /*!< XE (Bit 0) */ + #define R_FPU_FPCFG_XE_Msk (0x1fUL) /*!< XE (Bitfield-Mask: 0x1f) */ +/* ========================================================= FPEC ================================================ */ + #define R_FPU_FPEC_FPIVD_Pos (0UL) /*!< FPIVD (Bit 0) */ + #define R_FPU_FPEC_FPIVD_Msk (0x1UL) /*!< FPIVD (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4KH_FPU */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_MPU MPU Function Registers (MPU) + * @brief Type definitions for the MPU Function Registers (MPU) + * @{ + */ + +/** + * @brief Structure type to access the MPU Function Registers (MPU). + */ + +typedef union +{ + __IOM uint32_t MPM; /*!< (@ 0x00000000) Memory Protection Operation Mode */ + + struct + { + __IOM uint32_t MPE : 1; /*!< [0..0] This bit indicates that 32 128-bit vector registers are + * provided. */ + __IOM uint32_t SVP : 1; /*!< [1..1] This bit indicates that 4-way SIMD arithmetic unit is + * provided. */ + uint32_t : 30; + } MPM_b; +} RH850_MPU_MPM_Type; + +typedef union +{ + __IOM uint32_t MPCFG; /*!< (@ 0x00000000) MPU Configuration */ + + struct + { + __IM uint32_t NMPUE : 5; /*!< [4..0] These bits indicate the number of MPU entries implemented + * in this CPUminus 1. A value of 31 is read since this CPU + * incorporates 32 MPUentries. */ + uint32_t : 11; + __IM uint32_t ARCH : 4; /*!< [19..16] These bits hold the cause bits associated with operation + * way 1. */ + __IM uint32_t NBK : 2; /*!< [21..20] Indicates the "number of banks - 1" of the MPU bank + * 2 equipped in thisCPU.Since the MPU bank of this CPU is + * equipped with one bank, 0 is read. */ + uint32_t : 10; + } MPCFG_b; +} RH850_MPU_MPCFG_Type; + +typedef union +{ + __IOM uint32_t MCA; /*!< (@ 0x00000000) Memory Protection Setting Check Address */ + + struct + { + __IOM uint32_t MCA : 32; /*!< [31..0] These bits are used to specify the starting address + * of the memory areawhich subjects to a memory protection + * setting check in bytes. */ + } MCA_b; +} RH850_MPU_MCA_Type; + +typedef union +{ + __IOM uint32_t MCS; /*!< (@ 0x00000000) Memory Protection Setting Check Size */ + + struct + { + __IOM uint32_t MCS : 32; /*!< [31..0] These bits are used to specify the size of the memory + * area in bytes whichsubjects to a memory protection setting + * check. Because the specified sizeis assumed to represent + * an unsigned integer, it is not possible to check anarea + * in the direction in which the address value decreases relative + * to theMCA register value. */ + } MCS_b; +} RH850_MPU_MCS_Type; + +typedef union +{ + __IOM uint32_t MCC; /*!< (@ 0x00000000) Memory Protection Setting Check Command */ + + struct + { + __IOM uint32_t MCC : 32; /*!< [31..0] When any value is written to the MCC register, a memory + * protection settingcheck starts. By setting up the MCA / + * MCS register and then writing to theMCC register, results + * are stored in MCR. Because the check is started by anywritten + * value, a check can be started by using r0 as the source + * register withoutusing any unnecessary registers.Note that, + * for the check, the results are applied according to each + * area settingregardless of the state of the PSW.UM bit.This + * checking applies for memory protec */ + } MCC_b; +} RH850_MPU_MCC_Type; + +typedef union +{ + __IOM uint32_t MCR; /*!< (@ 0x00000000) Memory Protection Setting Check Result */ + + struct + { + __IOM uint32_t URE : 1; /*!< [0..0] If the specified area is contained within one protection + * area and reading fromthat area is permitted in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t UWE : 1; /*!< [1..1] If the specified area is contained within one protection + * area and writing fromthat area is permitted in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t UXE : 1; /*!< [2..2] If the specified area is contained within one protection + * area and execution ispermitted for that area in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t SRE : 1; /*!< [3..3] If the specified area is contained within one protection + * area and reading fromthat area is permitted in supervisor + * mode, 1 is stored in this bit. In other cases,0 is stored + * in this bit. */ + __IOM uint32_t SWE : 1; /*!< [4..4] If the specified area is contained within one protection + * area and writing to thatarea is permitted in supervisor + * mode, 1 is stored in this bit. In other cases, 0 isstored + * in this bit. */ + __IOM uint32_t SXE : 1; /*!< [5..5] If the specified area is contained within one protection + * area and execution ispermitted for that area in supervisor + * mode, 1 is stored in this bit. In othercases, 0 is stored + * in this bit. */ + uint32_t : 2; + __IOM uint32_t OV : 1; /*!< [8..8] If the specified area includes 0000 0000H or 7FFF FFFFH, + * 1 is stored in thisbit. In other cases, 0 is stored in + * this bit. */ + uint32_t : 23; + } MCR_b; +} RH850_MPU_MCR_Type; + +typedef union +{ + __IOM uint32_t MCI; /*!< (@ 0x00000000) Memory Protection Setting Check SPID */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 27; + } MCI_b; +} RH850_MPU_MCI_Type; + +typedef union +{ + __IOM uint32_t MPIDX; /*!< (@ 0x00000000) Index of Memory Protection Setting Registers + * to be Accessed */ + + struct + { + __IOM uint32_t IDX : 5; /*!< [4..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 27; + } MPIDX_b; +} RH850_MPU_MPIDX_type; + +typedef union +{ + __IOM uint32_t MPBK; /*!< (@ 0x00000000) MPU Bank Setting */ + + struct + { + __IOM uint32_t BK : 2; /*!< [1..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 30; + } MPBK_b; +} RH850_MPU_MPBK_Type; + +typedef union +{ + __IOM uint32_t MPLA; /*!< (@ 0x00000000) Base Address of the Interrupt Handler Address + * Table */ + + struct + { + uint32_t : 2; + __IOM uint32_t MPLA : 30; /*!< [31..2] These bits specify the minimum address of area n (n + * = 0 to MPCFG.NMPUE)specified by the MPIDX register.The + * specified minimum address is included in the range of area + * matching. */ + } MPLA_b; +} RH850_MPU_MPLA_Type; + +typedef union +{ + __IOM uint32_t MPUA; /*!< (@ 0x00000000) Protection Area Maximum Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t MPUA : 30; /*!< [31..2] These bits specify the maximum address of area n (n + * = 0 to MPCFG.NMPUE)specified by the MPIDX register.The + * specified maximum address is included in the range of area + * matching.Bits 1 and 0 of the maximum address are handled + * as 1. */ + } MPUA_b; +} RH850_MPU_MPUA_Type; + +typedef union +{ + __IOM uint32_t MPAT; /*!< (@ 0x00000000) Protection Area Attribute */ + + struct + { + __IOM uint32_t UR : 1; /*!< [0..0] This bit indicates the read permission in the user mode + * for area n (n = 0 toMPCFG.NMPUE) specified by the MPIDX + * register.*20: Reading is disabled.1: Reading is enabled. */ + __IOM uint32_t UW : 1; /*!< [1..1] This bit indicates the write permission in the user mode + * for area n (n = 0 toMPCFG.NMPUE) specified by the MPIDX + * register.0: Writing is disabled.1: Writing is enabled. */ + __IOM uint32_t UX : 1; /*!< [2..2] This bit indicates the execution permission in the user + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.0: Execution is disabled.1: Execution is + * enabled. */ + __IOM uint32_t SR : 1; /*!< [3..3] This bit indicates the read permission in the supervisor + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.*1, *20: Reading is disabled.1: Reading + * is enabled. */ + __IOM uint32_t SW : 1; /*!< [4..4] This bit indicates the write permission in the supervisor + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.*10: Writing is disabled.1: Writing is enabled. */ + __IOM uint32_t SX : 1; /*!< [5..5] This bit indicates the execution permission in the supervisor + * mode for area n(n = 0 to MPCFG.NMPUE) specified by the + * MPIDX register.*10: Execution is disabled.1: Execution + * is enabled. */ + uint32_t : 1; + __IOM uint32_t E : 1; /*!< [7..7] This bit indicates whether area n (n = 0 to MPCFG.NMPUE) + * specified by theMPIDX register is enabled or disabled.0: + * Area n is disabled.1: Area n is enabled. */ + uint32_t : 6; + __IOM uint32_t RG : 1; /*!< [14..14] This bit indicates the execution and read permissions + * for any SPID.0: Execution and reading is enabled by the + * settings of the MPIDn registerand RMPIDn bit (n = 0 to + * 7).1: Execution and reading by any SPID is enabled regardless + * of the settingsof the MPIDn register and RMPIDn bit (n + * = 0 to 7). */ + __IOM uint32_t WG : 1; /*!< [15..15] This bit indicates the write permission for any SPID.0: + * Writing is enabled by the settings of the MPIDn register + * and WMPIDn bit(n = 0 to 7).1: Writing by any SPID is enabled + * regardless of the settings of the MPIDnregister and WMPIDn + * bit (n = 0 to 7). */ + __IOM uint32_t RMPID : 8; /*!< [23..16] This bit indicates the execution and read permissions + * for the SPID specified inthe MPIDn (n = 0 to 7) register.0: + * Execution and reading by the SPID specified by the MPIDn + * register isdisabled.1: Execution and reading by the SPID + * specified by the MPIDn register isenabled. */ + __IOM uint32_t WMPID : 8; /*!< [31..24] This bit indicates the write permission for the SPID + * specified in the MPIDn (n =0 to 7) register.0: Writing + * by the SPID specified by the MPIDn register is disabled.1: + * Writing by the SPID specified by the MPIDn register is + * enabled. */ + } MPAT_b; +} RH850_MPU_MPAT_Type; + +typedef union +{ + __IOM uint32_t MPID; /*!< (@ 0x00000000) SPID which can Access Protection Area */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits specify the SPID which can access protection + * area. */ + uint32_t : 27; + } MPID_b; +} RH850_MPU_MPID_Type; + +/** @brief MPU Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_MPU ================ */ +/* ================================================================================================================== */ + +/* ========================================================== MPM ================================================= */ + #define R_MPU_MPM_SVP_Pos (1UL) /*!< SVP (Bit 1) */ + #define R_MPU_MPM_SVP_Msk (0x2UL) /*!< SVP (Bitfield-Mask: 0x01) */ + #define R_MPU_MPM_MPE_Pos (0UL) /*!< MPE (Bit 0) */ + #define R_MPU_MPM_MPE_Msk (0x1UL) /*!< MPE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCFG ================================================ */ + #define R_MPU_MPCFG_NBK_Pos (20UL) /*!< NBK (Bit 20) */ + #define R_MPU_MPCFG_NBK_Msk (0x300000UL) /*!< NBK (Bitfield-Mask: 0x03) */ + #define R_MPU_MPCFG_ARCH_Pos (16UL) /*!< ARCH (Bit 16) */ + #define R_MPU_MPCFG_ARCH_Msk (0xf0000UL) /*!< ARCH (Bitfield-Mask: 0x0f) */ + #define R_MPU_MPCFG_NMPUE_Pos (0UL) /*!< NMPUE (Bit 0) */ + #define R_MPU_MPCFG_NMPUE_Msk (0x1fUL) /*!< NMPUE (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCA ================================================= */ + #define R_MPU_MCA_MCA_Pos (0UL) /*!< MCA (Bit 0) */ + #define R_MPU_MCA_MCA_Msk (0xffffffffUL) /*!< MCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCS ================================================= */ + #define R_MPU_MCS_MCS_Pos (0UL) /*!< MCS (Bit 0) */ + #define R_MPU_MCS_MCS_Msk (0xffffffffUL) /*!< MCS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCC ================================================= */ + #define R_MPU_MCC_MCC_Pos (0UL) /*!< MCC (Bit 0) */ + #define R_MPU_MCC_MCC_Msk (0xffffffffUL) /*!< MCC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ================================================= */ + #define R_MPU_MCR_OV_Pos (8UL) /*!< OV (Bit 8) */ + #define R_MPU_MCR_OV_Msk (0x100UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SXE_Pos (5UL) /*!< SXE (Bit 5) */ + #define R_MPU_MCR_SXE_Msk (0x20UL) /*!< SXE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SWE_Pos (4UL) /*!< SWE (Bit 4) */ + #define R_MPU_MCR_SWE_Msk (0x10UL) /*!< SWE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SRE_Pos (3UL) /*!< SRE (Bit 3) */ + #define R_MPU_MCR_SRE_Msk (0x8UL) /*!< SRE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_UXE_Pos (2UL) /*!< UXE (Bit 2) */ + #define R_MPU_MCR_UXE_Msk (0x4UL) /*!< UXE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_UWE_Pos (1UL) /*!< UWE (Bit 1) */ + #define R_MPU_MCR_UWE_Msk (0x2UL) /*!< UWE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_URE_Pos (0UL) /*!< URE (Bit 0) */ + #define R_MPU_MCR_URE_Msk (0x1UL) /*!< URE (Bitfield-Mask: 0x01) */ +/* ========================================================== MCI ================================================= */ + #define R_MPU_MCI_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MCI_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPIDX ================================================ */ + #define R_MPU_MPIDX_IDX_Pos (0UL) /*!< IDX (Bit 0) */ + #define R_MPU_MPIDX_IDX_Msk (0x1fUL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPBK ================================================= */ + #define R_MPU_MPBK_BK_Pos (0UL) /*!< BK (Bit 0) */ + #define R_MPU_MPBK_BK_Msk (0x3UL) /*!< BK (Bitfield-Mask: 0x03) */ +/* ========================================================= MPLA ================================================= */ + #define R_MPU_MPLA_MPLA_Pos (2UL) /*!< MPLA (Bit 2) */ + #define R_MPU_MPLA_MPLA_Msk (0xfffffffcUL) /*!< MPLA (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= MPUA ==================== ============================ */ + #define R_MPU_MPUA_MPUA_Pos (2UL) /*!< MPUA (Bit 2) */ + #define R_MPU_MPUA_MPUA_Msk (0xfffffffcUL) /*!< MPUA (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= MPAT ================================================= */ + #define R_MPU_MPAT_WMPID_Pos (24UL) /*!< WMPID (Bit 24) */ + #define R_MPU_MPAT_WMPID_Msk (0xff000000UL) /*!< WMPID (Bitfield-Mask: 0xff) */ + #define R_MPU_MPAT_RMPID_Pos (16UL) /*!< RMPID (Bit 16) */ + #define R_MPU_MPAT_RMPID_Msk (0xff0000UL) /*!< RMPID (Bitfield-Mask: 0xff) */ + #define R_MPU_MPAT_WG_Pos (15UL) /*!< WG (Bit 15) */ + #define R_MPU_MPAT_WG_Msk (0x8000UL) /*!< WG (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_RG_Pos (14UL) /*!< RG (Bit 14) */ + #define R_MPU_MPAT_RG_Msk (0x4000UL) /*!< RG (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_E_Pos (7UL) /*!< E (Bit 7) */ + #define R_MPU_MPAT_E_Msk (0x80UL) /*!< E (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SX_Pos (5UL) /*!< SX (Bit 5) */ + #define R_MPU_MPAT_SX_Msk (0x20UL) /*!< SX (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SW_Pos (4UL) /*!< SW (Bit 4) */ + #define R_MPU_MPAT_SW_Msk (0x10UL) /*!< SW (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SR_Pos (3UL) /*!< SR (Bit 3) */ + #define R_MPU_MPAT_SR_Msk (0x8UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UX_Pos (2UL) /*!< UX (Bit 2) */ + #define R_MPU_MPAT_UX_Msk (0x4UL) /*!< UX (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UW_Pos (1UL) /*!< UW (Bit 1) */ + #define R_MPU_MPAT_UW_Msk (0x2UL) /*!< UW (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UR_Pos (0UL) /*!< UR (Bit 0) */ + #define R_MPU_MPAT_UR_Msk (0x1UL) /*!< UR (Bitfield-Mask: 0x01) */ +/* ========================================================= MPID0 ================================================ */ + #define R_MPU_MPID0_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID0_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID1 ================================================ */ + #define R_MPU_MPID1_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID1_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID2 ================================================ */ + #define R_MPU_MPID2_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID2_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID3 ================================================ */ + #define R_MPU_MPID3_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID3_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID4 ================================================ */ + #define R_MPU_MPID4_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID4_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID5 ================================================ */ + #define R_MPU_MPID5_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID5_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID6 ================================================ */ + #define R_MPU_MPID6_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID6_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID7 ================================================ */ + #define R_MPU_MPID7_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID7_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ + +/*@}*/ /* end of group RH850_G4KH_MPU */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_ICACHE Cache Operation Function Registers (ICACHE) + * @brief Type definitions for the Cache Operation Function Registers (ICACHE) + * @{ + */ + +/** + * @brief Structure type to access the Cache Operation Function Registers (ICACHE). + */ + +typedef union +{ + __IOM uint32_t ICTAGL; /*!< (@ 0x00000000) Instruction Cache Tag Lo Access */ + + struct + { + __IOM uint32_t V : 1; /*!< [0..0] This bit holds valid/invalid information of specified + * cache line.*30: The cache line is disabled.1: The cache + * line is enabled. */ + uint32_t : 1; + __IOM uint32_t L : 1; /*!< [2..2] This bit holds the lock information.*30: The cache line + * is not locked.1: The cache line is locked. */ + uint32_t : 1; + __IOM uint32_t LRU : 2; /*!< [5..4] These bits indicate LRU information of specified cache + * line. LRU informationcannot be freely changed to any value + * by the CIST instruction */ + uint32_t : 5; + __IOM uint32_t LPN : 21; /*!< [31..11] These bits hold address bits 27 to 11. Bits 31 to 28 + * must always be set to 0.Bits 27 to 11 are held if the cache + * size is 8 Kbytes.Bits 27 to 12 are held and bit 11 is always + * set to 0 if the cache size is 16Kbytes.*1Bits 27 to 13 + * are held and bit 12 and 11 are always set to 0 if the cache + * size is32 KBytes.*2 */ + } ICTAGL_b; +} RH850_ICACHE_ICTAGL_Type; + +typedef union +{ + __IOM uint32_t ICTAGH; /*!< (@ 0x00000000) Instruction Cache Tag Hi Access */ + + struct + { + uint32_t : 8; + __IOM uint32_t TAGECC : 8; /*!< [15..8] These bits hold ECC for tag RAM. Bit 15 is fixed to + * 0 */ + __IOM uint32_t DATAECC : 8; /*!< [23..16] These bits hold ECC for data RAM. */ + uint32_t : 4; + __IOM uint32_t PT : 1; /*!< [28..28] This bit specifies the data to be written to the ECC + * of the tag RAM when theWT bit is set to 1 and the CIST + * instruction is executed.0: ECC automatically generated + * from the write data is written to the ECC ofthe tag RAM.1: + * Values in the TAGECC field are written to the ECC of the + * tag RAM. */ + __IOM uint32_t WT : 1; /*!< [29..29] This bit specifies whether the tag RAM of the cache + * is updated duringexecution of the CIST instruction. When + * this bit is set to 1, the V bit and L bit ofthe cache line + * are also updated.0: Tag RAM of the cache is not updated.1: + * Tag RAM of the cache is updated. */ + __IOM uint32_t PD : 1; /*!< [30..30] This bit specifies the data to be written to the ECC + * of the data RAM when theWD bit is set to 1 and the CIST + * instruction is executed.0: ECC automatically generated + * from the write data is written to the ECC ofthe data RAM.1: + * Values in the DATAECC field are written to the ECC of the + * data RAM. */ + __IOM uint32_t WD : 1; /*!< [31..31] This bit specifies whether the data RAM of the cache + * is updated duringexecution of the CIST instruction.0: Data + * RAM of the cache is not updated.1: Data RAM of the cache + * is updated. */ + } ICTAGH_b; +} RH850_ICACHE_ICTAGH_type; + +typedef union +{ + __IOM uint32_t ICDATL; /*!< (@ 0x00000000) Instruction Cache Data Lo Access */ + + struct + { + __IOM uint32_t DATAL : 32; /*!< [31..0] These bits hold the lower-order 32 bits of the 64-bit + * instruction data*1 in theblock in the specified cache line. + * The bits to be held is specified by offset of theindex.*2Offset + * of index = 00: Bits 31 to 0*3Offset of index = 01: Bits + * 95 to 64*3Offset of index = 10: Bits 159 to 128*3Offset + * of index = 11: Bits 223 to 192*3 */ + } ICDATL_b; +} RH850_ICACHE_ICDATL_Type; + +typedef union +{ + __IOM uint32_t ICDATH; /*!< (@ 0x00000000) Instruction Cache Data Hi Access */ + + struct + { + __IOM uint32_t DATAH : 32; /*!< [31..0] These bits hold the upper-order 32 bits of the 64-bit + * instruction data*1 in theblock in the specified cache line. + * The bits to be held is specified by offset of theindex.*2Offset + * of index = 00: Bits 63 to 32*3Offset of index = 01: Bits + * 127 to 96*3Offset of index = 10: Bits 191 to 160*3Offset + * of index = 11: Bits 255 to 224*3 */ + } ICDATH_b; +} RH850_ICACHE_ICDATH_Type; + +typedef union +{ + __IOM uint32_t ICCTRL; /*!< (@ 0x00000000) Instruction Cache Control */ + + struct + { + __IOM uint32_t ICHEN : 1; /*!< [0..0] This bit indicates valid/invalid status of instruction + * cache.0: Instruction cache is invalid1: Instruction cache + * is valid */ + __IOM uint32_t ICHEMK : 1; /*!< [1..1] When this bit is set to 1, it masks notification of cache + * error exceptions forthe CPU after a cache error*2 has occurred. */ + __IOM uint32_t ICHEIV : 1; /*!< [2..2] When this bit is set to 1, the instruction cache is automatically + * set asinvalid (the ICHEN bit is cleared to 0) whenever + * a cache error*2 occurs. */ + uint32_t : 5; + __IOM uint32_t ICHCLR : 1; /*!< [8..8] When this bit is set to 1, the entire instruction cache + * is cleared. This clearsthe V and L bits (to 0) and initializes + * the LRU information. This bit isalways read as 0. */ + uint32_t : 23; + } ICCTRL_b; +} RH850_ICACHE_ICCTRL_Type; + +typedef union +{ + __IOM uint32_t ICCFG; /*!< (@ 0x00000000) Instruction Cache Configuration */ + + struct + { + __IM uint32_t ICHWAY : 4; /*!< [3..0] These bits indicate the number of ways in the instruction + * cache.0100: 4 waysOther than above: Setting prohibited */ + __IM uint32_t ICHLINE : 4; /*!< [7..4] These bits indicate the number of lines for each way + * in the instruction cache.0010: 64 lines0100: 128 lines1000: + * 256 linesOther than above: Setting prohibited */ + __IM uint32_t ICHSIZE : 7; /*!< [14..8] These bits indicate the size (in Kbytes) of the instruction + * cache.000 1000: 8 Kbytes001 0000: 16 Kbytes010 0000: 32 + * KbytesOther than above: Setting prohibited */ + uint32_t : 17; + } ICCFG_b; +} RH850_ICACHE_ICCFG_Type; + +typedef union +{ + __IOM uint32_t ICERR; /*!< (@ 0x00000000) Instruction Cache Error */ + + struct + { + __IOM uint32_t ICHERR : 1; /*!< [0..0] This bit is set to 1 when a cache error has occurred. */ + uint32_t : 1; + __IOM uint32_t ICHET : 1; /*!< [2..2] This bit indicates that an error has occurred in tag + * RAM. */ + __IOM uint32_t ICHED : 1; /*!< [3..3] This bit indicates that an error has occurred in data + * RAM. */ + __IOM uint32_t ICHERQ : 1; /*!< [4..4] When this bit is set to 1, this bit indicates that cache + * error exceptionnotification is in progress. However, if + * cache error exception notification hasbeen masked, the + * CPU is not notified even when 1 has been set to this bit. */ + __IOM uint32_t ICHEIX : 8; /*!< [12..5] These bits hold the cache index where a cache error + * occurred.Bits 10 to 5 are held and bits 12 and 11 are fixed + * to 0 for a cache size of 8Kbytes.*1Bits 11 to 5 are held + * and bit 12 is fixed to 0 for a cache size of 16 Kbytes.*2Bits + * 12 to 5 are held for cache size of 32 Kbytes. */ + __IOM uint32_t ICHEWY : 3; /*!< [15..13] These bits hold the way number where a cache error + * occurred. Bit 15 isalways set to 0. */ + __IOM uint32_t ERMDE : 1; /*!< [16..16] Error exception notification mask: Data RAM 2-bits + * error*3 */ + __IOM uint32_t ERMDC : 1; /*!< [17..17] Error exception notification mask: Data RAM 1-bit error*3 */ + __IOM uint32_t ERMTE2 : 1; /*!< [18..18] Error exception notification mask: Tag RAM 2-bits error*3 */ + __IOM uint32_t ERMTE1 : 1; /*!< [19..19] Error exception notification mask: Tag RAM 1-bit error*3 */ + __IOM uint32_t ERMPBSE : 1; /*!< [20..20] Error exception notification mask: WAY error*3 */ + __IOM uint32_t ERMMH : 1; /*!< [21..21] Error exception notification mask: Multi hit*3 */ + __IOM uint32_t ERMAFE : 1; /*!< [22..22] Error exception notification mask: Address feedback + * error*3 */ + uint32_t : 1; + __IOM uint32_t ESDE : 1; /*!< [24..24] Error status: Data RAM 2-bits error */ + __IOM uint32_t ESDC : 1; /*!< [25..25] Error status: Data RAM 1-bit error */ + __IOM uint32_t ESTE2 : 1; /*!< [26..26] Error status: Tag RAM 2-bits error */ + __IOM uint32_t ESTE1 : 1; /*!< [27..27] Error status: Tag RAM 1-bit error */ + __IOM uint32_t ESPBSE : 1; /*!< [28..28] Error status: WAY error */ + __IOM uint32_t ESMH : 1; /*!< [29..29] Error status: Multi hit */ + __IOM uint32_t ESAFE : 1; /*!< [30..30] Error status: Address feedback error */ + __IOM uint32_t CISTW : 1; /*!< [31..31] This bit is set to indicate that the destination way + * specified for a CISTIinstruction was in error. Although + * the entry information is overwritten so thatwriting is + * completed, the V bit will be cleared the next time the + * cache line isread (i.e. reading will be judged to have + * missed the cache). However, settingof this bit is not accompanied + * by an exception for the CPU. */ + } ICERR_b; +} RH850_ICACHE_ICERR_Type; + +/** @brief Cache Operation Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_ICACHE ================ */ +/* ================================================================================================================== */ + +/* ======================================================== ICTAGL ================================================ */ + #define R_ICACHE_ICTAGL_LPN_Pos (11UL) /*!< LPN (Bit 11) */ + #define R_ICACHE_ICTAGL_LPN_Msk (0xfffff800UL) /*!< LPN (Bitfield-Mask: 0x1fffff) */ + #define R_ICACHE_ICTAGL_LRU_Pos (4UL) /*!< LRU (Bit 4) */ + #define R_ICACHE_ICTAGL_LRU_Msk (0x30UL) /*!< LRU (Bitfield-Mask: 0x03) */ + #define R_ICACHE_ICTAGL_L_Pos (2UL) /*!< L (Bit 2) */ + #define R_ICACHE_ICTAGL_L_Msk (0x4UL) /*!< L (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGL_V_Pos (0UL) /*!< V (Bit 0) */ + #define R_ICACHE_ICTAGL_V_Msk (0x1UL) /*!< V (Bitfield-Mask: 0x01) */ +/* ======================================================== ICTAGH ================================================ */ + #define R_ICACHE_ICTAGH_WD_Pos (31UL) /*!< WD (Bit 31) */ + #define R_ICACHE_ICTAGH_WD_Msk (0x80000000UL) /*!< WD (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_PD_Pos (30UL) /*!< PD (Bit 30) */ + #define R_ICACHE_ICTAGH_PD_Msk (0x40000000UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_WT_Pos (29UL) /*!< WT (Bit 29) */ + #define R_ICACHE_ICTAGH_WT_Msk (0x20000000UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_PT_Pos (28UL) /*!< PT (Bit 28) */ + #define R_ICACHE_ICTAGH_PT_Msk (0x10000000UL) /*!< PT (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_DATAECC_Pos (16UL) /*!< DATAECC (Bit 16) */ + #define R_ICACHE_ICTAGH_DATAECC_Msk (0xff0000UL) /*!< DATAECC (Bitfield-Mask: 0xff) */ + #define R_ICACHE_ICTAGH_TAGECC_Pos (8UL) /*!< TAGECC (Bit 8) */ + #define R_ICACHE_ICTAGH_TAGECC_Msk (0xff00UL) /*!< TAGECC (Bitfield-Mask: 0xff) */ +/* ======================================================== ICDATL ================================================ */ + #define R_ICACHE_ICDATL_DATAL_Pos (0UL) /*!< DATAL (Bit 0) */ + #define R_ICACHE_ICDATL_DATAL_Msk (0xffffffffUL) /*!< DATAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICDATH ================================================ */ + #define R_ICACHE_ICDATH_DATAH_Pos (0UL) /*!< DATAH (Bit 0) */ + #define R_ICACHE_ICDATH_DATAH_Msk (0xffffffffUL) /*!< DATAH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICCTRL ================================================ */ + #define R_ICACHE_ICCTRL_ICHCLR_Pos (8UL) /*!< ICHCLR (Bit 8) */ + #define R_ICACHE_ICCTRL_ICHCLR_Msk (0x100UL) /*!< ICHCLR (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEIV_Pos (2UL) /*!< ICHEIV (Bit 2) */ + #define R_ICACHE_ICCTRL_ICHEIV_Msk (0x4UL) /*!< ICHEIV (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEMK_Pos (1UL) /*!< ICHEMK (Bit 1) */ + #define R_ICACHE_ICCTRL_ICHEMK_Msk (0x2UL) /*!< ICHEMK (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEN_Pos (0UL) /*!< ICHEN (Bit 0) */ + #define R_ICACHE_ICCTRL_ICHEN_Msk (0x1UL) /*!< ICHEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCFG ================================================ */ + #define R_ICACHE_ICCFG_ICHSIZE_Pos (8UL) /*!< ICHSIZE (Bit 8) */ + #define R_ICACHE_ICCFG_ICHSIZE_Msk (0x7f00UL) /*!< ICHSIZE (Bitfield-Mask: 0x7f) */ + #define R_ICACHE_ICCFG_ICHLINE_Pos (4UL) /*!< ICHLINE (Bit 4) */ + #define R_ICACHE_ICCFG_ICHLINE_Msk (0xf0UL) /*!< ICHLINE (Bitfield-Mask: 0x0f) */ + #define R_ICACHE_ICCFG_ICHWAY_Pos (0UL) /*!< ICHWAY (Bit 0) */ + #define R_ICACHE_ICCFG_ICHWAY_Msk (0xfUL) /*!< ICHWAY (Bitfield-Mask: 0x0f) */ +/* ========================================================= ICERR ================================================ */ + #define R_ICACHE_ICERR_CISTW_Pos (31UL) /*!< CISTW (Bit 31) */ + #define R_ICACHE_ICERR_CISTW_Msk (0x80000000UL) /*!< CISTW (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESAFE_Pos (30UL) /*!< ESAFE (Bit 30) */ + #define R_ICACHE_ICERR_ESAFE_Msk (0x40000000UL) /*!< ESAFE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESMH_Pos (29UL) /*!< ESMH (Bit 29) */ + #define R_ICACHE_ICERR_ESMH_Msk (0x20000000UL) /*!< ESMH (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESPBSE_Pos (28UL) /*!< ESPBSE (Bit 28) */ + #define R_ICACHE_ICERR_ESPBSE_Msk (0x10000000UL) /*!< ESPBSE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESTE1_Pos (27UL) /*!< ESTE1 (Bit 27) */ + #define R_ICACHE_ICERR_ESTE1_Msk (0x8000000UL) /*!< ESTE1 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESTE2_Pos (26UL) /*!< ESTE2 (Bit 26) */ + #define R_ICACHE_ICERR_ESTE2_Msk (0x4000000UL) /*!< ESTE2 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESDC_Pos (25UL) /*!< ESDC (Bit 25) */ + #define R_ICACHE_ICERR_ESDC_Msk (0x2000000UL) /*!< ESDC (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESDE_Pos (24UL) /*!< ESDE (Bit 24) */ + #define R_ICACHE_ICERR_ESDE_Msk (0x1000000UL) /*!< ESDE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMAFE_Pos (22UL) /*!< ERMAFE (Bit 22) */ + #define R_ICACHE_ICERR_ERMAFE_Msk (0x400000UL) /*!< ERMAFE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMMH_Pos (21UL) /*!< ERMMH (Bit 21) */ + #define R_ICACHE_ICERR_ERMMH_Msk (0x200000UL) /*!< ERMMH (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMPBSE_Pos (20UL) /*!< ERMPBSE (Bit 20) */ + #define R_ICACHE_ICERR_ERMPBSE_Msk (0x100000UL) /*!< ERMPBSE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMTE1_Pos (19UL) /*!< ERMTE1 (Bit 19) */ + #define R_ICACHE_ICERR_ERMTE1_Msk (0x80000UL) /*!< ERMTE1 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMTE2_Pos (18UL) /*!< ERMTE2 (Bit 18) */ + #define R_ICACHE_ICERR_ERMTE2_Msk (0x40000UL) /*!< ERMTE2 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMDC_Pos (17UL) /*!< ERMDC (Bit 17) */ + #define R_ICACHE_ICERR_ERMDC_Msk (0x20000UL) /*!< ERMDC (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMDE_Pos (16UL) /*!< ERMDE (Bit 16) */ + #define R_ICACHE_ICERR_ERMDE_Msk (0x10000UL) /*!< ERMDE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHEWY_Pos (13UL) /*!< ICHEWY (Bit 13) */ + #define R_ICACHE_ICERR_ICHEWY_Msk (0xe000UL) /*!< ICHEWY (Bitfield-Mask: 0x07) */ + #define R_ICACHE_ICERR_ICHEIX_Pos (5UL) /*!< ICHEIX (Bit 5) */ + #define R_ICACHE_ICERR_ICHEIX_Msk (0x1fe0UL) /*!< ICHEIX (Bitfield-Mask: 0xff) */ + #define R_ICACHE_ICERR_ICHERQ_Pos (4UL) /*!< ICHERQ (Bit 4) */ + #define R_ICACHE_ICERR_ICHERQ_Msk (0x10UL) /*!< ICHERQ (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHED_Pos (3UL) /*!< ICHED (Bit 3) */ + #define R_ICACHE_ICERR_ICHED_Msk (0x8UL) /*!< ICHED (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHET_Pos (2UL) /*!< ICHET (Bit 2) */ + #define R_ICACHE_ICERR_ICHET_Msk (0x4UL) /*!< ICHET (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHERR_Pos (0UL) /*!< ICHERR (Bit 0) */ + #define R_ICACHE_ICERR_ICHERR_Msk (0x1UL) /*!< ICHERR (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4KH_ICACHE */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_PMU Count Function Registers (PMU) + * @brief Type definitions for the Count Function Registers (PMU) + * @{ + */ + +/** + * @brief Structure type to access the Count Function Registers (PMU). + */ + +typedef union +{ + __IOM uint32_t PMUMCTRL; /*!< (@ 0x00000000) Performance Counter User Mode Control */ + + struct + { + __IOM uint32_t PMUE0 : 1; /*!< [0..0] This bit specifies the accessibility of the PMCTRL0, + * PMCOUNT0 and PMSUBCND0 registers in user mode.0: Disables + * accesses to PMCTRL0/PMCOUNT0/PMSUBCND0 in user mode.1: + * Enables accesses to PMCTRL0/PMCOUNT0/PMSUBCND0 in user + * mode. */ + __IOM uint32_t PMUE1 : 1; /*!< [1..1] This bit specifies the accessibility of the PMCTRL1, + * PMCOUNT1 and PMSUBCND1 registers in user mode.0: Disables + * accesses to PMCTRL1/PMCOUNT1/PMSUBCND1 in user mode.1: + * Enables accesses to PMCTRL1/PMCOUNT1/PMSUBCND1 in user + * mode. */ + __IOM uint32_t PMUE2 : 1; /*!< [2..2] This bit specifies the accessibility of the PMCTRL2, + * PMCOUNT2 and PMSUBCND2 registers in user mode.0: Disables + * accesses to PMCTRL2/PMCOUNT2/PMSUBCND2 in user mode.1: + * Enables accesses to PMCTRL2/PMCOUNT2/PMSUBCND2 in user + * mode. */ + __IOM uint32_t PMUE3 : 1; /*!< [3..3] This bit specifies the accessibility of the PMCTRL3, + * PMCOUNT3 and PMSUBCND3 registers in user mode.0: Disables + * accesses to PMCTRL3/PMCOUNT3/PMSUBCND3 in user mode.1: + * Enables accesses to PMCTRL3/PMCOUNT3/PMSUBCND3 in user + * mode. */ + uint32_t : 28; + } PMUMCTRL_b; +} RH850_PMU_PMUMCTRL_Type; + +typedef union +{ + __IOM uint32_t PMCTRL; /*!< (@ 0x00000000) Performance Counter User Mode Control */ + + struct + { + __IOM uint32_t CEN : 1; /*!< [0..0] This bit enables or disables the count operation of the + * PMCOUNTn register.0: Disables count operation.1: Enables + * count operation.If this bit is written with a 1 when it + * is set to 0, the counter starts countingimmediately. If + * this bit is written with a 0 when it is set to 1, the counter + * stopscounting immediately. If this bit is 0, the values + * of the PMCOUNTn register ispreserved. There is no factor + * that will automatically change the value of thisbit. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This bit serves as the overflow flag. This bit is set + * to 1 when an overflowoccurs in the PMCOUNTn register as + * the result of its count operation.This bit is not automatically + * cleared to 0. To reset the overflow state, write a 0into + * this bit.Since this bit can be written with a 1, it can + * be an overflow condition regardlessof the count operation. + * Although it does not affect the counter operation, caremust + * be taken not to take that condition for an overflow. */ + uint32_t : 6; + __IOM uint32_t CND : 8; /*!< [15..8] When read, the value after reset is returned. */ + uint32_t : 16; + } PMCTRL_b; +} RH850_PMU_PMCTRL_Type; + +typedef union +{ + __IOM uint32_t PMCOUNT; /*!< (@ 0x00000000) Performance Count */ + + struct + { + __IOM uint32_t PMCNT : 32; /*!< [31..0] These bits form a 32-bit counter register.The counter + * counts the number of occurrences of the event that is specified + * bythe PMCTRLn.CND bit.When this register counts up from + * FFFF FFFFH, the PMCTRLn.OVF bit is setto 1 and the register + * wraps around to 0000 0000H.This register is accessible + * at an arbitrary timing regardless of whethercounting is + * enabled or disabled. In addition, it is possible to start + * counting at anarbitrary count by loading that value in + * this register before starting to count. */ + } PMCOUNT_b; +} RH850_PMU_PMCOUNT_Type; + +typedef union +{ + __IOM uint32_t PMSUBCND; /*!< (@ 0x00000000) Performance Count */ + + struct + { + __IOM uint32_t SUBCND : 13; /*!< [12..0] How the value of the SUBCND field is used depends on + * the setting of thePMCTRLn.CND. If the value of the PMCTRLn.CND + * is other than the following,the value of the SUBCND field + * does not affect the operation of theperformance counter.R/W + * 0Value of thePMCTRLn.CND Operation of the performance counter20H + * The channel number of the interrupt (EIINTn) for which + * theacceptance count is counted can be limited. The operation + * isspecified by the value of bit 12.0: The channel number + * to be counted is no */ + uint32_t : 19; + } PMSUBCND_b; +} RH850_PMU_PMSUBCND_Type; + +/** @brief Count Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_PMU ================ */ +/* ================================================================================================================== */ + +/* ======================================================= PMUMCTRL =============================================== */ + #define R_PMU_PMUMCTRL_PMUE3_Pos (3UL) /*!< PMUE3 (Bit 3) */ + #define R_PMU_PMUMCTRL_PMUE3_Msk (0x8UL) /*!< PMUE3 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE2_Pos (2UL) /*!< PMUE2 (Bit 2) */ + #define R_PMU_PMUMCTRL_PMUE2_Msk (0x4UL) /*!< PMUE2 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE1_Pos (1UL) /*!< PMUE1 (Bit 1) */ + #define R_PMU_PMUMCTRL_PMUE1_Msk (0x2UL) /*!< PMUE1 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE0_Pos (0UL) /*!< PMUE0 (Bit 0) */ + #define R_PMU_PMUMCTRL_PMUE0_Msk (0x1UL) /*!< PMUE0 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE_Msk (0xFFUL) /*!< PMUE0 (Bitfield-Mask: 0x00) */ +/* ======================================================== PMCTRL0 =============================================== */ + #define R_PMU_PMCTRL0_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL0_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL0_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL0_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL0_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL1 =============================================== */ + #define R_PMU_PMCTRL1_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL1_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL1_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL1_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL2 =============================================== */ + #define R_PMU_PMCTRL2_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL2_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL2_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL2_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL2_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL2_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL3 =============================================== */ + #define R_PMU_PMCTRL3_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL3_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL3_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL3_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL3_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL3_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PMCOUNT0 =============================================== */ + #define R_PMU_PMCOUNT0_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT0_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT1 =============================================== */ + #define R_PMU_PMCOUNT1_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT1_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT2 =============================================== */ + #define R_PMU_PMCOUNT2_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT2_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT3 =============================================== */ + #define R_PMU_PMCOUNT3_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT3_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ + +/*@}*/ /* end of group RH850_G4KH_PMU */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_HWF Hardware Function Registers (HWF) + * @brief Type definitions for the Hardware Function Registers (HWF) + * @{ + */ + +/** + * @brief Structure type to access the Hardware Function Registers (HWF). + */ + +typedef union +{ + __IOM uint32_t LSTEST0; /*!< (@ 0x00000000) Lock-step Function Self-diagnosis Register 0 */ + + struct + { + __IOM uint32_t LSTEST0 : 32; /*!< [31..0] [Write]Write any value to bits of the LSTEST0 register.[Read]Value + * in LSTEST0 is read by the master CPU of the lock-stepped + * CPU.Value in LSTEST1 is read by the checker CPU of the + * lock-stepped CPU. */ + } LSTEST0_b; +} RH850_HWF_LSTEST0_Type; + +typedef union +{ + __IOM uint32_t LSTEST1; /*!< (@ 0x00000000) Lock-step Function Self-diagnosis Register 1 */ + + struct + { + __IOM uint32_t LSTEST1 : 32; /*!< [31..0] [Write]Write any value to bits of the LSTEST1 register.[Read]Value + * in LSTEST1 is read by the master CPU of the lock-stepped + * CPU.Value in LSTEST0 is read by the checker CPU of the + * lock-stepped CPU. */ + } LSTEST1_b; +} RH850_HWF_LSTEST1_Type; + +/** @brief Hardware Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_HWF ================ */ +/* ================================================================================================================== */ + +/* ======================================================== LSTEST0 =============================================== */ + #define R_HWF_LSTEST0_LSTEST0_Pos (0UL) /*!< LSTEST0 (Bit 0) */ + #define R_HWF_LSTEST0_LSTEST0_Msk (0xffffffffUL) /*!< LSTEST0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LSTEST1 =============================================== */ + #define R_HWF_LSTEST1_LSTEST1_Pos (0UL) /*!< LSTEST1 (Bit 0) */ + #define R_HWF_LSTEST1_LSTEST1_Msk (0xffffffffUL) /*!< LSTEST1 (Bitfield-Mask: 0xffffffff) */ + +/*@}*/ /* end of group RH850_G4KH_HWF */ + +/** + * @ingroup RH850_G4KH_Core_register + * @defgroup RH850_G4KH_TSC Timestamp counter (TSC) + * @brief Type definitions for the Timestamp counter (TSC) + * @{ + */ + +/** + * @brief Structure type to access the Timestamp counter (TSC). + */ + +typedef union +{ + __IOM uint32_t TSCOUNTL; /*!< (@ 0x00000000) Timestamp Count L */ + + struct + { + __IOM uint32_t TSCNTL : 32; /*!< [31..0] These bits account for the lower-order 32 bits of the + * 64-bit counter.If counting is enabled by the TSCTRL register, + * the value of this register isincremented by 1 on every + * clock cycle.When this register counts up from FFFF FFFFH, + * the TSCOUNTH register isincremented by 1 as a carryover + * and this register wraps around to0000 0000H.This register + * is accessible at an arbitrary timing regardless of whethercounting + * is enabled or disabled. In addition, it is possible to + * start counting at anarbitrary */ + } TSCOUNTL_b; +} RH850_TSC_TSCOUNTL_Type; + +typedef union +{ + __IOM uint32_t TSCOUNTH; /*!< (@ 0x00000000) Timestamp Count H */ + + struct + { + __IOM uint32_t TSCNTH : 32; /*!< [31..0] These bits account for the higher-order 32 bits of the + * 64-bit counter.If counting is enabled by the TSCTRL register, + * the value of this register isincremented by 1 when the + * TSCOUNTL register counts up and generates acarryover.If + * a carryover occurs in the TSCOUNTL register when this register + * holds avalue of FFFF FFFFH, the TSCTRL.OVF bit is set to + * 1 and this register wrapsaround to 0000 0000H.This register + * is accessible at an arbitrary timing regardless of whethercounting + * is enabled or disabl */ + } TSCOUNTH_b; +} RH850_TSC_TSCOUNTH_Type; + +typedef union +{ + __IOM uint32_t TSCTRL; /*!< (@ 0x00000000) Timestamp Count Control */ + + struct + { + __IOM uint32_t CEN : 1; /*!< [0..0] This bit enables or disables the count operation of the + * 64-bit timestampcounter which is implemented by combining + * the TSCOUNTH and TSCOUNTLregisters.0: Disables count operation.1: + * Enables count operation.If this bit is written with a 1 + * when it is set to 0, the counter starts countingimmediately. + * If this bit is written with a 0 when it is set to 1, the + * counter stopscounting immediately. If this bit is 0, the + * values of the TSCOUNTH andTSCOUNTL registers are preserved. + * There is no factor that */ + __IOM uint32_t OVF : 1; /*!< [1..1] This bit serves as the overflow flag. This bit is set + * to 1 when an overflowoccurs in the TSCOUNTH register as + * the result of its count operation.This bit is not automatically + * cleared to 0. To reset the overflow state, write a 0into + * this bit.Since this bit can be written with a 1, it can + * be an overflow condition regardlessof the count operation. + * Although it does not affect the counter operation, caremust + * be taken not to take that condition for an overflow. */ + uint32_t : 30; + } TSCTRL_b; +} RH850_TSC_TSCTRL_Type; + +/** @brief Timestamp counter macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_TSC ================ */ +/* ================================================================================================================== */ + +/* ======================================================= TSCOUNTL =============================================== */ + #define R_TSC_TSCOUNTL_TSCNTL_Pos (0UL) /*!< TSCNTL (Bit 0) */ + #define R_TSC_TSCOUNTL_TSCNTL_Msk (0xffffffffUL) /*!< TSCNTL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TSCOUNTH =============================================== */ + #define R_TSC_TSCOUNTH_TSCNTH_Pos (0UL) /*!< TSCNTH (Bit 0) */ + #define R_TSC_TSCOUNTH_TSCNTH_Msk (0xffffffffUL) /*!< TSCNTH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSCTRL ================================================ */ + #define R_TSC_TSCTRL_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_TSC_TSCTRL_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_TSC_TSCTRL_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_TSC_TSCTRL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4KH_TSC */ + +/*@}*/ /* end of group RH850_G4KH_Core_register */ +/*@}*/ /* end of group G4KH_Core_register */ + +/*********************************************************************************************************************** + * Hardware Abstraction Layer + **********************************************************************************************************************/ + +/** + * @defgroup RH850_API_Funcs RH850 Macro Wrapper API Functions + * @brief RH850 API Functions + * @defgroup RH850_G4KH_API_Funcs RH850 G4KH Macro Wrapper API Functions + * @brief RH850 G4KH Macro Wrapper API Functions + * @ingroup RH850_API_Funcs + * @{ + */ + +/* ############################################# FPU functions #################################################### */ + #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_FPU_API FPU API Functions + * @brief FPU API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + #include "G4-profile/rh850_g4_fpu.h" + + #define RH850_FPU_Enable __RH850_FPU_Enable /*!< Wrapper macro that calls the @ref __RH850_FPU_Enable */ + #define RH850_FPU_Disable __RH850_FPU_Disable /*!< Wrapper macro that calls the @ref __RH850_FPU_Disable */ + #define RH850_FPU_EnableGet __RH850_FPU_EnableGet /*!< Wrapper macro that calls the @ref __RH850_FPU_EnableGet */ + #define RH850_FPU_StatusGet __RH850_FPU_StatusGet /*!< Wrapper macro that calls the @ref __RH850_FPU_StatusGet */ + #define RH850_FPU_StatusClear __RH850_FPU_StatusClear /*!< Wrapper macro that calls the @ref __RH850_FPU_StatusClear */ + #define RH850_FPU_FpsrCcBitGet __RH850_FPU_FpsrCcBitGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrCcBitGet */ + #define RH850_FPU_FpsrCcBitSet __RH850_FPU_FpsrCcBitSet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrCcBitSet */ + #define RH850_FPU_FpsrIfBitGet __RH850_FPU_FpsrIfBitGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrIfBitGet */ + #define RH850_FPU_ModeFlushSet __RH850_FPU_ModeFlushSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeFlushSet */ + #define RH850_FPU_ModeFlushGet __RH850_FPU_ModeFlushGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeFlushGet */ + #define RH850_FPU_ModeRoundingSet __RH850_FPU_ModeRoundingSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeRoundingSet */ + #define RH850_FPU_ModeRoundingGet __RH850_FPU_ModeRoundingGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeRoundingGet */ + #define RH850_FPU_ExceptionEnableSet __RH850_FPU_ExceptionEnableSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ExceptionEnableSet */ + #define RH850_FPU_ExceptionEnableGet __RH850_FPU_ExceptionEnableGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ExceptionEnableGet*/ + #define RH850_FPU_FpepcGet __RH850_FPU_FpepcGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpepcGet*/ +/** @} */ /* end of RH850_FPU */ + #endif + +/* ########################## ICACHE functions ################################## */ + #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_ICACHE_API ICACHE API Functions + * @brief ICACHE API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_icache.h" + + #define RH850_ICache_Enable __RH850_ICache_Enable /*!< Wrapper macro that calls the @ref __RH850_ICache_Enable */ + #define RH850_ICache_Disable __RH850_ICache_Disable /*!< Wrapper macro that calls the @ref __RH850_ICache_Disable */ + #define RH850_ICache_EnableGet __RH850_ICache_EnableGet /*!< Wrapper macro that calls the @ref __RH850_ICache_EnableGet */ + #define RH850_ICache_CacheSizeGet __RH850_ICache_CacheSizeGet /*!< Wrapper macro that calls the @ref __RH850_ICache_CacheSizeGet */ + #define RH850_ICache_LinesPerWayGet __RH850_ICache_LinesPerWayGet /*!< Wrapper macro that calls the @ref __RH850_ICache_LinesPerWayGet */ + #define RH850_ICache_NumberOfWaysGet __RH850_ICache_NumberOfWaysGet /*!< Wrapper macro that calls the @ref __RH850_ICache_NumberOfWaysGet */ + #define RH850_ICache_ErrorStatusGet __RH850_ICache_ErrorStatusGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorStatusGet */ + #define RH850_ICache_ErrorIndexGet __RH850_ICache_ErrorIndexGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorIndexGet */ + #define RH850_ICache_ErrorWayGet __RH850_ICache_ErrorWayGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorWayGet */ + #define RH850_ICache_Clear __RH850_ICache_Clear /*!< Wrapper macro that calls the @ref __RH850_ICache_Clear */ + #define RH850_ICache_AutoInvalidateOnErrorSet __RH850_ICache_AutoInvalidateOnErrorSet /*!< Wrapper macro that calls the @ref __RH850_ICache_AutoInvalidateOnErrorSet */ + #define RH850_ICache_ErrorNotifyMaskSet __RH850_ICache_ErrorNotifyMaskSet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorNotifyMaskSet */ + #define RH850_ICache_TagLoGet __RH850_ICache_TagLoGet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagLoGet */ + #define RH850_ICache_TagLoSet __RH850_ICache_TagLoSet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagLoSet */ + #define RH850_ICache_TagHiGet __RH850_ICache_TagHiGet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagHiGet */ + #define RH850_ICache_TagHiSet __RH850_ICache_TagHiSet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagHiSet */ + #define RH850_ICache_DataLoGet __RH850_ICache_DataLoGet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataLoGet */ + #define RH850_ICache_DataLoSet __RH850_ICache_DataLoSet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataLoSet */ + #define RH850_ICache_DataHiGet __RH850_ICache_DataHiGet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataHiGet */ + #define RH850_ICache_DataHiSet __RH850_ICache_DataHiSet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataHiSet */ +/** @} */ /* end of RH850_ICACHE */ + #endif + +/* ############################################# IRQ functions #################################################### */ + #if defined(__IRQ_PRESENT) && (__IRQ_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_IRQ_API IRQ API Functions + * @brief IRQ API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + + #define RH850_INTC1_BASE 0xFFFC4000UL + #define RH850_INTC2_BASE 0xFFF80000UL + #define RH850_INTC1_OFFSET 0x4000U + #define RH850_INTC1_EIBD_OFFSET 0x0100U + #define RH850_INTC2_EIBD_OFFSET 0x2000U + #define RH850_INTC1_EEIC_OFFSET 0x0200U + #define RH850_INTC2_EEIC_OFFSET 0x4000U + + #include "G4-profile/rh850_g4_irq.h" + + #define RH850_IRQ_InterruptPriorityGet __RH850_IRQ_InterruptPriorityGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptPriorityGet */ + #define RH850_IRQ_InterruptMaskStatusGet __RH850_IRQ_InterruptMaskStatusGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptMaskStatusGet */ + #define RH850_IRQ_InterruptControlStatusGet __RH850_IRQ_InterruptControlStatusGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptControlStatusGet */ + #define RH850_IRQ_PriorityExtensionGet __RH850_IRQ_PriorityExtensionGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityExtensionGet */ + #define RH850_IRQ_PriorityExtensionSet __RH850_IRQ_PriorityExtensionSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityExtensionSet */ + #define RH850_IRQ_IsprUpdateModeGet __RH850_IRQ_IsprUpdateModeGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IsprUpdateModeGet */ + #define RH850_IRQ_IsprUpdateModeSet __RH850_IRQ_IsprUpdateModeSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IsprUpdateModeSet */ + #define RH850_IRQ_RegisterBankLimitGet __RH850_IRQ_RegisterBankLimitGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_RegisterBankLimitGet */ + #define RH850_IRQ_RegisterBankLimitSet __RH850_IRQ_RegisterBankLimitSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_RegisterBankLimitSet */ + #define RH850_IRQ_PriorityMaskLevelGet __RH850_IRQ_PriorityMaskLevelGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityMaskLevelGet */ + #define RH850_IRQ_PriorityMaskLevelSet __RH850_IRQ_PriorityMaskLevelSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityMaskLevelSet */ + #define RH850_IRQ_IntMaskGet __RH850_IRQ_IntMaskGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskGet */ + #define RH850_IRQ_IntMaskSet __RH850_IRQ_IntMaskSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ + #define RH850_IRQ_EnableIRQ __RH850_IRQ_EnableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_EnableIRQ */ + #define RH850_IRQ_EnableIRQByPE __RH850_IRQ_EnableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_EnableIRQ */ + #define RH850_IRQ_GetEnableIRQ __RH850_IRQ_GetEnableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetEnableIRQ */ + #define RH850_IRQ_GetEnableIRQByPE __RH850_IRQ_GetEnableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetEnableIRQ */ + #define RH850_IRQ_DisableIRQ __RH850_IRQ_DisableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_DisableIRQ */ + #define RH850_IRQ_DisableIRQByPE __RH850_IRQ_DisableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_DisableIRQ */ + #define RH850_IRQ_GetPendingIRQ __RH850_IRQ_GetPendingIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPendingIRQ */ + #define RH850_IRQ_GetPendingIRQByPE __RH850_IRQ_GetPendingIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPendingIRQ */ + #define RH850_IRQ_ClearPendingIRQ __RH850_IRQ_ClearPendingIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_ClearPendingIRQ */ + #define RH850_IRQ_ClearPendingIRQByPE __RH850_IRQ_ClearPendingIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_ClearPendingIRQ */ + #define RH850_IRQ_GetActive __RH850_IRQ_GetActive /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetActive */ + #define RH850_IRQ_GetActiveByPE __RH850_IRQ_GetActiveByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetActive */ + #define RH850_IRQ_SetPriority __RH850_IRQ_SetPriority /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetPriority */ + #define RH850_IRQ_SetPriorityByPE __RH850_IRQ_SetPriorityByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetPriority */ + #define RH850_IRQ_GetPriority __RH850_IRQ_GetPriority /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPriority */ + #define RH850_IRQ_GetPriorityByPE __RH850_IRQ_GetPriorityByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPriority */ + #define RH850_IRQ_SetIRQMethod __RH850_IRQ_SetIRQMethod /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetIRQMethod */ + #define RH850_IRQ_SetIRQMethodByPE __RH850_IRQ_SetIRQMethodByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetIRQMethod */ + #define RH850_IRQ_GetIRQMethod __RH850_IRQ_GetIRQMethod /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetIRQMethod */ + #define RH850_IRQ_GetIRQMethodByPE __RH850_IRQ_GetIRQMethodByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetIRQMethod */ + #define RH850_IRQ_SetIRQBoundToPE __RH850_IRQ_SetIRQBoundToPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ + #define RH850_IRQ_GetIRQBoundToPE __RH850_IRQ_GetIRQBoundToPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ +/** @} */ /* end of RH850_IRQ */ + #endif + +/* ############################################# MPU functions #################################################### */ + #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_MPU_API MPU API Functions + * @brief MPU API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_mpu.h" + + #define RH850_MPU_Enable __RH850_MPU_Enable /*!< Wrapper macro that calls the @ref __RH850_MPU_Enable */ + #define RH850_MPU_Disable __RH850_MPU_Disable /*!< Wrapper macro that calls the @ref __RH850_MPU_Disable */ + #define RH850_MPU_MpidSet __RH850_MPU_MpidSet /*!< Wrapper macro that calls the @ref __RH850_MPU_MpidSet */ + #define RH850_MPU_StateGet __RH850_MPU_StateGet /*!< Wrapper macro that calls the @ref __RH850_MPU_StateGet */ + #define RH850_MPU_SvStateGet __RH850_MPU_SvStateGet /*!< Wrapper macro that calls the @ref __RH850_MPU_SvStateGet */ + #define RH850_MPU_NumberofRegionsGet __RH850_MPU_NumberofRegionsGet /*!< Wrapper macro that calls the @ref __RH850_MPU_NumberofRegionsGet */ + #define RH850_MPU_NumberOfBanksGet __RH850_MPU_NumberOfBanksGet /*!< Wrapper macro that calls the @ref __RH850_MPU_NumberOfBanksGet */ + #define RH850_MPU_ArchitectureVersionGet __RH850_MPU_ArchitectureVersionGet /*!< Wrapper macro that calls the @ref __RH850_MPU_ArchitectureVersionGet */ + #define RH850_MPU_ExecMemProtectCheck __RH850_MPU_ExecMemProtectCheck /*!< Wrapper macro that calls the @ref __RH850_MPU_ExecMemProtectCheck */ + #define RH850_MPU_MpuIdSet __RH850_MPU_MpuIdSet /*!< Wrapper macro that calls the @ref __RH850_MPU_MpuIdSet */ + #define RH850_MPU_BankGet __RH850_MPU_BankGet /*!< Wrapper macro that calls the @ref __RH850_MPU_BankGet */ + #define RH850_MPU_AttrSet __RH850_MPU_AttrSet /*!< Wrapper macro that calls the @ref __RH850_MPU_AttrSet */ + #define RH850_MPU_AttrGet __RH850_MPU_AttrGet /*!< Wrapper macro that calls the @ref __RH850_MPU_AttrGet */ + #define RH850_MPU_RegionClear __RH850_MPU_RegionClear /*!< Wrapper macro that calls the @ref __RH850_MPU_RegionClear */ + #define RH850_MPU_RegionSet __RH850_MPU_RegionSet /*!< Wrapper macro that calls the @ref __RH850_MPU_RegionSet */ + #define RH850_MPU_LowerAddressGet __RH850_MPU_LowerAddressGet /*!< Wrapper macro that calls the @ref __RH850_MPU_LowerAddressGet */ + #define RH850_MPU_UpperAddressGet __RH850_MPU_UpperAddressGet /*!< Wrapper macro that calls the @ref __RH850_MPU_UpperAddressGet */ +/** @} */ /* end of RH850_MPU */ + #endif + +/* ############################################# PMU functions #################################################### */ + #if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_PMU_API PMU API Functions + * @brief PMU API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_pmu.h" + + #define RH850_PMU_ChannelEnable __RH850_PMU_ChannelEnable /*!< Wrapper macro that calls the @ref __RH850_PMU_ChannelEnable */ + #define RH850_PMU_ChannelDisable __RH850_PMU_ChannelDisable /*!< Wrapper macro that calls the @ref __RH850_PMU_ChannelDisable */ + #define RH850_PMU_StatusGet __RH850_PMU_StatusGet /*!< Wrapper macro that calls the @ref __RH850_PMU_StatusGet */ + #define RH850_PMU_ModeSet __RH850_PMU_ModeSet /*!< Wrapper macro that calls the @ref __RH850_PMU_ModeSet */ + #define RH850_PMU_ControlSet __RH850_PMU_ControlSet /*!< Wrapper macro that calls the @ref __RH850_PMU_ControlSet */ + #define RH850_PMU_OvfGet __RH850_PMU_OverflowGet /*!< Wrapper macro that calls the @ref __RH850_PMU_OverflowGet */ + #define RH850_PMU_OvfClear __RH850_PMU_OverflowClear /*!< Wrapper macro that calls the @ref __RH850_PMU_OverflowClear */ + #define RH850_PMU_CountSet __RH850_PMU_CounterSet /*!< Wrapper macro that calls the @ref __RH850_PMU_CounterSet */ + #define RH850_PMU_CountGet __RH850_PMU_CounterGet /*!< Wrapper macro that calls the @ref __RH850_PMU_CounterGet */ + #define RH850_PMU_SubCountSet __RH850_PMU_SubCountSet /*!< Wrapper macro that calls the @ref __RH850_PMU_SubCountSet */ + #define RH850_PMU_SubCountGet __RH850_PMU_SubCountGet /*!< Wrapper macro that calls the @ref __RH850_PMU_SubCountGet */ +/** @} */ /* end of RH850_PMU */ + #endif + +/* ############################################# TSC functions #################################################### */ + #if defined(__TSC_PRESENT) && (__TSC_PRESENT == 1U) + +/** + * @defgroup RH850_G4KH_TSC_API TSC API Functions + * @brief TSC API Functions + * @ingroup RH850_G4KH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_tsc.h" + + #define RH850_TSC_Enable __RH850_TSC_Enable /*!< Wrapper macro that calls the @ref __RH850_TSC_Enable */ + #define RH850_TSC_Disable __RH850_TSC_Disable /*!< Wrapper macro that calls the @ref __RH850_TSC_Disable */ + #define RH850_TSC_EnableGet __RH850_TSC_EnableGet /*!< Wrapper macro that calls the @ref __RH850_TSC_EnableGet */ + #define RH850_TSC_ControlRead __RH850_TSC_ControlRead /*!< Wrapper macro that calls the @ref __RH850_TSC_ControlRead */ + #define RH850_TSC_ControlSet __RH850_TSC_ControlSet /*!< Wrapper macro that calls the @ref __RH850_TSC_ControlSet */ + #define RH850_TSC_OverflowGet __RH850_TSC_OverflowGet /*!< Wrapper macro that calls the @ref __RH850_TSC_OverflowGet */ + #define RH850_TSC_OverflowClear __RH850_TSC_OverflowClear /*!< Wrapper macro that calls the @ref __RH850_TSC_OverflowClear */ + #define RH850_TSC_CounterHighGet __RH850_TSC_CounterHighGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterHighGet */ + #define RH850_TSC_CounterHighSet __RH850_TSC_CounterHighSet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterHighSet */ + #define RH850_TSC_CounterLowGet __RH850_TSC_CounterLowGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterLowGet */ + #define RH850_TSC_CounterLowSet __RH850_TSC_CounterLowSet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterLowSet */ + #define RH850_TSC_CounterFullGet __RH850_TSC_CounterFullGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterFullGet */ +/** @} */ /* end of RH850_TSC */ + #endif + +/** @} */ /* end of RH850_G4KH_API_Funcs */ + + #ifdef __cplusplus +} + #endif + + #endif /* __CORE_RH850_G4KH_H_DEPENDANT */ + +#endif /* __RH850_GENERIC */ diff --git a/arch/rh850/src/g4x/Core/Include/core_g4mh.h b/arch/rh850/src/g4x/Core/Include/core_g4mh.h new file mode 100644 index 0000000000000000000000000000000000000000..2bbfaa57707f3bfe32cf3588cd0a17c5db83e003 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/core_g4mh.h @@ -0,0 +1,3403 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file core_g4mh.h + * @brief RH850 G4MH Core Definitions + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __CORE_RH850_G4MH_H_GENERIC + #define __CORE_RH850_G4MH_H_GENERIC + + #include + #include + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * RH850 definitions + **********************************************************************************************************************/ + +/** + * @defgroup RH850_glob_defs RH850 Global Defines + * @brief RH850 Global Defines + * @{ + */ + +/** + * @defgroup RH850_G4MH RH850 G4MH + * @ingroup RH850_glob_defs + * @brief RH850 G4MH + * @{ + */ + +/** + * @ingroup RH850_G4MH + * @defgroup RH850_G4MH_Device_Capability_Def RH850 Device capabilitiy defines + * @brief RH850 Device capabilitiy defines + * @{ + */ + + #include "rh850_version.h" + +/* RH850 RH850_G4MH definitions */ + + #define __RH850_G4MH (1) /*!< RH850 G4MH Core */ + + #if defined(__CCRH__) + +/** __FPU_USED indicates whether an FPU is used or not. + */ + #if defined(__FPU) + #define __FPU_USED 1U + #else + #define __FPU_USED 0U + #endif + +/** __FXU_USED indicates whether an FXU is used or not. + */ + #if defined(__FXU) + #define __FXU_USED 1U + #else + #define __FXU_USED 0U + #endif + #endif + + #include "rh850_compiler.h" /* RH850 compiler specific defines */ + + #ifdef __cplusplus +} + #endif + +#endif /* __CORE_RH850_G4MH_H_GENERIC */ + +#ifndef __RH850_GENERIC + + #ifndef __CORE_RH850_G4MH_H_DEPENDANT + #define __CORE_RH850_G4MH_H_DEPENDANT + + #ifdef __cplusplus +extern "C" { + #endif + +/* check device defines and use defaults */ + #if defined __CHECK_DEVICE_DEFINES + #ifndef __RH850_G4MH_REV + #define __RH850_G4MH_REV 0x07U /*!< RH850 G4MH Core revision */ + #warning "__RH850_G4MH_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1U /*!< FPU present or not */ + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __FXU_PRESENT + #define __FXU_PRESENT 0U /*!< FXU present or not */ + #warning "__FXU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 1U /*!< ICACHE present or not */ + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __IRQ_PRESENT + #define __IRQ_PRESENT 1U /*!< IRQ present or not */ + #warning "__IRQ_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 1U /*!< MPU present or not */ + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 1U /*!< PMU present or not */ + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TSC_PRESENT + #define __TSC_PRESENT 1U /*!< TSC present or not */ + #warning "__TSC_PRESENT not defined in device header file; using default!" + #endif + #endif + +/** @} */ /* end of RH850_Device_Capability_Def */ + +/* IO definitions (access restrictions to peripheral registers) */ + +/** + * @ingroup RH850_G4MH + * @defgroup RH850_G4MH_IO_Type_Qualifiers RH850 IO Type Qualifiers + * @brief RH850 IO Type Qualifiers + * @{ + */ + + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ + #define __IM volatile const /*!< Defines 'read only' structure member permissions */ + #define __OM volatile /*!< Defines 'write only' structure member permissions */ + #define __IOM volatile /*!< Defines 'read / write' structure member permissions */ + +/** @} */ /* end of RH850_IO_Type_Qualifiers */ +/** @} */ /* end of RH850_G4MH */ +/** @} */ /* end of RH850_glob_defs */ + +/*********************************************************************************************************************** + * Register Abstraction + * Core Register contain: + * - Core Register + * - Core Debug Register + * - Core MPU Register + **********************************************************************************************************************/ + +/** + * @defgroup RH850_G4MH_core_register Defines and Type Definitions + * @ingroup RH850_G4MH_Core_register + * + * @brief Type definitions and defines for RH850 G4MH processor based devices. + */ + +/** + * @ingroup RH850_G4MH_core_register + * @defgroup RH850_G4MH_CORE Status and Control Registers + * @brief Core Register type definitions. Basic System Register Definitions for RH850 G4 + * This file provides symbolic names and documentation for system registers. + * @note Based on Table Basic System Registers (Renesas RH850 G4). + * @{ + */ + +/*********************************************************************************************************************** + * EI/FE Exception Registers + **********************************************************************************************************************/ + + #define SR_EIPC 0 /*!< RegID: Status save register for EI level exception (EIPC) (SR0, 0) */ + #define SL_EIPC 0 /*!< SelID: Status save register for EI level exception (EIPC) (SR0, 0) */ + #define SR_EIPSW 1 /*!< RegID: Status save register for EI level exception PSW (EIPSW) (SR1, 0) */ + #define SL_EIPSW 0 /*!< SelID: Status save register for EI level exception PSW (EIPSW) (SR1, 0) */ + #define SR_FEPC 2 /*!< RegID: Status save register for FE level exception (FEPC) (SR2, 0) */ + #define SL_FEPC 0 /*!< SelID: Status save register for FE level exception (FEPC) (SR2, 0) */ + #define SR_FEPSW 3 /*!< RegID: Status save register for FE level exception PSW (FEPSW) (SR3, 0) */ + #define SL_FEPSW 0 /*!< SelID: Status save register for FE level exception PSW (FEPSW) (SR3, 0) */ + #define SR_PSW 5 /*!< RegID: Program Status Word (PSW) (SR5, 0) */ + #define SL_PSW 0 /*!< SelID: Program Status Word (PSW) (SR5, 0) */ + +/*********************************************************************************************************************** + * FPU Registers + **********************************************************************************************************************/ + + #define SR_FPSR 6 /*!< RegID: Floating Point Status Register (FPSR) (SR6, 0) */ + #define SL_FPSR 0 /*!< SelID: Floating Point Status Register (FPSR) (SR6, 0) */ + #define SR_FPEPC 7 /*!< RegID: Floating Point Exception PC (FPEPC) (SR7, 0) */ + #define SL_FPEPC 0 /*!< SelID: Floating Point Exception PC (FPEPC) (SR7, 0) */ + #define SR_FPST 8 /*!< RegID: Floating Point Status (FPST) (SR8, 0) */ + #define SL_FPST 0 /*!< SelID: Floating Point Status (FPST) (SR8, 0) */ + #define SR_FPCC 9 /*!< RegID: Floating Point Condition Code (FPCC) (SR9, 0) */ + #define SL_FPCC 0 /*!< SelID: Floating Point Condition Code (FPCC) (SR9, 0) */ + #define SR_FPCFG 10 /*!< RegID: Floating Point Config (FPCFG) (SR10, 0) */ + #define SL_FPCFG 0 /*!< SelID: Floating Point Config (FPCFG) (SR10, 0) */ + +/*********************************************************************************************************************** + * Exception Cause Registers + **********************************************************************************************************************/ + + #define SR_EIIC 13 /*!< RegID: EI level exception cause (EIIC) (SR13, 0) */ + #define SL_EIIC 0 /*!< SelID: EI level exception cause (EIIC) (SR13, 0) */ + #define SR_FEIC 14 /*!< RegID: FE level exception cause (FEIC) (SR14, 0) */ + #define SL_FEIC 0 /*!< SelID: FE level exception cause (FEIC) (SR14, 0) */ + +/*********************************************************************************************************************** + * CALLT Registers + **********************************************************************************************************************/ + + #define SR_CTPC 16 /*!< RegID: CALLT execution status save register (CTPC) (SR16, 0) */ + #define SL_CTPC 0 /*!< SelID: CALLT execution status save register (CTPC) (SR16, 0) */ + #define SR_CTPSW 17 /*!< RegID: CALLT execution status save register (CTPSW) (SR17, 0) */ + #define SL_CTPSW 0 /*!< SelID: CALLT execution status save register (CTPSW) (SR17, 0) */ + #define SR_CTBP 20 /*!< RegID: CALLT base pointer (CTBP) (SR20, 0) */ + #define SL_CTBP 0 /*!< SelID: CALLT base pointer (CTBP) (SR20, 0) */ + +/*********************************************************************************************************************** + * SNOOZE Control + **********************************************************************************************************************/ + + #define SR_SNZCFG 21 /*!< RegID: SNOOZE control register (SNZCFG) (SR21, 0) */ + #define SL_SNZCFG 0 /*!< SelID: SNOOZE control register (SNZCFG) (SR21, 0) */ + +/*********************************************************************************************************************** + * Exception Registers + **********************************************************************************************************************/ + #define SR_EIWR 28 /*!< RegID: EI level exception working register (SR28, 0) */ + #define SL_EIWR 0 /*!< SelID: EI level exception working register (SR28, 0) */ + #define SR_FEWR 29 /*!< RegID: FE level exception working register (SR29, 0) */ + #define SL_FEWR 0 /*!< SelID: FE level exception working register (SR29, 0) */ + +/*********************************************************************************************************************** + * System Protection Registers + **********************************************************************************************************************/ + + #define SR_SPID 0 /*!< RegID: System protection identifier (SR0, 1) */ + #define SL_SPID 1 /*!< SelID: System protection identifier (SR0, 1) */ + #define SR_SPIDLIST 1 /*!< RegID: List of system protection identifiers (SR1, 1) */ + #define SL_SPIDLIST 1 /*!< SelID: List of system protection identifiers (SR1, 1) */ + #define SR_RBASE 2 /*!< RegID: Reset vector base address (SR2, 1) */ + #define SL_RBASE 1 /*!< SelID: Reset vector base address (SR2, 1) */ + #define SR_EBASE 3 /*!< RegID: Exception handler vector address (SR3, 1) */ + #define SL_EBASE 1 /*!< SelID: Exception handler vector address (SR3, 1) */ + #define SR_INTBP 4 /*!< RegID: Base address of interrupt handler table (SR4, 1) */ + #define SL_INTBP 1 /*!< SelID: Base address of interrupt handler table (SR4, 1) */ + #define SR_MCTL 5 /*!< RegID: CPU control (SR5, 1) */ + #define SL_MCTL 1 /*!< SelID: CPU control (SR5, 1) */ + #define SR_PID 6 /*!< RegID: Processor ID (SR6, 1) */ + #define SL_PID 1 /*!< SelID: Processor ID (SR6, 1) */ + #define SR_SVLOCK 8 /*!< RegID: Supervisor lock (SR8, 1) */ + #define SL_SVLOCK 1 /*!< SelID: Supervisor lock (SR8, 1) */ + #define SR_SCCFG 11 /*!< RegID: SYSCALL operation setting (SR11, 1) */ + #define SL_SCCFG 1 /*!< SelID: SYSCALL operation setting (SR11, 1) */ + #define SR_SCBP 12 /*!< RegID: SYSCALL base pointer (SR12, 1) */ + #define SL_SCBP 1 /*!< SelID: SYSCALL base pointer (SR12, 1) */ + +/*********************************************************************************************************************** + * Processor Element Registers + **********************************************************************************************************************/ + #define SR_PEID 0 /*!< RegID: Processor element identifier (SR0, 2) */ + #define SL_PEID 2 /*!< SelID: Processor element identifier (SR0, 2) */ + #define SR_BMID 1 /*!< RegID: Bus master identifier (SR1, 2) */ + #define SL_BMID 2 /*!< SelID: Bus master identifier (SR1, 2) */ + #define SR_MEA 6 /*!< RegID: Memory error address (SR6, 2) */ + #define SL_MEA 2 /*!< SelID: Memory error address (SR6, 2) */ + #define SR_MEI 8 /*!< RegID: Memory error information (SR8, 2) */ + #define SL_MEI 2 /*!< SelID: Memory error information (SR8, 2) */ + #define SR_RBCR0 15 /*!< RegID: Register bank control 0 (SR15, 2) */ + #define SL_RBCR0 2 /*!< SelID: Register bank control 0 (SR15, 2) */ + #define SR_RBCR1 16 /*!< RegID: Register bank control 1 (SR16, 2) */ + #define SL_RBCR1 2 /*!< SelID: Register bank control 1 (SR16, 2) */ + #define SR_RBNR 17 /*!< RegID: Register bank number (SR17, 2) */ + #define SL_RBNR 2 /*!< SelID: Register bank number (SR17, 2) */ + #define SR_RBIP 18 /*!< RegID: Register bank initial pointer (SR18, 2) */ + #define SL_RBIP 2 /*!< SelID: Register bank initial pointer (SR18, 2) */ + +/*********************************************************************************************************************** + * Interrupt Registers + **********************************************************************************************************************/ + #define SR_ISPR 10 /*!< RegID: Priority of interrupt being serviced (SR10, 2) */ + #define SL_ISPR 2 /*!< SelID: Priority of interrupt being serviced (SR10, 2) */ + #define SR_IMSR 11 /*!< RegID: Interrupt mask status (SR11, 2) */ + #define SL_IMSR 2 /*!< SelID: Interrupt mask status (SR11, 2) */ + #define SR_ICSR 12 /*!< RegID: Interrupt control status (SR12, 2) */ + #define SL_ICSR 2 /*!< SelID: Interrupt control status (SR12, 2) */ + #define SR_INTCFG 13 /*!< RegID: Interrupt function setting (SR13, 2) */ + #define SL_INTCFG 2 /*!< SelID: Interrupt function setting (SR13, 2) */ + #define SR_PLMR 14 /*!< RegID: Interrupt priority masking (SR14, 2) */ + #define SL_PLMR 2 /*!< SelID: Interrupt priority masking (SR14, 2) */ + +/*********************************************************************************************************************** + * FXU Registers + **********************************************************************************************************************/ + #define SR_FXSR 6 /*!< RegID: Extended floating-point operation configuration/status (SR6, 10) */ + #define SL_FXSR 10 /*!< SelID: Extended floating-point operation configuration/status (SR6, 10) */ + #define SR_FXST 8 /*!< RegID: Extended floating-point operation status (SR8, 10) */ + #define SL_FXST 10 /*!< SelID: Extended floating-point operation status (SR8, 10) */ + #define SR_FXINFO 9 /*!< RegID: FXU configuration information (SR9, 10) */ + #define SL_FXINFO 10 /*!< SelID: FXU configuration information (SR9, 10) */ + #define SR_FXCFG 10 /*!< RegID: Extended floating-point operation configuration (SR10, 10) */ + #define SL_FXCFG 10 /*!< SelID: Extended floating-point operation configuration (SR10, 10) */ + #define SR_FXXC 12 /*!< RegID: XC (cause) bits for each operation way (SR12, 10) */ + #define SL_FXXC 10 /*!< SelID: XC (cause) bits for each operation way (SR12, 10) */ + #define SR_FXXP 13 /*!< RegID: XP (preservation) bits for each operation way (SR13, 10) */ + #define SL_FXXP 10 /*!< SelID: XP (preservation) bits for each operation way (SR13, 10) */ + +/*********************************************************************************************************************** + * MPU Registers + **********************************************************************************************************************/ + #define SR_MPM 0 /*!< RegID: Memory protection operation mode setting (SR0, 5) */ + #define SL_MPM 5 /*!< SelID: Memory protection operation mode setting (SR0, 5) */ + #define SR_MPCFG 2 /*!< RegID: MPU configuration (SR2, 5) */ + #define SL_MPCFG 5 /*!< SelID: MPU configuration (SR2, 5) */ + #define SR_MCA 8 /*!< RegID: Memory protection setting check address (SR8, 5) */ + #define SL_MCA 5 /*!< SelID: Memory protection setting check address (SR8, 5) */ + #define SR_MCS 9 /*!< RegID: Memory protection setting check size (SR9, 5) */ + #define SL_MCS 5 /*!< SelID: Memory protection setting check size (SR9, 5) */ + #define SR_MCC 10 /*!< RegID: Memory protection setting check command (SR10, 5) */ + #define SL_MCC 5 /*!< SelID: Memory protection setting check command (SR10, 5) */ + #define SR_MCR 11 /*!< RegID: Memory protection setting check result (SR11, 5) */ + #define SL_MCR 5 /*!< SelID: Memory protection setting check result (SR11, 5) */ + #define SR_MCI 12 /*!< RegID: Memory protection setting check SPID (SR12, 5) */ + #define SL_MCI 5 /*!< SelID: Memory protection setting check SPID (SR12, 5) */ + #define SR_MPIDX 16 /*!< RegID: Index of memory protection setting registers to be accessed (SR16, 5) */ + #define SL_MPIDX 5 /*!< SelID: Index of memory protection setting registers to be accessed (SR16, 5) */ + #define SR_MPBK 17 /*!< RegID: MPU Bank Setting (SR17, 5) */ + #define SL_MPBK 5 /*!< SelID: MPU Bank Setting (SR17, 5) */ + #define SR_MPLA 20 /*!< RegID: Protection area minimum address (SR20, 5) */ + #define SL_MPLA 5 /*!< SelID: Protection area minimum address (SR20, 5) */ + #define SR_MPUA 21 /*!< RegID: Protection area maximum address (SR21, 5) */ + #define SL_MPUA 5 /*!< SelID: Protection area maximum address (SR21, 5) */ + #define SR_MPAT 22 /*!< RegID: Protection area attribute (SR22, 5) */ + #define SL_MPAT 5 /*!< SelID: Protection area attribute (SR22, 5) */ + #define SR_MPID0 24 /*!< RegID: SPID which can access protection area (SR24, 5) */ + #define SL_MPID0 5 /*!< SelID: SPID which can access protection area (SR24, 5) */ + #define SR_MPID1 25 /*!< RegID: SPID which can access protection area (SR25, 5) */ + #define SL_MPID1 5 /*!< SelID: SPID which can access protection area (SR25, 5) */ + #define SR_MPID2 26 /*!< RegID: SPID which can access protection area (SR26, 5) */ + #define SL_MPID2 5 /*!< SelID: SPID which can access protection area (SR25, 5) */ + #define SR_MPID3 27 /*!< RegID: SPID which can access protection area (SR27, 5) */ + #define SL_MPID3 5 /*!< SelID: SPID which can access protection area (SR27, 5) */ + #define SR_MPID4 28 /*!< RegID: SPID which can access protection area (SR28, 5) */ + #define SL_MPID4 5 /*!< SelID: SPID which can access protection area (SR28, 5) */ + #define SR_MPID5 29 /*!< RegID: SPID which can access protection area (SR29, 5) */ + #define SL_MPID5 5 /*!< SelID: SPID which can access protection area (SR29, 5) */ + #define SR_MPID6 30 /*!< RegID: SPID which can access protection area (SR30, 5) */ + #define SL_MPID6 5 /*!< SelID: SPID which can access protection area (SR30, 5) */ + #define SR_MPID7 31 /*!< RegID: SPID which can access protection area (SR31, 5) */ + #define SL_MPID7 5 /*!< SelID: SPID which can access protection area (SR31, 5) */ + +/*********************************************************************************************************************** + * ICAHCE Registers + **********************************************************************************************************************/ + #define SR_ICTAGL 16 /*!< RegID: Instruction cache tag Lo access (SR16, 4) */ + #define SL_ICTAGL 4 /*!< SelID: Instruction cache tag Lo access (SR16, 4) */ + #define SR_ICTAGH 17 /*!< RegID: Instruction cache tag Hi access (SR17, 4) */ + #define SL_ICTAGH 4 /*!< SelID: Instruction cache tag Hi access (SR17, 4) */ + #define SR_ICDATL 18 /*!< RegID: Instruction cache data Lo access (SR18, 4) */ + #define SL_ICDATL 4 /*!< SelID: Instruction cache data Lo access (SR18, 4) */ + #define SR_ICDATH 19 /*!< RegID: Instruction cache data Hi access (SR19, 4) */ + #define SL_ICDATH 4 /*!< SelID: Instruction cache data Hi access (SR19, 4) */ + #define SR_ICCTRL 24 /*!< RegID: Instruction cache control (SR24, 4) */ + #define SL_ICCTRL 4 /*!< SelID: Instruction cache control (SR24, 4) */ + #define SR_ICCFG 26 /*!< RegID: Instruction cache configuration (SR26, 4) */ + #define SL_ICCFG 4 /*!< SelID: Instruction cache configuration (SR26, 4) */ + #define SR_ICERR 28 /*!< RegID: Instruction cache error (SR28, 4) */ + #define SL_ICERR 4 /*!< SelID: Instruction cache error (SR28, 4) */ + +/*********************************************************************************************************************** + * Count Registers + **********************************************************************************************************************/ + #define SR_TSCOUNTL 0 /*!< RegID: Timestamp count L register (SR0, 11) */ + #define SL_TSCOUNTL 11 /*!< SelID: Timestamp count L register (SR0, 11) */ + #define SR_TSCOUNTH 1 /*!< RegID: Timestamp count H register (SR1, 11) */ + #define SL_TSCOUNTH 11 /*!< SelID: Timestamp count H register (SR1, 11) */ + #define SR_TSCTRL 2 /*!< RegID: Timestamp count control register (SR2, 11) */ + #define SL_TSCTRL 11 /*!< SelID: Timestamp count control register (SR2, 11) */ + #define SR_PMUMCTRL 8 /*!< RegID: Performance counter User mode control register (SR8, 11) */ + #define SL_PMUMCTRL 11 /*!< SelID: Performance counter User mode control register (SR8, 11) */ + #define SR_PMCTRL0 0 /*!< RegID: Performance count control 0 register (SR0, 14) */ + #define SL_PMCTRL0 14 /*!< SelID: Performance count control 0 register (SR0, 14) */ + #define SR_PMCTRL1 1 /*!< RegID: Performance count control 1 register (SR1, 14) */ + #define SL_PMCTRL1 14 /*!< SelID: Performance count control 1 register (SR1, 14) */ + #define SR_PMCTRL2 2 /*!< RegID: Performance count control 2 register (SR2, 14) */ + #define SL_PMCTRL2 14 /*!< SelID: Performance count control 2 register (SR2, 14) */ + #define SR_PMCTRL3 3 /*!< RegID: Performance count control 3 register (SR3, 14) */ + #define SL_PMCTRL3 14 /*!< SelID: Performance count control 3 register (SR3, 14) */ + #define SR_PMCTRL4 4 /*!< RegID: Performance count control 4 register (SR4, 14) */ + #define SL_PMCTRL4 14 /*!< SelID: Performance count control 4 register (SR4, 14) */ + #define SR_PMCTRL5 5 /*!< RegID: Performance count control 5 register (SR5, 14) */ + #define SL_PMCTRL5 14 /*!< SelID: Performance count control 5 register (SR5, 14) */ + #define SR_PMCTRL6 6 /*!< RegID: Performance count control 6 register (SR6, 14) */ + #define SL_PMCTRL6 14 /*!< SelID: Performance count control 6 register (SR6, 14) */ + #define SR_PMCTRL7 7 /*!< RegID: Performance count control 7 register (SR7, 14) */ + #define SL_PMCTRL7 14 /*!< SelID: Performance count control 7 register (SR7, 14) */ + #define SR_PMCOUNT0 16 /*!< RegID: Performance count 0 register (SR16, 14) */ + #define SL_PMCOUNT0 14 /*!< SelID: Performance count 0 register (SR16, 14) */ + #define SR_PMCOUNT1 17 /*!< RegID: Performance count 1 register (SR17, 14) */ + #define SL_PMCOUNT1 14 /*!< SelID: Performance count 1 register (SR17, 14) */ + #define SR_PMCOUNT2 18 /*!< RegID: Performance count 2 register (SR18, 14) */ + #define SL_PMCOUNT2 14 /*!< SelID: Performance count 2 register (SR18, 14) */ + #define SR_PMCOUNT3 19 /*!< RegID: Performance count 3 register (SR19, 14) */ + #define SL_PMCOUNT3 14 /*!< SelID: Performance count 3 register (SR19, 14) */ + #define SR_PMCOUNT4 20 /*!< RegID: Performance count 4 register (SR20, 14) */ + #define SL_PMCOUNT4 14 /*!< SelID: Performance count 4 register (SR20, 14) */ + #define SR_PMCOUNT5 21 /*!< RegID: Performance count 5 register (SR21, 14) */ + #define SL_PMCOUNT5 14 /*!< SelID: Performance count 5 register (SR21, 14) */ + #define SR_PMCOUNT6 22 /*!< RegID: Performance count 6 register (SR22, 14) */ + #define SL_PMCOUNT6 14 /*!< SelID: Performance count 6 register (SR22, 14) */ + #define SR_PMCOUNT7 23 /*!< RegID: Performance count 7 register (SR23, 14) */ + #define SL_PMCOUNT7 14 /*!< SelID: Performance count 7 register (SR23, 14) */ + #define SR_PMSUBCND0 0 /*!< RegID: Performance count subcondition 0 register (SR0, 15) */ + #define SL_PMSUBCND0 15 /*!< SelID: Performance count subcondition 0 register (SR0, 15) */ + #define SR_PMSUBCND1 1 /*!< RegID: Performance count subcondition 1 register (SR1, 15) */ + #define SL_PMSUBCND1 15 /*!< SelID: Performance count subcondition 1 register (SR1, 15) */ + #define SR_PMSUBCND2 2 /*!< RegID: Performance count subcondition 2 register (SR2, 15) */ + #define SL_PMSUBCND2 15 /*!< SelID: Performance count subcondition 2 register (SR2, 15) */ + #define SR_PMSUBCND3 3 /*!< RegID: Performance count subcondition 3 register (SR3, 15) */ + #define SL_PMSUBCND3 15 /*!< SelID: Performance count subcondition 3 register (SR3, 15) */ + #define SR_PMSUBCND4 4 /*!< RegID: Performance count subcondition 4 register (SR4, 15) */ + #define SL_PMSUBCND4 15 /*!< SelID: Performance count subcondition 4 register (SR4, 15) */ + #define SR_PMSUBCND5 5 /*!< RegID: Performance count subcondition 5 register (SR5, 15) */ + #define SL_PMSUBCND5 15 /*!< SelID: Performance count subcondition 5 register (SR5, 15) */ + #define SR_PMSUBCND6 6 /*!< RegID: Performance count subcondition 6 register (SR6, 15) */ + #define SL_PMSUBCND6 15 /*!< SelID: Performance count subcondition 6 register (SR6, 15) */ + #define SR_PMSUBCND7 7 /*!< RegID: Performance count subcondition 7 register (SR7, 15) */ + #define SL_PMSUBCND7 15 /*!< SelID: Performance count subcondition 7 register (SR7, 15) */ + +/*********************************************************************************************************************** + * Hardware Registers + **********************************************************************************************************************/ + #define SR_LSTEST0 0 /*!< RegID: Lock-step function self-diagnosis register 0 (SR0, 12) */ + #define SL_LSTEST0 12 /*!< SelID: Lock-step function self-diagnosis register 0 (SR0, 12) */ + #define SR_LSTEST1 1 /*!< RegID: Lock-step function self-diagnosis register 1 (SR1, 12) */ + #define SL_LSTEST1 12 /*!< SelID: Lock-step function self-diagnosis register 1 (SR1, 12) */ + #define SR_LSCFG 2 /*!< RegID: Lock-step function configuration (SR2, 12) */ + #define SL_LSCFG 12 /*!< SelID: Lock-step function configuration (SR2, 12) */ + #define SR_IFCR 5 /*!< RegID: Instruction fetch control register (SR5, 12) */ + #define SL_IFCR 12 /*!< SelID: Instruction fetch control register (SR5, 12) */ + #define SR_BRPCTRL0 8 /*!< RegID: Branch prediction function control register (SR8, 12) */ + #define SL_BRPCTRL0 12 /*!< SelID: Branch prediction function control register (SR8, 12) */ + #define SR_L1RCFG 12 /*!< RegID: L1RAM configuration (SR12, 13) */ + #define SL_L1RCFG 13 /*!< SelID: L1RAM configuration (SR12, 13) */ + #define SR_RDBCR 24 /*!< RegID: ROM data buffer control register (SR24, 13) */ + #define SL_RDBCR 13 /*!< SelID: ROM data buffer control register (SR24, 13) */ + #define SR_HVCFG 16 /*!< RegID: Setting virtualization support function (SR16, 1) */ + #define SL_HVCFG 1 /*!< SelID: Setting virtualization support function (SR16, 1) */ + +/*@} end of group RH850_CORE */ + +/** + * @ingroup RH850_G4MH_core_register + * @defgroup RH850_G4MH_core_bitfield Core register bit field macros + * @brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + * @{ + */ + +/** + * @brief Mask and shift a bit field value for use in a register bit range. + * @param[in] field Name of the register bit field. + * @param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + * @return Masked and shifted value. + */ + #define _VAL2FLD(field, value) (((uint32_t) (value) << field ## _Pos) & field ## _Msk) + +/** + * @brief Mask and shift a register value to extract a bit field value. + * @param[in] field Name of the register bit field. + * @param[in] value Value of register. This parameter is interpreted as an uint32_t type. + * @return Masked and shifted bit field value. + */ + #define _FLD2VAL(field, value) (((uint32_t) (value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group RH850_core_bitfield */ + +/*********************************************************************************************************************** + * RH850 definitions + **********************************************************************************************************************/ + +/** + * @defgroup RH850_Core_register RH850-Core Register + * @brief RH850-Core Register + * @{ + */ + +/** + * @defgroup RH850_G4MH_Core_register RH850 G4MH Core Register + * @brief RH850 G4MH Core Register + * @ingroup RH850_Core_register + * @{ + */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_SYS Basic System Register (SYS) + * @brief Type definitions for the basic sytem register (SYS) + * @{ + */ + +/** + * @brief Structure type to access the basic system register (SYS). + */ + +typedef union +{ + __IOM uint32_t EIPC; /*!< (@ 0x00000000) Status Save Register when Acknowledging EI Level + * Exception */ + + struct + { + __IOM uint32_t EIPC : 32; /*!< [31..0] These bits indicate the PC saved when an EI level exception + * isacknowledged.EIPC0:This bit indicates the PC saved when + * an EI level exception is acknowledged.Always set this bit + * to 0. Even if it is set to 1, the value transferred to + * the PCwhen the EIRET instruction is executed is 0. */ + } EIPC_b; +} RH850_SYS_EIPC_Type; + +typedef union +{ + __IOM uint32_t EIPSW; /*!< (@ 0x00000000) Status Save Register when Acknowledging EI Level + * Exception */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit stores the PSW.Z bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t S : 1; /*!< [1..1] This bit stores the PSW.S bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit stores the PSW.OV bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit stores the PSW.CY bit setting when an EI level + * exception isacknowledged. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit stores the PSW.SAT bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit stores the PSW.ID bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit stores the PSW.EP bit setting when an EI level + * exception isacknowledged */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit stores the PSW.NP bit setting when an EI level + * exception isacknowledged */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit stores the PSW.EBV bit setting when an EI + * level exception isacknowledged */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits store the PSW.CU2-0 field setting when an + * EI level exception isacknowledged */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This bit stores the PSW.EIMASK bit setting when an + * EI level exception isacknowledged */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit stores the PSW.UM bit setting when an EI level + * exception isacknowledged. */ + uint32_t : 1; + } EIPSW_b; +} RH850_SYS_EIPSW_Type; + +typedef union +{ + __IOM uint32_t FEPC; /*!< (@ 0x00000000) Status Save Register when Acknowledging FE Level + * Exception */ + + struct + { + __IOM uint32_t FEPC : 32; /*!< [31..0] This bit indicates the PC saved when an FE level exception + * isacknowledged.FEPC0: Always set this bit to 0. Even if + * it is set to 1, the value transferred to the PCwhen the + * FERET instruction is executed is 0. */ + } FEPC_b; +} RH850_SYS_FEPC_Type; + +typedef union +{ + __IOM uint32_t FEPSW; /*!< (@ 0x00000000) Status Save Register when Acknowledging FE Level + * Exception */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit stores the PSW.Z bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t S : 1; /*!< [1..1] This bit stores the PSW.S bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit stores the PSW.OV bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit stores the PSW.CY bit setting when an FE level + * exception isacknowledged. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit stores the PSW.SAT bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit stores the PSW.ID bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit stores the PSW.EP bit setting when an FE level + * exception isacknowledged */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit stores the PSW.NP bit setting when an FE level + * exception isacknowledged */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit stores the PSW.EBV bit setting when an FE + * level exception isacknowledged */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits store the PSW.CU2-0 field setting when an + * FE level exception isacknowledged */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This bit stores the PSW.EIMASK bit setting when an + * FE level exception isacknowledged */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit stores the PSW.UM bit setting when an FE level + * exception isacknowledged. */ + uint32_t : 1; + } FEPSW_b; +} RH850_SYS_FEPSW_Type; + +typedef union +{ + __IOM uint32_t PSW; /*!< (@ 0x00000000) Program Status Word */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit indicates whether or not the result of an operation + * is 0.0: Result of operation is not 0.1: Result of operation + * is 0. */ + __IOM uint32_t S : 1; /*!< [1..1] This bit indicates whether or not the result of an operation + * is negative.0: Result of operation is positive or 0.1: + * Result of operation is negative */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit indicates whether or not an overflow has occurred + * during anoperation.0: Overflow has not occurred.1: Overflow + * has occurred. */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit indicates whether a carry or borrow has occurred + * in the operationresult.0: Carry and borrow have not occurred.1: + * Carry or borrow has occurred. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit indicates that a saturation arithmetic operation + * instruction resulted inoverflow and saturation processing + * is applied to the result. This is acumulative flag, that + * is, it is set (1) once a saturation occurs and not cleared(0) + * by subsequent instructions with unsaturated results. This + * bit is cleared bythe LDSR instruction. Note that execution + * of an arithmetic operationinstruction neither set nor clear + * this flag.0: The result was not saturated1: The result + * was saturated */ + __IOM uint32_t ID : 1; /*!< [5..5] This bit disables the acknowledgement of EI level exception. + * When an EIlevel or FE level exception is acknowledged, + * this bit is set to 1 to disable theacknowledgement of EI + * level exception. As for the exceptions which the IDbit + * disables the acknowledgment, see Table 3.103, Exception + * Cause ListThis bit is also used to disable EI level exceptions + * from being acknowledgedas a critical section while an ordinary + * program or interrupt is being serviced.It is set to 1 when + * the DI instruction is executed */ + __IOM uint32_t EP : 1; /*!< [6..6] This bit indicates that an exception other than an interrupt + * is being serviced.It is set to 1 when the corresponding + * exception occurs. This bit does notaffect acknowledging + * an exception request even when it is set to 1.0: An exception + * other than an interrupt is not being serviced.1: An exception + * other than an interrupt is being serviced */ + __IOM uint32_t NP : 1; /*!< [7..7] This bit disables the acknowledgement of FE level exception. + * When an FElevel exception is acknowledged, this bit is + * set to 1 to disable theacknowledgement of EI level and + * FE level exceptions. As for the exceptionswhich the NP + * bit disables the acknowledgment, see Table 3.103, ExceptionCause + * List.0: The acknowledgement of FE level exception is enabled.1: + * The acknowledgement of FE level exception is disabled. */ + uint32_t : 7; + __IOM uint32_t EBV : 1; /*!< [15..15] This bit indicates the reset vector and exception vector + * operation. SeeSection 3.2.3.2(16), RBASE — Reset Vector + * Base Address and Section3.2.3.2(17), EBASE — Exception + * Handler Vector Address */ + __IOM uint32_t CU0 : 1; /*!< [16..16] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + __IOM uint32_t CU1 : 1; /*!< [17..17] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + __IOM uint32_t CU2 : 1; /*!< [18..18] These bits indicate the coprocessor use permissions. + * When the bitcorresponding to the coprocessor is 0, a coprocessor + * unusable exceptionoccurs if an instruction for the coprocessor + * is executed or a coprocessorresource (system register) + * is accessed.Bit 18 (CU2): Fixed to 0*2.Bit 17 (CU1): FXUBit + * 16 (CU0): FPUCU2 to CU0 are fixed to 0 in the devices that + * do not have correspondingcoprocessors. */ + uint32_t : 1; + __IOM uint32_t EIMASK : 6; /*!< [25..20] This field indicates the interrupt priority boundary + * between enabling anddisabling an acknowlegement of an interrupt + * (EIINTn). For an interrupt(EIINTn) with higher priority + * than the value set in this field, theacknowlegement is + * enabled. For an interrupt (EIINTn) with priority less thanor + * equal to the value set in this field, the acknowlegement + * is disabled.0: All priorities are not acceptable.1: Acceptable + * priority is 02: Acceptable priority is 0 to 1...62: Acceptable + * priority is 0 to 61 */ + uint32_t : 4; + __IOM uint32_t UM : 1; /*!< [30..30] This bit indicates that the CPU is in user mode (in + * UM mode).0: Supervisor mode1: User mode */ + uint32_t : 1; + } PSW_b; +} RH850_SYS_PSW_Type; + +typedef union +{ + __IOM uint32_t EIIC; /*!< (@ 0x00000000) EI Level Exception Cause */ + + struct + { + __IOM uint32_t EIIC : 32; /*!< [31..0] These bits store the exception cause code when an EI + * level exceptionoccurs. The EIIC15-0 field stores the exception + * cause codes shown in Table3.103, Exception Cause List. + * The EIIC31-16 field stores detailed exceptioncause codes + * defined individually for each exception. If there is no + * particulardefinition, these bits are set to 0. */ + } EIIC_b; +} RH850_SYS_EIIC_Type; + +typedef union +{ + __IOM uint32_t FEIC; /*!< (@ 0x00000000) FE Level Exception Cause */ + + struct + { + __IOM uint32_t FEIC : 32; /*!< [31..0] These bits store the exception cause code when an FE + * level exceptionoccurs. The FEIC15-0 field stores the exception + * cause codes shown inTable 3.103, Exception Cause List. + * The FEIC31-16 field stores detailedexception cause codes + * defined individually for each exception. If there is noparticular + * definition, these bits are set to 0. */ + } FEIC_b; +} RH850_SYS_FEIC_Type; + +typedef union +{ + __IOM uint32_t CTPC; /*!< (@ 0x00000000) Status Save Register when Executing CALLT */ + + struct + { + __IOM uint32_t CTPC : 32; /*!< [31..0] This bit indicates the PC of the instruction after the + * CALLT instruction.Always set this bit to 0. Even if it + * is set to 1, the value transferred to the PCwhen the CTRET + * instruction is executed is 0. */ + } CTPC_b; +} RH850_SYS_CTPC_Type; + +typedef union +{ + __IOM uint32_t CTPSW; /*!< (@ 0x00000000) Status Save Register when Executing CALLT */ + + struct + { + __IOM uint32_t Z : 1; /*!< [0..0] This bit indicates whether or not the result of an operation + * is 0.0: Result of operation is not 0.1: Result of operation + * is 0. */ + __IOM uint32_t S : 1; /*!< [1..1] This bit indicates whether or not the result of an operation + * is negative.0: Result of operation is positive or 0.1: + * Result of operation is negative */ + __IOM uint32_t OV : 1; /*!< [2..2] This bit indicates whether or not an overflow has occurred + * during anoperation.0: Overflow has not occurred.1: Overflow + * has occurred. */ + __IOM uint32_t CY : 1; /*!< [3..3] This bit indicates whether a carry or borrow has occurred + * in the operationresult.0: Carry and borrow have not occurred.1: + * Carry or borrow has occurred. */ + __IOM uint32_t SAT : 1; /*!< [4..4] This bit indicates that a saturation arithmetic operation + * instruction resulted inoverflow and saturation processing + * is applied to the result. This is acumulative flag, that + * is, it is set (1) once a saturation occurs and not cleared(0) + * by subsequent instructions with unsaturated results. This + * bit is cleared bythe LDSR instruction. Note that execution + * of an arithmetic operationinstruction neither set nor clear + * this flag.0: The result was not saturated1: The result + * was saturated */ + uint32_t : 27; + } CTPSW_b; +} RH850_SYS_CTPSW_Type; + +typedef union +{ + __IOM uint32_t CTBP; /*!< (@ 0x00000000) CALLT Base Pointer */ + + struct + { + __IM uint32_t CTBP0 : 1; /*!< [0..0] This bit indicates the base pointer address of the CALLT + * instruction.This bit indicates the start address of the + * table used by the CALLTinstruction. Always set this bit + * to 0. */ + __IOM uint32_t CTBP : 31; /*!< [31..1] This bit indicates the base pointer address of the CALLT + * instruction.This bit indicates the start address of the + * table used by the CALLTinstruction.CTBP0: Always set this + * bit to 0. */ + } CTBP_b; +} RH850_SYS_CTBP_Type; + +typedef union +{ + __IOM uint32_t SNZCFG; /*!< (@ 0x00000000) SNOOZE Configuration */ + + struct + { + __IOM uint32_t SNZCNT : 8; /*!< [7..0] These bits specify the number of clock cycles in which + * execution is to betemporarily halted by the SNOOZE instruction */ + uint32_t : 24; + } SNZCFG_b; +} RH850_SYS_SNZCFG_Type; + +typedef union +{ + __IOM uint32_t EIWR; /*!< (@ 0x00000000) EI Level Exception Working Register */ + + struct + { + __IOM uint32_t EIWR : 32; /*!< [31..0] These bits constitute a working register that can be + * used for any purposeduring the processing of an EI level + * exception. Use this register for purposessuch as storing + * the values of general-purpose registers */ + } EIWR_b; +} RH850_SYS_EIWR_Type; + +typedef union +{ + __IOM uint32_t FEWR; /*!< (@ 0x00000000) FE Level Exception Working Register */ + + struct + { + __IOM uint32_t FEWR : 32; /*!< [31..0] These bits constitute a working register that can be + * used for any purposeduring the processing of an FE level + * exception. Use this register forpurposes such as storing + * the values of general-purpose registers. */ + } FEWR_b; +} RH850_SYS_FEWR_Type; + +typedef union +{ + __IOM uint32_t SPID; /*!< (@ 0x00000000) System Protection Identifier */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits indicate the system protection identifier.The + * system protection identifier is a variable ID that is used + * for accessprotection in a product which consists of two + * or more bus masters includingthis CPU. For its uses and + * constraints on its value, see Section 3.10.7,Product information + * of initial value for G4MH register.Within this CPU, the + * SPID is used to check for area matching by the MPU. Itallows + * the system specifications defined for the product to be + * reflected in theMPU's protecti */ + uint32_t : 27; + } SPID_b; +} RH850_SYS_SPID_Type; + +typedef union +{ + __IOM uint32_t SPIDLIST; /*!< (@ 0x00000000) Legitimate System Protection Identifier List */ + + struct + { + __IM uint32_t SL : 32; /*!< [31..0] This bit indicates whether or not bit can be set as + * a system protection identifier */ + } SPIDLIST_b; +} RH850_SYS_SPIDLIST_Type; + +typedef union +{ + __IOM uint32_t RBASE; /*!< (@ 0x00000000) Reset Vector Base Address */ + + struct + { + __IM uint32_t RINT : 1; /*!< [0..0] When the RINT bit is set, the exception handler address + * for interruptprocessing is reduced. See Section 3.2.4.4(1)(a), + * Direct Vector Method.This bit is valid when PSW.EBV = 0. */ + __IM uint32_t DV : 1; /*!< [1..1] When the DV bit is set, the exception handler address + * for interrupt isdetermined by using the direct vector method. + * For details, see Section3.2.4.4(1)(b), Table Reference + * Method. This bit is valid when PSW.EBV =0. */ + uint32_t : 7; + __IM uint32_t RBASE : 23; /*!< [31..9] These bits indicate the reset vector when there is a + * reset. When PSW.EBV =0, this address is also used as the + * exception vector.The RBASE8 to RBASE0 bits are not assigned + * as names because these bitsare always 0. */ + } RBASE_b; +} RH850_SYS_RBASE_Type; + +typedef union +{ + __IOM uint32_t EBASE; /*!< (@ 0x00000000) Exception Handler Vector Address */ + + struct + { + __IOM uint32_t RINT : 1; /*!< [0..0] When the RINT bit is set, the exception handler address + * for interruptprocessing is reduced. See Section 3.2.4.4(1)(a), + * Direct Vector Method. */ + __IOM uint32_t DV : 1; /*!< [1..1] When the DV bit is set, the exception handler address + * for interrupt isdetermined by using the direct vector method. + * For details, see Section3.2.4.4(1)(b), Table Reference + * Method */ + uint32_t : 7; + __IOM uint32_t EBASE : 23; /*!< [31..9] The exception handler routine address is changed to + * the address resultingfrom adding the offset address of + * each exception to the base addressspecified for this register.The + * EBASE8 to EBASE0 bits are not assigned as names because + * these bitsare always 0. */ + } EBASE_b; +} RH850_SYS_EBASE_Type; + +typedef union +{ + __IOM uint32_t INTBP; /*!< (@ 0x00000000) Base Address of the Interrupt Handler Address + * Table */ + + struct + { + uint32_t : 9; + __IOM uint32_t INTBP : 23; /*!< [31..9] These bits indicate the base pointer address for an + * interrupt when the tablereference method is used.The value + * indicated by these bits is the first address in the table + * used todetermine the exception handler when the interrupt + * specified by the tablereference method (EIINTn) is acknowledged.The + * INTBP8 to INTBP0 bits are not assigned as names because + * these bitsare always 0. */ + } INTBP_b; +} RH850_SYS_INTBP_Type; + +typedef union +{ + __IOM uint32_t MCTL; /*!< (@ 0x00000000) Machine Control */ + + struct + { + __IOM uint32_t UIC : 1; /*!< [0..0] This bit is used to control the interrupt enable/disable + * operation in usermode. When this bit is set to 1, executing + * the EI/DI instruction in user modebecome possible */ + uint32_t : 31; + } MCTL_b; +} RH850_SYS_MCTL_Type; + +typedef union +{ + __IOM uint32_t SVLOCK; /*!< (@ 0x00000000) Supervisor Lock */ + + struct + { + __IOM uint32_t SVL : 1; /*!< [0..0] This bit specifies whether to restrict the CPU operation + * in supervisor mode.0: Does not restrict the CPU operation + * in supervisor mode.1: Restrict the CPU operation in supervisor + * mode.If the SVL bit is set to 1, the following system registers*1cannot + * be updated even when the CPU is in supervisor mode:SPID, + * MPM, MPLA, MPUA, MPAT, MPIDn, MPBK */ + uint32_t : 31; + } SVLOCK_b; +} RH850_SYS_SVLOCK_Type; + +typedef union +{ + __IOM uint32_t SCCFG; /*!< (@ 0x00000000) SYSCALL Operation Setting */ + + struct + { + __IOM uint32_t SIZE : 8; /*!< [7..0] These bits specify the maximum number of entries of a + * table that theSYSCALL instruction references. The maximum + * number of entries theSYSCALL instruction references is + * 1 if SIZE is 0, and 256 if SIZE is 255. Bysetting the maximum + * number of entries appropriately in accordance with thenumber + * of functions branched by the SYSCALL instruction, the memory + * areacan be effectively used.If a vector exceeding the maximum + * number of entries is specified for theSYSCALL instruction, + * the first entry is select */ + uint32_t : 24; + } SCCFG_b; +} RH850_SYS_SCCFG_Type; + +typedef union +{ + __IOM uint32_t SCBP; /*!< (@ 0x00000000) SYSCALL Base Pointer */ + + struct + { + __IOM uint32_t SCBP : 32; /*!< [31..0] These bits indicate the base pointer address of the + * SYSCALL instruction.These bits indicate the start address + * of the table used by the SYSCALLinstruction.SCBP[0:1]: + * Always set these bits to 0. */ + } SCBP_b; +} RH850_SYS_SCBP_Type; + +typedef union +{ + __IOM uint32_t PEID; /*!< (@ 0x00000000) Processor Element Identifier */ + + struct + { + __IM uint32_t PEID : 5; /*!< [4..0] These bits indicate the processor element identifier. */ + uint32_t : 27; + } PEID_b; +} RH850_SYS_PEID_Type; + +typedef union +{ + __IOM uint32_t BMID; /*!< (@ 0x00000000) Bus Master Identifier */ + + struct + { + __IM uint32_t BMID : 5; /*!< [4..0] These bits indicate the bus master identifier */ + uint32_t : 27; + } BMID_b; +} RH850_SYS_BMID_Type; + +typedef union +{ + __IOM uint32_t MEA; /*!< (@ 0x00000000) Memory Error Address */ + + struct + { + __IOM uint32_t MEA : 32; /*!< [31..0] These bits holds the address in which an MAE (misalignment) + * or MPUviolation occurred. */ + } MEA_b; +} RH850_SYS_MEA_Type; + +typedef union +{ + __IOM uint32_t MEI; /*!< (@ 0x00000000) Memory Error Information */ + + struct + { + __IOM uint32_t RW : 1; /*!< [0..0] This bit indicates whether the operation performed by + * the instruction thatcaused the exception is a read (Load-memory) + * or a write (Store-memory).0: Read (Load-memory)1: Write + * (Store-memory) */ + __IOM uint32_t ITYPE : 5; /*!< [5..1] These bits indicate the instruction that caused the exception */ + uint32_t : 2; + __IOM uint32_t U : 1; /*!< [8..8] This bit indicates the sign extension method of the instruction + * that causedthe exception.0: Signed1: Unsigned */ + __IOM uint32_t DS : 3; /*!< [11..9] These bits indicate the data type of the instruction + * that caused theexception*1.0: Byte (8 bits)1: Halfword + * (16 bits)2: Word (32 bits)3: Double-word (64 bits)4: Quad-word + * (128 bits) */ + uint32_t : 4; + __IOM uint32_t REG : 5; /*!< [20..16] These bits indicate the source register number or destination + * registernumber of the instruction that caused the exception */ + uint32_t : 7; + __IOM uint32_t LEN : 4; /*!< [31..28] These bits indicate the code size of the instruction + * that causes the exception.0: Non-instruction factor2: 16 + * bits4: 32 bits6: 48 bits8 :64 bits */ + } MEI_b; +} RH850_SYS_MEI_Type; + +typedef union +{ + __IOM uint32_t RBCR0; /*!< (@ 0x00000000) Register Bank Control 0 */ + + struct + { + __IOM uint32_t BE : 15; /*!< [14..0] These bits specify the priority level of the interrupt + * on which the register bankis to be used.0: Do not use the + * register bank on an interrupt of the level corresponding + * tothis bit.1: Use the register bank on an interrupt of + * the level corresponding to thisbit. */ + __IOM uint32_t BE15 : 1; /*!< [15..15] This bit specifies whether to use a register bank on + * an interrupt (EIINTn) withpriority 15 to 630: Do not use + * the register bank on an interrupt with the priority 15 + * to 631: Use the register bank on an interrupt with the + * priority 15 to 63While this bit is set to 1, if EI level + * interrupt (EIINTn) with priority 15 to 63 isacknowledged, + * the register bank function can be used. */ + __IOM uint32_t MD : 1; /*!< [16..16] This bit specifies the save mode of the register bank.0: + * Save mode 01: Save mode 1 */ + uint32_t : 15; + } RBCR0_b; +} RH850_SYS_RBCR0_Type; + +typedef union +{ + __IOM uint32_t RBCR1; /*!< (@ 0x00000000) Register Bank Control 1 */ + + struct + { + __IOM uint32_t NC : 15; /*!< [14..0] These bits specify the priority level of the interrupt + * on which the register bankis to be used.0: Do not use the + * register bank on an interrupt of the level corresponding + * tothis bit.1: Use the register bank on an interrupt of + * the level corresponding to thisbit. */ + __IOM uint32_t NC15 : 1; /*!< [15..15] This bit specifies whether to use a register bank on + * an interrupt (EIINTn) withpriority 15 to 630: Do not use + * the register bank on an interrupt with the priority 15 + * to 631: Use the register bank on an interrupt with the + * priority 15 to 63While this bit is set to 1, if EI level + * interrupt (EIINTn) with priority 15 to 63 isacknowledged, + * the register bank function can be used. */ + uint32_t : 16; + } RBCR1_b; +} RH850_SYS_RBCR1_Type; + +typedef union +{ + __IOM uint32_t RBNR; /*!< (@ 0x00000000) Register Bank Number */ + + struct + { + __IOM uint32_t BN : 6; /*!< [5..0] These bits indicate the number of the register bank to + * be used next.The value in these bits is incremented by + * 1 when an interrupt (EIINTn) thatuses a register bank is + * accepted. If the value of BN is larger thanINTCFG.ULNR, + * or if the value of BN is 63, if an interrupt (EIINTn) using + * theregister bank occurs, a SYSERR exception is generated. + * That interrupt is notaccepted, and it is put on hold.The + * value of BN is decremented by 1 when a RESBANK instruction + * isexecuted. If the RESBANK instruction i */ + uint32_t : 26; + } RBNR_b; +} RH850_SYS_RBNR_Type; + +typedef union +{ + __IOM uint32_t RBIP; /*!< (@ 0x00000000) Register Bank Initial Pointer */ + + struct + { + uint32_t : 4; + __IOM uint32_t RBIP : 28; /*!< [31..4] These bits indicate the initial pointer to the register + * bank.The values of RBCR0.MD and RBNR.BN together with this + * value determinethe memory address to which the next register + * bank to be used is allocatedas follows.• Save mode 0 + * (RBCR0.MD = 0): RBIP - RBNR.BN × 60H• Save mode 1 + * (RBCR0.MD = 1): RBIP - RBNR.BN × 90H */ + } RBIP_b; +} RH850_SYS_RBIP_Type; + +/** @brief Basic system register macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_SYS ================ */ +/* ================================================================================================================== */ + +/* ========================================================= EIPC ================================================= */ + #define R_SYS_EIPC_EIPC_Pos (0UL) /*!< EIPC (Bit 0) */ + #define R_SYS_EIPC_EIPC_Msk (0xffffffffUL) /*!< EIPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EIPSW ================================================ */ + #define R_SYS_EIPSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_EIPSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_EIPSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_EIPSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_EIPSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_EIPSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_EIPSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_EIPSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_EIPSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_EIPSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_EIPSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_EIPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_EIPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_EIPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_EIPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_EIPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_EIPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= FEPC ================================================= */ + #define R_SYS_FEPC_FEPC_Pos (0UL) /*!< FEPC (Bit 0) */ + #define R_SYS_FEPC_FEPC_Msk (0xffffffffUL) /*!< FEPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEPSW ================================================ */ + #define R_SYS_FEPSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_FEPSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_FEPSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_FEPSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_FEPSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_FEPSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_FEPSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_FEPSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_FEPSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_FEPSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_FEPSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_FEPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_FEPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_FEPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_FEPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_FEPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_FEPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================== PSW ================================================= */ + #define R_SYS_PSW_UM_Pos (30UL) /*!< UM (Bit 30) */ + #define R_SYS_PSW_UM_Msk (0x40000000UL) /*!< UM (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EIMASK_Pos (20UL) /*!< EIMASK (Bit 20) */ + #define R_SYS_PSW_EIMASK_Msk (0x3f00000UL) /*!< EIMASK (Bitfield-Mask: 0x3f) */ + #define R_SYS_PSW_CU2_Pos (18UL) /*!< CU2 (Bit 18) */ + #define R_SYS_PSW_CU2_Msk (0x40000UL) /*!< CU2 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CU1_Pos (17UL) /*!< CU1 (Bit 17) */ + #define R_SYS_PSW_CU1_Msk (0x20000UL) /*!< CU1 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CU0_Pos (16UL) /*!< CU0 (Bit 16) */ + #define R_SYS_PSW_CU0_Msk (0x10000UL) /*!< CU0 (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EBV_Pos (15UL) /*!< EBV (Bit 15) */ + #define R_SYS_PSW_EBV_Msk (0x8000UL) /*!< EBV (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_NP_Pos (7UL) /*!< NP (Bit 7) */ + #define R_SYS_PSW_NP_Msk (0x80UL) /*!< NP (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_EP_Pos (6UL) /*!< EP (Bit 6) */ + #define R_SYS_PSW_EP_Msk (0x40UL) /*!< EP (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_ID_Pos (5UL) /*!< ID (Bit 5) */ + #define R_SYS_PSW_ID_Msk (0x20UL) /*!< ID (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_PSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_PSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_PSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_PSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_PSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_PSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= EIIC ================================================= */ + #define R_SYS_EIIC_EIIC_Pos (0UL) /*!< EIIC (Bit 0) */ + #define R_SYS_EIIC_EIIC_Msk (0xffffffffUL) /*!< EIIC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEIC ================================================= */ + #define R_SYS_FEIC_FEIC_Pos (0UL) /*!< FEIC (Bit 0) */ + #define R_SYS_FEIC_FEIC_Msk (0xffffffffUL) /*!< FEIC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CTPC ================================================= */ + #define R_SYS_CTPC_CTPC_Pos (0UL) /*!< CTPC (Bit 0) */ + #define R_SYS_CTPC_CTPC_Msk (0xffffffffUL) /*!< CTPC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CTPSW ================================================ */ + #define R_SYS_CTPSW_SAT_Pos (4UL) /*!< SAT (Bit 4) */ + #define R_SYS_CTPSW_SAT_Msk (0x10UL) /*!< SAT (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_CY_Pos (3UL) /*!< CY (Bit 3) */ + #define R_SYS_CTPSW_CY_Msk (0x8UL) /*!< CY (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_OV_Pos (2UL) /*!< OV (Bit 2) */ + #define R_SYS_CTPSW_OV_Msk (0x4UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_S_Pos (1UL) /*!< S (Bit 1) */ + #define R_SYS_CTPSW_S_Msk (0x2UL) /*!< S (Bitfield-Mask: 0x01) */ + #define R_SYS_CTPSW_Z_Pos (0UL) /*!< Z (Bit 0) */ + #define R_SYS_CTPSW_Z_Msk (0x1UL) /*!< Z (Bitfield-Mask: 0x01) */ +/* ========================================================= CTBP ================================================= */ + #define R_SYS_CTBP_CTBP_Pos (1UL) /*!< CTBP (Bit 1) */ + #define R_SYS_CTBP_CTBP_Msk (0xfffffffeUL) /*!< CTBP (Bitfield-Mask: 0x7fffffff) */ + #define R_SYS_CTBP_CTBP0_Pos (0UL) /*!< CTBP0 (Bit 0) */ + #define R_SYS_CTBP_CTBP0_Msk (0x1UL) /*!< CTBP0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZCFG ================================================ */ + #define R_SYS_SNZCFG_SNZCNT_Pos (0UL) /*!< SNZCNT (Bit 0) */ + #define R_SYS_SNZCFG_SNZCNT_Msk (0xffUL) /*!< SNZCNT (Bitfield-Mask: 0xff) */ +/* ========================================================= EIWR ================================================= */ + #define R_SYS_EIWR_EIWR_Pos (0UL) /*!< EIWR (Bit 0) */ + #define R_SYS_EIWR_EIWR_Msk (0xffffffffUL) /*!< EIWR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FEWR ================================================= */ + #define R_SYS_FEWR_FEWR_Pos (0UL) /*!< FEWR (Bit 0) */ + #define R_SYS_FEWR_FEWR_Msk (0xffffffffUL) /*!< FEWR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SPID ================================================= */ + #define R_SYS_SPID_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_SYS_SPID_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ======================================================= SPIDLIST =============================================== */ + #define R_SYS_SPIDLIST_SL_Pos (0UL) /*!< SL (Bit 0) */ + #define R_SYS_SPIDLIST_SL_Msk (0xffffffffUL) /*!< SL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RBASE ================================================ */ + #define R_SYS_RBASE_RBASE_Pos (9UL) /*!< RBASE (Bit 9) */ + #define R_SYS_RBASE_RBASE_Msk (0xfffffe00UL) /*!< RBASE (Bitfield-Mask: 0x7fffff) */ + #define R_SYS_RBASE_DV_Pos (1UL) /*!< DV (Bit 1) */ + #define R_SYS_RBASE_DV_Msk (0x2UL) /*!< DV (Bitfield-Mask: 0x01) */ + #define R_SYS_RBASE_RINT_Pos (0UL) /*!< RINT (Bit 0) */ + #define R_SYS_RBASE_RINT_Msk (0x1UL) /*!< RINT (Bitfield-Mask: 0x01) */ +/* ========================================================= EBASE ================================================ */ + #define R_SYS_EBASE_EBASE_Pos (9UL) /*!< EBASE (Bit 9) */ + #define R_SYS_EBASE_EBASE_Msk (0xfffffe00UL) /*!< EBASE (Bitfield-Mask: 0x7fffff) */ + #define R_SYS_EBASE_DV_Pos (1UL) /*!< DV (Bit 1) */ + #define R_SYS_EBASE_DV_Msk (0x2UL) /*!< DV (Bitfield-Mask: 0x01) */ + #define R_SYS_EBASE_RINT_Pos (0UL) /*!< RINT (Bit 0) */ + #define R_SYS_EBASE_RINT_Msk (0x1UL) /*!< RINT (Bitfield-Mask: 0x01) */ +/* ========================================================= INTBP ================================================ */ + #define R_SYS_INTBP_INTBP_Pos (9UL) /*!< INTBP (Bit 9) */ + #define R_SYS_INTBP_INTBP_Msk (0xfffffe00UL) /*!< INTBP (Bitfield-Mask: 0x7fffff) */ +/* ========================================================= MCTL ================================================= */ + #define R_SYS_MCTL_UIC_Pos (0UL) /*!< UIC (Bit 0) */ + #define R_SYS_MCTL_UIC_Msk (0x1UL) /*!< UIC (Bitfield-Mask: 0x01) */ +/* ======================================================== SVLOCK ================================================ */ + #define R_SYS_SVLOCK_SVL_Pos (0UL) /*!< SVL (Bit 0) */ + #define R_SYS_SVLOCK_SVL_Msk (0x1UL) /*!< SVL (Bitfield-Mask: 0x01) */ +/* ========================================================= SCCFG ================================================ */ + #define R_SYS_SCCFG_SIZE_Pos (0UL) /*!< SIZE (Bit 0) */ + #define R_SYS_SCCFG_SIZE_Msk (0xffUL) /*!< SIZE (Bitfield-Mask: 0xff) */ +/* ========================================================= SCBP ================================================= */ + #define R_SYS_SCBP_SCBP_Pos (0UL) /*!< SCBP (Bit 0) */ + #define R_SYS_SCBP_SCBP_Msk (0xffffffffUL) /*!< SCBP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PEID ================================================= */ + #define R_SYS_PEID_PEID_Pos (0UL) /*!< PEID (Bit 0) */ + #define R_SYS_PEID_PEID_Msk (0x1fUL) /*!< PEID (Bitfield-Mask: 0x1f) */ +/* ========================================================= BMID ================================================= */ + #define R_SYS_BMID_BMID_Pos (0UL) /*!< BMID (Bit 0) */ + #define R_SYS_BMID_BMID_Msk (0x1fUL) /*!< BMID (Bitfield-Mask: 0x1f) */ +/* ========================================================== MEA ================================================= */ + #define R_SYS_MEA_MEA_Pos (0UL) /*!< MEA (Bit 0) */ + #define R_SYS_MEA_MEA_Msk (0xffffffffUL) /*!< MEA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MEI ================================================= */ + #define R_SYS_MEI_LEN_Pos (28UL) /*!< LEN (Bit 28) */ + #define R_SYS_MEI_LEN_Msk (0xf0000000UL) /*!< LEN (Bitfield-Mask: 0x0f) */ + #define R_SYS_MEI_REG_Pos (16UL) /*!< REG (Bit 16) */ + #define R_SYS_MEI_REG_Msk (0x1f0000UL) /*!< REG (Bitfield-Mask: 0x1f) */ + #define R_SYS_MEI_DS_Pos (9UL) /*!< DS (Bit 9) */ + #define R_SYS_MEI_DS_Msk (0xe00UL) /*!< DS (Bitfield-Mask: 0x07) */ + #define R_SYS_MEI_U_Pos (8UL) /*!< U (Bit 8) */ + #define R_SYS_MEI_U_Msk (0x100UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_SYS_MEI_ITYPE_Pos (1UL) /*!< ITYPE (Bit 1) */ + #define R_SYS_MEI_ITYPE_Msk (0x3eUL) /*!< ITYPE (Bitfield-Mask: 0x1f) */ + #define R_SYS_MEI_RW_Pos (0UL) /*!< RW (Bit 0) */ + #define R_SYS_MEI_RW_Msk (0x1UL) /*!< RW (Bitfield-Mask: 0x01) */ +/* ========================================================= RBCR0 ================================================ */ + #define R_SYS_RBCR0_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_SYS_RBCR0_MD_Msk (0x10000UL) /*!< MD (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR0_BE15_Pos (15UL) /*!< BE15 (Bit 15) */ + #define R_SYS_RBCR0_BE15_Msk (0x8000UL) /*!< BE15 (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR0_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_SYS_RBCR0_BE_Msk (0x7fffUL) /*!< BE (Bitfield-Mask: 0x7fff) */ +/* ========================================================= RBCR1 ================================================ */ + #define R_SYS_RBCR1_NC15_Pos (15UL) /*!< NC15 (Bit 15) */ + #define R_SYS_RBCR1_NC15_Msk (0x8000UL) /*!< NC15 (Bitfield-Mask: 0x01) */ + #define R_SYS_RBCR1_NC_Pos (0UL) /*!< NC (Bit 0) */ + #define R_SYS_RBCR1_NC_Msk (0x7fffUL) /*!< NC (Bitfield-Mask: 0x7fff) */ +/* ========================================================= RBNR ================================================= */ + #define R_SYS_RBNR_BN_Pos (0UL) /*!< BN (Bit 0) */ + #define R_SYS_RBNR_BN_Msk (0x3fUL) /*!< BN (Bitfield-Mask: 0x3f) */ +/* ========================================================= RBIP ================================================= */ + #define R_SYS_RBIP_RBIP_Pos (4UL) /*!< RBIP (Bit 4) */ + #define R_SYS_RBIP_RBIP_Msk (0xfffffff0UL) /*!< RBIP (Bitfield-Mask: 0xfffffff) */ +/* ========================================================= PID ================================================== */ + #define R_MPU_PID_MPU_Pos (8UL) /*!< MPU (Bit 8) */ + #define R_MPU_PID_MPU_Msk (0x100UL) /*!< MPU (Bitfield-Mask: 0x7f) */ + +/*@}*/ /* end of group RH850_G4MH_SYS */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_IRQ Interrupt Function Registers (IRQ) + * @brief Type definitions for the Interrupt Function Registers (IRQ) + * @{ + */ + +/** + * @brief Structure type to access the Interrupt Function Registers (SYS). + */ + +typedef union +{ + __IOM uint32_t ISPR; /*!< (@ 0x00000000) Priority of Interrupt being Serviced */ + + struct + { + __IM uint32_t ISP : 16; /*!< [15..0] These bits indicate the acknowledgment status of an + * EIINTn interrupt with apriority*1 that corresponds to the + * relevant bit position.0: An interrupt request for an interrupt + * whose priority corresponds to therelevant bit position + * has not been acknowledged.1: An interrupt request for an + * interrupt whose priority corresponds to therelevant position + * is being serviced by the CPU core. */ + uint32_t : 16; + } ISPR_b; +} RH850_IRQ_ISPR_Type; + +typedef union +{ + __IOM uint32_t IMSR; /*!< (@ 0x00000000) Interrupt Mask Status */ + + struct + { + __IOM uint32_t EEIM : 1; /*!< [0..0] This bit specifies the existence of EIINT whose acceptance + * is masked byISPR.ISP when INTCFG.EPL is cleared to 0 or + * PSW.EIMASK whenINTCFG.EPL is set to 1.0: EIINT masked by + * ISPR.ISP or PSW.EIMASK does not exist1: EIINT masked by + * ISPR.ISP or PSW.EIMASK exists */ + __IOM uint32_t EPLM : 1; /*!< [1..1] This bit specifies the existence of EIINT whose acceptance + * is masked byPLMR.PLM.0: EIINT masked by PLMR.PLM does not + * exist1: EIINT masked by PLMR.PLM exists */ + __IOM uint32_t EID : 1; /*!< [2..2] This bit specifies the existence of EIINT whose acceptance + * is masked byPSW.ID.0: EIINT masked by PSW.ID does not exist1: + * EIINT masked by PSW.ID exists */ + __IOM uint32_t ENP : 1; /*!< [3..3] This bit specifies the existence of EIINT whose acceptance + * is masked byPSW.NP.0: EIINT masked by PSW.NP does not exist1: + * EIINT masked by PSW.NP does exists */ + __IOM uint32_t FNP : 1; /*!< [4..4] This bit specifies the existence of FEINT whose acceptance + * is masked byPSW.NP.0: FEINT masked by PSW.NP does not exist1: + * FEINT masked by PSW.NP does exists */ + uint32_t : 27; + } IMSR_b; +} RH850_IRQ_IMSR_Type; + +typedef union +{ + __IOM uint32_t ICSR; /*!< (@ 0x00000000) Interrupt Control Status */ + + struct + { + __IM uint32_t PMEI : 1; /*!< [0..0] This bit specifies the existence of EIINT whose acceptance + * is masked byISPR.ISP when INTCFG.EPL is cleared to 0 or + * PSW.EIMASK whenINTCFG.EPL is set to 1.0: EIINT masked by + * ISPR.ISP or PSW.EIMASK does not exist1: EIINT masked by + * ISPR.ISP or PSW.EIMASK exists */ + uint32_t : 31; + } ICSR_b; +} RH850_IRQ_ICSR_Type; + +typedef union +{ + __IOM uint32_t INTCFG; /*!< (@ 0x00000000) Interrupt Function Setting */ + + struct + { + __IOM uint32_t ISPC : 1; /*!< [0..0] This bit changes how the ISPR register is written.0: + * The ISPR register is automatically updated. Updates triggered + * by theprogram (via execution of LDSR instruction) are ignored.1: + * The ISPR register is not automatically updated. Updates + * triggered by theprogram (via execution of LDSR instruction) + * are performed. */ + __IOM uint32_t EPL : 1; /*!< [1..1] For the interrupt (EIINTn), specify whether to enable + * interrupt priority levelextension function.0: Interrupt + * priority level extension function is disabled1: Interrupt + * priority level extension function is enabled */ + uint32_t : 14; + __IOM uint32_t ULNR : 6; /*!< [21..16] Specifying the maximum value of available register + * bank numbers.If the value of the RBNR.BN is bigger than + * the ULNR, or the value of theRBNR.BN is 63; and the interrupt + * (EIINTn) whose register bank function isenable occurs, + * the SYSERR exception will occur. Note that the interrupt(EIINTn) + * is not accepted and is held. */ + uint32_t : 10; + } INTCFG_b; +} RH850_IRQ_INTCFG_Type; + +typedef union +{ + __IOM uint32_t PLMR; /*!< (@ 0x00000000) Interrupt Priority Level Mask */ + + struct + { + __IOM uint32_t PLM : 6; /*!< [5..0] These bits are used to mask the interrupts (EIINTn) whose + * priority level is nothigher than the level specified by + * these bits.When an interrupt (EIINTn) is masked by this + * register, it is not accepted. */ + uint32_t : 26; + } PLMR_b; +} RH850_IRQ_PLMR_Type; + +typedef union +{ + __IOM uint32_t EEIC; /*!< (@ 0x00000200) Extended EI Level Interrupt Control Register + * [0..31] */ + + struct + { + __IOM uint32_t EIP : 6; /*!< [5..0] These bits specify 64 interrupt priority levels (0: highest + * priority, 63: lowestpriority).If two or more EI level interrupt + * requests are generated simultaneously, a sourcewith higher + * priority specified by these bits is selected and is sent + * to the CPUcore. If the priority specified by these bits + * is equal, a source of less-numberchannel is selected as + * fixed priority. Please note that the interrupt (EIINTn) + * withpriority level 63 is not acknowledged in any case. + * For details, see Section3.2.4.1(5), Interrupt Ex */ + uint32_t : 9; + __IOM uint32_t EIOV : 1; /*!< [15..15] Interrupt Overflow0: No interrupt overflow1: EIINTn + * rose in edge-detection mode (mode_Eict[n] = 0) when EEICn.EIRF= + * 1.This bit is independent of write access to EEICn.EIRF. + * If EEICn.EIRF=1,EEICn.EIOVn=0, and 1 is written to EEICn.EIRF + * by 8-bit access, EEICn.EIOV isNOT set. */ + uint32_t : 6; + __IOM uint32_t EITB : 1; /*!< [22..22] Interrupt Vector Method Select0: Direct branching method + * based on priority1: Table referencing method */ + __IOM uint32_t EIMK : 1; /*!< [23..23] Interrupt MaskIf this bit is set to 1, interrupt requests + * set in the interrupt request flag (EIRFn)are masked to + * inhibit interrupt requests from the channel to the CPU + * core.Notification of presence of unprocessed interrupts + * is not made and the PMEI bitin ICSR is not set from channels + * for which this bit is set to 1.Even when the interrupt + * request from the channel is masked with EIMKn = 1,the EIRFn + * still reflects the interrupt request for the channel and + * can be polled insoftware. When the EIMKn bit is cleare */ + uint32_t : 4; + __IOM uint32_t EIRF : 1; /*!< [28..28] Interrupt Request FlagOperation varies with the interrupt + * input interface.0: No interrupt request (Initial value)1: + * Interrupt request present• Edge detectionThis flag is + * automatically cleared to 0 when an interrupt request of + * thechannel is accepted by the CPU core.• Level detectionThis + * bit cannot be set or cleared by the software. This is a + * read-only bit. */ + uint32_t : 2; + __IM uint32_t EICT : 1; /*!< [31..31] This bit indicates the type of an interrupt detection. + * This bit is read only.0: Detection with an edge1: Detection + * of the levelWritten value to this bit must be the value + * after reset. */ + } EEIC_b; +} RH850_IRQ_EEIC_Type; + +typedef union +{ + __IOM uint32_t EIBD; /*!< (@ 0x00000100) EI Level Interrupt Bind Register [0..31]These + * registers are provided for each EI level + * interrupt source to define binding between + * interruptsources and PEs. For details on + * each of the interrupt sources, see the Interrupt + * table. */ + + struct + { + __IM uint32_t PEID : 3; /*!< [2..0] These bits specify the interrupt bind (request) destination.These + * bits are fixed in EIBD0 to EIBD31 and cannot be modified.000: + * Interrupt is bound to PE0.001: Interrupt is bound to PE1.010: + * Interrupt is bound to PE2.011: Interrupt is bound to PE3.100: + * Interrupt is bound to PE4.101: Interrupt is bound to PE5. */ + uint32_t : 29; + } EIBD_b; +} RH850_IRQ_EIBD_INTC1_Type; + +typedef union +{ + __IOM uint32_t EIBD; /*!< (@ 0x00002000) EI Level Interrupt Bind Register [32..1023]These + * registers are provided for each EI level + * interrupt source to define binding between + * interruptsources and PEs. For details on + * each of the interrupt sources, see the Interrupt + * table. */ + + struct + { + __IOM uint32_t PEID : 3; /*!< [2..0] These bits specify the interrupt bind (request) destination.These + * bits are fixed in EIBD0 to EIBD31 and cannot be modified.000: + * Interrupt is bound to PE0.001: Interrupt is bound to PE1.010: + * Interrupt is bound to PE2.011: Interrupt is bound to PE3.100: + * Interrupt is bound to PE4.101: Interrupt is bound to PE5. */ + uint32_t : 29; + } EIBD_b; +} RH850_IRQ_EIBD_INTC2_Type; + +/** @brief Interrupt Function Registers macro Definitions */ +/* ================================================================================================================== */ +/* ================ R_IRQ ================ */ +/* ================================================================================================================== */ + +/* ========================================================= ISPR ================================================= */ + #define R_IRQ_ISPR_ISP_Pos (0UL) /*!< ISP (Bit 0) */ + #define R_IRQ_ISPR_ISP_Msk (0xffffUL) /*!< ISP (Bitfield-Mask: 0xffff) */ +/* ========================================================= IMSR ================================================= */ + #define R_IRQ_IMSR_FNP_Pos (4UL) /*!< FNP (Bit 4) */ + #define R_IRQ_IMSR_FNP_Msk (0x10UL) /*!< FNP (Bitfield-Mask: 0x01) */ + #define R_IRQ_IMSR_ENP_Pos (3UL) /*!< ENP (Bit 3) */ + #define R_IRQ_IMSR_ENP_Msk (0x8UL) /*!< ENP (Bitfield-Mask: 0x01) */ + #define R_IRQ_IMSR_EID_Pos (2UL) /*!< EID (Bit 2) */ + #define R_IRQ_IMSR_EID_Msk (0x4UL) /*!< EID (Bitfield-Mask: 0x01) */ + #define R_IRQ_IMSR_EPLM_Pos (1UL) /*!< EPLM (Bit 1) */ + #define R_IRQ_IMSR_EPLM_Msk (0x2UL) /*!< EPLM (Bitfield-Mask: 0x01) */ + #define R_IRQ_IMSR_EEIM_Pos (0UL) /*!< EEIM (Bit 0) */ + #define R_IRQ_IMSR_EEIM_Msk (0x1UL) /*!< EEIM (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR ================================================= */ + #define R_IRQ_ICSR_PMEI_Pos (0UL) /*!< PMEI (Bit 0) */ + #define R_IRQ_ICSR_PMEI_Msk (0x1UL) /*!< PMEI (Bitfield-Mask: 0x01) */ +/* ======================================================== INTCFG ================================================ */ + #define R_IRQ_INTCFG_ULNR_Pos (16UL) /*!< ULNR (Bit 16) */ + #define R_IRQ_INTCFG_ULNR_Msk (0x3f0000UL) /*!< ULNR (Bitfield-Mask: 0x3f) */ + #define R_IRQ_INTCFG_EPL_Pos (1UL) /*!< EPL (Bit 1) */ + #define R_IRQ_INTCFG_EPL_Msk (0x2UL) /*!< EPL (Bitfield-Mask: 0x01) */ + #define R_IRQ_INTCFG_ISPC_Pos (0UL) /*!< ISPC (Bit 0) */ + #define R_IRQ_INTCFG_ISPC_Msk (0x1UL) /*!< ISPC (Bitfield-Mask: 0x01) */ +/* ========================================================= PLMR ================================================= */ + #define R_IRQ_PLMR_PLM_Pos (0UL) /*!< PLM (Bit 0) */ + #define R_IRQ_PLMR_PLM_Msk (0x3fUL) /*!< PLM (Bitfield-Mask: 0x3f) */ +/* ========================================================= EEIC ================================================= */ + #define R_IRQ_EEIC_EICT_Pos (31UL) /*!< EICT (Bit 31) */ + #define R_IRQ_EEIC_EICT_Msk (0x80000000UL) /*!< EICT (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIRF_Pos (28UL) /*!< EIRF (Bit 28) */ + #define R_IRQ_EEIC_EIRF_Msk (0x10000000UL) /*!< EIRF (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIMK_Pos (23UL) /*!< EIMK (Bit 23) */ + #define R_IRQ_EEIC_EIMK_Msk (0x800000UL) /*!< EIMK (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EITB_Pos (22UL) /*!< EITB (Bit 22) */ + #define R_IRQ_EEIC_EITB_Msk (0x400000UL) /*!< EITB (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIOV_Pos (15UL) /*!< EIOV (Bit 15) */ + #define R_IRQ_EEIC_EIOV_Msk (0x8000UL) /*!< EIOV (Bitfield-Mask: 0x01) */ + #define R_IRQ_EEIC_EIP_Pos (0UL) /*!< EIP (Bit 0) */ + #define R_IRQ_EEIC_EIP_Msk (0x3fUL) /*!< EIP (Bitfield-Mask: 0x3f) */ +/* ========================================================= EIBD ================================================= */ + #define R_IRQ_INCT1_EIBD_PEID_Pos (0UL) /*!< PEID (Bit 0) */ + #define R_IRQ_INCT1_EIBD_PEID_Msk (0x7UL) /*!< PEID (Bitfield-Mask: 0x07) */ + +/*@}*/ /* end of group RH850_G4MH_IRQ */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_FPU FPU Function Registers (FPU) + * @brief Type definitions for the FPU Function Registers (FPU) + * @{ + */ + +/** + * @brief Structure type to access the FPU Function Registers (SYS). + */ + +typedef union +{ + __IOM uint32_t FPSR; /*!< (@ 0x00000000) Floating-point Configuration/Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are the preservation bits. */ + __IOM uint32_t XE : 5; /*!< [9..5] These are the enable bits. */ + __IOM uint32_t XC : 6; /*!< [15..10] These are the cause bits. */ + uint32_t : 1; + __IOM uint32_t FS : 1; /*!< [17..17] This bit enables values that could not be normalized + * (subnormal numbers) tobe flushed. If the FS bit is set, + * input operands and operation results that aresubnormal + * numbers are flushed without causing an unimplemented operationexception + * (E). An input operand that is a subnormal number is flushed + * to 0with the same sign. Operation results that are subnormal + * numbers eitherbecome 0 or the minimum normalized number, + * depending on the roundingmode. */ + __IOM uint32_t RM : 2; /*!< [19..18] These are the rounding mode control bits. The RM bits + * define the roundingmode that the FPU uses for all floating-point + * instructions. */ + uint32_t : 1; + __IOM uint32_t PEM : 1; /*!< [21..21] This bit specifies whether to handle an exception as + * a precise exception. If thePEM bit is 1, exceptions that + * are caused by the execution of a floating-pointoperation + * instruction are handled as precise exceptions. */ + __IOM uint32_t IF : 1; /*!< [22..22] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section 3.2.6.1(8), Flushing Subnormal + * Numbers. */ + __IOM uint32_t FN : 1; /*!< [23..23] This bit enables flush-to-nearest mode. When the FN + * bit is set to 1, if therounding mode is RN and the operation + * result is a subnormal number, thenumber is flushed to the + * nearest number. For details, see Section 3.2.6.1 (9),Flush + * to Nearest. */ + __IOM uint32_t CC : 8; /*!< [31..24] These are the CC (condition) bits. They store the results + * of floating-pointcomparison instructions. The CC7 to CC0 + * bits are not affected by anyinstructions except the comparison + * instruction and LDSR instruction.0: Comparison result is + * false1: Comparison result is true */ + } FPSR_b; +} RH850_FPU_FPSR_Type; + +typedef union +{ + __IOM uint32_t FPEPC; /*!< (@ 0x00000000) Floating-point Exception Program Counter */ + + struct + { + __IM uint32_t FPEPC0 : 1; /*!< [0..0] This bit stores the program counter (PC) of the floating-point + * instruction thatcaused the exception when a floating-point + * operation exception that isenabled by an enable bit occurs. */ + uint32_t : 30; + __IOM uint32_t FPEPC : 1; /*!< [31..31] These bits store the program counter (PC) of the floating-point + * instruction thatcaused the exception when a floating-point + * operation exception that isenabled by an enable bit occurs. */ + } FPEPC_b; +} RH850_FPU_FPEPC_Type; + +typedef union +{ + __IOM uint32_t FPST; /*!< (@ 0x00000000) Floating-point Operation Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are preservation bits. For details, see Section + * 3.2.3.4(1),Preservation Bits (XP). Values written to these + * bits are reflected inFPSR.XP bits. */ + __IOM uint32_t IF : 1; /*!< [5..5] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section3.2.6.1 (8), Flushing Subnormal + * Numbers. Value written to this bit isreflected in FPSR.IF + * bit. */ + uint32_t : 2; + __IOM uint32_t XC : 6; /*!< [13..8] These are cause bits. For details, see Section 3.2.3.4(1), + * Cause Bits (XC).Values written to these bits are reflected + * in FPSR.XC bits. */ + uint32_t : 18; + } FPST_b; +} RH850_FPU_FPST_Type; + +typedef union +{ + __IOM uint32_t FPCC; /*!< (@ 0x00000000) Floating-point Operation Comparison Result */ + + struct + { + __IOM uint32_t CC : 8; /*!< [7..0] These are CC (condition) bits. They store the result + * of a floating-pointcomparison instruction. The CC7 to CC0 + * bits are not affected by anyinstructions except the comparison + * instruction and LDSR instruction. Valueswritten to these + * bits are reflected in the CC7 to CC0 bits of FPSR.0: Comparison + * result is false1: Comparison result is true */ + uint32_t : 24; + } FPCC_b; +} RH850_FPU_FPCC_Type; + +typedef union +{ + __IOM uint32_t FPCFG; /*!< (@ 0x00000000) Floating-point Operation Configuration */ + + struct + { + __IOM uint32_t XE : 5; /*!< [4..0] These are the enable bits. For details, see Section 3.2.3.4(1), + * Enable Bits(XE). Values written to these bits are reflected + * in the FPSR.XE bits */ + uint32_t : 3; + __IOM uint32_t RM : 2; /*!< [9..8] These are rounding mode control bits. The RM bits define + * the rounding modethat the FPU uses for all floating-point + * instructions. Values written to these bitsare reflected + * in RM bits of FPSR. */ + uint32_t : 22; + } FPCFG_b; +} RH850_FPU_FPCFG_Type; + +/** @brief FPU Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_FPU ================ */ +/* ================================================================================================================== */ + +/* ========================================================= FPSR ================================================= */ + #define R_FPU_FPSR_CC_Pos (24UL) /*!< CC (Bit 24) */ + #define R_FPU_FPSR_CC_Msk (0xff000000UL) /*!< CC (Bitfield-Mask: 0xff) */ + #define R_FPU_FPSR_FN_Pos (23UL) /*!< FN (Bit 23) */ + #define R_FPU_FPSR_FN_Msk (0x800000UL) /*!< FN (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_IF_Pos (22UL) /*!< IF (Bit 22) */ + #define R_FPU_FPSR_IF_Msk (0x400000UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_PEM_Pos (21UL) /*!< PEM (Bit 21) */ + #define R_FPU_FPSR_PEM_Msk (0x200000UL) /*!< PEM (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_RM_Pos (18UL) /*!< RM (Bit 18) */ + #define R_FPU_FPSR_RM_Msk (0xc0000UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FPU_FPSR_FS_Pos (17UL) /*!< FS (Bit 17) */ + #define R_FPU_FPSR_FS_Msk (0x20000UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_FPU_FPSR_XC_Pos (10UL) /*!< XC (Bit 10) */ + #define R_FPU_FPSR_XC_Msk (0xfc00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FPU_FPSR_XE_Pos (5UL) /*!< XE (Bit 5) */ + #define R_FPU_FPSR_XE_Msk (0x3e0UL) /*!< XE (Bitfield-Mask: 0x1f) */ + #define R_FPU_FPSR_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FPU_FPSR_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ========================================================= FPEPC ================================================ */ + #define R_FPU_FPEPC_FPEPC_Pos (31UL) /*!< FPEPC (Bit 31) */ + #define R_FPU_FPEPC_FPEPC_Msk (0x80000000UL) /*!< FPEPC (Bitfield-Mask: 0x01) */ + #define R_FPU_FPEPC_FPEPC0_Pos (0UL) /*!< FPEPC0 (Bit 0) */ + #define R_FPU_FPEPC_FPEPC0_Msk (0x1UL) /*!< FPEPC0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FPST ================================================= */ + #define R_FPU_FPST_XC_Pos (8UL) /*!< XC (Bit 8) */ + #define R_FPU_FPST_XC_Msk (0x3f00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FPU_FPST_IF_Pos (5UL) /*!< IF (Bit 5) */ + #define R_FPU_FPST_IF_Msk (0x20UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FPU_FPST_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FPU_FPST_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ========================================================= FPCC ================================================= */ + #define R_FPU_FPCC_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_FPU_FPCC_CC_Msk (0xffUL) /*!< CC (Bitfield-Mask: 0xff) */ +/* ========================================================= FPCFG ================================================ */ + #define R_FPU_FPCFG_RM_Pos (8UL) /*!< RM (Bit 8) */ + #define R_FPU_FPCFG_RM_Msk (0x300UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FPU_FPCFG_XE_Pos (0UL) /*!< XE (Bit 0) */ + #define R_FPU_FPCFG_XE_Msk (0x1fUL) /*!< XE (Bitfield-Mask: 0x1f) */ + +/*@}*/ /* end of group RH850_G4MH_FPU */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_FXU FXU Function Registers (FXU) + * @brief Type definitions for the FXU Function Registers (FXU) + * @{ + */ + +/** + * @brief Structure type to access the FXU Function Registers (FXU). + */ + +typedef union +{ + __IOM uint32_t FXSR; /*!< (@ 0x00000000) Extended Floating-point Operation Configuration/Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are the preservation bits */ + __IOM uint32_t XE : 5; /*!< [9..5] These are the enable bits */ + __IOM uint32_t XC : 6; /*!< [15..10] These are the cause bits */ + uint32_t : 1; + __IOM uint32_t FS : 1; /*!< [17..17] This bit enables values that could not be normalized + * (subnormal numbers) tobe flushed. If the FS bit is set, + * input operands and operation results that aresubnormal + * numbers are flushed without causing an unimplemented operationexception + * (E). An input operand that is a subnormal number is flushed + * to 0with the same sign. Operation results that are subnormal + * numbers eitherbecome 0 or the minimum normalized number, + * depending on the roundingmode. */ + __IOM uint32_t RM : 2; /*!< [19..18] These are the rounding mode control bits. The RM bits + * define the roundingmode that the FXU uses for all extended + * floating-point instructions */ + uint32_t : 2; + __IOM uint32_t IF : 1; /*!< [22..22] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section 3.2.6.2Section 3.2.6.1 (8), + * Flushing Subnormal Numbers. */ + __IOM uint32_t FN : 1; /*!< [23..23] This bit enables flush-to-nearest mode. When the FN + * bit is set to 1, if therounding mode is RN and the operation + * result is a subnormal number, thenumber is flushed to the + * nearest number. For details, see Section 3.2.6.1 (9),Flush + * to Nearest. */ + uint32_t : 8; + } FXSR_b; +} RH850_FXU_FXSR_Type; + +typedef union +{ + __IOM uint32_t FXST; /*!< (@ 0x00000000) Extended Floating-point Operation Status */ + + struct + { + __IOM uint32_t XP : 5; /*!< [4..0] These are preservation bits. For details, see Section + * 3.2.3.4(1), PreservationBits (XP). Values written to these + * bits are reflected in FXSR.XP bits. */ + __IOM uint32_t IF : 1; /*!< [5..5] This bit accumulates and indicates information about + * the flushing of inputoperands. For details about flushing + * subnormal numbers, see Section 3.2.6.1(8), Flushing Subnormal + * Numbers. Value written to this bit is reflected inFXSR.IF + * bit. */ + uint32_t : 2; + __IOM uint32_t XC : 6; /*!< [13..8] These are cause bits. For details, see Section 3.2.3.4(1), + * Cause Bits (XC).Values written to these bits are reflected + * in FXSR.XC bits. */ + uint32_t : 18; + } FXST_b; +} RH850_FXU_FXST_Type; + +typedef union +{ + __IOM uint32_t FXINFO; /*!< (@ 0x00000000) FXU Configuration Information */ + + struct + { + __IM uint32_t RSIZE : 1; /*!< [0..0] This bit indicates that 32 128-bit vector registers are + * provided. */ + __IM uint32_t NFPU : 1; /*!< [1..1] This bit indicates that 4-way SIMD arithmetic unit is + * provided. */ + uint32_t : 30; + } FXINFO_b; +} RH850_FXU_FXINFO_Type; + +typedef union +{ + __IOM uint32_t FXCFG; /*!< (@ 0x00000000) Extended Floating-point Operation Configuration */ + + struct + { + __IOM uint32_t XE : 5; /*!< [4..0] These are the enable bits. For details, see Section 3.2.3.4(1), + * Enable Bits(XE).Values written to these bits are reflected + * in FXSR.XE bits. */ + uint32_t : 3; + __IOM uint32_t RM : 2; /*!< [9..8] These are the rounding mode control bits. The RM bits + * define the roundingmode that the FXU uses for all extended + * floating-point instructions. Valueswritten to these bits + * are reflected in FXSR.RM bits. */ + uint32_t : 22; + } FXCFG_b; +} RH850_FXU_FXCFG_Type; + +typedef union +{ + __IOM uint32_t FXXC; /*!< (@ 0x00000000) XC (Cause) Bits for Each operation way */ + + struct + { + __IOM uint32_t XC0 : 6; /*!< [5..0] These bits hold the cause bits associated with operation + * way 0. */ + uint32_t : 2; + __IOM uint32_t XC1 : 6; /*!< [13..8] These bits hold the cause bits associated with operation + * way 1. */ + uint32_t : 2; + __IOM uint32_t XC2 : 6; /*!< [21..16] These bits hold the cause bits associated with operation + * way 2. */ + uint32_t : 2; + __IOM uint32_t XC3 : 6; /*!< [29..24] These bits hold the cause bits associated with operation + * way 3. */ + uint32_t : 2; + } FXXC_b; +} RH850_FXU_FXXC_Type; + +typedef union +{ + __IOM uint32_t FXXP; /*!< (@ 0x00000000) XP (Preservation) Bits for Each operation way */ + + struct + { + __IOM uint32_t XP0 : 6; /*!< [5..0] These bits hold the preservation bits associated with + * operation way 0. */ + uint32_t : 2; + __IOM uint32_t XP1 : 6; /*!< [13..8] These bits hold the preservation bits associated with + * operation way 1. */ + uint32_t : 2; + __IOM uint32_t XP2 : 6; /*!< [21..16] These bits hold the preservation bits associated with + * operation way 2. */ + uint32_t : 2; + __IOM uint32_t XP3 : 6; /*!< [29..24] These bits hold the preservation bits associated with + * operation way 3. */ + uint32_t : 2; + } FXXP_b; +} RH850_FXU_FXXP_Type; + +/** @brief FXU Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_FXU ================ */ +/* ================================================================================================================== */ + +/* ========================================================= FXSR ================================================= */ + #define R_FXU_FXSR_FN_Pos (23UL) /*!< FN (Bit 23) */ + #define R_FXU_FXSR_FN_Msk (0x800000UL) /*!< FN (Bitfield-Mask: 0x01) */ + #define R_FXU_FXSR_IF_Pos (22UL) /*!< IF (Bit 22) */ + #define R_FXU_FXSR_IF_Msk (0x400000UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FXU_FXSR_RM_Pos (18UL) /*!< RM (Bit 18) */ + #define R_FXU_FXSR_RM_Msk (0xc0000UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FXU_FXSR_FS_Pos (17UL) /*!< FS (Bit 17) */ + #define R_FXU_FXSR_FS_Msk (0x20000UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_FXU_FXSR_XC_Pos (10UL) /*!< XC (Bit 10) */ + #define R_FXU_FXSR_XC_Msk (0xfc00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXSR_XE_Pos (5UL) /*!< XE (Bit 5) */ + #define R_FXU_FXSR_XE_Msk (0x3e0UL) /*!< XE (Bitfield-Mask: 0x1f) */ + #define R_FXU_FXSR_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FXU_FXSR_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ========================================================= FXST ================================================= */ + #define R_FXU_FXST_XC_Pos (8UL) /*!< XC (Bit 8) */ + #define R_FXU_FXST_XC_Msk (0x3f00UL) /*!< XC (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXST_IF_Pos (5UL) /*!< IF (Bit 5) */ + #define R_FXU_FXST_IF_Msk (0x20UL) /*!< IF (Bitfield-Mask: 0x01) */ + #define R_FXU_FXST_XP_Pos (0UL) /*!< XP (Bit 0) */ + #define R_FXU_FXST_XP_Msk (0x1fUL) /*!< XP (Bitfield-Mask: 0x1f) */ +/* ======================================================== FXINFO ================================================ */ + #define R_FXU_FXINFO_NFPU_Pos (1UL) /*!< NFPU (Bit 1) */ + #define R_FXU_FXINFO_NFPU_Msk (0x2UL) /*!< NFPU (Bitfield-Mask: 0x01) */ + #define R_FXU_FXINFO_RSIZE_Pos (0UL) /*!< RSIZE (Bit 0) */ + #define R_FXU_FXINFO_RSIZE_Msk (0x1UL) /*!< RSIZE (Bitfield-Mask: 0x01) */ +/* ========================================================= FXCFG ================================================ */ + #define R_FXU_FXCFG_RM_Pos (8UL) /*!< RM (Bit 8) */ + #define R_FXU_FXCFG_RM_Msk (0x300UL) /*!< RM (Bitfield-Mask: 0x03) */ + #define R_FXU_FXCFG_XE_Pos (0UL) /*!< XE (Bit 0) */ + #define R_FXU_FXCFG_XE_Msk (0x1fUL) /*!< XE (Bitfield-Mask: 0x1f) */ +/* ========================================================= FXXC ================================================= */ + #define R_FXU_FXXC_XC3_Pos (24UL) /*!< XC3 (Bit 24) */ + #define R_FXU_FXXC_XC3_Msk (0x3f000000UL) /*!< XC3 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXC_XC2_Pos (16UL) /*!< XC2 (Bit 16) */ + #define R_FXU_FXXC_XC2_Msk (0x3f0000UL) /*!< XC2 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXC_XC1_Pos (8UL) /*!< XC1 (Bit 8) */ + #define R_FXU_FXXC_XC1_Msk (0x3f00UL) /*!< XC1 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXC_XC0_Pos (0UL) /*!< XC0 (Bit 0) */ + #define R_FXU_FXXC_XC0_Msk (0x3fUL) /*!< XC0 (Bitfield-Mask: 0x3f) */ +/* ========================================================= FXXP ================================================= */ + #define R_FXU_FXXP_XP3_Pos (24UL) /*!< XP3 (Bit 24) */ + #define R_FXU_FXXP_XP3_Msk (0x3f000000UL) /*!< XP3 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXP_XP2_Pos (16UL) /*!< XP2 (Bit 16) */ + #define R_FXU_FXXP_XP2_Msk (0x3f0000UL) /*!< XP2 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXP_XP1_Pos (8UL) /*!< XP1 (Bit 8) */ + #define R_FXU_FXXP_XP1_Msk (0x3f00UL) /*!< XP1 (Bitfield-Mask: 0x3f) */ + #define R_FXU_FXXP_XP0_Pos (0UL) /*!< XP0 (Bit 0) */ + #define R_FXU_FXXP_XP0_Msk (0x3fUL) /*!< XP0 (Bitfield-Mask: 0x3f) */ + +/*@}*/ /* end of group RH850_G4MH_FXU */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_MPU MPU Function Registers (MPU) + * @brief Type definitions for the MPU Function Registers (MPU) + * @{ + */ + +/** + * @brief Structure type to access the MPU Function Registers (MPU). + */ + +typedef union +{ + __IOM uint32_t MPM; /*!< (@ 0x00000000) Memory Protection Operation Mode */ + + struct + { + __IOM uint32_t MPE : 1; /*!< [0..0] This bit indicates that 32 128-bit vector registers are + * provided. */ + __IOM uint32_t SVP : 1; /*!< [1..1] This bit indicates that 4-way SIMD arithmetic unit is + * provided. */ + uint32_t : 30; + } MPM_b; +} RH850_MPU_MPM_Type; + +typedef union +{ + __IOM uint32_t MPCFG; /*!< (@ 0x00000000) MPU Configuration */ + + struct + { + __IM uint32_t NMPUE : 5; /*!< [4..0] These bits indicate the number of MPU entries implemented + * in this CPUminus 1. A value of 31 is read since this CPU + * incorporates 32 MPUentries. */ + uint32_t : 11; + __IM uint32_t ARCH : 4; /*!< [19..16] These bits hold the cause bits associated with operation + * way 1. */ + __IM uint32_t NBK : 2; /*!< [21..20] Indicates the "number of banks - 1" of the MPU bank + * 2 equipped in thisCPU.Since the MPU bank of this CPU is + * equipped with one bank, 0 is read. */ + uint32_t : 10; + } MPCFG_b; +} RH850_MPU_MPCFG_Type; + +typedef union +{ + __IOM uint32_t MCA; /*!< (@ 0x00000000) Memory Protection Setting Check Address */ + + struct + { + __IOM uint32_t MCA : 32; /*!< [31..0] These bits are used to specify the starting address + * of the memory areawhich subjects to a memory protection + * setting check in bytes. */ + } MCA_b; +} RH850_MPU_MCA_Type; + +typedef union +{ + __IOM uint32_t MCS; /*!< (@ 0x00000000) Memory Protection Setting Check Size */ + + struct + { + __IOM uint32_t MCS : 32; /*!< [31..0] These bits are used to specify the size of the memory + * area in bytes whichsubjects to a memory protection setting + * check. Because the specified sizeis assumed to represent + * an unsigned integer, it is not possible to check anarea + * in the direction in which the address value decreases relative + * to theMCA register value. */ + } MCS_b; +} RH850_MPU_MCS_Type; + +typedef union +{ + __IOM uint32_t MCC; /*!< (@ 0x00000000) Memory Protection Setting Check Command */ + + struct + { + __IOM uint32_t MCC : 32; /*!< [31..0] When any value is written to the MCC register, a memory + * protection settingcheck starts. By setting up the MCA / + * MCS register and then writing to theMCC register, results + * are stored in MCR. Because the check is started by anywritten + * value, a check can be started by using r0 as the source + * register withoutusing any unnecessary registers.Note that, + * for the check, the results are applied according to each + * area settingregardless of the state of the PSW.UM bit.This + * checking applies for memory protec */ + } MCC_b; +} RH850_MPU_MCC_Type; + +typedef union +{ + __IOM uint32_t MCR; /*!< (@ 0x00000000) Memory Protection Setting Check Result */ + + struct + { + __IOM uint32_t URE : 1; /*!< [0..0] If the specified area is contained within one protection + * area and reading fromthat area is permitted in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t UWE : 1; /*!< [1..1] If the specified area is contained within one protection + * area and writing fromthat area is permitted in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t UXE : 1; /*!< [2..2] If the specified area is contained within one protection + * area and execution ispermitted for that area in user mode, + * 1 is stored in this bit. In other cases, 0 isstored in + * this bit. */ + __IOM uint32_t SRE : 1; /*!< [3..3] If the specified area is contained within one protection + * area and reading fromthat area is permitted in supervisor + * mode, 1 is stored in this bit. In other cases,0 is stored + * in this bit. */ + __IOM uint32_t SWE : 1; /*!< [4..4] If the specified area is contained within one protection + * area and writing to thatarea is permitted in supervisor + * mode, 1 is stored in this bit. In other cases, 0 isstored + * in this bit. */ + __IOM uint32_t SXE : 1; /*!< [5..5] If the specified area is contained within one protection + * area and execution ispermitted for that area in supervisor + * mode, 1 is stored in this bit. In othercases, 0 is stored + * in this bit. */ + uint32_t : 2; + __IOM uint32_t OV : 1; /*!< [8..8] If the specified area includes 0000 0000H or 7FFF FFFFH, + * 1 is stored in thisbit. In other cases, 0 is stored in + * this bit. */ + uint32_t : 23; + } MCR_b; +} RH850_MPU_MCR_Type; + +typedef union +{ + __IOM uint32_t MCI; /*!< (@ 0x00000000) Memory Protection Setting Check SPID */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 27; + } MCI_b; +} RH850_MPU_MCI_Type; + +typedef union +{ + __IOM uint32_t MPIDX; /*!< (@ 0x00000000) Index of Memory Protection Setting Registers + * to be Accessed */ + + struct + { + __IOM uint32_t IDX : 5; /*!< [4..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 27; + } MPIDX_b; +} RH850_MPU_MPIDX_type; + +typedef union +{ + __IOM uint32_t MPBK; /*!< (@ 0x00000000) MPU Bank Setting */ + + struct + { + __IOM uint32_t BK : 2; /*!< [1..0] These bits specify the SPID for which a memory protection + * settings check is tobe performed. */ + uint32_t : 30; + } MPBK_b; +} RH850_MPU_MPBK_Type; + +typedef union +{ + __IOM uint32_t MPLA; /*!< (@ 0x00000000) Base Address of the Interrupt Handler Address + * Table */ + + struct + { + uint32_t : 2; + __IOM uint32_t MPLA : 30; /*!< [31..2] These bits specify the minimum address of area n (n + * = 0 to MPCFG.NMPUE)specified by the MPIDX register.The + * specified minimum address is included in the range of area + * matching. */ + } MPLA_b; +} RH850_MPU_MPLA_Type; + +typedef union +{ + __IOM uint32_t MPUA; /*!< (@ 0x00000000) Protection Area Maximum Address */ + + struct + { + uint32_t : 2; + __IOM uint32_t MPUA : 30; /*!< [31..2] These bits specify the maximum address of area n (n + * = 0 to MPCFG.NMPUE)specified by the MPIDX register.The + * specified maximum address is included in the range of area + * matching.Bits 1 and 0 of the maximum address are handled + * as 1. */ + } MPUA_b; +} RH850_MPU_MPUA_Type; + +typedef union +{ + __IOM uint32_t MPAT; /*!< (@ 0x00000000) Protection Area Attribute */ + + struct + { + __IOM uint32_t UR : 1; /*!< [0..0] This bit indicates the read permission in the user mode + * for area n (n = 0 toMPCFG.NMPUE) specified by the MPIDX + * register.*20: Reading is disabled.1: Reading is enabled. */ + __IOM uint32_t UW : 1; /*!< [1..1] This bit indicates the write permission in the user mode + * for area n (n = 0 toMPCFG.NMPUE) specified by the MPIDX + * register.0: Writing is disabled.1: Writing is enabled. */ + __IOM uint32_t UX : 1; /*!< [2..2] This bit indicates the execution permission in the user + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.0: Execution is disabled.1: Execution is + * enabled. */ + __IOM uint32_t SR : 1; /*!< [3..3] This bit indicates the read permission in the supervisor + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.*1, *20: Reading is disabled.1: Reading + * is enabled. */ + __IOM uint32_t SW : 1; /*!< [4..4] This bit indicates the write permission in the supervisor + * mode for area n (n = 0to MPCFG.NMPUE) specified by the + * MPIDX register.*10: Writing is disabled.1: Writing is enabled. */ + __IOM uint32_t SX : 1; /*!< [5..5] This bit indicates the execution permission in the supervisor + * mode for area n(n = 0 to MPCFG.NMPUE) specified by the + * MPIDX register.*10: Execution is disabled.1: Execution + * is enabled. */ + uint32_t : 1; + __IOM uint32_t E : 1; /*!< [7..7] This bit indicates whether area n (n = 0 to MPCFG.NMPUE) + * specified by theMPIDX register is enabled or disabled.0: + * Area n is disabled.1: Area n is enabled. */ + uint32_t : 6; + __IOM uint32_t RG : 1; /*!< [14..14] This bit indicates the execution and read permissions + * for any SPID.0: Execution and reading is enabled by the + * settings of the MPIDn registerand RMPIDn bit (n = 0 to + * 7).1: Execution and reading by any SPID is enabled regardless + * of the settingsof the MPIDn register and RMPIDn bit (n + * = 0 to 7). */ + __IOM uint32_t WG : 1; /*!< [15..15] This bit indicates the write permission for any SPID.0: + * Writing is enabled by the settings of the MPIDn register + * and WMPIDn bit(n = 0 to 7).1: Writing by any SPID is enabled + * regardless of the settings of the MPIDnregister and WMPIDn + * bit (n = 0 to 7). */ + __IOM uint32_t RMPID : 8; /*!< [23..16] This bit indicates the execution and read permissions + * for the SPID specified inthe MPIDn (n = 0 to 7) register.0: + * Execution and reading by the SPID specified by the MPIDn + * register isdisabled.1: Execution and reading by the SPID + * specified by the MPIDn register isenabled. */ + __IOM uint32_t WMPID : 8; /*!< [31..24] This bit indicates the write permission for the SPID + * specified in the MPIDn (n =0 to 7) register.0: Writing + * by the SPID specified by the MPIDn register is disabled.1: + * Writing by the SPID specified by the MPIDn register is + * enabled. */ + } MPAT_b; +} RH850_MPU_MPAT_Type; + +typedef union +{ + __IOM uint32_t MPID; /*!< (@ 0x00000000) SPID which can Access Protection Area */ + + struct + { + __IOM uint32_t SPID : 5; /*!< [4..0] These bits specify the SPID which can access protection + * area. */ + uint32_t : 27; + } MPID_b; +} RH850_MPU_MPID_Type; + +/** @brief MPU Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_MPU ================ */ +/* ================================================================================================================== */ + +/* ========================================================== MPM ================================================= */ + #define R_MPU_MPM_SVP_Pos (1UL) /*!< SVP (Bit 1) */ + #define R_MPU_MPM_SVP_Msk (0x2UL) /*!< SVP (Bitfield-Mask: 0x01) */ + #define R_MPU_MPM_MPE_Pos (0UL) /*!< MPE (Bit 0) */ + #define R_MPU_MPM_MPE_Msk (0x1UL) /*!< MPE (Bitfield-Mask: 0x01) */ +/* ========================================================= MPCFG ================================================ */ + #define R_MPU_MPCFG_NBK_Pos (20UL) /*!< NBK (Bit 20) */ + #define R_MPU_MPCFG_NBK_Msk (0x300000UL) /*!< NBK (Bitfield-Mask: 0x03) */ + #define R_MPU_MPCFG_ARCH_Pos (16UL) /*!< ARCH (Bit 16) */ + #define R_MPU_MPCFG_ARCH_Msk (0xf0000UL) /*!< ARCH (Bitfield-Mask: 0x0f) */ + #define R_MPU_MPCFG_NMPUE_Pos (0UL) /*!< NMPUE (Bit 0) */ + #define R_MPU_MPCFG_NMPUE_Msk (0x1fUL) /*!< NMPUE (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCA ================================================= */ + #define R_MPU_MCA_MCA_Pos (0UL) /*!< MCA (Bit 0) */ + #define R_MPU_MCA_MCA_Msk (0xffffffffUL) /*!< MCA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCS ================================================= */ + #define R_MPU_MCS_MCS_Pos (0UL) /*!< MCS (Bit 0) */ + #define R_MPU_MCS_MCS_Msk (0xffffffffUL) /*!< MCS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCC ================================================= */ + #define R_MPU_MCC_MCC_Pos (0UL) /*!< MCC (Bit 0) */ + #define R_MPU_MCC_MCC_Msk (0xffffffffUL) /*!< MCC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== MCR ================================================= */ + #define R_MPU_MCR_OV_Pos (8UL) /*!< OV (Bit 8) */ + #define R_MPU_MCR_OV_Msk (0x100UL) /*!< OV (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SXE_Pos (5UL) /*!< SXE (Bit 5) */ + #define R_MPU_MCR_SXE_Msk (0x20UL) /*!< SXE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SWE_Pos (4UL) /*!< SWE (Bit 4) */ + #define R_MPU_MCR_SWE_Msk (0x10UL) /*!< SWE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_SRE_Pos (3UL) /*!< SRE (Bit 3) */ + #define R_MPU_MCR_SRE_Msk (0x8UL) /*!< SRE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_UXE_Pos (2UL) /*!< UXE (Bit 2) */ + #define R_MPU_MCR_UXE_Msk (0x4UL) /*!< UXE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_UWE_Pos (1UL) /*!< UWE (Bit 1) */ + #define R_MPU_MCR_UWE_Msk (0x2UL) /*!< UWE (Bitfield-Mask: 0x01) */ + #define R_MPU_MCR_URE_Pos (0UL) /*!< URE (Bit 0) */ + #define R_MPU_MCR_URE_Msk (0x1UL) /*!< URE (Bitfield-Mask: 0x01) */ +/* ========================================================== MCI ================================================= */ + #define R_MPU_MCI_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MCI_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPIDX ================================================ */ + #define R_MPU_MPIDX_IDX_Pos (0UL) /*!< IDX (Bit 0) */ + #define R_MPU_MPIDX_IDX_Msk (0x1fUL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPBK ================================================= */ + #define R_MPU_MPBK_BK_Pos (0UL) /*!< BK (Bit 0) */ + #define R_MPU_MPBK_BK_Msk (0x3UL) /*!< BK (Bitfield-Mask: 0x03) */ +/* ========================================================= MPLA ================================================= */ + #define R_MPU_MPLA_MPLA_Pos (2UL) /*!< MPLA (Bit 2) */ + #define R_MPU_MPLA_MPLA_Msk (0xfffffffcUL) /*!< MPLA (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= MPUA ==================== ============================ */ + #define R_MPU_MPUA_MPUA_Pos (2UL) /*!< MPUA (Bit 2) */ + #define R_MPU_MPUA_MPUA_Msk (0xfffffffcUL) /*!< MPUA (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= MPAT ================================================= */ + #define R_MPU_MPAT_WMPID_Pos (24UL) /*!< WMPID (Bit 24) */ + #define R_MPU_MPAT_WMPID_Msk (0xff000000UL) /*!< WMPID (Bitfield-Mask: 0xff) */ + #define R_MPU_MPAT_RMPID_Pos (16UL) /*!< RMPID (Bit 16) */ + #define R_MPU_MPAT_RMPID_Msk (0xff0000UL) /*!< RMPID (Bitfield-Mask: 0xff) */ + #define R_MPU_MPAT_WG_Pos (15UL) /*!< WG (Bit 15) */ + #define R_MPU_MPAT_WG_Msk (0x8000UL) /*!< WG (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_RG_Pos (14UL) /*!< RG (Bit 14) */ + #define R_MPU_MPAT_RG_Msk (0x4000UL) /*!< RG (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_E_Pos (7UL) /*!< E (Bit 7) */ + #define R_MPU_MPAT_E_Msk (0x80UL) /*!< E (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SX_Pos (5UL) /*!< SX (Bit 5) */ + #define R_MPU_MPAT_SX_Msk (0x20UL) /*!< SX (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SW_Pos (4UL) /*!< SW (Bit 4) */ + #define R_MPU_MPAT_SW_Msk (0x10UL) /*!< SW (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_SR_Pos (3UL) /*!< SR (Bit 3) */ + #define R_MPU_MPAT_SR_Msk (0x8UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UX_Pos (2UL) /*!< UX (Bit 2) */ + #define R_MPU_MPAT_UX_Msk (0x4UL) /*!< UX (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UW_Pos (1UL) /*!< UW (Bit 1) */ + #define R_MPU_MPAT_UW_Msk (0x2UL) /*!< UW (Bitfield-Mask: 0x01) */ + #define R_MPU_MPAT_UR_Pos (0UL) /*!< UR (Bit 0) */ + #define R_MPU_MPAT_UR_Msk (0x1UL) /*!< UR (Bitfield-Mask: 0x01) */ +/* ========================================================= MPID0 ================================================ */ + #define R_MPU_MPID0_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID0_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID1 ================================================ */ + #define R_MPU_MPID1_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID1_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID2 ================================================ */ + #define R_MPU_MPID2_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID2_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID3 ================================================ */ + #define R_MPU_MPID3_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID3_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID4 ================================================ */ + #define R_MPU_MPID4_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID4_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID5 ================================================ */ + #define R_MPU_MPID5_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID5_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID6 ================================================ */ + #define R_MPU_MPID6_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID6_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ +/* ========================================================= MPID7 ================================================ */ + #define R_MPU_MPID7_SPID_Pos (0UL) /*!< SPID (Bit 0) */ + #define R_MPU_MPID7_SPID_Msk (0x1fUL) /*!< SPID (Bitfield-Mask: 0x1f) */ + +/*@}*/ /* end of group RH850_G4MH_MPU */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_ICACHE Cache Operation Function Registers (ICACHE) + * @brief Type definitions for the Cache Operation Function Registers (ICACHE) + * @{ + */ + +/** + * @brief Structure type to access the Cache Operation Function Registers (ICACHE). + */ + +typedef union +{ + __IOM uint32_t ICTAGL; /*!< (@ 0x00000000) Instruction Cache Tag Lo Access */ + + struct + { + __IOM uint32_t V : 1; /*!< [0..0] This bit holds valid/invalid information of specified + * cache line.*30: The cache line is disabled.1: The cache + * line is enabled. */ + uint32_t : 1; + __IOM uint32_t L : 1; /*!< [2..2] This bit holds the lock information.*30: The cache line + * is not locked.1: The cache line is locked. */ + uint32_t : 1; + __IOM uint32_t LRU : 2; /*!< [5..4] These bits indicate LRU information of specified cache + * line. LRU informationcannot be freely changed to any value + * by the CIST instruction */ + uint32_t : 5; + __IOM uint32_t LPN : 21; /*!< [31..11] These bits hold address bits 27 to 11. Bits 31 to 28 + * must always be set to 0.Bits 27 to 11 are held if the cache + * size is 8 Kbytes.Bits 27 to 12 are held and bit 11 is always + * set to 0 if the cache size is 16Kbytes.*1Bits 27 to 13 + * are held and bit 12 and 11 are always set to 0 if the cache + * size is32 KBytes.*2 */ + } ICTAGL_b; +} RH850_ICACHE_ICTAGL_Type; + +typedef union +{ + __IOM uint32_t ICTAGH; /*!< (@ 0x00000000) Instruction Cache Tag Hi Access */ + + struct + { + uint32_t : 8; + __IOM uint32_t TAGECC : 8; /*!< [15..8] These bits hold ECC for tag RAM. Bit 15 is fixed to + * 0 */ + __IOM uint32_t DATAECC : 8; /*!< [23..16] These bits hold ECC for data RAM. */ + uint32_t : 4; + __IOM uint32_t PT : 1; /*!< [28..28] This bit specifies the data to be written to the ECC + * of the tag RAM when theWT bit is set to 1 and the CIST + * instruction is executed.0: ECC automatically generated + * from the write data is written to the ECC ofthe tag RAM.1: + * Values in the TAGECC field are written to the ECC of the + * tag RAM. */ + __IOM uint32_t WT : 1; /*!< [29..29] This bit specifies whether the tag RAM of the cache + * is updated duringexecution of the CIST instruction. When + * this bit is set to 1, the V bit and L bit ofthe cache line + * are also updated.0: Tag RAM of the cache is not updated.1: + * Tag RAM of the cache is updated. */ + __IOM uint32_t PD : 1; /*!< [30..30] This bit specifies the data to be written to the ECC + * of the data RAM when theWD bit is set to 1 and the CIST + * instruction is executed.0: ECC automatically generated + * from the write data is written to the ECC ofthe data RAM.1: + * Values in the DATAECC field are written to the ECC of the + * data RAM. */ + __IOM uint32_t WD : 1; /*!< [31..31] This bit specifies whether the data RAM of the cache + * is updated duringexecution of the CIST instruction.0: Data + * RAM of the cache is not updated.1: Data RAM of the cache + * is updated. */ + } ICTAGH_b; +} RH850_ICACHE_ICTAGH_type; + +typedef union +{ + __IOM uint32_t ICDATL; /*!< (@ 0x00000000) Instruction Cache Data Lo Access */ + + struct + { + __IOM uint32_t DATAL : 32; /*!< [31..0] These bits hold the lower-order 32 bits of the 64-bit + * instruction data*1 in theblock in the specified cache line. + * The bits to be held is specified by offset of theindex.*2Offset + * of index = 00: Bits 31 to 0*3Offset of index = 01: Bits + * 95 to 64*3Offset of index = 10: Bits 159 to 128*3Offset + * of index = 11: Bits 223 to 192*3 */ + } ICDATL_b; +} RH850_ICACHE_ICDATL_Type; + +typedef union +{ + __IOM uint32_t ICDATH; /*!< (@ 0x00000000) Instruction Cache Data Hi Access */ + + struct + { + __IOM uint32_t DATAH : 32; /*!< [31..0] These bits hold the upper-order 32 bits of the 64-bit + * instruction data*1 in theblock in the specified cache line. + * The bits to be held is specified by offset of theindex.*2Offset + * of index = 00: Bits 63 to 32*3Offset of index = 01: Bits + * 127 to 96*3Offset of index = 10: Bits 191 to 160*3Offset + * of index = 11: Bits 255 to 224*3 */ + } ICDATH_b; +} RH850_ICACHE_ICDATH_Type; + +typedef union +{ + __IOM uint32_t ICCTRL; /*!< (@ 0x00000000) Instruction Cache Control */ + + struct + { + __IOM uint32_t ICHEN : 1; /*!< [0..0] This bit indicates valid/invalid status of instruction + * cache.0: Instruction cache is invalid1: Instruction cache + * is valid */ + __IOM uint32_t ICHEMK : 1; /*!< [1..1] When this bit is set to 1, it masks notification of cache + * error exceptions forthe CPU after a cache error*2 has occurred. */ + __IOM uint32_t ICHEIV : 1; /*!< [2..2] When this bit is set to 1, the instruction cache is automatically + * set asinvalid (the ICHEN bit is cleared to 0) whenever + * a cache error*2 occurs. */ + uint32_t : 5; + __IOM uint32_t ICHCLR : 1; /*!< [8..8] When this bit is set to 1, the entire instruction cache + * is cleared. This clearsthe V and L bits (to 0) and initializes + * the LRU information. This bit isalways read as 0. */ + uint32_t : 23; + } ICCTRL_b; +} RH850_ICACHE_ICCTRL_Type; + +typedef union +{ + __IOM uint32_t ICCFG; /*!< (@ 0x00000000) Instruction Cache Configuration */ + + struct + { + __IM uint32_t ICHWAY : 4; /*!< [3..0] These bits indicate the number of ways in the instruction + * cache.0100: 4 waysOther than above: Setting prohibited */ + __IM uint32_t ICHLINE : 4; /*!< [7..4] These bits indicate the number of lines for each way + * in the instruction cache.0010: 64 lines0100: 128 lines1000: + * 256 linesOther than above: Setting prohibited */ + __IM uint32_t ICHSIZE : 7; /*!< [14..8] These bits indicate the size (in Kbytes) of the instruction + * cache.000 1000: 8 Kbytes001 0000: 16 Kbytes010 0000: 32 + * KbytesOther than above: Setting prohibited */ + uint32_t : 17; + } ICCFG_b; +} RH850_ICACHE_ICCFG_Type; + +typedef union +{ + __IOM uint32_t ICERR; /*!< (@ 0x00000000) Instruction Cache Error */ + + struct + { + __IOM uint32_t ICHERR : 1; /*!< [0..0] This bit is set to 1 when a cache error has occurred. */ + uint32_t : 1; + __IOM uint32_t ICHET : 1; /*!< [2..2] This bit indicates that an error has occurred in tag + * RAM. */ + __IOM uint32_t ICHED : 1; /*!< [3..3] This bit indicates that an error has occurred in data + * RAM. */ + __IOM uint32_t ICHERQ : 1; /*!< [4..4] When this bit is set to 1, this bit indicates that cache + * error exceptionnotification is in progress. However, if + * cache error exception notification hasbeen masked, the + * CPU is not notified even when 1 has been set to this bit. */ + __IOM uint32_t ICHEIX : 8; /*!< [12..5] These bits hold the cache index where a cache error + * occurred.Bits 10 to 5 are held and bits 12 and 11 are fixed + * to 0 for a cache size of 8Kbytes.*1Bits 11 to 5 are held + * and bit 12 is fixed to 0 for a cache size of 16 Kbytes.*2Bits + * 12 to 5 are held for cache size of 32 Kbytes. */ + __IOM uint32_t ICHEWY : 3; /*!< [15..13] These bits hold the way number where a cache error + * occurred. Bit 15 isalways set to 0. */ + __IOM uint32_t ERMDE : 1; /*!< [16..16] Error exception notification mask: Data RAM 2-bits + * error*3 */ + __IOM uint32_t ERMDC : 1; /*!< [17..17] Error exception notification mask: Data RAM 1-bit error*3 */ + __IOM uint32_t ERMTE2 : 1; /*!< [18..18] Error exception notification mask: Tag RAM 2-bits error*3 */ + __IOM uint32_t ERMTE1 : 1; /*!< [19..19] Error exception notification mask: Tag RAM 1-bit error*3 */ + __IOM uint32_t ERMPBSE : 1; /*!< [20..20] Error exception notification mask: WAY error*3 */ + __IOM uint32_t ERMMH : 1; /*!< [21..21] Error exception notification mask: Multi hit*3 */ + __IOM uint32_t ERMAFE : 1; /*!< [22..22] Error exception notification mask: Address feedback + * error*3 */ + uint32_t : 1; + __IOM uint32_t ESDE : 1; /*!< [24..24] Error status: Data RAM 2-bits error */ + __IOM uint32_t ESDC : 1; /*!< [25..25] Error status: Data RAM 1-bit error */ + __IOM uint32_t ESTE2 : 1; /*!< [26..26] Error status: Tag RAM 2-bits error */ + __IOM uint32_t ESTE1 : 1; /*!< [27..27] Error status: Tag RAM 1-bit error */ + __IOM uint32_t ESPBSE : 1; /*!< [28..28] Error status: WAY error */ + __IOM uint32_t ESMH : 1; /*!< [29..29] Error status: Multi hit */ + __IOM uint32_t ESAFE : 1; /*!< [30..30] Error status: Address feedback error */ + __IOM uint32_t CISTW : 1; /*!< [31..31] This bit is set to indicate that the destination way + * specified for a CISTIinstruction was in error. Although + * the entry information is overwritten so thatwriting is + * completed, the V bit will be cleared the next time the + * cache line isread (i.e. reading will be judged to have + * missed the cache). However, settingof this bit is not accompanied + * by an exception for the CPU. */ + } ICERR_b; +} RH850_ICACHE_ICERR_Type; + +/** @brief Cache Operation Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_ICACHE ================ */ +/* ================================================================================================================== */ + +/* ======================================================== ICTAGL ================================================ */ + #define R_ICACHE_ICTAGL_LPN_Pos (11UL) /*!< LPN (Bit 11) */ + #define R_ICACHE_ICTAGL_LPN_Msk (0xfffff800UL) /*!< LPN (Bitfield-Mask: 0x1fffff) */ + #define R_ICACHE_ICTAGL_LRU_Pos (4UL) /*!< LRU (Bit 4) */ + #define R_ICACHE_ICTAGL_LRU_Msk (0x30UL) /*!< LRU (Bitfield-Mask: 0x03) */ + #define R_ICACHE_ICTAGL_L_Pos (2UL) /*!< L (Bit 2) */ + #define R_ICACHE_ICTAGL_L_Msk (0x4UL) /*!< L (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGL_V_Pos (0UL) /*!< V (Bit 0) */ + #define R_ICACHE_ICTAGL_V_Msk (0x1UL) /*!< V (Bitfield-Mask: 0x01) */ +/* ======================================================== ICTAGH ================================================ */ + #define R_ICACHE_ICTAGH_WD_Pos (31UL) /*!< WD (Bit 31) */ + #define R_ICACHE_ICTAGH_WD_Msk (0x80000000UL) /*!< WD (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_PD_Pos (30UL) /*!< PD (Bit 30) */ + #define R_ICACHE_ICTAGH_PD_Msk (0x40000000UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_WT_Pos (29UL) /*!< WT (Bit 29) */ + #define R_ICACHE_ICTAGH_WT_Msk (0x20000000UL) /*!< WT (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_PT_Pos (28UL) /*!< PT (Bit 28) */ + #define R_ICACHE_ICTAGH_PT_Msk (0x10000000UL) /*!< PT (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICTAGH_DATAECC_Pos (16UL) /*!< DATAECC (Bit 16) */ + #define R_ICACHE_ICTAGH_DATAECC_Msk (0xff0000UL) /*!< DATAECC (Bitfield-Mask: 0xff) */ + #define R_ICACHE_ICTAGH_TAGECC_Pos (8UL) /*!< TAGECC (Bit 8) */ + #define R_ICACHE_ICTAGH_TAGECC_Msk (0xff00UL) /*!< TAGECC (Bitfield-Mask: 0xff) */ +/* ======================================================== ICDATL ================================================ */ + #define R_ICACHE_ICDATL_DATAL_Pos (0UL) /*!< DATAL (Bit 0) */ + #define R_ICACHE_ICDATL_DATAL_Msk (0xffffffffUL) /*!< DATAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICDATH ================================================ */ + #define R_ICACHE_ICDATH_DATAH_Pos (0UL) /*!< DATAH (Bit 0) */ + #define R_ICACHE_ICDATH_DATAH_Msk (0xffffffffUL) /*!< DATAH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICCTRL ================================================ */ + #define R_ICACHE_ICCTRL_ICHCLR_Pos (8UL) /*!< ICHCLR (Bit 8) */ + #define R_ICACHE_ICCTRL_ICHCLR_Msk (0x100UL) /*!< ICHCLR (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEIV_Pos (2UL) /*!< ICHEIV (Bit 2) */ + #define R_ICACHE_ICCTRL_ICHEIV_Msk (0x4UL) /*!< ICHEIV (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEMK_Pos (1UL) /*!< ICHEMK (Bit 1) */ + #define R_ICACHE_ICCTRL_ICHEMK_Msk (0x2UL) /*!< ICHEMK (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICCTRL_ICHEN_Pos (0UL) /*!< ICHEN (Bit 0) */ + #define R_ICACHE_ICCTRL_ICHEN_Msk (0x1UL) /*!< ICHEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCFG ================================================ */ + #define R_ICACHE_ICCFG_ICHSIZE_Pos (8UL) /*!< ICHSIZE (Bit 8) */ + #define R_ICACHE_ICCFG_ICHSIZE_Msk (0x7f00UL) /*!< ICHSIZE (Bitfield-Mask: 0x7f) */ + #define R_ICACHE_ICCFG_ICHLINE_Pos (4UL) /*!< ICHLINE (Bit 4) */ + #define R_ICACHE_ICCFG_ICHLINE_Msk (0xf0UL) /*!< ICHLINE (Bitfield-Mask: 0x0f) */ + #define R_ICACHE_ICCFG_ICHWAY_Pos (0UL) /*!< ICHWAY (Bit 0) */ + #define R_ICACHE_ICCFG_ICHWAY_Msk (0xfUL) /*!< ICHWAY (Bitfield-Mask: 0x0f) */ +/* ========================================================= ICERR ================================================ */ + #define R_ICACHE_ICERR_CISTW_Pos (31UL) /*!< CISTW (Bit 31) */ + #define R_ICACHE_ICERR_CISTW_Msk (0x80000000UL) /*!< CISTW (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESAFE_Pos (30UL) /*!< ESAFE (Bit 30) */ + #define R_ICACHE_ICERR_ESAFE_Msk (0x40000000UL) /*!< ESAFE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESMH_Pos (29UL) /*!< ESMH (Bit 29) */ + #define R_ICACHE_ICERR_ESMH_Msk (0x20000000UL) /*!< ESMH (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESPBSE_Pos (28UL) /*!< ESPBSE (Bit 28) */ + #define R_ICACHE_ICERR_ESPBSE_Msk (0x10000000UL) /*!< ESPBSE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESTE1_Pos (27UL) /*!< ESTE1 (Bit 27) */ + #define R_ICACHE_ICERR_ESTE1_Msk (0x8000000UL) /*!< ESTE1 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESTE2_Pos (26UL) /*!< ESTE2 (Bit 26) */ + #define R_ICACHE_ICERR_ESTE2_Msk (0x4000000UL) /*!< ESTE2 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESDC_Pos (25UL) /*!< ESDC (Bit 25) */ + #define R_ICACHE_ICERR_ESDC_Msk (0x2000000UL) /*!< ESDC (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ESDE_Pos (24UL) /*!< ESDE (Bit 24) */ + #define R_ICACHE_ICERR_ESDE_Msk (0x1000000UL) /*!< ESDE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMAFE_Pos (22UL) /*!< ERMAFE (Bit 22) */ + #define R_ICACHE_ICERR_ERMAFE_Msk (0x400000UL) /*!< ERMAFE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMMH_Pos (21UL) /*!< ERMMH (Bit 21) */ + #define R_ICACHE_ICERR_ERMMH_Msk (0x200000UL) /*!< ERMMH (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMPBSE_Pos (20UL) /*!< ERMPBSE (Bit 20) */ + #define R_ICACHE_ICERR_ERMPBSE_Msk (0x100000UL) /*!< ERMPBSE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMTE1_Pos (19UL) /*!< ERMTE1 (Bit 19) */ + #define R_ICACHE_ICERR_ERMTE1_Msk (0x80000UL) /*!< ERMTE1 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMTE2_Pos (18UL) /*!< ERMTE2 (Bit 18) */ + #define R_ICACHE_ICERR_ERMTE2_Msk (0x40000UL) /*!< ERMTE2 (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMDC_Pos (17UL) /*!< ERMDC (Bit 17) */ + #define R_ICACHE_ICERR_ERMDC_Msk (0x20000UL) /*!< ERMDC (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ERMDE_Pos (16UL) /*!< ERMDE (Bit 16) */ + #define R_ICACHE_ICERR_ERMDE_Msk (0x10000UL) /*!< ERMDE (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHEWY_Pos (13UL) /*!< ICHEWY (Bit 13) */ + #define R_ICACHE_ICERR_ICHEWY_Msk (0xe000UL) /*!< ICHEWY (Bitfield-Mask: 0x07) */ + #define R_ICACHE_ICERR_ICHEIX_Pos (5UL) /*!< ICHEIX (Bit 5) */ + #define R_ICACHE_ICERR_ICHEIX_Msk (0x1fe0UL) /*!< ICHEIX (Bitfield-Mask: 0xff) */ + #define R_ICACHE_ICERR_ICHERQ_Pos (4UL) /*!< ICHERQ (Bit 4) */ + #define R_ICACHE_ICERR_ICHERQ_Msk (0x10UL) /*!< ICHERQ (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHED_Pos (3UL) /*!< ICHED (Bit 3) */ + #define R_ICACHE_ICERR_ICHED_Msk (0x8UL) /*!< ICHED (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHET_Pos (2UL) /*!< ICHET (Bit 2) */ + #define R_ICACHE_ICERR_ICHET_Msk (0x4UL) /*!< ICHET (Bitfield-Mask: 0x01) */ + #define R_ICACHE_ICERR_ICHERR_Pos (0UL) /*!< ICHERR (Bit 0) */ + #define R_ICACHE_ICERR_ICHERR_Msk (0x1UL) /*!< ICHERR (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4MH_ICACHE */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_PMU Count Function Registers (PMU) + * @brief Type definitions for the Count Function Registers (PMU) + * @{ + */ + +/** + * @brief Structure type to access the Count Function Registers (PMU). + */ + +typedef union +{ + __IOM uint32_t PMUMCTRL; /*!< (@ 0x00000000) Performance Counter User Mode Control */ + + struct + { + __IOM uint32_t PMUE0 : 1; /*!< [0..0] This bit specifies the accessibility of the PMCTRL0, + * PMCOUNT0 and PMSUBCND0 registers in user mode.0: Disables + * accesses to PMCTRL0/PMCOUNT0/PMSUBCND0 in user mode.1: + * Enables accesses to PMCTRL0/PMCOUNT0/PMSUBCND0 in user + * mode. */ + __IOM uint32_t PMUE1 : 1; /*!< [1..1] This bit specifies the accessibility of the PMCTRL1, + * PMCOUNT1 and PMSUBCND1 registers in user mode.0: Disables + * accesses to PMCTRL1/PMCOUNT1/PMSUBCND1 in user mode.1: + * Enables accesses to PMCTRL1/PMCOUNT1/PMSUBCND1 in user + * mode. */ + __IOM uint32_t PMUE2 : 1; /*!< [2..2] This bit specifies the accessibility of the PMCTRL2, + * PMCOUNT2 and PMSUBCND2 registers in user mode.0: Disables + * accesses to PMCTRL2/PMCOUNT2/PMSUBCND2 in user mode.1: + * Enables accesses to PMCTRL2/PMCOUNT2/PMSUBCND2 in user + * mode. */ + __IOM uint32_t PMUE3 : 1; /*!< [3..3] This bit specifies the accessibility of the PMCTRL3, + * PMCOUNT3 and PMSUBCND3 registers in user mode.0: Disables + * accesses to PMCTRL3/PMCOUNT3/PMSUBCND3 in user mode.1: + * Enables accesses to PMCTRL3/PMCOUNT3/PMSUBCND3 in user + * mode. */ + __IOM uint32_t PMUE4 : 1; /*!< [4..4] This bit specifies the accessibility of the PMCTRL4, + * PMCOUNT4 and PMSUBCND4 registers in user mode.0: Disables + * accesses to PMCTRL4/PMCOUNT4/PMSUBCND4 in user mode.1: + * Enables accesses to PMCTRL4/PMCOUNT4/PMSUBCND4 in user + * mode. */ + __IOM uint32_t PMUE5 : 1; /*!< [5..5] This bit specifies the accessibility of the PMCTRL5, + * PMCOUNT5 and PMSUBCND5 registers in user mode.0: Disables + * accesses to PMCTRL5/PMCOUNT5/PMSUBCND5 in user mode.1: + * Enables accesses to PMCTRL5/PMCOUNT5/PMSUBCND5 in user + * mode. */ + __IOM uint32_t PMUE6 : 1; /*!< [6..6] This bit specifies the accessibility of the PMCTRL6, + * PMCOUNT6 and PMSUBCND6 registers in user mode.0: Disables + * accesses to PMCTRL6/PMCOUNT6/PMSUBCND6 in user mode.1: + * Enables accesses to PMCTRL6/PMCOUNT6/PMSUBCND6 in user + * mode. */ + __IOM uint32_t PMUE7 : 1; /*!< [7..7] This bit specifies the accessibility of the PMCTRL7, + * PMCOUNT7 and PMSUBCND7 registers in user mode.0: Disables + * accesses to PMCTRL7/PMCOUNT7/PMSUBCND7 in user mode.1: + * Enables accesses to PMCTRL7/PMCOUNT7/PMSUBCND7 in user + * mode. */ + uint32_t : 24; + } PMUMCTRL_b; +} RH850_PMU_PMUMCTRL_Type; + +typedef union +{ + __IOM uint32_t PMCTRL; /*!< (@ 0x00000000) Performance Counter User Mode Control */ + + struct + { + __IOM uint32_t CEN : 1; /*!< [0..0] This bit enables or disables the count operation of the + * PMCOUNTn register.0: Disables count operation.1: Enables + * count operation.If this bit is written with a 1 when it + * is set to 0, the counter starts countingimmediately. If + * this bit is written with a 0 when it is set to 1, the counter + * stopscounting immediately. If this bit is 0, the values + * of the PMCOUNTn register ispreserved. There is no factor + * that will automatically change the value of thisbit. */ + __IOM uint32_t OVF : 1; /*!< [1..1] This bit serves as the overflow flag. This bit is set + * to 1 when an overflowoccurs in the PMCOUNTn register as + * the result of its count operation.This bit is not automatically + * cleared to 0. To reset the overflow state, write a 0into + * this bit.Since this bit can be written with a 1, it can + * be an overflow condition regardlessof the count operation. + * Although it does not affect the counter operation, caremust + * be taken not to take that condition for an overflow. */ + uint32_t : 6; + __IOM uint32_t CND : 8; /*!< [15..8] When read, the value after reset is returned. */ + uint32_t : 16; + } PMCTRL_b; +} RH850_PMU_PMCTRL_Type; + +typedef union +{ + __IOM uint32_t PMCOUNT; /*!< (@ 0x00000000) Performance Count */ + + struct + { + __IOM uint32_t PMCNT : 32; /*!< [31..0] These bits form a 32-bit counter register.The counter + * counts the number of occurrences of the event that is specified + * bythe PMCTRLn.CND bit.When this register counts up from + * FFFF FFFFH, the PMCTRLn.OVF bit is setto 1 and the register + * wraps around to 0000 0000H.This register is accessible + * at an arbitrary timing regardless of whethercounting is + * enabled or disabled. In addition, it is possible to start + * counting at anarbitrary count by loading that value in + * this register before starting to count. */ + } PMCOUNT_b; +} RH850_PMU_PMCOUNT_Type; + +typedef union +{ + __IOM uint32_t PMSUBCND; /*!< (@ 0x00000000) Performance Count */ + + struct + { + __IOM uint32_t SUBCND : 13; /*!< [12..0] How the value of the SUBCND field is used depends on + * the setting of thePMCTRLn.CND. If the value of the PMCTRLn.CND + * is other than the following,the value of the SUBCND field + * does not affect the operation of theperformance counter.R/W + * 0Value of thePMCTRLn.CND Operation of the performance counter20H + * The channel number of the interrupt (EIINTn) for which + * theacceptance count is counted can be limited. The operation + * isspecified by the value of bit 12.0: The channel number + * to be counted is no */ + uint32_t : 19; + } PMSUBCND_b; +} RH850_PMU_PMSUBCND_Type; + +/** @brief Count Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_PMU ================ */ +/* ================================================================================================================== */ + +/* ======================================================= PMUMCTRL =============================================== */ + #define R_PMU_PMUMCTRL_PMUE7_Pos (7UL) /*!< PMUE7 (Bit 7) */ + #define R_PMU_PMUMCTRL_PMUE7_Msk (0x80UL) /*!< PMUE7 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE6_Pos (6UL) /*!< PMUE6 (Bit 6) */ + #define R_PMU_PMUMCTRL_PMUE6_Msk (0x40UL) /*!< PMUE6 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE5_Pos (5UL) /*!< PMUE5 (Bit 5) */ + #define R_PMU_PMUMCTRL_PMUE5_Msk (0x20UL) /*!< PMUE5 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE4_Pos (4UL) /*!< PMUE4 (Bit 4) */ + #define R_PMU_PMUMCTRL_PMUE4_Msk (0x10UL) /*!< PMUE4 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE3_Pos (3UL) /*!< PMUE3 (Bit 3) */ + #define R_PMU_PMUMCTRL_PMUE3_Msk (0x8UL) /*!< PMUE3 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE2_Pos (2UL) /*!< PMUE2 (Bit 2) */ + #define R_PMU_PMUMCTRL_PMUE2_Msk (0x4UL) /*!< PMUE2 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE1_Pos (1UL) /*!< PMUE1 (Bit 1) */ + #define R_PMU_PMUMCTRL_PMUE1_Msk (0x2UL) /*!< PMUE1 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE0_Pos (0UL) /*!< PMUE0 (Bit 0) */ + #define R_PMU_PMUMCTRL_PMUE0_Msk (0x1UL) /*!< PMUE0 (Bitfield-Mask: 0x01) */ + #define R_PMU_PMUMCTRL_PMUE_Msk (0xFFUL) /*!< PMUE0 (Bitfield-Mask: 0x00) */ +/* ======================================================== PMCTRL0 =============================================== */ + #define R_PMU_PMCTRL0_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL0_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL0_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL0_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL0_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL1 =============================================== */ + #define R_PMU_PMCTRL1_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL1_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL1_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL1_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL1_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL1_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL2 =============================================== */ + #define R_PMU_PMCTRL2_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL2_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL2_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL2_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL2_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL2_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL3 =============================================== */ + #define R_PMU_PMCTRL3_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL3_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL3_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL3_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL3_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL3_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL4 =============================================== */ + #define R_PMU_PMCTRL4_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL4_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL4_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL4_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL4_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL4_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL5 =============================================== */ + #define R_PMU_PMCTRL5_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL5_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL5_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL5_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL5_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL5_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL6 =============================================== */ + #define R_PMU_PMCTRL6_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL6_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL6_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL6_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL6_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL6_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== PMCTRL7 =============================================== */ + #define R_PMU_PMCTRL7_CND_Pos (8UL) /*!< CND (Bit 8) */ + #define R_PMU_PMCTRL7_CND_Msk (0xff00UL) /*!< CND (Bitfield-Mask: 0xff) */ + #define R_PMU_PMCTRL7_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_PMU_PMCTRL7_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_PMU_PMCTRL7_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_PMU_PMCTRL7_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PMCOUNT0 =============================================== */ + #define R_PMU_PMCOUNT0_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT0_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT1 =============================================== */ + #define R_PMU_PMCOUNT1_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT1_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT2 =============================================== */ + #define R_PMU_PMCOUNT2_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT2_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT3 =============================================== */ + #define R_PMU_PMCOUNT3_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT3_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT4 =============================================== */ + #define R_PMU_PMCOUNT4_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT4_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT5 =============================================== */ + #define R_PMU_PMCOUNT5_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT5_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT6 =============================================== */ + #define R_PMU_PMCOUNT6_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT6_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMCOUNT7 =============================================== */ + #define R_PMU_PMCOUNT7_PMCNT_Pos (0UL) /*!< PMCNT (Bit 0) */ + #define R_PMU_PMCOUNT7_PMCNT_Msk (0xffffffffUL) /*!< PMCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PMSUBCND0 ============================================== */ + #define R_PMU_PMSUBCND0_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND0_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND1 ============================================== */ + #define R_PMU_PMSUBCND1_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND1_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND2 ==================================== ========= */ + #define R_PMU_PMSUBCND2_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND2_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND3 ============================================== */ + #define R_PMU_PMSUBCND3_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND3_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND4 ============================================== */ + #define R_PMU_PMSUBCND4_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND4_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND5 ============================================== */ + #define R_PMU_PMSUBCND5_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND5_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND6 ============================================== */ + #define R_PMU_PMSUBCND6_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND6_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ +/* ======================================================= PMSUBCND7 ============================================== */ + #define R_PMU_PMSUBCND7_SUBCND_Pos (0UL) /*!< SUBCND (Bit 0) */ + #define R_PMU_PMSUBCND7_SUBCND_Msk (0x1fffUL) /*!< SUBCND (Bitfield-Mask: 0x1fff) */ + +/*@}*/ /* end of group RH850_G4MH_PMU */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_HWF Hardware Function Registers (HWF) + * @brief Type definitions for the Hardware Function Registers (HWF) + * @{ + */ + +/** + * @brief Structure type to access the Hardware Function Registers (HWF). + */ + +typedef union +{ + __IOM uint32_t LSTEST0; /*!< (@ 0x00000000) Lock-step Function Self-diagnosis Register 0 */ + + struct + { + __IOM uint32_t LSTEST0 : 32; /*!< [31..0] [Write]Write any value to bits of the LSTEST0 register.[Read]Value + * in LSTEST0 is read by the master CPU of the lock-stepped + * CPU.Value in LSTEST1 is read by the checker CPU of the + * lock-stepped CPU. */ + } LSTEST0_b; +} RH850_HWF_LSTEST0_Type; + +typedef union +{ + __IOM uint32_t LSTEST1; /*!< (@ 0x00000000) Lock-step Function Self-diagnosis Register 1 */ + + struct + { + __IOM uint32_t LSTEST1 : 32; /*!< [31..0] [Write]Write any value to bits of the LSTEST1 register.[Read]Value + * in LSTEST1 is read by the master CPU of the lock-stepped + * CPU.Value in LSTEST0 is read by the checker CPU of the + * lock-stepped CPU. */ + } LSTEST1_b; +} RH850_HWF_LSTEST1_Type; + +typedef union +{ + __IOM uint32_t LSCFG; /*!< (@ 0x00000000) Configuration of Lock Step function */ + + struct + { + __IOM uint32_t LSE : 1; /*!< [0..0] This bit indicates the availability of the Lock Step + * function.0: The Lock Step function is not available.1: + * The Lock Step function is available. */ + uint32_t : 31; + } LSCFG_b; +} RH850_HWF_LSCFG_type; + +typedef union +{ + __IOM uint32_t IFCR; /*!< (@ 0x00000000) Instruction Fetch Control Register */ + + struct + { + __IOM uint32_t PLEN : 1; /*!< [0..0] This bit specifies whether the instruction fetch preload + * function is enabled ordisabled.0: Disabled1: Enabled */ + uint32_t : 31; + } IFCR_b; +} RH850_HWF_IFCR_Type; + +typedef union +{ + __IOM uint32_t BRPCTRL0; /*!< (@ 0x00000000) Branch Prediction Function Control Register */ + + struct + { + __IOM uint32_t BRPEN : 1; /*!< [0..0] This bit specifies whether the branch prediction function*1 + * is enabled ordisabled.0: Disabled1: Enabled */ + __IOM uint32_t BRPCLR : 1; /*!< [1..1] Setting this bit to 1 clears the buffers related to branch + * prediction function. Thisbit is always read as 0. */ + uint32_t : 30; + } BRPCTRL0_b; +} RH850_HWF_BRPCTRL0_Type; + +typedef union +{ + __IOM uint32_t L1RCFG; /*!< (@ 0x00000000) Configuration of L1RAM */ + + struct + { + __IM uint32_t L1RLNKE : 4; /*!< [3..0] This field indicates the number of entries of links available + * in L1RAM.(For example: 0010B: 2 entries) */ + uint32_t : 4; + __IM uint32_t L1RSIZE : 22; /*!< [29..8] This field indicates the L1RAM capacity (Kbytes).(For + * example: 000020H: 32 Kbytes) */ + uint32_t : 2; + } L1RCFG_b; +} RH850_HWF_L1RCFG_type; + +typedef union +{ + __IOM uint32_t RDBCR; /*!< (@ 0x00000000) ROM Data Buffer Control Register */ + + struct + { + __IOM uint32_t RDBEN : 1; /*!< [0..0] This bit specifies whether the ROM data buffer is enabled + * or disabled.0: ROM data buffer is disabled.1: ROM data + * buffer is enabled. */ + __IOM uint32_t RDBCLR : 1; /*!< [1..1] Setting this bit (to 1) clears the ROM data buffer and + * initializes the LRUinformation in the ROM data buffer.If + * this bit is set (to 1) during load processing or when a + * bus request issued bythe prefetch function is present, + * the load data is not registered in the ROMdata buffer.This + * bit is always read as 0. */ + uint32_t : 30; + } RDBCR_b; +} RH850_HWF_RDBCR_Type; + +/** @brief Hardware Function Registers macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_HWF ================ */ +/* ================================================================================================================== */ + +/* ======================================================== LSTEST0 =============================================== */ + #define R_HWF_LSTEST0_LSTEST0_Pos (0UL) /*!< LSTEST0 (Bit 0) */ + #define R_HWF_LSTEST0_LSTEST0_Msk (0xffffffffUL) /*!< LSTEST0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LSTEST1 =============================================== */ + #define R_HWF_LSTEST1_LSTEST1_Pos (0UL) /*!< LSTEST1 (Bit 0) */ + #define R_HWF_LSTEST1_LSTEST1_Msk (0xffffffffUL) /*!< LSTEST1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LSCFG ================================================ */ + #define R_HWF_LSCFG_LSE_Pos (0UL) /*!< LSE (Bit 0) */ + #define R_HWF_LSCFG_LSE_Msk (0x1UL) /*!< LSE (Bitfield-Mask: 0x01) */ +/* ========================================================= IFCR ================================================= */ + #define R_HWF_IFCR_PLEN_Pos (0UL) /*!< PLEN (Bit 0) */ + #define R_HWF_IFCR_PLEN_Msk (0x1UL) /*!< PLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= BRPCTRL0 =============================================== */ + #define R_HWF_BRPCTRL0_BRPCLR_Pos (1UL) /*!< BRPCLR (Bit 1) */ + #define R_HWF_BRPCTRL0_BRPCLR_Msk (0x2UL) /*!< BRPCLR (Bitfield-Mask: 0x01) */ + #define R_HWF_BRPCTRL0_BRPEN_Pos (0UL) /*!< BRPEN (Bit 0) */ + #define R_HWF_BRPCTRL0_BRPEN_Msk (0x1UL) /*!< BRPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== L1RCFG ================================================ */ + #define R_HWF_L1RCFG_L1RSIZE_Pos (8UL) /*!< L1RSIZE (Bit 8) */ + #define R_HWF_L1RCFG_L1RSIZE_Msk (0x3fffff00UL) /*!< L1RSIZE (Bitfield-Mask: 0x3fffff) */ + #define R_HWF_L1RCFG_L1RLNKE_Pos (0UL) /*!< L1RLNKE (Bit 0) */ + #define R_HWF_L1RCFG_L1RLNKE_Msk (0xfUL) /*!< L1RLNKE (Bitfield-Mask: 0x0f) */ +/* ========================================================= RDBCR ================================================ */ + #define R_HWF_RDBCR_RDBCLR_Pos (1UL) /*!< RDBCLR (Bit 1) */ + #define R_HWF_RDBCR_RDBCLR_Msk (0x2UL) /*!< RDBCLR (Bitfield-Mask: 0x01) */ + #define R_HWF_RDBCR_RDBEN_Pos (0UL) /*!< RDBEN (Bit 0) */ + #define R_HWF_RDBCR_RDBEN_Msk (0x1UL) /*!< RDBEN (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4MH_HWF */ + +/** + * @ingroup RH850_G4MH_Core_register + * @defgroup RH850_G4MH_TSC Timestamp counter (TSC) + * @brief Type definitions for the Timestamp counter (TSC) + * @{ + */ + +/** + * @brief Structure type to access the Timestamp counter (TSC). + */ + +typedef union +{ + __IOM uint32_t TSCOUNTL; /*!< (@ 0x00000000) Timestamp Count L */ + + struct + { + __IOM uint32_t TSCNTL : 32; /*!< [31..0] These bits account for the lower-order 32 bits of the + * 64-bit counter.If counting is enabled by the TSCTRL register, + * the value of this register isincremented by 1 on every + * clock cycle.When this register counts up from FFFF FFFFH, + * the TSCOUNTH register isincremented by 1 as a carryover + * and this register wraps around to0000 0000H.This register + * is accessible at an arbitrary timing regardless of whethercounting + * is enabled or disabled. In addition, it is possible to + * start counting at anarbitrary */ + } TSCOUNTL_b; +} RH850_TSC_TSCOUNTL_Type; + +typedef union +{ + __IOM uint32_t TSCOUNTH; /*!< (@ 0x00000000) Timestamp Count H */ + + struct + { + __IOM uint32_t TSCNTH : 32; /*!< [31..0] These bits account for the higher-order 32 bits of the + * 64-bit counter.If counting is enabled by the TSCTRL register, + * the value of this register isincremented by 1 when the + * TSCOUNTL register counts up and generates acarryover.If + * a carryover occurs in the TSCOUNTL register when this register + * holds avalue of FFFF FFFFH, the TSCTRL.OVF bit is set to + * 1 and this register wrapsaround to 0000 0000H.This register + * is accessible at an arbitrary timing regardless of whethercounting + * is enabled or disabl */ + } TSCOUNTH_b; +} RH850_TSC_TSCOUNTH_Type; + +typedef union +{ + __IOM uint32_t TSCTRL; /*!< (@ 0x00000000) Timestamp Count Control */ + + struct + { + __IOM uint32_t CEN : 1; /*!< [0..0] This bit enables or disables the count operation of the + * 64-bit timestampcounter which is implemented by combining + * the TSCOUNTH and TSCOUNTLregisters.0: Disables count operation.1: + * Enables count operation.If this bit is written with a 1 + * when it is set to 0, the counter starts countingimmediately. + * If this bit is written with a 0 when it is set to 1, the + * counter stopscounting immediately. If this bit is 0, the + * values of the TSCOUNTH andTSCOUNTL registers are preserved. + * There is no factor that */ + __IOM uint32_t OVF : 1; /*!< [1..1] This bit serves as the overflow flag. This bit is set + * to 1 when an overflowoccurs in the TSCOUNTH register as + * the result of its count operation.This bit is not automatically + * cleared to 0. To reset the overflow state, write a 0into + * this bit.Since this bit can be written with a 1, it can + * be an overflow condition regardlessof the count operation. + * Although it does not affect the counter operation, caremust + * be taken not to take that condition for an overflow. */ + uint32_t : 30; + } TSCTRL_b; +} RH850_TSC_TSCTRL_Type; + +/** @brief Timestamp counter macro Definitions */ + +/* ================================================================================================================== */ +/* ================ R_TSC ================ */ +/* ================================================================================================================== */ + +/* ======================================================= TSCOUNTL =============================================== */ + #define R_TSC_TSCOUNTL_TSCNTL_Pos (0UL) /*!< TSCNTL (Bit 0) */ + #define R_TSC_TSCOUNTL_TSCNTL_Msk (0xffffffffUL) /*!< TSCNTL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TSCOUNTH =============================================== */ + #define R_TSC_TSCOUNTH_TSCNTH_Pos (0UL) /*!< TSCNTH (Bit 0) */ + #define R_TSC_TSCOUNTH_TSCNTH_Msk (0xffffffffUL) /*!< TSCNTH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSCTRL ================================================ */ + #define R_TSC_TSCTRL_OVF_Pos (1UL) /*!< OVF (Bit 1) */ + #define R_TSC_TSCTRL_OVF_Msk (0x2UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_TSC_TSCTRL_CEN_Pos (0UL) /*!< CEN (Bit 0) */ + #define R_TSC_TSCTRL_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ + +/*@}*/ /* end of group RH850_G4MH_TSC */ + +/*@}*/ /* end of group RH850_G4MH_Core_register */ +/*@}*/ /* end of group G4MH_Core_register */ + +/*********************************************************************************************************************** + * Hardware Abstraction Layer + **********************************************************************************************************************/ + +/** + * @defgroup RH850_API_Funcs RH850 Macro Wrapper API Functions + * @brief RH850 API Functions + * @defgroup RH850_G4MH_API_Funcs RH850 G4MH Macro Wrapper API Functions + * @brief RH850 G4MH Macro Wrapper API Functions + * @ingroup RH850_API_Funcs + * @{ + */ + +/* ############################################# FPU functions #################################################### */ + #if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_FPU_API FPU API Functions + * @brief FPU API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + #include "G4-profile/rh850_g4_fpu.h" + + #define RH850_FPU_Enable __RH850_FPU_Enable /*!< Wrapper macro that calls the @ref __RH850_FPU_Enable */ + #define RH850_FPU_Disable __RH850_FPU_Disable /*!< Wrapper macro that calls the @ref __RH850_FPU_Disable */ + #define RH850_FPU_EnableGet __RH850_FPU_EnableGet /*!< Wrapper macro that calls the @ref __RH850_FPU_EnableGet */ + #define RH850_FPU_StatusGet __RH850_FPU_StatusGet /*!< Wrapper macro that calls the @ref __RH850_FPU_StatusGet */ + #define RH850_FPU_StatusClear __RH850_FPU_StatusClear /*!< Wrapper macro that calls the @ref __RH850_FPU_StatusClear */ + #define RH850_FPU_FpsrCcBitGet __RH850_FPU_FpsrCcBitGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrCcBitGet */ + #define RH850_FPU_FpsrCcBitSet __RH850_FPU_FpsrCcBitSet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrCcBitSet */ + #define RH850_FPU_FpsrIfBitGet __RH850_FPU_FpsrIfBitGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpsrIfBitGet */ + #define RH850_FPU_ModeFlushSet __RH850_FPU_ModeFlushSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeFlushSet */ + #define RH850_FPU_ModeFlushGet __RH850_FPU_ModeFlushGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeFlushGet */ + #define RH850_FPU_ModeRoundingSet __RH850_FPU_ModeRoundingSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeRoundingSet */ + #define RH850_FPU_ModeRoundingGet __RH850_FPU_ModeRoundingGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ModeRoundingGet */ + #define RH850_FPU_ExceptionEnableSet __RH850_FPU_ExceptionEnableSet /*!< Wrapper macro that calls the @ref __RH850_FPU_ExceptionEnableSet */ + #define RH850_FPU_ExceptionEnableGet __RH850_FPU_ExceptionEnableGet /*!< Wrapper macro that calls the @ref __RH850_FPU_ExceptionEnableGet*/ + #define RH850_FPU_FpepcGet __RH850_FPU_FpepcGet /*!< Wrapper macro that calls the @ref __RH850_FPU_FpepcGet*/ +/** @} */ /* end of RH850_FPU */ + #endif + +/* ############################################# FXU functions #################################################### */ + #if defined(__FXU_PRESENT) && (__FXU_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_FXU_API FXU API Functions + * @brief FXU API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_fxu.h" + + #define RH850_FXU_Enable __RH850_FXU_Enable /*!< Wrapper macro that calls the @ref __RH850_FXU_Enable */ + #define RH850_FXU_Disable __RH850_FXU_Disable /*!< Wrapper macro that calls the @ref __RH850_FXU_Disable */ + #define RH850_FXU_FxsrIfBitGet __RH850_FXU_FxsrIfBitGet /*!< Wrapper macro that calls the @ref __RH850_FXU_FxsrIfBitGet */ + #define RH850_FXU_ModeFlushSet __RH850_FXU_ModeFlushSet /*!< Wrapper macro that calls the @ref __RH850_FXU_ModeFlushSet */ + #define RH850_FXU_SimdUnitCheck __RH850_FXU_SimdUnitCheck /*!< Wrapper macro that calls the @ref __RH850_FXU_SimdUnitCheck */ + #define RH850_FXU_VectorRegisterCheck __RH850_FXU_VectorRegisterCheck /*!< Wrapper macro that calls the @ref __RH850_FXU_VectorRegisterCheck */ + #define RH850_FXU_ModeRoundingSet __RH850_FXU_ModeRoundingSet /*!< Wrapper macro that calls the @ref __RH850_FXU_ModeRoundingSet */ + #define RH850_FXU_ExceptionEnableSet __RH850_FXU_ExceptionEnableSet /*!< Wrapper macro that calls the @ref __RH850_FXU_ExceptionEnableSet */ + #define RH850_FXU_CauseBitsGet __RH850_FXU_CauseBitsGet /*!< Wrapper macro that calls the @ref __RH850_FXU_CauseBitsGet */ + #define RH850_FXU_PreservationBitsGet __RH850_FXU_PreservationBitsGet /*!< Wrapper macro that calls the @ref __RH850_FXU_PreservationBitsGet */ + #define RH850_FXU_StatusGet __RH850_FXU_StatusGet /*!< Wrapper macro that calls the @ref __RH850_FXU_StatusGet */ + #define RH850_FXU_StatusClear __RH850_FXU_StatusClear /*!< Wrapper macro that calls the @ref __RH850_FXU_StatusClear */ +/** @} */ /* end of RH850_FXU */ + #endif + +/* ########################## ICACHE functions ################################## */ + #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_ICACHE_API ICACHE API Functions + * @brief ICACHE API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_icache.h" + + #define RH850_ICache_Enable __RH850_ICache_Enable /*!< Wrapper macro that calls the @ref __RH850_ICache_Enable */ + #define RH850_ICache_Disable __RH850_ICache_Disable /*!< Wrapper macro that calls the @ref __RH850_ICache_Disable */ + #define RH850_ICache_EnableGet __RH850_ICache_EnableGet /*!< Wrapper macro that calls the @ref __RH850_ICache_EnableGet */ + #define RH850_ICache_CacheSizeGet __RH850_ICache_CacheSizeGet /*!< Wrapper macro that calls the @ref __RH850_ICache_CacheSizeGet */ + #define RH850_ICache_LinesPerWayGet __RH850_ICache_LinesPerWayGet /*!< Wrapper macro that calls the @ref __RH850_ICache_LinesPerWayGet */ + #define RH850_ICache_NumberOfWaysGet __RH850_ICache_NumberOfWaysGet /*!< Wrapper macro that calls the @ref __RH850_ICache_NumberOfWaysGet */ + #define RH850_ICache_ErrorStatusGet __RH850_ICache_ErrorStatusGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorStatusGet */ + #define RH850_ICache_ErrorIndexGet __RH850_ICache_ErrorIndexGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorIndexGet */ + #define RH850_ICache_ErrorWayGet __RH850_ICache_ErrorWayGet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorWayGet */ + #define RH850_ICache_Clear __RH850_ICache_Clear /*!< Wrapper macro that calls the @ref __RH850_ICache_Clear */ + #define RH850_ICache_AutoInvalidateOnErrorSet __RH850_ICache_AutoInvalidateOnErrorSet /*!< Wrapper macro that calls the @ref __RH850_ICache_AutoInvalidateOnErrorSet */ + #define RH850_ICache_ErrorNotifyMaskSet __RH850_ICache_ErrorNotifyMaskSet /*!< Wrapper macro that calls the @ref __RH850_ICache_ErrorNotifyMaskSet */ + #define RH850_ICache_TagLoGet __RH850_ICache_TagLoGet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagLoGet */ + #define RH850_ICache_TagLoSet __RH850_ICache_TagLoSet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagLoSet */ + #define RH850_ICache_TagHiGet __RH850_ICache_TagHiGet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagHiGet */ + #define RH850_ICache_TagHiSet __RH850_ICache_TagHiSet /*!< Wrapper macro that calls the @ref __RH850_ICache_TagHiSet */ + #define RH850_ICache_DataLoGet __RH850_ICache_DataLoGet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataLoGet */ + #define RH850_ICache_DataLoSet __RH850_ICache_DataLoSet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataLoSet */ + #define RH850_ICache_DataHiGet __RH850_ICache_DataHiGet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataHiGet */ + #define RH850_ICache_DataHiSet __RH850_ICache_DataHiSet /*!< Wrapper macro that calls the @ref __RH850_ICache_DataHiSet */ +/** @} */ /* end of RH850_ICACHE */ + #endif + +/* ############################################# IRQ functions #################################################### */ + #if defined(__IRQ_PRESENT) && (__IRQ_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_IRQ_API IRQ API Functions + * @brief IRQ API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #define RH850_INTC1_BASE 0xFFFC4000UL + #define RH850_INTC2_BASE 0xFFF80000UL + #define RH850_INTC1_OFFSET 0x4000U + #define RH850_INTC1_EIBD_OFFSET 0x0100U + #define RH850_INTC2_EIBD_OFFSET 0x2000U + #define RH850_INTC1_EEIC_OFFSET 0x0200U + #define RH850_INTC2_EEIC_OFFSET 0x4000U + + #include "G4-profile/rh850_g4_irq.h" + + #define RH850_IRQ_InterruptPriorityGet __RH850_IRQ_InterruptPriorityGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptPriorityGet */ + #define RH850_IRQ_InterruptMaskStatusGet __RH850_IRQ_InterruptMaskStatusGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptMaskStatusGet */ + #define RH850_IRQ_InterruptControlStatusGet __RH850_IRQ_InterruptControlStatusGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_InterruptControlStatusGet */ + #define RH850_IRQ_PriorityExtensionGet __RH850_IRQ_PriorityExtensionGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityExtensionGet */ + #define RH850_IRQ_PriorityExtensionSet __RH850_IRQ_PriorityExtensionSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityExtensionSet */ + #define RH850_IRQ_IsprUpdateModeGet __RH850_IRQ_IsprUpdateModeGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IsprUpdateModeGet */ + #define RH850_IRQ_IsprUpdateModeSet __RH850_IRQ_IsprUpdateModeSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IsprUpdateModeSet */ + #define RH850_IRQ_RegisterBankLimitGet __RH850_IRQ_RegisterBankLimitGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_RegisterBankLimitGet */ + #define RH850_IRQ_RegisterBankLimitSet __RH850_IRQ_RegisterBankLimitSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_RegisterBankLimitSet */ + #define RH850_IRQ_PriorityMaskLevelGet __RH850_IRQ_PriorityMaskLevelGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityMaskLevelGet */ + #define RH850_IRQ_PriorityMaskLevelSet __RH850_IRQ_PriorityMaskLevelSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_PriorityMaskLevelSet */ + #define RH850_IRQ_IntMaskGet __RH850_IRQ_IntMaskGet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskGet */ + #define RH850_IRQ_IntMaskSet __RH850_IRQ_IntMaskSet /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ + #define RH850_IRQ_EnableIRQ __RH850_IRQ_EnableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_EnableIRQ */ + #define RH850_IRQ_EnableIRQByPE __RH850_IRQ_EnableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_EnableIRQ */ + #define RH850_IRQ_GetEnableIRQ __RH850_IRQ_GetEnableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetEnableIRQ */ + #define RH850_IRQ_GetEnableIRQByPE __RH850_IRQ_GetEnableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetEnableIRQ */ + #define RH850_IRQ_DisableIRQ __RH850_IRQ_DisableIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_DisableIRQ */ + #define RH850_IRQ_DisableIRQByPE __RH850_IRQ_DisableIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_DisableIRQ */ + #define RH850_IRQ_GetPendingIRQ __RH850_IRQ_GetPendingIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPendingIRQ */ + #define RH850_IRQ_GetPendingIRQByPE __RH850_IRQ_GetPendingIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPendingIRQ */ + #define RH850_IRQ_ClearPendingIRQ __RH850_IRQ_ClearPendingIRQ /*!< Wrapper macro that calls the @ref __RH850_IRQ_ClearPendingIRQ */ + #define RH850_IRQ_ClearPendingIRQByPE __RH850_IRQ_ClearPendingIRQByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_ClearPendingIRQ */ + #define RH850_IRQ_GetActive __RH850_IRQ_GetActive /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetActive */ + #define RH850_IRQ_GetActiveByPE __RH850_IRQ_GetActiveByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetActive */ + #define RH850_IRQ_SetPriority __RH850_IRQ_SetPriority /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetPriority */ + #define RH850_IRQ_SetPriorityByPE __RH850_IRQ_SetPriorityByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetPriority */ + #define RH850_IRQ_GetPriority __RH850_IRQ_GetPriority /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPriority */ + #define RH850_IRQ_GetPriorityByPE __RH850_IRQ_GetPriorityByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetPriority */ + #define RH850_IRQ_SetIRQMethod __RH850_IRQ_SetIRQMethod /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetIRQMethod */ + #define RH850_IRQ_SetIRQMethodByPE __RH850_IRQ_SetIRQMethodByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_SetIRQMethod */ + #define RH850_IRQ_GetIRQMethod __RH850_IRQ_GetIRQMethod /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetIRQMethod */ + #define RH850_IRQ_GetIRQMethodByPE __RH850_IRQ_GetIRQMethodByPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_GetIRQMethod */ + #define RH850_IRQ_SetIRQBoundToPE __RH850_IRQ_SetIRQBoundToPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ + #define RH850_IRQ_GetIRQBoundToPE __RH850_IRQ_GetIRQBoundToPE /*!< Wrapper macro that calls the @ref __RH850_IRQ_IntMaskSet */ +/** @} */ /* end of RH850_IRQ */ + #endif + +/* ############################################# MPU functions #################################################### */ + #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_MPU_API MPU API Functions + * @brief MPU API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_mpu.h" + + #define RH850_MPU_Enable __RH850_MPU_Enable /*!< Wrapper macro that calls the @ref __RH850_MPU_Enable */ + #define RH850_MPU_Disable __RH850_MPU_Disable /*!< Wrapper macro that calls the @ref __RH850_MPU_Disable */ + #define RH850_MPU_MpidSet __RH850_MPU_MpidSet /*!< Wrapper macro that calls the @ref __RH850_MPU_MpidSet */ + #define RH850_MPU_StateGet __RH850_MPU_StateGet /*!< Wrapper macro that calls the @ref __RH850_MPU_StateGet */ + #define RH850_MPU_SvStateGet __RH850_MPU_SvStateGet /*!< Wrapper macro that calls the @ref __RH850_MPU_SvStateGet */ + #define RH850_MPU_NumberofRegionsGet __RH850_MPU_NumberofRegionsGet /*!< Wrapper macro that calls the @ref __RH850_MPU_NumberofRegionsGet */ + #define RH850_MPU_NumberOfBanksGet __RH850_MPU_NumberOfBanksGet /*!< Wrapper macro that calls the @ref __RH850_MPU_NumberOfBanksGet */ + #define RH850_MPU_ArchitectureVersionGet __RH850_MPU_ArchitectureVersionGet /*!< Wrapper macro that calls the @ref __RH850_MPU_ArchitectureVersionGet */ + #define RH850_MPU_ExecMemProtectCheck __RH850_MPU_ExecMemProtectCheck /*!< Wrapper macro that calls the @ref __RH850_MPU_ExecMemProtectCheck */ + #define RH850_MPU_MpuIdSet __RH850_MPU_MpuIdSet /*!< Wrapper macro that calls the @ref __RH850_MPU_MpuIdSet */ + #define RH850_MPU_BankGet __RH850_MPU_BankGet /*!< Wrapper macro that calls the @ref __RH850_MPU_BankGet */ + #define RH850_MPU_AttrSet __RH850_MPU_AttrSet /*!< Wrapper macro that calls the @ref __RH850_MPU_AttrSet */ + #define RH850_MPU_AttrGet __RH850_MPU_AttrGet /*!< Wrapper macro that calls the @ref __RH850_MPU_AttrGet */ + #define RH850_MPU_RegionClear __RH850_MPU_RegionClear /*!< Wrapper macro that calls the @ref __RH850_MPU_RegionClear */ + #define RH850_MPU_RegionSet __RH850_MPU_RegionSet /*!< Wrapper macro that calls the @ref __RH850_MPU_RegionSet */ + #define RH850_MPU_LowerAddressGet __RH850_MPU_LowerAddressGet /*!< Wrapper macro that calls the @ref __RH850_MPU_LowerAddressGet */ + #define RH850_MPU_UpperAddressGet __RH850_MPU_UpperAddressGet /*!< Wrapper macro that calls the @ref __RH850_MPU_UpperAddressGet */ +/** @} */ /* end of RH850_MPU */ + #endif + +/* ############################################# PMU functions #################################################### */ + #if defined(__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_PMU_API PMU API Functions + * @brief PMU API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_pmu.h" + + #define RH850_PMU_ChannelEnable __RH850_PMU_ChannelEnable /*!< Wrapper macro that calls the @ref __RH850_PMU_ChannelEnable */ + #define RH850_PMU_ChannelDisable __RH850_PMU_ChannelDisable /*!< Wrapper macro that calls the @ref __RH850_PMU_ChannelDisable */ + #define RH850_PMU_StatusGet __RH850_PMU_StatusGet /*!< Wrapper macro that calls the @ref __RH850_PMU_StatusGet */ + #define RH850_PMU_ModeSet __RH850_PMU_ModeSet /*!< Wrapper macro that calls the @ref __RH850_PMU_ModeSet */ + #define RH850_PMU_ControlSet __RH850_PMU_ControlSet /*!< Wrapper macro that calls the @ref __RH850_PMU_ControlSet */ + #define RH850_PMU_OvfGet __RH850_PMU_OverflowGet /*!< Wrapper macro that calls the @ref __RH850_PMU_OverflowGet */ + #define RH850_PMU_OvfClear __RH850_PMU_OverflowClear /*!< Wrapper macro that calls the @ref __RH850_PMU_OverflowClear */ + #define RH850_PMU_CountSet __RH850_PMU_CounterSet /*!< Wrapper macro that calls the @ref __RH850_PMU_CounterSet */ + #define RH850_PMU_CountGet __RH850_PMU_CounterGet /*!< Wrapper macro that calls the @ref __RH850_PMU_CounterGet */ + #define RH850_PMU_SubCountSet __RH850_PMU_SubCountSet /*!< Wrapper macro that calls the @ref __RH850_PMU_SubCountSet */ + #define RH850_PMU_SubCountGet __RH850_PMU_SubCountGet /*!< Wrapper macro that calls the @ref __RH850_PMU_SubCountGet */ +/** @} */ /* end of RH850_PMU */ + #endif + +/* ############################################# TSC functions #################################################### */ + #if defined(__TSC_PRESENT) && (__TSC_PRESENT == 1U) + +/** + * @defgroup RH850_G4MH_TSC_API TSC API Functions + * @brief TSC API Functions + * @ingroup RH850_G4MH_API_Funcs + * @{ + */ + + #include "G4-profile/rh850_g4_tsc.h" + + #define RH850_TSC_Enable __RH850_TSC_Enable /*!< Wrapper macro that calls the @ref __RH850_TSC_Enable */ + #define RH850_TSC_Disable __RH850_TSC_Disable /*!< Wrapper macro that calls the @ref __RH850_TSC_Disable */ + #define RH850_TSC_EnableGet __RH850_TSC_EnableGet /*!< Wrapper macro that calls the @ref __RH850_TSC_EnableGet */ + #define RH850_TSC_ControlRead __RH850_TSC_ControlRead /*!< Wrapper macro that calls the @ref __RH850_TSC_ControlRead */ + #define RH850_TSC_ControlSet __RH850_TSC_ControlSet /*!< Wrapper macro that calls the @ref __RH850_TSC_ControlSet */ + #define RH850_TSC_OverflowGet __RH850_TSC_OverflowGet /*!< Wrapper macro that calls the @ref __RH850_TSC_OverflowGet */ + #define RH850_TSC_OverflowClear __RH850_TSC_OverflowClear /*!< Wrapper macro that calls the @ref __RH850_TSC_OverflowClear */ + #define RH850_TSC_CounterHighGet __RH850_TSC_CounterHighGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterHighGet */ + #define RH850_TSC_CounterHighSet __RH850_TSC_CounterHighSet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterHighSet */ + #define RH850_TSC_CounterLowGet __RH850_TSC_CounterLowGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterLowGet */ + #define RH850_TSC_CounterLowSet __RH850_TSC_CounterLowSet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterLowSet */ + #define RH850_TSC_CounterFullGet __RH850_TSC_CounterFullGet /*!< Wrapper macro that calls the @ref __RH850_TSC_CounterFullGet */ +/** @} */ /* end of RH850_TSC */ + #endif + +/** @} */ /* end of RH850_G4MH_API_Funcs */ + + #ifdef __cplusplus +} + #endif + + #endif /* __CORE_RH850_G4MH_H_DEPENDANT */ + +#endif /* __RH850_GENERIC */ diff --git a/arch/rh850/src/g4x/Core/Include/rh850_ccrh.h b/arch/rh850/src/g4x/Core/Include/rh850_ccrh.h new file mode 100644 index 0000000000000000000000000000000000000000..3d6cc8af1090adc5e63ddf06dfcd6448974f4aa6 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/rh850_ccrh.h @@ -0,0 +1,3856 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_ccrh.h + * @brief RH850 compiler CCRH header file + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_CCRH_H +#define __RH850_CCRH_H + +/* RH850 compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN +#endif +#ifndef RH850_DEPRECATED + #define RH850_DEPRECATED +#endif +#ifndef RH850_UNSUPPORTED + #define RH850_UNSUPPORTED 0 +#endif +#ifndef __USED + #define __USED +#endif +#ifndef __WEAK + #define __WEAK +#endif +#ifndef __PACKED + #define __PACKED +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) +#endif +#ifndef __RESTRICT + #define __RESTRICT +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() +#endif +#ifndef __NO_INIT + #define __NO_INIT +#endif +#ifndef __ALIAS + #define __ALIAS(x) +#endif + +/* Convert token into a string and pass it to _Pragma */ +#ifndef __PRAGMA_HELPER + #define __PRAGMA_HELPER(x) _Pragma(#x) +#endif + +/* Create the pragma inline statement with the function name as argument */ +#ifndef __PRAGMA_PLACE_IN_SECTION + #define __PRAGMA_PLACE_IN_SECTION(sec, name) __PRAGMA_HELPER(section name) +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE(Func_Name) __PRAGMA_HELPER(inline Func_Name) +#endif +#ifndef __FORCEINLINE_ASM + #define __FORCEINLINE_ASM(Func_Name) __PRAGMA_HELPER(inline_asm Func_Name) +#endif + +/* ########################################## Core Instruction Access ############################################# */ + +/** @defgroup RH850_Core_InstructionInterface RH850-Core Instruction Interface + * @brief Access to dedicated instructions + * @{ + */ + +/** @ingroup RH850_Core_InstructionInterface + * @defgroup CCRH_RH850_Core_InstructionInterface CCRH RH850-Core Instruction Interface + * @brief CCRH RH850-Core Instruction Interface + * @{ + */ + +/********************************************* ARM INTRINSIC **********************************************************/ + +/** + * @brief Instruction Synchronization Barrier + * @details Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or memory, + * after the instruction has been completed. + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __ISB() __synci() + +/** + * @brief Data Synchronization Barrier + * @details Acts as a special kind of Data Memory Barrier. + * It completes when all explicit memory accesses before this instruction complete. + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __DSB() __syncp() + +/** + * @brief Data Memory Barrier + * @details Ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __DMB() __syncm() + +/** + * @brief Reverse byte order (32 bit) + * @details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __REV(value) __bsw(value) + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __REV16(value) __bsh(value) + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __REVSH(value) (int16_t) __bsh(value) + +/** + * @brief Rotate Right in unsigned value (32 bit) + * @details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + * @param [in] op1 Value to rotate + * @param [in] op2 Number of Bits to rotate + * @return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR (uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + * @brief Reverse bit order of value + * @details Reverses the bit order of the given value. + * @param [in] value Value to reverse + * @return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT (uint32_t value) +{ + uint32_t result; + + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return result; +} + +/** + * @brief Count leading zeros + * @details Counts the number of leading zeros of a data value. + * @param [in] value Value to count the leading zeros + * @return number of leading zeros in value + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __CLZ(value) ((__sch1l(value)) ? (__sch1l(value) - 1) : 32) + +/** + * @brief Signed Saturate + * @details Saturates a signed value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (1..32) + * @return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT (int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t) ((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + + return val; +} + +/** + * @brief Unsigned Saturate + * @details Saturates an unsigned value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (0..31) + * @return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT (int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t) max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + + return (uint32_t) val; +} + +/** + * @brief Remove the exclusive lock + * @details Removes the exclusive lock which is created by LDREX. + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __CLREX +static void __CLREX (void) +{ + cll; // Clear Load Link +} + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __LDREXB(addr) __ldlbu((unsigned char *) addr) + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __STREXB(value, addr) (!__stcb((unsigned char *) addr, (unsigned char) value)) + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __LDREXH(addr) __ldlhu((unsigned short *) addr) + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __STREXH(value, addr) (!__stch((unsigned short *) addr, (unsigned short) value)) + +/** + * @brief LDR Exclusive (32 bit) + * @details Executes a exclusive LDR instruction for 32 bit values. + * @param [in] addr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __LDREXW(addr) __ldlw((long *) addr) + +/** + * @brief STR Exclusive (32 bit) + * @details Executes a exclusive STR instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#define __STREXW(value, addr) (!__stcw((long *) addr, (long) value)) + +/** + * @brief Rotate Right with Extend (32 bit) + * @details Moves each bit of a bitstring right by one bit. + * The carry input is shifted in at the left end of the bitstring. + * @param [in] value Value to rotate + * @return Rotated value + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __RRX +static uint32_t __RRX (uint32_t value) +{ + ; // rrx32: r10 = (CY << 31) | (r6 >> 1) + ; // - Input : r6 + ; // - Output : r10 = result + ; // Note: PSW is system register #5; CY is bit3 (PSW[3]) + + ; // Get current CY from PSW and expand it to MSB mask (CY<<31) + stsr 5, r11, 0; // r11 <- PSW + shr 3, r11; // r11.bit0 = CY + andi 1, r11, r11; // r11 = CY (0 or 1) + shl 31, r11; // r11 = CY << 31 + + ; // Shift operand and inject CY into MSB + mov r6, r10; + shr 1, r10; // r10 = r6 >> 1 + or r11, r10; // r10 = (CY<<31) | (r6>>1) + + ; // Compute new CY from old LSB of r6: newCY_mask = (r6 & 1) << 3 + mov r6, r12; + andi 1, r12, r12; // r12 = old LSB of r6 (0 or 1) + shl 3, r12; // r12 = newCY_mask (0x0 or 0x8) + + ; // Read PSW, clear CY bit, then set according to newCY_mask + stsr 5, r13, 0; // r13 <- PSW + + ; // Clear-mask (~0x8) + movhi 0xFFFF, r0, r11; // r11 = 0xFFFF0000 + ori 0xFFF7, r11, r11; // r11 = 0xFFFF0000 + 0xFFF7 = 0xFFFFFFF7 + and r11, r13; // r13 &= ~0x8 (clear PSW.CY) + or r12, r13; // r13 |= newCY_mask + + ; // Write PSW back + ldsr r13, 5, 0; // PSW <- r13 +} + +/** + * @brief Load-Acquire (8 bit) + * @details Executes a LDAB instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDAB +static uint8_t __LDAB (volatile uint8_t * ptr) +{ + ld.bu 0[r6], r10 + synce +} + +/** + * @brief Load-Acquire (16 bit) + * @details Executes a LDAH instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDAH +static uint16_t __LDAH (volatile uint16_t * ptr) +{ + ld.hu 0[r6], r10 + synce +} + +/** + * @brief Load-Acquire (32 bit) + * @details Executes a LDA instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDA +static uint32_t __LDA (volatile uint32_t * ptr) +{ + ld.w 0[r6], r10 + synce +} + +/** + * @brief Store-Release (8 bit) + * @details Executes a STLB instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STLB +static void __STLB (uint8_t value, volatile uint8_t * ptr) +{ + synce + st.b r6, 0[r7] +} + +/** + * @brief Store-Release (16 bit) + * @details Executes a STLH instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STLH +static void __STLH (uint16_t value, volatile uint16_t * ptr) +{ + synce + st.h r6, 0[r7] +} + +/** + * @brief Store-Release (32 bit) + * @details Executes a STL instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STL +static void __STL (uint32_t value, volatile uint32_t * ptr) +{ + synce + st.w r6, 0[r7] +} + +/** + * @brief Load-Acquire Exclusive (8 bit) + * @details Executes a LDAB exclusive instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDAEXB +static uint8_t __LDAEXB (volatile uint8_t * ptr) +{ + ldl.bu[r6], r10 + synce +} + +/** + * @brief Load-Acquire Exclusive (16 bit) + * @details Executes a LDAH exclusive instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDAEXH +static uint16_t __LDAEXH (volatile uint16_t * ptr) +{ + ldl.hu[r6], r10 + synce +} + +/** + * @brief Load-Acquire Exclusive (32 bit) + * @details Executes a LDA exclusive instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __LDAEX +static uint32_t __LDAEX (volatile uint32_t * ptr) +{ + ldl.w[r6], r10 + synce +} + +/** + * @brief Store-Release Exclusive (8 bit) + * @details Executes a STLB exclusive instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STLEXB +static uint32_t __STLEXB (uint8_t value, volatile uint8_t * ptr) +{ + synce + stc.b r6, [r7] + mov 1, r10 + xor r6, r10 +} + +/** + * @brief Store-Release Exclusive (16 bit) + * @details Executes a STLH exclusive instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STLEXH +static uint32_t __STLEXH (uint16_t value, volatile uint16_t * ptr) +{ + synce + stc.h r6, [r7] + mov 1, r10 + xor r6, r10 +} + +/** + * @brief Store-Release Exclusive (32 bit) + * @details Executes a STL exclusive instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep CMSIS function name and ensure identical behavior on RH850. + */ +#pragma inline_asm __STLEX +static uint32_t __STLEX (uint32_t value, volatile uint32_t * ptr) +{ + synce + stc.w r6, [r7] + mov 1, r10 + xor r6, r10 +} + +/********************************************* RH850 INTRINSIC ********************************************************/ + +/* Load Instructions */ + +/** + * @brief Load byte + * @details Executes a LD.B instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type int8_t at (*ptr) + */ +#pragma inline_asm __LDB +static int8_t __LDB (volatile int8_t * ptr) +{ + ld.b 0[r6], r10 +} + +/** + * @brief Load byte unsigned + * @details Executes a LD.BU instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + */ +#pragma inline_asm __LDBU +static uint8_t __LDBU (volatile uint8_t * ptr) +{ + ld.bu 0[r6], r10 +} + +/** + * @brief Load halfword + * @details Executes a LD.H instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type int16_t at (*ptr) + */ +#pragma inline_asm __LDH +static int16_t __LDH (volatile int16_t * ptr) +{ + ld.h 0[r6], r10 +} + +/** + * @brief Load halfword unsigned + * @details Executes a LD.HU instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + */ +#pragma inline_asm __LDHU +static uint16_t __LDHU (volatile uint16_t * ptr) +{ + ld.hu 0[r6], r10 +} + +/** + * @brief Load word + * @details Executes a LD.W instruction for 32 bit value. + * @param [in] ptr Pointer to data + * @return value of type int32_t at (*ptr) + */ +#pragma inline_asm __LDW +static int32_t __LDW (volatile int32_t * ptr) +{ + ld.w 0[r6], r10 +} + +/** + * @brief Load double word + * @details Executes a LD.DW instruction for 64 bit value. + * @param [in] ptr Pointer to data + * @return value of type int32_t at (*ptr) + */ +#pragma inline_asm __LDDW +static int64_t __LDDW (volatile int64_t * ptr) +{ + ld.dw 0[r6], r10 +} + +/* Store Instructions */ + +/** + * @brief Store byte + * @details Executes a ST.B instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +#pragma inline_asm __STB +static void __STB (int8_t value, volatile int8_t * ptr) +{ + st.b r6, 0[r7] +} + +/** + * @brief Store halfword + * @details Executes a ST.H instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +#pragma inline_asm __STH +static void __STH (int16_t value, volatile int16_t * ptr) +{ + st.h r6, 0[r7] +} + +/** + * @brief Store word + * @details Executes a ST.W instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +#pragma inline_asm __STW +static void __STW (int32_t value, volatile int32_t * ptr) +{ + st.w r6, 0[r7] +} + +/** + * @brief Store double word + * @details Executes a ST.DW instruction for 64 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +#pragma inline_asm __STDW +static void __STDW (int64_t value, volatile int64_t * ptr) +{ + st.dw r6, 0[r8] +} + +/* Multiply Instructions */ + +/** + * @brief Multiplication of (signed) word data + * @details Assigns higher 32 bits of signed 64-bit multiplication result. + * @param [in] a First operand + * @param [in] b Second operand + * @return High 32 bits of result + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __MUL(a, b) __mul32((long) a, (long) b) + +/** + * @brief Signed 64-bit multiplication high 32 bits + * @details Assigns higher 32 bits of signed 64-bit multiplication result. + * @param [in] a First operand + * @param [in] b Second operand + * @return High 32 bits of result + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __MULU(a, b) __mul32u((long) a, (long) b) + +/** + * @brief Saturated addition + * @details Performs saturated addition of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated addition + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SATADD(a, b) __satadd((long) a, (long) b) + +/** + * @brief Saturated subtraction + * @details Performs saturated subtraction of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated subtraction + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SATSUB(a, b) __satsub((long) a, (long) b) + +/** + * @brief Halfword data byte swap + * @details Swaps bytes within a 16-bit halfword. + * @param [in] value Value to swap + * @return Swapped value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __BSH(value) __bsh((long) value) + +/** + * @brief Word data byte swap + * @details Swaps bytes within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __BSW(value) __bsw((long) value) + +/** + * @brief Signed data conversion from word to byte with saturation + * @details Conversion of signed word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CLIPB(value) __clipb((long) value) + +/** + * @brief Unsigned data conversion from word to byte with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CLIPBU(value) __clipbu((unsigned long) value) + +/** + * @brief Signed data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CLIPH(value) __cliph((long) value) + +/** + * @brief Unsigned data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to halfword data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CLIPHU(value) __cliphu((unsigned long) value) + +/** + * @brief Halfword swap halfword + * @details Swaps halfwords within a 16-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +#pragma inline_asm __HSH +static int16_t __HSH (int16_t value) +{ + hsh r6, r10 +} + +/** + * @brief Word data halfword swap + * @details Swaps halfwords within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __HSW(value) __hsw((long) value) + +/** + * @brief Rotate left + * @param [in] value Value to rotate + * @param [in] bit The specified shift amount + * @return Swapped value + */ +#pragma inline_asm __ROTL +static int32_t __ROTL (int32_t value, uint8_t bit) +{ + rotl r7, r6, r10 +} + +/** + * @brief Bit (0) search from MSB side + * @details Searches for first 0 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SCH0L(value) __sch0l((long) value) + +/** + * @brief Bit (0) search from LSB side + * @details Searches for first 0 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SCH0R(value) __sch0r((long) value) + +/** + * @brief Bit (1) search from MSB side + * @details Searches for first 1 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SCH1L(value) __sch1l((long) value) + +/** + * @brief Bit (1) search from LSB side + * @details Searches for first 1 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SCH1R(value) __sch1r((long) value) + +/** + * @brief Divide word + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return The remainder of quotient = num1/num2 + */ +#pragma inline_asm __DIV +static int32_t __DIV (int32_t num1, int32_t num2) +{ + div r7, r6, r10 +} + +/** + * @brief Divide word unsigned + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return The remainder of quotient = num1/num2 + */ +#pragma inline_asm __DIVU +static uint32_t __DIVU (uint32_t num1, uint32_t num2) +{ + divu r7, r6, r10 +} + +/** + * @brief Bit clear + * @details Clear bit a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CLR1(addr, bit) __clr1((unsigned char *) addr, (long) bit) + +/** + * @brief Bit set + * @details Sets a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __SET1(addr, bit) __set1((unsigned char *) addr, (long) bit) + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __NOT1(addr, bit) __not1((unsigned char *) addr, (long) bit) + +/** + * @brief Compare and Exchange + * @details Atomic compare and exchange operation. + * @param [in] addr Address + * @param [in] b Compare value + * @param [in] c Exchange value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __CAXI(addr, b, c) __caxi((long *) addr, (long) b, (long) c) + +/** + * @brief Clear Load Link + * @details Clear Load Link which is created by LDL. + */ +#pragma inline_asm __CLL +static void __CLL (void) +{ + cll; // Clear Load Link +} + +/** + * @brief Disable Interrupts + * @details Executes the DI instruction to disable maskable interrupts. + */ +#define __DI() __DI() + +/** + * @brief Enable Interrupts + * @details Executes the EI instruction to enable maskable interrupts. + */ +#define __EI() __EI() + +/** + * @brief Return from EI-level trap or interrupt + */ +#pragma inline_asm __EIRET +static void __EIRET (void) +{ + eiret +} + +/** + * @brief Return from FE-level trap or interrupt + */ +#pragma inline_asm __FERET +static void __FERET (void) +{ + feret +} + +/** + * @brief FE-level trap + */ +#define __FETRAP(vector) __ASM volatile ("fetrap " #vector) + +/** + * @brief Load to system register (with selector) + * @details Loads value into system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @param [in] value Value to load + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __LDSR(regID, selID, value) __ldsr_rh((long) regID, (long) selID, (unsigned long) value) + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*ptr) + */ +#define __LDLBU(addr) __ldlbu((unsigned char *) addr) + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*ptr) + */ +#define __LDLHU(addr) __ldlhu((unsigned short *) addr) + +/** + * @brief Atomic load to system register + * @details Loads a value into a system register atomically. + * @param [in] value Value to load + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __LDLW(value) __ldlw((long *) value) + +/** + * @brief No Operation + * @details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + +/** + * @brief Restore contexts from register bank + */ +#pragma inline_asm __RESBANK +static void __RESBANK (void) +{ + resbank +} + +/** + * @brief Snooze + */ +#pragma inline_asm __SNOOZE +static void __SNOOZE (void) +{ + snooze +} + +/** + * @brief Store contents of system register (with selector) + * @details Stores contents of system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @return Register value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __STSR(regID, selID) __stsr_rh((long) regID, (long) selID) + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +#define __STCB(addr, value) __stcb((unsigned char *) addr, (unsigned char) value) + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +#define __STCH(addr, value) __stch((unsigned short *) addr, (unsigned short) value) + +/** + * @brief Store word + * @details Stores a word to memory. + * @param [in] addr Address + * @param [in] value Value + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __STCW(addr, value) __stcw((long *) addr, (long) value) + +/** + * @brief Exception synchronization + * @details Synchronizes exception handling. + */ +#define __SYNCE() __synce() + +/** + * @brief Instruction pipeline synchronization + * @details Synchronizes instruction pipeline. + */ +#define __SYNCI() __synci() + +/** + * @brief Memory synchronization + * @details Synchronizes memory operations. + */ +#define __SYNCM() __syncm() + +/** + * @brief Pipeline synchronization + * @details Synchronizes pipeline operations. + */ +#define __SYNCP() __syncp() + +/** + * @brief Trap + */ +#define __TRAP(vector) __ASM volatile ("trap " #vector) + +/** + * @brief Halt CPU + * @details HALT instruction stops CPU execution until an interrupt or reset occurs. + */ +#define __HALT() __halt() + +/** + * @brief Debug checkpoint + * @details Inserts a debug checkpoint instruction. + */ +#define __DBCP() __dbcp() + +/** + * @brief Debug push + * @details Pushes debug registers. + * @param [in] regID1 First register ID + * @param [in] regID2 Second register ID + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +#define __DBPUSH(regID1, regID2) __dbpush((long) regID1, (long) regID2) + +/** + * @brief Debug tag + * @details Inserts a debug tag instruction. + * @param [in] a Tag value + */ +#define __DBTAG(a) __dbtag(a) + +/** @}*/ /* end of group CCRH_RH850_Core_InstructionInterface */ +/** @}*/ /* end of group RH850_Core_InstructionInterface */ + +/* ########################################## Core Function Access ################################################ */ + +/** @defgroup RH850_Core_FunctionInterface RH850-Core Register Access Functions + * @brief Access to the dedicated core register access function instructions + * @{ + */ + +/** @ingroup RH850_Core_FunctionInterface + * @defgroup CCRH_RH850_Core_RegAccFunctions CCRH RH850-Core Register Access Functions + * @brief CC-RH RH850-Core Register Access Functions + * @{ + */ + +/** + * @brief Enable IRQ Interrupts + * @details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __enable_irq() __EI() + +/** + * @brief Disable IRQ Interrupts + * @details Disables IRQ interrupts by setting special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __disable_irq() __DI() + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set EIPC (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_EIPC +static void __set_EIPC (uint32_t value) +{ + ldsr r6, 0, 0 +} + +/** + * @brief Get EIPC (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPC system register. + * @return uint32_t register value. + */ +#pragma inline_asm __get_EIPC +static uint32_t __get_EIPC (void) +{ + stsr 0, r10, 0 +} + +/** + * @brief Set EIPSW (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPSW system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_EIPSW +static void __set_EIPSW (uint32_t value) +{ + ldsr r6, 1, 0 +} + +/** + * @brief Get EIPSW (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPSW system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_EIPSW +static uint32_t __get_EIPSW (void) +{ + stsr 1, r10, 0 +} + +/** + * @brief Set FEPC (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FEPC +static void __set_FEPC (uint32_t value) +{ + ldsr r6, 2, 0 +} + +/** + * @brief Get FEPC (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FEPC +static uint32_t __get_FEPC (void) +{ + stsr 2, r10, 0 +} + +/** + * @brief Set FEPSW (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPSW system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FEPSW +static void __set_FEPSW (uint32_t value) +{ + ldsr r6, 3, 0 +} + +/** + * @brief Get FEPSW (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPSW system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FEPSW +static uint32_t __get_FEPSW (void) +{ + stsr 3, r10, 0 +} + +/** + * @brief Set PSW (Program status word). + * @details Writes a value to the PSW system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PSW +static void __set_PSW (uint32_t value) +{ + ldsr r6, 5, 0 +} + +/** + * @brief Get PSW (Program status word). + * @details Reads the current value of the PSW system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PSW +static uint32_t __get_PSW (void) +{ + stsr 5, r10, 0 +} + +/** + * @brief Set EIIC (EI level exception cause). + * @details Writes a value to the EIIC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_EIIC +static void __set_EIIC (uint32_t value) +{ + ldsr r6, 13, 0 +} + +/** + * @brief Get EIIC (EI level exception cause). + * @details Reads the current value of the EIIC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_EIIC +static uint32_t __get_EIIC (void) +{ + stsr 13, r10, 0 +} + +/** + * @brief Set FEIC (FE level exception cause). + * @details Writes a value to the FEIC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FEIC +static void __set_FEIC (uint32_t value) +{ + ldsr r6, 14, 0 +} + +/** + * @brief Get FEIC (FE level exception cause). + * @details Reads the current value of the FEIC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FEIC +static uint32_t __get_FEIC (void) +{ + stsr 14, r10, 0 +} + +/** + * @brief Set CTPC (CALLT execution status save register). + * @details Writes a value to the CTPC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_CTPC +static void __set_CTPC (uint32_t value) +{ + ldsr r6, 16, 0 +} + +/** + * @brief Get CTPC (CALLT execution status save register). + * @details Reads the current value of the CTPC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_CTPC +static uint32_t __get_CTPC (void) +{ + stsr 16, r10, 0 +} + +/** + * @brief Set CTPSW (CALLT execution status save register). + * @details Writes a value to the CTPSW system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_CTPSW +static void __set_CTPSW (uint32_t value) +{ + ldsr r6, 17, 0 +} + +/** + * @brief Get CTPSW (CALLT execution status save register). + * @details Reads the current value of the CTPSW system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_CTPSW +static uint32_t __get_CTPSW (void) +{ + stsr 17, r10, 0 +} + +/* CALLT base pointer */ + +/** + * @brief Set CTBP (CALLT base pointer). + * @details Writes a value to the CTBP system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_CTBP +static void __set_CTBP (uint32_t value) +{ + ldsr r6, 20, 0 +} + +/** + * @brief Get CTBP (CALLT base pointer). + * @details Reads the current value of the CTBP system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_CTBP +static uint32_t __get_CTBP (void) +{ + stsr 20, r10, 0 +} + +/** + * @brief Set SNZCFG (SNOOZE control register). + * @details Writes a value to the SNZCFG system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_SNZCFG +static void __set_SNZCFG (uint32_t value) +{ + ldsr r6, 21, 0 +} + +/** + * @brief Get SNZCFG (SNOOZE control register). + * @details Reads the current value of the SNZCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SNZCFG +static uint32_t __get_SNZCFG (void) +{ + stsr 21, r10, 0 +} + +/** + * @brief Set EIWR (EI level exception working register). + * @details Writes a value to the EIWR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_EIWR +static void __set_EIWR (uint32_t value) +{ + ldsr r6, 28, 0 +} + +/** + * @brief Get EIWR (EI level exception working register). + * @details Reads the current value of the EIWR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_EIWR +static uint32_t __get_EIWR (void) +{ + stsr 28, r10, 0 +} + +/** + * @brief Set FEWR (FE level exception working register). + * @details Writes a value to the FEWR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FEWR +static void __set_FEWR (uint32_t value) +{ + ldsr r6, 29, 0 +} + +/** + * @brief Get FEWR (FE level exception working register). + * @details Reads the current value of the FEWR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FEWR +static uint32_t __get_FEWR (void) +{ + stsr 29, r10, 0 +} + +/** + * @brief Get SPID (System protection identifier). + * @details Reads the current value of the SPID system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SPID +static uint32_t __get_SPID (void) +{ + stsr 0, r10, 1 +} + +/** + * @brief Set SPID (System protection identifier). + * @details Writes a value to the SPID system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_SPID +static void __set_SPID (uint32_t value) +{ + ldsr r6, 0, 1 +} + +/** + * @brief Get SPIDLIST (List of system protection identifiers that can be specified in SPID). + * @details Reads the current value of the SPIDLIST system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SPIDLIST +static uint32_t __get_SPIDLIST (void) +{ + stsr 1, r10, 1 +} + +/** + * @brief Get RBASE (Reset vector base address). + * @details Reads the current value of the RBASE system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_RBASE +static uint32_t __get_RBASE (void) +{ + stsr 2, r10, 1 +} + +/** + * @brief Set EBASE (Exception handler vector address). + * @details Writes a value to the EBASE system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_EBASE +static void __set_EBASE (uint32_t value) +{ + ldsr r6, 3, 1 +} + +/** + * @brief Get EBASE (Exception handler vector address). + * @details Reads the current value of the EBASE system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_EBASE +static uint32_t __get_EBASE (void) +{ + stsr 3, r10, 1 +} + +/** + * @brief Set INTBP (Base address of the interrupt handler “address” table). + * @details Writes a value to the INTBP system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_INTBP +static void __set_INTBP (uint32_t value) +{ + ldsr r6, 4, 1 +} + +/** + * @brief Get INTBP (Base address of the interrupt handler “address” table). + * @details Reads the current value of the INTBP system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_INTBP +static uint32_t __get_INTBP (void) +{ + stsr 4, r10, 1 +} + +/** + * @brief Set MCTL (CPU control). + * @details Writes a value to the MCTL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCTL +static void __set_MCTL (uint32_t value) +{ + ldsr r6, 5, 1 +} + +/** + * @brief Get MCTL (CPU control). + * @details Reads the current value of the MCTL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCTL +static uint32_t __get_MCTL (void) +{ + stsr 5, r10, 1 +} + +/** + * @brief Get PID (Processor ID). + * @details Reads the current value of the PID system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PID +static uint32_t __get_PID (void) +{ + stsr 6, r10, 1 +} + +/** + * @brief Set SVLOCK (Supervisor lock). + * @details Writes a value to the SVLOCK system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_SVLOCK +static void __set_SVLOCK (uint32_t value) +{ + ldsr r6, 8, 1 +} + +/** + * @brief Get SVLOCK (Supervisor lock). + * @details Reads the current value of the SVLOCK system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SVLOCK +static uint32_t __get_SVLOCK (void) +{ + stsr 8, r10, 1 +} + +/** + * @brief Set SCCFG (SYSCALL operation setting). + * @details Writes a value to the SCCFG system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_SCCFG +static void __set_SCCFG (uint32_t value) +{ + ldsr r6, 11, 1 +} + +/** + * @brief Get SCCFG (SYSCALL operation setting). + * @details Reads the current value of the SCCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SCCFG +static uint32_t __get_SCCFG (void) +{ + stsr 11, r10, 1 +} + +/** + * @brief Set SCBP (SYSCALL base pointer). + * @details Writes a value to the SCBP system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_SCBP +static void __set_SCBP (uint32_t value) +{ + ldsr r6, 12, 1 +} + +/** + * @brief Get SCBP (SYSCALL base pointer). + * @details Reads the current value of the SCBP system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_SCBP +static uint32_t __get_SCBP (void) +{ + stsr 12, r10, 1 +} + +/** + * @brief Get PEID (Processor element identifier). + * @details Reads the current value of the PEID system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PEID +static uint32_t __get_PEID (void) +{ + stsr 0, r10, 2 +} + +/** + * @brief Get BMID (Bus master identifier). + * @details Reads the current value of the BMID system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_BMID +static uint32_t __get_BMID (void) +{ + stsr 1, r10, 2 +} + +/** + * @brief Set MEA (Memory error address). + * @details Writes a value to the MEA system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MEA +static void __set_MEA (uint32_t value) +{ + ldsr r6, 6, 2 +} + +/** + * @brief Get MEA (Memory error address). + * @details Reads the current value of the MEA system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MEA +static uint32_t __get_MEA (void) +{ + stsr 6, r10, 2 +} + +/** + * @brief Set MEI (Memory error information). + * @details Writes a value to the MEI system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MEI +static void __set_MEI (uint32_t value) +{ + ldsr r6, 8, 2 +} + +/** + * @brief Get MEI (Memory error information). + * @details Reads the current value of the MEI system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MEI +static uint32_t __get_MEI (void) +{ + stsr 8, r10, 2 +} + +/** + * @brief Set RBCR0 (Register bank control 0). + * @details Writes a value to the RBCR0 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_RBCR0 +static void __set_RBCR0 (uint32_t value) +{ + ldsr r6, 15, 2 +} + +/** + * @brief Get RBCR0 (Register bank control 0). + * @details Reads the current value of the RBCR0 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_RBCR0 +static uint32_t __get_RBCR0 (void) +{ + stsr 15, r10, 2 +} + +/** + * @brief Set RBCR1 (Register bank control 1). + * @details Writes a value to the RBCR1 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_RBCR1 +static void __set_RBCR1 (uint32_t value) +{ + ldsr r6, 16, 2 +} + +/** + * @brief Get RBCR1 (Register bank control 1). + * @details Reads the current value of the RBCR1 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_RBCR1 +static uint32_t __get_RBCR1 (void) +{ + stsr 16, r10, 2 +} + +/** + * @brief Set RBNR (Register bank number). + * @details Writes a value to the RBNR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_RBNR +static void __set_RBNR (uint32_t value) +{ + ldsr r6, 17, 2 +} + +/** + * @brief Get RBNR (Register bank number). + * @details Reads the current value of the RBNR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_RBNR +static uint32_t __get_RBNR (void) +{ + stsr 17, r10, 2 +} + +/** + * @brief Set RBIP (Register bank initial pointer). + * @details Writes a value to the RBIP system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_RBIP +static void __set_RBIP (uint32_t value) +{ + ldsr r6, 18, 2 +} + +/** + * @brief Get RBIP (Register bank initial pointer). + * @details Reads the current value of the RBIP system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_RBIP +static uint32_t __get_RBIP (void) +{ + stsr 18, r10, 2 +} + +/*********************************************************************************************************************** + * Interrupt Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ISPR (Priority of interrupt being serviced). + * @details Writes a value to the ISPR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ISPR +static void __set_ISPR (uint32_t value) +{ + ldsr r6, 10, 2 +} + +/** + * @brief Get ISPR (Priority of interrupt being serviced). + * @details Reads the current value of the ISPR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ISPR +static uint32_t __get_ISPR (void) +{ + stsr 10, r10, 2 +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IMSR (Interrupt mask status). + * @details Reads the current value of the IMSR system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_IMSR +static uint32_t __get_IMSR (void) +{ + stsr 11, r10, 2 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Get ICSR (Interrupt control status). + * @details Reads the current value of the ICSR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICSR +static uint32_t __get_ICSR (void) +{ + stsr 12, r10, 2 +} + +/** + * @brief Set INTCFG (Interrupt function setting). + * @details Writes a value to the INTCFG system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_INTCFG +static void __set_INTCFG (uint32_t value) +{ + ldsr r6, 13, 2 +} + +/** + * @brief Get INTCFG (Interrupt function setting). + * @details Reads the current value of the INTCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_INTCFG +static uint32_t __get_INTCFG (void) +{ + stsr 13, r10, 2 +} + +/** + * @brief Set PLMR (Interrupt priority masking). + * @details Writes a value to the PLMR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PLMR +static void __set_PLMR (uint32_t value) +{ + ldsr r6, 14, 2 +} + +/** + * @brief Get PLMR (Interrupt priority masking). + * @details Reads the current value of the PLMR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PLMR +static uint32_t __get_PLMR (void) +{ + stsr 14, r10, 2 +} + +/*********************************************************************************************************************** + * FPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FPSR (Floating-point operation configuration/status). + * @details Writes a value to the FPSR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FPSR +static void __set_FPSR (uint32_t value) +{ + ldsr r6, 6, 0 +} + +/** + * @brief Get FPSR (Floating-point operation configuration/status). + * @details Reads the current value of the FPSR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FPSR +static uint32_t __get_FPSR (void) +{ + stsr 6, r10, 0 +} + +/** + * @brief Set FPEPC (Floating-point operation exception program counter). + * @details Writes a value to the FPEPC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FPEPC +static void __set_FPEPC (uint32_t value) +{ + ldsr r6, 7, 0 +} + +/** + * @brief Get FPEPC (Floating-point operation exception program counter). + * @details Reads the current value of the FPEPC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FPEPC +static uint32_t __get_FPEPC (void) +{ + stsr 7, r10, 0 +} + +/** + * @brief Set FPST (Floating point operation status). + * @details Writes a value to the FPST system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FPST +static void __set_FPST (uint32_t value) +{ + ldsr r6, 8, 0 +} + +/** + * @brief Get FPST (Floating point operation status). + * @details Reads the current value of the FPST system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FPST +static uint32_t __get_FPST (void) +{ + stsr 8, r10, 0 +} + +/** + * @brief Set FPCC (Floating-point operation comparison result). + * @details Writes a value to the FPCC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FPCC +static void __set_FPCC (uint32_t value) +{ + ldsr r6, 9, 0 +} + +/** + * @brief Get FPCC (Floating-point operation comparison result). + * @details Reads the current value of the FPCC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FPCC +static uint32_t __get_FPCC (void) +{ + stsr 9, r10, 0 +} + +/** + * @brief Set FPCFG (Floating-point operation configuration). + * @details Writes a value to the FPCFG system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FPCFG +static void __set_FPCFG (uint32_t value) +{ + ldsr r6, 10, 0 +} + +/** + * @brief Get FPCFG (Floating-point operation configuration). + * @details Reads the current value of the FPCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FPCFG +static uint32_t __get_FPCFG (void) +{ + stsr 10, r10, 0 +} + +#if defined(__RH850_G4KH) && (__RH850_G4KH == 1) + +/** + * @brief Set FPEC (Floating-point exception control). + * @details Writes a value to the FPEC system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_FPEC +static void __set_FPEC (uint32_t value) +{ + ldsr r6, 11, 0 +} + +/** + * @brief Get FPEC (Floating-point exception control). + * @details Reads the current value of the FPEC system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_FPEC +static uint32_t __get_FPEC (void) +{ + stsr 11, r10, 0 +} + +#endif /* #if defined(__RH850_G4KH) && (__RH850_G4KH == 1) */ + +/*********************************************************************************************************************** + * FXU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FXSR (Extended floating-point operation configuration/status). + * @details Writes a value to the FXSR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FXSR +static void __set_FXSR (uint32_t value) +{ + ldsr r6, 6, 10 +} + +/** + * @brief Get FXSR (Extended floating-point operation configuration/status). + * @details Reads the current value of the FXSR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXSR +static uint32_t __get_FXSR (void) +{ + stsr 6, r10, 10 +} + +/** + * @brief Set FXST (Extended floating-point operation status). + * @details Writes a value to the FXST system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FXST +static void __set_FXST (uint32_t value) +{ + ldsr r6, 8, 10 +} + +/** + * @brief Get FXST (Extended floating-point operation status). + * @details Reads the current value of the FXST system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXST +static uint32_t __get_FXST (void) +{ + stsr 8, r10, 10 +} + +/** + * @brief Get FXINFO (FXU configuration information). + * @details Reads the current value of the FXINFO system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXINFO +static uint32_t __get_FXINFO (void) +{ + stsr 9, r10, 10 +} + +/* Extended floating-point operation configuration */ + +/** + * @brief Set FXCFG (Extended floating-point operation configuration). + * @details Writes a value to the FXCFG system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FXCFG +static void __set_FXCFG (uint32_t value) +{ + ldsr r6, 10, 10 +} + +/** + * @brief Get FXCFG (Extended floating-point operation configuration). + * @details Reads the current value of the FXCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXCFG +static uint32_t __get_FXCFG (void) +{ + stsr 10, r10, 10 +} + +/* XC (cause) bits for each operation way */ + +/** + * @brief Set FXXC (XC (cause) bits for each operation way). + * @details Writes a value to the FXXC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FXXC +static void __set_FXXC (uint32_t value) +{ + ldsr r6, 12, 10 +} + +/** + * @brief Get FXXC (XC (cause) bits for each operation way). + * @details Reads the current value of the FXXC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXXC +static uint32_t __get_FXXC (void) +{ + stsr 12, r10, 10 +} + +/** + * @brief Set FXXP (XP (preservation) bits for each operation way). + * @details Writes a value to the FXXP system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_FXXP +static void __set_FXXP (uint32_t value) +{ + ldsr r6, 13, 10 +} + +/** + * @brief Get FXXP (XP (preservation) bits for each operation way). + * @details Reads the current value of the FXXP system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_FXXP +static uint32_t __get_FXXP (void) +{ + stsr 13, r10, 10 +} + +/*********************************************************************************************************************** + * MPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set MPM (Memory protection operation mode setting). + * @details Writes a value to the MPM system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPM +static void __set_MPM (uint32_t value) +{ + ldsr r6, 0, 5 +} + +/** + * @brief Get MPM (Memory protection operation mode setting). + * @details Reads the current value of the MPM system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPM +static uint32_t __get_MPM (void) +{ + stsr 0, r10, 5 +} + +/** + * @brief Get MPCFG (MPU configuration). + * @details Reads the current value of the MPCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPCFG +static uint32_t __get_MPCFG (void) +{ + stsr 2, r10, 5 +} + +/** + * @brief Set MCA (Memory protection setting check address). + * @details Writes a value to the MCA system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCA +static void __set_MCA (uint32_t value) +{ + ldsr r6, 8, 5 +} + +/** + * @brief Get MCA (Memory protection setting check address). + * @details Reads the current value of the MCA system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCA +static uint32_t __get_MCA (void) +{ + stsr 8, r10, 5 +} + +/** + * @brief Set MCS (Memory protection setting check size). + * @details Writes a value to the MCS system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCS +static void __set_MCS (uint32_t value) +{ + ldsr r6, 9, 5 +} + +/** + * @brief Get MCS (Memory protection setting check size). + * @details Reads the current value of the MCS system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCS +static uint32_t __get_MCS (void) +{ + stsr 9, r10, 5 +} + +/** + * @brief Set MCC (Memory protection setting check command). + * @details Writes a value to the MCC system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCC +static void __set_MCC (uint32_t value) +{ + ldsr r6, 10, 5 +} + +/** + * @brief Get MCC (Memory protection setting check command). + * @details Reads the current value of the MCC system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCC +static uint32_t __get_MCC (void) +{ + stsr 10, r10, 5 +} + +/** + * @brief Set MCR (Memory protection setting check result). + * @details Writes a value to the MCR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCR +static void __set_MCR (uint32_t value) +{ + ldsr r6, 11, 5 +} + +/** + * @brief Get MCR (Memory protection setting check result). + * @details Reads the current value of the MCR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCR +static uint32_t __get_MCR (void) +{ + stsr 11, r10, 5 +} + +/** + * @brief Set MCI (Memory protection setting check SPID). + * @details Writes a value to the MCI system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MCI +static void __set_MCI (uint32_t value) +{ + ldsr r6, 12, 5 +} + +/** + * @brief Get MCI (Memory protection setting check SPID). + * @details Reads the current value of the MCI system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MCI +static uint32_t __get_MCI (void) +{ + stsr 12, r10, 5 +} + +/** + * @brief Set MPIDX (Index of memory protection setting registers to be accessed). + * @details Writes a value to the MPIDX system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPIDX +static void __set_MPIDX (uint32_t value) +{ + ldsr r6, 16, 5 +} + +/** + * @brief Get MPIDX (Index of memory protection setting registers to be accessed). + * @details Reads the current value of the MPIDX system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPIDX +static uint32_t __get_MPIDX (void) +{ + stsr 16, r10, 5 +} + +/** + * @brief Set MPBK (MPU Bank Setting). + * @details Writes a value to the MPBK system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPBK +static void __set_MPBK (uint32_t value) +{ + ldsr r6, 17, 5 +} + +/** + * @brief Get MPBK (MPU Bank Setting). + * @details Reads the current value of the MPBK system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPBK +static uint32_t __get_MPBK (void) +{ + stsr 17, r10, 5 +} + +/** + * @brief Set MPLA (Protection area minimum address). + * @details Writes a value to the MPLA system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPLA +static void __set_MPLA (uint32_t value) +{ + ldsr r6, 20, 5 +} + +/** + * @brief Get MPLA (Protection area minimum address). + * @details Reads the current value of the MPLA system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPLA +static uint32_t __get_MPLA (void) +{ + stsr 20, r10, 5 +} + +/** + * @brief Set MPUA (Protection area maximum address). + * @details Writes a value to the MPUA system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPUA +static void __set_MPUA (uint32_t value) +{ + ldsr r6, 21, 5 +} + +/** + * @brief Get MPUA (Protection area maximum address). + * @details Reads the current value of the MPUA system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPUA +static uint32_t __get_MPUA (void) +{ + stsr 21, r10, 5 +} + +/** + * @brief Set MPAT (Protection area attribute). + * @details Writes a value to the MPAT system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPAT +static void __set_MPAT (uint32_t value) +{ + ldsr r6, 22, 5 +} + +/** + * @brief Get MPAT (Protection area attribute). + * @details Reads the current value of the MPAT system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPAT +static uint32_t __get_MPAT (void) +{ + stsr 22, r10, 5 +} + +/** + * @brief Set MPID0 (SPID which can access protection area). + * @details Writes a value to the MPID0 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID0 +static void __set_MPID0 (uint32_t value) +{ + ldsr r6, 24, 5 +} + +/** + * @brief Get MPID0 (SPID which can access protection area). + * @details Reads the current value of the MPID0 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID0 +static uint32_t __get_MPID0 (void) +{ + stsr 24, r10, 5 +} + +/** + * @brief Set MPID1 (SPID which can access protection area). + * @details Writes a value to the MPID1 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID1 +static void __set_MPID1 (uint32_t value) +{ + ldsr r6, 25, 5 +} + +/** + * @brief Get MPID1 (SPID which can access protection area). + * @details Reads the current value of the MPID1 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID1 +static uint32_t __get_MPID1 (void) +{ + stsr 25, r10, 5 +} + +/** + * @brief Set MPID2 (SPID which can access protection area). + * @details Writes a value to the MPID2 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID2 +static void __set_MPID2 (uint32_t value) +{ + ldsr r6, 26, 5 +} + +/** + * @brief Get MPID2 (SPID which can access protection area). + * @details Reads the current value of the MPID2 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID2 +static uint32_t __get_MPID2 (void) +{ + stsr 26, r10, 5 +} + +/** + * @brief Set MPID3 (SPID which can access protection area). + * @details Writes a value to the MPID3 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID3 +static void __set_MPID3 (uint32_t value) +{ + ldsr r6, 27, 5 +} + +/** + * @brief Get MPID3 (SPID which can access protection area). + * @details Reads the current value of the MPID3 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID3 +static uint32_t __get_MPID3 (void) +{ + stsr 27, r10, 5 +} + +/** + * @brief Set MPID4 (SPID which can access protection area). + * @details Writes a value to the MPID4 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID4 +static void __set_MPID4 (uint32_t value) +{ + ldsr r6, 28, 5 +} + +/** + * @brief Get MPID4 (SPID which can access protection area). + * @details Reads the current value of the MPID4 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID4 +static uint32_t __get_MPID4 (void) +{ + stsr 28, r10, 5 +} + +/** + * @brief Set MPID5 (SPID which can access protection area). + * @details Writes a value to the MPID5 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID5 +static void __set_MPID5 (uint32_t value) +{ + ldsr r6, 29, 5 +} + +/** + * @brief Get MPID5 (SPID which can access protection area). + * @details Reads the current value of the MPID5 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID5 +static uint32_t __get_MPID5 (void) +{ + stsr 29, r10, 5 +} + +/** + * @brief Set MPID6 (SPID which can access protection area). + * @details Writes a value to the MPID6 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID6 +static void __set_MPID6 (uint32_t value) +{ + ldsr r6, 30, 5 +} + +/** + * @brief Get MPID6 (SPID which can access protection area). + * @details Reads the current value of the MPID6 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID6 +static uint32_t __get_MPID6 (void) +{ + stsr 30, r10, 5 +} + +/** + * @brief Set MPID7 (SPID which can access protection area). + * @details Writes a value to the MPID7 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_MPID7 +static void __set_MPID7 (uint32_t value) +{ + ldsr r6, 31, 5 +} + +/** + * @brief Get MPID7 (SPID which can access protection area). + * @details Reads the current value of the MPID7 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_MPID7 +static uint32_t __get_MPID7 (void) +{ + stsr 31, r10, 5 +} + +/*********************************************************************************************************************** + * Cache Operation Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ICTAGL (Instruction cache tag Lo access). + * @details Writes a value to the ICTAGL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICTAGL +static void __set_ICTAGL (uint32_t value) +{ + ldsr r6, 16, 4 +} + +/** + * @brief Get ICTAGL (Instruction cache tag Lo access). + * @details Reads the current value of the ICTAGL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICTAGL +static uint32_t __get_ICTAGL (void) +{ + stsr 16, r10, 4 +} + +/** + * @brief Set ICTAGH (Instruction cache tag Hi access). + * @details Writes a value to the ICTAGH system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICTAGH +static void __set_ICTAGH (uint32_t value) +{ + ldsr r6, 17, 4 +} + +/** + * @brief Get ICTAGH (Instruction cache tag Hi access). + * @details Reads the current value of the ICTAGH system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICTAGH +static uint32_t __get_ICTAGH (void) +{ + stsr 17, r10, 4 +} + +/** + * @brief Set ICDATL (Instruction cache data Lo access). + * @details Writes a value to the ICDATL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICDATL +static void __set_ICDATL (uint32_t value) +{ + ldsr r6, 18, 4 +} + +/** + * @brief Get ICDATL (Instruction cache data Lo access). + * @details Reads the current value of the ICDATL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICDATL +static uint32_t __get_ICDATL (void) +{ + stsr 18, r10, 4 +} + +/** + * @brief Set ICDATH (Instruction cache data Hi access). + * @details Writes a value to the ICDATH system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICDATH +static void __set_ICDATH (uint32_t value) +{ + ldsr r6, 19, 4 +} + +/** + * @brief Get ICDATH (Instruction cache data Hi access). + * @details Reads the current value of the ICDATH system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICDATH +static uint32_t __get_ICDATH (void) +{ + stsr 19, r10, 4 +} + +/** + * @brief Set ICCTRL (Instruction cache control). + * @details Writes a value to the ICCTRL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICCTRL +static void __set_ICCTRL (uint32_t value) +{ + ldsr r6, 24, 4 +} + +/** + * @brief Get ICCTRL (Instruction cache control). + * @details Reads the current value of the ICCTRL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICCTRL +static uint32_t __get_ICCTRL (void) +{ + stsr 24, r10, 4 +} + +/** + * @brief Get ICCFG (Instruction cache configuration). + * @details Reads the current value of the ICCFG system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICCFG +static uint32_t __get_ICCFG (void) +{ + stsr 26, r10, 4 +} + +/** + * @brief Set ICERR (Instruction cache error). + * @details Writes a value to the ICERR system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_ICERR +static void __set_ICERR (uint32_t value) +{ + ldsr r6, 28, 4 +} + +/** + * @brief Get ICERR (Instruction cache error). + * @details Reads the current value of the ICERR system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_ICERR +static uint32_t __get_ICERR (void) +{ + stsr 28, r10, 4 +} + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set TSCOUNTL (Timestamp count L register). + * @details Writes a value to the TSCOUNTL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_TSCOUNTL +static void __set_TSCOUNTL (uint32_t value) +{ + ldsr r6, 0, 11 +} + +/** + * @brief Get TSCOUNTL (Timestamp count L register). + * @details Reads the current value of the TSCOUNTL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_TSCOUNTL +static uint32_t __get_TSCOUNTL (void) +{ + stsr 0, r10, 11 +} + +/** + * @brief Set TSCOUNTH (Timestamp count H register). + * @details Writes a value to the TSCOUNTH system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_TSCOUNTH +static void __set_TSCOUNTH (uint32_t value) +{ + ldsr r6, 1, 11 +} + +/** + * @brief Get TSCOUNTH (Timestamp count H register). + * @details Reads the current value of the TSCOUNTH system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_TSCOUNTH +static uint32_t __get_TSCOUNTH (void) +{ + stsr 1, r10, 11 +} + +/** + * @brief Set TSCTRL (Timestamp count control register). + * @details Writes a value to the TSCTRL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_TSCTRL +static void __set_TSCTRL (uint32_t value) +{ + ldsr r6, 2, 11 +} + +/** + * @brief Get TSCTRL (Timestamp count control register). + * @details Reads the current value of the TSCTRL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_TSCTRL +static uint32_t __get_TSCTRL (void) +{ + stsr 2, r10, 11 +} + +/** + * @brief Set PMUMCTRL (Performance counter User mode control register). + * @details Writes a value to the PMUMCTRL system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMUMCTRL +static void __set_PMUMCTRL (uint32_t value) +{ + ldsr r6, 8, 11 +} + +/** + * @brief Get PMUMCTRL (Performance counter User mode control register). + * @details Reads the current value of the PMUMCTRL system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMUMCTRL +static uint32_t __get_PMUMCTRL (void) +{ + stsr 8, r10, 11 +} + +/** + * @brief Set PMCTRL0 (Performance count control 0 register). + * @details Writes a value to the PMCTRL0 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCTRL0 +static void __set_PMCTRL0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 0, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 17, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL0 (Performance count control 0 register). + * @details Reads the current value of the PMCTRL0 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCTRL0 +static uint32_t __get_PMCTRL0 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 0, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 17, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Set PMCTRL1 (Performance count control 1 register). + * @details Writes a value to the PMCTRL1 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCTRL1 +static void __set_PMCTRL1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 1, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 19, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL1 (Performance count control 1 register). + * @details Reads the current value of the PMCTRL1 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCTRL1 +static uint32_t __get_PMCTRL1 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 1, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 19, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Set PMCTRL2 (Performance count control 2 register). + * @details Writes a value to the PMCTRL2 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCTRL2 +static void __set_PMCTRL2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 2, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 21, 11 +#endif +} + +/** + * @brief Get PMCTRL2 (Performance count control 2 register). + * @details Reads the current value of the PMCTRL2 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCTRL2 +static uint32_t __get_PMCTRL2 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 2, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 21, r10, 11 +#endif +} + +/** + * @brief Set PMCTRL3 (Performance count control 3 register). + * @details Writes a value to the PMCTRL3 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCTRL3 +static void __set_PMCTRL3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 3, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 23, 11 +#endif +} + +/** + * @brief Get PMCTRL3 (Performance count control 3 register). + * @details Reads the current value of the PMCTRL3 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCTRL3 +static uint32_t __get_PMCTRL3 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 3, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 23, r10, 11 +#endif +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL4 (Performance count control 4 register). + * @details Writes a value to the PMCTRL4 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCTRL4 +static void __set_PMCTRL4 (uint32_t value) +{ + ldsr r6, 4, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL4- (Performance count control 4 register). + * @details Reads the current value of the PMCTRL4 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCTRL4 +static uint32_t __get_PMCTRL4 (void) +{ + stsr 4, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL5 (Performance count control 5 register). + * @details Writes a value to the PMCTRL5 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCTRL5 +static void __set_PMCTRL5 (uint32_t value) +{ + ldsr r6, 5, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL5 (Performance count control 5 register). + * @details Reads the current value of the PMCTRL5 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCTRL5 +static uint32_t __get_PMCTRL5 (void) +{ + stsr 5, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL6 (Performance count control 6 register). + * @details Writes a value to the PMCTRL6 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCTRL6 +static void __set_PMCTRL6 (uint32_t value) +{ + ldsr r6, 6, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL6 (Performance count control 6 register). + * @details Reads the current value of the PMCTRL6 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCTRL6 +static uint32_t __get_PMCTRL6 (void) +{ + stsr 6, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL7 (Performance count control 7 register). + * @details Writes a value to the PMCTRL7 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCTRL7 +static void __set_PMCTRL7 (uint32_t value) +{ + ldsr r6, 7, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL7 (Performance count control 7 register). + * @details Reads the current value of the PMCTRL7 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCTRL7 +static uint32_t __get_PMCTRL7 (void) +{ + stsr 7, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Set PMCOUNT0 (Performance count 0 register). + * @details Writes a value to the PMCOUNT0 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCOUNT0 +static void __set_PMCOUNT0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 16, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 16, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT0 (Performance count 0 register). + * @details Reads the current value of the PMCOUNT0 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCOUNT0 +static uint32_t __get_PMCOUNT0 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 16, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 16, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Set PMCOUNT1 (Performance count 1 register). + * @details Writes a value to the PMCOUNT1 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCOUNT1 +static void __set_PMCOUNT1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 17, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 18, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT1 (Performance count 1 register). + * @details Reads the current value of the PMCOUNT1 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCOUNT1 +static uint32_t __get_PMCOUNT1 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 17, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 18, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Set PMCOUNT2 (Performance count 2 register). + * @details Writes a value to the PMCOUNT2 system register. + * @param[in] value uint32_t input. + */ + +/* Performance count 2 register */ +#pragma inline_asm __set_PMCOUNT2 +static void __set_PMCOUNT2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 18, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 20, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT2 (Performance count 2 register). + * @details Reads the current value of the PMCOUNT2 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCOUNT2 +static uint32_t __get_PMCOUNT2 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 18, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 20, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Set PMCOUNT3 (Performance count 3 register). + * @details Writes a value to the PMCOUNT3 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_PMCOUNT3 +static void __set_PMCOUNT3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + ldsr r6, 19, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + ldsr r6, 22, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT3 (Performance count 3 register). + * @details Reads the current value of the PMCOUNT3 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_PMCOUNT3 +static uint32_t __get_PMCOUNT3 (void) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + stsr 19, r10, 14 +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + stsr 22, r10, 11 +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT4 (Performance count 4 register). + * @details Writes a value to the PMCOUNT4 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCOUNT4 +static void __set_PMCOUNT4 (uint32_t value) +{ + ldsr r6, 20, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT4 (Performance count 4 register). + * @details Reads the current value of the PMCOUNT4 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCOUNT4 +static uint32_t __get_PMCOUNT4 (void) +{ + stsr 20, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT5 (Performance count 5 register). + * @details Writes a value to the PMCOUNT5 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCOUNT5 +static void __set_PMCOUNT5 (uint32_t value) +{ + ldsr r6, 21, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT5 (Performance count 5 register). + * @details Reads the current value of the PMCOUNT5 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCOUNT5 +static uint32_t __get_PMCOUNT5 (void) +{ + stsr 21, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT6 (Performance count 6 register). + * @details Writes a value to the PMCOUNT6 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCOUNT6 +static void __set_PMCOUNT6 (uint32_t value) +{ + ldsr r6, 22, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT6 (Performance count 6 register). + * @details Reads the current value of the PMCOUNT6 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCOUNT6 +static uint32_t __get_PMCOUNT6 (void) +{ + stsr 22, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT7 (Performance count 7 register). + * @details Writes a value to the PMCOUNT7 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMCOUNT7 +static void __set_PMCOUNT7 (uint32_t value) +{ + ldsr r6, 23, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT7 (Performance count 7 register). + * @details Reads the current value of the PMCOUNT7 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMCOUNT7 +static uint32_t __get_PMCOUNT7 (void) +{ + stsr 23, r10, 14 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND0 (Performance count subcondition 0 register). + * @details Writes a value to the PMSUBCND0 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND0 +static void __set_PMSUBCND0 (uint32_t value) +{ + ldsr r6, 0, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND0 (Performance count subcondition 0 register). + * @details Reads the current value of the PMSUBCND0 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND0 +static uint32_t __get_PMSUBCND0 (void) +{ + stsr 0, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND1 (Performance count subcondition 1 register). + * @details Writes a value to the PMSUBCND1 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND1 +static void __set_PMSUBCND1 (uint32_t value) +{ + ldsr r6, 1, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND1 (Performance count subcondition 1 register). + * @details Reads the current value of the PMSUBCND1 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND1 +static uint32_t __get_PMSUBCND1 (void) +{ + stsr 1, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND2 (Performance count subcondition 2 register). + * @details Writes a value to the PMSUBCND2 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND2 +static void __set_PMSUBCND2 (uint32_t value) +{ + ldsr r6, 2, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND2 (Performance count subcondition 2 register). + * @details Reads the current value of the PMSUBCND2 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND2 +static uint32_t __get_PMSUBCND2 (void) +{ + stsr 2, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND3 (Performance count subcondition 3 register). + * @details Writes a value to the PMSUBCND3 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND3 +static void __set_PMSUBCND3 (uint32_t value) +{ + ldsr r6, 3, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND3 (Performance count subcondition 3 register). + * @details Reads the current value of the PMSUBCND3 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND3 +static uint32_t __get_PMSUBCND3 (void) +{ + stsr 3, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND4 (Performance count subcondition 4 register). + * @details Writes a value to the PMSUBCND4 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND4 +static void __set_PMSUBCND4 (uint32_t value) +{ + ldsr r6, 4, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND4 (Performance count subcondition 4 register). + * @details Reads the current value of the PMSUBCND4 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND4 +static uint32_t __get_PMSUBCND4 (void) +{ + stsr 4, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND5 (Performance count subcondition 5 register). + * @details Writes a value to the PMSUBCND5 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND5 +static void __set_PMSUBCND5 (uint32_t value) +{ + ldsr r6, 5, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND5 (Performance count subcondition 5 register). + * @details Reads the current value of the PMSUBCND5 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND5 +static uint32_t __get_PMSUBCND5 (void) +{ + stsr 5, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND6 (Performance count subcondition 6 register). + * @details Writes a value to the PMSUBCND6 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND6 +static void __set_PMSUBCND6 (uint32_t value) +{ + ldsr r6, 6, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND6 (Performance count subcondition 6 register). + * @details Reads the current value of the PMSUBCND6 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND6 +static uint32_t __get_PMSUBCND6 (void) +{ + stsr 6, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND7 (Performance count subcondition 7 register). + * @details Writes a value to the PMSUBCND7 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_PMSUBCND7 +static void __set_PMSUBCND7 (uint32_t value) +{ + ldsr r6, 7, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND7 (Performance count subcondition 7 register). + * @details Reads the current value of the PMSUBCND7 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_PMSUBCND7 +static uint32_t __get_PMSUBCND7 (void) +{ + stsr 7, r10, 15 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Hardware Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Writes a value to the LSTEST0 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_LSTEST0 +static void __set_LSTEST0 (uint32_t value) +{ + ldsr r6, 0, 12 +} + +/** + * @brief Get LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Reads the current value of the LSTEST0 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_LSTEST0 +static uint32_t __get_LSTEST0 (void) +{ + stsr 0, r10, 12 +} + +/** + * @brief Set LSTEST1- (Lock-step function self-diagnosis register 1). + * @details Writes a value to the LSTEST1 system register. + * @param[in] value uint32_t input. + */ +#pragma inline_asm __set_LSTEST1 +static void __set_LSTEST1 (uint32_t value) +{ + ldsr r6, 1, 12 +} + +/** + * @brief Get LSTEST1 (Lock-step function self-diagnosis register 1). + * @details Reads the current value of the LSTEST1 system register. + * @return uint32_t register value. + * + */ +#pragma inline_asm __get_LSTEST1 +static uint32_t __get_LSTEST1 (void) +{ + stsr 1, r10, 12 +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get LSCFG (Lock-step function configuration). + * @details Reads the current value of the LSCFG system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_LSCFG +static uint32_t __get_LSCFG (void) +{ + stsr 2, r10, 12 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set IFCR (Instruction fetch control register). + * @details Writes a value to the IFCR system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_IFCR +static void __set_IFCR (uint32_t value) +{ + ldsr r6, 5, 12 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IFCR (Instruction fetch control register). + * @details Reads the current value of the IFCR system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_IFCR +static uint32_t __get_IFCR (void) +{ + stsr 5, r10, 12 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set BRPCTRL0 (Branch prediction function control register). + * @details Writes a value to the BRPCTRL0 system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_BRPCTRL0 +static void __set_BRPCTRL0 (uint32_t value) +{ + ldsr r6, 8, 12 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get BRPCTRL0 (Branch prediction function control register). + * @details Reads the current value of the BRPCTRL0 system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_BRPCTRL0 +static uint32_t __get_BRPCTRL0 (void) +{ + stsr 8, r10, 12 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get L1RCFG (L1RAM configuration). + * @details Reads the current value of the L1RCFG system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_L1RCFG +static uint32_t __get_L1RCFG (void) +{ + stsr 12, r10, 13 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set RDBCR (ROM data buffer control register). + * @details Writes a value to the RDBCR system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_RDBCR +static void __set_RDBCR (uint32_t value) +{ + ldsr r6, 24, 13 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get RDBCR (ROM data buffer control register). + * @details Reads the current value of the RDBCR system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_RDBCR +static uint32_t __get_RDBCR (void) +{ + stsr 24, r10, 13 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Virtualization Support Function System Registers + **********************************************************************************************************************/ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set HVCFG (Setting virtualization support function). + * @details Writes a value to the HVCFG system register. + * @param[in] value uint32_t input. + */ + #pragma inline_asm __set_HVCFG +static void __set_HVCFG (uint32_t value) +{ + ldsr r6, 16, 1 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get HVCFG (Setting virtualization support function). + * @details Reads the current value of the HVCFG system register. + * @return uint32_t register value. + * + */ + #pragma inline_asm __get_HVCFG +static uint32_t __get_HVCFG (void) +{ + stsr 16, r10, 1 +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** @} end of group CCRH_RH850_Core_RegAccFunctions */ + +/** @} end of group RH850_Core_FunctionInterface */ + +// Include the profile specific settings: +#include "G4-profile/rh850_ccrh_g4.h" + +#endif /* __RH850_CCRH_H */ diff --git a/arch/rh850/src/g4x/Core/Include/rh850_compiler.h b/arch/rh850/src/g4x/Core/Include/rh850_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..4a1e8ea501c4242ee45d343e87dd037e1aa729c0 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/rh850_compiler.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************************//** + * @file rh850_version.h + * @brief RH850 Compiler Generic Header File + * @version V0.0.1 + * @date 01. Jan 2026 + ******************************************************************************/ + +/* + * RH850 Compiler Generic Header File + */ + +#ifndef __RH850_COMPILER_H +#define __RH850_COMPILER_H + +#include + +/* + * CCRH Compiler + */ +#if defined(__CCRH__) + #include "rh850_ccrh.h" + +/* + * GHS Compiler + */ +#elif (__ghs__) + #include + #include "rh850_ghs.h" + +/* + * IAR Compiler + */ +#elif defined(__ICCRH850__) + #include + #include "rh850_iar.h" + +/* + * Not supported Compiler + */ +#else + #error Unknown compiler. +#endif + +#endif /* __RH850_COMPILER_H */ diff --git a/arch/rh850/src/g4x/Core/Include/rh850_ghs.h b/arch/rh850/src/g4x/Core/Include/rh850_ghs.h new file mode 100644 index 0000000000000000000000000000000000000000..d3c6b214e80c4031a200b9e66b660626f05743f4 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/rh850_ghs.h @@ -0,0 +1,4236 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_ghs.h + * @brief RH850 compiler GHS header file + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_GHS_H +#define __RH850_GHS_H + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* RH850 compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef RH850_DEPRECATED + #define RH850_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef RH850_UNSUPPORTED + #define RH850_UNSUPPORTED 0 +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { + uint16_t v; +}; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void) ((((struct T_UINT16_WRITE *) (void *) (addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { + uint16_t v; +}; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *) (const void *) (addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { + uint32_t v; +}; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void) ((((struct T_UINT32_WRITE *) (void *) (addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { + uint32_t v; +}; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *) (const void *) (addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile ("" ::: "memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__((section(".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__((alias(x))) +#endif + +/* Convert token into a string and pass it to _Pragma */ +#ifndef __PRAGMA_HELPER + #define __PRAGMA_HELPER(x) _Pragma(#x) +#endif + +/* Create the pragma inline statement with the function name as argument */ +#ifndef __PRAGMA_PLACE_IN_SECTION + #define __PRAGMA_PLACE_IN_SECTION(sec, name) __PRAGMA_HELPER(ghs section sec = name) +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE(Func_Name) __PRAGMA_HELPER(inline Func_Name) +#endif +#ifndef __FORCEINLINE_ASM + #define __FORCEINLINE_ASM(Func_Name) __PRAGMA_HELPER(inline_asm Func_Name) +#endif + +/* ########################################### Core Instruction Access ############################################ */ + +/** @defgroup RH850_Core_InstructionInterface RH850-Core Instruction Interface + * @brief Access to dedicated instructions + * @{ + */ + +/** @ingroup RH850_Core_InstructionInterface + * @defgroup GHS_RH850_Core_InstructionInterface GHS RH850-Core Instruction Interface + * @brief RH850-Core Instruction Interface + * @{ + */ + +/********************************************* ARM INTRINSIC **********************************************************/ + +/** + * @brief Instruction Synchronization Barrier + * @details Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or memory, + * after the instruction has been completed. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __ISB() __ASM volatile ("synci" ::: "memory") + +/** + * @brief Data Synchronization Barrier + * @details Acts as a special kind of Data Memory Barrier. + * It completes when all explicit memory accesses before this instruction complete. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __DSB() __ASM volatile ("syncp" ::: "memory") + +/** + * @brief Data Memory Barrier + * @details Ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __DMB() __ASM volatile ("syncm" ::: "memory") + +/** + * @brief Reverse byte order (32 bit) + * @details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __REV (uint32_t value) +{ + uint32_t result; + + __ASM volatile ("bsw %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __REV16 (uint32_t value) +{ + uint32_t result; + + __ASM volatile ("bsh %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE int16_t __REVSH (int16_t value) +{ + int16_t result; + + __ASM volatile ( + "bsh %1, %0 \n" + "andi 0xFFFF, %0, %0 \n" + : "=&r" (result) + : "r" (value) + : "memory"); + + return result; +} + +/** + * @brief Rotate Right in unsigned value (32 bit) + * @details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + * @param [in] op1 Value to rotate + * @param [in] op2 Number of Bits to rotate + * @return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR (uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + * @brief Reverse bit order of value + * @details Reverses the bit order of the given value. + * @param [in] value Value to reverse + * @return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT (uint32_t value) +{ + uint32_t result; + + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return result; +} + +/** + * @brief Count leading zeros + * @details Counts the number of leading zeros of a data value. + * @param [in] value Value to count the leading zeros + * @return number of leading zeros in value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __CLZ(value) ((__SCH1L(value)) ? (__SCH1L(value) - 1) : 32) + +/** + * @brief Signed Saturate + * @details Saturates a signed value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (1..32) + * @return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT (int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t) ((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + + return val; +} + +/** + * @brief Unsigned Saturate + * @details Saturates an unsigned value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (0..31) + * @return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT (int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t) max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + + return (uint32_t) val; +} + +/** + * @brief Remove the exclusive lock + * @details Removes the exclusive lock which is created by LDREX. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __CLREX() __CLL() + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __LDREXB(addr) (uint8_t) __LDL_BU((unsigned char *) addr) + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __LDREXH(addr) (uint16_t) __LDL_HU((unsigned short *) addr) + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __STREXH(value, addr) (uint32_t) (!__STC_H((short) value, (short *) addr)) + +/** + * @brief LDR Exclusive (32 bit) + * @details Executes a exclusive LDR instruction for 32 bit values. + * @param [in] addr Pointer to data + * @return value of type uint32_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __LDREXW(addr) __LDL_W((int *) addr) + +/** + * @brief STR Exclusive (32 bit) + * @details Executes a exclusive STR instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __STREXW(value, addr) (uint32_t) (!__STC_W((int) value, (int *) addr)) + +/** + * @brief Rotate Right with Extend (32 bit) + * @details Moves each bit of a bitstring right by one bit. + * The carry input is shifted in at the left end of the bitstring. + * @param [in] value Value to rotate + * @return Rotated value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __RRX (uint32_t value) +{ + uint32_t result; + + __ASM volatile ( + "stsr 5, r11, 0 \n" /* r11 <- PSW */ + "shr 3, r11 \n" /* r11.bit0 = CY */ + "andi 1, r11, r11 \n" /* r11 = CY (0 or 1) */ + "shl 31, r11 \n" /* r11 = CY << 31 */ + /* Shift operand and inject CY into MSB */ + "mov %1, %0 \n" + "shr 1, %0 \n" /* r10 = value >> 1 */ + "or r11, %0 \n" /* r10 = (CY<<31) | (value>>1) */ + + /* Compute new CY from old LSB of value: newCY_mask = (value & 1) << 3 */ + "mov %1, r12 \n" + "andi 1, r12, r12 \n" /* r12 = old LSB of value (0 or 1) */ + "shl 3, r12 \n" /* r12 = newCY_mask (0x0 or 0x8) */ + + /* Read PSW, clear CY bit, then set according to newCY_mask */ + "stsr 5, r13, 0 \n" /* r13 <- PSW */ + + /* Clear-mask (~0x8) */ + "movhi 0xFFFF, r0, r11 \n" /* r11 = 0xFFFF0000 */ + "ori 0xFFF7, r11, r11 \n" /* r11 = 0xFFFF0000 + 0xFFF7 = 0xFFFFFFF7 */ + "and r11, r13 \n" /* r13 &= ~0x8 (clear PSW.CY) */ + "or r12, r13 \n" /* r13 |= newCY_mask */ + + /* Write PSW back */ + "ldsr r13, 5, 0 \n" /* PSW <- r13 */ + : "=&r" (result) + : "r" (value) + : "memory", "r11", "r12", "r13" + ); + + return result; +} + +/** + * @brief Load-Acquire (8 bit) + * @details Executes a LDAB instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint8_t __LDAB (volatile uint8_t * ptr) +{ + uint8_t result; + + __ASM volatile ( + "ld.bu 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Load-Acquire (16 bit) + * @details Executes a LDAH instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint16_t __LDAH (volatile uint16_t * ptr) +{ + uint16_t result; + + __ASM volatile ( + "ld.hu 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Load-Acquire (32 bit) + * @details Executes a LDA instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __LDA (volatile uint32_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "ld.w 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Store-Release (8 bit) + * @details Executes a STLB instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STLB (uint8_t value, volatile uint8_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.b %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Store-Release (16 bit) + * @details Executes a STLH instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STLH (uint16_t value, volatile uint16_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.h %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Store-Release (32 bit) + * @details Executes a STL instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STL (uint32_t value, volatile uint32_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.w %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Load-Acquire Exclusive (8 bit) + * @details Executes a LDAB exclusive instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB (volatile uint8_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.bu [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return (uint8_t) result; +} + +/** + * @brief Load-Acquire Exclusive (16 bit) + * @details Executes a LDAH exclusive instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH (volatile uint16_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.hu [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return (uint16_t) result; +} + +/** + * @brief Load-Acquire Exclusive (32 bit) + * @details Executes a LDA exclusive instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __LDAEX (volatile uint32_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.w [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Store-Release Exclusive (8 bit) + * @details Executes a STLB exclusive instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEXB (uint8_t value, volatile uint8_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.b %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief Store-Release Exclusive (16 bit) + * @details Executes a STLH exclusive instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEXH (uint16_t value, volatile uint16_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.h %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief Store-Release Exclusive (32 bit) + * @details Executes a STL exclusive instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEX (uint32_t value, volatile uint32_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.w %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __STREXB(value, addr) (!__STC_B((char) value, (char *) addr)) + +/********************************************* RH850 INTRINSIC ********************************************************/ + +/* Load Instructions */ + +/** + * @brief Load byte + * @details Executes a LD.B instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type int8_t at (*ptr) + */ +__STATIC_FORCEINLINE int8_t __LDB (volatile int8_t * ptr) +{ + int8_t result; + __ASM volatile ("ld.b 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load byte unsigned + * @details Executes a LD.BU instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDBU (volatile uint8_t * ptr) +{ + uint8_t result; + __ASM volatile ("ld.bu 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load halfword + * @details Executes a LD.H instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type int16_t at (*ptr) + */ +__STATIC_FORCEINLINE int16_t __LDH (volatile int16_t * ptr) +{ + int16_t result; + __ASM volatile ("ld.h 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load halfword unsigned + * @details Executes a LD.HU instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type int16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDHU (volatile uint16_t * ptr) +{ + uint16_t result; + __ASM volatile ("ld.hu 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load word + * @details Executes a LD.W instruction for 32 bit value. + * @param [in] ptr Pointer to data + * @return value of type int32_t at (*ptr) + */ +__STATIC_FORCEINLINE int32_t __LDW (volatile int32_t * ptr) +{ + int32_t result; + __ASM volatile ("ld.w 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load double word + * @details Executes a LD.DW instruction for 64 bit value. + * @param [in] ptr Pointer to data + * @return value of type int64_t at (*ptr) + */ +__STATIC_FORCEINLINE int64_t __LDDW (volatile int64_t * ptr) +{ + int64_t result; + __ASM volatile ("ld.dw 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/* Store Instructions */ + +/** + * @brief Store byte + * @details Executes a ST.B instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STB (int8_t value, volatile int8_t * ptr) +{ + __ASM volatile ("st.b %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store halfword + * @details Executes a ST.H instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STH (int16_t value, volatile int16_t * ptr) +{ + __ASM volatile ("st.h %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store word + * @details Executes a ST.W instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STW (int32_t value, volatile int32_t * ptr) +{ + __ASM volatile ("st.w %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store double word + * @details Executes a ST.DW instruction for 64 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STDW (int64_t value, volatile int64_t * ptr) +{ + __ASM volatile ("st.dw %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/* Multiply Instructions */ + +/** + * @brief Signed 64-bit multiplication high 32 bits + * @details Assigns higher 32 bits of signed 64-bit multiplication result. + * @param [in] a Multiplicand + * @param [in] b Multiplier + * @return High 32 bits of result + */ +__STATIC_FORCEINLINE int32_t __MUL (int32_t a, int32_t b) +{ + int32_t result; + int32_t reg1 = a; + int32_t reg2 = b; + __ASM volatile ("mul %1, %2, %0" : "=r" (result) : "r" (reg1), "r" (reg2) : "memory"); + + return result; +} + +/** + * @brief Unsigned 64-bit multiplication high 32 bits + * @details Assigns higher 32 bits of unsigned 64-bit multiplication result. + * @param [in] a Multiplicand + * @param [in] b Multiplier + * @return High 32 bits of result + */ +__STATIC_FORCEINLINE long __MULU (long a, long b) +{ + long result; + long reg1 = a; + long reg2 = b; + + __ASM volatile ("mulu %1, %2, %0" : "=r" (result) : "r" (reg1), "r" (reg2) : "memory"); + + return result; +} + +/** + * @brief Saturated addition + * @details Performs saturated addition of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated addition + */ +#define __SATADD(a, b) __ADD_SAT((int) a, (int) b) + +/** + * @brief Saturated subtraction + * @details Performs saturated subtraction of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated subtraction + */ +#define __SATSUB(a, b) __SUB_SAT((int) a, (int) b) + +/** + * @brief Halfword data byte swap + * @details Swaps bytes within a 16-bit halfword. + * @param [in] value Value to swap + * @return Swapped value + */ +__STATIC_FORCEINLINE uint32_t __BSH (uint32_t value) +{ + uint32_t result; + __ASM volatile ("bsh %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Word data byte swap + * @details Swaps bytes within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +__STATIC_FORCEINLINE int32_t __BSW (int32_t value) +{ + int32_t result; + __ASM volatile ("bsw %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Signed data conversion from word to byte with saturation + * @details Conversion of signed word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + */ +#define __CLIPB(value) __CLIP_B((int) value) + +/** + * @brief Unsigned data conversion from word to byte with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + */ +#define __CLIPBU(value) __CLIP_BU((int) value) + +/** + * @brief Signed data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + */ +#define __CLIPH(value) __CLIP_H((int) value) + +/** + * @brief Unsigned data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to halfword data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + */ +#define __CLIPHU(value) __CLIP_HU((int) value) + +/** + * @brief Halfword swap halfword + * @details Swaps halfwords within a 16-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +__STATIC_FORCEINLINE int16_t __HSH (int16_t value) +{ + int16_t result; + __ASM volatile ("hsh %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Word data halfword swap + * @details Swaps halfwords within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +__STATIC_FORCEINLINE int32_t __HSW (int32_t value) +{ + int32_t result; + __ASM volatile ("hsw %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Rotate left + * @param [in] value Value to rotate + * @param [in] bit The specified shift amount + * @return Swapped value + */ +__STATIC_FORCEINLINE int32_t __ROTL (int32_t value, uint8_t bit) +{ + int32_t result; + __ASM volatile ("rotl %1, %2, %0" : "=&r" (result) : "r" (bit), "r" (value) : "memory"); + + return result; +} + +/** + * @brief Bit (0) search from MSB side + * @details Searches for first 0 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH0L(value) __SCH0L((int) value) + +/** + * @brief Bit (0) search from LSB side + * @details Searches for first 0 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH0R(value) __SCH0R((int) value) + +/** + * @brief Bit (1) search from MSB side + * @details Searches for first 1 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH1L(value) __SCH1L((int) value) + +/** + * @brief Bit (1) search from LSB side + * @details Searches for first 1 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH1R(value) __SCH1R((int) value) + +/** + * @brief Divide word + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return Quotient = num1/num2 + */ +__STATIC_FORCEINLINE int32_t __DIV (int32_t num1, int32_t num2) +{ + int32_t result; + __ASM volatile ("div %2, %1, %0" : "=&r" (result) : "r" (num1), "r" (num2) : "memory"); + + return result; +} + +/** + * @brief Divide word unsigned + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return Quotient = num1/num2 + */ +__STATIC_FORCEINLINE uint32_t __DIVU (uint32_t num1, uint32_t num2) +{ + uint32_t result; + __ASM volatile ("divu %2, %1, %0" : "=&r" (result) : "r" (num1), "r" (num2) : "memory"); + + return result; +} + +/** + * @brief Bit set + * @details Sets a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +__STATIC_FORCEINLINE void __clr1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "clr1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +#define __CLR1(addr, bit) __clr1(addr, bit) + +/** + * @brief Bit set + * @details Sets a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +__STATIC_FORCEINLINE void __set1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "set1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +#define __SET1(addr, bit) __set1(addr, bit) + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +__STATIC_FORCEINLINE void __not1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "not1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +#define __NOT1(addr, bit) __not1(addr, bit) + +/** + * @brief Compare and Exchange + * @details Atomic compare and exchange operation. + * @param [in] addr Address + * @param [in] b Compare value + * @param [in] c Exchange value + */ +#define __CAXI(addr, b, c) __CAXI((int *) addr, (int) b, (int) c) + +/** + * @brief Clear Load Link + * @details Clear Load Link which is created by LDL. + */ +#define __CLL() __CLL() + +/** + * @brief Disable Interrupts + * @details Executes the DI instruction to disable maskable interrupts. + */ +#define __DI() __DI() + +/** + * @brief Enable Interrupts + * @details Executes the EI instruction to enable maskable interrupts. + */ +#define __EI() __EI() + +/** + * @brief Return from EI-level trap or interrupt + */ +#define __EIRET() __ASM volatile ("eiret") + +/** + * @brief Return from FE-level trap or interrupt + */ +#define __FERET() __ASM volatile ("feret") + +/** + * @brief FE-level trap + */ +#define __FETRAP(vector) __ASM volatile ("fetrap " #vector) + +/** + * @brief Load to system register (with selector) + * @details Loads value into system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @param [in] value Value to load + */ +#define __LDSR(regID, selID, value) __LDSR((int) regID, (int) selID, (unsigned int) value) + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*addr) + */ +#define __LDLBU(addr) __LDL_BU((unsigned char *) addr) + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*ptr) + */ +#define __LDLHU(addr) __LDL_HU((unsigned short *) addr) + +/** + * @brief Atomic load to system register + * @details Loads a value into a system register atomically. + * @param [in] addr Value to load + */ +#define __LDLW(addr) __LDL_W((int *) addr) + +/** + * @brief No Operation + * @details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __NOP() + +/** + * @brief Restore contexts from register bank + */ +#define __RESBANK() __ASM volatile ("resbank") + +/** + * @brief Snooze + */ +#define __SNOOZE() __SNOOZE() + +/** + * @brief Store contents of system register (with selector) + * @details Stores contents of system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @return Register value + */ +#define __STSR(regID, selID) __STSR((int) regID, (int) selID) + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +#define __STCB(addr, value) __STC_B((char) value, (char *) addr) + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +#define __STCH(addr, value) __STC_H((short) value, (short *) addr) + +/** + * @brief Store word + * @details Stores a word to memory. + * @param [in] addr Address + * @param [in] value Value + */ +#define __STCW(addr, value) __STC_W((int) value, (int *) addr) + +/** + * @brief Exception synchronization + * @details Synchronizes exception handling. + */ +#define __SYNCE() __SYNCE() + +/** + * @brief Instruction pipeline synchronization + * @details Synchronizes instruction pipeline. + */ +#define __SYNCI() __SYNCI() + +/** + * @brief Memory synchronization + * @details Synchronizes memory operations. + */ +#define __SYNCM() __SYNCM() + +/** + * @brief Pipeline synchronization + * @details Synchronizes pipeline operations. + */ +#define __SYNCP() __SYNCP() + +/** + * @brief Trap + */ +#define __TRAP(vector) __ASM volatile ("trap " #vector::: "memory") + +/** + * @brief Halt CPU + * @details HALT instruction stops CPU execution until an interrupt or reset occurs. + */ +#define __HALT() __HALT() + +/** + * @brief Debug checkpoint + * @details Inserts a debug checkpoint instruction. + */ +#define __DBCP() __DBCP() + +/** + * @brief Debug push + * @details Pushes debug registers. + * @param [in] regID1 First register ID + * @param [in] regID2 Second register ID + */ +#define __DBPUSH(regID1, regID2) __DBPUSH((int) regID1, (int) regID2) + +/** + * @brief Debug tag + * @details Inserts a debug tag instruction. + * @param [in] a Tag value + */ +#define __DBTAG(a) __DBTAG(a) + +/** @}*/ /* end of group GHS_RH850_Core_InstructionInterface */ + +/** @}*/ /* end of group RH850_Core_InstructionInterface */ + +/* ########################################## Core Function Access ################################################ */ + +/** @defgroup RH850_Core_FunctionInterface RH850-Core Register Access Functions + * @brief Access to the dedicated core register access function instructions + * @{ + */ + +/** @ingroup RH850_Core_FunctionInterface + * @defgroup GHS_RH850_Core_RegAccFunctions GHS RH850-Core Register Access Functions + * @brief GHS RH850-Core Register Access Functions + * @{ + */ + +/** + * @brief Enable IRQ Interrupts + * @details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __enable_irq() __EI() + +/** + * @brief Disable IRQ Interrupts + * @details Disables IRQ interrupts by setting special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __disable_irq() __DI() + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set EIPC (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIPC (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIPSW (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIPSW (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEPC (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEPC (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEPSW (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEPSW (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set PSW (Program status word). + * @details Writes a value to the PSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get PSW (Program status word). + * @details Reads the current value of the PSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIIC (EI level exception cause). + * @details Writes a value to the EIIC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIIC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIIC (EI level exception cause). + * @details Reads the current value of the EIIC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIIC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEIC (FE level exception cause). + * @details Writes a value to the FEIC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEIC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 14, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEIC (FE level exception cause). + * @details Reads the current value of the FEIC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEIC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 14, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set CTPC (CALLT execution status save register). + * @details Writes a value to the CTPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTPC (CALLT execution status save register). + * @details Reads the current value of the CTPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set CTPSW (CALLT execution status save register). + * @details Writes a value to the CTPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTPSW (CALLT execution status save register). + * @details Reads the current value of the CTPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 0" : "=r" (result)); + + return result; +} + +/* CALLT base pointer */ + +/** + * @brief Set CTBP (CALLT base pointer). + * @details Writes a value to the CTBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTBP (CALLT base pointer). + * @details Reads the current value of the CTBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set SNZCFG (SNOOZE control register). + * @details Writes a value to the SNZCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SNZCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get SNZCFG (SNOOZE control register). + * @details Reads the current value of the SNZCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SNZCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIWR (EI level exception working register). + * @details Writes a value to the EIWR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIWR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIWR (EI level exception working register). + * @details Reads the current value of the EIWR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIWR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEWR (FE level exception working register). + * @details Writes a value to the FEWR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEWR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 29, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEWR (FE level exception working register). + * @details Reads the current value of the FEWR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEWR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 29, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Get SPID (System protection identifier). + * @details Reads the current value of the SPID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SPID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SPID (System protection identifier). + * @details Writes a value to the SPID system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SPID (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SPIDLIST (List of system protection identifiers that can be specified in SPID). + * @details Reads the current value of the SPIDLIST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SPIDLIST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get RBASE (Reset vector base address). + * @details Reads the current value of the RBASE system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBASE (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set EBASE (Exception handler vector address). + * @details Writes a value to the EBASE system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EBASE (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get EBASE (Exception handler vector address). + * @details Reads the current value of the EBASE system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EBASE (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set INTBP (Base address of the interrupt handler “address” table). + * @details Writes a value to the INTBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_INTBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get INTBP (Base address of the interrupt handler “address” table). + * @details Reads the current value of the INTBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_INTBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCTL (CPU control). + * @details Writes a value to the MCTL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCTL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCTL (CPU control). + * @details Reads the current value of the MCTL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCTL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get PID (Processor ID). + * @details Reads the current value of the PID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SVLOCK (Supervisor lock). + * @details Writes a value to the SVLOCK system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SVLOCK (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SVLOCK (Supervisor lock). + * @details Reads the current value of the SVLOCK system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SVLOCK (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SCCFG (SYSCALL operation setting). + * @details Writes a value to the SCCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SCCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SCCFG (SYSCALL operation setting). + * @details Reads the current value of the SCCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SCCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SCBP (SYSCALL base pointer). + * @details Writes a value to the SCBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SCBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SCBP (SYSCALL base pointer). + * @details Reads the current value of the SCBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SCBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get PEID (Processor element identifier). + * @details Reads the current value of the PEID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PEID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Get BMID (Bus master identifier). + * @details Reads the current value of the BMID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_BMID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set MEA (Memory error address). + * @details Writes a value to the MEA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MEA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get MEA (Memory error address). + * @details Reads the current value of the MEA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MEA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set MEI (Memory error information). + * @details Writes a value to the MEI system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MEI (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get MEI (Memory error information). + * @details Reads the current value of the MEI system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MEI (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBCR0 (Register bank control 0). + * @details Writes a value to the RBCR0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBCR0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 15, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBCR0 (Register bank control 0). + * @details Reads the current value of the RBCR0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBCR0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 15, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBCR1 (Register bank control 1). + * @details Writes a value to the RBCR1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBCR1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBCR1 (Register bank control 1). + * @details Reads the current value of the RBCR1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBCR1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBNR (Register bank number). + * @details Writes a value to the RBNR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBNR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBNR (Register bank number). + * @details Reads the current value of the RBNR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBNR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBIP (Register bank initial pointer). + * @details Writes a value to the RBIP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBIP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 18, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBIP (Register bank initial pointer). + * @details Reads the current value of the RBIP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBIP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 18, %0, 2" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Interrupt Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ISPR (Priority of interrupt being serviced). + * @details Writes a value to the ISPR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ISPR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get ISPR (Priority of interrupt being serviced). + * @details Reads the current value of the ISPR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ISPR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 2" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IMSR (Interrupt mask status). + * @details Reads the current value of the IMSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_IMSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 2" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Get ICSR (Interrupt control status). + * @details Reads the current value of the ICSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set INTCFG (Interrupt function setting). + * @details Writes a value to the INTCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_INTCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get INTCFG (Interrupt function setting). + * @details Reads the current value of the INTCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_INTCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set PLMR (Interrupt priority masking). + * @details Writes a value to the PLMR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PLMR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 14, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get PLMR (Interrupt priority masking). + * @details Reads the current value of the PLMR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PLMR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 14, %0, 2" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * FPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FPSR (Floating-point operation configuration/status). + * @details Writes a value to the FPSR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPSR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPSR (Floating-point operation configuration/status). + * @details Reads the current value of the FPSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPEPC (Floating-point operation exception program counter). + * @details Writes a value to the FPEPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPEPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPEPC (Floating-point operation exception program counter). + * @details Reads the current value of the FPEPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPEPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPST (Floating point operation status). + * @details Writes a value to the FPST system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPST (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPST (Floating point operation status). + * @details Reads the current value of the FPST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPCC (Floating-point operation comparison result). + * @details Writes a value to the FPCC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPCC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 9, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPCC (Floating-point operation comparison result). + * @details Reads the current value of the FPCC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPCC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPCFG (Floating-point operation configuration). + * @details Writes a value to the FPCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPCFG (Floating-point operation configuration). + * @details Reads the current value of the FPCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 0" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4KH) && (__RH850_G4KH == 1) + +/** + * @brief Set FPEC (Floating-point exception control). + * @details Writes a value to the FPEC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPEC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPEC (Floating-point exception control). + * @details Reads the current value of the FPEC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPEC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 0" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4KH) && (__RH850_G4KH == 1) */ + +/*********************************************************************************************************************** + * FXU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FXSR (Extended floating-point operation configuration/status). + * @details Writes a value to the FXSR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXSR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXSR (Extended floating-point operation configuration/status). + * @details Reads the current value of the FXSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Set FXST (Extended floating-point operation status). + * @details Writes a value to the FXST system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXST (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXST (Extended floating-point operation status). + * @details Reads the current value of the FXST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Get FXINFO (FXU configuration information). + * @details Reads the current value of the FXINFO system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXINFO (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 10" : "=r" (result)); + + return result; +} + +/* Extended floating-point operation configuration */ + +/** + * @brief Set FXCFG (Extended floating-point operation configuration). + * @details Writes a value to the FXCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXCFG (Extended floating-point operation configuration). + * @details Reads the current value of the FXCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 10" : "=r" (result)); + + return result; +} + +/* XC (cause) bits for each operation way */ + +/** + * @brief Set FXXC (XC (cause) bits for each operation way). + * @details Writes a value to the FXXC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXXC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXXC (XC (cause) bits for each operation way). + * @details Reads the current value of the FXXC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXXC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Set FXXP (XP (preservation) bits for each operation way). + * @details Writes a value to the FXXP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXXP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXXP (XP (preservation) bits for each operation way). + * @details Reads the current value of the FXXP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXXP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 10" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * MPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set MPM (Memory protection operation mode setting). + * @details Writes a value to the MPM system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPM (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPM (Memory protection operation mode setting). + * @details Reads the current value of the MPM system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPM (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Get MPCFG (MPU configuration). + * @details Reads the current value of the MPCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCA (Memory protection setting check address). + * @details Writes a value to the MCA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCA (Memory protection setting check address). + * @details Reads the current value of the MCA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCS (Memory protection setting check size). + * @details Writes a value to the MCS system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCS (uint32_t value) +{ + __ASM volatile ("ldsr %0, 9, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCS (Memory protection setting check size). + * @details Reads the current value of the MCS system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCS (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCC (Memory protection setting check command). + * @details Writes a value to the MCC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCC (Memory protection setting check command). + * @details Reads the current value of the MCC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCR (Memory protection setting check result). + * @details Writes a value to the MCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCR (Memory protection setting check result). + * @details Reads the current value of the MCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCI (Memory protection setting check SPID). + * @details Writes a value to the MCI system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCI (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCI (Memory protection setting check SPID). + * @details Reads the current value of the MCI system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCI (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPIDX (Index of memory protection setting registers to be accessed). + * @details Writes a value to the MPIDX system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPIDX (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPIDX (Index of memory protection setting registers to be accessed). + * @details Reads the current value of the MPIDX system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDX (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPBK (MPU Bank Setting). + * @details Writes a value to the MPBK system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPBK (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPBK (MPU Bank Setting). + * @details Reads the current value of the MPBK system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPBK (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPLA (Protection area minimum address). + * @details Writes a value to the MPLA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPLA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPLA (Protection area minimum address). + * @details Reads the current value of the MPLA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPLA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPUA (Protection area maximum address). + * @details Writes a value to the MPUA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPUA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPUA (Protection area maximum address). + * @details Reads the current value of the MPUA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPUA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPAT (Protection area attribute). + * @details Writes a value to the MPAT system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPAT (uint32_t value) +{ + __ASM volatile ("ldsr %0, 22, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPAT (Protection area attribute). + * @details Reads the current value of the MPAT system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPAT (void) +{ + uint32_t result; + + __ASM volatile ("stsr 22, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID0 (SPID which can access protection area). + * @details Writes a value to the MPID0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID0 (SPID which can access protection area). + * @details Reads the current value of the MPID0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID1 (SPID which can access protection area). + * @details Writes a value to the MPID1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 25, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID1 (SPID which can access protection area). + * @details Reads the current value of the MPID1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 25, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID2 (SPID which can access protection area). + * @details Writes a value to the MPID2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID2 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 26, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID2 (SPID which can access protection area). + * @details Reads the current value of the MPID2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID2 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 26, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID3 (SPID which can access protection area). + * @details Writes a value to the MPID3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID3 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 27, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID3 (SPID which can access protection area). + * @details Reads the current value of the MPID3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID3 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 27, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID4 (SPID which can access protection area). + * @details Writes a value to the MPID4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID4 (SPID which can access protection area). + * @details Reads the current value of the MPID4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID5 (SPID which can access protection area). + * @details Writes a value to the MPID5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 29, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID5 (SPID which can access protection area). + * @details Reads the current value of the MPID5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 29, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID6 (SPID which can access protection area). + * @details Writes a value to the MPID6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 30, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID6 (SPID which can access protection area). + * @details Reads the current value of the MPID6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 30, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID7 (SPID which can access protection area). + * @details Writes a value to the MPID7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 31, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID7 (SPID which can access protection area). + * @details Reads the current value of the MPID7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 31, %0, 5" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Cache Operation Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ICTAGL (Instruction cache tag Lo access). + * @details Writes a value to the ICTAGL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICTAGL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICTAGL (Instruction cache tag Lo access). + * @details Reads the current value of the ICTAGL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICTAGL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICTAGH (Instruction cache tag Hi access). + * @details Writes a value to the ICTAGH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICTAGH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICTAGH (Instruction cache tag Hi access). + * @details Reads the current value of the ICTAGH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICTAGH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICDATL (Instruction cache data Lo access). + * @details Writes a value to the ICDATL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICDATL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 18, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICDATL (Instruction cache data Lo access). + * @details Reads the current value of the ICDATL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICDATL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 18, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICDATH (Instruction cache data Hi access). + * @details Writes a value to the ICDATH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICDATH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 19, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICDATH (Instruction cache data Hi access). + * @details Reads the current value of the ICDATH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICDATH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 19, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICCTRL (Instruction cache control). + * @details Writes a value to the ICCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICCTRL (Instruction cache control). + * @details Reads the current value of the ICCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Get ICCFG (Instruction cache configuration). + * @details Reads the current value of the ICCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 26, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICERR (Instruction cache error). + * @details Writes a value to the ICERR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICERR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICERR (Instruction cache error). + * @details Reads the current value of the ICERR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICERR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 4" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set TSCOUNTL (Timestamp count L register). + * @details Writes a value to the TSCOUNTL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCOUNTL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCOUNTL (Timestamp count L register). + * @details Reads the current value of the TSCOUNTL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCOUNTL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set TSCOUNTH (Timestamp count H register). + * @details Writes a value to the TSCOUNTH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCOUNTH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCOUNTH (Timestamp count H register). + * @details Reads the current value of the TSCOUNTH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCOUNTH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set TSCTRL (Timestamp count control register). + * @details Writes a value to the TSCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCTRL (Timestamp count control register). + * @details Reads the current value of the TSCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set PMUMCTRL (Performance counter User mode control register). + * @details Writes a value to the PMUMCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMUMCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get PMUMCTRL (Performance counter User mode control register). + * @details Reads the current value of the PMUMCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMUMCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set PMCTRL0 (Performance count control 0 register). + * @details Writes a value to the PMCTRL0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 0, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 17, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL0 (Performance count control 0 register). + * @details Reads the current value of the PMCTRL0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL0 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 0, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 17, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL1 (Performance count control 1 register). + * @details Writes a value to the PMCTRL1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 1, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 19, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL1 (Performance count control 1 register). + * @details Reads the current value of the PMCTRL1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL1 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 1, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 19, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL2 (Performance count control 2 register). + * @details Writes a value to the PMCTRL2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 2, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 21, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL2 (Performance count control 2 register). + * @details Reads the current value of the PMCTRL2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL2 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 2, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 21, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL3 (Performance count control 3 register). + * @details Writes a value to the PMCTRL3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 3, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 23, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL3 (Performance count control 3 register). + * @details Reads the current value of the PMCTRL3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL3 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 3, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 23, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL4 (Performance count control 4 register). + * @details Writes a value to the PMCTRL4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL4- (Performance count control 4 register). + * @details Reads the current value of the PMCTRL4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL5 (Performance count control 5 register). + * @details Writes a value to the PMCTRL5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL5 (Performance count control 5 register). + * @details Reads the current value of the PMCTRL5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL6 (Performance count control 6 register). + * @details Writes a value to the PMCTRL6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL6 (Performance count control 6 register). + * @details Reads the current value of the PMCTRL6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL7 (Performance count control 7 register). + * @details Writes a value to the PMCTRL7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL7 (Performance count control 7 register). + * @details Reads the current value of the PMCTRL7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Set PMCOUNT0 (Performance count 0 register). + * @details Writes a value to the PMCOUNT0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 16, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 16, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT0 (Performance count 0 register). + * @details Reads the current value of the PMCOUNT0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT0 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 16, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 16, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT1 (Performance count 1 register). + * @details Writes a value to the PMCOUNT1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 17, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 18, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT1 (Performance count 1 register). + * @details Reads the current value of the PMCOUNT1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT1 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 17, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 18, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT2 (Performance count 2 register). + * @details Writes a value to the PMCOUNT2 system register. + * @param[in] value uint32_t input. + */ + +/* Performance count 2 register */ +__STATIC_FORCEINLINE void __set_PMCOUNT2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 18, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 20, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT2 (Performance count 2 register). + * @details Reads the current value of the PMCOUNT2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT2 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 18, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 20, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT3 (Performance count 3 register). + * @details Writes a value to the PMCOUNT3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 19, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 22, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT3 (Performance count 3 register). + * @details Reads the current value of the PMCOUNT3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT3 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 19, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 22, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT4 (Performance count 4 register). + * @details Writes a value to the PMCOUNT4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT4 (Performance count 4 register). + * @details Reads the current value of the PMCOUNT4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT5 (Performance count 5 register). + * @details Writes a value to the PMCOUNT5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT5 (Performance count 5 register). + * @details Reads the current value of the PMCOUNT5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT6 (Performance count 6 register). + * @details Writes a value to the PMCOUNT6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 22, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT6 (Performance count 6 register). + * @details Reads the current value of the PMCOUNT6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 22, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT7 (Performance count 7 register). + * @details Writes a value to the PMCOUNT7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 23, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT7 (Performance count 7 register). + * @details Reads the current value of the PMCOUNT7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 23, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND0 (Performance count subcondition 0 register). + * @details Writes a value to the PMSUBCND0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND0 (Performance count subcondition 0 register). + * @details Reads the current value of the PMSUBCND0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND1 (Performance count subcondition 1 register). + * @details Writes a value to the PMSUBCND1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND1 (Performance count subcondition 1 register). + * @details Reads the current value of the PMSUBCND1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND2 (Performance count subcondition 2 register). + * @details Writes a value to the PMSUBCND2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND2 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND2 (Performance count subcondition 2 register). + * @details Reads the current value of the PMSUBCND2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND2 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND3 (Performance count subcondition 3 register). + * @details Writes a value to the PMSUBCND3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND3 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND3 (Performance count subcondition 3 register). + * @details Reads the current value of the PMSUBCND3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND3 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND4 (Performance count subcondition 4 register). + * @details Writes a value to the PMSUBCND4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND4 (Performance count subcondition 4 register). + * @details Reads the current value of the PMSUBCND4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND5 (Performance count subcondition 5 register). + * @details Writes a value to the PMSUBCND5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND5 (Performance count subcondition 5 register). + * @details Reads the current value of the PMSUBCND5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND6 (Performance count subcondition 6 register). + * @details Writes a value to the PMSUBCND6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 15 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND6 (Performance count subcondition 6 register). + * @details Reads the current value of the PMSUBCND6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 15 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND7 (Performance count subcondition 7 register). + * @details Writes a value to the PMSUBCND7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 15 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND7 (Performance count subcondition 7 register). + * @details Reads the current value of the PMSUBCND7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 15 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Hardware Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Writes a value to the LSTEST0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_LSTEST0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 12 \n" : : "r" (value) : "memory"); +} + +/** + * @brief Get LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Reads the current value of the LSTEST0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSTEST0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 12 \n" : "=r" (result)); + + return result; +} + +/** + * @brief Set LSTEST1- (Lock-step function self-diagnosis register 1). + * @details Writes a value to the LSTEST1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_LSTEST1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 12 \n" : : "r" (value) : "memory"); +} + +/** + * @brief Get LSTEST1 (Lock-step function self-diagnosis register 1). + * @details Reads the current value of the LSTEST1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSTEST1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 12 \n" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get LSCFG (Lock-step function configuration). + * @details Reads the current value of the LSCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set IFCR (Instruction fetch control register). + * @details Writes a value to the IFCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_IFCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 12 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IFCR (Instruction fetch control register). + * @details Reads the current value of the IFCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_IFCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set BRPCTRL0 (Branch prediction function control register). + * @details Writes a value to the BRPCTRL0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_BRPCTRL0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 12 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get BRPCTRL0 (Branch prediction function control register). + * @details Reads the current value of the BRPCTRL0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_BRPCTRL0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get L1RCFG (L1RAM configuration). + * @details Reads the current value of the L1RCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_L1RCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 13 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set RDBCR (ROM data buffer control register). + * @details Writes a value to the RDBCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RDBCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 13 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get RDBCR (ROM data buffer control register). + * @details Reads the current value of the RDBCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RDBCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 13 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Virtualization Support Function System Registers + **********************************************************************************************************************/ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set HVCFG (Setting virtualization support function). + * @details Writes a value to the HVCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_HVCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 1 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get HVCFG (Setting virtualization support function). + * @details Reads the current value of the HVCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_HVCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 1 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** @} end of group GHS_RH850_Core_RegAccFunctions */ + +/** @} end of group RH850_Core_FunctionInterface */ + +// Include the profile specific settings: +#include "G4-profile/rh850_ghs_g4.h" + +#endif /* __RH850_GHS_H */ diff --git a/arch/rh850/src/g4x/Core/Include/rh850_iar.h b/arch/rh850/src/g4x/Core/Include/rh850_iar.h new file mode 100644 index 0000000000000000000000000000000000000000..b6ca59d6c3670ec4f99e5001d8c8476821f7006d --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/rh850_iar.h @@ -0,0 +1,4327 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file rh850_iar.h + * @brief RH850 compiler IAR header file + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef __RH850_IAR_H +#define __RH850_IAR_H + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* RH850 compiler specific defines */ +#ifdef SPIDLIST + #undef SPIDLIST +#endif +#ifdef __ASM + #undef __ASM +#endif +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef RH850_DEPRECATED + #define RH850_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef RH850_UNSUPPORTED + #define RH850_UNSUPPORTED 0 +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { + uint16_t v; +}; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void) ((((struct T_UINT16_WRITE *) (void *) (addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { + uint16_t v; +}; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *) (const void *) (addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { + uint32_t v; +}; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void) ((((struct T_UINT32_WRITE *) (void *) (addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { + uint32_t v; +}; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *) (const void *) (addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile ("" ::: "memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__((section(".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__((alias(x))) +#endif + +/* Convert token into a string and pass it to _Pragma */ +#ifndef __PRAGMA_HELPER + #define __PRAGMA_HELPER(x) _Pragma(#x) +#endif + +/* Create the pragma inline statement with the function name as argument */ +#ifndef __PRAGMA_PLACE_IN_SECTION + #define __PRAGMA_PLACE_IN_SECTION(sec, name) __PRAGMA_HELPER(sec = @ name) +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE(Func_Name) __PRAGMA_HELPER(inline Func_Name) +#endif +#ifndef __FORCEINLINE_ASM + #define __FORCEINLINE_ASM(Func_Name) __PRAGMA_HELPER(inline_asm Func_Name) +#endif + +/* ########################################### Core Instruction Access ############################################ */ + +/** @defgroup RH850_Core_InstructionInterface RH850-Core Instruction Interface + * @brief Access to dedicated instructions + * @{ + */ + +/** @ingroup RH850_Core_InstructionInterface + * @defgroup IAR_RH850_Core_InstructionInterface IAR RH850-Core Instruction Interface + * @brief RH850-Core Instruction Interface + * @{ + */ + +/********************************************* ARM INTRINSIC **********************************************************/ + +/** + * @brief Instruction Synchronization Barrier + * @details Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or memory, + * after the instruction has been completed. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __ISB() __SYNCI() + +/** + * @brief Data Synchronization Barrier + * @details Acts as a special kind of Data Memory Barrier. + * It completes when all explicit memory accesses before this instruction complete. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __DSB() __SYNCP() + +/** + * @brief Data Memory Barrier + * @details Ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __DMB() __SYNCM() + +/** + * @brief Reverse byte order (32 bit) + * @details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ + +#define __REV(value) __BSW(value) + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __REV16(value) __BSH(value) + +/** + * @brief Reverse byte order (16 bit) + * @details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + * @param [in] value Value to reverse + * @return Reversed value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ + +#define __REVSH(value) (int16_t) __BSH(value) + +/** + * @brief Rotate Right in unsigned value (32 bit) + * @details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + * @param [in] op1 Value to rotate + * @param [in] op2 Number of Bits to rotate + * @return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR (uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + * @brief Reverse bit order of value + * @details Reverses the bit order of the given value. + * @param [in] value Value to reverse + * @return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT (uint32_t value) +{ + uint32_t result; + + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + + result <<= s; /* shift when v's highest bits are zero */ + + return result; +} + +/** + * @brief Count leading zeros + * @details Counts the number of leading zeros of a data value. + * @param [in] value Value to count the leading zeros + * @return number of leading zeros in value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +#define __CLZ(value) ((__SCH1L(value)) ? (__SCH1L(value) - 1) : 32) + +/** + * @brief Signed Saturate + * @details Saturates a signed value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (1..32) + * @return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT (int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t) ((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + + return val; +} + +/** + * @brief Unsigned Saturate + * @details Saturates an unsigned value. + * @param [in] val Value to be saturated + * @param [in] sat Bit position to saturate to (0..31) + * @return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT (int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t) max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + + return (uint32_t) val; +} + +/** + * @brief Remove the exclusive lock + * @details Removes the exclusive lock which is created by LDREX. + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __CLREX (void) +{ + __ASM volatile ("cll" ::: "memory"); /* Clear Load Link */ +} + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint8_t __LDREXB (volatile uint8_t * addr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ("ldl.bu [%1], %0" : "=&r" (result) : "r" (addr) : "memory"); + + /* Add explicit type cast here */ + return (uint8_t) result; +} + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint16_t __LDREXH (volatile uint16_t * addr) +{ + uint16_t result; + + /* Load to start atomic halfword data manipulation */ + __ASM volatile ("ldl.hu [%1], %0" : "=&r" (result) : "r" (addr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STREXH (uint16_t value, volatile uint16_t * addr) +{ + uint32_t result; + + __ASM volatile ( + "stc.b %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (addr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief LDR Exclusive (32 bit) + * @details Executes a exclusive LDR instruction for 32 bit values. + * @param [in] addr Pointer to data + * @return value of type uint32_t at (*addr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __LDREXW (volatile uint32_t * addr) +{ + uint32_t result; + + /* Load to start atomic word data manipulation */ + __ASM volatile ("ldl.w [%1], %0" : "=&r" (result) : "r" (addr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief STR Exclusive (32 bit) + * @details Executes a exclusive STR instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STREXW (uint32_t value, volatile uint32_t * addr) +{ + uint32_t result; + + __ASM volatile ( + "stc.w %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (addr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief Rotate Right with Extend (32 bit) + * @details Moves each bit of a bitstring right by one bit. + * The carry input is shifted in at the left end of the bitstring. + * @param [in] value Value to rotate + * @return Rotated value + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __RRX (uint32_t value) +{ + uint32_t result; + + __ASM volatile ( + "stsr 5, r11, 0 \n" /* r11 <- PSW */ + "shr 3, r11 \n" /* r11.bit0 = CY */ + "andi 1, r11, r11 \n" /* r11 = CY (0 or 1) */ + "shl 31, r11 \n" /* r11 = CY << 31 */ + /* Shift operand and inject CY into MSB */ + "mov %1, %0 \n" + "shr 1, %0 \n" /* r10 = value >> 1 */ + "or r11, %0 \n" /* r10 = (CY<<31) | (value>>1) */ + + /* Compute new CY from old LSB of value: newCY_mask = (value & 1) << 3 */ + "mov %1, r12 \n" + "andi 1, r12, r12 \n" /* r12 = old LSB of value (0 or 1) */ + "shl 3, r12 \n" /* r12 = newCY_mask (0x0 or 0x8) */ + + /* Read PSW, clear CY bit, then set according to newCY_mask */ + "stsr 5, r13, 0 \n" /* r13 <- PSW */ + + /* Clear-mask (~0x8) */ + "movhi 0xFFFF, r0, r11 \n" /* r11 = 0xFFFF0000 */ + "ori 0xFFF7, r11, r11 \n" /* r11 = 0xFFFF0000 + 0xFFF7 = 0xFFFFFFF7 */ + "and r11, r13 \n" /* r13 &= ~0x8 (clear PSW.CY) */ + "or r12, r13 \n" /* r13 |= newCY_mask */ + + /* Write PSW back */ + "ldsr r13, 5, 0 \n" /* PSW <- r13 */ + : "=&r" (result) + : "r" (value) + : "memory", "r11", "r12", "r13" + ); + + return result; +} + +/** + * @brief Load-Acquire (8 bit) + * @details Executes a LDAB instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint8_t __LDAB (volatile uint8_t * ptr) +{ + uint8_t result; + + __ASM volatile ( + "ld.bu 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Load-Acquire (16 bit) + * @details Executes a LDAH instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint16_t __LDAH (volatile uint16_t * ptr) +{ + uint16_t result; + + __ASM volatile ( + "ld.hu 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Load-Acquire (32 bit) + * @details Executes a LDA instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __LDA (volatile uint32_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "ld.w 0[%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Store-Release (8 bit) + * @details Executes a STLB instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STLB (uint8_t value, volatile uint8_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.b %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Store-Release (16 bit) + * @details Executes a STLH instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STLH (uint16_t value, volatile uint16_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.h %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Store-Release (32 bit) + * @details Executes a STL instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE void __STL (uint32_t value, volatile uint32_t * ptr) +{ + __ASM volatile ( + "synce \n" + "st.w %0, 0[%1] \n" + : : "r" (value), "r" (ptr) : "memory" + ); +} + +/** + * @brief Load-Acquire Exclusive (8 bit) + * @details Executes a LDAB exclusive instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB (volatile uint8_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.bu [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return (uint8_t) result; +} + +/** + * @brief Load-Acquire Exclusive (16 bit) + * @details Executes a LDAH exclusive instruction for 16 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint16_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH (volatile uint16_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.hu [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return (uint16_t) result; +} + +/** + * @brief Load-Acquire Exclusive (32 bit) + * @details Executes a LDA exclusive instruction for 32 bit values. + * @param [in] ptr Pointer to data + * @return value of type uint32_t at (*ptr) + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __LDAEX (volatile uint32_t * ptr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ( + "ldl.w [%1], %0 \n" + "synce \n" + : "=&r" (result) : "r" (ptr) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief Store-Release Exclusive (8 bit) + * @details Executes a STLB exclusive instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEXB (uint8_t value, volatile uint8_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.h %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief Store-Release Exclusive (16 bit) + * @details Executes a STLH exclusive instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEXH (uint16_t value, volatile uint16_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.b %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief Store-Release Exclusive (32 bit) + * @details Executes a STL exclusive instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STLEX (uint32_t value, volatile uint32_t * ptr) +{ + uint32_t result; + + __ASM volatile ( + "synce \n" + "stc.w %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (ptr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + * @note Keep RH850 function name and ensure identical behavior on RH850. + */ +__STATIC_FORCEINLINE uint32_t __STREXB (uint8_t value, volatile uint8_t * addr) +{ + uint32_t result; + + __ASM volatile ( + "stc.h %2, [%1] \n" + "mov 1, %0 \n" + "xor %2, %0 \n" + : "=&r" (result) : "r" (addr), "r" (value) : "memory", "cc" + ); + + return result; +} + +/********************************************* RH850 INTRINSIC ********************************************************/ + +/* Load Instructions */ + +/** + * @brief Load byte + * @details Executes a LD.B instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type int8_t at (*ptr) + */ +__STATIC_FORCEINLINE int8_t __LDB (volatile int8_t * ptr) +{ + int8_t result; + __ASM volatile ("ld.b 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load byte unsigned + * @details Executes a LD.BU instruction for 8 bit value. + * @param [in] ptr Pointer to data + * @return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDBU (volatile uint8_t * ptr) +{ + uint8_t result; + __ASM volatile ("ld.bu 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load halfword + * @details Executes a LD.H instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type int16_t at (*ptr) + */ +__STATIC_FORCEINLINE int16_t __LDH (volatile int16_t * ptr) +{ + int16_t result; + __ASM volatile ("ld.h 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load halfword unsigned + * @details Executes a LD.HU instruction for 16 bit value. + * @param [in] ptr Pointer to data + * @return value of type int16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDHU (volatile uint16_t * ptr) +{ + uint16_t result; + __ASM volatile ("ld.hu 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load word + * @details Executes a LD.W instruction for 32 bit value. + * @param [in] ptr Pointer to data + * @return value of type int32_t at (*ptr) + */ +__STATIC_FORCEINLINE int32_t __LDW (volatile int32_t * ptr) +{ + int32_t result; + __ASM volatile ("ld.w 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/** + * @brief Load double word + * @details Executes a LD.DW instruction for 64 bit value. + * @param [in] ptr Pointer to data + * @return value of type int64_t at (*ptr) + */ +__STATIC_FORCEINLINE int64_t __LDDW (volatile int64_t * ptr) +{ + int64_t result; + __ASM volatile ("ld.dw 0[%1], %0" : "=&r" (result) : "r" (ptr) : "memory"); + + return result; +} + +/* Store Instructions */ + +/** + * @brief Store byte + * @details Executes a ST.B instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STB (int8_t value, volatile int8_t * ptr) +{ + __ASM volatile ("st.b %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store halfword + * @details Executes a ST.H instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STH (int16_t value, volatile int16_t * ptr) +{ + __ASM volatile ("st.h %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store word + * @details Executes a ST.W instruction for 32 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STW (int32_t value, volatile int32_t * ptr) +{ + __ASM volatile ("st.w %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/** + * @brief Store double word + * @details Executes a ST.DW instruction for 64 bit values. + * @param [in] value Value to store + * @param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STDW (int64_t value, volatile int64_t * ptr) +{ + __ASM volatile ("st.dw %0, 0[%1]" : : "r" (value), "r" (ptr) : "memory"); +} + +/* Multiply Instructions */ + +/** + * @brief Signed 64-bit multiplication high 32 bits + * @details Assigns higher 32 bits of signed 64-bit multiplication result. + * @param [in] a Multiplicand + * @param [in] b Multiplier + * @return High 32 bits of result + */ +__STATIC_FORCEINLINE int32_t __MUL (int32_t a, int32_t b) +{ + int32_t result; + int32_t reg1 = a; + int32_t reg2 = b; + __ASM volatile ("mul %1, %2, %0" : "=r" (result) : "r" (reg1), "r" (reg2) : "memory"); + + return result; +} + +/** + * @brief Unsigned 64-bit multiplication high 32 bits + * @details Assigns higher 32 bits of unsigned 64-bit multiplication result. + * @param [in] a Multiplicand + * @param [in] b Multiplier + * @return High 32 bits of result + */ +__STATIC_FORCEINLINE long __MULU (long a, long b) +{ + long result; + long reg1 = a; + long reg2 = b; + + __ASM volatile ("mulu %1, %2, %0" : "=r" (result) : "r" (reg1), "r" (reg2) : "memory"); + + return result; +} + +/** + * @brief Saturated addition + * @details Performs saturated addition of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated addition + */ +#ifndef __SATADD + #define __SATADD(a, b) __saturated_add((long) a, (long) b) +#endif + +/** + * @brief Saturated subtraction + * @details Performs saturated subtraction of two signed integers. + * @param [in] a First operand + * @param [in] b Second operand + * @return Result of saturated subtraction + */ +#ifndef __SATSUB + #define __SATSUB(a, b) __saturated_sub((long) a, (long) b) +#endif + +/** + * @brief Halfword data byte swap + * @details Swaps bytes within a 16-bit halfword. + * @param [in] value Value to swap + * @return Swapped value + */ +#define __BSH(value) __BSH((long) value) + +/** + * @brief Word data byte swap + * @details Swaps bytes within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +#define __BSW(value) __BSW((long) value) + +#if (RH850_UNSUPPORTED) + +/** + * @brief Signed data conversion from word to byte with saturation + * @details Conversion of signed word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + */ +RH850_UNSUPPORTED __STATIC_FORCEINLINE int8_t __CLIPB (int32_t value) +{ + int8_t result; + __ASM volatile ("clip.b %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Unsigned data conversion from word to byte with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in byte with saturation + */ +__STATIC_FORCEINLINE RH850_UNSUPPORTED uint8_t __CLIPBU (uint32_t value) +{ + uint8_t result; + __ASM volatile ("clip.bu %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Signed data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to byte data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + */ +__STATIC_FORCEINLINE RH850_UNSUPPORTED int16_t __CLIPH (int32_t value) +{ + int16_t result; + __ASM volatile ("clip.h %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Unsigned data conversion from word to halfword with saturation + * @details Conversion of unsigned word data to halfword data with saturation + * @param [in] value Data conversion + * @return Data in haflword with saturation + */ +__STATIC_FORCEINLINE RH850_UNSUPPORTED uint16_t __CLIPHU (uint32_t value) +{ + uint16_t result; + __ASM volatile ("clip.hu %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +#endif /* RH850_UNSUPPORTED */ + +/** + * @brief Halfword swap halfword + * @details Swaps halfwords within a 16-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +__STATIC_FORCEINLINE int16_t __HSH (int16_t value) +{ + int16_t result; + __ASM volatile ("hsh %1, %0" : "=&r" (result) : "r" (value) : "memory"); + + return result; +} + +/** + * @brief Word data halfword swap + * @details Swaps halfwords within a 32-bit word. + * @param [in] value Value to swap + * @return Swapped value + */ +#define __HSW(value) __HSW((long) value) + +/** + * @brief Rotate left + * @param [in] value Value to rotate + * @param [in] bit The specified shift amount + * @return Swapped value + */ +__STATIC_FORCEINLINE int32_t __ROTL (int32_t value, uint8_t bit) +{ + int32_t result; + __ASM volatile ("rotl %1, %2, %0" : "=&r" (result) : "r" (bit), "r" (value) : "memory"); + + return result; +} + +/** + * @brief Bit (0) search from MSB side + * @details Searches for first 0 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH0L(value) __SCH0L((long) value) + +/** + * @brief Bit (0) search from LSB side + * @details Searches for first 0 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH0R(value) __SCH0R((long) value) + +/** + * @brief Bit (1) search from MSB side + * @details Searches for first 1 bit starting from MSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH1L(value) __SCH1L((long) value) + +/** + * @brief Bit (1) search from LSB side + * @details Searches for first 1 bit starting from LSB. + * @param [in] value Value to search + * @return Bit position + */ +#define __SCH1R(value) __SCH1R((long) value) + +/** + * @brief Divide word + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return Quotient = num1/num2 + */ +__STATIC_FORCEINLINE int32_t __DIV (int32_t num1, int32_t num2) +{ + int32_t result; + __ASM volatile ("div %2, %1, %0" : "=&r" (result) : "r" (num1), "r" (num2) : "memory"); + + return result; +} + +/** + * @brief Divide word unsigned + * @param [in] num1 Dividend number + * @param [in] num2 Divisor number + * @return Quotient = num1/num2 + */ +__STATIC_FORCEINLINE uint32_t __DIVU (uint32_t num1, uint32_t num2) +{ + uint32_t result; + __ASM volatile ("divu %2, %1, %0" : "=&r" (result) : "r" (num1), "r" (num2) : "memory"); + + return result; +} + +/** + * @brief Bit clear + * @details Clear bit a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + * @note Default casts are applied to avoid cross‑compiler warnings and errors + */ +__STATIC_FORCEINLINE void __CLR1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "clr1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Bit set + * @details Sets a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +__STATIC_FORCEINLINE void __SET1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "set1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Bit not + * @details Toggles a specific bit in a value. + * @param [in] addr Address + * @param [in] bit Bit position + */ +__STATIC_FORCEINLINE void __NOT1 (volatile uint8_t * addr, uint8_t bit) +{ + __ASM volatile ( + "mov %0, r15 \n" + "not1 %0, [%1] \n" + : : "r" (bit), "r" (addr) : "memory", "r15"); +} + +/** + * @brief Compare and Exchange + * @details Atomic compare and exchange operation. + * @param [in] addr Address + * @param [in] b Compare value + * @param [in] c Exchange value + */ +#define __CAXI(addr, b, c) __CAXI((int *) addr, (int) b, (int) c) + +/** + * @brief Clear Load Link + * @details Clear Load Link which is created by LDL. + */ +__STATIC_FORCEINLINE void __CLL (void) +{ + __ASM volatile ("cll" ::: "memory"); /* Clear Load Link */ +} + +/** + * @brief Disable Interrupts + * @details Executes the DI instruction to disable maskable interrupts. + */ +#define __DI() __disable_interrupt() + +/** + * @brief Enable Interrupts + * @details Executes the EI instruction to enable maskable interrupts. + */ +#define __EI() __enable_interrupt() + +/** + * @brief Return from EI-level trap or interrupt + */ +#define __EIRET() __ASM volatile ("eiret") + +/** + * @brief Return from FE-level trap or interrupt + */ +#define __FERET() __ASM volatile ("feret") + +/** + * @brief FE-level trap + */ +#define __FETRAP(vector) __ASM volatile ("fetrap " #vector) + +/** + * @brief Load to system register (with selector) + * @details Loads value into system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @param [in] value Value to load + */ +#define __LDSR(regID, selID, value) __LDSR((int) regID, (int) selID, (long) value) + +/** + * @brief LDR Exclusive (8 bit) + * @details Executes a exclusive LDR instruction for 8 bit value. + * @param [in] addr Pointer to data + * @return value of type uint8_t at (*addr) + */ +__STATIC_FORCEINLINE uint8_t __LDLBU (volatile uint8_t * addr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ("ldl.bu [%1], %0" : "=&r" (result) : "r" (addr) : "memory"); + + /* Add explicit type cast here */ + return (uint8_t) result; +} + +/** + * @brief LDR Exclusive (16 bit) + * @details Executes a exclusive LDR instruction for 16 bit values. + * @param [in] addr Pointer to data + * @return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDLHU (volatile uint16_t * addr) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ("ldl.hu [%1], %0" : "=&r" (result) : "r" (addr) : "memory"); + + /* Add explicit type cast here */ + return (uint16_t) result; +} + +/** + * @brief Atomic load to system register + * @details Loads a value into a system register atomically. + * @param [in] value Value to load + */ +__STATIC_FORCEINLINE uint32_t __LDLW (volatile uint32_t * value) +{ + uint32_t result; + + /* Load to start atomic byte data manipulation */ + __ASM volatile ("ldl.w [%1], %0" : "=&r" (result) : "r" (value) : "memory"); + + /* Add explicit type cast here */ + return result; +} + +/** + * @brief No Operation + * @details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __no_operation() + +/** + * @brief Restore contexts from register bank + */ +#define __RESBANK() __ASM volatile ("resbank") + +/** + * @brief Snooze + */ +#define __SNOOZE() __snooze() + +/** + * @brief Store contents of system register (with selector) + * @details Stores contents of system register with selector ID. + * @param [in] regID Register ID + * @param [in] selID Selector ID + * @return Register value + */ +#define __STSR(regID, selID) __STSR((int) regID, (int) selID) + +/** + * @brief STR Exclusive (8 bit) + * @details Executes a exclusive STR instruction for 8 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +__STATIC_FORCEINLINE uint8_t __STCB (volatile uint8_t * addr, uint8_t value) +{ + uint32_t result; + + __ASM volatile ( + "stc.h %2, [%1] \n" + "mov %2, %0 \n" + : "=&r" (result) : "r" (addr), "r" (value) : "memory", "cc" + ); + + return (uint8_t) result; +} + +/** + * @brief STR Exclusive (16 bit) + * @details Executes a exclusive STR instruction for 16 bit values. + * @param [in] value Value to store + * @param [in] addr Pointer to location + * @return 0 Function succeeded + * @return 1 Function failed + */ +__STATIC_FORCEINLINE uint16_t __STCH (volatile uint16_t * addr, uint16_t value) +{ + uint32_t result; + + __ASM volatile ( + "stc.b %2, [%1] \n" + "mov %2, %0 \n" + : "=&r" (result) : "r" (addr), "r" (value) : "memory", "cc" + ); + + return (uint16_t) result; +} + +/** + * @brief Store word + * @details Stores a word to memory. + * @param [in] addr Address + * @param [in] value Value + */ +#define __STCW(addr, value) __STC((long *) addr, (long) value) + +/** + * @brief Exception synchronization + * @details Synchronizes exception handling. + */ +#define __SYNCE() __SYNCE() + +/** + * @brief Instruction pipeline synchronization + * @details Synchronizes instruction pipeline. + */ +#define __SYNCI() __SYNCI() + +/** + * @brief Memory synchronization + * @details Synchronizes memory operations. + */ +#define __SYNCM() __SYNCM() + +/** + * @brief Pipeline synchronization + * @details Synchronizes pipeline operations. + */ +#define __SYNCP() __SYNCP() + +/** + * @brief Trap + */ +#define __TRAP(vector) __ASM volatile ("trap " #vector::: "memory") + +/** + * @brief Halt CPU + * @details HALT instruction stops CPU execution until an interrupt or reset occurs. + */ +#define __HALT() __halt() + +/** + * @brief Debug checkpoint + * @details Inserts a debug checkpoint instruction. + */ +#define __DBCP() __DBCP() + +/** + * @brief Debug push + * @details Pushes debug registers. + * @param [in] regID1 First register ID + * @param [in] regID2 Second register ID + */ +#define __DBPUSH(regID1, regID2) __DBPUSH((long) regID1, (long) regID2) + +/** + * @brief Debug tag + * @details Inserts a debug tag instruction. + * @param [in] a Tag value + */ +#define __DBTAG(a) __DBTAG(a) + +/** @}*/ /* end of group IAR_RH850_Core_InstructionInterface */ + +/** @}*/ /* end of group RH850_Core_InstructionInterface */ + +/* ########################################## Core Function Access ################################################ */ + +/** @defgroup RH850_Core_FunctionInterface RH850-Core Register Access Functions + * @brief Access to the dedicated core register access function instructions + * @{ + */ + +/** @ingroup RH850_Core_FunctionInterface + * @defgroup IAR_RH850_Core_RegAccFunctions IAR RH850-Core Register Access Functions + * @brief IAR RH850-Core Register Access Functions + * @{ + */ + +/** + * @brief Enable IRQ Interrupts + * @details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __enable_irq() __EI() + +/** + * @brief Disable IRQ Interrupts + * @details Disables IRQ interrupts by setting special-purpose register PRIMASK. + * Can only be executed in Privileged modes. + */ +#define __disable_irq() __DI() + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set EIPC (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIPC (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIPSW (Status save registers when acknowledging EI level exception). + * @details Writes a value to the EIPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIPSW (Status save registers when acknowledging EI level exception). + * @details Reads the current value of the EIPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEPC (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEPC (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEPSW (Status save registers when acknowledging FE level exception). + * @details Writes a value to the FEPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEPSW (Status save registers when acknowledging FE level exception). + * @details Reads the current value of the FEPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set PSW (Program status word). + * @details Writes a value to the PSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get PSW (Program status word). + * @details Reads the current value of the PSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIIC (EI level exception cause). + * @details Writes a value to the EIIC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIIC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIIC (EI level exception cause). + * @details Reads the current value of the EIIC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIIC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEIC (FE level exception cause). + * @details Writes a value to the FEIC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEIC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 14, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEIC (FE level exception cause). + * @details Reads the current value of the FEIC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEIC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 14, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set CTPC (CALLT execution status save register). + * @details Writes a value to the CTPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTPC (CALLT execution status save register). + * @details Reads the current value of the CTPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set CTPSW (CALLT execution status save register). + * @details Writes a value to the CTPSW system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTPSW (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTPSW (CALLT execution status save register). + * @details Reads the current value of the CTPSW system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTPSW (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 0" : "=r" (result)); + + return result; +} + +/* CALLT base pointer */ + +/** + * @brief Set CTBP (CALLT base pointer). + * @details Writes a value to the CTBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_CTBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get CTBP (CALLT base pointer). + * @details Reads the current value of the CTBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_CTBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set SNZCFG (SNOOZE control register). + * @details Writes a value to the SNZCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SNZCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get SNZCFG (SNOOZE control register). + * @details Reads the current value of the SNZCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SNZCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set EIWR (EI level exception working register). + * @details Writes a value to the EIWR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EIWR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get EIWR (EI level exception working register). + * @details Reads the current value of the EIWR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EIWR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FEWR (FE level exception working register). + * @details Writes a value to the FEWR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FEWR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 29, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FEWR (FE level exception working register). + * @details Reads the current value of the FEWR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FEWR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 29, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Get SPID (System protection identifier). + * @details Reads the current value of the SPID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SPID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SPID (System protection identifier). + * @details Writes a value to the SPID system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SPID (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SPIDLIST (List of system protection identifiers that can be specified in SPID). + * @details Reads the current value of the SPIDLIST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SPIDLIST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get RBASE (Reset vector base address). + * @details Reads the current value of the RBASE system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBASE (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set EBASE (Exception handler vector address). + * @details Writes a value to the EBASE system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_EBASE (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get EBASE (Exception handler vector address). + * @details Reads the current value of the EBASE system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_EBASE (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set INTBP (Base address of the interrupt handler “address” table). + * @details Writes a value to the INTBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_INTBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get INTBP (Base address of the interrupt handler “address” table). + * @details Reads the current value of the INTBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_INTBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCTL (CPU control). + * @details Writes a value to the MCTL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCTL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCTL (CPU control). + * @details Reads the current value of the MCTL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCTL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get PID (Processor ID). + * @details Reads the current value of the PID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SVLOCK (Supervisor lock). + * @details Writes a value to the SVLOCK system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SVLOCK (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SVLOCK (Supervisor lock). + * @details Reads the current value of the SVLOCK system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SVLOCK (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SCCFG (SYSCALL operation setting). + * @details Writes a value to the SCCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SCCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SCCFG (SYSCALL operation setting). + * @details Reads the current value of the SCCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SCCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Set SCBP (SYSCALL base pointer). + * @details Writes a value to the SCBP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_SCBP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 1" : : "r" (value) : "memory"); +} + +/** + * @brief Get SCBP (SYSCALL base pointer). + * @details Reads the current value of the SCBP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_SCBP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 1" : "=r" (result)); + + return result; +} + +/** + * @brief Get PEID (Processor element identifier). + * @details Reads the current value of the PEID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PEID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Get BMID (Bus master identifier). + * @details Reads the current value of the BMID system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_BMID (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set MEA (Memory error address). + * @details Writes a value to the MEA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MEA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get MEA (Memory error address). + * @details Reads the current value of the MEA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MEA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set MEI (Memory error information). + * @details Writes a value to the MEI system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MEI (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get MEI (Memory error information). + * @details Reads the current value of the MEI system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MEI (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBCR0 (Register bank control 0). + * @details Writes a value to the RBCR0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBCR0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 15, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBCR0 (Register bank control 0). + * @details Reads the current value of the RBCR0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBCR0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 15, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBCR1 (Register bank control 1). + * @details Writes a value to the RBCR1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBCR1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBCR1 (Register bank control 1). + * @details Reads the current value of the RBCR1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBCR1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBNR (Register bank number). + * @details Writes a value to the RBNR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBNR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBNR (Register bank number). + * @details Reads the current value of the RBNR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBNR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set RBIP (Register bank initial pointer). + * @details Writes a value to the RBIP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RBIP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 18, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get RBIP (Register bank initial pointer). + * @details Reads the current value of the RBIP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RBIP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 18, %0, 2" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Interrupt Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ISPR (Priority of interrupt being serviced). + * @details Writes a value to the ISPR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ISPR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get ISPR (Priority of interrupt being serviced). + * @details Reads the current value of the ISPR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ISPR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 2" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IMSR (Interrupt mask status). + * @details Reads the current value of the IMSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_IMSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 2" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Get ICSR (Interrupt control status). + * @details Reads the current value of the ICSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set INTCFG (Interrupt function setting). + * @details Writes a value to the INTCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_INTCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get INTCFG (Interrupt function setting). + * @details Reads the current value of the INTCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_INTCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 2" : "=r" (result)); + + return result; +} + +/** + * @brief Set PLMR (Interrupt priority masking). + * @details Writes a value to the PLMR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PLMR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 14, 2" : : "r" (value) : "memory"); +} + +/** + * @brief Get PLMR (Interrupt priority masking). + * @details Reads the current value of the PLMR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PLMR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 14, %0, 2" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * FPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FPSR (Floating-point operation configuration/status). + * @details Writes a value to the FPSR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPSR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPSR (Floating-point operation configuration/status). + * @details Reads the current value of the FPSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPEPC (Floating-point operation exception program counter). + * @details Writes a value to the FPEPC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPEPC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPEPC (Floating-point operation exception program counter). + * @details Reads the current value of the FPEPC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPEPC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPST (Floating point operation status). + * @details Writes a value to the FPST system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPST (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPST (Floating point operation status). + * @details Reads the current value of the FPST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPCC (Floating-point operation comparison result). + * @details Writes a value to the FPCC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPCC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 9, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPCC (Floating-point operation comparison result). + * @details Reads the current value of the FPCC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPCC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 0" : "=r" (result)); + + return result; +} + +/** + * @brief Set FPCFG (Floating-point operation configuration). + * @details Writes a value to the FPCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPCFG (Floating-point operation configuration). + * @details Reads the current value of the FPCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 0" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4KH) && (__RH850_G4KH == 1) + +/** + * @brief Set FPEC (Floating-point exception control). + * @details Writes a value to the FPEC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FPEC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 0" : : "r" (value) : "memory"); +} + +/** + * @brief Get FPEC (Floating-point exception control). + * @details Reads the current value of the FPEC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FPEC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 0" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4KH) && (__RH850_G4KH == 1) */ + +/*********************************************************************************************************************** + * FXU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set FXSR (Extended floating-point operation configuration/status). + * @details Writes a value to the FXSR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXSR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXSR (Extended floating-point operation configuration/status). + * @details Reads the current value of the FXSR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXSR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Set FXST (Extended floating-point operation status). + * @details Writes a value to the FXST system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXST (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXST (Extended floating-point operation status). + * @details Reads the current value of the FXST system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXST (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Get FXINFO (FXU configuration information). + * @details Reads the current value of the FXINFO system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXINFO (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 10" : "=r" (result)); + + return result; +} + +/* Extended floating-point operation configuration */ + +/** + * @brief Set FXCFG (Extended floating-point operation configuration). + * @details Writes a value to the FXCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXCFG (Extended floating-point operation configuration). + * @details Reads the current value of the FXCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 10" : "=r" (result)); + + return result; +} + +/* XC (cause) bits for each operation way */ + +/** + * @brief Set FXXC (XC (cause) bits for each operation way). + * @details Writes a value to the FXXC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXXC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXXC (XC (cause) bits for each operation way). + * @details Reads the current value of the FXXC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXXC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 10" : "=r" (result)); + + return result; +} + +/** + * @brief Set FXXP (XP (preservation) bits for each operation way). + * @details Writes a value to the FXXP system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_FXXP (uint32_t value) +{ + __ASM volatile ("ldsr %0, 13, 10" : : "r" (value) : "memory"); +} + +/** + * @brief Get FXXP (XP (preservation) bits for each operation way). + * @details Reads the current value of the FXXP system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_FXXP (void) +{ + uint32_t result; + + __ASM volatile ("stsr 13, %0, 10" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * MPU Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set MPM (Memory protection operation mode setting). + * @details Writes a value to the MPM system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPM (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPM (Memory protection operation mode setting). + * @details Reads the current value of the MPM system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPM (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Get MPCFG (MPU configuration). + * @details Reads the current value of the MPCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCA (Memory protection setting check address). + * @details Writes a value to the MCA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCA (Memory protection setting check address). + * @details Reads the current value of the MCA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCS (Memory protection setting check size). + * @details Writes a value to the MCS system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCS (uint32_t value) +{ + __ASM volatile ("ldsr %0, 9, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCS (Memory protection setting check size). + * @details Reads the current value of the MCS system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCS (void) +{ + uint32_t result; + + __ASM volatile ("stsr 9, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCC (Memory protection setting check command). + * @details Writes a value to the MCC system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCC (uint32_t value) +{ + __ASM volatile ("ldsr %0, 10, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCC (Memory protection setting check command). + * @details Reads the current value of the MCC system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCC (void) +{ + uint32_t result; + + __ASM volatile ("stsr 10, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCR (Memory protection setting check result). + * @details Writes a value to the MCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 11, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCR (Memory protection setting check result). + * @details Reads the current value of the MCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 11, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MCI (Memory protection setting check SPID). + * @details Writes a value to the MCI system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MCI (uint32_t value) +{ + __ASM volatile ("ldsr %0, 12, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MCI (Memory protection setting check SPID). + * @details Reads the current value of the MCI system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MCI (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPIDX (Index of memory protection setting registers to be accessed). + * @details Writes a value to the MPIDX system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPIDX (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPIDX (Index of memory protection setting registers to be accessed). + * @details Reads the current value of the MPIDX system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDX (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPBK (MPU Bank Setting). + * @details Writes a value to the MPBK system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPBK (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPBK (MPU Bank Setting). + * @details Reads the current value of the MPBK system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPBK (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPLA (Protection area minimum address). + * @details Writes a value to the MPLA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPLA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPLA (Protection area minimum address). + * @details Reads the current value of the MPLA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPLA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPUA (Protection area maximum address). + * @details Writes a value to the MPUA system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPUA (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPUA (Protection area maximum address). + * @details Reads the current value of the MPUA system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPUA (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPAT (Protection area attribute). + * @details Writes a value to the MPAT system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPAT (uint32_t value) +{ + __ASM volatile ("ldsr %0, 22, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPAT (Protection area attribute). + * @details Reads the current value of the MPAT system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPAT (void) +{ + uint32_t result; + + __ASM volatile ("stsr 22, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID0 (SPID which can access protection area). + * @details Writes a value to the MPID0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID0 (SPID which can access protection area). + * @details Reads the current value of the MPID0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID1 (SPID which can access protection area). + * @details Writes a value to the MPID1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 25, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID1 (SPID which can access protection area). + * @details Reads the current value of the MPID1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 25, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID2 (SPID which can access protection area). + * @details Writes a value to the MPID2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID2 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 26, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID2 (SPID which can access protection area). + * @details Reads the current value of the MPID2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID2 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 26, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID3 (SPID which can access protection area). + * @details Writes a value to the MPID3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID3 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 27, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID3 (SPID which can access protection area). + * @details Reads the current value of the MPID3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID3 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 27, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID4 (SPID which can access protection area). + * @details Writes a value to the MPID4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID4 (SPID which can access protection area). + * @details Reads the current value of the MPID4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID5 (SPID which can access protection area). + * @details Writes a value to the MPID5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 29, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID5 (SPID which can access protection area). + * @details Reads the current value of the MPID5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 29, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID6 (SPID which can access protection area). + * @details Writes a value to the MPID6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 30, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID6 (SPID which can access protection area). + * @details Reads the current value of the MPID6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 30, %0, 5" : "=r" (result)); + + return result; +} + +/** + * @brief Set MPID7 (SPID which can access protection area). + * @details Writes a value to the MPID7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_MPID7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 31, 5" : : "r" (value) : "memory"); +} + +/** + * @brief Get MPID7 (SPID which can access protection area). + * @details Reads the current value of the MPID7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_MPID7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 31, %0, 5" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Cache Operation Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set ICTAGL (Instruction cache tag Lo access). + * @details Writes a value to the ICTAGL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICTAGL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICTAGL (Instruction cache tag Lo access). + * @details Reads the current value of the ICTAGL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICTAGL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICTAGH (Instruction cache tag Hi access). + * @details Writes a value to the ICTAGH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICTAGH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 17, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICTAGH (Instruction cache tag Hi access). + * @details Reads the current value of the ICTAGH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICTAGH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 17, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICDATL (Instruction cache data Lo access). + * @details Writes a value to the ICDATL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICDATL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 18, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICDATL (Instruction cache data Lo access). + * @details Reads the current value of the ICDATL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICDATL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 18, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICDATH (Instruction cache data Hi access). + * @details Writes a value to the ICDATH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICDATH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 19, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICDATH (Instruction cache data Hi access). + * @details Reads the current value of the ICDATH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICDATH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 19, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICCTRL (Instruction cache control). + * @details Writes a value to the ICCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICCTRL (Instruction cache control). + * @details Reads the current value of the ICCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Get ICCFG (Instruction cache configuration). + * @details Reads the current value of the ICCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 26, %0, 4" : "=r" (result)); + + return result; +} + +/** + * @brief Set ICERR (Instruction cache error). + * @details Writes a value to the ICERR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_ICERR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 28, 4" : : "r" (value) : "memory"); +} + +/** + * @brief Get ICERR (Instruction cache error). + * @details Reads the current value of the ICERR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_ICERR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 28, %0, 4" : "=r" (result)); + + return result; +} + +/*********************************************************************************************************************** + * Basic System Registers + **********************************************************************************************************************/ + +/** + * @brief Set TSCOUNTL (Timestamp count L register). + * @details Writes a value to the TSCOUNTL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCOUNTL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCOUNTL (Timestamp count L register). + * @details Reads the current value of the TSCOUNTL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCOUNTL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set TSCOUNTH (Timestamp count H register). + * @details Writes a value to the TSCOUNTH system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCOUNTH (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCOUNTH (Timestamp count H register). + * @details Reads the current value of the TSCOUNTH system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCOUNTH (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set TSCTRL (Timestamp count control register). + * @details Writes a value to the TSCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_TSCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get TSCTRL (Timestamp count control register). + * @details Reads the current value of the TSCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_TSCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set PMUMCTRL (Performance counter User mode control register). + * @details Writes a value to the PMUMCTRL system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMUMCTRL (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 11" : : "r" (value) : "memory"); +} + +/** + * @brief Get PMUMCTRL (Performance counter User mode control register). + * @details Reads the current value of the PMUMCTRL system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMUMCTRL (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 11" : "=r" (result)); + + return result; +} + +/** + * @brief Set PMCTRL0 (Performance count control 0 register). + * @details Writes a value to the PMCTRL0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 0, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 17, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL0 (Performance count control 0 register). + * @details Reads the current value of the PMCTRL0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL0 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 0, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 17, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL1 (Performance count control 1 register). + * @details Writes a value to the PMCTRL1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 1, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 19, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL1 (Performance count control 1 register). + * @details Reads the current value of the PMCTRL1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL1 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 1, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 19, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL2 (Performance count control 2 register). + * @details Writes a value to the PMCTRL2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 2, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 21, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL2 (Performance count control 2 register). + * @details Reads the current value of the PMCTRL2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL2 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 2, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 21, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCTRL3 (Performance count control 3 register). + * @details Writes a value to the PMCTRL3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 3, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 23, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCTRL3 (Performance count control 3 register). + * @details Reads the current value of the PMCTRL3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL3 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 3, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 23, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL4 (Performance count control 4 register). + * @details Writes a value to the PMCTRL4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL4- (Performance count control 4 register). + * @details Reads the current value of the PMCTRL4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL5 (Performance count control 5 register). + * @details Writes a value to the PMCTRL5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL5 (Performance count control 5 register). + * @details Reads the current value of the PMCTRL5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL6 (Performance count control 6 register). + * @details Writes a value to the PMCTRL6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL6 (Performance count control 6 register). + * @details Reads the current value of the PMCTRL6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCTRL7 (Performance count control 7 register). + * @details Writes a value to the PMCTRL7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCTRL7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCTRL7 (Performance count control 7 register). + * @details Reads the current value of the PMCTRL7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCTRL7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** + * @brief Set PMCOUNT0 (Performance count 0 register). + * @details Writes a value to the PMCOUNT0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT0 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 16, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 16, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT0 (Performance count 0 register). + * @details Reads the current value of the PMCOUNT0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT0 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 16, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 16, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT1 (Performance count 1 register). + * @details Writes a value to the PMCOUNT1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT1 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 17, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 18, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT1 (Performance count 1 register). + * @details Reads the current value of the PMCOUNT1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT1 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 17, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 18, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT2 (Performance count 2 register). + * @details Writes a value to the PMCOUNT2 system register. + * @param[in] value uint32_t input. + */ + +/* Performance count 2 register */ +__STATIC_FORCEINLINE void __set_PMCOUNT2 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 18, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 20, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT2 (Performance count 2 register). + * @details Reads the current value of the PMCOUNT2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT2 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 18, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 20, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +/** + * @brief Set PMCOUNT3 (Performance count 3 register). + * @details Writes a value to the PMCOUNT3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT3 (uint32_t value) +{ +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("ldsr %0, 19, 14" : : "r" (value) : "memory"); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("ldsr %0, 22, 11" : : "r" (value) : "memory"); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ +} + +/** + * @brief Get PMCOUNT3 (Performance count 3 register). + * @details Reads the current value of the PMCOUNT3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT3 (void) +{ + uint32_t result; + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + __ASM volatile ("stsr 19, %0, 14" : "=r" (result)); +#elif defined(__RH850_G4KH) && (__RH850_G4KH == 1) + __ASM volatile ("stsr 22, %0, 11" : "=r" (result)); +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT4 (Performance count 4 register). + * @details Writes a value to the PMCOUNT4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 20, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT4 (Performance count 4 register). + * @details Reads the current value of the PMCOUNT4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 20, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT5 (Performance count 5 register). + * @details Writes a value to the PMCOUNT5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 21, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT5 (Performance count 5 register). + * @details Reads the current value of the PMCOUNT5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 21, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT6 (Performance count 6 register). + * @details Writes a value to the PMCOUNT6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 22, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT6 (Performance count 6 register). + * @details Reads the current value of the PMCOUNT6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 22, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMCOUNT7 (Performance count 7 register). + * @details Writes a value to the PMCOUNT7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMCOUNT7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 23, 14" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMCOUNT7 (Performance count 7 register). + * @details Reads the current value of the PMCOUNT7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMCOUNT7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 23, %0, 14" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND0 (Performance count subcondition 0 register). + * @details Writes a value to the PMSUBCND0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND0 (Performance count subcondition 0 register). + * @details Reads the current value of the PMSUBCND0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND1 (Performance count subcondition 1 register). + * @details Writes a value to the PMSUBCND1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND1 (Performance count subcondition 1 register). + * @details Reads the current value of the PMSUBCND1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND2 (Performance count subcondition 2 register). + * @details Writes a value to the PMSUBCND2 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND2 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 2, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND2 (Performance count subcondition 2 register). + * @details Reads the current value of the PMSUBCND2 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND2 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND3 (Performance count subcondition 3 register). + * @details Writes a value to the PMSUBCND3 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND3 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 3, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND3 (Performance count subcondition 3 register). + * @details Reads the current value of the PMSUBCND3 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND3 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 3, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND4 (Performance count subcondition 4 register). + * @details Writes a value to the PMSUBCND4 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND4 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 4, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND4 (Performance count subcondition 4 register). + * @details Reads the current value of the PMSUBCND4 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND4 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 4, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND5 (Performance count subcondition 5 register). + * @details Writes a value to the PMSUBCND5 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND5 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 15" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND5 (Performance count subcondition 5 register). + * @details Reads the current value of the PMSUBCND5 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND5 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 15" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND6 (Performance count subcondition 6 register). + * @details Writes a value to the PMSUBCND6 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND6 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 6, 15 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND6 (Performance count subcondition 6 register). + * @details Reads the current value of the PMSUBCND6 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND6 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 6, %0, 15 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set PMSUBCND7 (Performance count subcondition 7 register). + * @details Writes a value to the PMSUBCND7 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_PMSUBCND7 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 7, 15 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get PMSUBCND7 (Performance count subcondition 7 register). + * @details Reads the current value of the PMSUBCND7 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_PMSUBCND7 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 7, %0, 15 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Hardware Function Registers + **********************************************************************************************************************/ + +/** + * @brief Set LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Writes a value to the LSTEST0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_LSTEST0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 0, 12 \n" : : "r" (value) : "memory"); +} + +/** + * @brief Get LSTEST0 (Lock-step function self-diagnosis register 0). + * @details Reads the current value of the LSTEST0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSTEST0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 0, %0, 12 \n" : "=r" (result)); + + return result; +} + +/** + * @brief Set LSTEST1- (Lock-step function self-diagnosis register 1). + * @details Writes a value to the LSTEST1 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_LSTEST1 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 1, 12 \n" : : "r" (value) : "memory"); +} + +/** + * @brief Get LSTEST1 (Lock-step function self-diagnosis register 1). + * @details Reads the current value of the LSTEST1 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSTEST1 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 1, %0, 12 \n" : "=r" (result)); + + return result; +} + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get LSCFG (Lock-step function configuration). + * @details Reads the current value of the LSCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_LSCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 2, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set IFCR (Instruction fetch control register). + * @details Writes a value to the IFCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_IFCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 5, 12 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get IFCR (Instruction fetch control register). + * @details Reads the current value of the IFCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_IFCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 5, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set BRPCTRL0 (Branch prediction function control register). + * @details Writes a value to the BRPCTRL0 system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_BRPCTRL0 (uint32_t value) +{ + __ASM volatile ("ldsr %0, 8, 12 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get BRPCTRL0 (Branch prediction function control register). + * @details Reads the current value of the BRPCTRL0 system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_BRPCTRL0 (void) +{ + uint32_t result; + + __ASM volatile ("stsr 8, %0, 12 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get L1RCFG (L1RAM configuration). + * @details Reads the current value of the L1RCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_L1RCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 12, %0, 13 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set RDBCR (ROM data buffer control register). + * @details Writes a value to the RDBCR system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_RDBCR (uint32_t value) +{ + __ASM volatile ("ldsr %0, 24, 13 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get RDBCR (ROM data buffer control register). + * @details Reads the current value of the RDBCR system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_RDBCR (void) +{ + uint32_t result; + + __ASM volatile ("stsr 24, %0, 13 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/*********************************************************************************************************************** + * Virtualization Support Function System Registers + **********************************************************************************************************************/ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Set HVCFG (Setting virtualization support function). + * @details Writes a value to the HVCFG system register. + * @param[in] value uint32_t input. + */ +__STATIC_FORCEINLINE void __set_HVCFG (uint32_t value) +{ + __ASM volatile ("ldsr %0, 16, 1 \n" : : "r" (value) : "memory"); +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +#if defined(__RH850_G4MH) && (__RH850_G4MH == 1) + +/** + * @brief Get HVCFG (Setting virtualization support function). + * @details Reads the current value of the HVCFG system register. + * @return uint32_t register value. + * + */ +__STATIC_FORCEINLINE uint32_t __get_HVCFG (void) +{ + uint32_t result; + + __ASM volatile ("stsr 16, %0, 1 \n" : "=r" (result)); + + return result; +} + +#endif /* #if defined(__RH850_G4MH) && (__RH850_G4MH == 1) */ + +/** @} end of group IAR_RH850_Core_RegAccFunctions */ + +/** @} end of group RH850_Core_FunctionInterface */ + +// Include the profile specific settings: +#include "G4-profile/rh850_iar_g4.h" + +#endif /* __RH850_IAR_H */ diff --git a/arch/rh850/src/g4x/Core/Include/rh850_version.h b/arch/rh850/src/g4x/Core/Include/rh850_version.h new file mode 100644 index 0000000000000000000000000000000000000000..ec391a2f2cb080cdc654b1ffccebc402f3060abc --- /dev/null +++ b/arch/rh850/src/g4x/Core/Include/rh850_version.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/**************************************************************************//** + * @file rh850_version.h + * @brief RH850 Core Version Definitions + * @version V0.0.1 + * @date 01. Jan 2026 + ******************************************************************************/ + +/* + * RH850-Core Version Definitions + */ + +#ifndef __RH850_VERSION_H +#define __RH850_VERSION_H + +/* RH850-G4 Version definitions */ +#define __G4_RH850_VERSION_MAIN (1U) /*!< [31:16] RH850-G4 main version */ +#define __G4_RH850_VERSION_SUB (0U) /*!< [15:0] RH850-G4 sub version */ +#define __G4_RH850_VERSION ((__G4_RH850_VERSION_MAIN << 16U) | \ + __G4_RH850_VERSION_SUB) /*!< RH850 G4 version number */ +#endif diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Config/Device_common.h b/arch/rh850/src/g4x/Core/Template/RH850/Config/Device_common.h new file mode 100644 index 0000000000000000000000000000000000000000..612408fdde8172adb25d940cb3fc6511745b7569 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Config/Device_common.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file Device_common.h + * @brief Provides common definitions and declarations for the RH850 G4 environment. + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef DEVICE_COMMON + #define DEVICE_COMMON + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + #include "Device.h" + #include "memory_regions.h" + +// #define BSP_CFG_STACK_MAIN_BYTES 0x1000 +// #define BSP_INTC_INTBP_MAX_ENTRIES 1024 +// #define BSP_CFG_HEAP_SIZE_BYTES 1024 + +#define __GHS__ 1 + +/* This is the value used to mark the stack for subsequent stack monitoring + * logic. + */ + +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + + #if defined(__CCRH__) + +/* Create the pragma inline statement with the function name as argument */ + #define BSP_PRAGMA_SECTION_DEFAULT default + #define BSP_PRAGMA_SECTION_INTVECT_PE0 .inttable_PE0 + #define BSP_PRAGMA_SECTION_INTVECT_PE1 .inttable_PE1 + + #define BSP_PRAGMA_SECTION_DATA + #define BSP_PRAGMA_SECTION_ROM_DATA + #define BSP_PRAGMA_SECTION_BSS + #define BSP_PRAGMA_SECTION_TEXT + + #define BSP_INTERRUPT_ATTRIBUTE ///< Interrupt attribute placeholder for CCRH + + #elif defined(__ghs__) + +/* Create the pragma inline statement with the function name as argument */ + #define BSP_PRAGMA_SECTION_DEFAULT default + #define BSP_PRAGMA_SECTION_INTVECT_PE0 ".inttable_PE0" + #define BSP_PRAGMA_SECTION_INTVECT_PE1 ".inttable_PE1" + + #define BSP_PRAGMA_SECTION_DATA sdata + #define BSP_PRAGMA_SECTION_ROM_DATA rosdata + #define BSP_PRAGMA_SECTION_BSS sbss + #define BSP_PRAGMA_SECTION_TEXT text + + #define BSP_INTERRUPT_ATTRIBUTE __interrupt ///< Interrupt attribute for GHS compiler + + #elif defined(__ICCRH850__) + #define BSP_PRAGMA_SECTION_DEFAULT "default" + #define BSP_PRAGMA_SECTION_INTVECT_PE0 ".inttable_PE0.data" + #define BSP_PRAGMA_SECTION_INTVECT_PE1 ".inttable_PE1.data" + + #define BSP_PRAGMA_SECTION_DATA default_variable_attributes + #define BSP_PRAGMA_SECTION_ROM_DATA default_variable_attributes + #define BSP_PRAGMA_SECTION_BSS default_variable_attributes + #define BSP_PRAGMA_SECTION_TEXT default_function_attributes + + #define BSP_INTERRUPT_ATTRIBUTE __ei_int __interrupt ///< Interrupt attribute placeholder for IAR + + #endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Include/Device.h b/arch/rh850/src/g4x/Core/Template/RH850/Include/Device.h new file mode 100644 index 0000000000000000000000000000000000000000..76a54df11105635d79c2484e30416aa9b8773dcd --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Include/Device.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +//! [RH850-Device-IO-Header-File] + +/*******************************************************************************************************************//** + * @file .h + * @brief RH850 Device Header File for Device + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup device + * @{ + */ + +#ifndef DEVICE_H + #define DEVICE_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_RH850 + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ============================ Configuration of the RH850 G4MH Processor and Core Peripherals ============================= */ + #if (__RH850_G4MH__) + #define __RH850_G4MH_REV 0x0001U /*!< RH850 G4MH Core Revision */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #if ((defined(RH850U2BX_BUILD) && (RH850U2BX_BUILD == 1)) || (defined(RH850U2BXE_BUILD) && (RH850U2BXE_BUILD == 1))) + #define __FXU_PRESENT 1 /*!< FXU present */ + #endif /* #if ((defined(RH850U2BX_BUILD) && (RH850U2BX_BUILD == 1)) || (defined(RH850U2BXE_BUILD) && (RH850U2BXE_BUILD == 1))) */ + #define __ICACHE_PRESENT 1 /*!< ICACHE prsent */ + #define __IRQ_PRESENT 1 /*!< IRQ prsent */ + #define __MPU_PRESENT 1 /*!< MPU prsent */ + #define __PMU_PRESENT 1 /*!< PMU prsent */ + #define __TSC_PRESENT 1 /*!< TSC prsent */ + #include "core_g4mh.h" + #elif (__RH850_G4KH__) + #define __RH850_G4KH_REV 0x0001U /*!< RH850 G4MH Core Revision */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __ICACHE_PRESENT 1 /*!< ICACHE prsent */ + #define __IRQ_PRESENT 1 /*!< IRQ prsent */ + #define __MPU_PRESENT 1 /*!< MPU prsent */ + #define __PMU_PRESENT 1 /*!< PMU prsent */ + #define __TSC_PRESENT 1 /*!< TSC prsent */ + + #include "core_g4kh.h" + #endif + +/** @} */ /* End of group Configuration_of_RH850 */ + + #include "system_Device.h" /*!< System */ + +/* ======================================== Start of section using anonymous unions ======================================== */ + +/* ToDo: add here your device specific peripheral access structure typedefs + * including bit definitions for Pos/Msk macros + * following is an example for a timer */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_EINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief This section describes the interrupt units. (R_EINT) + */ + +typedef struct /*!< (@ 0xFFC00000) R_EINT Structure */ +{ + union + { + __IOM uint8_t SINTC0; /*!< (@ 0x00000000) SINTR0 to SINTR3 are 8-bit registers used to + * control software interrupts 0 to 3 (SINT0 + * to SINT3).Writing 01H to these registers + * increments the value of the counter; writing + * 00H decrements it. When thevalue of the + * counter for any of these registers is 1 + * or more, the corresponding interrupt from + * amongsoftware interrupts 0 to 3 (SINT0 to + * SINT3) is generated. When reading the value + * from any of theseregisters, the read value + * is the current value of the counter. */ + + struct + { + __IOM uint8_t SINTC : 8; /*!< [7..0] Software Interrupt RequestThis bit generates a software + * interrupt.[Reading operation]The number of SINTn interrupt + * request counts is read out.[Writing operation]Writing 01H: + * Increments the counter.*1Writing 00H: Decrements the counter.*2 */ + } SINTC0_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SINTC1; /*!< (@ 0x00000004) SINTR0 to SINTR3 are 8-bit registers used to + * control software interrupts 0 to 3 (SINT0 + * to SINT3).Writing 01H to these registers + * increments the value of the counter; writing + * 00H decrements it. When thevalue of the + * counter for any of these registers is 1 + * or more, the corresponding interrupt from + * amongsoftware interrupts 0 to 3 (SINT0 to + * SINT3) is generated. When reading the value + * from any of theseregisters, the read value + * is the current value of the counter. */ + + struct + { + __IOM uint8_t SINTC : 8; /*!< [7..0] Software Interrupt RequestThis bit generates a software + * interrupt.[Reading operation]The number of SINTn interrupt + * request counts is read out.[Writing operation]Writing 01H: + * Increments the counter.*1Writing 00H: Decrements the counter.*2 */ + } SINTC1_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t SINTC2; /*!< (@ 0x00000008) SINTR0 to SINTR3 are 8-bit registers used to + * control software interrupts 0 to 3 (SINT0 + * to SINT3).Writing 01H to these registers + * increments the value of the counter; writing + * 00H decrements it. When thevalue of the + * counter for any of these registers is 1 + * or more, the corresponding interrupt from + * amongsoftware interrupts 0 to 3 (SINT0 to + * SINT3) is generated. When reading the value + * from any of theseregisters, the read value + * is the current value of the counter. */ + + struct + { + __IOM uint8_t SINTC : 8; /*!< [7..0] Software Interrupt RequestThis bit generates a software + * interrupt.[Reading operation]The number of SINTn interrupt + * request counts is read out.[Writing operation]Writing 01H: + * Increments the counter.*1Writing 00H: Decrements the counter.*2 */ + } SINTC2_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SINTC3; /*!< (@ 0x0000000C) SINTR0 to SINTR3 are 8-bit registers used to + * control software interrupts 0 to 3 (SINT0 + * to SINT3).Writing 01H to these registers + * increments the value of the counter; writing + * 00H decrements it. When thevalue of the + * counter for any of these registers is 1 + * or more, the corresponding interrupt from + * amongsoftware interrupts 0 to 3 (SINT0 to + * SINT3) is generated. When reading the value + * from any of theseregisters, the read value + * is the current value of the counter. */ + + struct + { + __IOM uint8_t SINTC : 8; /*!< [7..0] Software Interrupt RequestThis bit generates a software + * interrupt.[Reading operation]The number of SINTn interrupt + * request counts is read out.[Writing operation]Writing 01H: + * Increments the counter.*1Writing 00H: Decrements the counter.*2 */ + } SINTC3_b; + }; +} R_EINT_Type; /*!< Size = 13 (0xd) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_EINT_BASE 0xFFC00000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_EINT ((R_EINT_Type *) R_EINT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_EINT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SINTC0 ========================================================= */ + #define R_EINT_SINTC0_SINTC_Pos (0UL) /*!< SINTC (Bit 0) */ + #define R_EINT_SINTC0_SINTC_Msk (0xffUL) /*!< SINTC (Bitfield-Mask: 0xff) */ +/* ======================================================== SINTC1 ========================================================= */ + #define R_EINT_SINTC1_SINTC_Pos (0UL) /*!< SINTC (Bit 0) */ + #define R_EINT_SINTC1_SINTC_Msk (0xffUL) /*!< SINTC (Bitfield-Mask: 0xff) */ +/* ======================================================== SINTC2 ========================================================= */ + #define R_EINT_SINTC2_SINTC_Pos (0UL) /*!< SINTC (Bit 0) */ + #define R_EINT_SINTC2_SINTC_Msk (0xffUL) /*!< SINTC (Bitfield-Mask: 0xff) */ +/* ======================================================== SINTC3 ========================================================= */ + #define R_EINT_SINTC3_SINTC_Pos (0UL) /*!< SINTC (Bit 0) */ + #define R_EINT_SINTC3_SINTC_Msk (0xffUL) /*!< SINTC (Bitfield-Mask: 0xff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* DEVICE_H */ + +/** @} */ /* End of group device */ + +/** @} */ /* End of group Renesas */ + +//! [RH850-Device-IO-Header-File] diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Include/system_Device.h b/arch/rh850/src/g4x/Core/Template/RH850/Include/system_Device.h new file mode 100644 index 0000000000000000000000000000000000000000..a3f58bfc10577c17ac75b78edce0102388f92727 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Include/system_Device.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file system_Device.h + * @brief RH850 System file. + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +#ifndef SYSTEM_DEVICE_H + #define SYSTEM_DEVICE_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE0.c b/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE0.c new file mode 100644 index 0000000000000000000000000000000000000000..db01da86eed5b3b097a91f59aaa26d6f096689bd --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE0.c @@ -0,0 +1,8246 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file Interrupt_VectorTable_PE0.h + * @brief Interrupt vector table for PE0 + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if CONFIG_BSP_FSP_SUPPORT +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif + + +/*********************************************************************************************************************** + * Private functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Dummy ISR. + **********************************************************************************************************************/ +#define INT_PE0_DUMMY_IRQ ((const void (*)(void))Irq_Handler) +#ifndef INT_PE0_DUMMY_IRQ + extern BSP_INTERRUPT_ATTRIBUTE void DummyIsr(void); +#define INT_PE0_DUMMY_IRQ DummyIsr +#else +extern BSP_INTERRUPT_ATTRIBUTE void Irq_Handler(void); + +#endif + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ +#if (BSP_PE0_USED) + #if defined(__ICCRH850__) +typedef void (__cc_version1 __interrupt * VectorTableType)(void); +VectorTableType IntVectors_PE0[BSP_INTC_INTBP_MAX_ENTRIES] __attribute__((section(BSP_PRAGMA_SECTION_INTVECT_PE0))) +__attribute__((__used__)) = + #else +#pragma ghs section data=".inttable_PE0" +const void (* IntVectors_PE0[BSP_INTC_INTBP_MAX_ENTRIES])(void) = + #endif /* #if defined(__ICCRH850__) */ +{ + #if (BSP_INTC_INTBP_MAX_ENTRIES > 0) + #if defined(INT_VECTOR_PE0_IRQ_000) + INT_VECTOR_PE0_IRQ_000, /* EIC0 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1) + #if defined(INT_VECTOR_PE0_IRQ_001) + INT_VECTOR_PE0_IRQ_001, /* EIC1 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 2) + #if defined(INT_VECTOR_PE0_IRQ_002) + INT_VECTOR_PE0_IRQ_002, /* EIC2 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 3) + #if defined(INT_VECTOR_PE0_IRQ_003) + INT_VECTOR_PE0_IRQ_003, /* EIC3 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 4) + #if defined(INT_VECTOR_PE0_IRQ_004) + INT_VECTOR_PE0_IRQ_004, /* EIC4 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 5) + #if defined(INT_VECTOR_PE0_IRQ_005) + INT_VECTOR_PE0_IRQ_005, /* EIC5 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 6) + #if defined(INT_VECTOR_PE0_IRQ_006) + INT_VECTOR_PE0_IRQ_006, /* EIC6 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 7) + #if defined(INT_VECTOR_PE0_IRQ_007) + INT_VECTOR_PE0_IRQ_007, /* EIC7 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 8) + #if defined(INT_VECTOR_PE0_IRQ_008) + INT_VECTOR_PE0_IRQ_008, /* EIC8 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 9) + #if defined(INT_VECTOR_PE0_IRQ_009) + INT_VECTOR_PE0_IRQ_009, /* EIC9 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 10) + #if defined(INT_VECTOR_PE0_IRQ_010) + INT_VECTOR_PE0_IRQ_010, /* EIC10 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 11) + #if defined(INT_VECTOR_PE0_IRQ_011) + INT_VECTOR_PE0_IRQ_011, /* EIC11 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 12) + #if defined(INT_VECTOR_PE0_IRQ_012) + INT_VECTOR_PE0_IRQ_012, /* EIC12 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 13) + #if defined(INT_VECTOR_PE0_IRQ_013) + INT_VECTOR_PE0_IRQ_013, /* EIC13 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 14) + #if defined(INT_VECTOR_PE0_IRQ_014) + INT_VECTOR_PE0_IRQ_014, /* EIC14 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 15) + #if defined(INT_VECTOR_PE0_IRQ_015) + INT_VECTOR_PE0_IRQ_015, /* EIC15 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 16) + #if defined(INT_VECTOR_PE0_IRQ_016) + INT_VECTOR_PE0_IRQ_016, /* EIC16 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 17) + #if defined(INT_VECTOR_PE0_IRQ_017) + INT_VECTOR_PE0_IRQ_017, /* EIC17 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 18) + #if defined(INT_VECTOR_PE0_IRQ_018) + INT_VECTOR_PE0_IRQ_018, /* EIC18 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 19) + #if defined(INT_VECTOR_PE0_IRQ_019) + INT_VECTOR_PE0_IRQ_019, /* EIC19 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 20) + #if defined(INT_VECTOR_PE0_IRQ_020) + INT_VECTOR_PE0_IRQ_020, /* EIC20 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 21) + #if defined(INT_VECTOR_PE0_IRQ_021) + INT_VECTOR_PE0_IRQ_021, /* EIC21 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 22) + #if defined(INT_VECTOR_PE0_IRQ_022) + INT_VECTOR_PE0_IRQ_022, /* EIC22 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 23) + #if defined(INT_VECTOR_PE0_IRQ_023) + INT_VECTOR_PE0_IRQ_023, /* EIC23 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 24) + #if defined(INT_VECTOR_PE0_IRQ_024) + INT_VECTOR_PE0_IRQ_024, /* EIC24 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 25) + #if defined(INT_VECTOR_PE0_IRQ_025) + INT_VECTOR_PE0_IRQ_025, /* EIC25 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 26) + #if defined(INT_VECTOR_PE0_IRQ_026) + INT_VECTOR_PE0_IRQ_026, /* EIC26 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 27) + #if defined(INT_VECTOR_PE0_IRQ_027) + INT_VECTOR_PE0_IRQ_027, /* EIC27 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 28) + #if defined(INT_VECTOR_PE0_IRQ_028) + INT_VECTOR_PE0_IRQ_028, /* EIC28 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 29) + #if defined(INT_VECTOR_PE0_IRQ_029) + INT_VECTOR_PE0_IRQ_029, /* EIC29 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 30) + #if defined(INT_VECTOR_PE0_IRQ_030) + INT_VECTOR_PE0_IRQ_030, /* EIC30 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 31) + #if defined(INT_VECTOR_PE0_IRQ_031) + INT_VECTOR_PE0_IRQ_031, /* EIC31 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 32) + #if defined(INT_VECTOR_PE0_IRQ_032) + INT_VECTOR_PE0_IRQ_032, /* EIC32 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 33) + #if defined(INT_VECTOR_PE0_IRQ_033) + INT_VECTOR_PE0_IRQ_033, /* EIC33 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 34) + #if defined(INT_VECTOR_PE0_IRQ_034) + INT_VECTOR_PE0_IRQ_034, /* EIC34 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 35) + #if defined(INT_VECTOR_PE0_IRQ_035) + INT_VECTOR_PE0_IRQ_035, /* EIC35 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 36) + #if defined(INT_VECTOR_PE0_IRQ_036) + INT_VECTOR_PE0_IRQ_036, /* EIC36 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 37) + #if defined(INT_VECTOR_PE0_IRQ_037) + INT_VECTOR_PE0_IRQ_037, /* EIC37 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 38) + #if defined(INT_VECTOR_PE0_IRQ_038) + INT_VECTOR_PE0_IRQ_038, /* EIC38 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 39) + #if defined(INT_VECTOR_PE0_IRQ_039) + INT_VECTOR_PE0_IRQ_039, /* EIC39 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 40) + #if defined(INT_VECTOR_PE0_IRQ_040) + INT_VECTOR_PE0_IRQ_040, /* EIC40 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 41) + #if defined(INT_VECTOR_PE0_IRQ_041) + INT_VECTOR_PE0_IRQ_041, /* EIC41 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 42) + #if defined(INT_VECTOR_PE0_IRQ_042) + INT_VECTOR_PE0_IRQ_042, /* EIC42 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 43) + #if defined(INT_VECTOR_PE0_IRQ_043) + INT_VECTOR_PE0_IRQ_043, /* EIC43 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 44) + #if defined(INT_VECTOR_PE0_IRQ_044) + INT_VECTOR_PE0_IRQ_044, /* EIC44 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 45) + #if defined(INT_VECTOR_PE0_IRQ_045) + INT_VECTOR_PE0_IRQ_045, /* EIC45 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 46) + #if defined(INT_VECTOR_PE0_IRQ_046) + INT_VECTOR_PE0_IRQ_046, /* EIC46 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 47) + #if defined(INT_VECTOR_PE0_IRQ_047) + INT_VECTOR_PE0_IRQ_047, /* EIC47 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 48) + #if defined(INT_VECTOR_PE0_IRQ_048) + INT_VECTOR_PE0_IRQ_048, /* EIC48 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 49) + #if defined(INT_VECTOR_PE0_IRQ_049) + INT_VECTOR_PE0_IRQ_049, /* EIC49 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 50) + #if defined(INT_VECTOR_PE0_IRQ_050) + INT_VECTOR_PE0_IRQ_050, /* EIC50 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 51) + #if defined(INT_VECTOR_PE0_IRQ_051) + INT_VECTOR_PE0_IRQ_051, /* EIC51 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 52) + #if defined(INT_VECTOR_PE0_IRQ_052) + INT_VECTOR_PE0_IRQ_052, /* EIC52 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 53) + #if defined(INT_VECTOR_PE0_IRQ_053) + INT_VECTOR_PE0_IRQ_053, /* EIC53 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 54) + #if defined(INT_VECTOR_PE0_IRQ_054) + INT_VECTOR_PE0_IRQ_054, /* EIC54 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 55) + #if defined(INT_VECTOR_PE0_IRQ_055) + INT_VECTOR_PE0_IRQ_055, /* EIC55 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 56) + #if defined(INT_VECTOR_PE0_IRQ_056) + INT_VECTOR_PE0_IRQ_056, /* EIC56 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 57) + #if defined(INT_VECTOR_PE0_IRQ_057) + INT_VECTOR_PE0_IRQ_057, /* EIC57 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 58) + #if defined(INT_VECTOR_PE0_IRQ_058) + INT_VECTOR_PE0_IRQ_058, /* EIC58 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 59) + #if defined(INT_VECTOR_PE0_IRQ_059) + INT_VECTOR_PE0_IRQ_059, /* EIC59 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 60) + #if defined(INT_VECTOR_PE0_IRQ_060) + INT_VECTOR_PE0_IRQ_060, /* EIC60 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 61) + #if defined(INT_VECTOR_PE0_IRQ_061) + INT_VECTOR_PE0_IRQ_061, /* EIC61 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 62) + #if defined(INT_VECTOR_PE0_IRQ_062) + INT_VECTOR_PE0_IRQ_062, /* EIC62 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 63) + #if defined(INT_VECTOR_PE0_IRQ_063) + INT_VECTOR_PE0_IRQ_063, /* EIC63 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 64) + #if defined(INT_VECTOR_PE0_IRQ_064) + INT_VECTOR_PE0_IRQ_064, /* EIC64 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 65) + #if defined(INT_VECTOR_PE0_IRQ_065) + INT_VECTOR_PE0_IRQ_065, /* EIC65 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 66) + #if defined(INT_VECTOR_PE0_IRQ_066) + INT_VECTOR_PE0_IRQ_066, /* EIC66 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 67) + #if defined(INT_VECTOR_PE0_IRQ_067) + INT_VECTOR_PE0_IRQ_067, /* EIC67 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 68) + #if defined(INT_VECTOR_PE0_IRQ_068) + INT_VECTOR_PE0_IRQ_068, /* EIC68 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 69) + #if defined(INT_VECTOR_PE0_IRQ_069) + INT_VECTOR_PE0_IRQ_069, /* EIC69 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 70) + #if defined(INT_VECTOR_PE0_IRQ_070) + INT_VECTOR_PE0_IRQ_070, /* EIC70 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 71) + #if defined(INT_VECTOR_PE0_IRQ_071) + INT_VECTOR_PE0_IRQ_071, /* EIC71 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 72) + #if defined(INT_VECTOR_PE0_IRQ_072) + INT_VECTOR_PE0_IRQ_072, /* EIC72 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 73) + #if defined(INT_VECTOR_PE0_IRQ_073) + INT_VECTOR_PE0_IRQ_073, /* EIC73 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 74) + #if defined(INT_VECTOR_PE0_IRQ_074) + INT_VECTOR_PE0_IRQ_074, /* EIC74 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 75) + #if defined(INT_VECTOR_PE0_IRQ_075) + INT_VECTOR_PE0_IRQ_075, /* EIC75 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 76) + #if defined(INT_VECTOR_PE0_IRQ_076) + INT_VECTOR_PE0_IRQ_076, /* EIC76 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 77) + #if defined(INT_VECTOR_PE0_IRQ_077) + INT_VECTOR_PE0_IRQ_077, /* EIC77 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 78) + #if defined(INT_VECTOR_PE0_IRQ_078) + INT_VECTOR_PE0_IRQ_078, /* EIC78 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 79) + #if defined(INT_VECTOR_PE0_IRQ_079) + INT_VECTOR_PE0_IRQ_079, /* EIC79 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 80) + #if defined(INT_VECTOR_PE0_IRQ_080) + INT_VECTOR_PE0_IRQ_080, /* EIC80 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 81) + #if defined(INT_VECTOR_PE0_IRQ_081) + INT_VECTOR_PE0_IRQ_081, /* EIC81 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 82) + #if defined(INT_VECTOR_PE0_IRQ_082) + INT_VECTOR_PE0_IRQ_082, /* EIC82 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 83) + #if defined(INT_VECTOR_PE0_IRQ_083) + INT_VECTOR_PE0_IRQ_083, /* EIC83 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 84) + #if defined(INT_VECTOR_PE0_IRQ_084) + INT_VECTOR_PE0_IRQ_084, /* EIC84 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 85) + #if defined(INT_VECTOR_PE0_IRQ_085) + INT_VECTOR_PE0_IRQ_085, /* EIC85 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 86) + #if defined(INT_VECTOR_PE0_IRQ_086) + INT_VECTOR_PE0_IRQ_086, /* EIC86 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 87) + #if defined(INT_VECTOR_PE0_IRQ_087) + INT_VECTOR_PE0_IRQ_087, /* EIC87 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 88) + #if defined(INT_VECTOR_PE0_IRQ_088) + INT_VECTOR_PE0_IRQ_088, /* EIC88 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 89) + #if defined(INT_VECTOR_PE0_IRQ_089) + INT_VECTOR_PE0_IRQ_089, /* EIC89 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 90) + #if defined(INT_VECTOR_PE0_IRQ_090) + INT_VECTOR_PE0_IRQ_090, /* EIC90 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 91) + #if defined(INT_VECTOR_PE0_IRQ_091) + INT_VECTOR_PE0_IRQ_091, /* EIC91 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 92) + #if defined(INT_VECTOR_PE0_IRQ_092) + INT_VECTOR_PE0_IRQ_092, /* EIC92 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 93) + #if defined(INT_VECTOR_PE0_IRQ_093) + INT_VECTOR_PE0_IRQ_093, /* EIC93 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 94) + #if defined(INT_VECTOR_PE0_IRQ_094) + INT_VECTOR_PE0_IRQ_094, /* EIC94 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 95) + #if defined(INT_VECTOR_PE0_IRQ_095) + INT_VECTOR_PE0_IRQ_095, /* EIC95 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 96) + #if defined(INT_VECTOR_PE0_IRQ_096) + INT_VECTOR_PE0_IRQ_096, /* EIC96 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 97) + #if defined(INT_VECTOR_PE0_IRQ_097) + INT_VECTOR_PE0_IRQ_097, /* EIC97 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 98) + #if defined(INT_VECTOR_PE0_IRQ_098) + INT_VECTOR_PE0_IRQ_098, /* EIC98 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 99) + #if defined(INT_VECTOR_PE0_IRQ_099) + INT_VECTOR_PE0_IRQ_099, /* EIC99 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 100) + #if defined(INT_VECTOR_PE0_IRQ_100) + INT_VECTOR_PE0_IRQ_100, /* EIC100 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 101) + #if defined(INT_VECTOR_PE0_IRQ_101) + INT_VECTOR_PE0_IRQ_101, /* EIC101 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 102) + #if defined(INT_VECTOR_PE0_IRQ_102) + INT_VECTOR_PE0_IRQ_102, /* EIC102 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 103) + #if defined(INT_VECTOR_PE0_IRQ_103) + INT_VECTOR_PE0_IRQ_103, /* EIC103 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 104) + #if defined(INT_VECTOR_PE0_IRQ_104) + INT_VECTOR_PE0_IRQ_104, /* EIC104 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 105) + #if defined(INT_VECTOR_PE0_IRQ_105) + INT_VECTOR_PE0_IRQ_105, /* EIC105 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 106) + #if defined(INT_VECTOR_PE0_IRQ_106) + INT_VECTOR_PE0_IRQ_106, /* EIC106 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 107) + #if defined(INT_VECTOR_PE0_IRQ_107) + INT_VECTOR_PE0_IRQ_107, /* EIC107 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 108) + #if defined(INT_VECTOR_PE0_IRQ_108) + INT_VECTOR_PE0_IRQ_108, /* EIC108 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 109) + #if defined(INT_VECTOR_PE0_IRQ_109) + INT_VECTOR_PE0_IRQ_109, /* EIC109 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 110) + #if defined(INT_VECTOR_PE0_IRQ_110) + INT_VECTOR_PE0_IRQ_110, /* EIC110 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 111) + #if defined(INT_VECTOR_PE0_IRQ_111) + INT_VECTOR_PE0_IRQ_111, /* EIC111 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 112) + #if defined(INT_VECTOR_PE0_IRQ_112) + INT_VECTOR_PE0_IRQ_112, /* EIC112 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 113) + #if defined(INT_VECTOR_PE0_IRQ_113) + INT_VECTOR_PE0_IRQ_113, /* EIC113 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 114) + #if defined(INT_VECTOR_PE0_IRQ_114) + INT_VECTOR_PE0_IRQ_114, /* EIC114 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 115) + #if defined(INT_VECTOR_PE0_IRQ_115) + INT_VECTOR_PE0_IRQ_115, /* EIC115 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 116) + #if defined(INT_VECTOR_PE0_IRQ_116) + INT_VECTOR_PE0_IRQ_116, /* EIC116 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 117) + #if defined(INT_VECTOR_PE0_IRQ_117) + INT_VECTOR_PE0_IRQ_117, /* EIC117 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 118) + #if defined(INT_VECTOR_PE0_IRQ_118) + INT_VECTOR_PE0_IRQ_118, /* EIC118 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 119) + #if defined(INT_VECTOR_PE0_IRQ_119) + INT_VECTOR_PE0_IRQ_119, /* EIC119 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 120) + #if defined(INT_VECTOR_PE0_IRQ_120) + INT_VECTOR_PE0_IRQ_120, /* EIC120 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 121) + #if defined(INT_VECTOR_PE0_IRQ_121) + INT_VECTOR_PE0_IRQ_121, /* EIC121 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 122) + #if defined(INT_VECTOR_PE0_IRQ_122) + INT_VECTOR_PE0_IRQ_122, /* EIC122 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 123) + #if defined(INT_VECTOR_PE0_IRQ_123) + INT_VECTOR_PE0_IRQ_123, /* EIC123 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 124) + #if defined(INT_VECTOR_PE0_IRQ_124) + INT_VECTOR_PE0_IRQ_124, /* EIC124 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 125) + #if defined(INT_VECTOR_PE0_IRQ_125) + INT_VECTOR_PE0_IRQ_125, /* EIC125 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 126) + #if defined(INT_VECTOR_PE0_IRQ_126) + INT_VECTOR_PE0_IRQ_126, /* EIC126 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 127) + #if defined(INT_VECTOR_PE0_IRQ_127) + INT_VECTOR_PE0_IRQ_127, /* EIC127 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 128) + #if defined(INT_VECTOR_PE0_IRQ_128) + INT_VECTOR_PE0_IRQ_128, /* EIC128 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 129) + #if defined(INT_VECTOR_PE0_IRQ_129) + INT_VECTOR_PE0_IRQ_129, /* EIC129 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 130) + #if defined(INT_VECTOR_PE0_IRQ_130) + INT_VECTOR_PE0_IRQ_130, /* EIC130 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 131) + #if defined(INT_VECTOR_PE0_IRQ_131) + INT_VECTOR_PE0_IRQ_131, /* EIC131 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 132) + #if defined(INT_VECTOR_PE0_IRQ_132) + INT_VECTOR_PE0_IRQ_132, /* EIC132 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 133) + #if defined(INT_VECTOR_PE0_IRQ_133) + INT_VECTOR_PE0_IRQ_133, /* EIC133 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 134) + #if defined(INT_VECTOR_PE0_IRQ_134) + INT_VECTOR_PE0_IRQ_134, /* EIC134 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 135) + #if defined(INT_VECTOR_PE0_IRQ_135) + INT_VECTOR_PE0_IRQ_135, /* EIC135 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 136) + #if defined(INT_VECTOR_PE0_IRQ_136) + INT_VECTOR_PE0_IRQ_136, /* EIC136 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 137) + #if defined(INT_VECTOR_PE0_IRQ_137) + INT_VECTOR_PE0_IRQ_137, /* EIC137 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 138) + #if defined(INT_VECTOR_PE0_IRQ_138) + INT_VECTOR_PE0_IRQ_138, /* EIC138 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 139) + #if defined(INT_VECTOR_PE0_IRQ_139) + INT_VECTOR_PE0_IRQ_139, /* EIC139 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 140) + #if defined(INT_VECTOR_PE0_IRQ_140) + INT_VECTOR_PE0_IRQ_140, /* EIC140 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 141) + #if defined(INT_VECTOR_PE0_IRQ_141) + INT_VECTOR_PE0_IRQ_141, /* EIC141 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 142) + #if defined(INT_VECTOR_PE0_IRQ_142) + INT_VECTOR_PE0_IRQ_142, /* EIC142 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 143) + #if defined(INT_VECTOR_PE0_IRQ_143) + INT_VECTOR_PE0_IRQ_143, /* EIC143 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 144) + #if defined(INT_VECTOR_PE0_IRQ_144) + INT_VECTOR_PE0_IRQ_144, /* EIC144 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 145) + #if defined(INT_VECTOR_PE0_IRQ_145) + INT_VECTOR_PE0_IRQ_145, /* EIC145 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 146) + #if defined(INT_VECTOR_PE0_IRQ_146) + INT_VECTOR_PE0_IRQ_146, /* EIC146 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 147) + #if defined(INT_VECTOR_PE0_IRQ_147) + INT_VECTOR_PE0_IRQ_147, /* EIC147 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 148) + #if defined(INT_VECTOR_PE0_IRQ_148) + INT_VECTOR_PE0_IRQ_148, /* EIC148 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 149) + #if defined(INT_VECTOR_PE0_IRQ_149) + INT_VECTOR_PE0_IRQ_149, /* EIC149 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 150) + #if defined(INT_VECTOR_PE0_IRQ_150) + INT_VECTOR_PE0_IRQ_150, /* EIC150 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 151) + #if defined(INT_VECTOR_PE0_IRQ_151) + INT_VECTOR_PE0_IRQ_151, /* EIC151 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 152) + #if defined(INT_VECTOR_PE0_IRQ_152) + INT_VECTOR_PE0_IRQ_152, /* EIC152 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 153) + #if defined(INT_VECTOR_PE0_IRQ_153) + INT_VECTOR_PE0_IRQ_153, /* EIC153 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 154) + #if defined(INT_VECTOR_PE0_IRQ_154) + INT_VECTOR_PE0_IRQ_154, /* EIC154 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 155) + #if defined(INT_VECTOR_PE0_IRQ_155) + INT_VECTOR_PE0_IRQ_155, /* EIC155 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 156) + #if defined(INT_VECTOR_PE0_IRQ_156) + INT_VECTOR_PE0_IRQ_156, /* EIC156 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 157) + #if defined(INT_VECTOR_PE0_IRQ_157) + INT_VECTOR_PE0_IRQ_157, /* EIC157 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 158) + #if defined(INT_VECTOR_PE0_IRQ_158) + INT_VECTOR_PE0_IRQ_158, /* EIC158 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 159) + #if defined(INT_VECTOR_PE0_IRQ_159) + INT_VECTOR_PE0_IRQ_159, /* EIC159 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 160) + #if defined(INT_VECTOR_PE0_IRQ_160) + INT_VECTOR_PE0_IRQ_160, /* EIC160 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 161) + #if defined(INT_VECTOR_PE0_IRQ_161) + INT_VECTOR_PE0_IRQ_161, /* EIC161 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 162) + #if defined(INT_VECTOR_PE0_IRQ_162) + INT_VECTOR_PE0_IRQ_162, /* EIC162 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 163) + #if defined(INT_VECTOR_PE0_IRQ_163) + INT_VECTOR_PE0_IRQ_163, /* EIC163 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 164) + #if defined(INT_VECTOR_PE0_IRQ_164) + INT_VECTOR_PE0_IRQ_164, /* EIC164 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 165) + #if defined(INT_VECTOR_PE0_IRQ_165) + INT_VECTOR_PE0_IRQ_165, /* EIC165 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 166) + #if defined(INT_VECTOR_PE0_IRQ_166) + INT_VECTOR_PE0_IRQ_166, /* EIC166 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 167) + #if defined(INT_VECTOR_PE0_IRQ_167) + INT_VECTOR_PE0_IRQ_167, /* EIC167 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 168) + #if defined(INT_VECTOR_PE0_IRQ_168) + INT_VECTOR_PE0_IRQ_168, /* EIC168 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 169) + #if defined(INT_VECTOR_PE0_IRQ_169) + INT_VECTOR_PE0_IRQ_169, /* EIC169 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 170) + #if defined(INT_VECTOR_PE0_IRQ_170) + INT_VECTOR_PE0_IRQ_170, /* EIC170 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 171) + #if defined(INT_VECTOR_PE0_IRQ_171) + INT_VECTOR_PE0_IRQ_171, /* EIC171 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 172) + #if defined(INT_VECTOR_PE0_IRQ_172) + INT_VECTOR_PE0_IRQ_172, /* EIC172 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 173) + #if defined(INT_VECTOR_PE0_IRQ_173) + INT_VECTOR_PE0_IRQ_173, /* EIC173 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 174) + #if defined(INT_VECTOR_PE0_IRQ_174) + INT_VECTOR_PE0_IRQ_174, /* EIC174 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 175) + #if defined(INT_VECTOR_PE0_IRQ_175) + INT_VECTOR_PE0_IRQ_175, /* EIC175 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 176) + #if defined(INT_VECTOR_PE0_IRQ_176) + INT_VECTOR_PE0_IRQ_176, /* EIC176 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 177) + #if defined(INT_VECTOR_PE0_IRQ_177) + INT_VECTOR_PE0_IRQ_177, /* EIC177 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 178) + #if defined(INT_VECTOR_PE0_IRQ_178) + INT_VECTOR_PE0_IRQ_178, /* EIC178 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 179) + #if defined(INT_VECTOR_PE0_IRQ_179) + INT_VECTOR_PE0_IRQ_179, /* EIC179 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 180) + #if defined(INT_VECTOR_PE0_IRQ_180) + INT_VECTOR_PE0_IRQ_180, /* EIC180 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 181) + #if defined(INT_VECTOR_PE0_IRQ_181) + INT_VECTOR_PE0_IRQ_181, /* EIC181 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 182) + #if defined(INT_VECTOR_PE0_IRQ_182) + INT_VECTOR_PE0_IRQ_182, /* EIC182 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 183) + #if defined(INT_VECTOR_PE0_IRQ_183) + INT_VECTOR_PE0_IRQ_183, /* EIC183 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 184) + #if defined(INT_VECTOR_PE0_IRQ_184) + INT_VECTOR_PE0_IRQ_184, /* EIC184 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 185) + #if defined(INT_VECTOR_PE0_IRQ_185) + INT_VECTOR_PE0_IRQ_185, /* EIC185 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 186) + #if defined(INT_VECTOR_PE0_IRQ_186) + INT_VECTOR_PE0_IRQ_186, /* EIC186 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 187) + #if defined(INT_VECTOR_PE0_IRQ_187) + INT_VECTOR_PE0_IRQ_187, /* EIC187 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 188) + #if defined(INT_VECTOR_PE0_IRQ_188) + INT_VECTOR_PE0_IRQ_188, /* EIC188 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 189) + #if defined(INT_VECTOR_PE0_IRQ_189) + INT_VECTOR_PE0_IRQ_189, /* EIC189 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 190) + #if defined(INT_VECTOR_PE0_IRQ_190) + INT_VECTOR_PE0_IRQ_190, /* EIC190 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 191) + #if defined(INT_VECTOR_PE0_IRQ_191) + INT_VECTOR_PE0_IRQ_191, /* EIC191 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 192) + #if defined(INT_VECTOR_PE0_IRQ_192) + INT_VECTOR_PE0_IRQ_192, /* EIC192 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 193) + #if defined(INT_VECTOR_PE0_IRQ_193) + INT_VECTOR_PE0_IRQ_193, /* EIC193 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 194) + #if defined(INT_VECTOR_PE0_IRQ_194) + INT_VECTOR_PE0_IRQ_194, /* EIC194 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 195) + #if defined(INT_VECTOR_PE0_IRQ_195) + INT_VECTOR_PE0_IRQ_195, /* EIC195 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 196) + #if defined(INT_VECTOR_PE0_IRQ_196) + INT_VECTOR_PE0_IRQ_196, /* EIC196 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 197) + #if defined(INT_VECTOR_PE0_IRQ_197) + INT_VECTOR_PE0_IRQ_197, /* EIC197 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 198) + #if defined(INT_VECTOR_PE0_IRQ_198) + INT_VECTOR_PE0_IRQ_198, /* EIC198 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 199) + #if defined(INT_VECTOR_PE0_IRQ_199) + INT_VECTOR_PE0_IRQ_199, /* EIC199 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 200) + #if defined(INT_VECTOR_PE0_IRQ_200) + INT_VECTOR_PE0_IRQ_200, /* EIC200 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 201) + #if defined(INT_VECTOR_PE0_IRQ_201) + INT_VECTOR_PE0_IRQ_201, /* EIC201 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 202) + #if defined(INT_VECTOR_PE0_IRQ_202) + INT_VECTOR_PE0_IRQ_202, /* EIC202 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 203) + #if defined(INT_VECTOR_PE0_IRQ_203) + INT_VECTOR_PE0_IRQ_203, /* EIC203 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 204) + #if defined(INT_VECTOR_PE0_IRQ_204) + INT_VECTOR_PE0_IRQ_204, /* EIC204 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 205) + #if defined(INT_VECTOR_PE0_IRQ_205) + INT_VECTOR_PE0_IRQ_205, /* EIC205 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 206) + #if defined(INT_VECTOR_PE0_IRQ_206) + INT_VECTOR_PE0_IRQ_206, /* EIC206 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 207) + #if defined(INT_VECTOR_PE0_IRQ_207) + INT_VECTOR_PE0_IRQ_207, /* EIC207 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 208) + #if defined(INT_VECTOR_PE0_IRQ_208) + INT_VECTOR_PE0_IRQ_208, /* EIC208 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 209) + #if defined(INT_VECTOR_PE0_IRQ_209) + INT_VECTOR_PE0_IRQ_209, /* EIC209 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 210) + #if defined(INT_VECTOR_PE0_IRQ_210) + INT_VECTOR_PE0_IRQ_210, /* EIC210 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 211) + #if defined(INT_VECTOR_PE0_IRQ_211) + INT_VECTOR_PE0_IRQ_211, /* EIC211 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 212) + #if defined(INT_VECTOR_PE0_IRQ_212) + INT_VECTOR_PE0_IRQ_212, /* EIC212 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 213) + #if defined(INT_VECTOR_PE0_IRQ_213) + INT_VECTOR_PE0_IRQ_213, /* EIC213 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 214) + #if defined(INT_VECTOR_PE0_IRQ_214) + INT_VECTOR_PE0_IRQ_214, /* EIC214 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 215) + #if defined(INT_VECTOR_PE0_IRQ_215) + INT_VECTOR_PE0_IRQ_215, /* EIC215 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 216) + #if defined(INT_VECTOR_PE0_IRQ_216) + INT_VECTOR_PE0_IRQ_216, /* EIC216 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 217) + #if defined(INT_VECTOR_PE0_IRQ_217) + INT_VECTOR_PE0_IRQ_217, /* EIC217 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 218) + #if defined(INT_VECTOR_PE0_IRQ_218) + INT_VECTOR_PE0_IRQ_218, /* EIC218 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 219) + #if defined(INT_VECTOR_PE0_IRQ_219) + INT_VECTOR_PE0_IRQ_219, /* EIC219 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 220) + #if defined(INT_VECTOR_PE0_IRQ_220) + INT_VECTOR_PE0_IRQ_220, /* EIC220 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 221) + #if defined(INT_VECTOR_PE0_IRQ_221) + INT_VECTOR_PE0_IRQ_221, /* EIC221 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 222) + #if defined(INT_VECTOR_PE0_IRQ_222) + INT_VECTOR_PE0_IRQ_222, /* EIC222 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 223) + #if defined(INT_VECTOR_PE0_IRQ_223) + INT_VECTOR_PE0_IRQ_223, /* EIC223 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 224) + #if defined(INT_VECTOR_PE0_IRQ_224) + INT_VECTOR_PE0_IRQ_224, /* EIC224 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 225) + #if defined(INT_VECTOR_PE0_IRQ_225) + INT_VECTOR_PE0_IRQ_225, /* EIC225 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 226) + #if defined(INT_VECTOR_PE0_IRQ_226) + INT_VECTOR_PE0_IRQ_226, /* EIC226 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 227) + #if defined(INT_VECTOR_PE0_IRQ_227) + INT_VECTOR_PE0_IRQ_227, /* EIC227 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 228) + #if defined(INT_VECTOR_PE0_IRQ_228) + INT_VECTOR_PE0_IRQ_228, /* EIC228 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 229) + #if defined(INT_VECTOR_PE0_IRQ_229) + INT_VECTOR_PE0_IRQ_229, /* EIC229 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 230) + #if defined(INT_VECTOR_PE0_IRQ_230) + INT_VECTOR_PE0_IRQ_230, /* EIC230 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 231) + #if defined(INT_VECTOR_PE0_IRQ_231) + INT_VECTOR_PE0_IRQ_231, /* EIC231 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 232) + #if defined(INT_VECTOR_PE0_IRQ_232) + INT_VECTOR_PE0_IRQ_232, /* EIC232 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 233) + #if defined(INT_VECTOR_PE0_IRQ_233) + INT_VECTOR_PE0_IRQ_233, /* EIC233 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 234) + #if defined(INT_VECTOR_PE0_IRQ_234) + INT_VECTOR_PE0_IRQ_234, /* EIC234 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 235) + #if defined(INT_VECTOR_PE0_IRQ_235) + INT_VECTOR_PE0_IRQ_235, /* EIC235 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 236) + #if defined(INT_VECTOR_PE0_IRQ_236) + INT_VECTOR_PE0_IRQ_236, /* EIC236 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 237) + #if defined(INT_VECTOR_PE0_IRQ_237) + INT_VECTOR_PE0_IRQ_237, /* EIC237 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 238) + #if defined(INT_VECTOR_PE0_IRQ_238) + INT_VECTOR_PE0_IRQ_238, /* EIC238 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 239) + #if defined(INT_VECTOR_PE0_IRQ_239) + INT_VECTOR_PE0_IRQ_239, /* EIC239 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 240) + #if defined(INT_VECTOR_PE0_IRQ_240) + INT_VECTOR_PE0_IRQ_240, /* EIC240 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 241) + #if defined(INT_VECTOR_PE0_IRQ_241) + INT_VECTOR_PE0_IRQ_241, /* EIC241 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 242) + #if defined(INT_VECTOR_PE0_IRQ_242) + INT_VECTOR_PE0_IRQ_242, /* EIC242 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 243) + #if defined(INT_VECTOR_PE0_IRQ_243) + INT_VECTOR_PE0_IRQ_243, /* EIC243 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 244) + #if defined(INT_VECTOR_PE0_IRQ_244) + INT_VECTOR_PE0_IRQ_244, /* EIC244 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 245) + #if defined(INT_VECTOR_PE0_IRQ_245) + INT_VECTOR_PE0_IRQ_245, /* EIC245 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 246) + #if defined(INT_VECTOR_PE0_IRQ_246) + INT_VECTOR_PE0_IRQ_246, /* EIC246 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 247) + #if defined(INT_VECTOR_PE0_IRQ_247) + INT_VECTOR_PE0_IRQ_247, /* EIC247 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 248) + #if defined(INT_VECTOR_PE0_IRQ_248) + INT_VECTOR_PE0_IRQ_248, /* EIC248 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 249) + #if defined(INT_VECTOR_PE0_IRQ_249) + INT_VECTOR_PE0_IRQ_249, /* EIC249 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 250) + #if defined(INT_VECTOR_PE0_IRQ_250) + INT_VECTOR_PE0_IRQ_250, /* EIC250 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 251) + #if defined(INT_VECTOR_PE0_IRQ_251) + INT_VECTOR_PE0_IRQ_251, /* EIC251 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 252) + #if defined(INT_VECTOR_PE0_IRQ_252) + INT_VECTOR_PE0_IRQ_252, /* EIC252 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 253) + #if defined(INT_VECTOR_PE0_IRQ_253) + INT_VECTOR_PE0_IRQ_253, /* EIC253 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 254) + #if defined(INT_VECTOR_PE0_IRQ_254) + INT_VECTOR_PE0_IRQ_254, /* EIC254 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 255) + #if defined(INT_VECTOR_PE0_IRQ_255) + INT_VECTOR_PE0_IRQ_255, /* EIC255 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 256) + #if defined(INT_VECTOR_PE0_IRQ_256) + INT_VECTOR_PE0_IRQ_256, /* EIC256 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 257) + #if defined(INT_VECTOR_PE0_IRQ_257) + INT_VECTOR_PE0_IRQ_257, /* EIC257 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 258) + #if defined(INT_VECTOR_PE0_IRQ_258) + INT_VECTOR_PE0_IRQ_258, /* EIC258 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 259) + #if defined(INT_VECTOR_PE0_IRQ_259) + INT_VECTOR_PE0_IRQ_259, /* EIC259 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 260) + #if defined(INT_VECTOR_PE0_IRQ_260) + INT_VECTOR_PE0_IRQ_260, /* EIC260 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 261) + #if defined(INT_VECTOR_PE0_IRQ_261) + INT_VECTOR_PE0_IRQ_261, /* EIC261 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 262) + #if defined(INT_VECTOR_PE0_IRQ_262) + INT_VECTOR_PE0_IRQ_262, /* EIC262 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 263) + #if defined(INT_VECTOR_PE0_IRQ_263) + INT_VECTOR_PE0_IRQ_263, /* EIC263 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 264) + #if defined(INT_VECTOR_PE0_IRQ_264) + INT_VECTOR_PE0_IRQ_264, /* EIC264 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 265) + #if defined(INT_VECTOR_PE0_IRQ_265) + INT_VECTOR_PE0_IRQ_265, /* EIC265 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 266) + #if defined(INT_VECTOR_PE0_IRQ_266) + INT_VECTOR_PE0_IRQ_266, /* EIC266 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 267) + #if defined(INT_VECTOR_PE0_IRQ_267) + INT_VECTOR_PE0_IRQ_267, /* EIC267 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 268) + #if defined(INT_VECTOR_PE0_IRQ_268) + INT_VECTOR_PE0_IRQ_268, /* EIC268 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 269) + #if defined(INT_VECTOR_PE0_IRQ_269) + INT_VECTOR_PE0_IRQ_269, /* EIC269 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 270) + #if defined(INT_VECTOR_PE0_IRQ_270) + INT_VECTOR_PE0_IRQ_270, /* EIC270 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 271) + #if defined(INT_VECTOR_PE0_IRQ_271) + INT_VECTOR_PE0_IRQ_271, /* EIC271 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 272) + #if defined(INT_VECTOR_PE0_IRQ_272) + INT_VECTOR_PE0_IRQ_272, /* EIC272 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 273) + #if defined(INT_VECTOR_PE0_IRQ_273) + INT_VECTOR_PE0_IRQ_273, /* EIC273 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 274) + #if defined(INT_VECTOR_PE0_IRQ_274) + INT_VECTOR_PE0_IRQ_274, /* EIC274 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 275) + #if defined(INT_VECTOR_PE0_IRQ_275) + INT_VECTOR_PE0_IRQ_275, /* EIC275 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 276) + #if defined(INT_VECTOR_PE0_IRQ_276) + INT_VECTOR_PE0_IRQ_276, /* EIC276 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 277) + #if defined(INT_VECTOR_PE0_IRQ_277) + INT_VECTOR_PE0_IRQ_277, /* EIC277 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 278) + #if defined(INT_VECTOR_PE0_IRQ_278) + INT_VECTOR_PE0_IRQ_278, /* EIC278 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 279) + #if defined(INT_VECTOR_PE0_IRQ_279) + INT_VECTOR_PE0_IRQ_279, /* EIC279 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 280) + #if defined(INT_VECTOR_PE0_IRQ_280) + INT_VECTOR_PE0_IRQ_280, /* EIC280 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 281) + #if defined(INT_VECTOR_PE0_IRQ_281) + INT_VECTOR_PE0_IRQ_281, /* EIC281 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 282) + #if defined(INT_VECTOR_PE0_IRQ_282) + INT_VECTOR_PE0_IRQ_282, /* EIC282 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 283) + #if defined(INT_VECTOR_PE0_IRQ_283) + INT_VECTOR_PE0_IRQ_283, /* EIC283 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 284) + #if defined(INT_VECTOR_PE0_IRQ_284) + INT_VECTOR_PE0_IRQ_284, /* EIC284 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 285) + #if defined(INT_VECTOR_PE0_IRQ_285) + INT_VECTOR_PE0_IRQ_285, /* EIC285 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 286) + #if defined(INT_VECTOR_PE0_IRQ_286) + INT_VECTOR_PE0_IRQ_286, /* EIC286 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 287) + #if defined(INT_VECTOR_PE0_IRQ_287) + INT_VECTOR_PE0_IRQ_287, /* EIC287 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 288) + #if defined(INT_VECTOR_PE0_IRQ_288) + INT_VECTOR_PE0_IRQ_288, /* EIC288 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 289) + #if defined(INT_VECTOR_PE0_IRQ_289) + INT_VECTOR_PE0_IRQ_289, /* EIC289 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 290) + #if defined(INT_VECTOR_PE0_IRQ_290) + INT_VECTOR_PE0_IRQ_290, /* EIC290 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 291) + #if defined(INT_VECTOR_PE0_IRQ_291) + INT_VECTOR_PE0_IRQ_291, /* EIC291 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 292) + #if defined(INT_VECTOR_PE0_IRQ_292) + INT_VECTOR_PE0_IRQ_292, /* EIC292 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 293) + #if defined(INT_VECTOR_PE0_IRQ_293) + INT_VECTOR_PE0_IRQ_293, /* EIC293 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 294) + #if defined(INT_VECTOR_PE0_IRQ_294) + INT_VECTOR_PE0_IRQ_294, /* EIC294 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 295) + #if defined(INT_VECTOR_PE0_IRQ_295) + INT_VECTOR_PE0_IRQ_295, /* EIC295 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 296) + #if defined(INT_VECTOR_PE0_IRQ_296) + INT_VECTOR_PE0_IRQ_296, /* EIC296 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 297) + #if defined(INT_VECTOR_PE0_IRQ_297) + INT_VECTOR_PE0_IRQ_297, /* EIC297 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 298) + #if defined(INT_VECTOR_PE0_IRQ_298) + INT_VECTOR_PE0_IRQ_298, /* EIC298 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 299) + #if defined(INT_VECTOR_PE0_IRQ_299) + INT_VECTOR_PE0_IRQ_299, /* EIC299 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 300) + #if defined(INT_VECTOR_PE0_IRQ_300) + INT_VECTOR_PE0_IRQ_300, /* EIC300 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 301) + #if defined(INT_VECTOR_PE0_IRQ_301) + INT_VECTOR_PE0_IRQ_301, /* EIC301 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 302) + #if defined(INT_VECTOR_PE0_IRQ_302) + INT_VECTOR_PE0_IRQ_302, /* EIC302 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 303) + #if defined(INT_VECTOR_PE0_IRQ_303) + INT_VECTOR_PE0_IRQ_303, /* EIC303 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 304) + #if defined(INT_VECTOR_PE0_IRQ_304) + INT_VECTOR_PE0_IRQ_304, /* EIC304 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 305) + #if defined(INT_VECTOR_PE0_IRQ_305) + INT_VECTOR_PE0_IRQ_305, /* EIC305 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 306) + #if defined(INT_VECTOR_PE0_IRQ_306) + INT_VECTOR_PE0_IRQ_306, /* EIC306 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 307) + #if defined(INT_VECTOR_PE0_IRQ_307) + INT_VECTOR_PE0_IRQ_307, /* EIC307 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 308) + #if defined(INT_VECTOR_PE0_IRQ_308) + INT_VECTOR_PE0_IRQ_308, /* EIC308 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 309) + #if defined(INT_VECTOR_PE0_IRQ_309) + INT_VECTOR_PE0_IRQ_309, /* EIC309 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 310) + #if defined(INT_VECTOR_PE0_IRQ_310) + INT_VECTOR_PE0_IRQ_310, /* EIC310 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 311) + #if defined(INT_VECTOR_PE0_IRQ_311) + INT_VECTOR_PE0_IRQ_311, /* EIC311 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 312) + #if defined(INT_VECTOR_PE0_IRQ_312) + INT_VECTOR_PE0_IRQ_312, /* EIC312 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 313) + #if defined(INT_VECTOR_PE0_IRQ_313) + INT_VECTOR_PE0_IRQ_313, /* EIC313 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 314) + #if defined(INT_VECTOR_PE0_IRQ_314) + INT_VECTOR_PE0_IRQ_314, /* EIC314 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 315) + #if defined(INT_VECTOR_PE0_IRQ_315) + INT_VECTOR_PE0_IRQ_315, /* EIC315 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 316) + #if defined(INT_VECTOR_PE0_IRQ_316) + INT_VECTOR_PE0_IRQ_316, /* EIC316 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 317) + #if defined(INT_VECTOR_PE0_IRQ_317) + INT_VECTOR_PE0_IRQ_317, /* EIC317 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 318) + #if defined(INT_VECTOR_PE0_IRQ_318) + INT_VECTOR_PE0_IRQ_318, /* EIC318 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 319) + #if defined(INT_VECTOR_PE0_IRQ_319) + INT_VECTOR_PE0_IRQ_319, /* EIC319 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 320) + #if defined(INT_VECTOR_PE0_IRQ_320) + INT_VECTOR_PE0_IRQ_320, /* EIC320 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 321) + #if defined(INT_VECTOR_PE0_IRQ_321) + INT_VECTOR_PE0_IRQ_321, /* EIC321 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 322) + #if defined(INT_VECTOR_PE0_IRQ_322) + INT_VECTOR_PE0_IRQ_322, /* EIC322 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 323) + #if defined(INT_VECTOR_PE0_IRQ_323) + INT_VECTOR_PE0_IRQ_323, /* EIC323 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 324) + #if defined(INT_VECTOR_PE0_IRQ_324) + INT_VECTOR_PE0_IRQ_324, /* EIC324 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 325) + #if defined(INT_VECTOR_PE0_IRQ_325) + INT_VECTOR_PE0_IRQ_325, /* EIC325 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 326) + #if defined(INT_VECTOR_PE0_IRQ_326) + INT_VECTOR_PE0_IRQ_326, /* EIC326 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 327) + #if defined(INT_VECTOR_PE0_IRQ_327) + INT_VECTOR_PE0_IRQ_327, /* EIC327 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 328) + #if defined(INT_VECTOR_PE0_IRQ_328) + INT_VECTOR_PE0_IRQ_328, /* EIC328 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 329) + #if defined(INT_VECTOR_PE0_IRQ_329) + INT_VECTOR_PE0_IRQ_329, /* EIC329 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 330) + #if defined(INT_VECTOR_PE0_IRQ_330) + INT_VECTOR_PE0_IRQ_330, /* EIC330 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 331) + #if defined(INT_VECTOR_PE0_IRQ_331) + INT_VECTOR_PE0_IRQ_331, /* EIC331 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 332) + #if defined(INT_VECTOR_PE0_IRQ_332) + INT_VECTOR_PE0_IRQ_332, /* EIC332 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 333) + #if defined(INT_VECTOR_PE0_IRQ_333) + INT_VECTOR_PE0_IRQ_333, /* EIC333 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 334) + #if defined(INT_VECTOR_PE0_IRQ_334) + INT_VECTOR_PE0_IRQ_334, /* EIC334 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 335) + #if defined(INT_VECTOR_PE0_IRQ_335) + INT_VECTOR_PE0_IRQ_335, /* EIC335 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 336) + #if defined(INT_VECTOR_PE0_IRQ_336) + INT_VECTOR_PE0_IRQ_336, /* EIC336 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 337) + #if defined(INT_VECTOR_PE0_IRQ_337) + INT_VECTOR_PE0_IRQ_337, /* EIC337 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 338) + #if defined(INT_VECTOR_PE0_IRQ_338) + INT_VECTOR_PE0_IRQ_338, /* EIC338 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 339) + #if defined(INT_VECTOR_PE0_IRQ_339) + INT_VECTOR_PE0_IRQ_339, /* EIC339 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 340) + #if defined(INT_VECTOR_PE0_IRQ_340) + INT_VECTOR_PE0_IRQ_340, /* EIC340 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 341) + #if defined(INT_VECTOR_PE0_IRQ_341) + INT_VECTOR_PE0_IRQ_341, /* EIC341 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 342) + #if defined(INT_VECTOR_PE0_IRQ_342) + INT_VECTOR_PE0_IRQ_342, /* EIC342 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 343) + #if defined(INT_VECTOR_PE0_IRQ_343) + INT_VECTOR_PE0_IRQ_343, /* EIC343 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 344) + #if defined(INT_VECTOR_PE0_IRQ_344) + INT_VECTOR_PE0_IRQ_344, /* EIC344 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 345) + #if defined(INT_VECTOR_PE0_IRQ_345) + INT_VECTOR_PE0_IRQ_345, /* EIC345 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 346) + #if defined(INT_VECTOR_PE0_IRQ_346) + INT_VECTOR_PE0_IRQ_346, /* EIC346 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 347) + #if defined(INT_VECTOR_PE0_IRQ_347) + INT_VECTOR_PE0_IRQ_347, /* EIC347 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 348) + #if defined(INT_VECTOR_PE0_IRQ_348) + INT_VECTOR_PE0_IRQ_348, /* EIC348 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 349) + #if defined(INT_VECTOR_PE0_IRQ_349) + INT_VECTOR_PE0_IRQ_349, /* EIC349 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 350) + #if defined(INT_VECTOR_PE0_IRQ_350) + INT_VECTOR_PE0_IRQ_350, /* EIC350 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 351) + #if defined(INT_VECTOR_PE0_IRQ_351) + INT_VECTOR_PE0_IRQ_351, /* EIC351 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 352) + #if defined(INT_VECTOR_PE0_IRQ_352) + INT_VECTOR_PE0_IRQ_352, /* EIC352 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 353) + #if defined(INT_VECTOR_PE0_IRQ_353) + INT_VECTOR_PE0_IRQ_353, /* EIC353 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 354) + #if defined(INT_VECTOR_PE0_IRQ_354) + INT_VECTOR_PE0_IRQ_354, /* EIC354 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 355) + #if defined(INT_VECTOR_PE0_IRQ_355) + INT_VECTOR_PE0_IRQ_355, /* EIC355 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 356) + #if defined(INT_VECTOR_PE0_IRQ_356) + INT_VECTOR_PE0_IRQ_356, /* EIC356 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 357) + #if defined(INT_VECTOR_PE0_IRQ_357) + INT_VECTOR_PE0_IRQ_357, /* EIC357 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 358) + #if defined(INT_VECTOR_PE0_IRQ_358) + INT_VECTOR_PE0_IRQ_358, /* EIC358 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 359) + #if defined(INT_VECTOR_PE0_IRQ_359) + INT_VECTOR_PE0_IRQ_359, /* EIC359 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 360) + #if defined(INT_VECTOR_PE0_IRQ_360) + INT_VECTOR_PE0_IRQ_360, /* EIC360 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 361) + #if defined(INT_VECTOR_PE0_IRQ_361) + INT_VECTOR_PE0_IRQ_361, /* EIC361 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 362) + #if defined(INT_VECTOR_PE0_IRQ_362) + INT_VECTOR_PE0_IRQ_362, /* EIC362 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 363) + #if defined(INT_VECTOR_PE0_IRQ_363) + INT_VECTOR_PE0_IRQ_363, /* EIC363 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 364) + #if defined(INT_VECTOR_PE0_IRQ_364) + INT_VECTOR_PE0_IRQ_364, /* EIC364 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 365) + #if defined(INT_VECTOR_PE0_IRQ_365) + INT_VECTOR_PE0_IRQ_365, /* EIC365 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 366) + #if defined(INT_VECTOR_PE0_IRQ_366) + INT_VECTOR_PE0_IRQ_366, /* EIC366 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 367) + #if defined(INT_VECTOR_PE0_IRQ_367) + INT_VECTOR_PE0_IRQ_367, /* EIC367 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 368) + #if defined(INT_VECTOR_PE0_IRQ_368) + INT_VECTOR_PE0_IRQ_368, /* EIC368 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 369) + #if defined(INT_VECTOR_PE0_IRQ_369) + INT_VECTOR_PE0_IRQ_369, /* EIC369 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 370) + #if defined(INT_VECTOR_PE0_IRQ_370) + INT_VECTOR_PE0_IRQ_370, /* EIC370 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 371) + #if defined(INT_VECTOR_PE0_IRQ_371) + INT_VECTOR_PE0_IRQ_371, /* EIC371 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 372) + #if defined(INT_VECTOR_PE0_IRQ_372) + INT_VECTOR_PE0_IRQ_372, /* EIC372 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 373) + #if defined(INT_VECTOR_PE0_IRQ_373) + INT_VECTOR_PE0_IRQ_373, /* EIC373 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 374) + #if defined(INT_VECTOR_PE0_IRQ_374) + INT_VECTOR_PE0_IRQ_374, /* EIC374 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 375) + #if defined(INT_VECTOR_PE0_IRQ_375) + INT_VECTOR_PE0_IRQ_375, /* EIC375 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 376) + #if defined(INT_VECTOR_PE0_IRQ_376) + INT_VECTOR_PE0_IRQ_376, /* EIC376 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 377) + #if defined(INT_VECTOR_PE0_IRQ_377) + INT_VECTOR_PE0_IRQ_377, /* EIC377 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 378) + #if defined(INT_VECTOR_PE0_IRQ_378) + INT_VECTOR_PE0_IRQ_378, /* EIC378 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 379) + #if defined(INT_VECTOR_PE0_IRQ_379) + INT_VECTOR_PE0_IRQ_379, /* EIC379 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 380) + #if defined(INT_VECTOR_PE0_IRQ_380) + INT_VECTOR_PE0_IRQ_380, /* EIC380 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 381) + #if defined(INT_VECTOR_PE0_IRQ_381) + INT_VECTOR_PE0_IRQ_381, /* EIC381 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 382) + #if defined(INT_VECTOR_PE0_IRQ_382) + INT_VECTOR_PE0_IRQ_382, /* EIC382 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 383) + #if defined(INT_VECTOR_PE0_IRQ_383) + INT_VECTOR_PE0_IRQ_383, /* EIC383 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 384) + #if defined(INT_VECTOR_PE0_IRQ_384) + INT_VECTOR_PE0_IRQ_384, /* EIC384 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 385) + #if defined(INT_VECTOR_PE0_IRQ_385) + INT_VECTOR_PE0_IRQ_385, /* EIC385 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 386) + #if defined(INT_VECTOR_PE0_IRQ_386) + INT_VECTOR_PE0_IRQ_386, /* EIC386 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 387) + #if defined(INT_VECTOR_PE0_IRQ_387) + INT_VECTOR_PE0_IRQ_387, /* EIC387 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 388) + #if defined(INT_VECTOR_PE0_IRQ_388) + INT_VECTOR_PE0_IRQ_388, /* EIC388 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 389) + #if defined(INT_VECTOR_PE0_IRQ_389) + INT_VECTOR_PE0_IRQ_389, /* EIC389 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 390) + #if defined(INT_VECTOR_PE0_IRQ_390) + INT_VECTOR_PE0_IRQ_390, /* EIC390 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 391) + #if defined(INT_VECTOR_PE0_IRQ_391) + INT_VECTOR_PE0_IRQ_391, /* EIC391 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 392) + #if defined(INT_VECTOR_PE0_IRQ_392) + INT_VECTOR_PE0_IRQ_392, /* EIC392 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 393) + #if defined(INT_VECTOR_PE0_IRQ_393) + INT_VECTOR_PE0_IRQ_393, /* EIC393 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 394) + #if defined(INT_VECTOR_PE0_IRQ_394) + INT_VECTOR_PE0_IRQ_394, /* EIC394 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 395) + #if defined(INT_VECTOR_PE0_IRQ_395) + INT_VECTOR_PE0_IRQ_395, /* EIC395 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 396) + #if defined(INT_VECTOR_PE0_IRQ_396) + INT_VECTOR_PE0_IRQ_396, /* EIC396 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 397) + #if defined(INT_VECTOR_PE0_IRQ_397) + INT_VECTOR_PE0_IRQ_397, /* EIC397 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 398) + #if defined(INT_VECTOR_PE0_IRQ_398) + INT_VECTOR_PE0_IRQ_398, /* EIC398 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 399) + #if defined(INT_VECTOR_PE0_IRQ_399) + INT_VECTOR_PE0_IRQ_399, /* EIC399 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 400) + #if defined(INT_VECTOR_PE0_IRQ_400) + INT_VECTOR_PE0_IRQ_400, /* EIC400 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 401) + #if defined(INT_VECTOR_PE0_IRQ_401) + INT_VECTOR_PE0_IRQ_401, /* EIC401 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 402) + #if defined(INT_VECTOR_PE0_IRQ_402) + INT_VECTOR_PE0_IRQ_402, /* EIC402 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 403) + #if defined(INT_VECTOR_PE0_IRQ_403) + INT_VECTOR_PE0_IRQ_403, /* EIC403 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 404) + #if defined(INT_VECTOR_PE0_IRQ_404) + INT_VECTOR_PE0_IRQ_404, /* EIC404 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 405) + #if defined(INT_VECTOR_PE0_IRQ_405) + INT_VECTOR_PE0_IRQ_405, /* EIC405 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 406) + #if defined(INT_VECTOR_PE0_IRQ_406) + INT_VECTOR_PE0_IRQ_406, /* EIC406 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 407) + #if defined(INT_VECTOR_PE0_IRQ_407) + INT_VECTOR_PE0_IRQ_407, /* EIC407 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 408) + #if defined(INT_VECTOR_PE0_IRQ_408) + INT_VECTOR_PE0_IRQ_408, /* EIC408 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 409) + #if defined(INT_VECTOR_PE0_IRQ_409) + INT_VECTOR_PE0_IRQ_409, /* EIC409 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 410) + #if defined(INT_VECTOR_PE0_IRQ_410) + INT_VECTOR_PE0_IRQ_410, /* EIC410 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 411) + #if defined(INT_VECTOR_PE0_IRQ_411) + INT_VECTOR_PE0_IRQ_411, /* EIC411 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 412) + #if defined(INT_VECTOR_PE0_IRQ_412) + INT_VECTOR_PE0_IRQ_412, /* EIC412 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 413) + #if defined(INT_VECTOR_PE0_IRQ_413) + INT_VECTOR_PE0_IRQ_413, /* EIC413 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 414) + #if defined(INT_VECTOR_PE0_IRQ_414) + INT_VECTOR_PE0_IRQ_414, /* EIC414 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 415) + #if defined(INT_VECTOR_PE0_IRQ_415) + INT_VECTOR_PE0_IRQ_415, /* EIC415 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 416) + #if defined(INT_VECTOR_PE0_IRQ_416) + INT_VECTOR_PE0_IRQ_416, /* EIC416 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 417) + #if defined(INT_VECTOR_PE0_IRQ_417) + INT_VECTOR_PE0_IRQ_417, /* EIC417 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 418) + #if defined(INT_VECTOR_PE0_IRQ_418) + INT_VECTOR_PE0_IRQ_418, /* EIC418 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 419) + #if defined(INT_VECTOR_PE0_IRQ_419) + INT_VECTOR_PE0_IRQ_419, /* EIC419 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 420) + #if defined(INT_VECTOR_PE0_IRQ_420) + INT_VECTOR_PE0_IRQ_420, /* EIC420 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 421) + #if defined(INT_VECTOR_PE0_IRQ_421) + INT_VECTOR_PE0_IRQ_421, /* EIC421 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 422) + #if defined(INT_VECTOR_PE0_IRQ_422) + INT_VECTOR_PE0_IRQ_422, /* EIC422 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 423) + #if defined(INT_VECTOR_PE0_IRQ_423) + INT_VECTOR_PE0_IRQ_423, /* EIC423 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 424) + #if defined(INT_VECTOR_PE0_IRQ_424) + INT_VECTOR_PE0_IRQ_424, /* EIC424 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 425) + #if defined(INT_VECTOR_PE0_IRQ_425) + INT_VECTOR_PE0_IRQ_425, /* EIC425 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 426) + #if defined(INT_VECTOR_PE0_IRQ_426) + INT_VECTOR_PE0_IRQ_426, /* EIC426 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 427) + #if defined(INT_VECTOR_PE0_IRQ_427) + INT_VECTOR_PE0_IRQ_427, /* EIC427 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 428) + #if defined(INT_VECTOR_PE0_IRQ_428) + INT_VECTOR_PE0_IRQ_428, /* EIC428 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 429) + #if defined(INT_VECTOR_PE0_IRQ_429) + INT_VECTOR_PE0_IRQ_429, /* EIC429 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 430) + #if defined(INT_VECTOR_PE0_IRQ_430) + INT_VECTOR_PE0_IRQ_430, /* EIC430 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 431) + #if defined(INT_VECTOR_PE0_IRQ_431) + INT_VECTOR_PE0_IRQ_431, /* EIC431 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 432) + #if defined(INT_VECTOR_PE0_IRQ_432) + INT_VECTOR_PE0_IRQ_432, /* EIC432 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 433) + #if defined(INT_VECTOR_PE0_IRQ_433) + INT_VECTOR_PE0_IRQ_433, /* EIC433 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 434) + #if defined(INT_VECTOR_PE0_IRQ_434) + INT_VECTOR_PE0_IRQ_434, /* EIC434 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 435) + #if defined(INT_VECTOR_PE0_IRQ_435) + INT_VECTOR_PE0_IRQ_435, /* EIC435 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 436) + #if defined(INT_VECTOR_PE0_IRQ_436) + INT_VECTOR_PE0_IRQ_436, /* EIC436 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 437) + #if defined(INT_VECTOR_PE0_IRQ_437) + INT_VECTOR_PE0_IRQ_437, /* EIC437 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 438) + #if defined(INT_VECTOR_PE0_IRQ_438) + INT_VECTOR_PE0_IRQ_438, /* EIC438 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 439) + #if defined(INT_VECTOR_PE0_IRQ_439) + INT_VECTOR_PE0_IRQ_439, /* EIC439 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 440) + #if defined(INT_VECTOR_PE0_IRQ_440) + INT_VECTOR_PE0_IRQ_440, /* EIC440 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 441) + #if defined(INT_VECTOR_PE0_IRQ_441) + INT_VECTOR_PE0_IRQ_441, /* EIC441 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 442) + #if defined(INT_VECTOR_PE0_IRQ_442) + INT_VECTOR_PE0_IRQ_442, /* EIC442 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 443) + #if defined(INT_VECTOR_PE0_IRQ_443) + INT_VECTOR_PE0_IRQ_443, /* EIC443 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 444) + #if defined(INT_VECTOR_PE0_IRQ_444) + INT_VECTOR_PE0_IRQ_444, /* EIC444 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 445) + #if defined(INT_VECTOR_PE0_IRQ_445) + INT_VECTOR_PE0_IRQ_445, /* EIC445 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 446) + #if defined(INT_VECTOR_PE0_IRQ_446) + INT_VECTOR_PE0_IRQ_446, /* EIC446 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 447) + #if defined(INT_VECTOR_PE0_IRQ_447) + INT_VECTOR_PE0_IRQ_447, /* EIC447 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 448) + #if defined(INT_VECTOR_PE0_IRQ_448) + INT_VECTOR_PE0_IRQ_448, /* EIC448 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 449) + #if defined(INT_VECTOR_PE0_IRQ_449) + INT_VECTOR_PE0_IRQ_449, /* EIC449 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 450) + #if defined(INT_VECTOR_PE0_IRQ_450) + INT_VECTOR_PE0_IRQ_450, /* EIC450 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 451) + #if defined(INT_VECTOR_PE0_IRQ_451) + INT_VECTOR_PE0_IRQ_451, /* EIC451 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 452) + #if defined(INT_VECTOR_PE0_IRQ_452) + INT_VECTOR_PE0_IRQ_452, /* EIC452 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 453) + #if defined(INT_VECTOR_PE0_IRQ_453) + INT_VECTOR_PE0_IRQ_453, /* EIC453 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 454) + #if defined(INT_VECTOR_PE0_IRQ_454) + INT_VECTOR_PE0_IRQ_454, /* EIC454 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 455) + #if defined(INT_VECTOR_PE0_IRQ_455) + INT_VECTOR_PE0_IRQ_455, /* EIC455 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 456) + #if defined(INT_VECTOR_PE0_IRQ_456) + INT_VECTOR_PE0_IRQ_456, /* EIC456 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 457) + #if defined(INT_VECTOR_PE0_IRQ_457) + INT_VECTOR_PE0_IRQ_457, /* EIC457 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 458) + #if defined(INT_VECTOR_PE0_IRQ_458) + INT_VECTOR_PE0_IRQ_458, /* EIC458 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 459) + #if defined(INT_VECTOR_PE0_IRQ_459) + INT_VECTOR_PE0_IRQ_459, /* EIC459 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 460) + #if defined(INT_VECTOR_PE0_IRQ_460) + INT_VECTOR_PE0_IRQ_460, /* EIC460 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 461) + #if defined(INT_VECTOR_PE0_IRQ_461) + INT_VECTOR_PE0_IRQ_461, /* EIC461 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 462) + #if defined(INT_VECTOR_PE0_IRQ_462) + INT_VECTOR_PE0_IRQ_462, /* EIC462 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 463) + #if defined(INT_VECTOR_PE0_IRQ_463) + INT_VECTOR_PE0_IRQ_463, /* EIC463 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 464) + #if defined(INT_VECTOR_PE0_IRQ_464) + INT_VECTOR_PE0_IRQ_464, /* EIC464 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 465) + #if defined(INT_VECTOR_PE0_IRQ_465) + INT_VECTOR_PE0_IRQ_465, /* EIC465 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 466) + #if defined(INT_VECTOR_PE0_IRQ_466) + INT_VECTOR_PE0_IRQ_466, /* EIC466 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 467) + #if defined(INT_VECTOR_PE0_IRQ_467) + INT_VECTOR_PE0_IRQ_467, /* EIC467 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 468) + #if defined(INT_VECTOR_PE0_IRQ_468) + INT_VECTOR_PE0_IRQ_468, /* EIC468 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 469) + #if defined(INT_VECTOR_PE0_IRQ_469) + INT_VECTOR_PE0_IRQ_469, /* EIC469 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 470) + #if defined(INT_VECTOR_PE0_IRQ_470) + INT_VECTOR_PE0_IRQ_470, /* EIC470 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 471) + #if defined(INT_VECTOR_PE0_IRQ_471) + INT_VECTOR_PE0_IRQ_471, /* EIC471 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 472) + #if defined(INT_VECTOR_PE0_IRQ_472) + INT_VECTOR_PE0_IRQ_472, /* EIC472 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 473) + #if defined(INT_VECTOR_PE0_IRQ_473) + INT_VECTOR_PE0_IRQ_473, /* EIC473 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 474) + #if defined(INT_VECTOR_PE0_IRQ_474) + INT_VECTOR_PE0_IRQ_474, /* EIC474 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 475) + #if defined(INT_VECTOR_PE0_IRQ_475) + INT_VECTOR_PE0_IRQ_475, /* EIC475 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 476) + #if defined(INT_VECTOR_PE0_IRQ_476) + INT_VECTOR_PE0_IRQ_476, /* EIC476 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 477) + #if defined(INT_VECTOR_PE0_IRQ_477) + INT_VECTOR_PE0_IRQ_477, /* EIC477 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 478) + #if defined(INT_VECTOR_PE0_IRQ_478) + INT_VECTOR_PE0_IRQ_478, /* EIC478 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 479) + #if defined(INT_VECTOR_PE0_IRQ_479) + INT_VECTOR_PE0_IRQ_479, /* EIC479 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 480) + #if defined(INT_VECTOR_PE0_IRQ_480) + INT_VECTOR_PE0_IRQ_480, /* EIC480 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 481) + #if defined(INT_VECTOR_PE0_IRQ_481) + INT_VECTOR_PE0_IRQ_481, /* EIC481 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 482) + #if defined(INT_VECTOR_PE0_IRQ_482) + INT_VECTOR_PE0_IRQ_482, /* EIC482 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 483) + #if defined(INT_VECTOR_PE0_IRQ_483) + INT_VECTOR_PE0_IRQ_483, /* EIC483 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 484) + #if defined(INT_VECTOR_PE0_IRQ_484) + INT_VECTOR_PE0_IRQ_484, /* EIC484 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 485) + #if defined(INT_VECTOR_PE0_IRQ_485) + INT_VECTOR_PE0_IRQ_485, /* EIC485 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 486) + #if defined(INT_VECTOR_PE0_IRQ_486) + INT_VECTOR_PE0_IRQ_486, /* EIC486 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 487) + #if defined(INT_VECTOR_PE0_IRQ_487) + INT_VECTOR_PE0_IRQ_487, /* EIC487 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 488) + #if defined(INT_VECTOR_PE0_IRQ_488) + INT_VECTOR_PE0_IRQ_488, /* EIC488 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 489) + #if defined(INT_VECTOR_PE0_IRQ_489) + INT_VECTOR_PE0_IRQ_489, /* EIC489 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 490) + #if defined(INT_VECTOR_PE0_IRQ_490) + INT_VECTOR_PE0_IRQ_490, /* EIC490 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 491) + #if defined(INT_VECTOR_PE0_IRQ_491) + INT_VECTOR_PE0_IRQ_491, /* EIC491 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 492) + #if defined(INT_VECTOR_PE0_IRQ_492) + INT_VECTOR_PE0_IRQ_492, /* EIC492 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 493) + #if defined(INT_VECTOR_PE0_IRQ_493) + INT_VECTOR_PE0_IRQ_493, /* EIC493 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 494) + #if defined(INT_VECTOR_PE0_IRQ_494) + INT_VECTOR_PE0_IRQ_494, /* EIC494 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 495) + #if defined(INT_VECTOR_PE0_IRQ_495) + INT_VECTOR_PE0_IRQ_495, /* EIC495 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 496) + #if defined(INT_VECTOR_PE0_IRQ_496) + INT_VECTOR_PE0_IRQ_496, /* EIC496 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 497) + #if defined(INT_VECTOR_PE0_IRQ_497) + INT_VECTOR_PE0_IRQ_497, /* EIC497 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 498) + #if defined(INT_VECTOR_PE0_IRQ_498) + INT_VECTOR_PE0_IRQ_498, /* EIC498 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 499) + #if defined(INT_VECTOR_PE0_IRQ_499) + INT_VECTOR_PE0_IRQ_499, /* EIC499 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 500) + #if defined(INT_VECTOR_PE0_IRQ_500) + INT_VECTOR_PE0_IRQ_500, /* EIC500 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 501) + #if defined(INT_VECTOR_PE0_IRQ_501) + INT_VECTOR_PE0_IRQ_501, /* EIC501 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 502) + #if defined(INT_VECTOR_PE0_IRQ_502) + INT_VECTOR_PE0_IRQ_502, /* EIC502 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 503) + #if defined(INT_VECTOR_PE0_IRQ_503) + INT_VECTOR_PE0_IRQ_503, /* EIC503 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 504) + #if defined(INT_VECTOR_PE0_IRQ_504) + INT_VECTOR_PE0_IRQ_504, /* EIC504 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 505) + #if defined(INT_VECTOR_PE0_IRQ_505) + INT_VECTOR_PE0_IRQ_505, /* EIC505 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 506) + #if defined(INT_VECTOR_PE0_IRQ_506) + INT_VECTOR_PE0_IRQ_506, /* EIC506 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 507) + #if defined(INT_VECTOR_PE0_IRQ_507) + INT_VECTOR_PE0_IRQ_507, /* EIC507 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 508) + #if defined(INT_VECTOR_PE0_IRQ_508) + INT_VECTOR_PE0_IRQ_508, /* EIC508 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 509) + #if defined(INT_VECTOR_PE0_IRQ_509) + INT_VECTOR_PE0_IRQ_509, /* EIC509 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 510) + #if defined(INT_VECTOR_PE0_IRQ_510) + INT_VECTOR_PE0_IRQ_510, /* EIC510 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 511) + #if defined(INT_VECTOR_PE0_IRQ_511) + INT_VECTOR_PE0_IRQ_511, /* EIC511 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 512) + #if defined(INT_VECTOR_PE0_IRQ_512) + INT_VECTOR_PE0_IRQ_512, /* EIC512 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 513) + #if defined(INT_VECTOR_PE0_IRQ_513) + INT_VECTOR_PE0_IRQ_513, /* EIC513 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 514) + #if defined(INT_VECTOR_PE0_IRQ_514) + INT_VECTOR_PE0_IRQ_514, /* EIC514 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 515) + #if defined(INT_VECTOR_PE0_IRQ_515) + INT_VECTOR_PE0_IRQ_515, /* EIC515 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 516) + #if defined(INT_VECTOR_PE0_IRQ_516) + INT_VECTOR_PE0_IRQ_516, /* EIC516 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 517) + #if defined(INT_VECTOR_PE0_IRQ_517) + INT_VECTOR_PE0_IRQ_517, /* EIC517 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 518) + #if defined(INT_VECTOR_PE0_IRQ_518) + INT_VECTOR_PE0_IRQ_518, /* EIC518 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 519) + #if defined(INT_VECTOR_PE0_IRQ_519) + INT_VECTOR_PE0_IRQ_519, /* EIC519 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 520) + #if defined(INT_VECTOR_PE0_IRQ_520) + INT_VECTOR_PE0_IRQ_520, /* EIC520 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 521) + #if defined(INT_VECTOR_PE0_IRQ_521) + INT_VECTOR_PE0_IRQ_521, /* EIC521 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 522) + #if defined(INT_VECTOR_PE0_IRQ_522) + INT_VECTOR_PE0_IRQ_522, /* EIC522 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 523) + #if defined(INT_VECTOR_PE0_IRQ_523) + INT_VECTOR_PE0_IRQ_523, /* EIC523 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 524) + #if defined(INT_VECTOR_PE0_IRQ_524) + INT_VECTOR_PE0_IRQ_524, /* EIC524 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 525) + #if defined(INT_VECTOR_PE0_IRQ_525) + INT_VECTOR_PE0_IRQ_525, /* EIC525 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 526) + #if defined(INT_VECTOR_PE0_IRQ_526) + INT_VECTOR_PE0_IRQ_526, /* EIC526 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 527) + #if defined(INT_VECTOR_PE0_IRQ_527) + INT_VECTOR_PE0_IRQ_527, /* EIC527 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 528) + #if defined(INT_VECTOR_PE0_IRQ_528) + INT_VECTOR_PE0_IRQ_528, /* EIC528 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 529) + #if defined(INT_VECTOR_PE0_IRQ_529) + INT_VECTOR_PE0_IRQ_529, /* EIC529 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 530) + #if defined(INT_VECTOR_PE0_IRQ_530) + INT_VECTOR_PE0_IRQ_530, /* EIC530 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 531) + #if defined(INT_VECTOR_PE0_IRQ_531) + INT_VECTOR_PE0_IRQ_531, /* EIC531 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 532) + #if defined(INT_VECTOR_PE0_IRQ_532) + INT_VECTOR_PE0_IRQ_532, /* EIC532 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 533) + #if defined(INT_VECTOR_PE0_IRQ_533) + INT_VECTOR_PE0_IRQ_533, /* EIC533 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 534) + #if defined(INT_VECTOR_PE0_IRQ_534) + INT_VECTOR_PE0_IRQ_534, /* EIC534 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 535) + #if defined(INT_VECTOR_PE0_IRQ_535) + INT_VECTOR_PE0_IRQ_535, /* EIC535 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 536) + #if defined(INT_VECTOR_PE0_IRQ_536) + INT_VECTOR_PE0_IRQ_536, /* EIC536 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 537) + #if defined(INT_VECTOR_PE0_IRQ_537) + INT_VECTOR_PE0_IRQ_537, /* EIC537 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 538) + #if defined(INT_VECTOR_PE0_IRQ_538) + INT_VECTOR_PE0_IRQ_538, /* EIC538 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 539) + #if defined(INT_VECTOR_PE0_IRQ_539) + INT_VECTOR_PE0_IRQ_539, /* EIC539 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 540) + #if defined(INT_VECTOR_PE0_IRQ_540) + INT_VECTOR_PE0_IRQ_540, /* EIC540 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 541) + #if defined(INT_VECTOR_PE0_IRQ_541) + INT_VECTOR_PE0_IRQ_541, /* EIC541 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 542) + #if defined(INT_VECTOR_PE0_IRQ_542) + INT_VECTOR_PE0_IRQ_542, /* EIC542 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 543) + #if defined(INT_VECTOR_PE0_IRQ_543) + INT_VECTOR_PE0_IRQ_543, /* EIC543 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 544) + #if defined(INT_VECTOR_PE0_IRQ_544) + INT_VECTOR_PE0_IRQ_544, /* EIC544 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 545) + #if defined(INT_VECTOR_PE0_IRQ_545) + INT_VECTOR_PE0_IRQ_545, /* EIC545 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 546) + #if defined(INT_VECTOR_PE0_IRQ_546) + INT_VECTOR_PE0_IRQ_546, /* EIC546 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 547) + #if defined(INT_VECTOR_PE0_IRQ_547) + INT_VECTOR_PE0_IRQ_547, /* EIC547 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 548) + #if defined(INT_VECTOR_PE0_IRQ_548) + INT_VECTOR_PE0_IRQ_548, /* EIC548 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 549) + #if defined(INT_VECTOR_PE0_IRQ_549) + INT_VECTOR_PE0_IRQ_549, /* EIC549 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 550) + #if defined(INT_VECTOR_PE0_IRQ_550) + INT_VECTOR_PE0_IRQ_550, /* EIC550 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 551) + #if defined(INT_VECTOR_PE0_IRQ_551) + INT_VECTOR_PE0_IRQ_551, /* EIC551 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 552) + #if defined(INT_VECTOR_PE0_IRQ_552) + INT_VECTOR_PE0_IRQ_552, /* EIC552 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 553) + #if defined(INT_VECTOR_PE0_IRQ_553) + INT_VECTOR_PE0_IRQ_553, /* EIC553 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 554) + #if defined(INT_VECTOR_PE0_IRQ_554) + INT_VECTOR_PE0_IRQ_554, /* EIC554 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 555) + #if defined(INT_VECTOR_PE0_IRQ_555) + INT_VECTOR_PE0_IRQ_555, /* EIC555 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 556) + #if defined(INT_VECTOR_PE0_IRQ_556) + INT_VECTOR_PE0_IRQ_556, /* EIC556 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 557) + #if defined(INT_VECTOR_PE0_IRQ_557) + INT_VECTOR_PE0_IRQ_557, /* EIC557 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 558) + #if defined(INT_VECTOR_PE0_IRQ_558) + INT_VECTOR_PE0_IRQ_558, /* EIC558 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 559) + #if defined(INT_VECTOR_PE0_IRQ_559) + INT_VECTOR_PE0_IRQ_559, /* EIC559 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 560) + #if defined(INT_VECTOR_PE0_IRQ_560) + INT_VECTOR_PE0_IRQ_560, /* EIC560 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 561) + #if defined(INT_VECTOR_PE0_IRQ_561) + INT_VECTOR_PE0_IRQ_561, /* EIC561 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 562) + #if defined(INT_VECTOR_PE0_IRQ_562) + INT_VECTOR_PE0_IRQ_562, /* EIC562 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 563) + #if defined(INT_VECTOR_PE0_IRQ_563) + INT_VECTOR_PE0_IRQ_563, /* EIC563 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 564) + #if defined(INT_VECTOR_PE0_IRQ_564) + INT_VECTOR_PE0_IRQ_564, /* EIC564 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 565) + #if defined(INT_VECTOR_PE0_IRQ_565) + INT_VECTOR_PE0_IRQ_565, /* EIC565 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 566) + #if defined(INT_VECTOR_PE0_IRQ_566) + INT_VECTOR_PE0_IRQ_566, /* EIC566 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 567) + #if defined(INT_VECTOR_PE0_IRQ_567) + INT_VECTOR_PE0_IRQ_567, /* EIC567 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 568) + #if defined(INT_VECTOR_PE0_IRQ_568) + INT_VECTOR_PE0_IRQ_568, /* EIC568 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 569) + #if defined(INT_VECTOR_PE0_IRQ_569) + INT_VECTOR_PE0_IRQ_569, /* EIC569 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 570) + #if defined(INT_VECTOR_PE0_IRQ_570) + INT_VECTOR_PE0_IRQ_570, /* EIC570 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 571) + #if defined(INT_VECTOR_PE0_IRQ_571) + INT_VECTOR_PE0_IRQ_571, /* EIC571 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 572) + #if defined(INT_VECTOR_PE0_IRQ_572) + INT_VECTOR_PE0_IRQ_572, /* EIC572 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 573) + #if defined(INT_VECTOR_PE0_IRQ_573) + INT_VECTOR_PE0_IRQ_573, /* EIC573 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 574) + #if defined(INT_VECTOR_PE0_IRQ_574) + INT_VECTOR_PE0_IRQ_574, /* EIC574 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 575) + #if defined(INT_VECTOR_PE0_IRQ_575) + INT_VECTOR_PE0_IRQ_575, /* EIC575 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 576) + #if defined(INT_VECTOR_PE0_IRQ_576) + INT_VECTOR_PE0_IRQ_576, /* EIC576 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 577) + #if defined(INT_VECTOR_PE0_IRQ_577) + INT_VECTOR_PE0_IRQ_577, /* EIC577 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 578) + #if defined(INT_VECTOR_PE0_IRQ_578) + INT_VECTOR_PE0_IRQ_578, /* EIC578 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 579) + #if defined(INT_VECTOR_PE0_IRQ_579) + INT_VECTOR_PE0_IRQ_579, /* EIC579 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 580) + #if defined(INT_VECTOR_PE0_IRQ_580) + INT_VECTOR_PE0_IRQ_580, /* EIC580 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 581) + #if defined(INT_VECTOR_PE0_IRQ_581) + INT_VECTOR_PE0_IRQ_581, /* EIC581 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 582) + #if defined(INT_VECTOR_PE0_IRQ_582) + INT_VECTOR_PE0_IRQ_582, /* EIC582 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 583) + #if defined(INT_VECTOR_PE0_IRQ_583) + INT_VECTOR_PE0_IRQ_583, /* EIC583 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 584) + #if defined(INT_VECTOR_PE0_IRQ_584) + INT_VECTOR_PE0_IRQ_584, /* EIC584 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 585) + #if defined(INT_VECTOR_PE0_IRQ_585) + INT_VECTOR_PE0_IRQ_585, /* EIC585 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 586) + #if defined(INT_VECTOR_PE0_IRQ_586) + INT_VECTOR_PE0_IRQ_586, /* EIC586 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 587) + #if defined(INT_VECTOR_PE0_IRQ_587) + INT_VECTOR_PE0_IRQ_587, /* EIC587 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 588) + #if defined(INT_VECTOR_PE0_IRQ_588) + INT_VECTOR_PE0_IRQ_588, /* EIC588 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 589) + #if defined(INT_VECTOR_PE0_IRQ_589) + INT_VECTOR_PE0_IRQ_589, /* EIC589 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 590) + #if defined(INT_VECTOR_PE0_IRQ_590) + INT_VECTOR_PE0_IRQ_590, /* EIC590 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 591) + #if defined(INT_VECTOR_PE0_IRQ_591) + INT_VECTOR_PE0_IRQ_591, /* EIC591 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 592) + #if defined(INT_VECTOR_PE0_IRQ_592) + INT_VECTOR_PE0_IRQ_592, /* EIC592 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 593) + #if defined(INT_VECTOR_PE0_IRQ_593) + INT_VECTOR_PE0_IRQ_593, /* EIC593 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 594) + #if defined(INT_VECTOR_PE0_IRQ_594) + INT_VECTOR_PE0_IRQ_594, /* EIC594 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 595) + #if defined(INT_VECTOR_PE0_IRQ_595) + INT_VECTOR_PE0_IRQ_595, /* EIC595 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 596) + #if defined(INT_VECTOR_PE0_IRQ_596) + INT_VECTOR_PE0_IRQ_596, /* EIC596 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 597) + #if defined(INT_VECTOR_PE0_IRQ_597) + INT_VECTOR_PE0_IRQ_597, /* EIC597 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 598) + #if defined(INT_VECTOR_PE0_IRQ_598) + INT_VECTOR_PE0_IRQ_598, /* EIC598 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 599) + #if defined(INT_VECTOR_PE0_IRQ_599) + INT_VECTOR_PE0_IRQ_599, /* EIC599 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 600) + #if defined(INT_VECTOR_PE0_IRQ_600) + INT_VECTOR_PE0_IRQ_600, /* EIC600 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 601) + #if defined(INT_VECTOR_PE0_IRQ_601) + INT_VECTOR_PE0_IRQ_601, /* EIC601 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 602) + #if defined(INT_VECTOR_PE0_IRQ_602) + INT_VECTOR_PE0_IRQ_602, /* EIC602 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 603) + #if defined(INT_VECTOR_PE0_IRQ_603) + INT_VECTOR_PE0_IRQ_603, /* EIC603 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 604) + #if defined(INT_VECTOR_PE0_IRQ_604) + INT_VECTOR_PE0_IRQ_604, /* EIC604 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 605) + #if defined(INT_VECTOR_PE0_IRQ_605) + INT_VECTOR_PE0_IRQ_605, /* EIC605 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 606) + #if defined(INT_VECTOR_PE0_IRQ_606) + INT_VECTOR_PE0_IRQ_606, /* EIC606 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 607) + #if defined(INT_VECTOR_PE0_IRQ_607) + INT_VECTOR_PE0_IRQ_607, /* EIC607 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 608) + #if defined(INT_VECTOR_PE0_IRQ_608) + INT_VECTOR_PE0_IRQ_608, /* EIC608 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 609) + #if defined(INT_VECTOR_PE0_IRQ_609) + INT_VECTOR_PE0_IRQ_609, /* EIC609 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 610) + #if defined(INT_VECTOR_PE0_IRQ_610) + INT_VECTOR_PE0_IRQ_610, /* EIC610 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 611) + #if defined(INT_VECTOR_PE0_IRQ_611) + INT_VECTOR_PE0_IRQ_611, /* EIC611 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 612) + #if defined(INT_VECTOR_PE0_IRQ_612) + INT_VECTOR_PE0_IRQ_612, /* EIC612 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 613) + #if defined(INT_VECTOR_PE0_IRQ_613) + INT_VECTOR_PE0_IRQ_613, /* EIC613 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 614) + #if defined(INT_VECTOR_PE0_IRQ_614) + INT_VECTOR_PE0_IRQ_614, /* EIC614 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 615) + #if defined(INT_VECTOR_PE0_IRQ_615) + INT_VECTOR_PE0_IRQ_615, /* EIC615 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 616) + #if defined(INT_VECTOR_PE0_IRQ_616) + INT_VECTOR_PE0_IRQ_616, /* EIC616 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 617) + #if defined(INT_VECTOR_PE0_IRQ_617) + INT_VECTOR_PE0_IRQ_617, /* EIC617 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 618) + #if defined(INT_VECTOR_PE0_IRQ_618) + INT_VECTOR_PE0_IRQ_618, /* EIC618 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 619) + #if defined(INT_VECTOR_PE0_IRQ_619) + INT_VECTOR_PE0_IRQ_619, /* EIC619 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 620) + #if defined(INT_VECTOR_PE0_IRQ_620) + INT_VECTOR_PE0_IRQ_620, /* EIC620 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 621) + #if defined(INT_VECTOR_PE0_IRQ_621) + INT_VECTOR_PE0_IRQ_621, /* EIC621 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 622) + #if defined(INT_VECTOR_PE0_IRQ_622) + INT_VECTOR_PE0_IRQ_622, /* EIC622 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 623) + #if defined(INT_VECTOR_PE0_IRQ_623) + INT_VECTOR_PE0_IRQ_623, /* EIC623 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 624) + #if defined(INT_VECTOR_PE0_IRQ_624) + INT_VECTOR_PE0_IRQ_624, /* EIC624 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 625) + #if defined(INT_VECTOR_PE0_IRQ_625) + INT_VECTOR_PE0_IRQ_625, /* EIC625 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 626) + #if defined(INT_VECTOR_PE0_IRQ_626) + INT_VECTOR_PE0_IRQ_626, /* EIC626 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 627) + #if defined(INT_VECTOR_PE0_IRQ_627) + INT_VECTOR_PE0_IRQ_627, /* EIC627 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 628) + #if defined(INT_VECTOR_PE0_IRQ_628) + INT_VECTOR_PE0_IRQ_628, /* EIC628 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 629) + #if defined(INT_VECTOR_PE0_IRQ_629) + INT_VECTOR_PE0_IRQ_629, /* EIC629 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 630) + #if defined(INT_VECTOR_PE0_IRQ_630) + INT_VECTOR_PE0_IRQ_630, /* EIC630 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 631) + #if defined(INT_VECTOR_PE0_IRQ_631) + INT_VECTOR_PE0_IRQ_631, /* EIC631 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 632) + #if defined(INT_VECTOR_PE0_IRQ_632) + INT_VECTOR_PE0_IRQ_632, /* EIC632 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 633) + #if defined(INT_VECTOR_PE0_IRQ_633) + INT_VECTOR_PE0_IRQ_633, /* EIC633 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 634) + #if defined(INT_VECTOR_PE0_IRQ_634) + INT_VECTOR_PE0_IRQ_634, /* EIC634 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 635) + #if defined(INT_VECTOR_PE0_IRQ_635) + INT_VECTOR_PE0_IRQ_635, /* EIC635 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 636) + #if defined(INT_VECTOR_PE0_IRQ_636) + INT_VECTOR_PE0_IRQ_636, /* EIC636 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 637) + #if defined(INT_VECTOR_PE0_IRQ_637) + INT_VECTOR_PE0_IRQ_637, /* EIC637 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 638) + #if defined(INT_VECTOR_PE0_IRQ_638) + INT_VECTOR_PE0_IRQ_638, /* EIC638 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 639) + #if defined(INT_VECTOR_PE0_IRQ_639) + INT_VECTOR_PE0_IRQ_639, /* EIC639 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 640) + #if defined(INT_VECTOR_PE0_IRQ_640) + INT_VECTOR_PE0_IRQ_640, /* EIC640 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 641) + #if defined(INT_VECTOR_PE0_IRQ_641) + INT_VECTOR_PE0_IRQ_641, /* EIC641 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 642) + #if defined(INT_VECTOR_PE0_IRQ_642) + INT_VECTOR_PE0_IRQ_642, /* EIC642 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 643) + #if defined(INT_VECTOR_PE0_IRQ_643) + INT_VECTOR_PE0_IRQ_643, /* EIC643 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 644) + #if defined(INT_VECTOR_PE0_IRQ_644) + INT_VECTOR_PE0_IRQ_644, /* EIC644 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 645) + #if defined(INT_VECTOR_PE0_IRQ_645) + INT_VECTOR_PE0_IRQ_645, /* EIC645 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 646) + #if defined(INT_VECTOR_PE0_IRQ_646) + INT_VECTOR_PE0_IRQ_646, /* EIC646 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 647) + #if defined(INT_VECTOR_PE0_IRQ_647) + INT_VECTOR_PE0_IRQ_647, /* EIC647 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 648) + #if defined(INT_VECTOR_PE0_IRQ_648) + INT_VECTOR_PE0_IRQ_648, /* EIC648 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 649) + #if defined(INT_VECTOR_PE0_IRQ_649) + INT_VECTOR_PE0_IRQ_649, /* EIC649 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 650) + #if defined(INT_VECTOR_PE0_IRQ_650) + INT_VECTOR_PE0_IRQ_650, /* EIC650 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 651) + #if defined(INT_VECTOR_PE0_IRQ_651) + INT_VECTOR_PE0_IRQ_651, /* EIC651 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 652) + #if defined(INT_VECTOR_PE0_IRQ_652) + INT_VECTOR_PE0_IRQ_652, /* EIC652 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 653) + #if defined(INT_VECTOR_PE0_IRQ_653) + INT_VECTOR_PE0_IRQ_653, /* EIC653 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 654) + #if defined(INT_VECTOR_PE0_IRQ_654) + INT_VECTOR_PE0_IRQ_654, /* EIC654 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 655) + #if defined(INT_VECTOR_PE0_IRQ_655) + INT_VECTOR_PE0_IRQ_655, /* EIC655 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 656) + #if defined(INT_VECTOR_PE0_IRQ_656) + INT_VECTOR_PE0_IRQ_656, /* EIC656 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 657) + #if defined(INT_VECTOR_PE0_IRQ_657) + INT_VECTOR_PE0_IRQ_657, /* EIC657 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 658) + #if defined(INT_VECTOR_PE0_IRQ_658) + INT_VECTOR_PE0_IRQ_658, /* EIC658 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 659) + #if defined(INT_VECTOR_PE0_IRQ_659) + INT_VECTOR_PE0_IRQ_659, /* EIC659 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 660) + #if defined(INT_VECTOR_PE0_IRQ_660) + INT_VECTOR_PE0_IRQ_660, /* EIC660 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 661) + #if defined(INT_VECTOR_PE0_IRQ_661) + INT_VECTOR_PE0_IRQ_661, /* EIC661 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 662) + #if defined(INT_VECTOR_PE0_IRQ_662) + INT_VECTOR_PE0_IRQ_662, /* EIC662 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 663) + #if defined(INT_VECTOR_PE0_IRQ_663) + INT_VECTOR_PE0_IRQ_663, /* EIC663 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 664) + #if defined(INT_VECTOR_PE0_IRQ_664) + INT_VECTOR_PE0_IRQ_664, /* EIC664 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 665) + #if defined(INT_VECTOR_PE0_IRQ_665) + INT_VECTOR_PE0_IRQ_665, /* EIC665 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 666) + #if defined(INT_VECTOR_PE0_IRQ_666) + INT_VECTOR_PE0_IRQ_666, /* EIC666 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 667) + #if defined(INT_VECTOR_PE0_IRQ_667) + INT_VECTOR_PE0_IRQ_667, /* EIC667 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 668) + #if defined(INT_VECTOR_PE0_IRQ_668) + INT_VECTOR_PE0_IRQ_668, /* EIC668 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 669) + #if defined(INT_VECTOR_PE0_IRQ_669) + INT_VECTOR_PE0_IRQ_669, /* EIC669 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 670) + #if defined(INT_VECTOR_PE0_IRQ_670) + INT_VECTOR_PE0_IRQ_670, /* EIC670 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 671) + #if defined(INT_VECTOR_PE0_IRQ_671) + INT_VECTOR_PE0_IRQ_671, /* EIC671 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 672) + #if defined(INT_VECTOR_PE0_IRQ_672) + INT_VECTOR_PE0_IRQ_672, /* EIC672 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 673) + #if defined(INT_VECTOR_PE0_IRQ_673) + INT_VECTOR_PE0_IRQ_673, /* EIC673 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 674) + #if defined(INT_VECTOR_PE0_IRQ_674) + INT_VECTOR_PE0_IRQ_674, /* EIC674 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 675) + #if defined(INT_VECTOR_PE0_IRQ_675) + INT_VECTOR_PE0_IRQ_675, /* EIC675 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 676) + #if defined(INT_VECTOR_PE0_IRQ_676) + INT_VECTOR_PE0_IRQ_676, /* EIC676 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 677) + #if defined(INT_VECTOR_PE0_IRQ_677) + INT_VECTOR_PE0_IRQ_677, /* EIC677 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 678) + #if defined(INT_VECTOR_PE0_IRQ_678) + INT_VECTOR_PE0_IRQ_678, /* EIC678 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 679) + #if defined(INT_VECTOR_PE0_IRQ_679) + INT_VECTOR_PE0_IRQ_679, /* EIC679 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 680) + #if defined(INT_VECTOR_PE0_IRQ_680) + INT_VECTOR_PE0_IRQ_680, /* EIC680 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 681) + #if defined(INT_VECTOR_PE0_IRQ_681) + INT_VECTOR_PE0_IRQ_681, /* EIC681 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 682) + #if defined(INT_VECTOR_PE0_IRQ_682) + INT_VECTOR_PE0_IRQ_682, /* EIC682 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 683) + #if defined(INT_VECTOR_PE0_IRQ_683) + INT_VECTOR_PE0_IRQ_683, /* EIC683 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 684) + #if defined(INT_VECTOR_PE0_IRQ_684) + INT_VECTOR_PE0_IRQ_684, /* EIC684 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 685) + #if defined(INT_VECTOR_PE0_IRQ_685) + INT_VECTOR_PE0_IRQ_685, /* EIC685 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 686) + #if defined(INT_VECTOR_PE0_IRQ_686) + INT_VECTOR_PE0_IRQ_686, /* EIC686 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 687) + #if defined(INT_VECTOR_PE0_IRQ_687) + INT_VECTOR_PE0_IRQ_687, /* EIC687 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 688) + #if defined(INT_VECTOR_PE0_IRQ_688) + INT_VECTOR_PE0_IRQ_688, /* EIC688 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 689) + #if defined(INT_VECTOR_PE0_IRQ_689) + INT_VECTOR_PE0_IRQ_689, /* EIC689 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 690) + #if defined(INT_VECTOR_PE0_IRQ_690) + INT_VECTOR_PE0_IRQ_690, /* EIC690 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 691) + #if defined(INT_VECTOR_PE0_IRQ_691) + INT_VECTOR_PE0_IRQ_691, /* EIC691 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 692) + #if defined(INT_VECTOR_PE0_IRQ_692) + INT_VECTOR_PE0_IRQ_692, /* EIC692 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 693) + #if defined(INT_VECTOR_PE0_IRQ_693) + INT_VECTOR_PE0_IRQ_693, /* EIC693 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 694) + #if defined(INT_VECTOR_PE0_IRQ_694) + INT_VECTOR_PE0_IRQ_694, /* EIC694 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 695) + #if defined(INT_VECTOR_PE0_IRQ_695) + INT_VECTOR_PE0_IRQ_695, /* EIC695 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 696) + #if defined(INT_VECTOR_PE0_IRQ_696) + INT_VECTOR_PE0_IRQ_696, /* EIC696 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 697) + #if defined(INT_VECTOR_PE0_IRQ_697) + INT_VECTOR_PE0_IRQ_697, /* EIC697 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 698) + #if defined(INT_VECTOR_PE0_IRQ_698) + INT_VECTOR_PE0_IRQ_698, /* EIC698 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 699) + #if defined(INT_VECTOR_PE0_IRQ_699) + INT_VECTOR_PE0_IRQ_699, /* EIC699 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 700) + #if defined(INT_VECTOR_PE0_IRQ_700) + INT_VECTOR_PE0_IRQ_700, /* EIC700 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 701) + #if defined(INT_VECTOR_PE0_IRQ_701) + INT_VECTOR_PE0_IRQ_701, /* EIC701 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 702) + #if defined(INT_VECTOR_PE0_IRQ_702) + INT_VECTOR_PE0_IRQ_702, /* EIC702 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 703) + #if defined(INT_VECTOR_PE0_IRQ_703) + INT_VECTOR_PE0_IRQ_703, /* EIC703 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 704) + #if defined(INT_VECTOR_PE0_IRQ_704) + INT_VECTOR_PE0_IRQ_704, /* EIC704 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 705) + #if defined(INT_VECTOR_PE0_IRQ_705) + INT_VECTOR_PE0_IRQ_705, /* EIC705 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 706) + #if defined(INT_VECTOR_PE0_IRQ_706) + INT_VECTOR_PE0_IRQ_706, /* EIC706 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 707) + #if defined(INT_VECTOR_PE0_IRQ_707) + INT_VECTOR_PE0_IRQ_707, /* EIC707 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 708) + #if defined(INT_VECTOR_PE0_IRQ_708) + INT_VECTOR_PE0_IRQ_708, /* EIC708 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 709) + #if defined(INT_VECTOR_PE0_IRQ_709) + INT_VECTOR_PE0_IRQ_709, /* EIC709 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 710) + #if defined(INT_VECTOR_PE0_IRQ_710) + INT_VECTOR_PE0_IRQ_710, /* EIC710 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 711) + #if defined(INT_VECTOR_PE0_IRQ_711) + INT_VECTOR_PE0_IRQ_711, /* EIC711 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 712) + #if defined(INT_VECTOR_PE0_IRQ_712) + INT_VECTOR_PE0_IRQ_712, /* EIC712 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 713) + #if defined(INT_VECTOR_PE0_IRQ_713) + INT_VECTOR_PE0_IRQ_713, /* EIC713 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 714) + #if defined(INT_VECTOR_PE0_IRQ_714) + INT_VECTOR_PE0_IRQ_714, /* EIC714 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 715) + #if defined(INT_VECTOR_PE0_IRQ_715) + INT_VECTOR_PE0_IRQ_715, /* EIC715 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 716) + #if defined(INT_VECTOR_PE0_IRQ_716) + INT_VECTOR_PE0_IRQ_716, /* EIC716 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 717) + #if defined(INT_VECTOR_PE0_IRQ_717) + INT_VECTOR_PE0_IRQ_717, /* EIC717 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 718) + #if defined(INT_VECTOR_PE0_IRQ_718) + INT_VECTOR_PE0_IRQ_718, /* EIC718 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 719) + #if defined(INT_VECTOR_PE0_IRQ_719) + INT_VECTOR_PE0_IRQ_719, /* EIC719 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 720) + #if defined(INT_VECTOR_PE0_IRQ_720) + INT_VECTOR_PE0_IRQ_720, /* EIC720 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 721) + #if defined(INT_VECTOR_PE0_IRQ_721) + INT_VECTOR_PE0_IRQ_721, /* EIC721 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 722) + #if defined(INT_VECTOR_PE0_IRQ_722) + INT_VECTOR_PE0_IRQ_722, /* EIC722 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 723) + #if defined(INT_VECTOR_PE0_IRQ_723) + INT_VECTOR_PE0_IRQ_723, /* EIC723 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 724) + #if defined(INT_VECTOR_PE0_IRQ_724) + INT_VECTOR_PE0_IRQ_724, /* EIC724 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 725) + #if defined(INT_VECTOR_PE0_IRQ_725) + INT_VECTOR_PE0_IRQ_725, /* EIC725 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 726) + #if defined(INT_VECTOR_PE0_IRQ_726) + INT_VECTOR_PE0_IRQ_726, /* EIC726 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 727) + #if defined(INT_VECTOR_PE0_IRQ_727) + INT_VECTOR_PE0_IRQ_727, /* EIC727 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 728) + #if defined(INT_VECTOR_PE0_IRQ_728) + INT_VECTOR_PE0_IRQ_728, /* EIC728 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 729) + #if defined(INT_VECTOR_PE0_IRQ_729) + INT_VECTOR_PE0_IRQ_729, /* EIC729 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 730) + #if defined(INT_VECTOR_PE0_IRQ_730) + INT_VECTOR_PE0_IRQ_730, /* EIC730 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 731) + #if defined(INT_VECTOR_PE0_IRQ_731) + INT_VECTOR_PE0_IRQ_731, /* EIC731 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 732) + #if defined(INT_VECTOR_PE0_IRQ_732) + INT_VECTOR_PE0_IRQ_732, /* EIC732 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 733) + #if defined(INT_VECTOR_PE0_IRQ_733) + INT_VECTOR_PE0_IRQ_733, /* EIC733 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 734) + #if defined(INT_VECTOR_PE0_IRQ_734) + INT_VECTOR_PE0_IRQ_734, /* EIC734 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 735) + #if defined(INT_VECTOR_PE0_IRQ_735) + INT_VECTOR_PE0_IRQ_735, /* EIC735 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 736) + #if defined(INT_VECTOR_PE0_IRQ_736) + INT_VECTOR_PE0_IRQ_736, /* EIC736 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 737) + #if defined(INT_VECTOR_PE0_IRQ_737) + INT_VECTOR_PE0_IRQ_737, /* EIC737 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 738) + #if defined(INT_VECTOR_PE0_IRQ_738) + INT_VECTOR_PE0_IRQ_738, /* EIC738 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 739) + #if defined(INT_VECTOR_PE0_IRQ_739) + INT_VECTOR_PE0_IRQ_739, /* EIC739 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 740) + #if defined(INT_VECTOR_PE0_IRQ_740) + INT_VECTOR_PE0_IRQ_740, /* EIC740 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 741) + #if defined(INT_VECTOR_PE0_IRQ_741) + INT_VECTOR_PE0_IRQ_741, /* EIC741 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 742) + #if defined(INT_VECTOR_PE0_IRQ_742) + INT_VECTOR_PE0_IRQ_742, /* EIC742 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 743) + #if defined(INT_VECTOR_PE0_IRQ_743) + INT_VECTOR_PE0_IRQ_743, /* EIC743 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 744) + #if defined(INT_VECTOR_PE0_IRQ_744) + INT_VECTOR_PE0_IRQ_744, /* EIC744 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 745) + #if defined(INT_VECTOR_PE0_IRQ_745) + INT_VECTOR_PE0_IRQ_745, /* EIC745 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 746) + #if defined(INT_VECTOR_PE0_IRQ_746) + INT_VECTOR_PE0_IRQ_746, /* EIC746 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 747) + #if defined(INT_VECTOR_PE0_IRQ_747) + INT_VECTOR_PE0_IRQ_747, /* EIC747 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 748) + #if defined(INT_VECTOR_PE0_IRQ_748) + INT_VECTOR_PE0_IRQ_748, /* EIC748 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 749) + #if defined(INT_VECTOR_PE0_IRQ_749) + INT_VECTOR_PE0_IRQ_749, /* EIC749 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 750) + #if defined(INT_VECTOR_PE0_IRQ_750) + INT_VECTOR_PE0_IRQ_750, /* EIC750 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 751) + #if defined(INT_VECTOR_PE0_IRQ_751) + INT_VECTOR_PE0_IRQ_751, /* EIC751 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 752) + #if defined(INT_VECTOR_PE0_IRQ_752) + INT_VECTOR_PE0_IRQ_752, /* EIC752 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 753) + #if defined(INT_VECTOR_PE0_IRQ_753) + INT_VECTOR_PE0_IRQ_753, /* EIC753 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 754) + #if defined(INT_VECTOR_PE0_IRQ_754) + INT_VECTOR_PE0_IRQ_754, /* EIC754 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 755) + #if defined(INT_VECTOR_PE0_IRQ_755) + INT_VECTOR_PE0_IRQ_755, /* EIC755 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 756) + #if defined(INT_VECTOR_PE0_IRQ_756) + INT_VECTOR_PE0_IRQ_756, /* EIC756 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 757) + #if defined(INT_VECTOR_PE0_IRQ_757) + INT_VECTOR_PE0_IRQ_757, /* EIC757 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 758) + #if defined(INT_VECTOR_PE0_IRQ_758) + INT_VECTOR_PE0_IRQ_758, /* EIC758 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 759) + #if defined(INT_VECTOR_PE0_IRQ_759) + INT_VECTOR_PE0_IRQ_759, /* EIC759 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 760) + #if defined(INT_VECTOR_PE0_IRQ_760) + INT_VECTOR_PE0_IRQ_760, /* EIC760 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 761) + #if defined(INT_VECTOR_PE0_IRQ_761) + INT_VECTOR_PE0_IRQ_761, /* EIC761 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 762) + #if defined(INT_VECTOR_PE0_IRQ_762) + INT_VECTOR_PE0_IRQ_762, /* EIC762 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 763) + #if defined(INT_VECTOR_PE0_IRQ_763) + INT_VECTOR_PE0_IRQ_763, /* EIC763 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 764) + #if defined(INT_VECTOR_PE0_IRQ_764) + INT_VECTOR_PE0_IRQ_764, /* EIC764 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 765) + #if defined(INT_VECTOR_PE0_IRQ_765) + INT_VECTOR_PE0_IRQ_765, /* EIC765 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 766) + #if defined(INT_VECTOR_PE0_IRQ_766) + INT_VECTOR_PE0_IRQ_766, /* EIC766 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 767) + #if defined(INT_VECTOR_PE0_IRQ_767) + INT_VECTOR_PE0_IRQ_767, /* EIC767 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 768) + #if defined(INT_VECTOR_PE0_IRQ_768) + INT_VECTOR_PE0_IRQ_768, /* EIC768 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 769) + #if defined(INT_VECTOR_PE0_IRQ_769) + INT_VECTOR_PE0_IRQ_769, /* EIC769 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 770) + #if defined(INT_VECTOR_PE0_IRQ_770) + INT_VECTOR_PE0_IRQ_770, /* EIC770 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 771) + #if defined(INT_VECTOR_PE0_IRQ_771) + INT_VECTOR_PE0_IRQ_771, /* EIC771 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 772) + #if defined(INT_VECTOR_PE0_IRQ_772) + INT_VECTOR_PE0_IRQ_772, /* EIC772 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 773) + #if defined(INT_VECTOR_PE0_IRQ_773) + INT_VECTOR_PE0_IRQ_773, /* EIC773 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 774) + #if defined(INT_VECTOR_PE0_IRQ_774) + INT_VECTOR_PE0_IRQ_774, /* EIC774 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 775) + #if defined(INT_VECTOR_PE0_IRQ_775) + INT_VECTOR_PE0_IRQ_775, /* EIC775 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 776) + #if defined(INT_VECTOR_PE0_IRQ_776) + INT_VECTOR_PE0_IRQ_776, /* EIC776 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 777) + #if defined(INT_VECTOR_PE0_IRQ_777) + INT_VECTOR_PE0_IRQ_777, /* EIC777 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 778) + #if defined(INT_VECTOR_PE0_IRQ_778) + INT_VECTOR_PE0_IRQ_778, /* EIC778 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 779) + #if defined(INT_VECTOR_PE0_IRQ_779) + INT_VECTOR_PE0_IRQ_779, /* EIC779 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 780) + #if defined(INT_VECTOR_PE0_IRQ_780) + INT_VECTOR_PE0_IRQ_780, /* EIC780 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 781) + #if defined(INT_VECTOR_PE0_IRQ_781) + INT_VECTOR_PE0_IRQ_781, /* EIC781 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 782) + #if defined(INT_VECTOR_PE0_IRQ_782) + INT_VECTOR_PE0_IRQ_782, /* EIC782 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 783) + #if defined(INT_VECTOR_PE0_IRQ_783) + INT_VECTOR_PE0_IRQ_783, /* EIC783 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 784) + #if defined(INT_VECTOR_PE0_IRQ_784) + INT_VECTOR_PE0_IRQ_784, /* EIC784 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 785) + #if defined(INT_VECTOR_PE0_IRQ_785) + INT_VECTOR_PE0_IRQ_785, /* EIC785 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 786) + #if defined(INT_VECTOR_PE0_IRQ_786) + INT_VECTOR_PE0_IRQ_786, /* EIC786 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 787) + #if defined(INT_VECTOR_PE0_IRQ_787) + INT_VECTOR_PE0_IRQ_787, /* EIC787 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 788) + #if defined(INT_VECTOR_PE0_IRQ_788) + INT_VECTOR_PE0_IRQ_788, /* EIC788 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 789) + #if defined(INT_VECTOR_PE0_IRQ_789) + INT_VECTOR_PE0_IRQ_789, /* EIC789 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 790) + #if defined(INT_VECTOR_PE0_IRQ_790) + INT_VECTOR_PE0_IRQ_790, /* EIC790 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 791) + #if defined(INT_VECTOR_PE0_IRQ_791) + INT_VECTOR_PE0_IRQ_791, /* EIC791 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 792) + #if defined(INT_VECTOR_PE0_IRQ_792) + INT_VECTOR_PE0_IRQ_792, /* EIC792 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 793) + #if defined(INT_VECTOR_PE0_IRQ_793) + INT_VECTOR_PE0_IRQ_793, /* EIC793 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 794) + #if defined(INT_VECTOR_PE0_IRQ_794) + INT_VECTOR_PE0_IRQ_794, /* EIC794 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 795) + #if defined(INT_VECTOR_PE0_IRQ_795) + INT_VECTOR_PE0_IRQ_795, /* EIC795 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 796) + #if defined(INT_VECTOR_PE0_IRQ_796) + INT_VECTOR_PE0_IRQ_796, /* EIC796 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 797) + #if defined(INT_VECTOR_PE0_IRQ_797) + INT_VECTOR_PE0_IRQ_797, /* EIC797 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 798) + #if defined(INT_VECTOR_PE0_IRQ_798) + INT_VECTOR_PE0_IRQ_798, /* EIC798 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 799) + #if defined(INT_VECTOR_PE0_IRQ_799) + INT_VECTOR_PE0_IRQ_799, /* EIC799 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 800) + #if defined(INT_VECTOR_PE0_IRQ_800) + INT_VECTOR_PE0_IRQ_800, /* EIC800 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 801) + #if defined(INT_VECTOR_PE0_IRQ_801) + INT_VECTOR_PE0_IRQ_801, /* EIC801 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 802) + #if defined(INT_VECTOR_PE0_IRQ_802) + INT_VECTOR_PE0_IRQ_802, /* EIC802 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 803) + #if defined(INT_VECTOR_PE0_IRQ_803) + INT_VECTOR_PE0_IRQ_803, /* EIC803 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 804) + #if defined(INT_VECTOR_PE0_IRQ_804) + INT_VECTOR_PE0_IRQ_804, /* EIC804 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 805) + #if defined(INT_VECTOR_PE0_IRQ_805) + INT_VECTOR_PE0_IRQ_805, /* EIC805 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 806) + #if defined(INT_VECTOR_PE0_IRQ_806) + INT_VECTOR_PE0_IRQ_806, /* EIC806 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 807) + #if defined(INT_VECTOR_PE0_IRQ_807) + INT_VECTOR_PE0_IRQ_807, /* EIC807 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 808) + #if defined(INT_VECTOR_PE0_IRQ_808) + INT_VECTOR_PE0_IRQ_808, /* EIC808 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 809) + #if defined(INT_VECTOR_PE0_IRQ_809) + INT_VECTOR_PE0_IRQ_809, /* EIC809 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 810) + #if defined(INT_VECTOR_PE0_IRQ_810) + INT_VECTOR_PE0_IRQ_810, /* EIC810 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 811) + #if defined(INT_VECTOR_PE0_IRQ_811) + INT_VECTOR_PE0_IRQ_811, /* EIC811 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 812) + #if defined(INT_VECTOR_PE0_IRQ_812) + INT_VECTOR_PE0_IRQ_812, /* EIC812 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 813) + #if defined(INT_VECTOR_PE0_IRQ_813) + INT_VECTOR_PE0_IRQ_813, /* EIC813 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 814) + #if defined(INT_VECTOR_PE0_IRQ_814) + INT_VECTOR_PE0_IRQ_814, /* EIC814 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 815) + #if defined(INT_VECTOR_PE0_IRQ_815) + INT_VECTOR_PE0_IRQ_815, /* EIC815 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 816) + #if defined(INT_VECTOR_PE0_IRQ_816) + INT_VECTOR_PE0_IRQ_816, /* EIC816 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 817) + #if defined(INT_VECTOR_PE0_IRQ_817) + INT_VECTOR_PE0_IRQ_817, /* EIC817 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 818) + #if defined(INT_VECTOR_PE0_IRQ_818) + INT_VECTOR_PE0_IRQ_818, /* EIC818 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 819) + #if defined(INT_VECTOR_PE0_IRQ_819) + INT_VECTOR_PE0_IRQ_819, /* EIC819 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 820) + #if defined(INT_VECTOR_PE0_IRQ_820) + INT_VECTOR_PE0_IRQ_820, /* EIC820 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 821) + #if defined(INT_VECTOR_PE0_IRQ_821) + INT_VECTOR_PE0_IRQ_821, /* EIC821 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 822) + #if defined(INT_VECTOR_PE0_IRQ_822) + INT_VECTOR_PE0_IRQ_822, /* EIC822 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 823) + #if defined(INT_VECTOR_PE0_IRQ_823) + INT_VECTOR_PE0_IRQ_823, /* EIC823 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 824) + #if defined(INT_VECTOR_PE0_IRQ_824) + INT_VECTOR_PE0_IRQ_824, /* EIC824 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 825) + #if defined(INT_VECTOR_PE0_IRQ_825) + INT_VECTOR_PE0_IRQ_825, /* EIC825 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 826) + #if defined(INT_VECTOR_PE0_IRQ_826) + INT_VECTOR_PE0_IRQ_826, /* EIC826 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 827) + #if defined(INT_VECTOR_PE0_IRQ_827) + INT_VECTOR_PE0_IRQ_827, /* EIC827 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 828) + #if defined(INT_VECTOR_PE0_IRQ_828) + INT_VECTOR_PE0_IRQ_828, /* EIC828 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 829) + #if defined(INT_VECTOR_PE0_IRQ_829) + INT_VECTOR_PE0_IRQ_829, /* EIC829 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 830) + #if defined(INT_VECTOR_PE0_IRQ_830) + INT_VECTOR_PE0_IRQ_830, /* EIC830 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 831) + #if defined(INT_VECTOR_PE0_IRQ_831) + INT_VECTOR_PE0_IRQ_831, /* EIC831 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 832) + #if defined(INT_VECTOR_PE0_IRQ_832) + INT_VECTOR_PE0_IRQ_832, /* EIC832 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 833) + #if defined(INT_VECTOR_PE0_IRQ_833) + INT_VECTOR_PE0_IRQ_833, /* EIC833 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 834) + #if defined(INT_VECTOR_PE0_IRQ_834) + INT_VECTOR_PE0_IRQ_834, /* EIC834 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 835) + #if defined(INT_VECTOR_PE0_IRQ_835) + INT_VECTOR_PE0_IRQ_835, /* EIC835 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 836) + #if defined(INT_VECTOR_PE0_IRQ_836) + INT_VECTOR_PE0_IRQ_836, /* EIC836 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 837) + #if defined(INT_VECTOR_PE0_IRQ_837) + INT_VECTOR_PE0_IRQ_837, /* EIC837 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 838) + #if defined(INT_VECTOR_PE0_IRQ_838) + INT_VECTOR_PE0_IRQ_838, /* EIC838 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 839) + #if defined(INT_VECTOR_PE0_IRQ_839) + INT_VECTOR_PE0_IRQ_839, /* EIC839 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 840) + #if defined(INT_VECTOR_PE0_IRQ_840) + INT_VECTOR_PE0_IRQ_840, /* EIC840 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 841) + #if defined(INT_VECTOR_PE0_IRQ_841) + INT_VECTOR_PE0_IRQ_841, /* EIC841 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 842) + #if defined(INT_VECTOR_PE0_IRQ_842) + INT_VECTOR_PE0_IRQ_842, /* EIC842 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 843) + #if defined(INT_VECTOR_PE0_IRQ_843) + INT_VECTOR_PE0_IRQ_843, /* EIC843 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 844) + #if defined(INT_VECTOR_PE0_IRQ_844) + INT_VECTOR_PE0_IRQ_844, /* EIC844 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 845) + #if defined(INT_VECTOR_PE0_IRQ_845) + INT_VECTOR_PE0_IRQ_845, /* EIC845 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 846) + #if defined(INT_VECTOR_PE0_IRQ_846) + INT_VECTOR_PE0_IRQ_846, /* EIC846 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 847) + #if defined(INT_VECTOR_PE0_IRQ_847) + INT_VECTOR_PE0_IRQ_847, /* EIC847 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 848) + #if defined(INT_VECTOR_PE0_IRQ_848) + INT_VECTOR_PE0_IRQ_848, /* EIC848 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 849) + #if defined(INT_VECTOR_PE0_IRQ_849) + INT_VECTOR_PE0_IRQ_849, /* EIC849 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 850) + #if defined(INT_VECTOR_PE0_IRQ_850) + INT_VECTOR_PE0_IRQ_850, /* EIC850 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 851) + #if defined(INT_VECTOR_PE0_IRQ_851) + INT_VECTOR_PE0_IRQ_851, /* EIC851 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 852) + #if defined(INT_VECTOR_PE0_IRQ_852) + INT_VECTOR_PE0_IRQ_852, /* EIC852 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 853) + #if defined(INT_VECTOR_PE0_IRQ_853) + INT_VECTOR_PE0_IRQ_853, /* EIC853 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 854) + #if defined(INT_VECTOR_PE0_IRQ_854) + INT_VECTOR_PE0_IRQ_854, /* EIC854 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 855) + #if defined(INT_VECTOR_PE0_IRQ_855) + INT_VECTOR_PE0_IRQ_855, /* EIC855 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 856) + #if defined(INT_VECTOR_PE0_IRQ_856) + INT_VECTOR_PE0_IRQ_856, /* EIC856 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 857) + #if defined(INT_VECTOR_PE0_IRQ_857) + INT_VECTOR_PE0_IRQ_857, /* EIC857 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 858) + #if defined(INT_VECTOR_PE0_IRQ_858) + INT_VECTOR_PE0_IRQ_858, /* EIC858 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 859) + #if defined(INT_VECTOR_PE0_IRQ_859) + INT_VECTOR_PE0_IRQ_859, /* EIC859 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 860) + #if defined(INT_VECTOR_PE0_IRQ_860) + INT_VECTOR_PE0_IRQ_860, /* EIC860 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 861) + #if defined(INT_VECTOR_PE0_IRQ_861) + INT_VECTOR_PE0_IRQ_861, /* EIC861 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 862) + #if defined(INT_VECTOR_PE0_IRQ_862) + INT_VECTOR_PE0_IRQ_862, /* EIC862 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 863) + #if defined(INT_VECTOR_PE0_IRQ_863) + INT_VECTOR_PE0_IRQ_863, /* EIC863 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 864) + #if defined(INT_VECTOR_PE0_IRQ_864) + INT_VECTOR_PE0_IRQ_864, /* EIC864 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 865) + #if defined(INT_VECTOR_PE0_IRQ_865) + INT_VECTOR_PE0_IRQ_865, /* EIC865 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 866) + #if defined(INT_VECTOR_PE0_IRQ_866) + INT_VECTOR_PE0_IRQ_866, /* EIC866 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 867) + #if defined(INT_VECTOR_PE0_IRQ_867) + INT_VECTOR_PE0_IRQ_867, /* EIC867 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 868) + #if defined(INT_VECTOR_PE0_IRQ_868) + INT_VECTOR_PE0_IRQ_868, /* EIC868 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 869) + #if defined(INT_VECTOR_PE0_IRQ_869) + INT_VECTOR_PE0_IRQ_869, /* EIC869 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 870) + #if defined(INT_VECTOR_PE0_IRQ_870) + INT_VECTOR_PE0_IRQ_870, /* EIC870 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 871) + #if defined(INT_VECTOR_PE0_IRQ_871) + INT_VECTOR_PE0_IRQ_871, /* EIC871 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 872) + #if defined(INT_VECTOR_PE0_IRQ_872) + INT_VECTOR_PE0_IRQ_872, /* EIC872 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 873) + #if defined(INT_VECTOR_PE0_IRQ_873) + INT_VECTOR_PE0_IRQ_873, /* EIC873 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 874) + #if defined(INT_VECTOR_PE0_IRQ_874) + INT_VECTOR_PE0_IRQ_874, /* EIC874 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 875) + #if defined(INT_VECTOR_PE0_IRQ_875) + INT_VECTOR_PE0_IRQ_875, /* EIC875 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 876) + #if defined(INT_VECTOR_PE0_IRQ_876) + INT_VECTOR_PE0_IRQ_876, /* EIC876 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 877) + #if defined(INT_VECTOR_PE0_IRQ_877) + INT_VECTOR_PE0_IRQ_877, /* EIC877 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 878) + #if defined(INT_VECTOR_PE0_IRQ_878) + INT_VECTOR_PE0_IRQ_878, /* EIC878 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 879) + #if defined(INT_VECTOR_PE0_IRQ_879) + INT_VECTOR_PE0_IRQ_879, /* EIC879 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 880) + #if defined(INT_VECTOR_PE0_IRQ_880) + INT_VECTOR_PE0_IRQ_880, /* EIC880 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 881) + #if defined(INT_VECTOR_PE0_IRQ_881) + INT_VECTOR_PE0_IRQ_881, /* EIC881 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 882) + #if defined(INT_VECTOR_PE0_IRQ_882) + INT_VECTOR_PE0_IRQ_882, /* EIC882 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 883) + #if defined(INT_VECTOR_PE0_IRQ_883) + INT_VECTOR_PE0_IRQ_883, /* EIC883 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 884) + #if defined(INT_VECTOR_PE0_IRQ_884) + INT_VECTOR_PE0_IRQ_884, /* EIC884 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 885) + #if defined(INT_VECTOR_PE0_IRQ_885) + INT_VECTOR_PE0_IRQ_885, /* EIC885 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 886) + #if defined(INT_VECTOR_PE0_IRQ_886) + INT_VECTOR_PE0_IRQ_886, /* EIC886 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 887) + #if defined(INT_VECTOR_PE0_IRQ_887) + INT_VECTOR_PE0_IRQ_887, /* EIC887 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 888) + #if defined(INT_VECTOR_PE0_IRQ_888) + INT_VECTOR_PE0_IRQ_888, /* EIC888 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 889) + #if defined(INT_VECTOR_PE0_IRQ_889) + INT_VECTOR_PE0_IRQ_889, /* EIC889 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 890) + #if defined(INT_VECTOR_PE0_IRQ_890) + INT_VECTOR_PE0_IRQ_890, /* EIC890 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 891) + #if defined(INT_VECTOR_PE0_IRQ_891) + INT_VECTOR_PE0_IRQ_891, /* EIC891 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 892) + #if defined(INT_VECTOR_PE0_IRQ_892) + INT_VECTOR_PE0_IRQ_892, /* EIC892 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 893) + #if defined(INT_VECTOR_PE0_IRQ_893) + INT_VECTOR_PE0_IRQ_893, /* EIC893 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 894) + #if defined(INT_VECTOR_PE0_IRQ_894) + INT_VECTOR_PE0_IRQ_894, /* EIC894 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 895) + #if defined(INT_VECTOR_PE0_IRQ_895) + INT_VECTOR_PE0_IRQ_895, /* EIC895 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 896) + #if defined(INT_VECTOR_PE0_IRQ_896) + INT_VECTOR_PE0_IRQ_896, /* EIC896 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 897) + #if defined(INT_VECTOR_PE0_IRQ_897) + INT_VECTOR_PE0_IRQ_897, /* EIC897 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 898) + #if defined(INT_VECTOR_PE0_IRQ_898) + INT_VECTOR_PE0_IRQ_898, /* EIC898 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 899) + #if defined(INT_VECTOR_PE0_IRQ_899) + INT_VECTOR_PE0_IRQ_899, /* EIC899 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 900) + #if defined(INT_VECTOR_PE0_IRQ_900) + INT_VECTOR_PE0_IRQ_900, /* EIC900 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 901) + #if defined(INT_VECTOR_PE0_IRQ_901) + INT_VECTOR_PE0_IRQ_901, /* EIC901 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 902) + #if defined(INT_VECTOR_PE0_IRQ_902) + INT_VECTOR_PE0_IRQ_902, /* EIC902 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 903) + #if defined(INT_VECTOR_PE0_IRQ_903) + INT_VECTOR_PE0_IRQ_903, /* EIC903 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 904) + #if defined(INT_VECTOR_PE0_IRQ_904) + INT_VECTOR_PE0_IRQ_904, /* EIC904 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 905) + #if defined(INT_VECTOR_PE0_IRQ_905) + INT_VECTOR_PE0_IRQ_905, /* EIC905 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 906) + #if defined(INT_VECTOR_PE0_IRQ_906) + INT_VECTOR_PE0_IRQ_906, /* EIC906 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 907) + #if defined(INT_VECTOR_PE0_IRQ_907) + INT_VECTOR_PE0_IRQ_907, /* EIC907 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 908) + #if defined(INT_VECTOR_PE0_IRQ_908) + INT_VECTOR_PE0_IRQ_908, /* EIC908 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 909) + #if defined(INT_VECTOR_PE0_IRQ_909) + INT_VECTOR_PE0_IRQ_909, /* EIC909 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 910) + #if defined(INT_VECTOR_PE0_IRQ_910) + INT_VECTOR_PE0_IRQ_910, /* EIC910 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 911) + #if defined(INT_VECTOR_PE0_IRQ_911) + INT_VECTOR_PE0_IRQ_911, /* EIC911 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 912) + #if defined(INT_VECTOR_PE0_IRQ_912) + INT_VECTOR_PE0_IRQ_912, /* EIC912 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 913) + #if defined(INT_VECTOR_PE0_IRQ_913) + INT_VECTOR_PE0_IRQ_913, /* EIC913 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 914) + #if defined(INT_VECTOR_PE0_IRQ_914) + INT_VECTOR_PE0_IRQ_914, /* EIC914 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 915) + #if defined(INT_VECTOR_PE0_IRQ_915) + INT_VECTOR_PE0_IRQ_915, /* EIC915 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 916) + #if defined(INT_VECTOR_PE0_IRQ_916) + INT_VECTOR_PE0_IRQ_916, /* EIC916 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 917) + #if defined(INT_VECTOR_PE0_IRQ_917) + INT_VECTOR_PE0_IRQ_917, /* EIC917 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 918) + #if defined(INT_VECTOR_PE0_IRQ_918) + INT_VECTOR_PE0_IRQ_918, /* EIC918 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 919) + #if defined(INT_VECTOR_PE0_IRQ_919) + INT_VECTOR_PE0_IRQ_919, /* EIC919 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 920) + #if defined(INT_VECTOR_PE0_IRQ_920) + INT_VECTOR_PE0_IRQ_920, /* EIC920 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 921) + #if defined(INT_VECTOR_PE0_IRQ_921) + INT_VECTOR_PE0_IRQ_921, /* EIC921 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 922) + #if defined(INT_VECTOR_PE0_IRQ_922) + INT_VECTOR_PE0_IRQ_922, /* EIC922 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 923) + #if defined(INT_VECTOR_PE0_IRQ_923) + INT_VECTOR_PE0_IRQ_923, /* EIC923 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 924) + #if defined(INT_VECTOR_PE0_IRQ_924) + INT_VECTOR_PE0_IRQ_924, /* EIC924 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 925) + #if defined(INT_VECTOR_PE0_IRQ_925) + INT_VECTOR_PE0_IRQ_925, /* EIC925 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 926) + #if defined(INT_VECTOR_PE0_IRQ_926) + INT_VECTOR_PE0_IRQ_926, /* EIC926 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 927) + #if defined(INT_VECTOR_PE0_IRQ_927) + INT_VECTOR_PE0_IRQ_927, /* EIC927 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 928) + #if defined(INT_VECTOR_PE0_IRQ_928) + INT_VECTOR_PE0_IRQ_928, /* EIC928 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 929) + #if defined(INT_VECTOR_PE0_IRQ_929) + INT_VECTOR_PE0_IRQ_929, /* EIC929 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 930) + #if defined(INT_VECTOR_PE0_IRQ_930) + INT_VECTOR_PE0_IRQ_930, /* EIC930 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 931) + #if defined(INT_VECTOR_PE0_IRQ_931) + INT_VECTOR_PE0_IRQ_931, /* EIC931 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 932) + #if defined(INT_VECTOR_PE0_IRQ_932) + INT_VECTOR_PE0_IRQ_932, /* EIC932 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 933) + #if defined(INT_VECTOR_PE0_IRQ_933) + INT_VECTOR_PE0_IRQ_933, /* EIC933 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 934) + #if defined(INT_VECTOR_PE0_IRQ_934) + INT_VECTOR_PE0_IRQ_934, /* EIC934 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 935) + #if defined(INT_VECTOR_PE0_IRQ_935) + INT_VECTOR_PE0_IRQ_935, /* EIC935 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 936) + #if defined(INT_VECTOR_PE0_IRQ_936) + INT_VECTOR_PE0_IRQ_936, /* EIC936 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 937) + #if defined(INT_VECTOR_PE0_IRQ_937) + INT_VECTOR_PE0_IRQ_937, /* EIC937 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 938) + #if defined(INT_VECTOR_PE0_IRQ_938) + INT_VECTOR_PE0_IRQ_938, /* EIC938 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 939) + #if defined(INT_VECTOR_PE0_IRQ_939) + INT_VECTOR_PE0_IRQ_939, /* EIC939 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 940) + #if defined(INT_VECTOR_PE0_IRQ_940) + INT_VECTOR_PE0_IRQ_940, /* EIC940 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 941) + #if defined(INT_VECTOR_PE0_IRQ_941) + INT_VECTOR_PE0_IRQ_941, /* EIC941 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 942) + #if defined(INT_VECTOR_PE0_IRQ_942) + INT_VECTOR_PE0_IRQ_942, /* EIC942 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 943) + #if defined(INT_VECTOR_PE0_IRQ_943) + INT_VECTOR_PE0_IRQ_943, /* EIC943 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 944) + #if defined(INT_VECTOR_PE0_IRQ_944) + INT_VECTOR_PE0_IRQ_944, /* EIC944 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 945) + #if defined(INT_VECTOR_PE0_IRQ_945) + INT_VECTOR_PE0_IRQ_945, /* EIC945 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 946) + #if defined(INT_VECTOR_PE0_IRQ_946) + INT_VECTOR_PE0_IRQ_946, /* EIC946 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 947) + #if defined(INT_VECTOR_PE0_IRQ_947) + INT_VECTOR_PE0_IRQ_947, /* EIC947 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 948) + #if defined(INT_VECTOR_PE0_IRQ_948) + INT_VECTOR_PE0_IRQ_948, /* EIC948 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 949) + #if defined(INT_VECTOR_PE0_IRQ_949) + INT_VECTOR_PE0_IRQ_949, /* EIC949 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 950) + #if defined(INT_VECTOR_PE0_IRQ_950) + INT_VECTOR_PE0_IRQ_950, /* EIC950 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 951) + #if defined(INT_VECTOR_PE0_IRQ_951) + INT_VECTOR_PE0_IRQ_951, /* EIC951 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 952) + #if defined(INT_VECTOR_PE0_IRQ_952) + INT_VECTOR_PE0_IRQ_952, /* EIC952 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 953) + #if defined(INT_VECTOR_PE0_IRQ_953) + INT_VECTOR_PE0_IRQ_953, /* EIC953 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 954) + #if defined(INT_VECTOR_PE0_IRQ_954) + INT_VECTOR_PE0_IRQ_954, /* EIC954 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 955) + #if defined(INT_VECTOR_PE0_IRQ_955) + INT_VECTOR_PE0_IRQ_955, /* EIC955 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 956) + #if defined(INT_VECTOR_PE0_IRQ_956) + INT_VECTOR_PE0_IRQ_956, /* EIC956 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 957) + #if defined(INT_VECTOR_PE0_IRQ_957) + INT_VECTOR_PE0_IRQ_957, /* EIC957 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 958) + #if defined(INT_VECTOR_PE0_IRQ_958) + INT_VECTOR_PE0_IRQ_958, /* EIC958 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 959) + #if defined(INT_VECTOR_PE0_IRQ_959) + INT_VECTOR_PE0_IRQ_959, /* EIC959 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 960) + #if defined(INT_VECTOR_PE0_IRQ_960) + INT_VECTOR_PE0_IRQ_960, /* EIC960 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 961) + #if defined(INT_VECTOR_PE0_IRQ_961) + INT_VECTOR_PE0_IRQ_961, /* EIC961 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 962) + #if defined(INT_VECTOR_PE0_IRQ_962) + INT_VECTOR_PE0_IRQ_962, /* EIC962 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 963) + #if defined(INT_VECTOR_PE0_IRQ_963) + INT_VECTOR_PE0_IRQ_963, /* EIC963 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 964) + #if defined(INT_VECTOR_PE0_IRQ_964) + INT_VECTOR_PE0_IRQ_964, /* EIC964 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 965) + #if defined(INT_VECTOR_PE0_IRQ_965) + INT_VECTOR_PE0_IRQ_965, /* EIC965 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 966) + #if defined(INT_VECTOR_PE0_IRQ_966) + INT_VECTOR_PE0_IRQ_966, /* EIC966 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 967) + #if defined(INT_VECTOR_PE0_IRQ_967) + INT_VECTOR_PE0_IRQ_967, /* EIC967 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 968) + #if defined(INT_VECTOR_PE0_IRQ_968) + INT_VECTOR_PE0_IRQ_968, /* EIC968 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 969) + #if defined(INT_VECTOR_PE0_IRQ_969) + INT_VECTOR_PE0_IRQ_969, /* EIC969 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 970) + #if defined(INT_VECTOR_PE0_IRQ_970) + INT_VECTOR_PE0_IRQ_970, /* EIC970 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 971) + #if defined(INT_VECTOR_PE0_IRQ_971) + INT_VECTOR_PE0_IRQ_971, /* EIC971 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 972) + #if defined(INT_VECTOR_PE0_IRQ_972) + INT_VECTOR_PE0_IRQ_972, /* EIC972 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 973) + #if defined(INT_VECTOR_PE0_IRQ_973) + INT_VECTOR_PE0_IRQ_973, /* EIC973 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 974) + #if defined(INT_VECTOR_PE0_IRQ_974) + INT_VECTOR_PE0_IRQ_974, /* EIC974 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 975) + #if defined(INT_VECTOR_PE0_IRQ_975) + INT_VECTOR_PE0_IRQ_975, /* EIC975 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 976) + #if defined(INT_VECTOR_PE0_IRQ_976) + INT_VECTOR_PE0_IRQ_976, /* EIC976 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 977) + #if defined(INT_VECTOR_PE0_IRQ_977) + INT_VECTOR_PE0_IRQ_977, /* EIC977 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 978) + #if defined(INT_VECTOR_PE0_IRQ_978) + INT_VECTOR_PE0_IRQ_978, /* EIC978 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 979) + #if defined(INT_VECTOR_PE0_IRQ_979) + INT_VECTOR_PE0_IRQ_979, /* EIC979 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 980) + #if defined(INT_VECTOR_PE0_IRQ_980) + INT_VECTOR_PE0_IRQ_980, /* EIC980 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 981) + #if defined(INT_VECTOR_PE0_IRQ_981) + INT_VECTOR_PE0_IRQ_981, /* EIC981 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 982) + #if defined(INT_VECTOR_PE0_IRQ_982) + INT_VECTOR_PE0_IRQ_982, /* EIC982 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 983) + #if defined(INT_VECTOR_PE0_IRQ_983) + INT_VECTOR_PE0_IRQ_983, /* EIC983 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 984) + #if defined(INT_VECTOR_PE0_IRQ_984) + INT_VECTOR_PE0_IRQ_984, /* EIC984 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 985) + #if defined(INT_VECTOR_PE0_IRQ_985) + INT_VECTOR_PE0_IRQ_985, /* EIC985 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 986) + #if defined(INT_VECTOR_PE0_IRQ_986) + INT_VECTOR_PE0_IRQ_986, /* EIC986 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 987) + #if defined(INT_VECTOR_PE0_IRQ_987) + INT_VECTOR_PE0_IRQ_987, /* EIC987 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 988) + #if defined(INT_VECTOR_PE0_IRQ_988) + INT_VECTOR_PE0_IRQ_988, /* EIC988 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 989) + #if defined(INT_VECTOR_PE0_IRQ_989) + INT_VECTOR_PE0_IRQ_989, /* EIC989 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 990) + #if defined(INT_VECTOR_PE0_IRQ_990) + INT_VECTOR_PE0_IRQ_990, /* EIC990 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 991) + #if defined(INT_VECTOR_PE0_IRQ_991) + INT_VECTOR_PE0_IRQ_991, /* EIC991 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 992) + #if defined(INT_VECTOR_PE0_IRQ_992) + INT_VECTOR_PE0_IRQ_992, /* EIC992 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 993) + #if defined(INT_VECTOR_PE0_IRQ_993) + INT_VECTOR_PE0_IRQ_993, /* EIC993 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 994) + #if defined(INT_VECTOR_PE0_IRQ_994) + INT_VECTOR_PE0_IRQ_994, /* EIC994 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 995) + #if defined(INT_VECTOR_PE0_IRQ_995) + INT_VECTOR_PE0_IRQ_995, /* EIC995 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 996) + #if defined(INT_VECTOR_PE0_IRQ_996) + INT_VECTOR_PE0_IRQ_996, /* EIC996 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 997) + #if defined(INT_VECTOR_PE0_IRQ_997) + INT_VECTOR_PE0_IRQ_997, /* EIC997 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 998) + #if defined(INT_VECTOR_PE0_IRQ_998) + INT_VECTOR_PE0_IRQ_998, /* EIC998 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 999) + #if defined(INT_VECTOR_PE0_IRQ_999) + INT_VECTOR_PE0_IRQ_999, /* EIC999 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1000) + #if defined(INT_VECTOR_PE0_IRQ_1000) + INT_VECTOR_PE0_IRQ_1000, /* EIC1000 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1001) + #if defined(INT_VECTOR_PE0_IRQ_1001) + INT_VECTOR_PE0_IRQ_1001, /* EIC1001 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1002) + #if defined(INT_VECTOR_PE0_IRQ_1002) + INT_VECTOR_PE0_IRQ_1002, /* EIC1002 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1003) + #if defined(INT_VECTOR_PE0_IRQ_1003) + INT_VECTOR_PE0_IRQ_1003, /* EIC1003 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1004) + #if defined(INT_VECTOR_PE0_IRQ_1004) + INT_VECTOR_PE0_IRQ_1004, /* EIC1004 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1005) + #if defined(INT_VECTOR_PE0_IRQ_1005) + INT_VECTOR_PE0_IRQ_1005, /* EIC1005 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1006) + #if defined(INT_VECTOR_PE0_IRQ_1006) + INT_VECTOR_PE0_IRQ_1006, /* EIC1006 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1007) + #if defined(INT_VECTOR_PE0_IRQ_1007) + INT_VECTOR_PE0_IRQ_1007, /* EIC1007 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1008) + #if defined(INT_VECTOR_PE0_IRQ_1008) + INT_VECTOR_PE0_IRQ_1008, /* EIC1008 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1009) + #if defined(INT_VECTOR_PE0_IRQ_1009) + INT_VECTOR_PE0_IRQ_1009, /* EIC1009 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1010) + #if defined(INT_VECTOR_PE0_IRQ_1010) + INT_VECTOR_PE0_IRQ_1010, /* EIC1010 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1011) + #if defined(INT_VECTOR_PE0_IRQ_1011) + INT_VECTOR_PE0_IRQ_1011, /* EIC1011 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1012) + #if defined(INT_VECTOR_PE0_IRQ_1012) + INT_VECTOR_PE0_IRQ_1012, /* EIC1012 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1013) + #if defined(INT_VECTOR_PE0_IRQ_1013) + INT_VECTOR_PE0_IRQ_1013, /* EIC1013 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1014) + #if defined(INT_VECTOR_PE0_IRQ_1014) + INT_VECTOR_PE0_IRQ_1014, /* EIC1014 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1015) + #if defined(INT_VECTOR_PE0_IRQ_1015) + INT_VECTOR_PE0_IRQ_1015, /* EIC1015 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1016) + #if defined(INT_VECTOR_PE0_IRQ_1016) + INT_VECTOR_PE0_IRQ_1016, /* EIC1016 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1017) + #if defined(INT_VECTOR_PE0_IRQ_1017) + INT_VECTOR_PE0_IRQ_1017, /* EIC1017 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1018) + #if defined(INT_VECTOR_PE0_IRQ_1018) + INT_VECTOR_PE0_IRQ_1018, /* EIC1018 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1019) + #if defined(INT_VECTOR_PE0_IRQ_1019) + INT_VECTOR_PE0_IRQ_1019, /* EIC1019 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1020) + #if defined(INT_VECTOR_PE0_IRQ_1020) + INT_VECTOR_PE0_IRQ_1020, /* EIC1020 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1021) + #if defined(INT_VECTOR_PE0_IRQ_1021) + INT_VECTOR_PE0_IRQ_1021, /* EIC1021 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1022) + #if defined(INT_VECTOR_PE0_IRQ_1022) + INT_VECTOR_PE0_IRQ_1022, /* EIC1022 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1023) + #if defined(INT_VECTOR_PE0_IRQ_1023) + INT_VECTOR_PE0_IRQ_1023, /* EIC1023 */ + #else + INT_PE0_DUMMY_IRQ, + #endif + #endif +}; +__PRAGMA_PLACE_IN_SECTION(BSP_PRAGMA_SECTION_DATA, BSP_PRAGMA_SECTION_DEFAULT) +#endif diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE1.c b/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE1.c new file mode 100644 index 0000000000000000000000000000000000000000..2215cb1986c37878a92f4e9a4d2a62a2e4f7b0dc --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/Interrupt_VectorTable_PE1.c @@ -0,0 +1,8245 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*******************************************************************************************************************//** + * @file Interrupt_VectorTable_PE0.h + * @brief Interrupt vector table for PE1 + * @version V0.0.1 + * @date 01. Jan 2026 + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if CONFIG_BSP_FSP_SUPPORT +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif + + +/*********************************************************************************************************************** + * Private functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Dummy ISR. + **********************************************************************************************************************/ +#define INT_PE0_DUMMY_IRQ ((const void (*)(void))Irq_Handler) +#ifndef INT_PE1_DUMMY_IRQ + extern BSP_INTERRUPT_ATTRIBUTE void DummyIsr(void); +#define INT_PE1_DUMMY_IRQ DummyIsr +#else + extern BSP_INTERRUPT_ATTRIBUTE void Irq_Handler(void); +#endif +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ +#if (BSP_PE1_USED) + #if defined(__ICCRH850__) +typedef void (__cc_version1 __interrupt * VectorTableType)(void); +const VectorTableType IntVectors_PE1[BSP_INTC_INTBP_MAX_ENTRIES] __attribute__((section(BSP_PRAGMA_SECTION_INTVECT_PE1))) +__attribute__((__used__)) = + #else +#pragma ghs section data=".inttable_PE1" +const void (* IntVectors_PE1[BSP_INTC_INTBP_MAX_ENTRIES])(void) = + #endif /* #if defined(__ICCRH850__) */ +{ + #if (BSP_INTC_INTBP_MAX_ENTRIES > 0) + #if defined(INT_VECTOR_PE1_IRQ_000) + INT_VECTOR_PE1_IRQ_000, /* EIC0 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1) + #if defined(INT_VECTOR_PE1_IRQ_001) + INT_VECTOR_PE1_IRQ_001, /* EIC1 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 2) + #if defined(INT_VECTOR_PE1_IRQ_002) + INT_VECTOR_PE1_IRQ_002, /* EIC2 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 3) + #if defined(INT_VECTOR_PE1_IRQ_003) + INT_VECTOR_PE1_IRQ_003, /* EIC3 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 4) + #if defined(INT_VECTOR_PE1_IRQ_004) + INT_VECTOR_PE1_IRQ_004, /* EIC4 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 5) + #if defined(INT_VECTOR_PE1_IRQ_005) + INT_VECTOR_PE1_IRQ_005, /* EIC5 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 6) + #if defined(INT_VECTOR_PE1_IRQ_006) + INT_VECTOR_PE1_IRQ_006, /* EIC6 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 7) + #if defined(INT_VECTOR_PE1_IRQ_007) + INT_VECTOR_PE1_IRQ_007, /* EIC7 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 8) + #if defined(INT_VECTOR_PE1_IRQ_008) + INT_VECTOR_PE1_IRQ_008, /* EIC8 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 9) + #if defined(INT_VECTOR_PE1_IRQ_009) + INT_VECTOR_PE1_IRQ_009, /* EIC9 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 10) + #if defined(INT_VECTOR_PE1_IRQ_010) + INT_VECTOR_PE1_IRQ_010, /* EIC10 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 11) + #if defined(INT_VECTOR_PE1_IRQ_011) + INT_VECTOR_PE1_IRQ_011, /* EIC11 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 12) + #if defined(INT_VECTOR_PE1_IRQ_012) + INT_VECTOR_PE1_IRQ_012, /* EIC12 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 13) + #if defined(INT_VECTOR_PE1_IRQ_013) + INT_VECTOR_PE1_IRQ_013, /* EIC13 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 14) + #if defined(INT_VECTOR_PE1_IRQ_014) + INT_VECTOR_PE1_IRQ_014, /* EIC14 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 15) + #if defined(INT_VECTOR_PE1_IRQ_015) + INT_VECTOR_PE1_IRQ_015, /* EIC15 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 16) + #if defined(INT_VECTOR_PE1_IRQ_016) + INT_VECTOR_PE1_IRQ_016, /* EIC16 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 17) + #if defined(INT_VECTOR_PE1_IRQ_017) + INT_VECTOR_PE1_IRQ_017, /* EIC17 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 18) + #if defined(INT_VECTOR_PE1_IRQ_018) + INT_VECTOR_PE1_IRQ_018, /* EIC18 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 19) + #if defined(INT_VECTOR_PE1_IRQ_019) + INT_VECTOR_PE1_IRQ_019, /* EIC19 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 20) + #if defined(INT_VECTOR_PE1_IRQ_020) + INT_VECTOR_PE1_IRQ_020, /* EIC20 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 21) + #if defined(INT_VECTOR_PE1_IRQ_021) + INT_VECTOR_PE1_IRQ_021, /* EIC21 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 22) + #if defined(INT_VECTOR_PE1_IRQ_022) + INT_VECTOR_PE1_IRQ_022, /* EIC22 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 23) + #if defined(INT_VECTOR_PE1_IRQ_023) + INT_VECTOR_PE1_IRQ_023, /* EIC23 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 24) + #if defined(INT_VECTOR_PE1_IRQ_024) + INT_VECTOR_PE1_IRQ_024, /* EIC24 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 25) + #if defined(INT_VECTOR_PE1_IRQ_025) + INT_VECTOR_PE1_IRQ_025, /* EIC25 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 26) + #if defined(INT_VECTOR_PE1_IRQ_026) + INT_VECTOR_PE1_IRQ_026, /* EIC26 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 27) + #if defined(INT_VECTOR_PE1_IRQ_027) + INT_VECTOR_PE1_IRQ_027, /* EIC27 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 28) + #if defined(INT_VECTOR_PE1_IRQ_028) + INT_VECTOR_PE1_IRQ_028, /* EIC28 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 29) + #if defined(INT_VECTOR_PE1_IRQ_029) + INT_VECTOR_PE1_IRQ_029, /* EIC29 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 30) + #if defined(INT_VECTOR_PE1_IRQ_030) + INT_VECTOR_PE1_IRQ_030, /* EIC30 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 31) + #if defined(INT_VECTOR_PE1_IRQ_031) + INT_VECTOR_PE1_IRQ_031, /* EIC31 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 32) + #if defined(INT_VECTOR_PE1_IRQ_032) + INT_VECTOR_PE1_IRQ_032, /* EIC32 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 33) + #if defined(INT_VECTOR_PE1_IRQ_033) + INT_VECTOR_PE1_IRQ_033, /* EIC33 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 34) + #if defined(INT_VECTOR_PE1_IRQ_034) + INT_VECTOR_PE1_IRQ_034, /* EIC34 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 35) + #if defined(INT_VECTOR_PE1_IRQ_035) + INT_VECTOR_PE1_IRQ_035, /* EIC35 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 36) + #if defined(INT_VECTOR_PE1_IRQ_036) + INT_VECTOR_PE1_IRQ_036, /* EIC36 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 37) + #if defined(INT_VECTOR_PE1_IRQ_037) + INT_VECTOR_PE1_IRQ_037, /* EIC37 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 38) + #if defined(INT_VECTOR_PE1_IRQ_038) + INT_VECTOR_PE1_IRQ_038, /* EIC38 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 39) + #if defined(INT_VECTOR_PE1_IRQ_039) + INT_VECTOR_PE1_IRQ_039, /* EIC39 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 40) + #if defined(INT_VECTOR_PE1_IRQ_040) + INT_VECTOR_PE1_IRQ_040, /* EIC40 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 41) + #if defined(INT_VECTOR_PE1_IRQ_041) + INT_VECTOR_PE1_IRQ_041, /* EIC41 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 42) + #if defined(INT_VECTOR_PE1_IRQ_042) + INT_VECTOR_PE1_IRQ_042, /* EIC42 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 43) + #if defined(INT_VECTOR_PE1_IRQ_043) + INT_VECTOR_PE1_IRQ_043, /* EIC43 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 44) + #if defined(INT_VECTOR_PE1_IRQ_044) + INT_VECTOR_PE1_IRQ_044, /* EIC44 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 45) + #if defined(INT_VECTOR_PE1_IRQ_045) + INT_VECTOR_PE1_IRQ_045, /* EIC45 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 46) + #if defined(INT_VECTOR_PE1_IRQ_046) + INT_VECTOR_PE1_IRQ_046, /* EIC46 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 47) + #if defined(INT_VECTOR_PE1_IRQ_047) + INT_VECTOR_PE1_IRQ_047, /* EIC47 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 48) + #if defined(INT_VECTOR_PE1_IRQ_048) + INT_VECTOR_PE1_IRQ_048, /* EIC48 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 49) + #if defined(INT_VECTOR_PE1_IRQ_049) + INT_VECTOR_PE1_IRQ_049, /* EIC49 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 50) + #if defined(INT_VECTOR_PE1_IRQ_050) + INT_VECTOR_PE1_IRQ_050, /* EIC50 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 51) + #if defined(INT_VECTOR_PE1_IRQ_051) + INT_VECTOR_PE1_IRQ_051, /* EIC51 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 52) + #if defined(INT_VECTOR_PE1_IRQ_052) + INT_VECTOR_PE1_IRQ_052, /* EIC52 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 53) + #if defined(INT_VECTOR_PE1_IRQ_053) + INT_VECTOR_PE1_IRQ_053, /* EIC53 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 54) + #if defined(INT_VECTOR_PE1_IRQ_054) + INT_VECTOR_PE1_IRQ_054, /* EIC54 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 55) + #if defined(INT_VECTOR_PE1_IRQ_055) + INT_VECTOR_PE1_IRQ_055, /* EIC55 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 56) + #if defined(INT_VECTOR_PE1_IRQ_056) + INT_VECTOR_PE1_IRQ_056, /* EIC56 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 57) + #if defined(INT_VECTOR_PE1_IRQ_057) + INT_VECTOR_PE1_IRQ_057, /* EIC57 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 58) + #if defined(INT_VECTOR_PE1_IRQ_058) + INT_VECTOR_PE1_IRQ_058, /* EIC58 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 59) + #if defined(INT_VECTOR_PE1_IRQ_059) + INT_VECTOR_PE1_IRQ_059, /* EIC59 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 60) + #if defined(INT_VECTOR_PE1_IRQ_060) + INT_VECTOR_PE1_IRQ_060, /* EIC60 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 61) + #if defined(INT_VECTOR_PE1_IRQ_061) + INT_VECTOR_PE1_IRQ_061, /* EIC61 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 62) + #if defined(INT_VECTOR_PE1_IRQ_062) + INT_VECTOR_PE1_IRQ_062, /* EIC62 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 63) + #if defined(INT_VECTOR_PE1_IRQ_063) + INT_VECTOR_PE1_IRQ_063, /* EIC63 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 64) + #if defined(INT_VECTOR_PE1_IRQ_064) + INT_VECTOR_PE1_IRQ_064, /* EIC64 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 65) + #if defined(INT_VECTOR_PE1_IRQ_065) + INT_VECTOR_PE1_IRQ_065, /* EIC65 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 66) + #if defined(INT_VECTOR_PE1_IRQ_066) + INT_VECTOR_PE1_IRQ_066, /* EIC66 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 67) + #if defined(INT_VECTOR_PE1_IRQ_067) + INT_VECTOR_PE1_IRQ_067, /* EIC67 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 68) + #if defined(INT_VECTOR_PE1_IRQ_068) + INT_VECTOR_PE1_IRQ_068, /* EIC68 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 69) + #if defined(INT_VECTOR_PE1_IRQ_069) + INT_VECTOR_PE1_IRQ_069, /* EIC69 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 70) + #if defined(INT_VECTOR_PE1_IRQ_070) + INT_VECTOR_PE1_IRQ_070, /* EIC70 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 71) + #if defined(INT_VECTOR_PE1_IRQ_071) + INT_VECTOR_PE1_IRQ_071, /* EIC71 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 72) + #if defined(INT_VECTOR_PE1_IRQ_072) + INT_VECTOR_PE1_IRQ_072, /* EIC72 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 73) + #if defined(INT_VECTOR_PE1_IRQ_073) + INT_VECTOR_PE1_IRQ_073, /* EIC73 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 74) + #if defined(INT_VECTOR_PE1_IRQ_074) + INT_VECTOR_PE1_IRQ_074, /* EIC74 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 75) + #if defined(INT_VECTOR_PE1_IRQ_075) + INT_VECTOR_PE1_IRQ_075, /* EIC75 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 76) + #if defined(INT_VECTOR_PE1_IRQ_076) + INT_VECTOR_PE1_IRQ_076, /* EIC76 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 77) + #if defined(INT_VECTOR_PE1_IRQ_077) + INT_VECTOR_PE1_IRQ_077, /* EIC77 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 78) + #if defined(INT_VECTOR_PE1_IRQ_078) + INT_VECTOR_PE1_IRQ_078, /* EIC78 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 79) + #if defined(INT_VECTOR_PE1_IRQ_079) + INT_VECTOR_PE1_IRQ_079, /* EIC79 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 80) + #if defined(INT_VECTOR_PE1_IRQ_080) + INT_VECTOR_PE1_IRQ_080, /* EIC80 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 81) + #if defined(INT_VECTOR_PE1_IRQ_081) + INT_VECTOR_PE1_IRQ_081, /* EIC81 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 82) + #if defined(INT_VECTOR_PE1_IRQ_082) + INT_VECTOR_PE1_IRQ_082, /* EIC82 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 83) + #if defined(INT_VECTOR_PE1_IRQ_083) + INT_VECTOR_PE1_IRQ_083, /* EIC83 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 84) + #if defined(INT_VECTOR_PE1_IRQ_084) + INT_VECTOR_PE1_IRQ_084, /* EIC84 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 85) + #if defined(INT_VECTOR_PE1_IRQ_085) + INT_VECTOR_PE1_IRQ_085, /* EIC85 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 86) + #if defined(INT_VECTOR_PE1_IRQ_086) + INT_VECTOR_PE1_IRQ_086, /* EIC86 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 87) + #if defined(INT_VECTOR_PE1_IRQ_087) + INT_VECTOR_PE1_IRQ_087, /* EIC87 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 88) + #if defined(INT_VECTOR_PE1_IRQ_088) + INT_VECTOR_PE1_IRQ_088, /* EIC88 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 89) + #if defined(INT_VECTOR_PE1_IRQ_089) + INT_VECTOR_PE1_IRQ_089, /* EIC89 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 90) + #if defined(INT_VECTOR_PE1_IRQ_090) + INT_VECTOR_PE1_IRQ_090, /* EIC90 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 91) + #if defined(INT_VECTOR_PE1_IRQ_091) + INT_VECTOR_PE1_IRQ_091, /* EIC91 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 92) + #if defined(INT_VECTOR_PE1_IRQ_092) + INT_VECTOR_PE1_IRQ_092, /* EIC92 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 93) + #if defined(INT_VECTOR_PE1_IRQ_093) + INT_VECTOR_PE1_IRQ_093, /* EIC93 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 94) + #if defined(INT_VECTOR_PE1_IRQ_094) + INT_VECTOR_PE1_IRQ_094, /* EIC94 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 95) + #if defined(INT_VECTOR_PE1_IRQ_095) + INT_VECTOR_PE1_IRQ_095, /* EIC95 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 96) + #if defined(INT_VECTOR_PE1_IRQ_096) + INT_VECTOR_PE1_IRQ_096, /* EIC96 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 97) + #if defined(INT_VECTOR_PE1_IRQ_097) + INT_VECTOR_PE1_IRQ_097, /* EIC97 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 98) + #if defined(INT_VECTOR_PE1_IRQ_098) + INT_VECTOR_PE1_IRQ_098, /* EIC98 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 99) + #if defined(INT_VECTOR_PE1_IRQ_099) + INT_VECTOR_PE1_IRQ_099, /* EIC99 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 100) + #if defined(INT_VECTOR_PE1_IRQ_100) + INT_VECTOR_PE1_IRQ_100, /* EIC100 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 101) + #if defined(INT_VECTOR_PE1_IRQ_101) + INT_VECTOR_PE1_IRQ_101, /* EIC101 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 102) + #if defined(INT_VECTOR_PE1_IRQ_102) + INT_VECTOR_PE1_IRQ_102, /* EIC102 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 103) + #if defined(INT_VECTOR_PE1_IRQ_103) + INT_VECTOR_PE1_IRQ_103, /* EIC103 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 104) + #if defined(INT_VECTOR_PE1_IRQ_104) + INT_VECTOR_PE1_IRQ_104, /* EIC104 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 105) + #if defined(INT_VECTOR_PE1_IRQ_105) + INT_VECTOR_PE1_IRQ_105, /* EIC105 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 106) + #if defined(INT_VECTOR_PE1_IRQ_106) + INT_VECTOR_PE1_IRQ_106, /* EIC106 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 107) + #if defined(INT_VECTOR_PE1_IRQ_107) + INT_VECTOR_PE1_IRQ_107, /* EIC107 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 108) + #if defined(INT_VECTOR_PE1_IRQ_108) + INT_VECTOR_PE1_IRQ_108, /* EIC108 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 109) + #if defined(INT_VECTOR_PE1_IRQ_109) + INT_VECTOR_PE1_IRQ_109, /* EIC109 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 110) + #if defined(INT_VECTOR_PE1_IRQ_110) + INT_VECTOR_PE1_IRQ_110, /* EIC110 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 111) + #if defined(INT_VECTOR_PE1_IRQ_111) + INT_VECTOR_PE1_IRQ_111, /* EIC111 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 112) + #if defined(INT_VECTOR_PE1_IRQ_112) + INT_VECTOR_PE1_IRQ_112, /* EIC112 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 113) + #if defined(INT_VECTOR_PE1_IRQ_113) + INT_VECTOR_PE1_IRQ_113, /* EIC113 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 114) + #if defined(INT_VECTOR_PE1_IRQ_114) + INT_VECTOR_PE1_IRQ_114, /* EIC114 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 115) + #if defined(INT_VECTOR_PE1_IRQ_115) + INT_VECTOR_PE1_IRQ_115, /* EIC115 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 116) + #if defined(INT_VECTOR_PE1_IRQ_116) + INT_VECTOR_PE1_IRQ_116, /* EIC116 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 117) + #if defined(INT_VECTOR_PE1_IRQ_117) + INT_VECTOR_PE1_IRQ_117, /* EIC117 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 118) + #if defined(INT_VECTOR_PE1_IRQ_118) + INT_VECTOR_PE1_IRQ_118, /* EIC118 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 119) + #if defined(INT_VECTOR_PE1_IRQ_119) + INT_VECTOR_PE1_IRQ_119, /* EIC119 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 120) + #if defined(INT_VECTOR_PE1_IRQ_120) + INT_VECTOR_PE1_IRQ_120, /* EIC120 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 121) + #if defined(INT_VECTOR_PE1_IRQ_121) + INT_VECTOR_PE1_IRQ_121, /* EIC121 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 122) + #if defined(INT_VECTOR_PE1_IRQ_122) + INT_VECTOR_PE1_IRQ_122, /* EIC122 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 123) + #if defined(INT_VECTOR_PE1_IRQ_123) + INT_VECTOR_PE1_IRQ_123, /* EIC123 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 124) + #if defined(INT_VECTOR_PE1_IRQ_124) + INT_VECTOR_PE1_IRQ_124, /* EIC124 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 125) + #if defined(INT_VECTOR_PE1_IRQ_125) + INT_VECTOR_PE1_IRQ_125, /* EIC125 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 126) + #if defined(INT_VECTOR_PE1_IRQ_126) + INT_VECTOR_PE1_IRQ_126, /* EIC126 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 127) + #if defined(INT_VECTOR_PE1_IRQ_127) + INT_VECTOR_PE1_IRQ_127, /* EIC127 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 128) + #if defined(INT_VECTOR_PE1_IRQ_128) + INT_VECTOR_PE1_IRQ_128, /* EIC128 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 129) + #if defined(INT_VECTOR_PE1_IRQ_129) + INT_VECTOR_PE1_IRQ_129, /* EIC129 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 130) + #if defined(INT_VECTOR_PE1_IRQ_130) + INT_VECTOR_PE1_IRQ_130, /* EIC130 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 131) + #if defined(INT_VECTOR_PE1_IRQ_131) + INT_VECTOR_PE1_IRQ_131, /* EIC131 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 132) + #if defined(INT_VECTOR_PE1_IRQ_132) + INT_VECTOR_PE1_IRQ_132, /* EIC132 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 133) + #if defined(INT_VECTOR_PE1_IRQ_133) + INT_VECTOR_PE1_IRQ_133, /* EIC133 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 134) + #if defined(INT_VECTOR_PE1_IRQ_134) + INT_VECTOR_PE1_IRQ_134, /* EIC134 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 135) + #if defined(INT_VECTOR_PE1_IRQ_135) + INT_VECTOR_PE1_IRQ_135, /* EIC135 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 136) + #if defined(INT_VECTOR_PE1_IRQ_136) + INT_VECTOR_PE1_IRQ_136, /* EIC136 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 137) + #if defined(INT_VECTOR_PE1_IRQ_137) + INT_VECTOR_PE1_IRQ_137, /* EIC137 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 138) + #if defined(INT_VECTOR_PE1_IRQ_138) + INT_VECTOR_PE1_IRQ_138, /* EIC138 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 139) + #if defined(INT_VECTOR_PE1_IRQ_139) + INT_VECTOR_PE1_IRQ_139, /* EIC139 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 140) + #if defined(INT_VECTOR_PE1_IRQ_140) + INT_VECTOR_PE1_IRQ_140, /* EIC140 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 141) + #if defined(INT_VECTOR_PE1_IRQ_141) + INT_VECTOR_PE1_IRQ_141, /* EIC141 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 142) + #if defined(INT_VECTOR_PE1_IRQ_142) + INT_VECTOR_PE1_IRQ_142, /* EIC142 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 143) + #if defined(INT_VECTOR_PE1_IRQ_143) + INT_VECTOR_PE1_IRQ_143, /* EIC143 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 144) + #if defined(INT_VECTOR_PE1_IRQ_144) + INT_VECTOR_PE1_IRQ_144, /* EIC144 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 145) + #if defined(INT_VECTOR_PE1_IRQ_145) + INT_VECTOR_PE1_IRQ_145, /* EIC145 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 146) + #if defined(INT_VECTOR_PE1_IRQ_146) + INT_VECTOR_PE1_IRQ_146, /* EIC146 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 147) + #if defined(INT_VECTOR_PE1_IRQ_147) + INT_VECTOR_PE1_IRQ_147, /* EIC147 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 148) + #if defined(INT_VECTOR_PE1_IRQ_148) + INT_VECTOR_PE1_IRQ_148, /* EIC148 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 149) + #if defined(INT_VECTOR_PE1_IRQ_149) + INT_VECTOR_PE1_IRQ_149, /* EIC149 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 150) + #if defined(INT_VECTOR_PE1_IRQ_150) + INT_VECTOR_PE1_IRQ_150, /* EIC150 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 151) + #if defined(INT_VECTOR_PE1_IRQ_151) + INT_VECTOR_PE1_IRQ_151, /* EIC151 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 152) + #if defined(INT_VECTOR_PE1_IRQ_152) + INT_VECTOR_PE1_IRQ_152, /* EIC152 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 153) + #if defined(INT_VECTOR_PE1_IRQ_153) + INT_VECTOR_PE1_IRQ_153, /* EIC153 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 154) + #if defined(INT_VECTOR_PE1_IRQ_154) + INT_VECTOR_PE1_IRQ_154, /* EIC154 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 155) + #if defined(INT_VECTOR_PE1_IRQ_155) + INT_VECTOR_PE1_IRQ_155, /* EIC155 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 156) + #if defined(INT_VECTOR_PE1_IRQ_156) + INT_VECTOR_PE1_IRQ_156, /* EIC156 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 157) + #if defined(INT_VECTOR_PE1_IRQ_157) + INT_VECTOR_PE1_IRQ_157, /* EIC157 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 158) + #if defined(INT_VECTOR_PE1_IRQ_158) + INT_VECTOR_PE1_IRQ_158, /* EIC158 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 159) + #if defined(INT_VECTOR_PE1_IRQ_159) + INT_VECTOR_PE1_IRQ_159, /* EIC159 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 160) + #if defined(INT_VECTOR_PE1_IRQ_160) + INT_VECTOR_PE1_IRQ_160, /* EIC160 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 161) + #if defined(INT_VECTOR_PE1_IRQ_161) + INT_VECTOR_PE1_IRQ_161, /* EIC161 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 162) + #if defined(INT_VECTOR_PE1_IRQ_162) + INT_VECTOR_PE1_IRQ_162, /* EIC162 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 163) + #if defined(INT_VECTOR_PE1_IRQ_163) + INT_VECTOR_PE1_IRQ_163, /* EIC163 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 164) + #if defined(INT_VECTOR_PE1_IRQ_164) + INT_VECTOR_PE1_IRQ_164, /* EIC164 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 165) + #if defined(INT_VECTOR_PE1_IRQ_165) + INT_VECTOR_PE1_IRQ_165, /* EIC165 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 166) + #if defined(INT_VECTOR_PE1_IRQ_166) + INT_VECTOR_PE1_IRQ_166, /* EIC166 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 167) + #if defined(INT_VECTOR_PE1_IRQ_167) + INT_VECTOR_PE1_IRQ_167, /* EIC167 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 168) + #if defined(INT_VECTOR_PE1_IRQ_168) + INT_VECTOR_PE1_IRQ_168, /* EIC168 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 169) + #if defined(INT_VECTOR_PE1_IRQ_169) + INT_VECTOR_PE1_IRQ_169, /* EIC169 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 170) + #if defined(INT_VECTOR_PE1_IRQ_170) + INT_VECTOR_PE1_IRQ_170, /* EIC170 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 171) + #if defined(INT_VECTOR_PE1_IRQ_171) + INT_VECTOR_PE1_IRQ_171, /* EIC171 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 172) + #if defined(INT_VECTOR_PE1_IRQ_172) + INT_VECTOR_PE1_IRQ_172, /* EIC172 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 173) + #if defined(INT_VECTOR_PE1_IRQ_173) + INT_VECTOR_PE1_IRQ_173, /* EIC173 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 174) + #if defined(INT_VECTOR_PE1_IRQ_174) + INT_VECTOR_PE1_IRQ_174, /* EIC174 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 175) + #if defined(INT_VECTOR_PE1_IRQ_175) + INT_VECTOR_PE1_IRQ_175, /* EIC175 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 176) + #if defined(INT_VECTOR_PE1_IRQ_176) + INT_VECTOR_PE1_IRQ_176, /* EIC176 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 177) + #if defined(INT_VECTOR_PE1_IRQ_177) + INT_VECTOR_PE1_IRQ_177, /* EIC177 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 178) + #if defined(INT_VECTOR_PE1_IRQ_178) + INT_VECTOR_PE1_IRQ_178, /* EIC178 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 179) + #if defined(INT_VECTOR_PE1_IRQ_179) + INT_VECTOR_PE1_IRQ_179, /* EIC179 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 180) + #if defined(INT_VECTOR_PE1_IRQ_180) + INT_VECTOR_PE1_IRQ_180, /* EIC180 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 181) + #if defined(INT_VECTOR_PE1_IRQ_181) + INT_VECTOR_PE1_IRQ_181, /* EIC181 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 182) + #if defined(INT_VECTOR_PE1_IRQ_182) + INT_VECTOR_PE1_IRQ_182, /* EIC182 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 183) + #if defined(INT_VECTOR_PE1_IRQ_183) + INT_VECTOR_PE1_IRQ_183, /* EIC183 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 184) + #if defined(INT_VECTOR_PE1_IRQ_184) + INT_VECTOR_PE1_IRQ_184, /* EIC184 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 185) + #if defined(INT_VECTOR_PE1_IRQ_185) + INT_VECTOR_PE1_IRQ_185, /* EIC185 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 186) + #if defined(INT_VECTOR_PE1_IRQ_186) + INT_VECTOR_PE1_IRQ_186, /* EIC186 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 187) + #if defined(INT_VECTOR_PE1_IRQ_187) + INT_VECTOR_PE1_IRQ_187, /* EIC187 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 188) + #if defined(INT_VECTOR_PE1_IRQ_188) + INT_VECTOR_PE1_IRQ_188, /* EIC188 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 189) + #if defined(INT_VECTOR_PE1_IRQ_189) + INT_VECTOR_PE1_IRQ_189, /* EIC189 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 190) + #if defined(INT_VECTOR_PE1_IRQ_190) + INT_VECTOR_PE1_IRQ_190, /* EIC190 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 191) + #if defined(INT_VECTOR_PE1_IRQ_191) + INT_VECTOR_PE1_IRQ_191, /* EIC191 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 192) + #if defined(INT_VECTOR_PE1_IRQ_192) + INT_VECTOR_PE1_IRQ_192, /* EIC192 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 193) + #if defined(INT_VECTOR_PE1_IRQ_193) + INT_VECTOR_PE1_IRQ_193, /* EIC193 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 194) + #if defined(INT_VECTOR_PE1_IRQ_194) + INT_VECTOR_PE1_IRQ_194, /* EIC194 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 195) + #if defined(INT_VECTOR_PE1_IRQ_195) + INT_VECTOR_PE1_IRQ_195, /* EIC195 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 196) + #if defined(INT_VECTOR_PE1_IRQ_196) + INT_VECTOR_PE1_IRQ_196, /* EIC196 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 197) + #if defined(INT_VECTOR_PE1_IRQ_197) + INT_VECTOR_PE1_IRQ_197, /* EIC197 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 198) + #if defined(INT_VECTOR_PE1_IRQ_198) + INT_VECTOR_PE1_IRQ_198, /* EIC198 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 199) + #if defined(INT_VECTOR_PE1_IRQ_199) + INT_VECTOR_PE1_IRQ_199, /* EIC199 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 200) + #if defined(INT_VECTOR_PE1_IRQ_200) + INT_VECTOR_PE1_IRQ_200, /* EIC200 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 201) + #if defined(INT_VECTOR_PE1_IRQ_201) + INT_VECTOR_PE1_IRQ_201, /* EIC201 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 202) + #if defined(INT_VECTOR_PE1_IRQ_202) + INT_VECTOR_PE1_IRQ_202, /* EIC202 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 203) + #if defined(INT_VECTOR_PE1_IRQ_203) + INT_VECTOR_PE1_IRQ_203, /* EIC203 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 204) + #if defined(INT_VECTOR_PE1_IRQ_204) + INT_VECTOR_PE1_IRQ_204, /* EIC204 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 205) + #if defined(INT_VECTOR_PE1_IRQ_205) + INT_VECTOR_PE1_IRQ_205, /* EIC205 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 206) + #if defined(INT_VECTOR_PE1_IRQ_206) + INT_VECTOR_PE1_IRQ_206, /* EIC206 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 207) + #if defined(INT_VECTOR_PE1_IRQ_207) + INT_VECTOR_PE1_IRQ_207, /* EIC207 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 208) + #if defined(INT_VECTOR_PE1_IRQ_208) + INT_VECTOR_PE1_IRQ_208, /* EIC208 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 209) + #if defined(INT_VECTOR_PE1_IRQ_209) + INT_VECTOR_PE1_IRQ_209, /* EIC209 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 210) + #if defined(INT_VECTOR_PE1_IRQ_210) + INT_VECTOR_PE1_IRQ_210, /* EIC210 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 211) + #if defined(INT_VECTOR_PE1_IRQ_211) + INT_VECTOR_PE1_IRQ_211, /* EIC211 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 212) + #if defined(INT_VECTOR_PE1_IRQ_212) + INT_VECTOR_PE1_IRQ_212, /* EIC212 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 213) + #if defined(INT_VECTOR_PE1_IRQ_213) + INT_VECTOR_PE1_IRQ_213, /* EIC213 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 214) + #if defined(INT_VECTOR_PE1_IRQ_214) + INT_VECTOR_PE1_IRQ_214, /* EIC214 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 215) + #if defined(INT_VECTOR_PE1_IRQ_215) + INT_VECTOR_PE1_IRQ_215, /* EIC215 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 216) + #if defined(INT_VECTOR_PE1_IRQ_216) + INT_VECTOR_PE1_IRQ_216, /* EIC216 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 217) + #if defined(INT_VECTOR_PE1_IRQ_217) + INT_VECTOR_PE1_IRQ_217, /* EIC217 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 218) + #if defined(INT_VECTOR_PE1_IRQ_218) + INT_VECTOR_PE1_IRQ_218, /* EIC218 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 219) + #if defined(INT_VECTOR_PE1_IRQ_219) + INT_VECTOR_PE1_IRQ_219, /* EIC219 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 220) + #if defined(INT_VECTOR_PE1_IRQ_220) + INT_VECTOR_PE1_IRQ_220, /* EIC220 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 221) + #if defined(INT_VECTOR_PE1_IRQ_221) + INT_VECTOR_PE1_IRQ_221, /* EIC221 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 222) + #if defined(INT_VECTOR_PE1_IRQ_222) + INT_VECTOR_PE1_IRQ_222, /* EIC222 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 223) + #if defined(INT_VECTOR_PE1_IRQ_223) + INT_VECTOR_PE1_IRQ_223, /* EIC223 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 224) + #if defined(INT_VECTOR_PE1_IRQ_224) + INT_VECTOR_PE1_IRQ_224, /* EIC224 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 225) + #if defined(INT_VECTOR_PE1_IRQ_225) + INT_VECTOR_PE1_IRQ_225, /* EIC225 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 226) + #if defined(INT_VECTOR_PE1_IRQ_226) + INT_VECTOR_PE1_IRQ_226, /* EIC226 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 227) + #if defined(INT_VECTOR_PE1_IRQ_227) + INT_VECTOR_PE1_IRQ_227, /* EIC227 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 228) + #if defined(INT_VECTOR_PE1_IRQ_228) + INT_VECTOR_PE1_IRQ_228, /* EIC228 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 229) + #if defined(INT_VECTOR_PE1_IRQ_229) + INT_VECTOR_PE1_IRQ_229, /* EIC229 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 230) + #if defined(INT_VECTOR_PE1_IRQ_230) + INT_VECTOR_PE1_IRQ_230, /* EIC230 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 231) + #if defined(INT_VECTOR_PE1_IRQ_231) + INT_VECTOR_PE1_IRQ_231, /* EIC231 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 232) + #if defined(INT_VECTOR_PE1_IRQ_232) + INT_VECTOR_PE1_IRQ_232, /* EIC232 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 233) + #if defined(INT_VECTOR_PE1_IRQ_233) + INT_VECTOR_PE1_IRQ_233, /* EIC233 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 234) + #if defined(INT_VECTOR_PE1_IRQ_234) + INT_VECTOR_PE1_IRQ_234, /* EIC234 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 235) + #if defined(INT_VECTOR_PE1_IRQ_235) + INT_VECTOR_PE1_IRQ_235, /* EIC235 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 236) + #if defined(INT_VECTOR_PE1_IRQ_236) + INT_VECTOR_PE1_IRQ_236, /* EIC236 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 237) + #if defined(INT_VECTOR_PE1_IRQ_237) + INT_VECTOR_PE1_IRQ_237, /* EIC237 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 238) + #if defined(INT_VECTOR_PE1_IRQ_238) + INT_VECTOR_PE1_IRQ_238, /* EIC238 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 239) + #if defined(INT_VECTOR_PE1_IRQ_239) + INT_VECTOR_PE1_IRQ_239, /* EIC239 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 240) + #if defined(INT_VECTOR_PE1_IRQ_240) + INT_VECTOR_PE1_IRQ_240, /* EIC240 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 241) + #if defined(INT_VECTOR_PE1_IRQ_241) + INT_VECTOR_PE1_IRQ_241, /* EIC241 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 242) + #if defined(INT_VECTOR_PE1_IRQ_242) + INT_VECTOR_PE1_IRQ_242, /* EIC242 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 243) + #if defined(INT_VECTOR_PE1_IRQ_243) + INT_VECTOR_PE1_IRQ_243, /* EIC243 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 244) + #if defined(INT_VECTOR_PE1_IRQ_244) + INT_VECTOR_PE1_IRQ_244, /* EIC244 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 245) + #if defined(INT_VECTOR_PE1_IRQ_245) + INT_VECTOR_PE1_IRQ_245, /* EIC245 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 246) + #if defined(INT_VECTOR_PE1_IRQ_246) + INT_VECTOR_PE1_IRQ_246, /* EIC246 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 247) + #if defined(INT_VECTOR_PE1_IRQ_247) + INT_VECTOR_PE1_IRQ_247, /* EIC247 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 248) + #if defined(INT_VECTOR_PE1_IRQ_248) + INT_VECTOR_PE1_IRQ_248, /* EIC248 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 249) + #if defined(INT_VECTOR_PE1_IRQ_249) + INT_VECTOR_PE1_IRQ_249, /* EIC249 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 250) + #if defined(INT_VECTOR_PE1_IRQ_250) + INT_VECTOR_PE1_IRQ_250, /* EIC250 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 251) + #if defined(INT_VECTOR_PE1_IRQ_251) + INT_VECTOR_PE1_IRQ_251, /* EIC251 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 252) + #if defined(INT_VECTOR_PE1_IRQ_252) + INT_VECTOR_PE1_IRQ_252, /* EIC252 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 253) + #if defined(INT_VECTOR_PE1_IRQ_253) + INT_VECTOR_PE1_IRQ_253, /* EIC253 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 254) + #if defined(INT_VECTOR_PE1_IRQ_254) + INT_VECTOR_PE1_IRQ_254, /* EIC254 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 255) + #if defined(INT_VECTOR_PE1_IRQ_255) + INT_VECTOR_PE1_IRQ_255, /* EIC255 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 256) + #if defined(INT_VECTOR_PE1_IRQ_256) + INT_VECTOR_PE1_IRQ_256, /* EIC256 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 257) + #if defined(INT_VECTOR_PE1_IRQ_257) + INT_VECTOR_PE1_IRQ_257, /* EIC257 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 258) + #if defined(INT_VECTOR_PE1_IRQ_258) + INT_VECTOR_PE1_IRQ_258, /* EIC258 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 259) + #if defined(INT_VECTOR_PE1_IRQ_259) + INT_VECTOR_PE1_IRQ_259, /* EIC259 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 260) + #if defined(INT_VECTOR_PE1_IRQ_260) + INT_VECTOR_PE1_IRQ_260, /* EIC260 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 261) + #if defined(INT_VECTOR_PE1_IRQ_261) + INT_VECTOR_PE1_IRQ_261, /* EIC261 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 262) + #if defined(INT_VECTOR_PE1_IRQ_262) + INT_VECTOR_PE1_IRQ_262, /* EIC262 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 263) + #if defined(INT_VECTOR_PE1_IRQ_263) + INT_VECTOR_PE1_IRQ_263, /* EIC263 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 264) + #if defined(INT_VECTOR_PE1_IRQ_264) + INT_VECTOR_PE1_IRQ_264, /* EIC264 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 265) + #if defined(INT_VECTOR_PE1_IRQ_265) + INT_VECTOR_PE1_IRQ_265, /* EIC265 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 266) + #if defined(INT_VECTOR_PE1_IRQ_266) + INT_VECTOR_PE1_IRQ_266, /* EIC266 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 267) + #if defined(INT_VECTOR_PE1_IRQ_267) + INT_VECTOR_PE1_IRQ_267, /* EIC267 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 268) + #if defined(INT_VECTOR_PE1_IRQ_268) + INT_VECTOR_PE1_IRQ_268, /* EIC268 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 269) + #if defined(INT_VECTOR_PE1_IRQ_269) + INT_VECTOR_PE1_IRQ_269, /* EIC269 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 270) + #if defined(INT_VECTOR_PE1_IRQ_270) + INT_VECTOR_PE1_IRQ_270, /* EIC270 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 271) + #if defined(INT_VECTOR_PE1_IRQ_271) + INT_VECTOR_PE1_IRQ_271, /* EIC271 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 272) + #if defined(INT_VECTOR_PE1_IRQ_272) + INT_VECTOR_PE1_IRQ_272, /* EIC272 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 273) + #if defined(INT_VECTOR_PE1_IRQ_273) + INT_VECTOR_PE1_IRQ_273, /* EIC273 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 274) + #if defined(INT_VECTOR_PE1_IRQ_274) + INT_VECTOR_PE1_IRQ_274, /* EIC274 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 275) + #if defined(INT_VECTOR_PE1_IRQ_275) + INT_VECTOR_PE1_IRQ_275, /* EIC275 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 276) + #if defined(INT_VECTOR_PE1_IRQ_276) + INT_VECTOR_PE1_IRQ_276, /* EIC276 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 277) + #if defined(INT_VECTOR_PE1_IRQ_277) + INT_VECTOR_PE1_IRQ_277, /* EIC277 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 278) + #if defined(INT_VECTOR_PE1_IRQ_278) + INT_VECTOR_PE1_IRQ_278, /* EIC278 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 279) + #if defined(INT_VECTOR_PE1_IRQ_279) + INT_VECTOR_PE1_IRQ_279, /* EIC279 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 280) + #if defined(INT_VECTOR_PE1_IRQ_280) + INT_VECTOR_PE1_IRQ_280, /* EIC280 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 281) + #if defined(INT_VECTOR_PE1_IRQ_281) + INT_VECTOR_PE1_IRQ_281, /* EIC281 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 282) + #if defined(INT_VECTOR_PE1_IRQ_282) + INT_VECTOR_PE1_IRQ_282, /* EIC282 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 283) + #if defined(INT_VECTOR_PE1_IRQ_283) + INT_VECTOR_PE1_IRQ_283, /* EIC283 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 284) + #if defined(INT_VECTOR_PE1_IRQ_284) + INT_VECTOR_PE1_IRQ_284, /* EIC284 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 285) + #if defined(INT_VECTOR_PE1_IRQ_285) + INT_VECTOR_PE1_IRQ_285, /* EIC285 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 286) + #if defined(INT_VECTOR_PE1_IRQ_286) + INT_VECTOR_PE1_IRQ_286, /* EIC286 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 287) + #if defined(INT_VECTOR_PE1_IRQ_287) + INT_VECTOR_PE1_IRQ_287, /* EIC287 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 288) + #if defined(INT_VECTOR_PE1_IRQ_288) + INT_VECTOR_PE1_IRQ_288, /* EIC288 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 289) + #if defined(INT_VECTOR_PE1_IRQ_289) + INT_VECTOR_PE1_IRQ_289, /* EIC289 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 290) + #if defined(INT_VECTOR_PE1_IRQ_290) + INT_VECTOR_PE1_IRQ_290, /* EIC290 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 291) + #if defined(INT_VECTOR_PE1_IRQ_291) + INT_VECTOR_PE1_IRQ_291, /* EIC291 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 292) + #if defined(INT_VECTOR_PE1_IRQ_292) + INT_VECTOR_PE1_IRQ_292, /* EIC292 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 293) + #if defined(INT_VECTOR_PE1_IRQ_293) + INT_VECTOR_PE1_IRQ_293, /* EIC293 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 294) + #if defined(INT_VECTOR_PE1_IRQ_294) + INT_VECTOR_PE1_IRQ_294, /* EIC294 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 295) + #if defined(INT_VECTOR_PE1_IRQ_295) + INT_VECTOR_PE1_IRQ_295, /* EIC295 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 296) + #if defined(INT_VECTOR_PE1_IRQ_296) + INT_VECTOR_PE1_IRQ_296, /* EIC296 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 297) + #if defined(INT_VECTOR_PE1_IRQ_297) + INT_VECTOR_PE1_IRQ_297, /* EIC297 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 298) + #if defined(INT_VECTOR_PE1_IRQ_298) + INT_VECTOR_PE1_IRQ_298, /* EIC298 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 299) + #if defined(INT_VECTOR_PE1_IRQ_299) + INT_VECTOR_PE1_IRQ_299, /* EIC299 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 300) + #if defined(INT_VECTOR_PE1_IRQ_300) + INT_VECTOR_PE1_IRQ_300, /* EIC300 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 301) + #if defined(INT_VECTOR_PE1_IRQ_301) + INT_VECTOR_PE1_IRQ_301, /* EIC301 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 302) + #if defined(INT_VECTOR_PE1_IRQ_302) + INT_VECTOR_PE1_IRQ_302, /* EIC302 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 303) + #if defined(INT_VECTOR_PE1_IRQ_303) + INT_VECTOR_PE1_IRQ_303, /* EIC303 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 304) + #if defined(INT_VECTOR_PE1_IRQ_304) + INT_VECTOR_PE1_IRQ_304, /* EIC304 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 305) + #if defined(INT_VECTOR_PE1_IRQ_305) + INT_VECTOR_PE1_IRQ_305, /* EIC305 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 306) + #if defined(INT_VECTOR_PE1_IRQ_306) + INT_VECTOR_PE1_IRQ_306, /* EIC306 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 307) + #if defined(INT_VECTOR_PE1_IRQ_307) + INT_VECTOR_PE1_IRQ_307, /* EIC307 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 308) + #if defined(INT_VECTOR_PE1_IRQ_308) + INT_VECTOR_PE1_IRQ_308, /* EIC308 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 309) + #if defined(INT_VECTOR_PE1_IRQ_309) + INT_VECTOR_PE1_IRQ_309, /* EIC309 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 310) + #if defined(INT_VECTOR_PE1_IRQ_310) + INT_VECTOR_PE1_IRQ_310, /* EIC310 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 311) + #if defined(INT_VECTOR_PE1_IRQ_311) + INT_VECTOR_PE1_IRQ_311, /* EIC311 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 312) + #if defined(INT_VECTOR_PE1_IRQ_312) + INT_VECTOR_PE1_IRQ_312, /* EIC312 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 313) + #if defined(INT_VECTOR_PE1_IRQ_313) + INT_VECTOR_PE1_IRQ_313, /* EIC313 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 314) + #if defined(INT_VECTOR_PE1_IRQ_314) + INT_VECTOR_PE1_IRQ_314, /* EIC314 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 315) + #if defined(INT_VECTOR_PE1_IRQ_315) + INT_VECTOR_PE1_IRQ_315, /* EIC315 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 316) + #if defined(INT_VECTOR_PE1_IRQ_316) + INT_VECTOR_PE1_IRQ_316, /* EIC316 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 317) + #if defined(INT_VECTOR_PE1_IRQ_317) + INT_VECTOR_PE1_IRQ_317, /* EIC317 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 318) + #if defined(INT_VECTOR_PE1_IRQ_318) + INT_VECTOR_PE1_IRQ_318, /* EIC318 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 319) + #if defined(INT_VECTOR_PE1_IRQ_319) + INT_VECTOR_PE1_IRQ_319, /* EIC319 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 320) + #if defined(INT_VECTOR_PE1_IRQ_320) + INT_VECTOR_PE1_IRQ_320, /* EIC320 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 321) + #if defined(INT_VECTOR_PE1_IRQ_321) + INT_VECTOR_PE1_IRQ_321, /* EIC321 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 322) + #if defined(INT_VECTOR_PE1_IRQ_322) + INT_VECTOR_PE1_IRQ_322, /* EIC322 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 323) + #if defined(INT_VECTOR_PE1_IRQ_323) + INT_VECTOR_PE1_IRQ_323, /* EIC323 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 324) + #if defined(INT_VECTOR_PE1_IRQ_324) + INT_VECTOR_PE1_IRQ_324, /* EIC324 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 325) + #if defined(INT_VECTOR_PE1_IRQ_325) + INT_VECTOR_PE1_IRQ_325, /* EIC325 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 326) + #if defined(INT_VECTOR_PE1_IRQ_326) + INT_VECTOR_PE1_IRQ_326, /* EIC326 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 327) + #if defined(INT_VECTOR_PE1_IRQ_327) + INT_VECTOR_PE1_IRQ_327, /* EIC327 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 328) + #if defined(INT_VECTOR_PE1_IRQ_328) + INT_VECTOR_PE1_IRQ_328, /* EIC328 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 329) + #if defined(INT_VECTOR_PE1_IRQ_329) + INT_VECTOR_PE1_IRQ_329, /* EIC329 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 330) + #if defined(INT_VECTOR_PE1_IRQ_330) + INT_VECTOR_PE1_IRQ_330, /* EIC330 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 331) + #if defined(INT_VECTOR_PE1_IRQ_331) + INT_VECTOR_PE1_IRQ_331, /* EIC331 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 332) + #if defined(INT_VECTOR_PE1_IRQ_332) + INT_VECTOR_PE1_IRQ_332, /* EIC332 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 333) + #if defined(INT_VECTOR_PE1_IRQ_333) + INT_VECTOR_PE1_IRQ_333, /* EIC333 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 334) + #if defined(INT_VECTOR_PE1_IRQ_334) + INT_VECTOR_PE1_IRQ_334, /* EIC334 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 335) + #if defined(INT_VECTOR_PE1_IRQ_335) + INT_VECTOR_PE1_IRQ_335, /* EIC335 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 336) + #if defined(INT_VECTOR_PE1_IRQ_336) + INT_VECTOR_PE1_IRQ_336, /* EIC336 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 337) + #if defined(INT_VECTOR_PE1_IRQ_337) + INT_VECTOR_PE1_IRQ_337, /* EIC337 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 338) + #if defined(INT_VECTOR_PE1_IRQ_338) + INT_VECTOR_PE1_IRQ_338, /* EIC338 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 339) + #if defined(INT_VECTOR_PE1_IRQ_339) + INT_VECTOR_PE1_IRQ_339, /* EIC339 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 340) + #if defined(INT_VECTOR_PE1_IRQ_340) + INT_VECTOR_PE1_IRQ_340, /* EIC340 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 341) + #if defined(INT_VECTOR_PE1_IRQ_341) + INT_VECTOR_PE1_IRQ_341, /* EIC341 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 342) + #if defined(INT_VECTOR_PE1_IRQ_342) + INT_VECTOR_PE1_IRQ_342, /* EIC342 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 343) + #if defined(INT_VECTOR_PE1_IRQ_343) + INT_VECTOR_PE1_IRQ_343, /* EIC343 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 344) + #if defined(INT_VECTOR_PE1_IRQ_344) + INT_VECTOR_PE1_IRQ_344, /* EIC344 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 345) + #if defined(INT_VECTOR_PE1_IRQ_345) + INT_VECTOR_PE1_IRQ_345, /* EIC345 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 346) + #if defined(INT_VECTOR_PE1_IRQ_346) + INT_VECTOR_PE1_IRQ_346, /* EIC346 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 347) + #if defined(INT_VECTOR_PE1_IRQ_347) + INT_VECTOR_PE1_IRQ_347, /* EIC347 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 348) + #if defined(INT_VECTOR_PE1_IRQ_348) + INT_VECTOR_PE1_IRQ_348, /* EIC348 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 349) + #if defined(INT_VECTOR_PE1_IRQ_349) + INT_VECTOR_PE1_IRQ_349, /* EIC349 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 350) + #if defined(INT_VECTOR_PE1_IRQ_350) + INT_VECTOR_PE1_IRQ_350, /* EIC350 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 351) + #if defined(INT_VECTOR_PE1_IRQ_351) + INT_VECTOR_PE1_IRQ_351, /* EIC351 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 352) + #if defined(INT_VECTOR_PE1_IRQ_352) + INT_VECTOR_PE1_IRQ_352, /* EIC352 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 353) + #if defined(INT_VECTOR_PE1_IRQ_353) + INT_VECTOR_PE1_IRQ_353, /* EIC353 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 354) + #if defined(INT_VECTOR_PE1_IRQ_354) + INT_VECTOR_PE1_IRQ_354, /* EIC354 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 355) + #if defined(INT_VECTOR_PE1_IRQ_355) + INT_VECTOR_PE1_IRQ_355, /* EIC355 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 356) + #if defined(INT_VECTOR_PE1_IRQ_356) + INT_VECTOR_PE1_IRQ_356, /* EIC356 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 357) + #if defined(INT_VECTOR_PE1_IRQ_357) + INT_VECTOR_PE1_IRQ_357, /* EIC357 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 358) + #if defined(INT_VECTOR_PE1_IRQ_358) + INT_VECTOR_PE1_IRQ_358, /* EIC358 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 359) + #if defined(INT_VECTOR_PE1_IRQ_359) + INT_VECTOR_PE1_IRQ_359, /* EIC359 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 360) + #if defined(INT_VECTOR_PE1_IRQ_360) + INT_VECTOR_PE1_IRQ_360, /* EIC360 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 361) + #if defined(INT_VECTOR_PE1_IRQ_361) + INT_VECTOR_PE1_IRQ_361, /* EIC361 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 362) + #if defined(INT_VECTOR_PE1_IRQ_362) + INT_VECTOR_PE1_IRQ_362, /* EIC362 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 363) + #if defined(INT_VECTOR_PE1_IRQ_363) + INT_VECTOR_PE1_IRQ_363, /* EIC363 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 364) + #if defined(INT_VECTOR_PE1_IRQ_364) + INT_VECTOR_PE1_IRQ_364, /* EIC364 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 365) + #if defined(INT_VECTOR_PE1_IRQ_365) + INT_VECTOR_PE1_IRQ_365, /* EIC365 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 366) + #if defined(INT_VECTOR_PE1_IRQ_366) + INT_VECTOR_PE1_IRQ_366, /* EIC366 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 367) + #if defined(INT_VECTOR_PE1_IRQ_367) + INT_VECTOR_PE1_IRQ_367, /* EIC367 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 368) + #if defined(INT_VECTOR_PE1_IRQ_368) + INT_VECTOR_PE1_IRQ_368, /* EIC368 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 369) + #if defined(INT_VECTOR_PE1_IRQ_369) + INT_VECTOR_PE1_IRQ_369, /* EIC369 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 370) + #if defined(INT_VECTOR_PE1_IRQ_370) + INT_VECTOR_PE1_IRQ_370, /* EIC370 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 371) + #if defined(INT_VECTOR_PE1_IRQ_371) + INT_VECTOR_PE1_IRQ_371, /* EIC371 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 372) + #if defined(INT_VECTOR_PE1_IRQ_372) + INT_VECTOR_PE1_IRQ_372, /* EIC372 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 373) + #if defined(INT_VECTOR_PE1_IRQ_373) + INT_VECTOR_PE1_IRQ_373, /* EIC373 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 374) + #if defined(INT_VECTOR_PE1_IRQ_374) + INT_VECTOR_PE1_IRQ_374, /* EIC374 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 375) + #if defined(INT_VECTOR_PE1_IRQ_375) + INT_VECTOR_PE1_IRQ_375, /* EIC375 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 376) + #if defined(INT_VECTOR_PE1_IRQ_376) + INT_VECTOR_PE1_IRQ_376, /* EIC376 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 377) + #if defined(INT_VECTOR_PE1_IRQ_377) + INT_VECTOR_PE1_IRQ_377, /* EIC377 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 378) + #if defined(INT_VECTOR_PE1_IRQ_378) + INT_VECTOR_PE1_IRQ_378, /* EIC378 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 379) + #if defined(INT_VECTOR_PE1_IRQ_379) + INT_VECTOR_PE1_IRQ_379, /* EIC379 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 380) + #if defined(INT_VECTOR_PE1_IRQ_380) + INT_VECTOR_PE1_IRQ_380, /* EIC380 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 381) + #if defined(INT_VECTOR_PE1_IRQ_381) + INT_VECTOR_PE1_IRQ_381, /* EIC381 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 382) + #if defined(INT_VECTOR_PE1_IRQ_382) + INT_VECTOR_PE1_IRQ_382, /* EIC382 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 383) + #if defined(INT_VECTOR_PE1_IRQ_383) + INT_VECTOR_PE1_IRQ_383, /* EIC383 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 384) + #if defined(INT_VECTOR_PE1_IRQ_384) + INT_VECTOR_PE1_IRQ_384, /* EIC384 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 385) + #if defined(INT_VECTOR_PE1_IRQ_385) + INT_VECTOR_PE1_IRQ_385, /* EIC385 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 386) + #if defined(INT_VECTOR_PE1_IRQ_386) + INT_VECTOR_PE1_IRQ_386, /* EIC386 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 387) + #if defined(INT_VECTOR_PE1_IRQ_387) + INT_VECTOR_PE1_IRQ_387, /* EIC387 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 388) + #if defined(INT_VECTOR_PE1_IRQ_388) + INT_VECTOR_PE1_IRQ_388, /* EIC388 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 389) + #if defined(INT_VECTOR_PE1_IRQ_389) + INT_VECTOR_PE1_IRQ_389, /* EIC389 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 390) + #if defined(INT_VECTOR_PE1_IRQ_390) + INT_VECTOR_PE1_IRQ_390, /* EIC390 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 391) + #if defined(INT_VECTOR_PE1_IRQ_391) + INT_VECTOR_PE1_IRQ_391, /* EIC391 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 392) + #if defined(INT_VECTOR_PE1_IRQ_392) + INT_VECTOR_PE1_IRQ_392, /* EIC392 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 393) + #if defined(INT_VECTOR_PE1_IRQ_393) + INT_VECTOR_PE1_IRQ_393, /* EIC393 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 394) + #if defined(INT_VECTOR_PE1_IRQ_394) + INT_VECTOR_PE1_IRQ_394, /* EIC394 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 395) + #if defined(INT_VECTOR_PE1_IRQ_395) + INT_VECTOR_PE1_IRQ_395, /* EIC395 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 396) + #if defined(INT_VECTOR_PE1_IRQ_396) + INT_VECTOR_PE1_IRQ_396, /* EIC396 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 397) + #if defined(INT_VECTOR_PE1_IRQ_397) + INT_VECTOR_PE1_IRQ_397, /* EIC397 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 398) + #if defined(INT_VECTOR_PE1_IRQ_398) + INT_VECTOR_PE1_IRQ_398, /* EIC398 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 399) + #if defined(INT_VECTOR_PE1_IRQ_399) + INT_VECTOR_PE1_IRQ_399, /* EIC399 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 400) + #if defined(INT_VECTOR_PE1_IRQ_400) + INT_VECTOR_PE1_IRQ_400, /* EIC400 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 401) + #if defined(INT_VECTOR_PE1_IRQ_401) + INT_VECTOR_PE1_IRQ_401, /* EIC401 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 402) + #if defined(INT_VECTOR_PE1_IRQ_402) + INT_VECTOR_PE1_IRQ_402, /* EIC402 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 403) + #if defined(INT_VECTOR_PE1_IRQ_403) + INT_VECTOR_PE1_IRQ_403, /* EIC403 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 404) + #if defined(INT_VECTOR_PE1_IRQ_404) + INT_VECTOR_PE1_IRQ_404, /* EIC404 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 405) + #if defined(INT_VECTOR_PE1_IRQ_405) + INT_VECTOR_PE1_IRQ_405, /* EIC405 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 406) + #if defined(INT_VECTOR_PE1_IRQ_406) + INT_VECTOR_PE1_IRQ_406, /* EIC406 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 407) + #if defined(INT_VECTOR_PE1_IRQ_407) + INT_VECTOR_PE1_IRQ_407, /* EIC407 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 408) + #if defined(INT_VECTOR_PE1_IRQ_408) + INT_VECTOR_PE1_IRQ_408, /* EIC408 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 409) + #if defined(INT_VECTOR_PE1_IRQ_409) + INT_VECTOR_PE1_IRQ_409, /* EIC409 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 410) + #if defined(INT_VECTOR_PE1_IRQ_410) + INT_VECTOR_PE1_IRQ_410, /* EIC410 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 411) + #if defined(INT_VECTOR_PE1_IRQ_411) + INT_VECTOR_PE1_IRQ_411, /* EIC411 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 412) + #if defined(INT_VECTOR_PE1_IRQ_412) + INT_VECTOR_PE1_IRQ_412, /* EIC412 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 413) + #if defined(INT_VECTOR_PE1_IRQ_413) + INT_VECTOR_PE1_IRQ_413, /* EIC413 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 414) + #if defined(INT_VECTOR_PE1_IRQ_414) + INT_VECTOR_PE1_IRQ_414, /* EIC414 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 415) + #if defined(INT_VECTOR_PE1_IRQ_415) + INT_VECTOR_PE1_IRQ_415, /* EIC415 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 416) + #if defined(INT_VECTOR_PE1_IRQ_416) + INT_VECTOR_PE1_IRQ_416, /* EIC416 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 417) + #if defined(INT_VECTOR_PE1_IRQ_417) + INT_VECTOR_PE1_IRQ_417, /* EIC417 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 418) + #if defined(INT_VECTOR_PE1_IRQ_418) + INT_VECTOR_PE1_IRQ_418, /* EIC418 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 419) + #if defined(INT_VECTOR_PE1_IRQ_419) + INT_VECTOR_PE1_IRQ_419, /* EIC419 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 420) + #if defined(INT_VECTOR_PE1_IRQ_420) + INT_VECTOR_PE1_IRQ_420, /* EIC420 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 421) + #if defined(INT_VECTOR_PE1_IRQ_421) + INT_VECTOR_PE1_IRQ_421, /* EIC421 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 422) + #if defined(INT_VECTOR_PE1_IRQ_422) + INT_VECTOR_PE1_IRQ_422, /* EIC422 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 423) + #if defined(INT_VECTOR_PE1_IRQ_423) + INT_VECTOR_PE1_IRQ_423, /* EIC423 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 424) + #if defined(INT_VECTOR_PE1_IRQ_424) + INT_VECTOR_PE1_IRQ_424, /* EIC424 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 425) + #if defined(INT_VECTOR_PE1_IRQ_425) + INT_VECTOR_PE1_IRQ_425, /* EIC425 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 426) + #if defined(INT_VECTOR_PE1_IRQ_426) + INT_VECTOR_PE1_IRQ_426, /* EIC426 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 427) + #if defined(INT_VECTOR_PE1_IRQ_427) + INT_VECTOR_PE1_IRQ_427, /* EIC427 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 428) + #if defined(INT_VECTOR_PE1_IRQ_428) + INT_VECTOR_PE1_IRQ_428, /* EIC428 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 429) + #if defined(INT_VECTOR_PE1_IRQ_429) + INT_VECTOR_PE1_IRQ_429, /* EIC429 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 430) + #if defined(INT_VECTOR_PE1_IRQ_430) + INT_VECTOR_PE1_IRQ_430, /* EIC430 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 431) + #if defined(INT_VECTOR_PE1_IRQ_431) + INT_VECTOR_PE1_IRQ_431, /* EIC431 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 432) + #if defined(INT_VECTOR_PE1_IRQ_432) + INT_VECTOR_PE1_IRQ_432, /* EIC432 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 433) + #if defined(INT_VECTOR_PE1_IRQ_433) + INT_VECTOR_PE1_IRQ_433, /* EIC433 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 434) + #if defined(INT_VECTOR_PE1_IRQ_434) + INT_VECTOR_PE1_IRQ_434, /* EIC434 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 435) + #if defined(INT_VECTOR_PE1_IRQ_435) + INT_VECTOR_PE1_IRQ_435, /* EIC435 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 436) + #if defined(INT_VECTOR_PE1_IRQ_436) + INT_VECTOR_PE1_IRQ_436, /* EIC436 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 437) + #if defined(INT_VECTOR_PE1_IRQ_437) + INT_VECTOR_PE1_IRQ_437, /* EIC437 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 438) + #if defined(INT_VECTOR_PE1_IRQ_438) + INT_VECTOR_PE1_IRQ_438, /* EIC438 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 439) + #if defined(INT_VECTOR_PE1_IRQ_439) + INT_VECTOR_PE1_IRQ_439, /* EIC439 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 440) + #if defined(INT_VECTOR_PE1_IRQ_440) + INT_VECTOR_PE1_IRQ_440, /* EIC440 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 441) + #if defined(INT_VECTOR_PE1_IRQ_441) + INT_VECTOR_PE1_IRQ_441, /* EIC441 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 442) + #if defined(INT_VECTOR_PE1_IRQ_442) + INT_VECTOR_PE1_IRQ_442, /* EIC442 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 443) + #if defined(INT_VECTOR_PE1_IRQ_443) + INT_VECTOR_PE1_IRQ_443, /* EIC443 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 444) + #if defined(INT_VECTOR_PE1_IRQ_444) + INT_VECTOR_PE1_IRQ_444, /* EIC444 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 445) + #if defined(INT_VECTOR_PE1_IRQ_445) + INT_VECTOR_PE1_IRQ_445, /* EIC445 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 446) + #if defined(INT_VECTOR_PE1_IRQ_446) + INT_VECTOR_PE1_IRQ_446, /* EIC446 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 447) + #if defined(INT_VECTOR_PE1_IRQ_447) + INT_VECTOR_PE1_IRQ_447, /* EIC447 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 448) + #if defined(INT_VECTOR_PE1_IRQ_448) + INT_VECTOR_PE1_IRQ_448, /* EIC448 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 449) + #if defined(INT_VECTOR_PE1_IRQ_449) + INT_VECTOR_PE1_IRQ_449, /* EIC449 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 450) + #if defined(INT_VECTOR_PE1_IRQ_450) + INT_VECTOR_PE1_IRQ_450, /* EIC450 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 451) + #if defined(INT_VECTOR_PE1_IRQ_451) + INT_VECTOR_PE1_IRQ_451, /* EIC451 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 452) + #if defined(INT_VECTOR_PE1_IRQ_452) + INT_VECTOR_PE1_IRQ_452, /* EIC452 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 453) + #if defined(INT_VECTOR_PE1_IRQ_453) + INT_VECTOR_PE1_IRQ_453, /* EIC453 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 454) + #if defined(INT_VECTOR_PE1_IRQ_454) + INT_VECTOR_PE1_IRQ_454, /* EIC454 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 455) + #if defined(INT_VECTOR_PE1_IRQ_455) + INT_VECTOR_PE1_IRQ_455, /* EIC455 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 456) + #if defined(INT_VECTOR_PE1_IRQ_456) + INT_VECTOR_PE1_IRQ_456, /* EIC456 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 457) + #if defined(INT_VECTOR_PE1_IRQ_457) + INT_VECTOR_PE1_IRQ_457, /* EIC457 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 458) + #if defined(INT_VECTOR_PE1_IRQ_458) + INT_VECTOR_PE1_IRQ_458, /* EIC458 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 459) + #if defined(INT_VECTOR_PE1_IRQ_459) + INT_VECTOR_PE1_IRQ_459, /* EIC459 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 460) + #if defined(INT_VECTOR_PE1_IRQ_460) + INT_VECTOR_PE1_IRQ_460, /* EIC460 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 461) + #if defined(INT_VECTOR_PE1_IRQ_461) + INT_VECTOR_PE1_IRQ_461, /* EIC461 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 462) + #if defined(INT_VECTOR_PE1_IRQ_462) + INT_VECTOR_PE1_IRQ_462, /* EIC462 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 463) + #if defined(INT_VECTOR_PE1_IRQ_463) + INT_VECTOR_PE1_IRQ_463, /* EIC463 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 464) + #if defined(INT_VECTOR_PE1_IRQ_464) + INT_VECTOR_PE1_IRQ_464, /* EIC464 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 465) + #if defined(INT_VECTOR_PE1_IRQ_465) + INT_VECTOR_PE1_IRQ_465, /* EIC465 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 466) + #if defined(INT_VECTOR_PE1_IRQ_466) + INT_VECTOR_PE1_IRQ_466, /* EIC466 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 467) + #if defined(INT_VECTOR_PE1_IRQ_467) + INT_VECTOR_PE1_IRQ_467, /* EIC467 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 468) + #if defined(INT_VECTOR_PE1_IRQ_468) + INT_VECTOR_PE1_IRQ_468, /* EIC468 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 469) + #if defined(INT_VECTOR_PE1_IRQ_469) + INT_VECTOR_PE1_IRQ_469, /* EIC469 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 470) + #if defined(INT_VECTOR_PE1_IRQ_470) + INT_VECTOR_PE1_IRQ_470, /* EIC470 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 471) + #if defined(INT_VECTOR_PE1_IRQ_471) + INT_VECTOR_PE1_IRQ_471, /* EIC471 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 472) + #if defined(INT_VECTOR_PE1_IRQ_472) + INT_VECTOR_PE1_IRQ_472, /* EIC472 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 473) + #if defined(INT_VECTOR_PE1_IRQ_473) + INT_VECTOR_PE1_IRQ_473, /* EIC473 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 474) + #if defined(INT_VECTOR_PE1_IRQ_474) + INT_VECTOR_PE1_IRQ_474, /* EIC474 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 475) + #if defined(INT_VECTOR_PE1_IRQ_475) + INT_VECTOR_PE1_IRQ_475, /* EIC475 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 476) + #if defined(INT_VECTOR_PE1_IRQ_476) + INT_VECTOR_PE1_IRQ_476, /* EIC476 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 477) + #if defined(INT_VECTOR_PE1_IRQ_477) + INT_VECTOR_PE1_IRQ_477, /* EIC477 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 478) + #if defined(INT_VECTOR_PE1_IRQ_478) + INT_VECTOR_PE1_IRQ_478, /* EIC478 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 479) + #if defined(INT_VECTOR_PE1_IRQ_479) + INT_VECTOR_PE1_IRQ_479, /* EIC479 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 480) + #if defined(INT_VECTOR_PE1_IRQ_480) + INT_VECTOR_PE1_IRQ_480, /* EIC480 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 481) + #if defined(INT_VECTOR_PE1_IRQ_481) + INT_VECTOR_PE1_IRQ_481, /* EIC481 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 482) + #if defined(INT_VECTOR_PE1_IRQ_482) + INT_VECTOR_PE1_IRQ_482, /* EIC482 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 483) + #if defined(INT_VECTOR_PE1_IRQ_483) + INT_VECTOR_PE1_IRQ_483, /* EIC483 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 484) + #if defined(INT_VECTOR_PE1_IRQ_484) + INT_VECTOR_PE1_IRQ_484, /* EIC484 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 485) + #if defined(INT_VECTOR_PE1_IRQ_485) + INT_VECTOR_PE1_IRQ_485, /* EIC485 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 486) + #if defined(INT_VECTOR_PE1_IRQ_486) + INT_VECTOR_PE1_IRQ_486, /* EIC486 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 487) + #if defined(INT_VECTOR_PE1_IRQ_487) + INT_VECTOR_PE1_IRQ_487, /* EIC487 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 488) + #if defined(INT_VECTOR_PE1_IRQ_488) + INT_VECTOR_PE1_IRQ_488, /* EIC488 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 489) + #if defined(INT_VECTOR_PE1_IRQ_489) + INT_VECTOR_PE1_IRQ_489, /* EIC489 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 490) + #if defined(INT_VECTOR_PE1_IRQ_490) + INT_VECTOR_PE1_IRQ_490, /* EIC490 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 491) + #if defined(INT_VECTOR_PE1_IRQ_491) + INT_VECTOR_PE1_IRQ_491, /* EIC491 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 492) + #if defined(INT_VECTOR_PE1_IRQ_492) + INT_VECTOR_PE1_IRQ_492, /* EIC492 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 493) + #if defined(INT_VECTOR_PE1_IRQ_493) + INT_VECTOR_PE1_IRQ_493, /* EIC493 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 494) + #if defined(INT_VECTOR_PE1_IRQ_494) + INT_VECTOR_PE1_IRQ_494, /* EIC494 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 495) + #if defined(INT_VECTOR_PE1_IRQ_495) + INT_VECTOR_PE1_IRQ_495, /* EIC495 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 496) + #if defined(INT_VECTOR_PE1_IRQ_496) + INT_VECTOR_PE1_IRQ_496, /* EIC496 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 497) + #if defined(INT_VECTOR_PE1_IRQ_497) + INT_VECTOR_PE1_IRQ_497, /* EIC497 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 498) + #if defined(INT_VECTOR_PE1_IRQ_498) + INT_VECTOR_PE1_IRQ_498, /* EIC498 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 499) + #if defined(INT_VECTOR_PE1_IRQ_499) + INT_VECTOR_PE1_IRQ_499, /* EIC499 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 500) + #if defined(INT_VECTOR_PE1_IRQ_500) + INT_VECTOR_PE1_IRQ_500, /* EIC500 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 501) + #if defined(INT_VECTOR_PE1_IRQ_501) + INT_VECTOR_PE1_IRQ_501, /* EIC501 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 502) + #if defined(INT_VECTOR_PE1_IRQ_502) + INT_VECTOR_PE1_IRQ_502, /* EIC502 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 503) + #if defined(INT_VECTOR_PE1_IRQ_503) + INT_VECTOR_PE1_IRQ_503, /* EIC503 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 504) + #if defined(INT_VECTOR_PE1_IRQ_504) + INT_VECTOR_PE1_IRQ_504, /* EIC504 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 505) + #if defined(INT_VECTOR_PE1_IRQ_505) + INT_VECTOR_PE1_IRQ_505, /* EIC505 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 506) + #if defined(INT_VECTOR_PE1_IRQ_506) + INT_VECTOR_PE1_IRQ_506, /* EIC506 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 507) + #if defined(INT_VECTOR_PE1_IRQ_507) + INT_VECTOR_PE1_IRQ_507, /* EIC507 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 508) + #if defined(INT_VECTOR_PE1_IRQ_508) + INT_VECTOR_PE1_IRQ_508, /* EIC508 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 509) + #if defined(INT_VECTOR_PE1_IRQ_509) + INT_VECTOR_PE1_IRQ_509, /* EIC509 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 510) + #if defined(INT_VECTOR_PE1_IRQ_510) + INT_VECTOR_PE1_IRQ_510, /* EIC510 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 511) + #if defined(INT_VECTOR_PE1_IRQ_511) + INT_VECTOR_PE1_IRQ_511, /* EIC511 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 512) + #if defined(INT_VECTOR_PE1_IRQ_512) + INT_VECTOR_PE1_IRQ_512, /* EIC512 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 513) + #if defined(INT_VECTOR_PE1_IRQ_513) + INT_VECTOR_PE1_IRQ_513, /* EIC513 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 514) + #if defined(INT_VECTOR_PE1_IRQ_514) + INT_VECTOR_PE1_IRQ_514, /* EIC514 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 515) + #if defined(INT_VECTOR_PE1_IRQ_515) + INT_VECTOR_PE1_IRQ_515, /* EIC515 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 516) + #if defined(INT_VECTOR_PE1_IRQ_516) + INT_VECTOR_PE1_IRQ_516, /* EIC516 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 517) + #if defined(INT_VECTOR_PE1_IRQ_517) + INT_VECTOR_PE1_IRQ_517, /* EIC517 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 518) + #if defined(INT_VECTOR_PE1_IRQ_518) + INT_VECTOR_PE1_IRQ_518, /* EIC518 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 519) + #if defined(INT_VECTOR_PE1_IRQ_519) + INT_VECTOR_PE1_IRQ_519, /* EIC519 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 520) + #if defined(INT_VECTOR_PE1_IRQ_520) + INT_VECTOR_PE1_IRQ_520, /* EIC520 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 521) + #if defined(INT_VECTOR_PE1_IRQ_521) + INT_VECTOR_PE1_IRQ_521, /* EIC521 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 522) + #if defined(INT_VECTOR_PE1_IRQ_522) + INT_VECTOR_PE1_IRQ_522, /* EIC522 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 523) + #if defined(INT_VECTOR_PE1_IRQ_523) + INT_VECTOR_PE1_IRQ_523, /* EIC523 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 524) + #if defined(INT_VECTOR_PE1_IRQ_524) + INT_VECTOR_PE1_IRQ_524, /* EIC524 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 525) + #if defined(INT_VECTOR_PE1_IRQ_525) + INT_VECTOR_PE1_IRQ_525, /* EIC525 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 526) + #if defined(INT_VECTOR_PE1_IRQ_526) + INT_VECTOR_PE1_IRQ_526, /* EIC526 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 527) + #if defined(INT_VECTOR_PE1_IRQ_527) + INT_VECTOR_PE1_IRQ_527, /* EIC527 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 528) + #if defined(INT_VECTOR_PE1_IRQ_528) + INT_VECTOR_PE1_IRQ_528, /* EIC528 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 529) + #if defined(INT_VECTOR_PE1_IRQ_529) + INT_VECTOR_PE1_IRQ_529, /* EIC529 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 530) + #if defined(INT_VECTOR_PE1_IRQ_530) + INT_VECTOR_PE1_IRQ_530, /* EIC530 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 531) + #if defined(INT_VECTOR_PE1_IRQ_531) + INT_VECTOR_PE1_IRQ_531, /* EIC531 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 532) + #if defined(INT_VECTOR_PE1_IRQ_532) + INT_VECTOR_PE1_IRQ_532, /* EIC532 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 533) + #if defined(INT_VECTOR_PE1_IRQ_533) + INT_VECTOR_PE1_IRQ_533, /* EIC533 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 534) + #if defined(INT_VECTOR_PE1_IRQ_534) + INT_VECTOR_PE1_IRQ_534, /* EIC534 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 535) + #if defined(INT_VECTOR_PE1_IRQ_535) + INT_VECTOR_PE1_IRQ_535, /* EIC535 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 536) + #if defined(INT_VECTOR_PE1_IRQ_536) + INT_VECTOR_PE1_IRQ_536, /* EIC536 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 537) + #if defined(INT_VECTOR_PE1_IRQ_537) + INT_VECTOR_PE1_IRQ_537, /* EIC537 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 538) + #if defined(INT_VECTOR_PE1_IRQ_538) + INT_VECTOR_PE1_IRQ_538, /* EIC538 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 539) + #if defined(INT_VECTOR_PE1_IRQ_539) + INT_VECTOR_PE1_IRQ_539, /* EIC539 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 540) + #if defined(INT_VECTOR_PE1_IRQ_540) + INT_VECTOR_PE1_IRQ_540, /* EIC540 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 541) + #if defined(INT_VECTOR_PE1_IRQ_541) + INT_VECTOR_PE1_IRQ_541, /* EIC541 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 542) + #if defined(INT_VECTOR_PE1_IRQ_542) + INT_VECTOR_PE1_IRQ_542, /* EIC542 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 543) + #if defined(INT_VECTOR_PE1_IRQ_543) + INT_VECTOR_PE1_IRQ_543, /* EIC543 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 544) + #if defined(INT_VECTOR_PE1_IRQ_544) + INT_VECTOR_PE1_IRQ_544, /* EIC544 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 545) + #if defined(INT_VECTOR_PE1_IRQ_545) + INT_VECTOR_PE1_IRQ_545, /* EIC545 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 546) + #if defined(INT_VECTOR_PE1_IRQ_546) + INT_VECTOR_PE1_IRQ_546, /* EIC546 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 547) + #if defined(INT_VECTOR_PE1_IRQ_547) + INT_VECTOR_PE1_IRQ_547, /* EIC547 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 548) + #if defined(INT_VECTOR_PE1_IRQ_548) + INT_VECTOR_PE1_IRQ_548, /* EIC548 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 549) + #if defined(INT_VECTOR_PE1_IRQ_549) + INT_VECTOR_PE1_IRQ_549, /* EIC549 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 550) + #if defined(INT_VECTOR_PE1_IRQ_550) + INT_VECTOR_PE1_IRQ_550, /* EIC550 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 551) + #if defined(INT_VECTOR_PE1_IRQ_551) + INT_VECTOR_PE1_IRQ_551, /* EIC551 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 552) + #if defined(INT_VECTOR_PE1_IRQ_552) + INT_VECTOR_PE1_IRQ_552, /* EIC552 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 553) + #if defined(INT_VECTOR_PE1_IRQ_553) + INT_VECTOR_PE1_IRQ_553, /* EIC553 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 554) + #if defined(INT_VECTOR_PE1_IRQ_554) + INT_VECTOR_PE1_IRQ_554, /* EIC554 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 555) + #if defined(INT_VECTOR_PE1_IRQ_555) + INT_VECTOR_PE1_IRQ_555, /* EIC555 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 556) + #if defined(INT_VECTOR_PE1_IRQ_556) + INT_VECTOR_PE1_IRQ_556, /* EIC556 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 557) + #if defined(INT_VECTOR_PE1_IRQ_557) + INT_VECTOR_PE1_IRQ_557, /* EIC557 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 558) + #if defined(INT_VECTOR_PE1_IRQ_558) + INT_VECTOR_PE1_IRQ_558, /* EIC558 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 559) + #if defined(INT_VECTOR_PE1_IRQ_559) + INT_VECTOR_PE1_IRQ_559, /* EIC559 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 560) + #if defined(INT_VECTOR_PE1_IRQ_560) + INT_VECTOR_PE1_IRQ_560, /* EIC560 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 561) + #if defined(INT_VECTOR_PE1_IRQ_561) + INT_VECTOR_PE1_IRQ_561, /* EIC561 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 562) + #if defined(INT_VECTOR_PE1_IRQ_562) + INT_VECTOR_PE1_IRQ_562, /* EIC562 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 563) + #if defined(INT_VECTOR_PE1_IRQ_563) + INT_VECTOR_PE1_IRQ_563, /* EIC563 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 564) + #if defined(INT_VECTOR_PE1_IRQ_564) + INT_VECTOR_PE1_IRQ_564, /* EIC564 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 565) + #if defined(INT_VECTOR_PE1_IRQ_565) + INT_VECTOR_PE1_IRQ_565, /* EIC565 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 566) + #if defined(INT_VECTOR_PE1_IRQ_566) + INT_VECTOR_PE1_IRQ_566, /* EIC566 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 567) + #if defined(INT_VECTOR_PE1_IRQ_567) + INT_VECTOR_PE1_IRQ_567, /* EIC567 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 568) + #if defined(INT_VECTOR_PE1_IRQ_568) + INT_VECTOR_PE1_IRQ_568, /* EIC568 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 569) + #if defined(INT_VECTOR_PE1_IRQ_569) + INT_VECTOR_PE1_IRQ_569, /* EIC569 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 570) + #if defined(INT_VECTOR_PE1_IRQ_570) + INT_VECTOR_PE1_IRQ_570, /* EIC570 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 571) + #if defined(INT_VECTOR_PE1_IRQ_571) + INT_VECTOR_PE1_IRQ_571, /* EIC571 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 572) + #if defined(INT_VECTOR_PE1_IRQ_572) + INT_VECTOR_PE1_IRQ_572, /* EIC572 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 573) + #if defined(INT_VECTOR_PE1_IRQ_573) + INT_VECTOR_PE1_IRQ_573, /* EIC573 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 574) + #if defined(INT_VECTOR_PE1_IRQ_574) + INT_VECTOR_PE1_IRQ_574, /* EIC574 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 575) + #if defined(INT_VECTOR_PE1_IRQ_575) + INT_VECTOR_PE1_IRQ_575, /* EIC575 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 576) + #if defined(INT_VECTOR_PE1_IRQ_576) + INT_VECTOR_PE1_IRQ_576, /* EIC576 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 577) + #if defined(INT_VECTOR_PE1_IRQ_577) + INT_VECTOR_PE1_IRQ_577, /* EIC577 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 578) + #if defined(INT_VECTOR_PE1_IRQ_578) + INT_VECTOR_PE1_IRQ_578, /* EIC578 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 579) + #if defined(INT_VECTOR_PE1_IRQ_579) + INT_VECTOR_PE1_IRQ_579, /* EIC579 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 580) + #if defined(INT_VECTOR_PE1_IRQ_580) + INT_VECTOR_PE1_IRQ_580, /* EIC580 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 581) + #if defined(INT_VECTOR_PE1_IRQ_581) + INT_VECTOR_PE1_IRQ_581, /* EIC581 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 582) + #if defined(INT_VECTOR_PE1_IRQ_582) + INT_VECTOR_PE1_IRQ_582, /* EIC582 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 583) + #if defined(INT_VECTOR_PE1_IRQ_583) + INT_VECTOR_PE1_IRQ_583, /* EIC583 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 584) + #if defined(INT_VECTOR_PE1_IRQ_584) + INT_VECTOR_PE1_IRQ_584, /* EIC584 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 585) + #if defined(INT_VECTOR_PE1_IRQ_585) + INT_VECTOR_PE1_IRQ_585, /* EIC585 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 586) + #if defined(INT_VECTOR_PE1_IRQ_586) + INT_VECTOR_PE1_IRQ_586, /* EIC586 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 587) + #if defined(INT_VECTOR_PE1_IRQ_587) + INT_VECTOR_PE1_IRQ_587, /* EIC587 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 588) + #if defined(INT_VECTOR_PE1_IRQ_588) + INT_VECTOR_PE1_IRQ_588, /* EIC588 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 589) + #if defined(INT_VECTOR_PE1_IRQ_589) + INT_VECTOR_PE1_IRQ_589, /* EIC589 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 590) + #if defined(INT_VECTOR_PE1_IRQ_590) + INT_VECTOR_PE1_IRQ_590, /* EIC590 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 591) + #if defined(INT_VECTOR_PE1_IRQ_591) + INT_VECTOR_PE1_IRQ_591, /* EIC591 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 592) + #if defined(INT_VECTOR_PE1_IRQ_592) + INT_VECTOR_PE1_IRQ_592, /* EIC592 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 593) + #if defined(INT_VECTOR_PE1_IRQ_593) + INT_VECTOR_PE1_IRQ_593, /* EIC593 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 594) + #if defined(INT_VECTOR_PE1_IRQ_594) + INT_VECTOR_PE1_IRQ_594, /* EIC594 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 595) + #if defined(INT_VECTOR_PE1_IRQ_595) + INT_VECTOR_PE1_IRQ_595, /* EIC595 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 596) + #if defined(INT_VECTOR_PE1_IRQ_596) + INT_VECTOR_PE1_IRQ_596, /* EIC596 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 597) + #if defined(INT_VECTOR_PE1_IRQ_597) + INT_VECTOR_PE1_IRQ_597, /* EIC597 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 598) + #if defined(INT_VECTOR_PE1_IRQ_598) + INT_VECTOR_PE1_IRQ_598, /* EIC598 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 599) + #if defined(INT_VECTOR_PE1_IRQ_599) + INT_VECTOR_PE1_IRQ_599, /* EIC599 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 600) + #if defined(INT_VECTOR_PE1_IRQ_600) + INT_VECTOR_PE1_IRQ_600, /* EIC600 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 601) + #if defined(INT_VECTOR_PE1_IRQ_601) + INT_VECTOR_PE1_IRQ_601, /* EIC601 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 602) + #if defined(INT_VECTOR_PE1_IRQ_602) + INT_VECTOR_PE1_IRQ_602, /* EIC602 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 603) + #if defined(INT_VECTOR_PE1_IRQ_603) + INT_VECTOR_PE1_IRQ_603, /* EIC603 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 604) + #if defined(INT_VECTOR_PE1_IRQ_604) + INT_VECTOR_PE1_IRQ_604, /* EIC604 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 605) + #if defined(INT_VECTOR_PE1_IRQ_605) + INT_VECTOR_PE1_IRQ_605, /* EIC605 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 606) + #if defined(INT_VECTOR_PE1_IRQ_606) + INT_VECTOR_PE1_IRQ_606, /* EIC606 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 607) + #if defined(INT_VECTOR_PE1_IRQ_607) + INT_VECTOR_PE1_IRQ_607, /* EIC607 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 608) + #if defined(INT_VECTOR_PE1_IRQ_608) + INT_VECTOR_PE1_IRQ_608, /* EIC608 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 609) + #if defined(INT_VECTOR_PE1_IRQ_609) + INT_VECTOR_PE1_IRQ_609, /* EIC609 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 610) + #if defined(INT_VECTOR_PE1_IRQ_610) + INT_VECTOR_PE1_IRQ_610, /* EIC610 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 611) + #if defined(INT_VECTOR_PE1_IRQ_611) + INT_VECTOR_PE1_IRQ_611, /* EIC611 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 612) + #if defined(INT_VECTOR_PE1_IRQ_612) + INT_VECTOR_PE1_IRQ_612, /* EIC612 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 613) + #if defined(INT_VECTOR_PE1_IRQ_613) + INT_VECTOR_PE1_IRQ_613, /* EIC613 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 614) + #if defined(INT_VECTOR_PE1_IRQ_614) + INT_VECTOR_PE1_IRQ_614, /* EIC614 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 615) + #if defined(INT_VECTOR_PE1_IRQ_615) + INT_VECTOR_PE1_IRQ_615, /* EIC615 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 616) + #if defined(INT_VECTOR_PE1_IRQ_616) + INT_VECTOR_PE1_IRQ_616, /* EIC616 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 617) + #if defined(INT_VECTOR_PE1_IRQ_617) + INT_VECTOR_PE1_IRQ_617, /* EIC617 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 618) + #if defined(INT_VECTOR_PE1_IRQ_618) + INT_VECTOR_PE1_IRQ_618, /* EIC618 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 619) + #if defined(INT_VECTOR_PE1_IRQ_619) + INT_VECTOR_PE1_IRQ_619, /* EIC619 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 620) + #if defined(INT_VECTOR_PE1_IRQ_620) + INT_VECTOR_PE1_IRQ_620, /* EIC620 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 621) + #if defined(INT_VECTOR_PE1_IRQ_621) + INT_VECTOR_PE1_IRQ_621, /* EIC621 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 622) + #if defined(INT_VECTOR_PE1_IRQ_622) + INT_VECTOR_PE1_IRQ_622, /* EIC622 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 623) + #if defined(INT_VECTOR_PE1_IRQ_623) + INT_VECTOR_PE1_IRQ_623, /* EIC623 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 624) + #if defined(INT_VECTOR_PE1_IRQ_624) + INT_VECTOR_PE1_IRQ_624, /* EIC624 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 625) + #if defined(INT_VECTOR_PE1_IRQ_625) + INT_VECTOR_PE1_IRQ_625, /* EIC625 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 626) + #if defined(INT_VECTOR_PE1_IRQ_626) + INT_VECTOR_PE1_IRQ_626, /* EIC626 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 627) + #if defined(INT_VECTOR_PE1_IRQ_627) + INT_VECTOR_PE1_IRQ_627, /* EIC627 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 628) + #if defined(INT_VECTOR_PE1_IRQ_628) + INT_VECTOR_PE1_IRQ_628, /* EIC628 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 629) + #if defined(INT_VECTOR_PE1_IRQ_629) + INT_VECTOR_PE1_IRQ_629, /* EIC629 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 630) + #if defined(INT_VECTOR_PE1_IRQ_630) + INT_VECTOR_PE1_IRQ_630, /* EIC630 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 631) + #if defined(INT_VECTOR_PE1_IRQ_631) + INT_VECTOR_PE1_IRQ_631, /* EIC631 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 632) + #if defined(INT_VECTOR_PE1_IRQ_632) + INT_VECTOR_PE1_IRQ_632, /* EIC632 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 633) + #if defined(INT_VECTOR_PE1_IRQ_633) + INT_VECTOR_PE1_IRQ_633, /* EIC633 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 634) + #if defined(INT_VECTOR_PE1_IRQ_634) + INT_VECTOR_PE1_IRQ_634, /* EIC634 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 635) + #if defined(INT_VECTOR_PE1_IRQ_635) + INT_VECTOR_PE1_IRQ_635, /* EIC635 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 636) + #if defined(INT_VECTOR_PE1_IRQ_636) + INT_VECTOR_PE1_IRQ_636, /* EIC636 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 637) + #if defined(INT_VECTOR_PE1_IRQ_637) + INT_VECTOR_PE1_IRQ_637, /* EIC637 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 638) + #if defined(INT_VECTOR_PE1_IRQ_638) + INT_VECTOR_PE1_IRQ_638, /* EIC638 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 639) + #if defined(INT_VECTOR_PE1_IRQ_639) + INT_VECTOR_PE1_IRQ_639, /* EIC639 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 640) + #if defined(INT_VECTOR_PE1_IRQ_640) + INT_VECTOR_PE1_IRQ_640, /* EIC640 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 641) + #if defined(INT_VECTOR_PE1_IRQ_641) + INT_VECTOR_PE1_IRQ_641, /* EIC641 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 642) + #if defined(INT_VECTOR_PE1_IRQ_642) + INT_VECTOR_PE1_IRQ_642, /* EIC642 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 643) + #if defined(INT_VECTOR_PE1_IRQ_643) + INT_VECTOR_PE1_IRQ_643, /* EIC643 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 644) + #if defined(INT_VECTOR_PE1_IRQ_644) + INT_VECTOR_PE1_IRQ_644, /* EIC644 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 645) + #if defined(INT_VECTOR_PE1_IRQ_645) + INT_VECTOR_PE1_IRQ_645, /* EIC645 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 646) + #if defined(INT_VECTOR_PE1_IRQ_646) + INT_VECTOR_PE1_IRQ_646, /* EIC646 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 647) + #if defined(INT_VECTOR_PE1_IRQ_647) + INT_VECTOR_PE1_IRQ_647, /* EIC647 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 648) + #if defined(INT_VECTOR_PE1_IRQ_648) + INT_VECTOR_PE1_IRQ_648, /* EIC648 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 649) + #if defined(INT_VECTOR_PE1_IRQ_649) + INT_VECTOR_PE1_IRQ_649, /* EIC649 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 650) + #if defined(INT_VECTOR_PE1_IRQ_650) + INT_VECTOR_PE1_IRQ_650, /* EIC650 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 651) + #if defined(INT_VECTOR_PE1_IRQ_651) + INT_VECTOR_PE1_IRQ_651, /* EIC651 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 652) + #if defined(INT_VECTOR_PE1_IRQ_652) + INT_VECTOR_PE1_IRQ_652, /* EIC652 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 653) + #if defined(INT_VECTOR_PE1_IRQ_653) + INT_VECTOR_PE1_IRQ_653, /* EIC653 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 654) + #if defined(INT_VECTOR_PE1_IRQ_654) + INT_VECTOR_PE1_IRQ_654, /* EIC654 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 655) + #if defined(INT_VECTOR_PE1_IRQ_655) + INT_VECTOR_PE1_IRQ_655, /* EIC655 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 656) + #if defined(INT_VECTOR_PE1_IRQ_656) + INT_VECTOR_PE1_IRQ_656, /* EIC656 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 657) + #if defined(INT_VECTOR_PE1_IRQ_657) + INT_VECTOR_PE1_IRQ_657, /* EIC657 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 658) + #if defined(INT_VECTOR_PE1_IRQ_658) + INT_VECTOR_PE1_IRQ_658, /* EIC658 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 659) + #if defined(INT_VECTOR_PE1_IRQ_659) + INT_VECTOR_PE1_IRQ_659, /* EIC659 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 660) + #if defined(INT_VECTOR_PE1_IRQ_660) + INT_VECTOR_PE1_IRQ_660, /* EIC660 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 661) + #if defined(INT_VECTOR_PE1_IRQ_661) + INT_VECTOR_PE1_IRQ_661, /* EIC661 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 662) + #if defined(INT_VECTOR_PE1_IRQ_662) + INT_VECTOR_PE1_IRQ_662, /* EIC662 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 663) + #if defined(INT_VECTOR_PE1_IRQ_663) + INT_VECTOR_PE1_IRQ_663, /* EIC663 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 664) + #if defined(INT_VECTOR_PE1_IRQ_664) + INT_VECTOR_PE1_IRQ_664, /* EIC664 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 665) + #if defined(INT_VECTOR_PE1_IRQ_665) + INT_VECTOR_PE1_IRQ_665, /* EIC665 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 666) + #if defined(INT_VECTOR_PE1_IRQ_666) + INT_VECTOR_PE1_IRQ_666, /* EIC666 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 667) + #if defined(INT_VECTOR_PE1_IRQ_667) + INT_VECTOR_PE1_IRQ_667, /* EIC667 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 668) + #if defined(INT_VECTOR_PE1_IRQ_668) + INT_VECTOR_PE1_IRQ_668, /* EIC668 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 669) + #if defined(INT_VECTOR_PE1_IRQ_669) + INT_VECTOR_PE1_IRQ_669, /* EIC669 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 670) + #if defined(INT_VECTOR_PE1_IRQ_670) + INT_VECTOR_PE1_IRQ_670, /* EIC670 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 671) + #if defined(INT_VECTOR_PE1_IRQ_671) + INT_VECTOR_PE1_IRQ_671, /* EIC671 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 672) + #if defined(INT_VECTOR_PE1_IRQ_672) + INT_VECTOR_PE1_IRQ_672, /* EIC672 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 673) + #if defined(INT_VECTOR_PE1_IRQ_673) + INT_VECTOR_PE1_IRQ_673, /* EIC673 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 674) + #if defined(INT_VECTOR_PE1_IRQ_674) + INT_VECTOR_PE1_IRQ_674, /* EIC674 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 675) + #if defined(INT_VECTOR_PE1_IRQ_675) + INT_VECTOR_PE1_IRQ_675, /* EIC675 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 676) + #if defined(INT_VECTOR_PE1_IRQ_676) + INT_VECTOR_PE1_IRQ_676, /* EIC676 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 677) + #if defined(INT_VECTOR_PE1_IRQ_677) + INT_VECTOR_PE1_IRQ_677, /* EIC677 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 678) + #if defined(INT_VECTOR_PE1_IRQ_678) + INT_VECTOR_PE1_IRQ_678, /* EIC678 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 679) + #if defined(INT_VECTOR_PE1_IRQ_679) + INT_VECTOR_PE1_IRQ_679, /* EIC679 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 680) + #if defined(INT_VECTOR_PE1_IRQ_680) + INT_VECTOR_PE1_IRQ_680, /* EIC680 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 681) + #if defined(INT_VECTOR_PE1_IRQ_681) + INT_VECTOR_PE1_IRQ_681, /* EIC681 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 682) + #if defined(INT_VECTOR_PE1_IRQ_682) + INT_VECTOR_PE1_IRQ_682, /* EIC682 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 683) + #if defined(INT_VECTOR_PE1_IRQ_683) + INT_VECTOR_PE1_IRQ_683, /* EIC683 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 684) + #if defined(INT_VECTOR_PE1_IRQ_684) + INT_VECTOR_PE1_IRQ_684, /* EIC684 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 685) + #if defined(INT_VECTOR_PE1_IRQ_685) + INT_VECTOR_PE1_IRQ_685, /* EIC685 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 686) + #if defined(INT_VECTOR_PE1_IRQ_686) + INT_VECTOR_PE1_IRQ_686, /* EIC686 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 687) + #if defined(INT_VECTOR_PE1_IRQ_687) + INT_VECTOR_PE1_IRQ_687, /* EIC687 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 688) + #if defined(INT_VECTOR_PE1_IRQ_688) + INT_VECTOR_PE1_IRQ_688, /* EIC688 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 689) + #if defined(INT_VECTOR_PE1_IRQ_689) + INT_VECTOR_PE1_IRQ_689, /* EIC689 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 690) + #if defined(INT_VECTOR_PE1_IRQ_690) + INT_VECTOR_PE1_IRQ_690, /* EIC690 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 691) + #if defined(INT_VECTOR_PE1_IRQ_691) + INT_VECTOR_PE1_IRQ_691, /* EIC691 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 692) + #if defined(INT_VECTOR_PE1_IRQ_692) + INT_VECTOR_PE1_IRQ_692, /* EIC692 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 693) + #if defined(INT_VECTOR_PE1_IRQ_693) + INT_VECTOR_PE1_IRQ_693, /* EIC693 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 694) + #if defined(INT_VECTOR_PE1_IRQ_694) + INT_VECTOR_PE1_IRQ_694, /* EIC694 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 695) + #if defined(INT_VECTOR_PE1_IRQ_695) + INT_VECTOR_PE1_IRQ_695, /* EIC695 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 696) + #if defined(INT_VECTOR_PE1_IRQ_696) + INT_VECTOR_PE1_IRQ_696, /* EIC696 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 697) + #if defined(INT_VECTOR_PE1_IRQ_697) + INT_VECTOR_PE1_IRQ_697, /* EIC697 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 698) + #if defined(INT_VECTOR_PE1_IRQ_698) + INT_VECTOR_PE1_IRQ_698, /* EIC698 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 699) + #if defined(INT_VECTOR_PE1_IRQ_699) + INT_VECTOR_PE1_IRQ_699, /* EIC699 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 700) + #if defined(INT_VECTOR_PE1_IRQ_700) + INT_VECTOR_PE1_IRQ_700, /* EIC700 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 701) + #if defined(INT_VECTOR_PE1_IRQ_701) + INT_VECTOR_PE1_IRQ_701, /* EIC701 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 702) + #if defined(INT_VECTOR_PE1_IRQ_702) + INT_VECTOR_PE1_IRQ_702, /* EIC702 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 703) + #if defined(INT_VECTOR_PE1_IRQ_703) + INT_VECTOR_PE1_IRQ_703, /* EIC703 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 704) + #if defined(INT_VECTOR_PE1_IRQ_704) + INT_VECTOR_PE1_IRQ_704, /* EIC704 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 705) + #if defined(INT_VECTOR_PE1_IRQ_705) + INT_VECTOR_PE1_IRQ_705, /* EIC705 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 706) + #if defined(INT_VECTOR_PE1_IRQ_706) + INT_VECTOR_PE1_IRQ_706, /* EIC706 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 707) + #if defined(INT_VECTOR_PE1_IRQ_707) + INT_VECTOR_PE1_IRQ_707, /* EIC707 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 708) + #if defined(INT_VECTOR_PE1_IRQ_708) + INT_VECTOR_PE1_IRQ_708, /* EIC708 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 709) + #if defined(INT_VECTOR_PE1_IRQ_709) + INT_VECTOR_PE1_IRQ_709, /* EIC709 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 710) + #if defined(INT_VECTOR_PE1_IRQ_710) + INT_VECTOR_PE1_IRQ_710, /* EIC710 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 711) + #if defined(INT_VECTOR_PE1_IRQ_711) + INT_VECTOR_PE1_IRQ_711, /* EIC711 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 712) + #if defined(INT_VECTOR_PE1_IRQ_712) + INT_VECTOR_PE1_IRQ_712, /* EIC712 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 713) + #if defined(INT_VECTOR_PE1_IRQ_713) + INT_VECTOR_PE1_IRQ_713, /* EIC713 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 714) + #if defined(INT_VECTOR_PE1_IRQ_714) + INT_VECTOR_PE1_IRQ_714, /* EIC714 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 715) + #if defined(INT_VECTOR_PE1_IRQ_715) + INT_VECTOR_PE1_IRQ_715, /* EIC715 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 716) + #if defined(INT_VECTOR_PE1_IRQ_716) + INT_VECTOR_PE1_IRQ_716, /* EIC716 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 717) + #if defined(INT_VECTOR_PE1_IRQ_717) + INT_VECTOR_PE1_IRQ_717, /* EIC717 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 718) + #if defined(INT_VECTOR_PE1_IRQ_718) + INT_VECTOR_PE1_IRQ_718, /* EIC718 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 719) + #if defined(INT_VECTOR_PE1_IRQ_719) + INT_VECTOR_PE1_IRQ_719, /* EIC719 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 720) + #if defined(INT_VECTOR_PE1_IRQ_720) + INT_VECTOR_PE1_IRQ_720, /* EIC720 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 721) + #if defined(INT_VECTOR_PE1_IRQ_721) + INT_VECTOR_PE1_IRQ_721, /* EIC721 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 722) + #if defined(INT_VECTOR_PE1_IRQ_722) + INT_VECTOR_PE1_IRQ_722, /* EIC722 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 723) + #if defined(INT_VECTOR_PE1_IRQ_723) + INT_VECTOR_PE1_IRQ_723, /* EIC723 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 724) + #if defined(INT_VECTOR_PE1_IRQ_724) + INT_VECTOR_PE1_IRQ_724, /* EIC724 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 725) + #if defined(INT_VECTOR_PE1_IRQ_725) + INT_VECTOR_PE1_IRQ_725, /* EIC725 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 726) + #if defined(INT_VECTOR_PE1_IRQ_726) + INT_VECTOR_PE1_IRQ_726, /* EIC726 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 727) + #if defined(INT_VECTOR_PE1_IRQ_727) + INT_VECTOR_PE1_IRQ_727, /* EIC727 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 728) + #if defined(INT_VECTOR_PE1_IRQ_728) + INT_VECTOR_PE1_IRQ_728, /* EIC728 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 729) + #if defined(INT_VECTOR_PE1_IRQ_729) + INT_VECTOR_PE1_IRQ_729, /* EIC729 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 730) + #if defined(INT_VECTOR_PE1_IRQ_730) + INT_VECTOR_PE1_IRQ_730, /* EIC730 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 731) + #if defined(INT_VECTOR_PE1_IRQ_731) + INT_VECTOR_PE1_IRQ_731, /* EIC731 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 732) + #if defined(INT_VECTOR_PE1_IRQ_732) + INT_VECTOR_PE1_IRQ_732, /* EIC732 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 733) + #if defined(INT_VECTOR_PE1_IRQ_733) + INT_VECTOR_PE1_IRQ_733, /* EIC733 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 734) + #if defined(INT_VECTOR_PE1_IRQ_734) + INT_VECTOR_PE1_IRQ_734, /* EIC734 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 735) + #if defined(INT_VECTOR_PE1_IRQ_735) + INT_VECTOR_PE1_IRQ_735, /* EIC735 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 736) + #if defined(INT_VECTOR_PE1_IRQ_736) + INT_VECTOR_PE1_IRQ_736, /* EIC736 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 737) + #if defined(INT_VECTOR_PE1_IRQ_737) + INT_VECTOR_PE1_IRQ_737, /* EIC737 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 738) + #if defined(INT_VECTOR_PE1_IRQ_738) + INT_VECTOR_PE1_IRQ_738, /* EIC738 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 739) + #if defined(INT_VECTOR_PE1_IRQ_739) + INT_VECTOR_PE1_IRQ_739, /* EIC739 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 740) + #if defined(INT_VECTOR_PE1_IRQ_740) + INT_VECTOR_PE1_IRQ_740, /* EIC740 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 741) + #if defined(INT_VECTOR_PE1_IRQ_741) + INT_VECTOR_PE1_IRQ_741, /* EIC741 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 742) + #if defined(INT_VECTOR_PE1_IRQ_742) + INT_VECTOR_PE1_IRQ_742, /* EIC742 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 743) + #if defined(INT_VECTOR_PE1_IRQ_743) + INT_VECTOR_PE1_IRQ_743, /* EIC743 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 744) + #if defined(INT_VECTOR_PE1_IRQ_744) + INT_VECTOR_PE1_IRQ_744, /* EIC744 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 745) + #if defined(INT_VECTOR_PE1_IRQ_745) + INT_VECTOR_PE1_IRQ_745, /* EIC745 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 746) + #if defined(INT_VECTOR_PE1_IRQ_746) + INT_VECTOR_PE1_IRQ_746, /* EIC746 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 747) + #if defined(INT_VECTOR_PE1_IRQ_747) + INT_VECTOR_PE1_IRQ_747, /* EIC747 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 748) + #if defined(INT_VECTOR_PE1_IRQ_748) + INT_VECTOR_PE1_IRQ_748, /* EIC748 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 749) + #if defined(INT_VECTOR_PE1_IRQ_749) + INT_VECTOR_PE1_IRQ_749, /* EIC749 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 750) + #if defined(INT_VECTOR_PE1_IRQ_750) + INT_VECTOR_PE1_IRQ_750, /* EIC750 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 751) + #if defined(INT_VECTOR_PE1_IRQ_751) + INT_VECTOR_PE1_IRQ_751, /* EIC751 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 752) + #if defined(INT_VECTOR_PE1_IRQ_752) + INT_VECTOR_PE1_IRQ_752, /* EIC752 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 753) + #if defined(INT_VECTOR_PE1_IRQ_753) + INT_VECTOR_PE1_IRQ_753, /* EIC753 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 754) + #if defined(INT_VECTOR_PE1_IRQ_754) + INT_VECTOR_PE1_IRQ_754, /* EIC754 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 755) + #if defined(INT_VECTOR_PE1_IRQ_755) + INT_VECTOR_PE1_IRQ_755, /* EIC755 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 756) + #if defined(INT_VECTOR_PE1_IRQ_756) + INT_VECTOR_PE1_IRQ_756, /* EIC756 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 757) + #if defined(INT_VECTOR_PE1_IRQ_757) + INT_VECTOR_PE1_IRQ_757, /* EIC757 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 758) + #if defined(INT_VECTOR_PE1_IRQ_758) + INT_VECTOR_PE1_IRQ_758, /* EIC758 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 759) + #if defined(INT_VECTOR_PE1_IRQ_759) + INT_VECTOR_PE1_IRQ_759, /* EIC759 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 760) + #if defined(INT_VECTOR_PE1_IRQ_760) + INT_VECTOR_PE1_IRQ_760, /* EIC760 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 761) + #if defined(INT_VECTOR_PE1_IRQ_761) + INT_VECTOR_PE1_IRQ_761, /* EIC761 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 762) + #if defined(INT_VECTOR_PE1_IRQ_762) + INT_VECTOR_PE1_IRQ_762, /* EIC762 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 763) + #if defined(INT_VECTOR_PE1_IRQ_763) + INT_VECTOR_PE1_IRQ_763, /* EIC763 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 764) + #if defined(INT_VECTOR_PE1_IRQ_764) + INT_VECTOR_PE1_IRQ_764, /* EIC764 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 765) + #if defined(INT_VECTOR_PE1_IRQ_765) + INT_VECTOR_PE1_IRQ_765, /* EIC765 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 766) + #if defined(INT_VECTOR_PE1_IRQ_766) + INT_VECTOR_PE1_IRQ_766, /* EIC766 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 767) + #if defined(INT_VECTOR_PE1_IRQ_767) + INT_VECTOR_PE1_IRQ_767, /* EIC767 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 768) + #if defined(INT_VECTOR_PE1_IRQ_768) + INT_VECTOR_PE1_IRQ_768, /* EIC768 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 769) + #if defined(INT_VECTOR_PE1_IRQ_769) + INT_VECTOR_PE1_IRQ_769, /* EIC769 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 770) + #if defined(INT_VECTOR_PE1_IRQ_770) + INT_VECTOR_PE1_IRQ_770, /* EIC770 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 771) + #if defined(INT_VECTOR_PE1_IRQ_771) + INT_VECTOR_PE1_IRQ_771, /* EIC771 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 772) + #if defined(INT_VECTOR_PE1_IRQ_772) + INT_VECTOR_PE1_IRQ_772, /* EIC772 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 773) + #if defined(INT_VECTOR_PE1_IRQ_773) + INT_VECTOR_PE1_IRQ_773, /* EIC773 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 774) + #if defined(INT_VECTOR_PE1_IRQ_774) + INT_VECTOR_PE1_IRQ_774, /* EIC774 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 775) + #if defined(INT_VECTOR_PE1_IRQ_775) + INT_VECTOR_PE1_IRQ_775, /* EIC775 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 776) + #if defined(INT_VECTOR_PE1_IRQ_776) + INT_VECTOR_PE1_IRQ_776, /* EIC776 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 777) + #if defined(INT_VECTOR_PE1_IRQ_777) + INT_VECTOR_PE1_IRQ_777, /* EIC777 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 778) + #if defined(INT_VECTOR_PE1_IRQ_778) + INT_VECTOR_PE1_IRQ_778, /* EIC778 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 779) + #if defined(INT_VECTOR_PE1_IRQ_779) + INT_VECTOR_PE1_IRQ_779, /* EIC779 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 780) + #if defined(INT_VECTOR_PE1_IRQ_780) + INT_VECTOR_PE1_IRQ_780, /* EIC780 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 781) + #if defined(INT_VECTOR_PE1_IRQ_781) + INT_VECTOR_PE1_IRQ_781, /* EIC781 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 782) + #if defined(INT_VECTOR_PE1_IRQ_782) + INT_VECTOR_PE1_IRQ_782, /* EIC782 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 783) + #if defined(INT_VECTOR_PE1_IRQ_783) + INT_VECTOR_PE1_IRQ_783, /* EIC783 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 784) + #if defined(INT_VECTOR_PE1_IRQ_784) + INT_VECTOR_PE1_IRQ_784, /* EIC784 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 785) + #if defined(INT_VECTOR_PE1_IRQ_785) + INT_VECTOR_PE1_IRQ_785, /* EIC785 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 786) + #if defined(INT_VECTOR_PE1_IRQ_786) + INT_VECTOR_PE1_IRQ_786, /* EIC786 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 787) + #if defined(INT_VECTOR_PE1_IRQ_787) + INT_VECTOR_PE1_IRQ_787, /* EIC787 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 788) + #if defined(INT_VECTOR_PE1_IRQ_788) + INT_VECTOR_PE1_IRQ_788, /* EIC788 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 789) + #if defined(INT_VECTOR_PE1_IRQ_789) + INT_VECTOR_PE1_IRQ_789, /* EIC789 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 790) + #if defined(INT_VECTOR_PE1_IRQ_790) + INT_VECTOR_PE1_IRQ_790, /* EIC790 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 791) + #if defined(INT_VECTOR_PE1_IRQ_791) + INT_VECTOR_PE1_IRQ_791, /* EIC791 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 792) + #if defined(INT_VECTOR_PE1_IRQ_792) + INT_VECTOR_PE1_IRQ_792, /* EIC792 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 793) + #if defined(INT_VECTOR_PE1_IRQ_793) + INT_VECTOR_PE1_IRQ_793, /* EIC793 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 794) + #if defined(INT_VECTOR_PE1_IRQ_794) + INT_VECTOR_PE1_IRQ_794, /* EIC794 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 795) + #if defined(INT_VECTOR_PE1_IRQ_795) + INT_VECTOR_PE1_IRQ_795, /* EIC795 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 796) + #if defined(INT_VECTOR_PE1_IRQ_796) + INT_VECTOR_PE1_IRQ_796, /* EIC796 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 797) + #if defined(INT_VECTOR_PE1_IRQ_797) + INT_VECTOR_PE1_IRQ_797, /* EIC797 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 798) + #if defined(INT_VECTOR_PE1_IRQ_798) + INT_VECTOR_PE1_IRQ_798, /* EIC798 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 799) + #if defined(INT_VECTOR_PE1_IRQ_799) + INT_VECTOR_PE1_IRQ_799, /* EIC799 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 800) + #if defined(INT_VECTOR_PE1_IRQ_800) + INT_VECTOR_PE1_IRQ_800, /* EIC800 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 801) + #if defined(INT_VECTOR_PE1_IRQ_801) + INT_VECTOR_PE1_IRQ_801, /* EIC801 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 802) + #if defined(INT_VECTOR_PE1_IRQ_802) + INT_VECTOR_PE1_IRQ_802, /* EIC802 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 803) + #if defined(INT_VECTOR_PE1_IRQ_803) + INT_VECTOR_PE1_IRQ_803, /* EIC803 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 804) + #if defined(INT_VECTOR_PE1_IRQ_804) + INT_VECTOR_PE1_IRQ_804, /* EIC804 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 805) + #if defined(INT_VECTOR_PE1_IRQ_805) + INT_VECTOR_PE1_IRQ_805, /* EIC805 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 806) + #if defined(INT_VECTOR_PE1_IRQ_806) + INT_VECTOR_PE1_IRQ_806, /* EIC806 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 807) + #if defined(INT_VECTOR_PE1_IRQ_807) + INT_VECTOR_PE1_IRQ_807, /* EIC807 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 808) + #if defined(INT_VECTOR_PE1_IRQ_808) + INT_VECTOR_PE1_IRQ_808, /* EIC808 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 809) + #if defined(INT_VECTOR_PE1_IRQ_809) + INT_VECTOR_PE1_IRQ_809, /* EIC809 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 810) + #if defined(INT_VECTOR_PE1_IRQ_810) + INT_VECTOR_PE1_IRQ_810, /* EIC810 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 811) + #if defined(INT_VECTOR_PE1_IRQ_811) + INT_VECTOR_PE1_IRQ_811, /* EIC811 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 812) + #if defined(INT_VECTOR_PE1_IRQ_812) + INT_VECTOR_PE1_IRQ_812, /* EIC812 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 813) + #if defined(INT_VECTOR_PE1_IRQ_813) + INT_VECTOR_PE1_IRQ_813, /* EIC813 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 814) + #if defined(INT_VECTOR_PE1_IRQ_814) + INT_VECTOR_PE1_IRQ_814, /* EIC814 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 815) + #if defined(INT_VECTOR_PE1_IRQ_815) + INT_VECTOR_PE1_IRQ_815, /* EIC815 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 816) + #if defined(INT_VECTOR_PE1_IRQ_816) + INT_VECTOR_PE1_IRQ_816, /* EIC816 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 817) + #if defined(INT_VECTOR_PE1_IRQ_817) + INT_VECTOR_PE1_IRQ_817, /* EIC817 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 818) + #if defined(INT_VECTOR_PE1_IRQ_818) + INT_VECTOR_PE1_IRQ_818, /* EIC818 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 819) + #if defined(INT_VECTOR_PE1_IRQ_819) + INT_VECTOR_PE1_IRQ_819, /* EIC819 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 820) + #if defined(INT_VECTOR_PE1_IRQ_820) + INT_VECTOR_PE1_IRQ_820, /* EIC820 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 821) + #if defined(INT_VECTOR_PE1_IRQ_821) + INT_VECTOR_PE1_IRQ_821, /* EIC821 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 822) + #if defined(INT_VECTOR_PE1_IRQ_822) + INT_VECTOR_PE1_IRQ_822, /* EIC822 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 823) + #if defined(INT_VECTOR_PE1_IRQ_823) + INT_VECTOR_PE1_IRQ_823, /* EIC823 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 824) + #if defined(INT_VECTOR_PE1_IRQ_824) + INT_VECTOR_PE1_IRQ_824, /* EIC824 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 825) + #if defined(INT_VECTOR_PE1_IRQ_825) + INT_VECTOR_PE1_IRQ_825, /* EIC825 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 826) + #if defined(INT_VECTOR_PE1_IRQ_826) + INT_VECTOR_PE1_IRQ_826, /* EIC826 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 827) + #if defined(INT_VECTOR_PE1_IRQ_827) + INT_VECTOR_PE1_IRQ_827, /* EIC827 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 828) + #if defined(INT_VECTOR_PE1_IRQ_828) + INT_VECTOR_PE1_IRQ_828, /* EIC828 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 829) + #if defined(INT_VECTOR_PE1_IRQ_829) + INT_VECTOR_PE1_IRQ_829, /* EIC829 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 830) + #if defined(INT_VECTOR_PE1_IRQ_830) + INT_VECTOR_PE1_IRQ_830, /* EIC830 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 831) + #if defined(INT_VECTOR_PE1_IRQ_831) + INT_VECTOR_PE1_IRQ_831, /* EIC831 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 832) + #if defined(INT_VECTOR_PE1_IRQ_832) + INT_VECTOR_PE1_IRQ_832, /* EIC832 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 833) + #if defined(INT_VECTOR_PE1_IRQ_833) + INT_VECTOR_PE1_IRQ_833, /* EIC833 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 834) + #if defined(INT_VECTOR_PE1_IRQ_834) + INT_VECTOR_PE1_IRQ_834, /* EIC834 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 835) + #if defined(INT_VECTOR_PE1_IRQ_835) + INT_VECTOR_PE1_IRQ_835, /* EIC835 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 836) + #if defined(INT_VECTOR_PE1_IRQ_836) + INT_VECTOR_PE1_IRQ_836, /* EIC836 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 837) + #if defined(INT_VECTOR_PE1_IRQ_837) + INT_VECTOR_PE1_IRQ_837, /* EIC837 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 838) + #if defined(INT_VECTOR_PE1_IRQ_838) + INT_VECTOR_PE1_IRQ_838, /* EIC838 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 839) + #if defined(INT_VECTOR_PE1_IRQ_839) + INT_VECTOR_PE1_IRQ_839, /* EIC839 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 840) + #if defined(INT_VECTOR_PE1_IRQ_840) + INT_VECTOR_PE1_IRQ_840, /* EIC840 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 841) + #if defined(INT_VECTOR_PE1_IRQ_841) + INT_VECTOR_PE1_IRQ_841, /* EIC841 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 842) + #if defined(INT_VECTOR_PE1_IRQ_842) + INT_VECTOR_PE1_IRQ_842, /* EIC842 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 843) + #if defined(INT_VECTOR_PE1_IRQ_843) + INT_VECTOR_PE1_IRQ_843, /* EIC843 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 844) + #if defined(INT_VECTOR_PE1_IRQ_844) + INT_VECTOR_PE1_IRQ_844, /* EIC844 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 845) + #if defined(INT_VECTOR_PE1_IRQ_845) + INT_VECTOR_PE1_IRQ_845, /* EIC845 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 846) + #if defined(INT_VECTOR_PE1_IRQ_846) + INT_VECTOR_PE1_IRQ_846, /* EIC846 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 847) + #if defined(INT_VECTOR_PE1_IRQ_847) + INT_VECTOR_PE1_IRQ_847, /* EIC847 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 848) + #if defined(INT_VECTOR_PE1_IRQ_848) + INT_VECTOR_PE1_IRQ_848, /* EIC848 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 849) + #if defined(INT_VECTOR_PE1_IRQ_849) + INT_VECTOR_PE1_IRQ_849, /* EIC849 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 850) + #if defined(INT_VECTOR_PE1_IRQ_850) + INT_VECTOR_PE1_IRQ_850, /* EIC850 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 851) + #if defined(INT_VECTOR_PE1_IRQ_851) + INT_VECTOR_PE1_IRQ_851, /* EIC851 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 852) + #if defined(INT_VECTOR_PE1_IRQ_852) + INT_VECTOR_PE1_IRQ_852, /* EIC852 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 853) + #if defined(INT_VECTOR_PE1_IRQ_853) + INT_VECTOR_PE1_IRQ_853, /* EIC853 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 854) + #if defined(INT_VECTOR_PE1_IRQ_854) + INT_VECTOR_PE1_IRQ_854, /* EIC854 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 855) + #if defined(INT_VECTOR_PE1_IRQ_855) + INT_VECTOR_PE1_IRQ_855, /* EIC855 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 856) + #if defined(INT_VECTOR_PE1_IRQ_856) + INT_VECTOR_PE1_IRQ_856, /* EIC856 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 857) + #if defined(INT_VECTOR_PE1_IRQ_857) + INT_VECTOR_PE1_IRQ_857, /* EIC857 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 858) + #if defined(INT_VECTOR_PE1_IRQ_858) + INT_VECTOR_PE1_IRQ_858, /* EIC858 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 859) + #if defined(INT_VECTOR_PE1_IRQ_859) + INT_VECTOR_PE1_IRQ_859, /* EIC859 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 860) + #if defined(INT_VECTOR_PE1_IRQ_860) + INT_VECTOR_PE1_IRQ_860, /* EIC860 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 861) + #if defined(INT_VECTOR_PE1_IRQ_861) + INT_VECTOR_PE1_IRQ_861, /* EIC861 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 862) + #if defined(INT_VECTOR_PE1_IRQ_862) + INT_VECTOR_PE1_IRQ_862, /* EIC862 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 863) + #if defined(INT_VECTOR_PE1_IRQ_863) + INT_VECTOR_PE1_IRQ_863, /* EIC863 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 864) + #if defined(INT_VECTOR_PE1_IRQ_864) + INT_VECTOR_PE1_IRQ_864, /* EIC864 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 865) + #if defined(INT_VECTOR_PE1_IRQ_865) + INT_VECTOR_PE1_IRQ_865, /* EIC865 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 866) + #if defined(INT_VECTOR_PE1_IRQ_866) + INT_VECTOR_PE1_IRQ_866, /* EIC866 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 867) + #if defined(INT_VECTOR_PE1_IRQ_867) + INT_VECTOR_PE1_IRQ_867, /* EIC867 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 868) + #if defined(INT_VECTOR_PE1_IRQ_868) + INT_VECTOR_PE1_IRQ_868, /* EIC868 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 869) + #if defined(INT_VECTOR_PE1_IRQ_869) + INT_VECTOR_PE1_IRQ_869, /* EIC869 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 870) + #if defined(INT_VECTOR_PE1_IRQ_870) + INT_VECTOR_PE1_IRQ_870, /* EIC870 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 871) + #if defined(INT_VECTOR_PE1_IRQ_871) + INT_VECTOR_PE1_IRQ_871, /* EIC871 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 872) + #if defined(INT_VECTOR_PE1_IRQ_872) + INT_VECTOR_PE1_IRQ_872, /* EIC872 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 873) + #if defined(INT_VECTOR_PE1_IRQ_873) + INT_VECTOR_PE1_IRQ_873, /* EIC873 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 874) + #if defined(INT_VECTOR_PE1_IRQ_874) + INT_VECTOR_PE1_IRQ_874, /* EIC874 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 875) + #if defined(INT_VECTOR_PE1_IRQ_875) + INT_VECTOR_PE1_IRQ_875, /* EIC875 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 876) + #if defined(INT_VECTOR_PE1_IRQ_876) + INT_VECTOR_PE1_IRQ_876, /* EIC876 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 877) + #if defined(INT_VECTOR_PE1_IRQ_877) + INT_VECTOR_PE1_IRQ_877, /* EIC877 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 878) + #if defined(INT_VECTOR_PE1_IRQ_878) + INT_VECTOR_PE1_IRQ_878, /* EIC878 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 879) + #if defined(INT_VECTOR_PE1_IRQ_879) + INT_VECTOR_PE1_IRQ_879, /* EIC879 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 880) + #if defined(INT_VECTOR_PE1_IRQ_880) + INT_VECTOR_PE1_IRQ_880, /* EIC880 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 881) + #if defined(INT_VECTOR_PE1_IRQ_881) + INT_VECTOR_PE1_IRQ_881, /* EIC881 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 882) + #if defined(INT_VECTOR_PE1_IRQ_882) + INT_VECTOR_PE1_IRQ_882, /* EIC882 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 883) + #if defined(INT_VECTOR_PE1_IRQ_883) + INT_VECTOR_PE1_IRQ_883, /* EIC883 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 884) + #if defined(INT_VECTOR_PE1_IRQ_884) + INT_VECTOR_PE1_IRQ_884, /* EIC884 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 885) + #if defined(INT_VECTOR_PE1_IRQ_885) + INT_VECTOR_PE1_IRQ_885, /* EIC885 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 886) + #if defined(INT_VECTOR_PE1_IRQ_886) + INT_VECTOR_PE1_IRQ_886, /* EIC886 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 887) + #if defined(INT_VECTOR_PE1_IRQ_887) + INT_VECTOR_PE1_IRQ_887, /* EIC887 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 888) + #if defined(INT_VECTOR_PE1_IRQ_888) + INT_VECTOR_PE1_IRQ_888, /* EIC888 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 889) + #if defined(INT_VECTOR_PE1_IRQ_889) + INT_VECTOR_PE1_IRQ_889, /* EIC889 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 890) + #if defined(INT_VECTOR_PE1_IRQ_890) + INT_VECTOR_PE1_IRQ_890, /* EIC890 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 891) + #if defined(INT_VECTOR_PE1_IRQ_891) + INT_VECTOR_PE1_IRQ_891, /* EIC891 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 892) + #if defined(INT_VECTOR_PE1_IRQ_892) + INT_VECTOR_PE1_IRQ_892, /* EIC892 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 893) + #if defined(INT_VECTOR_PE1_IRQ_893) + INT_VECTOR_PE1_IRQ_893, /* EIC893 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 894) + #if defined(INT_VECTOR_PE1_IRQ_894) + INT_VECTOR_PE1_IRQ_894, /* EIC894 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 895) + #if defined(INT_VECTOR_PE1_IRQ_895) + INT_VECTOR_PE1_IRQ_895, /* EIC895 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 896) + #if defined(INT_VECTOR_PE1_IRQ_896) + INT_VECTOR_PE1_IRQ_896, /* EIC896 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 897) + #if defined(INT_VECTOR_PE1_IRQ_897) + INT_VECTOR_PE1_IRQ_897, /* EIC897 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 898) + #if defined(INT_VECTOR_PE1_IRQ_898) + INT_VECTOR_PE1_IRQ_898, /* EIC898 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 899) + #if defined(INT_VECTOR_PE1_IRQ_899) + INT_VECTOR_PE1_IRQ_899, /* EIC899 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 900) + #if defined(INT_VECTOR_PE1_IRQ_900) + INT_VECTOR_PE1_IRQ_900, /* EIC900 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 901) + #if defined(INT_VECTOR_PE1_IRQ_901) + INT_VECTOR_PE1_IRQ_901, /* EIC901 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 902) + #if defined(INT_VECTOR_PE1_IRQ_902) + INT_VECTOR_PE1_IRQ_902, /* EIC902 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 903) + #if defined(INT_VECTOR_PE1_IRQ_903) + INT_VECTOR_PE1_IRQ_903, /* EIC903 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 904) + #if defined(INT_VECTOR_PE1_IRQ_904) + INT_VECTOR_PE1_IRQ_904, /* EIC904 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 905) + #if defined(INT_VECTOR_PE1_IRQ_905) + INT_VECTOR_PE1_IRQ_905, /* EIC905 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 906) + #if defined(INT_VECTOR_PE1_IRQ_906) + INT_VECTOR_PE1_IRQ_906, /* EIC906 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 907) + #if defined(INT_VECTOR_PE1_IRQ_907) + INT_VECTOR_PE1_IRQ_907, /* EIC907 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 908) + #if defined(INT_VECTOR_PE1_IRQ_908) + INT_VECTOR_PE1_IRQ_908, /* EIC908 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 909) + #if defined(INT_VECTOR_PE1_IRQ_909) + INT_VECTOR_PE1_IRQ_909, /* EIC909 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 910) + #if defined(INT_VECTOR_PE1_IRQ_910) + INT_VECTOR_PE1_IRQ_910, /* EIC910 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 911) + #if defined(INT_VECTOR_PE1_IRQ_911) + INT_VECTOR_PE1_IRQ_911, /* EIC911 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 912) + #if defined(INT_VECTOR_PE1_IRQ_912) + INT_VECTOR_PE1_IRQ_912, /* EIC912 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 913) + #if defined(INT_VECTOR_PE1_IRQ_913) + INT_VECTOR_PE1_IRQ_913, /* EIC913 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 914) + #if defined(INT_VECTOR_PE1_IRQ_914) + INT_VECTOR_PE1_IRQ_914, /* EIC914 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 915) + #if defined(INT_VECTOR_PE1_IRQ_915) + INT_VECTOR_PE1_IRQ_915, /* EIC915 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 916) + #if defined(INT_VECTOR_PE1_IRQ_916) + INT_VECTOR_PE1_IRQ_916, /* EIC916 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 917) + #if defined(INT_VECTOR_PE1_IRQ_917) + INT_VECTOR_PE1_IRQ_917, /* EIC917 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 918) + #if defined(INT_VECTOR_PE1_IRQ_918) + INT_VECTOR_PE1_IRQ_918, /* EIC918 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 919) + #if defined(INT_VECTOR_PE1_IRQ_919) + INT_VECTOR_PE1_IRQ_919, /* EIC919 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 920) + #if defined(INT_VECTOR_PE1_IRQ_920) + INT_VECTOR_PE1_IRQ_920, /* EIC920 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 921) + #if defined(INT_VECTOR_PE1_IRQ_921) + INT_VECTOR_PE1_IRQ_921, /* EIC921 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 922) + #if defined(INT_VECTOR_PE1_IRQ_922) + INT_VECTOR_PE1_IRQ_922, /* EIC922 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 923) + #if defined(INT_VECTOR_PE1_IRQ_923) + INT_VECTOR_PE1_IRQ_923, /* EIC923 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 924) + #if defined(INT_VECTOR_PE1_IRQ_924) + INT_VECTOR_PE1_IRQ_924, /* EIC924 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 925) + #if defined(INT_VECTOR_PE1_IRQ_925) + INT_VECTOR_PE1_IRQ_925, /* EIC925 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 926) + #if defined(INT_VECTOR_PE1_IRQ_926) + INT_VECTOR_PE1_IRQ_926, /* EIC926 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 927) + #if defined(INT_VECTOR_PE1_IRQ_927) + INT_VECTOR_PE1_IRQ_927, /* EIC927 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 928) + #if defined(INT_VECTOR_PE1_IRQ_928) + INT_VECTOR_PE1_IRQ_928, /* EIC928 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 929) + #if defined(INT_VECTOR_PE1_IRQ_929) + INT_VECTOR_PE1_IRQ_929, /* EIC929 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 930) + #if defined(INT_VECTOR_PE1_IRQ_930) + INT_VECTOR_PE1_IRQ_930, /* EIC930 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 931) + #if defined(INT_VECTOR_PE1_IRQ_931) + INT_VECTOR_PE1_IRQ_931, /* EIC931 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 932) + #if defined(INT_VECTOR_PE1_IRQ_932) + INT_VECTOR_PE1_IRQ_932, /* EIC932 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 933) + #if defined(INT_VECTOR_PE1_IRQ_933) + INT_VECTOR_PE1_IRQ_933, /* EIC933 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 934) + #if defined(INT_VECTOR_PE1_IRQ_934) + INT_VECTOR_PE1_IRQ_934, /* EIC934 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 935) + #if defined(INT_VECTOR_PE1_IRQ_935) + INT_VECTOR_PE1_IRQ_935, /* EIC935 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 936) + #if defined(INT_VECTOR_PE1_IRQ_936) + INT_VECTOR_PE1_IRQ_936, /* EIC936 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 937) + #if defined(INT_VECTOR_PE1_IRQ_937) + INT_VECTOR_PE1_IRQ_937, /* EIC937 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 938) + #if defined(INT_VECTOR_PE1_IRQ_938) + INT_VECTOR_PE1_IRQ_938, /* EIC938 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 939) + #if defined(INT_VECTOR_PE1_IRQ_939) + INT_VECTOR_PE1_IRQ_939, /* EIC939 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 940) + #if defined(INT_VECTOR_PE1_IRQ_940) + INT_VECTOR_PE1_IRQ_940, /* EIC940 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 941) + #if defined(INT_VECTOR_PE1_IRQ_941) + INT_VECTOR_PE1_IRQ_941, /* EIC941 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 942) + #if defined(INT_VECTOR_PE1_IRQ_942) + INT_VECTOR_PE1_IRQ_942, /* EIC942 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 943) + #if defined(INT_VECTOR_PE1_IRQ_943) + INT_VECTOR_PE1_IRQ_943, /* EIC943 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 944) + #if defined(INT_VECTOR_PE1_IRQ_944) + INT_VECTOR_PE1_IRQ_944, /* EIC944 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 945) + #if defined(INT_VECTOR_PE1_IRQ_945) + INT_VECTOR_PE1_IRQ_945, /* EIC945 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 946) + #if defined(INT_VECTOR_PE1_IRQ_946) + INT_VECTOR_PE1_IRQ_946, /* EIC946 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 947) + #if defined(INT_VECTOR_PE1_IRQ_947) + INT_VECTOR_PE1_IRQ_947, /* EIC947 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 948) + #if defined(INT_VECTOR_PE1_IRQ_948) + INT_VECTOR_PE1_IRQ_948, /* EIC948 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 949) + #if defined(INT_VECTOR_PE1_IRQ_949) + INT_VECTOR_PE1_IRQ_949, /* EIC949 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 950) + #if defined(INT_VECTOR_PE1_IRQ_950) + INT_VECTOR_PE1_IRQ_950, /* EIC950 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 951) + #if defined(INT_VECTOR_PE1_IRQ_951) + INT_VECTOR_PE1_IRQ_951, /* EIC951 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 952) + #if defined(INT_VECTOR_PE1_IRQ_952) + INT_VECTOR_PE1_IRQ_952, /* EIC952 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 953) + #if defined(INT_VECTOR_PE1_IRQ_953) + INT_VECTOR_PE1_IRQ_953, /* EIC953 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 954) + #if defined(INT_VECTOR_PE1_IRQ_954) + INT_VECTOR_PE1_IRQ_954, /* EIC954 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 955) + #if defined(INT_VECTOR_PE1_IRQ_955) + INT_VECTOR_PE1_IRQ_955, /* EIC955 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 956) + #if defined(INT_VECTOR_PE1_IRQ_956) + INT_VECTOR_PE1_IRQ_956, /* EIC956 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 957) + #if defined(INT_VECTOR_PE1_IRQ_957) + INT_VECTOR_PE1_IRQ_957, /* EIC957 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 958) + #if defined(INT_VECTOR_PE1_IRQ_958) + INT_VECTOR_PE1_IRQ_958, /* EIC958 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 959) + #if defined(INT_VECTOR_PE1_IRQ_959) + INT_VECTOR_PE1_IRQ_959, /* EIC959 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 960) + #if defined(INT_VECTOR_PE1_IRQ_960) + INT_VECTOR_PE1_IRQ_960, /* EIC960 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 961) + #if defined(INT_VECTOR_PE1_IRQ_961) + INT_VECTOR_PE1_IRQ_961, /* EIC961 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 962) + #if defined(INT_VECTOR_PE1_IRQ_962) + INT_VECTOR_PE1_IRQ_962, /* EIC962 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 963) + #if defined(INT_VECTOR_PE1_IRQ_963) + INT_VECTOR_PE1_IRQ_963, /* EIC963 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 964) + #if defined(INT_VECTOR_PE1_IRQ_964) + INT_VECTOR_PE1_IRQ_964, /* EIC964 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 965) + #if defined(INT_VECTOR_PE1_IRQ_965) + INT_VECTOR_PE1_IRQ_965, /* EIC965 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 966) + #if defined(INT_VECTOR_PE1_IRQ_966) + INT_VECTOR_PE1_IRQ_966, /* EIC966 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 967) + #if defined(INT_VECTOR_PE1_IRQ_967) + INT_VECTOR_PE1_IRQ_967, /* EIC967 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 968) + #if defined(INT_VECTOR_PE1_IRQ_968) + INT_VECTOR_PE1_IRQ_968, /* EIC968 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 969) + #if defined(INT_VECTOR_PE1_IRQ_969) + INT_VECTOR_PE1_IRQ_969, /* EIC969 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 970) + #if defined(INT_VECTOR_PE1_IRQ_970) + INT_VECTOR_PE1_IRQ_970, /* EIC970 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 971) + #if defined(INT_VECTOR_PE1_IRQ_971) + INT_VECTOR_PE1_IRQ_971, /* EIC971 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 972) + #if defined(INT_VECTOR_PE1_IRQ_972) + INT_VECTOR_PE1_IRQ_972, /* EIC972 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 973) + #if defined(INT_VECTOR_PE1_IRQ_973) + INT_VECTOR_PE1_IRQ_973, /* EIC973 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 974) + #if defined(INT_VECTOR_PE1_IRQ_974) + INT_VECTOR_PE1_IRQ_974, /* EIC974 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 975) + #if defined(INT_VECTOR_PE1_IRQ_975) + INT_VECTOR_PE1_IRQ_975, /* EIC975 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 976) + #if defined(INT_VECTOR_PE1_IRQ_976) + INT_VECTOR_PE1_IRQ_976, /* EIC976 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 977) + #if defined(INT_VECTOR_PE1_IRQ_977) + INT_VECTOR_PE1_IRQ_977, /* EIC977 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 978) + #if defined(INT_VECTOR_PE1_IRQ_978) + INT_VECTOR_PE1_IRQ_978, /* EIC978 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 979) + #if defined(INT_VECTOR_PE1_IRQ_979) + INT_VECTOR_PE1_IRQ_979, /* EIC979 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 980) + #if defined(INT_VECTOR_PE1_IRQ_980) + INT_VECTOR_PE1_IRQ_980, /* EIC980 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 981) + #if defined(INT_VECTOR_PE1_IRQ_981) + INT_VECTOR_PE1_IRQ_981, /* EIC981 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 982) + #if defined(INT_VECTOR_PE1_IRQ_982) + INT_VECTOR_PE1_IRQ_982, /* EIC982 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 983) + #if defined(INT_VECTOR_PE1_IRQ_983) + INT_VECTOR_PE1_IRQ_983, /* EIC983 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 984) + #if defined(INT_VECTOR_PE1_IRQ_984) + INT_VECTOR_PE1_IRQ_984, /* EIC984 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 985) + #if defined(INT_VECTOR_PE1_IRQ_985) + INT_VECTOR_PE1_IRQ_985, /* EIC985 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 986) + #if defined(INT_VECTOR_PE1_IRQ_986) + INT_VECTOR_PE1_IRQ_986, /* EIC986 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 987) + #if defined(INT_VECTOR_PE1_IRQ_987) + INT_VECTOR_PE1_IRQ_987, /* EIC987 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 988) + #if defined(INT_VECTOR_PE1_IRQ_988) + INT_VECTOR_PE1_IRQ_988, /* EIC988 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 989) + #if defined(INT_VECTOR_PE1_IRQ_989) + INT_VECTOR_PE1_IRQ_989, /* EIC989 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 990) + #if defined(INT_VECTOR_PE1_IRQ_990) + INT_VECTOR_PE1_IRQ_990, /* EIC990 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 991) + #if defined(INT_VECTOR_PE1_IRQ_991) + INT_VECTOR_PE1_IRQ_991, /* EIC991 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 992) + #if defined(INT_VECTOR_PE1_IRQ_992) + INT_VECTOR_PE1_IRQ_992, /* EIC992 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 993) + #if defined(INT_VECTOR_PE1_IRQ_993) + INT_VECTOR_PE1_IRQ_993, /* EIC993 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 994) + #if defined(INT_VECTOR_PE1_IRQ_994) + INT_VECTOR_PE1_IRQ_994, /* EIC994 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 995) + #if defined(INT_VECTOR_PE1_IRQ_995) + INT_VECTOR_PE1_IRQ_995, /* EIC995 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 996) + #if defined(INT_VECTOR_PE1_IRQ_996) + INT_VECTOR_PE1_IRQ_996, /* EIC996 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 997) + #if defined(INT_VECTOR_PE1_IRQ_997) + INT_VECTOR_PE1_IRQ_997, /* EIC997 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 998) + #if defined(INT_VECTOR_PE1_IRQ_998) + INT_VECTOR_PE1_IRQ_998, /* EIC998 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 999) + #if defined(INT_VECTOR_PE1_IRQ_999) + INT_VECTOR_PE1_IRQ_999, /* EIC999 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1000) + #if defined(INT_VECTOR_PE1_IRQ_1000) + INT_VECTOR_PE1_IRQ_1000, /* EIC1000 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1001) + #if defined(INT_VECTOR_PE1_IRQ_1001) + INT_VECTOR_PE1_IRQ_1001, /* EIC1001 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1002) + #if defined(INT_VECTOR_PE1_IRQ_1002) + INT_VECTOR_PE1_IRQ_1002, /* EIC1002 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1003) + #if defined(INT_VECTOR_PE1_IRQ_1003) + INT_VECTOR_PE1_IRQ_1003, /* EIC1003 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1004) + #if defined(INT_VECTOR_PE1_IRQ_1004) + INT_VECTOR_PE1_IRQ_1004, /* EIC1004 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1005) + #if defined(INT_VECTOR_PE1_IRQ_1005) + INT_VECTOR_PE1_IRQ_1005, /* EIC1005 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1006) + #if defined(INT_VECTOR_PE1_IRQ_1006) + INT_VECTOR_PE1_IRQ_1006, /* EIC1006 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1007) + #if defined(INT_VECTOR_PE1_IRQ_1007) + INT_VECTOR_PE1_IRQ_1007, /* EIC1007 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1008) + #if defined(INT_VECTOR_PE1_IRQ_1008) + INT_VECTOR_PE1_IRQ_1008, /* EIC1008 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1009) + #if defined(INT_VECTOR_PE1_IRQ_1009) + INT_VECTOR_PE1_IRQ_1009, /* EIC1009 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1010) + #if defined(INT_VECTOR_PE1_IRQ_1010) + INT_VECTOR_PE1_IRQ_1010, /* EIC1010 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1011) + #if defined(INT_VECTOR_PE1_IRQ_1011) + INT_VECTOR_PE1_IRQ_1011, /* EIC1011 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1012) + #if defined(INT_VECTOR_PE1_IRQ_1012) + INT_VECTOR_PE1_IRQ_1012, /* EIC1012 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1013) + #if defined(INT_VECTOR_PE1_IRQ_1013) + INT_VECTOR_PE1_IRQ_1013, /* EIC1013 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1014) + #if defined(INT_VECTOR_PE1_IRQ_1014) + INT_VECTOR_PE1_IRQ_1014, /* EIC1014 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1015) + #if defined(INT_VECTOR_PE1_IRQ_1015) + INT_VECTOR_PE1_IRQ_1015, /* EIC1015 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1016) + #if defined(INT_VECTOR_PE1_IRQ_1016) + INT_VECTOR_PE1_IRQ_1016, /* EIC1016 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1017) + #if defined(INT_VECTOR_PE1_IRQ_1017) + INT_VECTOR_PE1_IRQ_1017, /* EIC1017 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1018) + #if defined(INT_VECTOR_PE1_IRQ_1018) + INT_VECTOR_PE1_IRQ_1018, /* EIC1018 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1019) + #if defined(INT_VECTOR_PE1_IRQ_1019) + INT_VECTOR_PE1_IRQ_1019, /* EIC1019 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1020) + #if defined(INT_VECTOR_PE1_IRQ_1020) + INT_VECTOR_PE1_IRQ_1020, /* EIC1020 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1021) + #if defined(INT_VECTOR_PE1_IRQ_1021) + INT_VECTOR_PE1_IRQ_1021, /* EIC1021 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1022) + #if defined(INT_VECTOR_PE1_IRQ_1022) + INT_VECTOR_PE1_IRQ_1022, /* EIC1022 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif + + #if (BSP_INTC_INTBP_MAX_ENTRIES > 1023) + #if defined(INT_VECTOR_PE1_IRQ_1023) + INT_VECTOR_PE1_IRQ_1023, /* EIC1023 */ + #else + INT_PE1_DUMMY_IRQ, + #endif + #endif +}; +__PRAGMA_PLACE_IN_SECTION(BSP_PRAGMA_SECTION_DATA, BSP_PRAGMA_SECTION_DEFAULT) +#endif diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/boot.850 b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/boot.850 new file mode 100644 index 0000000000000000000000000000000000000000..4062ab57b22c2dc13c18c56b98b8c42779968d5c --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/boot.850 @@ -0,0 +1,481 @@ +/* {REA_DISCLAIMER_PLACEHOLDER} */ + +-- //! [RH850-Boot-Up] + +------------------------------------------------------------------------------------------------------------------------ +-- Includes , "Project Includes" +------------------------------------------------------------------------------------------------------------------------ + #include "memory_regions.h" + +------------------------------------------------------------------------------------------------------------------------ +-- Macro definitions (Define MACRO as 0 if it is not already) +------------------------------------------------------------------------------------------------------------------------ + /* Local RAM self */ + + /* Local RAM CPUn */ +#if !defined(LOCAL_RAM_CPU0_START) + LOCAL_RAM_CPU0_START .set 0 +#endif +#if !defined(LOCAL_RAM_CPU0_LENGTH) + LOCAL_RAM_CPU0_LENGTH .set 0 +#endif +#if !defined(LOCAL_RAM_CPU1_START) + LOCAL_RAM_CPU1_START .set 0 +#endif +#if !defined(LOCAL_RAM_CPU1_LENGTH) + LOCAL_RAM_CPU1_LENGTH .set 0 +#endif + + /* Cluster RAM */ +#if !defined(CLUSTER_RAM_0_START) + CLUSTER_RAM_0_START .set 0 +#endif +#if !defined(CLUSTER_RAM_0_LENGTH) + CLUSTER_RAM_0_LENGTH .set 0 +#endif + + /* Retention RAM */ + + /* PEn_VTOR */ +#if !defined(PE1_VTOR) + PE1_VTOR .set 0 +#endif + + MEV_ADDR .set MEV_ADDRESS_START + +------------------------------------------------------------------------------------------------------------------------- +--------------- Public function delaration +------------------------------------------------------------------------------------------------------------------------- + .global _Reset_Handler + .global _DummyIsr + + .extern __cstart + .extern _cstart_pen + .extern _R_BSP_SpinlockGet + .extern _R_BSP_SpinLockRelease + .extern _DummyIsr + +------------------------------------------------------------------------------------------------------------------------- +-- Exception vector table +------------------------------------------------------------------------------------------------------------------------- +.section "RESET", text +.align 512 + +_Reset_Handler: + jr __start -- RESET + + .align 16 + syncp + jr _DummyIsr -- SYSERR + + .align 16 + jr _DummyIsr -- (R.F.U.) + + .align 16 + jr _DummyIsr -- FETRAP + + .align 16 + jr _TRAP0_Handler -- TRAP0 + + .align 16 + jr _DummyIsr -- TRAP1 + + .align 16 + jr _DummyIsr -- RIE + + .align 16 + syncp + jr _DummyIsr -- FPP/FPI + + .align 16 + jr _DummyIsr -- UCPOP + + .align 16 + jr _DummyIsr -- MIP/MDP + + .align 16 + jr _DummyIsr -- PIE + + .align 16 + jr _DummyIsr -- (R.F.U.) + + .align 16 + jr _DummyIsr -- MAE + + .align 16 + jr _DummyIsr -- (R.F.U.) + + .align 16 + syncp + jr _DummyIsr -- FENMI + + .align 16 + syncp + jr _DummyIsr -- FEINT + + .align 16 + syncp + jr _DummyIsr -- INTn(priority0) + + /* Condition: Table reference method OFF and interrupt reduction OFF */ + .align 16 + syncp + jr _DummyIsr -- INTn(priority1) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority2) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority3) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority4) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority5) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority6) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority7) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority8) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority9) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority10) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority11) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority12) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority13) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority14) + + .align 16 + syncp + jr _DummyIsr -- INTn(priority15) + +.section .text +.align 2 + +_DummyIsr: + br _DummyIsr + +------------------------------------------------------------------------------------------------------------------------ +-- Startup +------------------------------------------------------------------------------------------------------------------------ +.section .text +.align 2 +__start: + mov r0, r10 -- initialize r10 register + stsr 0, r10, 2 -- get PEID.PEID + + #if (BSP_PE0_USED == 1) + cmp 0, r10 + bz __INITIALIZE_SETTING -- if PEID.PEID is 0 + #endif + + #if (BSP_PE1_USED == 0) + cmp 1, r10 + bz .L.Reset_Handler_PE1 + #endif + +#if (1) +__INITIALIZE_SETTING: + /* General purpose register */ + mov r0, r1 -- r1 Assembler reserved register + mov r0, r2 -- r2 Register for address and data variables + mov r0, r3 -- r3 Stack pointer (SP) + mov r0, r4 -- r4 Global pointer (GP) + mov r0, r5 -- r5 Text pointer (TP) + mov r0, r6 -- r6 to r29 Register for addresses and data variables + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + mov r0, r30 -- r30 Element pointer (EP) + mov r0, r31 -- r31 Link pointer (LP) + + /* Basic system register */ + ldsr r0, 0, 0 -- SR0,0 EIPC + ldsr r0, 2, 0 -- SR2,0 FEPC + ldsr r0, 16, 0 -- SR16,0 CTPC + ldsr r0, 28, 0 -- SR28,0 EIWR + ldsr r0, 29, 0 -- SR29,0 FEWR + ldsr r0, 3, 1 -- SR3,1 EBASE + ldsr r0, 4, 1 -- SR4,1 INTBP + ldsr r0, 6, 2 -- SR6,2 MEA + ldsr r0, 8, 2 -- SR8,2 MEI + ldsr r0, 18, 2 -- SR18,2 RBIP + + /* MPU function register */ + ldsr r0, 8, 5 -- SR8,5 MCA + ldsr r0, 9, 5 -- SR9,5 MCS + ldsr r0, 11, 5 -- SR11,5 MCR + + mov r0, r12 + /* Get total number of MPU's regions */ + stsr 2, r13, 5 + andi 31, r13, r13 + addi 1, r13, r13 +_loop: -- Initialize MPU Areas + ldsr r12, 16, 5 -- SR16,5 MPIDX + ldsr r0, 20, 5 -- SR20,5 MPLA + ldsr r0, 21, 5 -- SR21,5 MPUA + ldsr r0, 22, 5 -- SR22,5 MPAT + add 0x1, r12 + cmp r13, r12 + bne _loop + + ldsr r0, 24, 5 -- SR24,5 MPID0 + ldsr r0, 25, 5 -- SR25,5 MPID1 + ldsr r0, 26, 5 -- SR26,5 MPID2 + ldsr r0, 27, 5 -- SR27,5 MPID3 + ldsr r0, 28, 5 -- SR28,5 MPID4 + ldsr r0, 29, 5 -- SR29,5 MPID5 + ldsr r0, 30, 5 -- SR30,5 MPID6 + ldsr r0, 31, 5 -- SR31,5 MPID7 + ldsr r0, 12, 5 -- SR12,5 MCI + + /* Cache Operation Function Registers */ + ldsr r0, 16, 4 -- SR16,4 ICTAGL + ldsr r0, 17, 4 -- SR17,4 ICTAGH + ldsr r0, 18, 4 -- SR18,4 ICDATL + ldsr r0, 19, 4 -- SR19,4 ICDATH + ldsr r0, 28, 4 -- SR28,4 ICERR + + /* Virtualization support function system register */ + ldsr r0, 20, 1 -- SR20,1 HVSB + + /* Guest Context Register */ + ldsr r0, 0, 9 -- SR0,9 GMEIPC + ldsr r0, 2, 9 -- SR2,9 GMFEPC + ldsr r0, 19, 9 -- SR19,9 GMEBASE + ldsr r0, 20, 9 -- SR20,9 GMINTBP + ldsr r0, 28, 9 -- SR28,9 GMEIWR + ldsr r0, 29, 9 -- SR29,9 GMFEWR + ldsr r0, 6, 9 -- SR6,9 GMMEA + ldsr r0, 8, 9 -- SR8,9 GMMEI +#endif + +#if (BSP_PE0_USED == 1) + stsr 0, r10, 2 -- get PEID.PEID + cmp 0, r10 + bnz .L1.entry_PEx +_BOOTCTRL_SETTING_PE0: + ld.w 0xfffb2000[r0], r10 -- get BOOTCTRL + mov 1, r11 -- enabled PE0 by default, disable all other PEn + st.w r11, 0xfffb2000[r0] -- set BOOTCTRL + mov 0x0, r2 -- wait for 100us(0x9c40(40,000)count) + br .L.start_PE0.1 +.L.start_PE0.0: + add 0x1, r2 +.L.start_PE0.1: + andi 0xffff, r2, tp + ori 0x9c40, r0, r6 + cmp r6, tp + blt .L.start_PE0.0 + + /* Perform initialization of all configured memory regions on PE0 */ + jarl _hdwinit_PE0, lp -- initialize hardware + + /* Multual Exclusive Control PE0 and PEn */ + mov MEV_ADDR, r6 + st.w r0, 0[r6] + jarl _R_BSP_SpinlockGet, lp +#if (BSP_PE1_BOOT == 1) + ld.w 0xfffb2000[r0], r10 -- get BOOTCTRL + ori 2, r10, r11 -- set 1 in BOOTCTRL.BC1 for enabled PE1 + st.w r11, 0xfffb2000[r0] -- set BOOTCTRL + mov 0x0, r2 -- wait for 100us(0x9c40(40,000)count) + br .L.start_PE1.1 +.L.start_PE1.0: + add 0x1, r2 +.L.start_PE1.1: + andi 0xffff, r2, tp + ori 0x9c40, r0, r6 + cmp r6, tp + blt .L.start_PE1.0 +#endif +#endif + +#if 1 +.L1.entry_PEx: + +#if ((BSP_CONFIG_USE_SMP_MODE == 1) && (BSP_PE0_USED != 1)) + mov BSP_PE_USED, r11 + sch1r r11, r11 + stsr 0, r10, 2 -- get PEID.PEID + mov 1, r12 + shl r10, r12 + cmp r11, r12 + bnz .L1.Mul_Setting_Skip + + -- Multual Exclusive Control between PEn + mov #__MEV_CPU_SYNC_ADDR, r6 + st.w r0, 0[r6] + jarl _R_BSP_SpinlockGet, lp +.L1.Mul_Setting_Skip: +#endif + + /* Jump to entry point of each PE */ + stsr 0, r10, 2 -- get PEID or HTCFG0 + stsr 6, r11, 1 -- get PID + shr 24, r11 + cmp 6, r11 + bnl .L1 + shr 16, r10 -- get PEID (for G3) +.L1: +#if (BSP_PE0_USED == 1) + cmp 0, r10 + bz .L.entry_PE0 +#endif + +#if (BSP_PE1_USED == 1) + cmp 1, r10 + bz .L.entry_PE1 +#endif + +__exit: + br __exit + +#if (BSP_PE0_USED == 1) +.L.entry_PE0: + jr __cstart +#endif + +#if (BSP_PE1_USED == 1) +.L.entry_PE1: + jarl _hdwinit_PE1, lp -- initialize hardware + jr _cstart_pen + br __exit +#else +.L.Reset_Handler_PE1: + mov PE1_VTOR, r10 + jmp [r10] +#endif +#endif + +------------------------------------------------------------------------------------------------------------------------ +-- hdwinit +-- Specify RAM addresses suitable to your system if needed. +------------------------------------------------------------------------------------------------------------------------ + .align 2 +#if (BSP_PE0_USED == 1) +_hdwinit_PE0: + mov lp, r14 -- save return address + + /* Clear Local RAM Self */ + + /* Clear Local RAM CPU0 */ +#if (LOCAL_RAM_CPU0_LENGTH != 0) + mov LOCAL_RAM_CPU0_START, r6 + mov LOCAL_RAM_CPU0_LENGTH, r7 + add r6, r7 + jarl _initRam, lp +#endif + + /* Clear Cluster RAM 0 */ +#if (CLUSTER_RAM_0_LENGTH != 0) + mov CLUSTER_RAM_0_START, r6 + mov CLUSTER_RAM_0_LENGTH, r7 + add r6, r7 + jarl _initRam, lp +#endif + + /* Clear Cluster RAM 1 */ + /* Clear Cluster RAM 0 */ +#if (CLUSTER_RAM_1_LENGTH != 0) + mov CLUSTER_RAM_1_START, r6 + mov CLUSTER_RAM_1_LENGTH, r7 + add r6, r7 + jarl _initRam, lp +#endif + + /* Clear Cluster RAM 2 */ + + /* Clear Cluster RAM 3 */ + + /* Retention RAM */ + + mov r14, lp -- load return address back + jmp [lp] -- jump to return address +#endif + + .align 2 +#if (BSP_PE1_USED == 1) +_hdwinit_PE1: + mov lp, r14 -- save return address + + /* Clear Local RAM PE1 */ +#if (LOCAL_RAM_CPU1_LENGTH != 0) + mov LOCAL_RAM_CPU1_START, r6 + mov LOCAL_RAM_CPU1_LENGTH, r7 + add r6, r7 + jarl _initRam, lp +#endif + + mov r14, lp -- load return address back + jmp [lp] -- jump to return address +#endif + +------------------------------------------------------------------------------------------------------------------------- +-- initRam +------------------------------------------------------------------------------------------------------------------------ + .align 2 +_initRam: + mov 0x00000000, r8 + br .L.initRam.2 +.L.initRam.1: + st.w r8, 0[r6] + add 4, r6 +.L.initRam.2: + cmp r6, r7 + bh .L.initRam.1 + jmp [lp] + +----------------------------------------------- End of start up module ------------------------------------------------- + +-- //! [RH850-Boot-Up] diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart.850 b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart.850 new file mode 100644 index 0000000000000000000000000000000000000000..b9b721b977cf2417fd323af92d15ee8b37249452 --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart.850 @@ -0,0 +1,565 @@ +/* {REA_DISCLAIMER_PLACEHOLDER} */ + +-- //! [RH850-PE0-StartUp] + +------------------------------------------------------------------------------------------------------------------------ +-- Includes , "Project Includes" +------------------------------------------------------------------------------------------------------------------------ + #include "memory_regions.h" + +------------------------------------------------------------------------------------------------------------------------ +-- Macro definitions (Define MACRO as 0 if it is not already) +------------------------------------------------------------------------------------------------------------------------ + /* Local RAM self */ + + /* Cluster RAM */ +#if !defined(CLUSTER_RAM_0_LENGTH) + CLUSTER_RAM_0_LENGTH .set 0 +#endif + + BSP_WARM_START_RESET .set 0 + BSP_WARM_START_POST_CLOCK .set 1 + BSP_WARM_START_POST_C .set 2 + MEV_ADDR .set MEV_ADDRESS_START + +------------------------------------------------------------------------------------------------------------------------ +-------------- Public function delaration +------------------------------------------------------------------------------------------------------------------------ + .public _R_BSP_SpinLockRelease + .public _R_BSP_SpinlockGet + .public __Ram_Init + .public __clear_bss + .public __cstart + .extern nx_start + + .extern _DummyIsr + +------------------------------------------------------------------------------------------------------------------------ +-- Used for sync between other core +------------------------------------------------------------------------------------------------------------------------ +.section .text +.align 2 +_R_BSP_SpinLockRelease: + /* .mev_address section in cRAM_0 is used for Sync flags */ + mov r6, r20 + st.w r0, 0[r20] + jmp [lp] + +------------------------------------------------------------------------------------------------------------------------ +-- Sync PE0 Routine +------------------------------------------------------------------------------------------------------------------------ +.section .text +.align 2 +_R_BSP_SpinlockGet: + mov r6, r20 +.R_BSP_SpinlockGet.Lock: + ldl.w [r20], r21 + cmp r0, r21 + bnz .R_BSP_SpinlockGet.Lock_wait + mov 1, r21 + stc.w r21, [r20] + cmp r0, r21 + bnz .R_BSP_SpinlockGet.Lock_success +.R_BSP_SpinlockGet.Lock_wait: + snooze + br .R_BSP_SpinlockGet.Lock +.R_BSP_SpinlockGet.Lock_success: + jmp [lp] + +------------------------------------------------------------------------------------------------------------------------ +-- startup +------------------------------------------------------------------------------------------------------------------------ + +.section .text +.align 2 +__cstart: + +#if (BSP_PE0_USED == 1) + /* Initialization for RAM */ + jarl __Ram_Init, lp + + /* Copy initialized RAM data from ROM to RAM */ + /* Local RAM 0 */ + mov ___ghsbegin_pe0_data, r6 + mov ___ghsend_pe0_data, r7 + mov ___ghsbegin_ROM_pe0_data, r8 + jarl __copy_data, lp + + /* Copy initialized RAM data from ROM to RAM */ + mov ___ghsbegin_pe0_data, r6 + mov ___ghsend_pe0_data, r7 + mov ___ghsbegin_ROM_pe0_data, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_UNSPECIFIED data from ROM to RAM */ + mov ___ghsbegin_RAM_UNSPECIFIED, r6 + mov ___ghsend_RAM_UNSPECIFIED, r7 + mov ___ghsbegin_ROM_RAM_UNSPECIFIED, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_INIT_PTR data from ROM to RAM */ + mov ___ghsbegin_RAM_INIT_PTR, r6 + mov ___ghsend_RAM_INIT_PTR, r7 + mov ___ghsbegin_ROM_RAM_INIT_PTR, r8 + jarl __copy_data, lp + + /* Copy initialized RZCU_SEC_INIT_DATA_DDS data from ROM to RAM */ + mov ___ghsbegin_RZCU_SEC_INIT_DATA_DDS, r6 + mov ___ghsend_RZCU_SEC_INIT_DATA_DDS, r7 + mov ___ghsbegin_ROM_RZCU_SEC_INIT_DATA_DDS, r8 + jarl __copy_data, lp + + /* Copy initialized RZCU_SEC_DATA_DDS data from ROM to RAM */ + mov ___ghsbegin_RZCU_SEC_DATA_DDS, r6 + mov ___ghsend_RZCU_SEC_DATA_DDS, r7 + mov ___ghsbegin_ROM_RZCU_SEC_DATA_DDS, r8 + jarl __copy_data, lp + + /* Copy initialized ROM.data.private.systemapplication_core0.bsw data from ROM to RAM */ + mov ___ghsbegin_data_private_systemapplication_core0_bsw , r6 + mov ___ghsend_data_private_systemapplication_core0_bsw, r7 + mov ___ghsbegin_ROM_data_private_systemapplication_core0_bsw, r8 + jarl __copy_data, lp + + /* Copy initialized ETH_PORT_RAM_0 data from ROM to RAM */ + mov ___ghsbegin_ETH_PORT_RAM_0 , r6 + mov ___ghsend_ETH_PORT_RAM_0, r7 + mov ___ghsbegin_ROM_ETH_PORT_RAM_0, r8 + jarl __copy_data, lp + + /* Copy initialized ETH_PORT_RAM_1 data from ROM to RAM */ + mov ___ghsbegin_ETH_PORT_RAM_1 , r6 + mov ___ghsend_ETH_PORT_RAM_1, r7 + mov ___ghsbegin_ROM_ETH_PORT_RAM_1, r8 + jarl __copy_data, lp + + /* Copy initialized ETH_PORT_RAM_2 data from ROM to RAM */ + mov ___ghsbegin_ETH_PORT_RAM_2 , r6 + mov ___ghsend_ETH_PORT_RAM_2, r7 + mov ___ghsbegin_ROM_ETH_PORT_RAM_2, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_1BIT data from ROM to RAM */ + mov ___ghsbegin_RAM_1BIT , r6 + mov ___ghsend_RAM_1BIT, r7 + mov ___ghsbegin_ROM_RAM_1BIT, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_8BIT data from ROM to RAM */ + mov ___ghsbegin_RAM_8BIT , r6 + mov ___ghsend_RAM_8BIT, r7 + mov ___ghsbegin_ROM_RAM_8BIT, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_16BIT data from ROM to RAM */ + mov ___ghsbegin_RAM_16BIT , r6 + mov ___ghsend_RAM_16BIT, r7 + mov ___ghsbegin_ROM_RAM_16BIT, r8 + jarl __copy_data, lp + + /* Copy initialized RAM_32BIT data from ROM to RAM */ + mov ___ghsbegin_RAM_32BIT , r6 + mov ___ghsend_RAM_32BIT, r7 + mov ___ghsbegin_ROM_RAM_32BIT, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_1BIT data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_1BIT , r6 + mov ___ghsend_FAST_RAM_1BIT, r7 + mov ___ghsbegin_ROM_FAST_RAM_1BIT, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_8BIT data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_8BIT , r6 + mov ___ghsend_FAST_RAM_8BIT, r7 + mov ___ghsbegin_ROM_FAST_RAM_8BIT, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_16BIT data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_16BIT , r6 + mov ___ghsend_FAST_RAM_16BIT, r7 + mov ___ghsbegin_ROM_FAST_RAM_16BIT, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_32BIT data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_32BIT , r6 + mov ___ghsend_FAST_RAM_32BIT, r7 + mov ___ghsbegin_ROM_FAST_RAM_32BIT, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_UNSPECIFIED data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_UNSPECIFIED , r6 + mov ___ghsend_FAST_RAM_UNSPECIFIED, r7 + mov ___ghsbegin_ROM_FAST_RAM_UNSPECIFIED, r8 + jarl __copy_data, lp + + /* Copy initialized FAST_RAM_INIT_PTR data from ROM to RAM */ + mov ___ghsbegin_FAST_RAM_INIT_PTR , r6 + mov ___ghsend_FAST_RAM_INIT_PTR, r7 + mov ___ghsbegin_ROM_FAST_RAM_INIT_PTR, r8 + jarl __copy_data, lp + + /* Copy initialized zdata data from ROM to RAM */ + mov ___ghsbegin_zdata , r6 + mov ___ghsend_zdata, r7 + mov ___ghsbegin_ROM_zdata, r8 + jarl __copy_data, lp + + /* Copy initialized zdata data from ROM to RAM */ + mov ___ghsbegin_tdata , r6 + mov ___ghsend_tdata, r7 + mov ___ghsbegin_ROM_tdata, r8 + jarl __copy_data, lp + + /* Copy initialized zdata data from ROM to RAM */ + mov ___ghsbegin_sldata , r6 + mov ___ghsend_sldata, r7 + mov ___ghsbegin_ROM_sldata, r8 + jarl __copy_data, lp + + /* Copy initialized zdata data from ROM to RAM */ + mov ___ghsbeginClearFarData_Align4_DDSMemory1 , r6 + mov ___ghsendClearFarData_Align4_DDSMemory1, r7 + mov ___ghsbegin_ROM_ClearFarData_Align4_DDSMemory1, r8 + jarl __copy_data, lp + + /* Copy initialized ClearFarData_Align4_DDSMemory2 data from ROM to RAM */ + mov ___ghsbeginClearFarData_Align4_DDSMemory2 , r6 + mov ___ghsendClearFarData_Align4_DDSMemory2, r7 + mov ___ghsbegin_ROM_ClearFarData_Align4_DDSMemory2, r8 + jarl __copy_data, lp + + + /* Zero out BSS for PE0 */ + mov ___ghsbegin_pe0_bss, r6 + mov ___ghsend_pe0_bss, r7 + jarl __clear_bss, lp + + + mov ___ghsend_stack_pe0, sp -- set sp register + /* Initialization of the gp, ep, tp pointer */ + mov __gp, gp -- set gp register + mov __ep, ep -- set ep register + mov __tp, tp -- set tp register + + /* Initialization of the interrupt base pointer */ + mov _IntVectors_PE0, r6 + ldsr r6, 4, 1 -- set INTBP + + /* Compute RINT and DV bits */ + + /* Extend Priority Interrupt */ + + /* then set 1 to PSW.EBV -> RBASE!=EBASE + then set 1 to PSW.CU0 and CU1 */ + stsr 5, r10, 0 -- PSW + mov 0x8000, r11 -- CUx_EBV + or r11, r10 + ldsr r10, 5, 0 -- PSW + synci + + /* Perform MCU initialization */ + jarl _SystemInit, lp + + /* Release lock for other cores */ + mov MEV_ADDR, r6 + jarl _R_BSP_SpinLockRelease, lp + + /* set various flags to PSW via FEPSW */ + stsr 5, r10, 0 -- r10 <- PSW + ldsr r10, 3, 0 -- FEPSW <- r10 + mov _exit, lp -- lp <- #_exit + mov _nx_start, r10 + ldsr r10, 2, 0 -- FEPC <- #_nx_start, Then start NuttX + + /* apply PSW and PC to start user mode */ + feret + +_exit: + br _exit -- end of program +#endif + +------------------------------------------------------------------------------------------------------------------------ +-- FPU initialization +------------------------------------------------------------------------------------------------------------------------ + .public _R_BSP_FPU_Init + .align 2 +_R_BSP_FPU_Init: + mov lp, r12 -- save return address + mov lp, r12 -- save return address + /* Enable FPU */ + stsr 6, r10, 1 -- r10 <- PID + shl 21, r10 + shr 30, r10 + bz .L1 -- detecting FPU + stsr 5, r10, 0 -- r10 <- PSW + movhi 0x0001, r0, r11 + or r11, r10 + ldsr r10, 5, 0 -- enable FPU + synci + + movhi 0x0002, r0, r11 + ldsr r11, 6, 0 -- initialize FPSR + ldsr r0, 7, 0 -- initialize FPEPC +.L1: + mov r12, lp + jmp [lp] + +------------------------------------------------------------------------------------------------------------------------ +-- FXU initialization +------------------------------------------------------------------------------------------------------------------------ + .public _R_BSP_FXU_Init + .align 2 +_R_BSP_FXU_Init: + mov lp, r12 -- save return address + stsr 6, r10, 1 -- r10 <- PID + shl 20, r10 + shr 31, r10 + bz .L2 -- detecting FXU + stsr 5, r10, 0 -- r10 <- PSW + movhi 0x0002, r0, r11 + or r11, r10 + ldsr r10, 5, 0 -- enable FXU + synci + + movhi 0x0002, r0, r11 + ldsr r11, 6, 10 -- initialize FXSR + ldsr r0, 8, 10 -- initialize FXST + ldsr r0, 10, 10 -- initialize FXCFG +.L2: + mov r12, lp + mov r12, lp + jmp [lp] + +-- //! [RH850-Interrupt-Vector-Relocation] +------------------------------------------------------------------------------------------------------------------------ +-- Start Section for exception table (PE0) +------------------------------------------------------------------------------------------------------------------------ +#if (BSP_PE0_USED == 1) +.section ex_entry_PE0 +.global _ex_entry_PE0 +.align 4 + +_ex_entry_PE0: +-----RESET + .offset 0x0000 + jr _DummyIsr + +-----SYSERR + .offset 0x0010 + jr _DummyIsr + +-----FETRAP + .offset 0x0030 + jr _DummyIsr + +-----TRAP0 + .offset 0x0040 + jr _TRAP0_Handler + +-----TRAP1 + .offset 0x0050 + jr _DummyIsr + +-----RIEX + .offset 0x0060 + jr _DummyIsr + +-----UCPOP + .offset 0x0080 + jr _DummyIsr + +-----MIP_MDP + .offset 0x0090 + jr _DummyIsr + +-----PIE + .offset 0x00a0 + jr _DummyIsr + +-----MAE_MAEX + .offset 0x00c0 + jr _DummyIsr + +-----FENMI + .offset 0x00e0 + jr _DummyIsr + +-----FEINT + .offset 0x00f0 + jr _DummyIsr + +-----EIINTn priority_0 + .offset 0x0100 + jr _DummyIsr + + /* Condition: Table reference method OFF and interrupt reduction OFF */ +-----EIINTn priority_1 + .offset 0x0110 + jr _DummyIsr + +-----EIINTn priority_2 + .offset 0x0120 + jr _DummyIsr + +-----EIINTn priority_3 + .offset 0x0130 + jr _DummyIsr + +-----EIINTn priority_4 + .offset 0x0140 + jr _DummyIsr + +-----EIINTn priority_5 + .offset 0x0150 + jr _DummyIsr + +-----EIINTn priority_6 + .offset 0x0160 + jr _DummyIsr + +-----EIINTn priority_7 + .offset 0x0170 + jr _DummyIsr + +-----EIINTn priority_8 + .offset 0x0180 + jr _DummyIsr + +-----EIINTn priority_9 + .offset 0x0190 + jr _DummyIsr + +-----EIINTn priority_10 + .offset 0x01a0 + jr _DummyIsr + +-----EIINTn priority_11 + .offset 0x01b0 + jr _DummyIsr + +-----EIINTn priority_12 + .offset 0x01c0 + jr _DummyIsr + +-----EIINTn priority_13 + .offset 0x01d0 + jr _DummyIsr + +-----EIINTn priority_14 + .offset 0x01e0 + jr _DummyIsr + +-----EIINTn priority_15 + .offset 0x01f0 + jr _DummyIsr + +#endif +-- //! [RH850-Interrupt-Vector-Relocation] +---------------------------------------------- End of exception table ------------------------------------------------# + +.section .text +.align 2 +----------------------------------------------------------------------------------------------------------------------- +-- RAM initialization +----------------------------------------------------------------------------------------------------------------------- + +__Ram_Init: + mov lp, r14 -- save return address + + /* Default section of GHS */ + mov ___ghsbegin_data, r6 + mov ___ghsend_data, r7 + mov ___ghsbegin_ROM_data, r8 + jarl __copy_data, lp + + mov ___ghsbegin_sdata, r6 + mov ___ghsend_sdata, r7 + mov ___ghsbegin_ROM_sdata, r8 + jarl __copy_data, lp + + mov ___ghsbegin_zdata, r6 + mov ___ghsend_zdata, r7 + mov ___ghsbegin_ROM_zdata, r8 + jarl __copy_data, lp + + mov ___ghsbegin_tdata, r6 + mov ___ghsend_tdata, r7 + mov ___ghsbegin_ROM_tdata, r8 + jarl __copy_data, lp + + mov ___ghsbegin_sldata, r6 + mov ___ghsend_sldata, r7 + mov ___ghsbegin_ROM_sldata, r8 + jarl __copy_data, lp + + /* Zero out BSS */ + mov ___ghsbegin_bss, r6 + mov ___ghsend_bss, r7 + jarl __clear_bss, lp + + mov ___ghsbegin_zbss, r6 + mov ___ghsend_zbss, r7 + jarl __clear_bss, lp + + mov ___ghsbegin_slbss, r6 + mov ___ghsend_slbss, r7 + jarl __clear_bss, lp + + mov ___ghsbegin_sbss, r6 + mov ___ghsend_sbss, r7 + jarl __clear_bss, lp + + /* Copy initialized RAM data from ROM to RAM */ + +#if (CLUSTER_RAM_0_LENGTH != 0) + /* Cluster RAM 0 */ + mov ___ghsbegin_cluster_ram0_data, r6 + mov ___ghsend_cluster_ram0_data, r7 + mov ___ghsbegin_ROM_cluster_ram0_data, r8 + jarl __copy_data, lp +#endif + + /* Zero out BSS */ + +#if (CLUSTER_RAM_0_LENGTH != 0) + /* Cluster RAM 0 */ + mov ___ghsbegin_cluster_ram0_bss, r6 + mov ___ghsend_cluster_ram0_bss, r7 + jarl __clear_bss, lp +#endif + + mov r14, lp + jmp [lp] +----------------------------------------------------------------------------------------------------------------------- +-- Copy initialized RAM data from ROM to RAM +----------------------------------------------------------------------------------------------------------------------- +__copy_data: + br .L.copy_data_section.2 +.L.copy_data_section.1: + ld.bu 0[r8], r10 + st.b r10, 0[r6] + add 1, r6 + add 1, r8 +.L.copy_data_section.2: + cmp r6, r7 + bh .L.copy_data_section.1 + jmp [lp] + +----------------------------------------------------------------------------------------------------------------------- +-- Zero out BSS +----------------------------------------------------------------------------------------------------------------------- +__clear_bss: + mov r0, r8 + br .L.clear_bss_section.2 +.L.clear_bss_section.1: + st.b r8, 0[r6] + add 1, r6 +.L.clear_bss_section.2: + cmp r6, r7 + bh .L.clear_bss_section.1 + jmp [lp] + +--------------------------------------------- end of start up module --------------------------------------------------- + +-- //! [RH850-PE0-StartUp] diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart_pen.850 b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart_pen.850 new file mode 100644 index 0000000000000000000000000000000000000000..d3ee5e90b202fd77c5559caa97901c3dc400c0dd --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/cstart_pen.850 @@ -0,0 +1,285 @@ +/* {REA_DISCLAIMER_PLACEHOLDER} */ + +-- //! [RH850-PEn-StartUp] + +------------------------------------------------------------------------------------------------------------------------ +-- Includes , "Project Includes" +------------------------------------------------------------------------------------------------------------------------ + #include "memory_regions.h" + +------------------------------------------------------------------------------------------------------------------------ +-- Macro definitions (Define MACRO as 0 if it is not already) +------------------------------------------------------------------------------------------------------------------------ + BSP_WARM_START_RESET .set 0 + BSP_WARM_START_POST_CLOCK .set 1 + BSP_WARM_START_POST_C .set 2 + + MEV_ADDR .set MEV_ADDRESS_START + +------------------------------------------------------------------------------------------------------------------------ +-------------- Public function delaration +------------------------------------------------------------------------------------------------------------------------ + .global _cstart_pen + + .extern _R_BSP_SpinlockGet + .extern _R_BSP_SpinLockRelease + .extern _exit + .extern __copy_data + .extern __clear_bss + .extern __Ram_Init + .extern _DummyIsr + +------------------------------------------------------------------------------------------------------------------------ +-- startup +------------------------------------------------------------------------------------------------------------------------ +.section .text +.align 2 + +_cstart_pen: + mov r0, r10 -- initialize r10 to default value + /* Waiting CPU0 startup */ + mov MEV_ADDR, r6 + jarl _R_BSP_SpinlockGet, lp + mov MEV_ADDR, r6 + jarl _R_BSP_SpinLockRelease, lp + + /* This operation was performed on PE0 while running in SMP mode */ +#if (BSP_CONFIG_USE_SMP_MODE == 0) + jarl __Ram_Init, lp +#elif (BSP_PE0_USED != 1) + mov BSP_PE_USED, r11 + sch1r r11, r11 + stsr 0, r10, 2 -- get PEID.PEID + mov 1, r12 + shl r10, r12 + cmp r11, r12 + bnz .L1.Ram_Init_Skip + jarl __Ram_Init, lp + /* Release lock for other cores */ + mov #__MEV_CPU_SYNC_ADDR, r6 + jarl _R_BSP_SpinLockRelease, lp + +.L1.Ram_Init_Skip: + /* Waiting CPUn Initial the common RAM */ + mov #__MEV_CPU_SYNC_ADDR, r6 + jarl _R_BSP_SpinlockGet, lp + mov #__MEV_CPU_SYNC_ADDR, r6 + jarl _R_BSP_SpinLockRelease, lp +#endif + + /* Initialization of the gp, ep, tp pointer */ + mov __gp, gp -- set gp register + mov __ep, ep -- set ep register + mov __tp, tp -- set tp register + + stsr 0, r10, 2 -- get PEID.PEID +#if (BSP_PE1_USED == 1) + cmp 1, r10 + bz _PE1_Initialization -- if PEID.PEID is 1 +#endif + +------------------------------------------------------------------------------------------------------------------------ +-- PEn Initialization +------------------------------------------------------------------------------------------------------------------------ +#if (BSP_PE1_USED == 1) +_PE1_Initialization: + /* Copy initialized RAM data from ROM to RAM */ + /* Local RAM 1 */ + mov ___ghsbegin_pe1_data, r6 + mov ___ghsend_pe1_data, r7 + mov ___ghsbegin_ROM_pe1_data, r8 + jarl __copy_data, lp + + /* Initialization of the stack pointer */ + /* Zero out BSS for PE1 */ + mov ___ghsbegin_pe1_bss, r6 + mov ___ghsend_pe1_bss, r7 + jarl __clear_bss, lp + + mov ___ghsend_stack_pe1, sp -- set sp register + + /* Initialization of the interrupt base pointer */ + mov _IntVectors_PE1, r10 + ldsr r10, 4, 1 -- INTBP + /* First set EBASE register address (set to "ex_entry_PE1" function) */ + mov _IntVectors_PE1, r10 + br _skip +#endif + +_skip: + /* Compute RINT and DV bits */ + + /* Extend Priority Interrupt */ + + /* Then set 1 to PSW.EBV -> RBASE!=EBASE */ + stsr 5, r10, 0 -- PSW + /* Then set 1 to PSW.CU0 and CU1 */ + mov 0x8000, r11 -- CUx_EBV + or r11, r10 + ldsr r10, 5, 0 -- PSW + synci + + /* Perform MCU initialization */ + jarl _SystemInit, lp + syncp + + /* Enable interrupt */ + -- ei + + /* set various flags to PSW via FEPSW */ + stsr 5, r10, 0 -- r10 <- PSW + ldsr r10, 3, 0 -- FEPSW <- r10 + mov _exit, lp -- lp <- #_exit + /* Jump to main() */ + +------------------------------------------------------------------------------------------------------------------------ +-- Jump to entry point of each PE main function +------------------------------------------------------------------------------------------------------------------------ + + stsr 0, r10, 2 -- get PEID.PEID +#if (BSP_PE1_USED == 1) + cmp 1, r10 + bz _INIT_PE1 -- if PEID.PEID is 1 +#endif + +_exit: + br _exit -- end of program + +_loop: + br _loop + +#if (BSP_PE1_USED == 1) +_INIT_PE1: + mov _main_PE1, r10 + ldsr r10, 2, 0 -- FEPC <- #_main + /* Apply PSW and PC to start user mode */ + feret + br _exit +#endif + +------------------------------------------------------------------------------------------------------------------------ +-- Start Section for exception table (PE1) +------------------------------------------------------------------------------------------------------------------------ +#if (BSP_PE1_USED == 1) +.section ex_entry_PE1 +.global _ex_entry_PE1 + +_ex_entry_PE1: +------RESET + .offset 0x0000 + jr _DummyIsr + +------SYSERR + .offset 0x0010 + jr _DummyIsr + +------FETRAP + .offset 0x0030 + jr _DummyIsr + +------TRAP0 + .offset 0x0040 + jr _DummyIsr + +------TRAP1 + .offset 0x0050 + jr _DummyIsr + +------RIEX + .offset 0x0060 + jr _DummyIsr + +------UCPOP + .offset 0x0080 + jr _DummyIsr + +------MIP_MDP + .offset 0x0090 + jr _DummyIsr + +------PIE + .offset 0x00a0 + jr _DummyIsr + +------MAE_MAEX + .offset 0x00c0 + jr _DummyIsr + +------FENMI + .offset 0x00e0 + jr _DummyIsr + +------FEINT + .offset 0x00f0 + jr _DummyIsr + +------EIINTn priority_0 + .offset 0x0100 + jr _DummyIsr + + /* Condition: Table reference method OFF and interrupt reduction OFF */ +------EIINTn priority_1 + .offset 0x0110 + jr _DummyIsr + +------EIINTn priority_2 + .offset 0x0120 + jr _DummyIsr + +------EIINTn priority_3 + .offset 0x0130 + jr _DummyIsr + +------EIINTn priority_4 + .offset 0x0140 + jr _DummyIsr + +------EIINTn priority_5 + .offset 0x0150 + jr _DummyIsr + +------EIINTn priority_6 + .offset 0x0160 + jr _DummyIsr + +------EIINTn priority_7 + .offset 0x0170 + jr _DummyIsr + +------EIINTn priority_8 + .offset 0x0180 + jr _DummyIsr + +------EIINTn priority_9 + .offset 0x0190 + jr _DummyIsr + +------EIINTn priority_10 + .offset 0x01a0 + jr _DummyIsr + +------EIINTn priority_11 + .offset 0x01b0 + jr _DummyIsr + +------EIINTn priority_12 + .offset 0x01c0 + jr _DummyIsr + +------EIINTn priority_13 + .offset 0x01d0 + jr _DummyIsr + +------EIINTn priority_14 + .offset 0x01e0 + jr _DummyIsr + +------EIINTn priority_15 + .offset 0x01f0 + jr _DummyIsr +#endif +----------------------------------------- End of exception table ------------------------------------------------------- + +----------------------------------------- End of start up module ------------------------------------------------------- + +-- //! [RH850-PEn-StartUp] diff --git a/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/system.c b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/system.c new file mode 100644 index 0000000000000000000000000000000000000000..9e131ffb2903698ea5c24392eff2f160edd4f93e --- /dev/null +++ b/arch/rh850/src/g4x/Core/Template/RH850/Source/ghs/system.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2026 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +#if CONFIG_BSP_FSP_SUPPORT +#include "bsp_api.h" +#else +#include "Device_common.h" +#endif +#include + + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* Heap boundaries provided by the linker script */ +extern uint32_t __ghsbegin_heap; +extern uint32_t __ghsend_heap; +extern uint32_t __ghsbegin_kheap; +extern uint32_t __ghsend_kheap; +extern uint32_t * uxInterruptStack; + +/* Variables that store heap start/end addresses as uint32_t values */ +uint32_t __heap_start = (uint32_t) &__ghsbegin_heap; +uint32_t __heap_end = (uint32_t) &__ghsend_heap; +/* Variables that store heap start/end addresses as uint32_t values */ +uint32_t __kheap_start = (uint32_t) &__ghsbegin_kheap; +uint32_t __kheap_end = (uint32_t) &__ghsend_kheap; + + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/* Address Access Mutual Exclusion Mechanism */ +#if (BSP_CFG_MEV_SIZE_BYTES > 0) + #pragma ghs section sbss=".mev_address" + +/* Used in baremetal pack */ +uint32_t g_mev_cpusync_address; + +/* Used in baremetal pack */ +uint32_t g_mev_address[BSP_CFG_MEV_SIZE_BYTES >> 2]; +#else + #pragma ghs section sbss=".mev_address" + +/* Used in baremetal pack */ +uint32_t g_mev_cpusync_address; +#endif + +#define BSP_INTERRUPT_STACK_SIZE 0x9000 +#define BSP_MAIN_STACK_SIZE 0x5000 +#define BSP_HEAP_SIZE 0x10000 +#define BSP_KHEAP_SIZE 0x10000 + +/* Main stack definition section */ +#pragma ghs section bss=".stack_pe0" +uint32_t g_interrupt_stack_pe0[BSP_INTERRUPT_STACK_SIZE >> 2]; +uint32_t g_main_stack_pe0[BSP_MAIN_STACK_SIZE >> 2]; + +#if (BSP_PE1_USED) + #pragma ghs section sbss=".stack_pe1" +uint32_t g_main_stack_pe1[BSP_CFG_STACK_MAIN_BYTES >> 2]; +#endif + +/* Heap definition section (only if heap size is greater than 0) */ + +#pragma ghs section bss=".heap" +uint32_t _REL_sysheap[BSP_HEAP_SIZE >> 2]; +uint32_t _REL_sizeof_sysheap = BSP_HEAP_SIZE >> 2; +#pragma ghs section bss=".kheap" +uint32_t _REL_k_sysheap[BSP_KHEAP_SIZE >> 2]; +uint32_t _REL_sizeof_syskheap = BSP_KHEAP_SIZE >> 2; + +#pragma ghs section sbss = default +uint32_t * uxInterruptStack = (uint32_t *)&g_interrupt_stack_pe0[BSP_INTERRUPT_STACK_SIZE>>2]; + +uint32_t checkcrash_cstart = 0; +#if (CONFIG_BSP_FSP_SUPPORT == 1) +extern void R_BSP_WarmStart(void); +#endif +extern void R_BSP_FPU_Init(); +void SystemInit(void); + + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ + + void SystemInit (void) +{ + /* Get the current core ID */ + + /* Call Post C runtime initialization hook for RESET stage */ + + /* Check if the System Init is invoked in CPU0 */ + { + /* Configure system clocks and Guard */ + +#if (CONFIG_BSP_FSP_SUPPORT == 1) + R_BSP_WarmStart(); +#endif + /* Call Post C runtime initialization hook for POST CLOCK stage */ + } + + /* Call Post C runtime initialization hook. */ + + + /* Configure MPU */ + + /* Instruction cache is enabled by default; disable it by changing Instruction Cache Enable option in BSP tab */ + + /* FPU Init */ + R_BSP_FPU_Init(); +} diff --git a/arch/rh850/src/g4x/Kconfig b/arch/rh850/src/g4x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..3794f616a850965e794a7cba726ddd6d4e3d7f72 --- /dev/null +++ b/arch/rh850/src/g4x/Kconfig @@ -0,0 +1,21 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_U2B24E +comment "U2Bx-E Configuration Options" + +menu "U2Bx-E Peripheral Selections" + +config U2BX_UART + bool "UART" + default n + select UART_SERIALDRIVER + +config BSP_FSP_SUPPORT + bool "Enable FSP support for RH850" + default n + +endmenu # U2Bx-E Peripheral Selections +endif \ No newline at end of file diff --git a/arch/rh850/src/g4x/Make.defs b/arch/rh850/src/g4x/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..1a896e552dd591418bbe60902486f4326731a171 --- /dev/null +++ b/arch/rh850/src/g4x/Make.defs @@ -0,0 +1,19 @@ +############################################################################ +# arch/rh850/src/u2bx/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ diff --git a/arch/rh850/src/g4x/Toolchain.defs b/arch/rh850/src/g4x/Toolchain.defs new file mode 100644 index 0000000000000000000000000000000000000000..ae47640c39d4100e9a3aa24555f8b1635eb278c8 --- /dev/null +++ b/arch/rh850/src/g4x/Toolchain.defs @@ -0,0 +1,21 @@ +############################################################################ +# arch/arm/src/arm/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/arch/rh850/src/common/Toolchain.defs diff --git a/boards/Kconfig b/boards/Kconfig index 9299b8c3045b24c13939fbdeaf8a1e22d8df0f95..be1195d08019df8e7f2b7deee44dbc6434d089cc 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -139,6 +139,9 @@ config ARCH_BOARD_DK_TM4C129X Tiva DK-TM4C129x Connected Development Kit featuring the TM4C129XNCZAD MCU. +config ARCH_BOARD_U2BX + bool "u2bx board" + config ARCH_BOARD_EA3131 bool "Embedded Artists EA3131 Development board" depends on ARCH_CHIP_LPC3131 diff --git a/cmake/nuttx_add_library.cmake b/cmake/nuttx_add_library.cmake index 76b861a053ea43bd05decfd1717a7ab7e5a03153..32c3a6f6bd65232ec2622a5370064e7eb533df74 100644 --- a/cmake/nuttx_add_library.cmake +++ b/cmake/nuttx_add_library.cmake @@ -159,6 +159,7 @@ function(nuttx_add_kernel_library target) PRIVATE $>) endif() + if(NOT "${target}" STREQUAL "${kernel_target}") # The k${target} lib will have the same sources added to that ${target} lib. diff --git a/drivers/syslog/syslog_write.c b/drivers/syslog/syslog_write.c index d1ddf962458e44b25a00e6bee607315c403f11d1..9a8799688104decb34ee8e3c6f3ff23b6a19efcb 100644 --- a/drivers/syslog/syslog_write.c +++ b/drivers/syslog/syslog_write.c @@ -142,7 +142,12 @@ ssize_t syslog_write_foreach(FAR const char *buffer, ret = write(channel, buffer + nwritten, head - nwritten); if (ret >= 0) { + #ifndef CONFIG_RH850_TOOLCHAIN_GHS ret = write(channel, "\r\n", 2); + #else + char crlf[2] = {'\r', '\n'}; + ret = write(channel, crlf, 2); + #endif } if (ret < 0) diff --git a/include/err.h b/include/err.h index 9adf35048f66e775f322e744788a0bd6fee693ed..60dffeca766ed17ed92a347845ec099b87ad5cb1 100644 --- a/include/err.h +++ b/include/err.h @@ -89,6 +89,13 @@ void verrx(int status, FAR const char *fmt, va_list ap) printf_like(2, 0); * if result is unused. */ + +#ifndef unlikely +#define __builtin_expect(expr, value) (((expr) ? 1 : 0) == value) +#define unlikely(x) (__builtin_expect(!!(x), 0)) +#endif + + #define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-__ELASTERROR) /** diff --git a/include/nuttx/compiler.h b/include/nuttx/compiler.h index 5a405ac50e5b6636d47bdfe137c17cc12ac24d2e..90ec9a8f8fa824977e7c0ce26c6bed2b1a16a97f 100644 --- a/include/nuttx/compiler.h +++ b/include/nuttx/compiler.h @@ -1227,6 +1227,16 @@ #endif +#if defined(__ghs__) +// #ifndef likely +// # define likely(x) (x) +// #endif + +// #ifndef unlikely +// # define unlikely(x) (x) +// #endif +#endif + #ifndef CONFIG_HAVE_LONG_LONG # undef CONFIG_FS_LARGEFILE #endif diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 70f1cf0311acdfd835985739f57cc811a0fea12a..724ad7cf11705146890a6e1bed0159a53e6a28f7 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -55,10 +55,16 @@ #else /* CONFIG_PRIORITY_INHERITANCE */ /* semcount, flags, waitlist */ +#if defined(CONFIG_RT_FRAMEWORK) && (CONFIG_RT_FRAMEWORK == 1) +# define NXSEM_INITIALIZER(c, f) \ + {(c), (f), SEM_WAITLIST_INITIALIZER, SEM_VALUE_MAX} +#else # define NXSEM_INITIALIZER(c, f) \ {(c), (f), SEM_WAITLIST_INITIALIZER} +#endif #endif /* CONFIG_PRIORITY_INHERITANCE */ + /**************************************************************************** * Public Type Definitions ****************************************************************************/ diff --git a/include/nuttx/userspace.h b/include/nuttx/userspace.h index 59285ac9605dc4f4b0fa390007cd740ad55c7d9c..450497d915995ff4fb0bdecb88aa9a3a52b229f0 100644 --- a/include/nuttx/userspace.h +++ b/include/nuttx/userspace.h @@ -83,7 +83,7 @@ struct mm_heap_s; /* Forward reference */ * the blob. The form of that header is provided by struct userspace_s. An * instance of this is expected to reside at CONFIG_NUTTX_USERSPACE. */ - +#warning ----------userspace_s--------------- struct userspace_s { /* General memory map */ diff --git a/include/termios.h b/include/termios.h index d8a86073c549f01279d47bc1ccf25b9f56ed85e1..e6dd89172c695aa98bf309836ceaab1d50ee6851 100644 --- a/include/termios.h +++ b/include/termios.h @@ -64,10 +64,10 @@ # define NL0 (0 << 8) /* Newline character type 0 */ # define NL1 (1 << 8) /* Newline character type 1 */ #define CRDLY (3 << 9) /* Bits 9-10: Select carriage-return delays: */ -# define CR0 (0 << 9) /* Carriage-return delay type 0 */ -# define CR1 (1 << 9) /* Carriage-return delay type 1 */ -# define CR2 (2 << 9) /* Carriage-return delay type 2 */ -# define CR3 (3 << 9) /* Carriage-return delay type 3 */ +# define TER_CR0 (0 << 9) /* Carriage-return delay type 0 */ +# define TER_CR1 (1 << 9) /* Carriage-return delay type 1 */ +# define TER_CR2 (2 << 9) /* Carriage-return delay type 2 */ +# define TER_CR3 (3 << 9) /* Carriage-return delay type 3 */ #define TABDLY (3 << 11) /* Bits 11-12: Select horizontal-tab delays: */ # define TAB0 (0 << 11) /* Horizontal-tab delay type 0 */ # define TAB1 (1 << 11) /* Horizontal-tab delay type 1 */ diff --git a/libs/libc/machine/Kconfig b/libs/libc/machine/Kconfig index 5b0caacccdabf7352b0e15451588c2d16e142be8..537eb7c770055b7a7134f423033ba5d39e2ef9b2 100644 --- a/libs/libc/machine/Kconfig +++ b/libs/libc/machine/Kconfig @@ -802,6 +802,10 @@ if ARCH_RENESAS source "libs/libc/machine/renesas/Kconfig" endif +if ARCH_RH850 +source "libs/libc/machine/rh850/Kconfig" +endif + if ARCH_SPARC source "libs/libc/machine/sparc/Kconfig" endif diff --git a/libs/libc/machine/rh850/CMakeLists.txt b/libs/libc/machine/rh850/CMakeLists.txt index e1f670a869e460b1f2c0b78013b2c245052acb80..0981d6aeccab7af78415360330d516a48ef34e0b 100644 --- a/libs/libc/machine/rh850/CMakeLists.txt +++ b/libs/libc/machine/rh850/CMakeLists.txt @@ -19,3 +19,11 @@ # the License. # # ############################################################################## + +set(SRCS) + +if(CONFIG_ARCH_SETJMP_H) + list(APPEND SRCS ghs/arch_setjmp.850) +endif() + +target_sources(c PRIVATE ${SRCS}) diff --git a/libs/libc/machine/rh850/Kconfig b/libs/libc/machine/rh850/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..fb9b054398b626a68663336d2bc16e0f0d44a59b --- /dev/null +++ b/libs/libc/machine/rh850/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +#if ARCH_RENESAS_RH850 +#source "libs/libc/machine/rh850/Kconfig" +#endif + diff --git a/libs/libc/machine/rh850/Make.defs b/libs/libc/machine/rh850/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..16d211112ed384da15cb5e7befbed204b9679cd5 --- /dev/null +++ b/libs/libc/machine/rh850/Make.defs @@ -0,0 +1,32 @@ +############################################################################ +# libs/libc/machine/renesas/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_SETJMP_H),y) +ASRCS += arch_setjmp.850 +endif + +message("arch_setjmp.850") + +set_source_files_properties(arch_setjmp.850 PROPERTIES LANGUAGE ASM) + +DEPPATH += --dep-path machine/rh850/ghs +VPATH += :machine/rh850/ghs \ No newline at end of file diff --git a/libs/libc/machine/rh850/ghs/arch_setjmp.850 b/libs/libc/machine/rh850/ghs/arch_setjmp.850 new file mode 100644 index 0000000000000000000000000000000000000000..ac62678c7f3ebb086b3bd09bd675f17900ff938c --- /dev/null +++ b/libs/libc/machine/rh850/ghs/arch_setjmp.850 @@ -0,0 +1,137 @@ +-------------------------------------------------------------------------------- +-- Function setjump. +-------------------------------------------------------------------------------- + -- C Function Prototype: + -- int setjmp(jmp_buf env); + +.global _setjmp +.extern _setjmp +_setjmp: + mov r6, r12 ; r12 = env + + st.w r1, 0[r12] + st.w r2, 4[r12] + st.w sp, 8[r12] + st.w r4, 12[r12] + st.w r5, 16[r12] + st.w r6, 20[r12] + st.w r7, 24[r12] + st.w r8, 28[r12] + st.w r9, 32[r12] + st.w r10, 36[r12] + st.w r11, 40[r12] + st.w r12, 44[r12] + st.w r13, 48[r12] + st.w r14, 52[r12] + st.w r15, 56[r12] + st.w r16, 60[r12] + st.w r17, 64[r12] + st.w r18, 68[r12] + st.w r19, 72[r12] + st.w r20, 76[r12] + st.w r21, 80[r12] + st.w r22, 84[r12] + st.w r23, 88[r12] + st.w r24, 92[r12] + st.w r25, 96[r12] + st.w r26, 100[r12] + st.w r27, 104[r12] + st.w r28, 108[r12] + st.w r29, 112[r12] + st.w r30, 116[r12] + st.w r31, 120[r12] + + stsr EIPSW, r15 + stsr EIPC, r16 + stsr EIIC, r17 + stsr CTPSW, r18 + stsr CTPC, r19 + st.w r15, 124[r12] + st.w r16, 128[r12] + st.w r17, 132[r12] + st.w r18, 136[r12] + st.w r19, 140[r12] + + stsr FPSR, r18 + stsr FPEPC, r19 + st.w r18, 144[r12] + st.w r19, 148[r12] + + mov 0, r10 + jmp [lp] + +-------------------------------------------------------------------------------- +-- Function longjmp. +-------------------------------------------------------------------------------- +-- C Function Prototype: +-- void longjmp(jmp_buf env, int val); +-- Input Parameters: +-- jmp_buf env +-- int val + +.global _longjmp +.extern _longjmp +_longjmp: + /* r6 = env, r7 = val */ + mov r6, r12 + mov r7, r15 + + cmp r0, r15 + bne _longjmprestore + mov 1, r15 +_longjmprestore: + + ld.w 0[r12], r1 + ld.w 4[r12], r2 + ld.w 8[r12], sp + ld.w 12[r12], r4 + ld.w 16[r12], r5 + ld.w 20[r12], r6 + ld.w 24[r12], r7 + ld.w 28[r12], r8 + ld.w 32[r12], r9 + ld.w 40[r12], r11 + /* skip r12 because it holds return value */ + ld.w 48[r12], r13 + ld.w 52[r12], r14 + /* skip r15 because it holds return value */ + ld.w 60[r12], r16 + ld.w 64[r12], r17 + ld.w 68[r12], r18 + ld.w 72[r12], r19 + ld.w 76[r12], r20 + ld.w 80[r12], r21 + ld.w 84[r12], r22 + ld.w 88[r12], r23 + ld.w 92[r12], r24 + ld.w 96[r12], r25 + ld.w 100[r12], r26 + ld.w 104[r12], r27 + ld.w 108[r12], r28 + ld.w 112[r12], r29 + ld.w 116[r12], r30 + ld.w 120[r12], r31 + + ld.w 124[r12], r16 + ldsr r16, EIPSW + ld.w 128[r12], r16 + ldsr r16, EIPC + ld.w 132[r12], r16 + ldsr r16, EIIC + ld.w 136[r12], r16 + ldsr r16, CTPSW + ld.w 140[r12], r16 + ldsr r16, CTPC + ld.w 144[r12], r16 + ldsr r16, FPSR + ld.w 148[r12], r16 + ldsr r16, FPEPC + + cmp r0, r10 -- check whether LP == NULL then call _longjmp_lp_error + be _longjmp_lp_error + + mov r15, r10 -- val return value for setjmp + jmp [lp] + +_longjmp_lp_error: + br _longjmp_lp_error diff --git a/sched/init/nx_bringup.c b/sched/init/nx_bringup.c index 2ea82b920ad33347e8f7d3e62c009235cf6bf749..f33511aa4dd93324bab96159d8a7754c98d076e7 100644 --- a/sched/init/nx_bringup.c +++ b/sched/init/nx_bringup.c @@ -295,7 +295,7 @@ static inline void nx_romfsetc(void) * ****************************************************************************/ -static inline void nx_start_application(void) +void nx_start_application(void) { #ifndef CONFIG_INIT_NONE FAR char * const argv[] = diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c index 6cc74b680f362e880c52b72ee53f4b6e784c20f9..4e90399d068e331fbe314fbb699edcb8cc60d52b 100644 --- a/sched/init/nx_start.c +++ b/sched/init/nx_start.c @@ -549,7 +549,6 @@ static void idle_group_initialize(void) * Does not return. * ****************************************************************************/ - void nx_start(void) { int i; @@ -598,7 +597,6 @@ void nx_start(void) /* Get the user-mode heap from the platform specific code and configure * the user-mode memory allocator. */ - up_allocate_heap(&heap_start, &heap_size); kumm_initialize(heap_start, heap_size); #endif @@ -607,7 +605,6 @@ void nx_start(void) /* Get the kernel-mode heap from the platform specific code and * configure the kernel-mode memory allocator. */ - up_allocate_kheap(&heap_start, &heap_size); kmm_initialize(heap_start, heap_size); #endif @@ -617,7 +614,6 @@ void nx_start(void) * heap information from the platform-specific code and configure the * page allocator. */ - up_allocate_pgheap(&heap_start, &heap_size); mm_pginitialize(heap_start, heap_size); #endif @@ -790,7 +786,6 @@ void nx_start(void) g_nx_initstate = OSINIT_OSREADY; /* Create initial tasks and bring-up the system */ - DEBUGVERIFY(nx_bringup()); /* Enter to idleloop */ @@ -800,8 +795,10 @@ void nx_start(void) /* Let other threads have access to the memory manager */ sched_trace_end(); + sched_unlock(); + /* The IDLE Loop **********************************************************/ /* When control is return to this point, the system is idle. */ diff --git a/sched/sched/sched_processtimer.c b/sched/sched/sched_processtimer.c index 0de54a4038ff9cdd68a7c54b699435310818a91f..097d8f6d5b5c0ec626801422ad71a16505f672a1 100644 --- a/sched/sched/sched_processtimer.c +++ b/sched/sched/sched_processtimer.c @@ -61,7 +61,7 @@ ****************************************************************************/ #if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_SPORADIC) -static inline void nxsched_cpu_scheduler(int cpu) +static void nxsched_cpu_scheduler(int cpu) { FAR struct tcb_s *rtcb = current_task(cpu); @@ -109,7 +109,7 @@ static inline void nxsched_cpu_scheduler(int cpu) ****************************************************************************/ #if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_SPORADIC) -static inline void nxsched_process_scheduler(void) +static void nxsched_process_scheduler(void) { irqstate_t flags; int i; diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index 219de4ee139dd2c541e06e15641989c9c65810f8..8f05c7c9b57208edf69f0a371a15e4a7741aae9a 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -330,7 +330,7 @@ int nxsig_clockwait(int clockid, int flags, dq_addlast((FAR dq_entry_t *)rtcb, &g_waitingforsignal); /* Now, perform the context switch if one is needed */ - + up_switch_context(this_task(), rtcb); /* We no longer need the watchdog */