# ddr5-testbed

**Repository Path**: hilbert-wang/ddr5-testbed

## Basic Information

- **Project Name**: ddr5-testbed
- **Description**: https://github.com/antmicro/ddr5-testbed
- **Primary Language**: Unknown
- **License**: Apache-2.0
- **Default Branch**: main
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-12-08
- **Last Updated**: 2024-12-08

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# DDR5 Testbed

Copyright (c) 2022-2024 [Antmicro](https://www.antmicro.com)

![](img/ddr5-testbed.png)

## Overview

This project contains open hardware design files for an experimental test module in the mechanical form factor of SO-DIMM.
The module includes a single DDR5 RAM IC with all signals break-routed in the SO-DIMM edge connector.
The board has been designed to target Micron [MT60B2G8HB-48B:A](https://www.farnell.com/datasheets/3704816.pdf)
16Gb DRAM.
The design files were prepared in KiCad.
Please note that this board is not electrically compatible with off-the-shelf SO-DIMM DDR memory modules.
It is compatible with [this](https://github.com/antmicro/lpddr4-test-board) experimental testing platform.

### Project structure

The main project directory contains KiCad PCB project files, a LICENSE and a README.
The remaining files are stored in the following directories:

* `img` - contains graphics for this README
* `doc` - contains schematics in PDF form
* `assets` - contains visual assets for showcasing this design on [Open Hardware Portal](https://openhardware.antmicro.com).

## License

This project is published under the [Apache-2.0](LICENSE) license.