diff --git a/cpu/soc-x2600/include/tcu.h b/cpu/soc-x2600/include/tcu.h new file mode 100644 index 0000000000000000000000000000000000000000..f2dd7134f7a4d5bf81b7c2c17d0f8dc6996b2fae --- /dev/null +++ b/cpu/soc-x2600/include/tcu.h @@ -0,0 +1,1234 @@ +#ifndef __REG_TCU_H__ +#define __REG_TCU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup group_TCU TCU控制器 + * @{ + */ + +/** + * @addtogroup g_TCU_reg TCU 寄存器定义 + * @{ + */ + +typedef struct { + __IO unsigned long TDFRn; /*!< Channel n full data value ,RW, 0x040 + n * 0x10 n=0~7 */ + __IO unsigned long TDHRn; /*!< Channel n half data value ,RW, 0x044 + n * 0x10 n=0~7 */ + __IO unsigned long TCNTn; /*!< Channel n timer counter ,RW, 0x048 + n * 0x10 n=0~7 */ + __IO unsigned long TCRn; /*!< Channel n timer control ,RW, 0x04C + n * 0x10 n=0~7 */ +} TCU_CHAN_TypeDef; +/** +* @brief Registers for tcu +*/ +typedef struct { + ////TODO, 添加寄存器Reserved，填充地址空间 + unsigned long RESERVED_0x00[4]; /*!< Reserved Memory Area start from 0x00 to 0x10*/ + __I unsigned long TER; /*!< Enable timer counter , R, 0x010 */ + __O unsigned long TESR; /*!< Set enable , W, 0x014 */ + __O unsigned long TECR; /*!< Clear enable , W, 0x018 */ + __I unsigned long TSR; /*!< Stop timer counter , R, 0x01C */ + __I unsigned long TFR; /*!< Comparison flag , R, 0x020 */ + __O unsigned long TFSR; /*!< Set comparison flag , W, 0x024 */ + __O unsigned long TFCR; /*!< Clear comparison flag , W, 0x028 */ + __O unsigned long TSSR; /*!< Set stop , W, 0x02C */ + __I unsigned long TMR; /*!< Interrupt mask , R, 0x030 */ + __O unsigned long TMSR; /*!< Set interrupt mask , W, 0x034 */ + __O unsigned long TMCR; /*!< Clear interrupt mask , W, 0x038 */ + __O unsigned long TSCR; /*!< Clear stop , W, 0x03C */ + TCU_CHAN_TypeDef CHAN[8]; + __IO unsigned long CAPCRn[8]; /*!< Channel n capture control ,RW, 0x0C0 + n * 0x04 n=0~7 */ + __IO unsigned long CAPVR0; /*!< Channel 0 capture value ,RW, 0x0E0 */ + __IO unsigned long CAPVR1; /*!< Channel 1 capture value ,RW, 0x0E4 */ + __IO unsigned long CAPVR2; /*!< Channel 2 capture value ,RW, 0x0E8 */ + __IO unsigned long CAPVR3; /*!< Channel 3 capture value ,RW, 0x0EC */ + __IO unsigned long CAPVR4; /*!< Channel 4 capture value ,RW, 0x0F0 */ + __IO unsigned long CAPVR5; /*!< Channel 5 capture value ,RW, 0xF4 */ + __IO unsigned long CAPVR6; /*!< Channel 6 capture value ,RW, 0xF8 */ + __IO unsigned long CAPVR7; /*!< Channel 7 capture value ,RW, 0xFC */ + unsigned long RESERVED_0x100[40]; /*!< Reserved Memory Area start from 0x100 to 0x1a0*/ + __IO unsigned long FIRVRn[8]; /*!< Channel n filter counter value ,RW, 0x1A0 + n * 0x04 n=0~7 */ + unsigned long RESERVED_0x1c0[16]; /*!< Reserved Memory Area start from 0x1c0 to 0x200*/ + __I unsigned long TSFR; /*!< Store flag , R, 0x200 */ + __O unsigned long TSFSR; /*!< Set store falg , W, 0x204 */ + __O unsigned long TSFCR; /*!< Clear store flag , W, 0x208 */ + unsigned long RESERVED_0x20c[1]; /*!< Reserved Memory Area start from 0x20c to 0x210*/ + __I unsigned long TSMR; /*!< Store interrupt mask , R, 0x210 */ + __O unsigned long TSMSR; /*!< Set store interrupt mask , W, 0x214 */ + __O unsigned long TSMCR; /*!< Clear store interrupt mask , W, 0x218 */ + unsigned long RESERVED_0x21c[1]; /*!< Reserved Memory Area start from 0x21c to 0x220*/ + __IO unsigned long TSVRn[8]; /*!< Channel n value of stored conter,RW, 0x220 + n * 0x04 n=0~7 */ + __IO unsigned long TSFVRn[8]; /*!< Channel n value of stored filter conter,RW, 0x240 + n * 0x04 n=0~7 */ +} TCU_TypeDef; + +/********* Register BitField Details: TER BASE+0x0010 *********/ +#define TER_OSTEN_Pos (15U) +#define TER_OSTEN_Msk (0x1UL << TER_OSTEN_Pos) /*!< 0x00008000 */ +#define TER_OSTEN TER_OSTEN_Msk +#define TER_OSTEN_0 (0x1UL << TER_OSTEN_Pos) /*!< 0x00008000 */ +#define TER_TCEN7_Pos (7U) +#define TER_TCEN7_Msk (0x1UL << TER_TCEN7_Pos) /*!< 0x00000080 */ +#define TER_TCEN7 TER_TCEN7_Msk +#define TER_TCEN7_0 (0x1UL << TER_TCEN7_Pos) /*!< 0x00000080 */ +#define TER_TCEN6_Pos (6U) +#define TER_TCEN6_Msk (0x1UL << TER_TCEN6_Pos) /*!< 0x00000040 */ +#define TER_TCEN6 TER_TCEN6_Msk +#define TER_TCEN6_0 (0x1UL << TER_TCEN6_Pos) /*!< 0x00000040 */ +#define TER_TCEN5_Pos (5U) +#define TER_TCEN5_Msk (0x1UL << TER_TCEN5_Pos) /*!< 0x00000020 */ +#define TER_TCEN5 TER_TCEN5_Msk +#define TER_TCEN5_0 (0x1UL << TER_TCEN5_Pos) /*!< 0x00000020 */ +#define TER_TCEN4_Pos (4U) +#define TER_TCEN4_Msk (0x1UL << TER_TCEN4_Pos) /*!< 0x00000010 */ +#define TER_TCEN4 TER_TCEN4_Msk +#define TER_TCEN4_0 (0x1UL << TER_TCEN4_Pos) /*!< 0x00000010 */ +#define TER_TCEN3_Pos (3U) +#define TER_TCEN3_Msk (0x1UL << TER_TCEN3_Pos) /*!< 0x00000008 */ +#define TER_TCEN3 TER_TCEN3_Msk +#define TER_TCEN3_0 (0x1UL << TER_TCEN3_Pos) /*!< 0x00000008 */ +#define TER_TCEN2_Pos (2U) +#define TER_TCEN2_Msk (0x1UL << TER_TCEN2_Pos) /*!< 0x00000004 */ +#define TER_TCEN2 TER_TCEN2_Msk +#define TER_TCEN2_0 (0x1UL << TER_TCEN2_Pos) /*!< 0x00000004 */ +#define TER_TCEN1_Pos (1U) +#define TER_TCEN1_Msk (0x1UL << TER_TCEN1_Pos) /*!< 0x00000002 */ +#define TER_TCEN1 TER_TCEN1_Msk +#define TER_TCEN1_0 (0x1UL << TER_TCEN1_Pos) /*!< 0x00000002 */ +#define TER_TCEN0_Pos (0U) +#define TER_TCEN0_Msk (0x1UL << TER_TCEN0_Pos) /*!< 0x00000001 */ +#define TER_TCEN0 TER_TCEN0_Msk +#define TER_TCEN0_0 (0x1UL << TER_TCEN0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TESR BASE+0x0014 *********/ +#define TESR_OSTST_Pos (15U) +#define TESR_OSTST_Msk (0x1UL << TESR_OSTST_Pos) /*!< 0x00008000 */ +#define TESR_OSTST TESR_OSTST_Msk +#define TESR_OSTST_0 (0x1UL << TESR_OSTST_Pos) /*!< 0x00008000 */ +#define TESR_TCST7_Pos (7U) +#define TESR_TCST7_Msk (0x1UL << TESR_TCST7_Pos) /*!< 0x00000080 */ +#define TESR_TCST7 TESR_TCST7_Msk +#define TESR_TCST7_0 (0x1UL << TESR_TCST7_Pos) /*!< 0x00000080 */ +#define TESR_TCST6_Pos (6U) +#define TESR_TCST6_Msk (0x1UL << TESR_TCST6_Pos) /*!< 0x00000040 */ +#define TESR_TCST6 TESR_TCST6_Msk +#define TESR_TCST6_0 (0x1UL << TESR_TCST6_Pos) /*!< 0x00000040 */ +#define TESR_TCST5_Pos (5U) +#define TESR_TCST5_Msk (0x1UL << TESR_TCST5_Pos) /*!< 0x00000020 */ +#define TESR_TCST5 TESR_TCST5_Msk +#define TESR_TCST5_0 (0x1UL << TESR_TCST5_Pos) /*!< 0x00000020 */ +#define TESR_TCST4_Pos (4U) +#define TESR_TCST4_Msk (0x1UL << TESR_TCST4_Pos) /*!< 0x00000010 */ +#define TESR_TCST4 TESR_TCST4_Msk +#define TESR_TCST4_0 (0x1UL << TESR_TCST4_Pos) /*!< 0x00000010 */ +#define TESR_TCST3_Pos (3U) +#define TESR_TCST3_Msk (0x1UL << TESR_TCST3_Pos) /*!< 0x00000008 */ +#define TESR_TCST3 TESR_TCST3_Msk +#define TESR_TCST3_0 (0x1UL << TESR_TCST3_Pos) /*!< 0x00000008 */ +#define TESR_TCST2_Pos (2U) +#define TESR_TCST2_Msk (0x1UL << TESR_TCST2_Pos) /*!< 0x00000004 */ +#define TESR_TCST2 TESR_TCST2_Msk +#define TESR_TCST2_0 (0x1UL << TESR_TCST2_Pos) /*!< 0x00000004 */ +#define TESR_TCST1_Pos (1U) +#define TESR_TCST1_Msk (0x1UL << TESR_TCST1_Pos) /*!< 0x00000002 */ +#define TESR_TCST1 TESR_TCST1_Msk +#define TESR_TCST1_0 (0x1UL << TESR_TCST1_Pos) /*!< 0x00000002 */ +#define TESR_TCST0_Pos (0U) +#define TESR_TCST0_Msk (0x1UL << TESR_TCST0_Pos) /*!< 0x00000001 */ +#define TESR_TCST0 TESR_TCST0_Msk +#define TESR_TCST0_0 (0x1UL << TESR_TCST0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TECR BASE+0x0018 *********/ +#define TECR_OSTCL_Pos (15U) +#define TECR_OSTCL_Msk (0x1UL << TECR_OSTCL_Pos) /*!< 0x00008000 */ +#define TECR_OSTCL TECR_OSTCL_Msk +#define TECR_OSTCL_0 (0x1UL << TECR_OSTCL_Pos) /*!< 0x00008000 */ +#define TECR_TCCL7_Pos (7U) +#define TECR_TCCL7_Msk (0x1UL << TECR_TCCL7_Pos) /*!< 0x00000080 */ +#define TECR_TCCL7 TECR_TCCL7_Msk +#define TECR_TCCL7_0 (0x1UL << TECR_TCCL7_Pos) /*!< 0x00000080 */ +#define TECR_TCCL6_Pos (6U) +#define TECR_TCCL6_Msk (0x1UL << TECR_TCCL6_Pos) /*!< 0x00000040 */ +#define TECR_TCCL6 TECR_TCCL6_Msk +#define TECR_TCCL6_0 (0x1UL << TECR_TCCL6_Pos) /*!< 0x00000040 */ +#define TECR_TCCL5_Pos (5U) +#define TECR_TCCL5_Msk (0x1UL << TECR_TCCL5_Pos) /*!< 0x00000020 */ +#define TECR_TCCL5 TECR_TCCL5_Msk +#define TECR_TCCL5_0 (0x1UL << TECR_TCCL5_Pos) /*!< 0x00000020 */ +#define TECR_TCCL4_Pos (4U) +#define TECR_TCCL4_Msk (0x1UL << TECR_TCCL4_Pos) /*!< 0x00000010 */ +#define TECR_TCCL4 TECR_TCCL4_Msk +#define TECR_TCCL4_0 (0x1UL << TECR_TCCL4_Pos) /*!< 0x00000010 */ +#define TECR_TCCL3_Pos (3U) +#define TECR_TCCL3_Msk (0x1UL << TECR_TCCL3_Pos) /*!< 0x00000008 */ +#define TECR_TCCL3 TECR_TCCL3_Msk +#define TECR_TCCL3_0 (0x1UL << TECR_TCCL3_Pos) /*!< 0x00000008 */ +#define TECR_TCCL2_Pos (2U) +#define TECR_TCCL2_Msk (0x1UL << TECR_TCCL2_Pos) /*!< 0x00000004 */ +#define TECR_TCCL2 TECR_TCCL2_Msk +#define TECR_TCCL2_0 (0x1UL << TECR_TCCL2_Pos) /*!< 0x00000004 */ +#define TECR_TCCL1_Pos (1U) +#define TECR_TCCL1_Msk (0x1UL << TECR_TCCL1_Pos) /*!< 0x00000002 */ +#define TECR_TCCL1 TECR_TCCL1_Msk +#define TECR_TCCL1_0 (0x1UL << TECR_TCCL1_Pos) /*!< 0x00000002 */ +#define TECR_TCCL0_Pos (0U) +#define TECR_TCCL0_Msk (0x1UL << TECR_TCCL0_Pos) /*!< 0x00000001 */ +#define TECR_TCCL0 TECR_TCCL0_Msk +#define TECR_TCCL0_0 (0x1UL << TECR_TCCL0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSR BASE+0x001c *********/ +#define TSR_WDTS_Pos (16U) +#define TSR_WDTS_Msk (0x1UL << TSR_WDTS_Pos) /*!< 0x00010000 */ +#define TSR_WDTS TSR_WDTS_Msk +#define TSR_WDTS_0 (0x1UL << TSR_WDTS_Pos) /*!< 0x00010000 */ +#define TSR_OSTS_Pos (15U) +#define TSR_OSTS_Msk (0x1UL << TSR_OSTS_Pos) /*!< 0x00008000 */ +#define TSR_OSTS TSR_OSTS_Msk +#define TSR_OSTS_0 (0x1UL << TSR_OSTS_Pos) /*!< 0x00008000 */ +#define TSR_STOP7_Pos (7U) +#define TSR_STOP7_Msk (0x1UL << TSR_STOP7_Pos) /*!< 0x00000080 */ +#define TSR_STOP7 TSR_STOP7_Msk +#define TSR_STOP7_0 (0x1UL << TSR_STOP7_Pos) /*!< 0x00000080 */ +#define TSR_STOP6_Pos (6U) +#define TSR_STOP6_Msk (0x1UL << TSR_STOP6_Pos) /*!< 0x00000040 */ +#define TSR_STOP6 TSR_STOP6_Msk +#define TSR_STOP6_0 (0x1UL << TSR_STOP6_Pos) /*!< 0x00000040 */ +#define TSR_STOP5_Pos (5U) +#define TSR_STOP5_Msk (0x1UL << TSR_STOP5_Pos) /*!< 0x00000020 */ +#define TSR_STOP5 TSR_STOP5_Msk +#define TSR_STOP5_0 (0x1UL << TSR_STOP5_Pos) /*!< 0x00000020 */ +#define TSR_STOP4_Pos (4U) +#define TSR_STOP4_Msk (0x1UL << TSR_STOP4_Pos) /*!< 0x00000010 */ +#define TSR_STOP4 TSR_STOP4_Msk +#define TSR_STOP4_0 (0x1UL << TSR_STOP4_Pos) /*!< 0x00000010 */ +#define TSR_STOP3_Pos (3U) +#define TSR_STOP3_Msk (0x1UL << TSR_STOP3_Pos) /*!< 0x00000008 */ +#define TSR_STOP3 TSR_STOP3_Msk +#define TSR_STOP3_0 (0x1UL << TSR_STOP3_Pos) /*!< 0x00000008 */ +#define TSR_STOP2_Pos (2U) +#define TSR_STOP2_Msk (0x1UL << TSR_STOP2_Pos) /*!< 0x00000004 */ +#define TSR_STOP2 TSR_STOP2_Msk +#define TSR_STOP2_0 (0x1UL << TSR_STOP2_Pos) /*!< 0x00000004 */ +#define TSR_STOP1_Pos (1U) +#define TSR_STOP1_Msk (0x1UL << TSR_STOP1_Pos) /*!< 0x00000002 */ +#define TSR_STOP1 TSR_STOP1_Msk +#define TSR_STOP1_0 (0x1UL << TSR_STOP1_Pos) /*!< 0x00000002 */ +#define TSR_STOP0_Pos (0U) +#define TSR_STOP0_Msk (0x1UL << TSR_STOP0_Pos) /*!< 0x00000001 */ +#define TSR_STOP0 TSR_STOP0_Msk +#define TSR_STOP0_0 (0x1UL << TSR_STOP0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TFR BASE+0x0020 *********/ +#define TFR_HFALGW_Pos (24U) +#define TFR_HFALGW_Msk (0x1UL << TFR_HFALGW_Pos) /*!< 0x01000000 */ +#define TFR_HFALGW TFR_HFALGW_Msk +#define TFR_HFALGW_0 (0x1UL << TFR_HFALGW_Pos) /*!< 0x01000000 */ +#define TFR_HFLAG7_Pos (23U) +#define TFR_HFLAG7_Msk (0x1UL << TFR_HFLAG7_Pos) /*!< 0x00800000 */ +#define TFR_HFLAG7 TFR_HFLAG7_Msk +#define TFR_HFLAG7_0 (0x1UL << TFR_HFLAG7_Pos) /*!< 0x00800000 */ +#define TFR_HFLAG6_Pos (22U) +#define TFR_HFLAG6_Msk (0x1UL << TFR_HFLAG6_Pos) /*!< 0x00400000 */ +#define TFR_HFLAG6 TFR_HFLAG6_Msk +#define TFR_HFLAG6_0 (0x1UL << TFR_HFLAG6_Pos) /*!< 0x00400000 */ +#define TFR_HFLAG5_Pos (21U) +#define TFR_HFLAG5_Msk (0x1UL << TFR_HFLAG5_Pos) /*!< 0x00200000 */ +#define TFR_HFLAG5 TFR_HFLAG5_Msk +#define TFR_HFLAG5_0 (0x1UL << TFR_HFLAG5_Pos) /*!< 0x00200000 */ +#define TFR_HFLAG4_Pos (20U) +#define TFR_HFLAG4_Msk (0x1UL << TFR_HFLAG4_Pos) /*!< 0x00100000 */ +#define TFR_HFLAG4 TFR_HFLAG4_Msk +#define TFR_HFLAG4_0 (0x1UL << TFR_HFLAG4_Pos) /*!< 0x00100000 */ +#define TFR_HFLAG3_Pos (19U) +#define TFR_HFLAG3_Msk (0x1UL << TFR_HFLAG3_Pos) /*!< 0x00080000 */ +#define TFR_HFLAG3 TFR_HFLAG3_Msk +#define TFR_HFLAG3_0 (0x1UL << TFR_HFLAG3_Pos) /*!< 0x00080000 */ +#define TFR_HFLAG2_Pos (18U) +#define TFR_HFLAG2_Msk (0x1UL << TFR_HFLAG2_Pos) /*!< 0x00040000 */ +#define TFR_HFLAG2 TFR_HFLAG2_Msk +#define TFR_HFLAG2_0 (0x1UL << TFR_HFLAG2_Pos) /*!< 0x00040000 */ +#define TFR_HFLAG1_Pos (17U) +#define TFR_HFLAG1_Msk (0x1UL << TFR_HFLAG1_Pos) /*!< 0x00020000 */ +#define TFR_HFLAG1 TFR_HFLAG1_Msk +#define TFR_HFLAG1_0 (0x1UL << TFR_HFLAG1_Pos) /*!< 0x00020000 */ +#define TFR_HFLAG0_Pos (16U) +#define TFR_HFLAG0_Msk (0x1UL << TFR_HFLAG0_Pos) /*!< 0x00010000 */ +#define TFR_HFLAG0 TFR_HFLAG0_Msk +#define TFR_HFLAG0_0 (0x1UL << TFR_HFLAG0_Pos) /*!< 0x00010000 */ +#define TFR_OSTFLAG_Pos (15U) +#define TFR_OSTFLAG_Msk (0x1UL << TFR_OSTFLAG_Pos) /*!< 0x00008000 */ +#define TFR_OSTFLAG TFR_OSTFLAG_Msk +#define TFR_OSTFLAG_0 (0x1UL << TFR_OSTFLAG_Pos) /*!< 0x00008000 */ +#define TFR_FFLAG7_Pos (7U) +#define TFR_FFLAG7_Msk (0x1UL << TFR_FFLAG7_Pos) /*!< 0x00000080 */ +#define TFR_FFLAG7 TFR_FFLAG7_Msk +#define TFR_FFLAG7_0 (0x1UL << TFR_FFLAG7_Pos) /*!< 0x00000080 */ +#define TFR_FFLAG6_Pos (6U) +#define TFR_FFLAG6_Msk (0x1UL << TFR_FFLAG6_Pos) /*!< 0x00000040 */ +#define TFR_FFLAG6 TFR_FFLAG6_Msk +#define TFR_FFLAG6_0 (0x1UL << TFR_FFLAG6_Pos) /*!< 0x00000040 */ +#define TFR_FFLAG5_Pos (5U) +#define TFR_FFLAG5_Msk (0x1UL << TFR_FFLAG5_Pos) /*!< 0x00000020 */ +#define TFR_FFLAG5 TFR_FFLAG5_Msk +#define TFR_FFLAG5_0 (0x1UL << TFR_FFLAG5_Pos) /*!< 0x00000020 */ +#define TFR_FFLAG4_Pos (4U) +#define TFR_FFLAG4_Msk (0x1UL << TFR_FFLAG4_Pos) /*!< 0x00000010 */ +#define TFR_FFLAG4 TFR_FFLAG4_Msk +#define TFR_FFLAG4_0 (0x1UL << TFR_FFLAG4_Pos) /*!< 0x00000010 */ +#define TFR_FFLAG3_Pos (3U) +#define TFR_FFLAG3_Msk (0x1UL << TFR_FFLAG3_Pos) /*!< 0x00000008 */ +#define TFR_FFLAG3 TFR_FFLAG3_Msk +#define TFR_FFLAG3_0 (0x1UL << TFR_FFLAG3_Pos) /*!< 0x00000008 */ +#define TFR_FFLAG2_Pos (2U) +#define TFR_FFLAG2_Msk (0x1UL << TFR_FFLAG2_Pos) /*!< 0x00000004 */ +#define TFR_FFLAG2 TFR_FFLAG2_Msk +#define TFR_FFLAG2_0 (0x1UL << TFR_FFLAG2_Pos) /*!< 0x00000004 */ +#define TFR_FFLAG1_Pos (1U) +#define TFR_FFLAG1_Msk (0x1UL << TFR_FFLAG1_Pos) /*!< 0x00000002 */ +#define TFR_FFLAG1 TFR_FFLAG1_Msk +#define TFR_FFLAG1_0 (0x1UL << TFR_FFLAG1_Pos) /*!< 0x00000002 */ +#define TFR_FFLAG0_Pos (0U) +#define TFR_FFLAG0_Msk (0x1UL << TFR_FFLAG0_Pos) /*!< 0x00000001 */ +#define TFR_FFLAG0 TFR_FFLAG0_Msk +#define TFR_FFLAG0_0 (0x1UL << TFR_FFLAG0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TFSR BASE+0x0024 *********/ +#define TFSR_HFST7_Pos (23U) +#define TFSR_HFST7_Msk (0x1UL << TFSR_HFST7_Pos) /*!< 0x00800000 */ +#define TFSR_HFST7 TFSR_HFST7_Msk +#define TFSR_HFST7_0 (0x1UL << TFSR_HFST7_Pos) /*!< 0x00800000 */ +#define TFSR_HFST6_Pos (22U) +#define TFSR_HFST6_Msk (0x1UL << TFSR_HFST6_Pos) /*!< 0x00400000 */ +#define TFSR_HFST6 TFSR_HFST6_Msk +#define TFSR_HFST6_0 (0x1UL << TFSR_HFST6_Pos) /*!< 0x00400000 */ +#define TFSR_HFST5_Pos (21U) +#define TFSR_HFST5_Msk (0x1UL << TFSR_HFST5_Pos) /*!< 0x00200000 */ +#define TFSR_HFST5 TFSR_HFST5_Msk +#define TFSR_HFST5_0 (0x1UL << TFSR_HFST5_Pos) /*!< 0x00200000 */ +#define TFSR_HFST4_Pos (20U) +#define TFSR_HFST4_Msk (0x1UL << TFSR_HFST4_Pos) /*!< 0x00100000 */ +#define TFSR_HFST4 TFSR_HFST4_Msk +#define TFSR_HFST4_0 (0x1UL << TFSR_HFST4_Pos) /*!< 0x00100000 */ +#define TFSR_HFST3_Pos (19U) +#define TFSR_HFST3_Msk (0x1UL << TFSR_HFST3_Pos) /*!< 0x00080000 */ +#define TFSR_HFST3 TFSR_HFST3_Msk +#define TFSR_HFST3_0 (0x1UL << TFSR_HFST3_Pos) /*!< 0x00080000 */ +#define TFSR_HFST2_Pos (18U) +#define TFSR_HFST2_Msk (0x1UL << TFSR_HFST2_Pos) /*!< 0x00040000 */ +#define TFSR_HFST2 TFSR_HFST2_Msk +#define TFSR_HFST2_0 (0x1UL << TFSR_HFST2_Pos) /*!< 0x00040000 */ +#define TFSR_HFST1_Pos (17U) +#define TFSR_HFST1_Msk (0x1UL << TFSR_HFST1_Pos) /*!< 0x00020000 */ +#define TFSR_HFST1 TFSR_HFST1_Msk +#define TFSR_HFST1_0 (0x1UL << TFSR_HFST1_Pos) /*!< 0x00020000 */ +#define TFSR_HFST0_Pos (16U) +#define TFSR_HFST0_Msk (0x1UL << TFSR_HFST0_Pos) /*!< 0x00010000 */ +#define TFSR_HFST0 TFSR_HFST0_Msk +#define TFSR_HFST0_0 (0x1UL << TFSR_HFST0_Pos) /*!< 0x00010000 */ +#define TFSR_OSTFST_Pos (15U) +#define TFSR_OSTFST_Msk (0x1UL << TFSR_OSTFST_Pos) /*!< 0x00008000 */ +#define TFSR_OSTFST TFSR_OSTFST_Msk +#define TFSR_OSTFST_0 (0x1UL << TFSR_OSTFST_Pos) /*!< 0x00008000 */ +#define TFSR_FFST7_Pos (7U) +#define TFSR_FFST7_Msk (0x1UL << TFSR_FFST7_Pos) /*!< 0x00000080 */ +#define TFSR_FFST7 TFSR_FFST7_Msk +#define TFSR_FFST7_0 (0x1UL << TFSR_FFST7_Pos) /*!< 0x00000080 */ +#define TFSR_FFST6_Pos (6U) +#define TFSR_FFST6_Msk (0x1UL << TFSR_FFST6_Pos) /*!< 0x00000040 */ +#define TFSR_FFST6 TFSR_FFST6_Msk +#define TFSR_FFST6_0 (0x1UL << TFSR_FFST6_Pos) /*!< 0x00000040 */ +#define TFSR_FFST5_Pos (5U) +#define TFSR_FFST5_Msk (0x1UL << TFSR_FFST5_Pos) /*!< 0x00000020 */ +#define TFSR_FFST5 TFSR_FFST5_Msk +#define TFSR_FFST5_0 (0x1UL << TFSR_FFST5_Pos) /*!< 0x00000020 */ +#define TFSR_FFST4_Pos (4U) +#define TFSR_FFST4_Msk (0x1UL << TFSR_FFST4_Pos) /*!< 0x00000010 */ +#define TFSR_FFST4 TFSR_FFST4_Msk +#define TFSR_FFST4_0 (0x1UL << TFSR_FFST4_Pos) /*!< 0x00000010 */ +#define TFSR_FFST3_Pos (3U) +#define TFSR_FFST3_Msk (0x1UL << TFSR_FFST3_Pos) /*!< 0x00000008 */ +#define TFSR_FFST3 TFSR_FFST3_Msk +#define TFSR_FFST3_0 (0x1UL << TFSR_FFST3_Pos) /*!< 0x00000008 */ +#define TFSR_FFST2_Pos (2U) +#define TFSR_FFST2_Msk (0x1UL << TFSR_FFST2_Pos) /*!< 0x00000004 */ +#define TFSR_FFST2 TFSR_FFST2_Msk +#define TFSR_FFST2_0 (0x1UL << TFSR_FFST2_Pos) /*!< 0x00000004 */ +#define TFSR_FFST1_Pos (1U) +#define TFSR_FFST1_Msk (0x1UL << TFSR_FFST1_Pos) /*!< 0x00000002 */ +#define TFSR_FFST1 TFSR_FFST1_Msk +#define TFSR_FFST1_0 (0x1UL << TFSR_FFST1_Pos) /*!< 0x00000002 */ +#define TFSR_FFST0_Pos (0U) +#define TFSR_FFST0_Msk (0x1UL << TFSR_FFST0_Pos) /*!< 0x00000001 */ +#define TFSR_FFST0 TFSR_FFST0_Msk +#define TFSR_FFST0_0 (0x1UL << TFSR_FFST0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TFCR BASE+0x0028 *********/ +#define TFCR_HFCLW_Pos (24U) +#define TFCR_HFCLW_Msk (0x1UL << TFCR_HFCLW_Pos) /*!< 0x01000000 */ +#define TFCR_HFCLW TFCR_HFCLW_Msk +#define TFCR_HFCLW_0 (0x1UL << TFCR_HFCLW_Pos) /*!< 0x01000000 */ +#define TFCR_HFCL7_Pos (23U) +#define TFCR_HFCL7_Msk (0x1UL << TFCR_HFCL7_Pos) /*!< 0x00800000 */ +#define TFCR_HFCL7 TFCR_HFCL7_Msk +#define TFCR_HFCL7_0 (0x1UL << TFCR_HFCL7_Pos) /*!< 0x00800000 */ +#define TFCR_HFCL6_Pos (22U) +#define TFCR_HFCL6_Msk (0x1UL << TFCR_HFCL6_Pos) /*!< 0x00400000 */ +#define TFCR_HFCL6 TFCR_HFCL6_Msk +#define TFCR_HFCL6_0 (0x1UL << TFCR_HFCL6_Pos) /*!< 0x00400000 */ +#define TFCR_HFCL5_Pos (21U) +#define TFCR_HFCL5_Msk (0x1UL << TFCR_HFCL5_Pos) /*!< 0x00200000 */ +#define TFCR_HFCL5 TFCR_HFCL5_Msk +#define TFCR_HFCL5_0 (0x1UL << TFCR_HFCL5_Pos) /*!< 0x00200000 */ +#define TFCR_HFCL4_Pos (20U) +#define TFCR_HFCL4_Msk (0x1UL << TFCR_HFCL4_Pos) /*!< 0x00100000 */ +#define TFCR_HFCL4 TFCR_HFCL4_Msk +#define TFCR_HFCL4_0 (0x1UL << TFCR_HFCL4_Pos) /*!< 0x00100000 */ +#define TFCR_HFCL3_Pos (19U) +#define TFCR_HFCL3_Msk (0x1UL << TFCR_HFCL3_Pos) /*!< 0x00080000 */ +#define TFCR_HFCL3 TFCR_HFCL3_Msk +#define TFCR_HFCL3_0 (0x1UL << TFCR_HFCL3_Pos) /*!< 0x00080000 */ +#define TFCR_HFCL2_Pos (18U) +#define TFCR_HFCL2_Msk (0x1UL << TFCR_HFCL2_Pos) /*!< 0x00040000 */ +#define TFCR_HFCL2 TFCR_HFCL2_Msk +#define TFCR_HFCL2_0 (0x1UL << TFCR_HFCL2_Pos) /*!< 0x00040000 */ +#define TFCR_HFCL1_Pos (17U) +#define TFCR_HFCL1_Msk (0x1UL << TFCR_HFCL1_Pos) /*!< 0x00020000 */ +#define TFCR_HFCL1 TFCR_HFCL1_Msk +#define TFCR_HFCL1_0 (0x1UL << TFCR_HFCL1_Pos) /*!< 0x00020000 */ +#define TFCR_HFCL0_Pos (16U) +#define TFCR_HFCL0_Msk (0x1UL << TFCR_HFCL0_Pos) /*!< 0x00010000 */ +#define TFCR_HFCL0 TFCR_HFCL0_Msk +#define TFCR_HFCL0_0 (0x1UL << TFCR_HFCL0_Pos) /*!< 0x00010000 */ +#define TFCR_OSTFCL_Pos (15U) +#define TFCR_OSTFCL_Msk (0x1UL << TFCR_OSTFCL_Pos) /*!< 0x00008000 */ +#define TFCR_OSTFCL TFCR_OSTFCL_Msk +#define TFCR_OSTFCL_0 (0x1UL << TFCR_OSTFCL_Pos) /*!< 0x00008000 */ +#define TFCR_FFCL7_Pos (7U) +#define TFCR_FFCL7_Msk (0x1UL << TFCR_FFCL7_Pos) /*!< 0x00000080 */ +#define TFCR_FFCL7 TFCR_FFCL7_Msk +#define TFCR_FFCL7_0 (0x1UL << TFCR_FFCL7_Pos) /*!< 0x00000080 */ +#define TFCR_FFCL6_Pos (6U) +#define TFCR_FFCL6_Msk (0x1UL << TFCR_FFCL6_Pos) /*!< 0x00000040 */ +#define TFCR_FFCL6 TFCR_FFCL6_Msk +#define TFCR_FFCL6_0 (0x1UL << TFCR_FFCL6_Pos) /*!< 0x00000040 */ +#define TFCR_FFCL5_Pos (5U) +#define TFCR_FFCL5_Msk (0x1UL << TFCR_FFCL5_Pos) /*!< 0x00000020 */ +#define TFCR_FFCL5 TFCR_FFCL5_Msk +#define TFCR_FFCL5_0 (0x1UL << TFCR_FFCL5_Pos) /*!< 0x00000020 */ +#define TFCR_FFCL4_Pos (4U) +#define TFCR_FFCL4_Msk (0x1UL << TFCR_FFCL4_Pos) /*!< 0x00000010 */ +#define TFCR_FFCL4 TFCR_FFCL4_Msk +#define TFCR_FFCL4_0 (0x1UL << TFCR_FFCL4_Pos) /*!< 0x00000010 */ +#define TFCR_FFCL3_Pos (3U) +#define TFCR_FFCL3_Msk (0x1UL << TFCR_FFCL3_Pos) /*!< 0x00000008 */ +#define TFCR_FFCL3 TFCR_FFCL3_Msk +#define TFCR_FFCL3_0 (0x1UL << TFCR_FFCL3_Pos) /*!< 0x00000008 */ +#define TFCR_FFCL2_Pos (2U) +#define TFCR_FFCL2_Msk (0x1UL << TFCR_FFCL2_Pos) /*!< 0x00000004 */ +#define TFCR_FFCL2 TFCR_FFCL2_Msk +#define TFCR_FFCL2_0 (0x1UL << TFCR_FFCL2_Pos) /*!< 0x00000004 */ +#define TFCR_FFCL1_Pos (1U) +#define TFCR_FFCL1_Msk (0x1UL << TFCR_FFCL1_Pos) /*!< 0x00000002 */ +#define TFCR_FFCL1 TFCR_FFCL1_Msk +#define TFCR_FFCL1_0 (0x1UL << TFCR_FFCL1_Pos) /*!< 0x00000002 */ +#define TFCR_FFCL0_Pos (0U) +#define TFCR_FFCL0_Msk (0x1UL << TFCR_FFCL0_Pos) /*!< 0x00000001 */ +#define TFCR_FFCL0 TFCR_FFCL0_Msk +#define TFCR_FFCL0_0 (0x1UL << TFCR_FFCL0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSSR BASE+0x002c *********/ +#define TSSR_WDTSS_Pos (16U) +#define TSSR_WDTSS_Msk (0x1UL << TSSR_WDTSS_Pos) /*!< 0x00010000 */ +#define TSSR_WDTSS TSSR_WDTSS_Msk +#define TSSR_WDTSS_0 (0x1UL << TSSR_WDTSS_Pos) /*!< 0x00010000 */ +#define TSSR_OSTSS_Pos (15U) +#define TSSR_OSTSS_Msk (0x1UL << TSSR_OSTSS_Pos) /*!< 0x00008000 */ +#define TSSR_OSTSS TSSR_OSTSS_Msk +#define TSSR_OSTSS_0 (0x1UL << TSSR_OSTSS_Pos) /*!< 0x00008000 */ +#define TSSR_STPS7_Pos (7U) +#define TSSR_STPS7_Msk (0x1UL << TSSR_STPS7_Pos) /*!< 0x00000080 */ +#define TSSR_STPS7 TSSR_STPS7_Msk +#define TSSR_STPS7_0 (0x1UL << TSSR_STPS7_Pos) /*!< 0x00000080 */ +#define TSSR_STPS6_Pos (6U) +#define TSSR_STPS6_Msk (0x1UL << TSSR_STPS6_Pos) /*!< 0x00000040 */ +#define TSSR_STPS6 TSSR_STPS6_Msk +#define TSSR_STPS6_0 (0x1UL << TSSR_STPS6_Pos) /*!< 0x00000040 */ +#define TSSR_STPS5_Pos (5U) +#define TSSR_STPS5_Msk (0x1UL << TSSR_STPS5_Pos) /*!< 0x00000020 */ +#define TSSR_STPS5 TSSR_STPS5_Msk +#define TSSR_STPS5_0 (0x1UL << TSSR_STPS5_Pos) /*!< 0x00000020 */ +#define TSSR_STPS4_Pos (4U) +#define TSSR_STPS4_Msk (0x1UL << TSSR_STPS4_Pos) /*!< 0x00000010 */ +#define TSSR_STPS4 TSSR_STPS4_Msk +#define TSSR_STPS4_0 (0x1UL << TSSR_STPS4_Pos) /*!< 0x00000010 */ +#define TSSR_STPS3_Pos (3U) +#define TSSR_STPS3_Msk (0x1UL << TSSR_STPS3_Pos) /*!< 0x00000008 */ +#define TSSR_STPS3 TSSR_STPS3_Msk +#define TSSR_STPS3_0 (0x1UL << TSSR_STPS3_Pos) /*!< 0x00000008 */ +#define TSSR_STPS2_Pos (2U) +#define TSSR_STPS2_Msk (0x1UL << TSSR_STPS2_Pos) /*!< 0x00000004 */ +#define TSSR_STPS2 TSSR_STPS2_Msk +#define TSSR_STPS2_0 (0x1UL << TSSR_STPS2_Pos) /*!< 0x00000004 */ +#define TSSR_STPS1_Pos (1U) +#define TSSR_STPS1_Msk (0x1UL << TSSR_STPS1_Pos) /*!< 0x00000002 */ +#define TSSR_STPS1 TSSR_STPS1_Msk +#define TSSR_STPS1_0 (0x1UL << TSSR_STPS1_Pos) /*!< 0x00000002 */ +#define TSSR_STPS0_Pos (0U) +#define TSSR_STPS0_Msk (0x1UL << TSSR_STPS0_Pos) /*!< 0x00000001 */ +#define TSSR_STPS0 TSSR_STPS0_Msk +#define TSSR_STPS0_0 (0x1UL << TSSR_STPS0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TMR BASE+0x0030 *********/ +#define TMR_HMASKW_Pos (24U) +#define TMR_HMASKW_Msk (0x1UL << TMR_HMASKW_Pos) /*!< 0x01000000 */ +#define TMR_HMASKW TMR_HMASKW_Msk +#define TMR_HMASKW_0 (0x1UL << TMR_HMASKW_Pos) /*!< 0x01000000 */ +#define TMR_HMASK7_Pos (23U) +#define TMR_HMASK7_Msk (0x1UL << TMR_HMASK7_Pos) /*!< 0x00800000 */ +#define TMR_HMASK7 TMR_HMASK7_Msk +#define TMR_HMASK7_0 (0x1UL << TMR_HMASK7_Pos) /*!< 0x00800000 */ +#define TMR_HMASK6_Pos (22U) +#define TMR_HMASK6_Msk (0x1UL << TMR_HMASK6_Pos) /*!< 0x00400000 */ +#define TMR_HMASK6 TMR_HMASK6_Msk +#define TMR_HMASK6_0 (0x1UL << TMR_HMASK6_Pos) /*!< 0x00400000 */ +#define TMR_HMASK5_Pos (21U) +#define TMR_HMASK5_Msk (0x1UL << TMR_HMASK5_Pos) /*!< 0x00200000 */ +#define TMR_HMASK5 TMR_HMASK5_Msk +#define TMR_HMASK5_0 (0x1UL << TMR_HMASK5_Pos) /*!< 0x00200000 */ +#define TMR_HMASK4_Pos (20U) +#define TMR_HMASK4_Msk (0x1UL << TMR_HMASK4_Pos) /*!< 0x00100000 */ +#define TMR_HMASK4 TMR_HMASK4_Msk +#define TMR_HMASK4_0 (0x1UL << TMR_HMASK4_Pos) /*!< 0x00100000 */ +#define TMR_HMASK3_Pos (19U) +#define TMR_HMASK3_Msk (0x1UL << TMR_HMASK3_Pos) /*!< 0x00080000 */ +#define TMR_HMASK3 TMR_HMASK3_Msk +#define TMR_HMASK3_0 (0x1UL << TMR_HMASK3_Pos) /*!< 0x00080000 */ +#define TMR_HMASK2_Pos (18U) +#define TMR_HMASK2_Msk (0x1UL << TMR_HMASK2_Pos) /*!< 0x00040000 */ +#define TMR_HMASK2 TMR_HMASK2_Msk +#define TMR_HMASK2_0 (0x1UL << TMR_HMASK2_Pos) /*!< 0x00040000 */ +#define TMR_HMASK1_Pos (17U) +#define TMR_HMASK1_Msk (0x1UL << TMR_HMASK1_Pos) /*!< 0x00020000 */ +#define TMR_HMASK1 TMR_HMASK1_Msk +#define TMR_HMASK1_0 (0x1UL << TMR_HMASK1_Pos) /*!< 0x00020000 */ +#define TMR_HMASK0_Pos (16U) +#define TMR_HMASK0_Msk (0x1UL << TMR_HMASK0_Pos) /*!< 0x00010000 */ +#define TMR_HMASK0 TMR_HMASK0_Msk +#define TMR_HMASK0_0 (0x1UL << TMR_HMASK0_Pos) /*!< 0x00010000 */ +#define TMR_OSTMASK_Pos (15U) +#define TMR_OSTMASK_Msk (0x1UL << TMR_OSTMASK_Pos) /*!< 0x00008000 */ +#define TMR_OSTMASK TMR_OSTMASK_Msk +#define TMR_OSTMASK_0 (0x1UL << TMR_OSTMASK_Pos) /*!< 0x00008000 */ +#define TMR_FMASK7_Pos (7U) +#define TMR_FMASK7_Msk (0x1UL << TMR_FMASK7_Pos) /*!< 0x00000080 */ +#define TMR_FMASK7 TMR_FMASK7_Msk +#define TMR_FMASK7_0 (0x1UL << TMR_FMASK7_Pos) /*!< 0x00000080 */ +#define TMR_FMASK6_Pos (6U) +#define TMR_FMASK6_Msk (0x1UL << TMR_FMASK6_Pos) /*!< 0x00000040 */ +#define TMR_FMASK6 TMR_FMASK6_Msk +#define TMR_FMASK6_0 (0x1UL << TMR_FMASK6_Pos) /*!< 0x00000040 */ +#define TMR_FMASK5_Pos (5U) +#define TMR_FMASK5_Msk (0x1UL << TMR_FMASK5_Pos) /*!< 0x00000020 */ +#define TMR_FMASK5 TMR_FMASK5_Msk +#define TMR_FMASK5_0 (0x1UL << TMR_FMASK5_Pos) /*!< 0x00000020 */ +#define TMR_FMASK4_Pos (4U) +#define TMR_FMASK4_Msk (0x1UL << TMR_FMASK4_Pos) /*!< 0x00000010 */ +#define TMR_FMASK4 TMR_FMASK4_Msk +#define TMR_FMASK4_0 (0x1UL << TMR_FMASK4_Pos) /*!< 0x00000010 */ +#define TMR_FMASK3_Pos (3U) +#define TMR_FMASK3_Msk (0x1UL << TMR_FMASK3_Pos) /*!< 0x00000008 */ +#define TMR_FMASK3 TMR_FMASK3_Msk +#define TMR_FMASK3_0 (0x1UL << TMR_FMASK3_Pos) /*!< 0x00000008 */ +#define TMR_FMASK2_Pos (2U) +#define TMR_FMASK2_Msk (0x1UL << TMR_FMASK2_Pos) /*!< 0x00000004 */ +#define TMR_FMASK2 TMR_FMASK2_Msk +#define TMR_FMASK2_0 (0x1UL << TMR_FMASK2_Pos) /*!< 0x00000004 */ +#define TMR_FMASK1_Pos (1U) +#define TMR_FMASK1_Msk (0x1UL << TMR_FMASK1_Pos) /*!< 0x00000002 */ +#define TMR_FMASK1 TMR_FMASK1_Msk +#define TMR_FMASK1_0 (0x1UL << TMR_FMASK1_Pos) /*!< 0x00000002 */ +#define TMR_FMASK0_Pos (0U) +#define TMR_FMASK0_Msk (0x1UL << TMR_FMASK0_Pos) /*!< 0x00000001 */ +#define TMR_FMASK0 TMR_FMASK0_Msk +#define TMR_FMASK0_0 (0x1UL << TMR_FMASK0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TMSR BASE+0x0034 *********/ +#define TMSR_HMSKW_Pos (24U) +#define TMSR_HMSKW_Msk (0x1UL << TMSR_HMSKW_Pos) /*!< 0x01000000 */ +#define TMSR_HMSKW TMSR_HMSKW_Msk +#define TMSR_HMSKW_0 (0x1UL << TMSR_HMSKW_Pos) /*!< 0x01000000 */ +#define TMSR_HMAK7_Pos (23U) +#define TMSR_HMAK7_Msk (0x1UL << TMSR_HMAK7_Pos) /*!< 0x00800000 */ +#define TMSR_HMAK7 TMSR_HMAK7_Msk +#define TMSR_HMAK7_0 (0x1UL << TMSR_HMAK7_Pos) /*!< 0x00800000 */ +#define TMSR_HMAK6_Pos (22U) +#define TMSR_HMAK6_Msk (0x1UL << TMSR_HMAK6_Pos) /*!< 0x00400000 */ +#define TMSR_HMAK6 TMSR_HMAK6_Msk +#define TMSR_HMAK6_0 (0x1UL << TMSR_HMAK6_Pos) /*!< 0x00400000 */ +#define TMSR_HMAK5_Pos (21U) +#define TMSR_HMAK5_Msk (0x1UL << TMSR_HMAK5_Pos) /*!< 0x00200000 */ +#define TMSR_HMAK5 TMSR_HMAK5_Msk +#define TMSR_HMAK5_0 (0x1UL << TMSR_HMAK5_Pos) /*!< 0x00200000 */ +#define TMSR_HMAK4_Pos (20U) +#define TMSR_HMAK4_Msk (0x1UL << TMSR_HMAK4_Pos) /*!< 0x00100000 */ +#define TMSR_HMAK4 TMSR_HMAK4_Msk +#define TMSR_HMAK4_0 (0x1UL << TMSR_HMAK4_Pos) /*!< 0x00100000 */ +#define TMSR_HMAK3_Pos (19U) +#define TMSR_HMAK3_Msk (0x1UL << TMSR_HMAK3_Pos) /*!< 0x00080000 */ +#define TMSR_HMAK3 TMSR_HMAK3_Msk +#define TMSR_HMAK3_0 (0x1UL << TMSR_HMAK3_Pos) /*!< 0x00080000 */ +#define TMSR_HMAK2_Pos (18U) +#define TMSR_HMAK2_Msk (0x1UL << TMSR_HMAK2_Pos) /*!< 0x00040000 */ +#define TMSR_HMAK2 TMSR_HMAK2_Msk +#define TMSR_HMAK2_0 (0x1UL << TMSR_HMAK2_Pos) /*!< 0x00040000 */ +#define TMSR_HMAK1_Pos (17U) +#define TMSR_HMAK1_Msk (0x1UL << TMSR_HMAK1_Pos) /*!< 0x00020000 */ +#define TMSR_HMAK1 TMSR_HMAK1_Msk +#define TMSR_HMAK1_0 (0x1UL << TMSR_HMAK1_Pos) /*!< 0x00020000 */ +#define TMSR_HMAK0_Pos (16U) +#define TMSR_HMAK0_Msk (0x1UL << TMSR_HMAK0_Pos) /*!< 0x00010000 */ +#define TMSR_HMAK0 TMSR_HMAK0_Msk +#define TMSR_HMAK0_0 (0x1UL << TMSR_HMAK0_Pos) /*!< 0x00010000 */ +#define TMSR_OSTMSK_Pos (15U) +#define TMSR_OSTMSK_Msk (0x1UL << TMSR_OSTMSK_Pos) /*!< 0x00008000 */ +#define TMSR_OSTMSK TMSR_OSTMSK_Msk +#define TMSR_OSTMSK_0 (0x1UL << TMSR_OSTMSK_Pos) /*!< 0x00008000 */ +#define TMSR_FMSK7_Pos (7U) +#define TMSR_FMSK7_Msk (0x1UL << TMSR_FMSK7_Pos) /*!< 0x00000080 */ +#define TMSR_FMSK7 TMSR_FMSK7_Msk +#define TMSR_FMSK7_0 (0x1UL << TMSR_FMSK7_Pos) /*!< 0x00000080 */ +#define TMSR_FMSK6_Pos (6U) +#define TMSR_FMSK6_Msk (0x1UL << TMSR_FMSK6_Pos) /*!< 0x00000040 */ +#define TMSR_FMSK6 TMSR_FMSK6_Msk +#define TMSR_FMSK6_0 (0x1UL << TMSR_FMSK6_Pos) /*!< 0x00000040 */ +#define TMSR_FMSK5_Pos (5U) +#define TMSR_FMSK5_Msk (0x1UL << TMSR_FMSK5_Pos) /*!< 0x00000020 */ +#define TMSR_FMSK5 TMSR_FMSK5_Msk +#define TMSR_FMSK5_0 (0x1UL << TMSR_FMSK5_Pos) /*!< 0x00000020 */ +#define TMSR_FMSK4_Pos (4U) +#define TMSR_FMSK4_Msk (0x1UL << TMSR_FMSK4_Pos) /*!< 0x00000010 */ +#define TMSR_FMSK4 TMSR_FMSK4_Msk +#define TMSR_FMSK4_0 (0x1UL << TMSR_FMSK4_Pos) /*!< 0x00000010 */ +#define TMSR_FMSK3_Pos (3U) +#define TMSR_FMSK3_Msk (0x1UL << TMSR_FMSK3_Pos) /*!< 0x00000008 */ +#define TMSR_FMSK3 TMSR_FMSK3_Msk +#define TMSR_FMSK3_0 (0x1UL << TMSR_FMSK3_Pos) /*!< 0x00000008 */ +#define TMSR_FMSK2_Pos (2U) +#define TMSR_FMSK2_Msk (0x1UL << TMSR_FMSK2_Pos) /*!< 0x00000004 */ +#define TMSR_FMSK2 TMSR_FMSK2_Msk +#define TMSR_FMSK2_0 (0x1UL << TMSR_FMSK2_Pos) /*!< 0x00000004 */ +#define TMSR_FMSK1_Pos (1U) +#define TMSR_FMSK1_Msk (0x1UL << TMSR_FMSK1_Pos) /*!< 0x00000002 */ +#define TMSR_FMSK1 TMSR_FMSK1_Msk +#define TMSR_FMSK1_0 (0x1UL << TMSR_FMSK1_Pos) /*!< 0x00000002 */ +#define TMSR_FMSK0_Pos (0U) +#define TMSR_FMSK0_Msk (0x1UL << TMSR_FMSK0_Pos) /*!< 0x00000001 */ +#define TMSR_FMSK0 TMSR_FMSK0_Msk +#define TMSR_FMSK0_0 (0x1UL << TMSR_FMSK0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TMCR BASE+0x0038 *********/ +#define TMCR_HMCLW_Pos (24U) +#define TMCR_HMCLW_Msk (0x1UL << TMCR_HMCLW_Pos) /*!< 0x01000000 */ +#define TMCR_HMCLW TMCR_HMCLW_Msk +#define TMCR_HMCLW_0 (0x1UL << TMCR_HMCLW_Pos) /*!< 0x01000000 */ +#define TMCR_HMCL7_Pos (23U) +#define TMCR_HMCL7_Msk (0x1UL << TMCR_HMCL7_Pos) /*!< 0x00800000 */ +#define TMCR_HMCL7 TMCR_HMCL7_Msk +#define TMCR_HMCL7_0 (0x1UL << TMCR_HMCL7_Pos) /*!< 0x00800000 */ +#define TMCR_HMCL6_Pos (22U) +#define TMCR_HMCL6_Msk (0x1UL << TMCR_HMCL6_Pos) /*!< 0x00400000 */ +#define TMCR_HMCL6 TMCR_HMCL6_Msk +#define TMCR_HMCL6_0 (0x1UL << TMCR_HMCL6_Pos) /*!< 0x00400000 */ +#define TMCR_HMCL5_Pos (21U) +#define TMCR_HMCL5_Msk (0x1UL << TMCR_HMCL5_Pos) /*!< 0x00200000 */ +#define TMCR_HMCL5 TMCR_HMCL5_Msk +#define TMCR_HMCL5_0 (0x1UL << TMCR_HMCL5_Pos) /*!< 0x00200000 */ +#define TMCR_HMCL4_Pos (20U) +#define TMCR_HMCL4_Msk (0x1UL << TMCR_HMCL4_Pos) /*!< 0x00100000 */ +#define TMCR_HMCL4 TMCR_HMCL4_Msk +#define TMCR_HMCL4_0 (0x1UL << TMCR_HMCL4_Pos) /*!< 0x00100000 */ +#define TMCR_HMCL3_Pos (19U) +#define TMCR_HMCL3_Msk (0x1UL << TMCR_HMCL3_Pos) /*!< 0x00080000 */ +#define TMCR_HMCL3 TMCR_HMCL3_Msk +#define TMCR_HMCL3_0 (0x1UL << TMCR_HMCL3_Pos) /*!< 0x00080000 */ +#define TMCR_HMCL2_Pos (18U) +#define TMCR_HMCL2_Msk (0x1UL << TMCR_HMCL2_Pos) /*!< 0x00040000 */ +#define TMCR_HMCL2 TMCR_HMCL2_Msk +#define TMCR_HMCL2_0 (0x1UL << TMCR_HMCL2_Pos) /*!< 0x00040000 */ +#define TMCR_HMCL1_Pos (17U) +#define TMCR_HMCL1_Msk (0x1UL << TMCR_HMCL1_Pos) /*!< 0x00020000 */ +#define TMCR_HMCL1 TMCR_HMCL1_Msk +#define TMCR_HMCL1_0 (0x1UL << TMCR_HMCL1_Pos) /*!< 0x00020000 */ +#define TMCR_HMCL0_Pos (16U) +#define TMCR_HMCL0_Msk (0x1UL << TMCR_HMCL0_Pos) /*!< 0x00010000 */ +#define TMCR_HMCL0 TMCR_HMCL0_Msk +#define TMCR_HMCL0_0 (0x1UL << TMCR_HMCL0_Pos) /*!< 0x00010000 */ +#define TMCR_OSTMCL_Pos (15U) +#define TMCR_OSTMCL_Msk (0x1UL << TMCR_OSTMCL_Pos) /*!< 0x00008000 */ +#define TMCR_OSTMCL TMCR_OSTMCL_Msk +#define TMCR_OSTMCL_0 (0x1UL << TMCR_OSTMCL_Pos) /*!< 0x00008000 */ +#define TMCR_FMCL7_Pos (7U) +#define TMCR_FMCL7_Msk (0x1UL << TMCR_FMCL7_Pos) /*!< 0x00000080 */ +#define TMCR_FMCL7 TMCR_FMCL7_Msk +#define TMCR_FMCL7_0 (0x1UL << TMCR_FMCL7_Pos) /*!< 0x00000080 */ +#define TMCR_FMCL6_Pos (6U) +#define TMCR_FMCL6_Msk (0x1UL << TMCR_FMCL6_Pos) /*!< 0x00000040 */ +#define TMCR_FMCL6 TMCR_FMCL6_Msk +#define TMCR_FMCL6_0 (0x1UL << TMCR_FMCL6_Pos) /*!< 0x00000040 */ +#define TMCR_FMCL5_Pos (5U) +#define TMCR_FMCL5_Msk (0x1UL << TMCR_FMCL5_Pos) /*!< 0x00000020 */ +#define TMCR_FMCL5 TMCR_FMCL5_Msk +#define TMCR_FMCL5_0 (0x1UL << TMCR_FMCL5_Pos) /*!< 0x00000020 */ +#define TMCR_FMCL4_Pos (4U) +#define TMCR_FMCL4_Msk (0x1UL << TMCR_FMCL4_Pos) /*!< 0x00000010 */ +#define TMCR_FMCL4 TMCR_FMCL4_Msk +#define TMCR_FMCL4_0 (0x1UL << TMCR_FMCL4_Pos) /*!< 0x00000010 */ +#define TMCR_FMCL3_Pos (3U) +#define TMCR_FMCL3_Msk (0x1UL << TMCR_FMCL3_Pos) /*!< 0x00000008 */ +#define TMCR_FMCL3 TMCR_FMCL3_Msk +#define TMCR_FMCL3_0 (0x1UL << TMCR_FMCL3_Pos) /*!< 0x00000008 */ +#define TMCR_FMCL2_Pos (2U) +#define TMCR_FMCL2_Msk (0x1UL << TMCR_FMCL2_Pos) /*!< 0x00000004 */ +#define TMCR_FMCL2 TMCR_FMCL2_Msk +#define TMCR_FMCL2_0 (0x1UL << TMCR_FMCL2_Pos) /*!< 0x00000004 */ +#define TMCR_FMCL1_Pos (1U) +#define TMCR_FMCL1_Msk (0x1UL << TMCR_FMCL1_Pos) /*!< 0x00000002 */ +#define TMCR_FMCL1 TMCR_FMCL1_Msk +#define TMCR_FMCL1_0 (0x1UL << TMCR_FMCL1_Pos) /*!< 0x00000002 */ +#define TMCR_FMCL0_Pos (0U) +#define TMCR_FMCL0_Msk (0x1UL << TMCR_FMCL0_Pos) /*!< 0x00000001 */ +#define TMCR_FMCL0 TMCR_FMCL0_Msk +#define TMCR_FMCL0_0 (0x1UL << TMCR_FMCL0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSCR BASE+0x003c *********/ +#define TSCR_WDTSC_Pos (16U) +#define TSCR_WDTSC_Msk (0x1UL << TSCR_WDTSC_Pos) /*!< 0x00010000 */ +#define TSCR_WDTSC TSCR_WDTSC_Msk +#define TSCR_WDTSC_0 (0x1UL << TSCR_WDTSC_Pos) /*!< 0x00010000 */ +#define TSCR_OSTSC_Pos (15U) +#define TSCR_OSTSC_Msk (0x1UL << TSCR_OSTSC_Pos) /*!< 0x00008000 */ +#define TSCR_OSTSC TSCR_OSTSC_Msk +#define TSCR_OSTSC_0 (0x1UL << TSCR_OSTSC_Pos) /*!< 0x00008000 */ +#define TSCR_STPC7_Pos (7U) +#define TSCR_STPC7_Msk (0x1UL << TSCR_STPC7_Pos) /*!< 0x00000080 */ +#define TSCR_STPC7 TSCR_STPC7_Msk +#define TSCR_STPC7_0 (0x1UL << TSCR_STPC7_Pos) /*!< 0x00000080 */ +#define TSCR_STPC6_Pos (6U) +#define TSCR_STPC6_Msk (0x1UL << TSCR_STPC6_Pos) /*!< 0x00000040 */ +#define TSCR_STPC6 TSCR_STPC6_Msk +#define TSCR_STPC6_0 (0x1UL << TSCR_STPC6_Pos) /*!< 0x00000040 */ +#define TSCR_STPC5_Pos (5U) +#define TSCR_STPC5_Msk (0x1UL << TSCR_STPC5_Pos) /*!< 0x00000020 */ +#define TSCR_STPC5 TSCR_STPC5_Msk +#define TSCR_STPC5_0 (0x1UL << TSCR_STPC5_Pos) /*!< 0x00000020 */ +#define TSCR_STPC4_Pos (4U) +#define TSCR_STPC4_Msk (0x1UL << TSCR_STPC4_Pos) /*!< 0x00000010 */ +#define TSCR_STPC4 TSCR_STPC4_Msk +#define TSCR_STPC4_0 (0x1UL << TSCR_STPC4_Pos) /*!< 0x00000010 */ +#define TSCR_STPC3_Pos (3U) +#define TSCR_STPC3_Msk (0x1UL << TSCR_STPC3_Pos) /*!< 0x00000008 */ +#define TSCR_STPC3 TSCR_STPC3_Msk +#define TSCR_STPC3_0 (0x1UL << TSCR_STPC3_Pos) /*!< 0x00000008 */ +#define TSCR_STPC2_Pos (2U) +#define TSCR_STPC2_Msk (0x1UL << TSCR_STPC2_Pos) /*!< 0x00000004 */ +#define TSCR_STPC2 TSCR_STPC2_Msk +#define TSCR_STPC2_0 (0x1UL << TSCR_STPC2_Pos) /*!< 0x00000004 */ +#define TSCR_STPC1_Pos (1U) +#define TSCR_STPC1_Msk (0x1UL << TSCR_STPC1_Pos) /*!< 0x00000002 */ +#define TSCR_STPC1 TSCR_STPC1_Msk +#define TSCR_STPC1_0 (0x1UL << TSCR_STPC1_Pos) /*!< 0x00000002 */ +#define TSCR_STPC0_Pos (0U) +#define TSCR_STPC0_Msk (0x1UL << TSCR_STPC0_Pos) /*!< 0x00000001 */ +#define TSCR_STPC0 TSCR_STPC0_Msk +#define TSCR_STPC0_0 (0x1UL << TSCR_STPC0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TDFRn BASE+0x0040+(n*0x10) *********/ +#define TDFRn_TDFR_Pos (0U) +#define TDFRn_TDFR_Msk (0xffffUL << TDFRn_TDFR_Pos) /*!< 0x0000ffff */ +#define TDFRn_TDFR TDFRn_TDFR_Msk +#define TDFRn_TDFR_0 (0x1UL << TDFRn_TDFR_Pos) /*!< 0x00000001 */ +#define TDFRn_TDFR_1 (0x2UL << TDFRn_TDFR_Pos) /*!< 0x00000002 */ +#define TDFRn_TDFR_2 (0x4UL << TDFRn_TDFR_Pos) /*!< 0x00000004 */ +#define TDFRn_TDFR_3 (0x8UL << TDFRn_TDFR_Pos) /*!< 0x00000008 */ +#define TDFRn_TDFR_4 (0x10UL << TDFRn_TDFR_Pos) /*!< 0x00000010 */ +#define TDFRn_TDFR_5 (0x20UL << TDFRn_TDFR_Pos) /*!< 0x00000020 */ +#define TDFRn_TDFR_6 (0x40UL << TDFRn_TDFR_Pos) /*!< 0x00000040 */ +#define TDFRn_TDFR_7 (0x80UL << TDFRn_TDFR_Pos) /*!< 0x00000080 */ +#define TDFRn_TDFR_8 (0x100UL << TDFRn_TDFR_Pos) /*!< 0x00000100 */ +#define TDFRn_TDFR_9 (0x200UL << TDFRn_TDFR_Pos) /*!< 0x00000200 */ +#define TDFRn_TDFR_10 (0x400UL << TDFRn_TDFR_Pos) /*!< 0x00000400 */ +#define TDFRn_TDFR_11 (0x800UL << TDFRn_TDFR_Pos) /*!< 0x00000800 */ +#define TDFRn_TDFR_12 (0x1000UL << TDFRn_TDFR_Pos) /*!< 0x00001000 */ +#define TDFRn_TDFR_13 (0x2000UL << TDFRn_TDFR_Pos) /*!< 0x00002000 */ +#define TDFRn_TDFR_14 (0x4000UL << TDFRn_TDFR_Pos) /*!< 0x00004000 */ +#define TDFRn_TDFR_15 (0x8000UL << TDFRn_TDFR_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: TDHRn BASE+0x0044+(n*0x10) *********/ +#define TDHRn_TDHR_Pos (0U) +#define TDHRn_TDHR_Msk (0xffffUL << TDHRn_TDHR_Pos) /*!< 0x0000ffff */ +#define TDHRn_TDHR TDHRn_TDHR_Msk +#define TDHRn_TDHR_0 (0x1UL << TDHRn_TDHR_Pos) /*!< 0x00000001 */ +#define TDHRn_TDHR_1 (0x2UL << TDHRn_TDHR_Pos) /*!< 0x00000002 */ +#define TDHRn_TDHR_2 (0x4UL << TDHRn_TDHR_Pos) /*!< 0x00000004 */ +#define TDHRn_TDHR_3 (0x8UL << TDHRn_TDHR_Pos) /*!< 0x00000008 */ +#define TDHRn_TDHR_4 (0x10UL << TDHRn_TDHR_Pos) /*!< 0x00000010 */ +#define TDHRn_TDHR_5 (0x20UL << TDHRn_TDHR_Pos) /*!< 0x00000020 */ +#define TDHRn_TDHR_6 (0x40UL << TDHRn_TDHR_Pos) /*!< 0x00000040 */ +#define TDHRn_TDHR_7 (0x80UL << TDHRn_TDHR_Pos) /*!< 0x00000080 */ +#define TDHRn_TDHR_8 (0x100UL << TDHRn_TDHR_Pos) /*!< 0x00000100 */ +#define TDHRn_TDHR_9 (0x200UL << TDHRn_TDHR_Pos) /*!< 0x00000200 */ +#define TDHRn_TDHR_10 (0x400UL << TDHRn_TDHR_Pos) /*!< 0x00000400 */ +#define TDHRn_TDHR_11 (0x800UL << TDHRn_TDHR_Pos) /*!< 0x00000800 */ +#define TDHRn_TDHR_12 (0x1000UL << TDHRn_TDHR_Pos) /*!< 0x00001000 */ +#define TDHRn_TDHR_13 (0x2000UL << TDHRn_TDHR_Pos) /*!< 0x00002000 */ +#define TDHRn_TDHR_14 (0x4000UL << TDHRn_TDHR_Pos) /*!< 0x00004000 */ +#define TDHRn_TDHR_15 (0x8000UL << TDHRn_TDHR_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: TCNTn BASE+0x0048+(n*0x10) *********/ +#define TCNTn_TCNT_Pos (0U) +#define TCNTn_TCNT_Msk (0xffffUL << TCNTn_TCNT_Pos) /*!< 0x0000ffff */ +#define TCNTn_TCNT TCNTn_TCNT_Msk +#define TCNTn_TCNT_0 (0x1UL << TCNTn_TCNT_Pos) /*!< 0x00000001 */ +#define TCNTn_TCNT_1 (0x2UL << TCNTn_TCNT_Pos) /*!< 0x00000002 */ +#define TCNTn_TCNT_2 (0x4UL << TCNTn_TCNT_Pos) /*!< 0x00000004 */ +#define TCNTn_TCNT_3 (0x8UL << TCNTn_TCNT_Pos) /*!< 0x00000008 */ +#define TCNTn_TCNT_4 (0x10UL << TCNTn_TCNT_Pos) /*!< 0x00000010 */ +#define TCNTn_TCNT_5 (0x20UL << TCNTn_TCNT_Pos) /*!< 0x00000020 */ +#define TCNTn_TCNT_6 (0x40UL << TCNTn_TCNT_Pos) /*!< 0x00000040 */ +#define TCNTn_TCNT_7 (0x80UL << TCNTn_TCNT_Pos) /*!< 0x00000080 */ +#define TCNTn_TCNT_8 (0x100UL << TCNTn_TCNT_Pos) /*!< 0x00000100 */ +#define TCNTn_TCNT_9 (0x200UL << TCNTn_TCNT_Pos) /*!< 0x00000200 */ +#define TCNTn_TCNT_10 (0x400UL << TCNTn_TCNT_Pos) /*!< 0x00000400 */ +#define TCNTn_TCNT_11 (0x800UL << TCNTn_TCNT_Pos) /*!< 0x00000800 */ +#define TCNTn_TCNT_12 (0x1000UL << TCNTn_TCNT_Pos) /*!< 0x00001000 */ +#define TCNTn_TCNT_13 (0x2000UL << TCNTn_TCNT_Pos) /*!< 0x00002000 */ +#define TCNTn_TCNT_14 (0x4000UL << TCNTn_TCNT_Pos) /*!< 0x00004000 */ +#define TCNTn_TCNT_15 (0x8000UL << TCNTn_TCNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: TCRn BASE+0x004c+(n*0x10) *********/ +#define TCRn_STORE_NEG_EN_Pos (26U) +#define TCRn_STORE_NEG_EN_Msk (0x1UL << TCRn_STORE_NEG_EN_Pos) /*!< 0x04000000 */ +#define TCRn_STORE_NEG_EN TCRn_STORE_NEG_EN_Msk +#define TCRn_STORE_NEG_EN_0 (0x1UL << TCRn_STORE_NEG_EN_Pos) /*!< 0x04000000 */ +#define TCRn_STORE_POS_EN_Pos (25U) +#define TCRn_STORE_POS_EN_Msk (0x1UL << TCRn_STORE_POS_EN_Pos) /*!< 0x02000000 */ +#define TCRn_STORE_POS_EN TCRn_STORE_POS_EN_Msk +#define TCRn_STORE_POS_EN_0 (0x1UL << TCRn_STORE_POS_EN_Pos) /*!< 0x02000000 */ +#define TCRn_STORE_EN_Pos (24U) +#define TCRn_STORE_EN_Msk (0x1UL << TCRn_STORE_EN_Pos) /*!< 0x01000000 */ +#define TCRn_STORE_EN TCRn_STORE_EN_Msk +#define TCRn_STORE_EN_0 (0x1UL << TCRn_STORE_EN_Pos) /*!< 0x01000000 */ +#define TCRn_COUNT_MODE_Pos (22U) +#define TCRn_COUNT_MODE_Msk (0x3UL << TCRn_COUNT_MODE_Pos) /*!< 0x00c00000 */ +#define TCRn_COUNT_MODE TCRn_COUNT_MODE_Msk +#define TCRn_COUNT_MODE_0 (0x1UL << TCRn_COUNT_MODE_Pos) /*!< 0x00400000 */ +#define TCRn_COUNT_MODE_1 (0x2UL << TCRn_COUNT_MODE_Pos) /*!< 0x00800000 */ +#define TCRn_GPIO1_NEG_EN_Pos (21U) +#define TCRn_GPIO1_NEG_EN_Msk (0x1UL << TCRn_GPIO1_NEG_EN_Pos) /*!< 0x00200000 */ +#define TCRn_GPIO1_NEG_EN TCRn_GPIO1_NEG_EN_Msk +#define TCRn_GPIO1_NEG_EN_0 (0x1UL << TCRn_GPIO1_NEG_EN_Pos) /*!< 0x00200000 */ +#define TCRn_GPIO1_POS_EN_Pos (20U) +#define TCRn_GPIO1_POS_EN_Msk (0x1UL << TCRn_GPIO1_POS_EN_Pos) /*!< 0x00100000 */ +#define TCRn_GPIO1_POS_EN TCRn_GPIO1_POS_EN_Msk +#define TCRn_GPIO1_POS_EN_0 (0x1UL << TCRn_GPIO1_POS_EN_Pos) /*!< 0x00100000 */ +#define TCRn_GPIO0_NEG_EN_Pos (19U) +#define TCRn_GPIO0_NEG_EN_Msk (0x1UL << TCRn_GPIO0_NEG_EN_Pos) /*!< 0x00080000 */ +#define TCRn_GPIO0_NEG_EN TCRn_GPIO0_NEG_EN_Msk +#define TCRn_GPIO0_NEG_EN_0 (0x1UL << TCRn_GPIO0_NEG_EN_Pos) /*!< 0x00080000 */ +#define TCRn_GPIO0_POS_EN_Pos (18U) +#define TCRn_GPIO0_POS_EN_Msk (0x1UL << TCRn_GPIO0_POS_EN_Pos) /*!< 0x00040000 */ +#define TCRn_GPIO0_POS_EN TCRn_GPIO0_POS_EN_Msk +#define TCRn_GPIO0_POS_EN_0 (0x1UL << TCRn_GPIO0_POS_EN_Pos) /*!< 0x00040000 */ +#define TCRn_CLK_NEG_EN_Pos (17U) +#define TCRn_CLK_NEG_EN_Msk (0x1UL << TCRn_CLK_NEG_EN_Pos) /*!< 0x00020000 */ +#define TCRn_CLK_NEG_EN TCRn_CLK_NEG_EN_Msk +#define TCRn_CLK_NEG_EN_0 (0x1UL << TCRn_CLK_NEG_EN_Pos) /*!< 0x00020000 */ +#define TCRn_CLK_POS_EN_Pos (16U) +#define TCRn_CLK_POS_EN_Msk (0x1UL << TCRn_CLK_POS_EN_Pos) /*!< 0x00010000 */ +#define TCRn_CLK_POS_EN TCRn_CLK_POS_EN_Msk +#define TCRn_CLK_POS_EN_0 (0x1UL << TCRn_CLK_POS_EN_Pos) /*!< 0x00010000 */ +#define TCRn_SHUTDOWN_Pos (15U) +#define TCRn_SHUTDOWN_Msk (0x1UL << TCRn_SHUTDOWN_Pos) /*!< 0x00008000 */ +#define TCRn_SHUTDOWN TCRn_SHUTDOWN_Msk +#define TCRn_SHUTDOWN_0 (0x1UL << TCRn_SHUTDOWN_Pos) /*!< 0x00008000 */ +#define TCRn_GATE_POLA_Pos (14U) +#define TCRn_GATE_POLA_Msk (0x1UL << TCRn_GATE_POLA_Pos) /*!< 0x00004000 */ +#define TCRn_GATE_POLA TCRn_GATE_POLA_Msk +#define TCRn_GATE_POLA_0 (0x1UL << TCRn_GATE_POLA_Pos) /*!< 0x00004000 */ +#define TCRn_DIRECTION_POLA_Pos (13U) +#define TCRn_DIRECTION_POLA_Msk (0x1UL << TCRn_DIRECTION_POLA_Pos) /*!< 0x00002000 */ +#define TCRn_DIRECTION_POLA TCRn_DIRECTION_POLA_Msk +#define TCRn_DIRECTION_POLA_0 (0x1UL << TCRn_DIRECTION_POLA_Pos) /*!< 0x00002000 */ +#define TCRn_GATE_SEI_Pos (11U) +#define TCRn_GATE_SEI_Msk (0x3UL << TCRn_GATE_SEI_Pos) /*!< 0x00001800 */ +#define TCRn_GATE_SEI TCRn_GATE_SEI_Msk +#define TCRn_GATE_SEI_0 (0x1UL << TCRn_GATE_SEI_Pos) /*!< 0x00000800 */ +#define TCRn_GATE_SEI_1 (0x2UL << TCRn_GATE_SEI_Pos) /*!< 0x00001000 */ +#define TCRn_DIRECTION_SEL_Pos (8U) +#define TCRn_DIRECTION_SEL_Msk (0x7UL << TCRn_DIRECTION_SEL_Pos) /*!< 0x00000700 */ +#define TCRn_DIRECTION_SEL TCRn_DIRECTION_SEL_Msk +#define TCRn_DIRECTION_SEL_0 (0x1UL << TCRn_DIRECTION_SEL_Pos) /*!< 0x00000100 */ +#define TCRn_DIRECTION_SEL_1 (0x2UL << TCRn_DIRECTION_SEL_Pos) /*!< 0x00000200 */ +#define TCRn_DIRECTION_SEL_2 (0x4UL << TCRn_DIRECTION_SEL_Pos) /*!< 0x00000400 */ +#define TCRn_GPIO1_EN_Pos (7U) +#define TCRn_GPIO1_EN_Msk (0x1UL << TCRn_GPIO1_EN_Pos) /*!< 0x00000080 */ +#define TCRn_GPIO1_EN TCRn_GPIO1_EN_Msk +#define TCRn_GPIO1_EN_0 (0x1UL << TCRn_GPIO1_EN_Pos) /*!< 0x00000080 */ +#define TCRn_GPIO0_EN_Pos (6U) +#define TCRn_GPIO0_EN_Msk (0x1UL << TCRn_GPIO0_EN_Pos) /*!< 0x00000040 */ +#define TCRn_GPIO0_EN TCRn_GPIO0_EN_Msk +#define TCRn_GPIO0_EN_0 (0x1UL << TCRn_GPIO0_EN_Pos) /*!< 0x00000040 */ +#define TCRn_PRESCALE_Pos (3U) +#define TCRn_PRESCALE_Msk (0x7UL << TCRn_PRESCALE_Pos) /*!< 0x00000038 */ +#define TCRn_PRESCALE TCRn_PRESCALE_Msk +#define TCRn_PRESCALE_0 (0x1UL << TCRn_PRESCALE_Pos) /*!< 0x00000008 */ +#define TCRn_PRESCALE_1 (0x2UL << TCRn_PRESCALE_Pos) /*!< 0x00000010 */ +#define TCRn_PRESCALE_2 (0x4UL << TCRn_PRESCALE_Pos) /*!< 0x00000020 */ +#define TCRn_EXT_EN_Pos (2U) +#define TCRn_EXT_EN_Msk (0x1UL << TCRn_EXT_EN_Pos) /*!< 0x00000004 */ +#define TCRn_EXT_EN TCRn_EXT_EN_Msk +#define TCRn_EXT_EN_0 (0x1UL << TCRn_EXT_EN_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: CAPCRn BASE+0x00c0+(n*0x4) *********/ +#define CAPCRn_CAPTURE_SEL_Pos (16U) +#define CAPCRn_CAPTURE_SEL_Msk (0x7UL << CAPCRn_CAPTURE_SEL_Pos) /*!< 0x00070000 */ +#define CAPCRn_CAPTURE_SEL CAPCRn_CAPTURE_SEL_Msk +#define CAPCRn_CAPTURE_SEL_0 (0x1UL << CAPCRn_CAPTURE_SEL_Pos) /*!< 0x00010000 */ +#define CAPCRn_CAPTURE_SEL_1 (0x2UL << CAPCRn_CAPTURE_SEL_Pos) /*!< 0x00020000 */ +#define CAPCRn_CAPTURE_SEL_2 (0x4UL << CAPCRn_CAPTURE_SEL_Pos) /*!< 0x00040000 */ +#define CAPCRn_CAPTURE_NUM_Pos (0U) +#define CAPCRn_CAPTURE_NUM_Msk (0xffUL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x000000ff */ +#define CAPCRn_CAPTURE_NUM CAPCRn_CAPTURE_NUM_Msk +#define CAPCRn_CAPTURE_NUM_0 (0x1UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000001 */ +#define CAPCRn_CAPTURE_NUM_1 (0x2UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000002 */ +#define CAPCRn_CAPTURE_NUM_2 (0x4UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000004 */ +#define CAPCRn_CAPTURE_NUM_3 (0x8UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000008 */ +#define CAPCRn_CAPTURE_NUM_4 (0x10UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000010 */ +#define CAPCRn_CAPTURE_NUM_5 (0x20UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000020 */ +#define CAPCRn_CAPTURE_NUM_6 (0x40UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000040 */ +#define CAPCRn_CAPTURE_NUM_7 (0x80UL << CAPCRn_CAPTURE_NUM_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: CAPVRn BASE+0x00E0+(n*0x4) *********/ +#define CAPVRn_CAPTURE_ALL_Pos (16U) +#define CAPVRn_CAPTURE_ALL_Msk (0xffffUL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0xffff0000 */ +#define CAPVRn_CAPTURE_ALL CAPVRn_CAPTURE_ALL_Msk +#define CAPVRn_CAPTURE_ALL_0 (0x1UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00010000 */ +#define CAPVRn_CAPTURE_ALL_1 (0x2UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00020000 */ +#define CAPVRn_CAPTURE_ALL_2 (0x4UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00040000 */ +#define CAPVRn_CAPTURE_ALL_3 (0x8UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00080000 */ +#define CAPVRn_CAPTURE_ALL_4 (0x10UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00100000 */ +#define CAPVRn_CAPTURE_ALL_5 (0x20UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00200000 */ +#define CAPVRn_CAPTURE_ALL_6 (0x40UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00400000 */ +#define CAPVRn_CAPTURE_ALL_7 (0x80UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x00800000 */ +#define CAPVRn_CAPTURE_ALL_8 (0x100UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x01000000 */ +#define CAPVRn_CAPTURE_ALL_9 (0x200UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x02000000 */ +#define CAPVRn_CAPTURE_ALL_10 (0x400UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x04000000 */ +#define CAPVRn_CAPTURE_ALL_11 (0x800UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x08000000 */ +#define CAPVRn_CAPTURE_ALL_12 (0x1000UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x10000000 */ +#define CAPVRn_CAPTURE_ALL_13 (0x2000UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x20000000 */ +#define CAPVRn_CAPTURE_ALL_14 (0x4000UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x40000000 */ +#define CAPVRn_CAPTURE_ALL_15 (0x8000UL << CAPVRn_CAPTURE_ALL_Pos) /*!< 0x80000000 */ +#define CAPVRn_CAPTURE_HEIGHT_Pos (0U) +#define CAPVRn_CAPTURE_HEIGHT_Msk (0xffffUL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x0000ffff */ +#define CAPVRn_CAPTURE_HEIGHT CAPVRn_CAPTURE_HEIGHT_Msk +#define CAPVRn_CAPTURE_HEIGHT_0 (0x1UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000001 */ +#define CAPVRn_CAPTURE_HEIGHT_1 (0x2UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000002 */ +#define CAPVRn_CAPTURE_HEIGHT_2 (0x4UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000004 */ +#define CAPVRn_CAPTURE_HEIGHT_3 (0x8UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000008 */ +#define CAPVRn_CAPTURE_HEIGHT_4 (0x10UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000010 */ +#define CAPVRn_CAPTURE_HEIGHT_5 (0x20UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000020 */ +#define CAPVRn_CAPTURE_HEIGHT_6 (0x40UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000040 */ +#define CAPVRn_CAPTURE_HEIGHT_7 (0x80UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000080 */ +#define CAPVRn_CAPTURE_HEIGHT_8 (0x100UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000100 */ +#define CAPVRn_CAPTURE_HEIGHT_9 (0x200UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000200 */ +#define CAPVRn_CAPTURE_HEIGHT_10 (0x400UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000400 */ +#define CAPVRn_CAPTURE_HEIGHT_11 (0x800UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00000800 */ +#define CAPVRn_CAPTURE_HEIGHT_12 (0x1000UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00001000 */ +#define CAPVRn_CAPTURE_HEIGHT_13 (0x2000UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00002000 */ +#define CAPVRn_CAPTURE_HEIGHT_14 (0x4000UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00004000 */ +#define CAPVRn_CAPTURE_HEIGHT_15 (0x8000UL << CAPVRn_CAPTURE_HEIGHT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: FIRVRn BASE+0x1A0+n*0x04n=0~7 *********/ +#define FIRVRn_FIL_B_Pos (16U) +#define FIRVRn_FIL_B_Msk (0x3ffUL << FIRVRn_FIL_B_Pos) /*!< 0x03ff0000 */ +#define FIRVRn_FIL_B FIRVRn_FIL_B_Msk +#define FIRVRn_FIL_B_0 (0x1UL << FIRVRn_FIL_B_Pos) /*!< 0x00010000 */ +#define FIRVRn_FIL_B_1 (0x2UL << FIRVRn_FIL_B_Pos) /*!< 0x00020000 */ +#define FIRVRn_FIL_B_2 (0x4UL << FIRVRn_FIL_B_Pos) /*!< 0x00040000 */ +#define FIRVRn_FIL_B_3 (0x8UL << FIRVRn_FIL_B_Pos) /*!< 0x00080000 */ +#define FIRVRn_FIL_B_4 (0x10UL << FIRVRn_FIL_B_Pos) /*!< 0x00100000 */ +#define FIRVRn_FIL_B_5 (0x20UL << FIRVRn_FIL_B_Pos) /*!< 0x00200000 */ +#define FIRVRn_FIL_B_6 (0x40UL << FIRVRn_FIL_B_Pos) /*!< 0x00400000 */ +#define FIRVRn_FIL_B_7 (0x80UL << FIRVRn_FIL_B_Pos) /*!< 0x00800000 */ +#define FIRVRn_FIL_B_8 (0x100UL << FIRVRn_FIL_B_Pos) /*!< 0x01000000 */ +#define FIRVRn_FIL_B_9 (0x200UL << FIRVRn_FIL_B_Pos) /*!< 0x02000000 */ +#define FIRVRn_FIL_A_Pos (0U) +#define FIRVRn_FIL_A_Msk (0x3ffUL << FIRVRn_FIL_A_Pos) /*!< 0x000003ff */ +#define FIRVRn_FIL_A FIRVRn_FIL_A_Msk +#define FIRVRn_FIL_A_0 (0x1UL << FIRVRn_FIL_A_Pos) /*!< 0x00000001 */ +#define FIRVRn_FIL_A_1 (0x2UL << FIRVRn_FIL_A_Pos) /*!< 0x00000002 */ +#define FIRVRn_FIL_A_2 (0x4UL << FIRVRn_FIL_A_Pos) /*!< 0x00000004 */ +#define FIRVRn_FIL_A_3 (0x8UL << FIRVRn_FIL_A_Pos) /*!< 0x00000008 */ +#define FIRVRn_FIL_A_4 (0x10UL << FIRVRn_FIL_A_Pos) /*!< 0x00000010 */ +#define FIRVRn_FIL_A_5 (0x20UL << FIRVRn_FIL_A_Pos) /*!< 0x00000020 */ +#define FIRVRn_FIL_A_6 (0x40UL << FIRVRn_FIL_A_Pos) /*!< 0x00000040 */ +#define FIRVRn_FIL_A_7 (0x80UL << FIRVRn_FIL_A_Pos) /*!< 0x00000080 */ +#define FIRVRn_FIL_A_8 (0x100UL << FIRVRn_FIL_A_Pos) /*!< 0x00000100 */ +#define FIRVRn_FIL_A_9 (0x200UL << FIRVRn_FIL_A_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: TSFR BASE+0x0200 *********/ +#define TSFR_SFLAG7_Pos (7U) +#define TSFR_SFLAG7_Msk (0x1UL << TSFR_SFLAG7_Pos) /*!< 0x00000080 */ +#define TSFR_SFLAG7 TSFR_SFLAG7_Msk +#define TSFR_SFLAG7_0 (0x1UL << TSFR_SFLAG7_Pos) /*!< 0x00000080 */ +#define TSFR_SFLAG6_Pos (6U) +#define TSFR_SFLAG6_Msk (0x1UL << TSFR_SFLAG6_Pos) /*!< 0x00000040 */ +#define TSFR_SFLAG6 TSFR_SFLAG6_Msk +#define TSFR_SFLAG6_0 (0x1UL << TSFR_SFLAG6_Pos) /*!< 0x00000040 */ +#define TSFR_SFLAG5_Pos (5U) +#define TSFR_SFLAG5_Msk (0x1UL << TSFR_SFLAG5_Pos) /*!< 0x00000020 */ +#define TSFR_SFLAG5 TSFR_SFLAG5_Msk +#define TSFR_SFLAG5_0 (0x1UL << TSFR_SFLAG5_Pos) /*!< 0x00000020 */ +#define TSFR_SFLAG4_Pos (4U) +#define TSFR_SFLAG4_Msk (0x1UL << TSFR_SFLAG4_Pos) /*!< 0x00000010 */ +#define TSFR_SFLAG4 TSFR_SFLAG4_Msk +#define TSFR_SFLAG4_0 (0x1UL << TSFR_SFLAG4_Pos) /*!< 0x00000010 */ +#define TSFR_SFLAG3_Pos (3U) +#define TSFR_SFLAG3_Msk (0x1UL << TSFR_SFLAG3_Pos) /*!< 0x00000008 */ +#define TSFR_SFLAG3 TSFR_SFLAG3_Msk +#define TSFR_SFLAG3_0 (0x1UL << TSFR_SFLAG3_Pos) /*!< 0x00000008 */ +#define TSFR_SFLAG2_Pos (2U) +#define TSFR_SFLAG2_Msk (0x1UL << TSFR_SFLAG2_Pos) /*!< 0x00000004 */ +#define TSFR_SFLAG2 TSFR_SFLAG2_Msk +#define TSFR_SFLAG2_0 (0x1UL << TSFR_SFLAG2_Pos) /*!< 0x00000004 */ +#define TSFR_SFLAG1_Pos (1U) +#define TSFR_SFLAG1_Msk (0x1UL << TSFR_SFLAG1_Pos) /*!< 0x00000002 */ +#define TSFR_SFLAG1 TSFR_SFLAG1_Msk +#define TSFR_SFLAG1_0 (0x1UL << TSFR_SFLAG1_Pos) /*!< 0x00000002 */ +#define TSFR_SFLAG0_Pos (0U) +#define TSFR_SFLAG0_Msk (0x1UL << TSFR_SFLAG0_Pos) /*!< 0x00000001 */ +#define TSFR_SFLAG0 TSFR_SFLAG0_Msk +#define TSFR_SFLAG0_0 (0x1UL << TSFR_SFLAG0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSFSR BASE+0x0204 *********/ +#define TSFSR_SFS7_Pos (7U) +#define TSFSR_SFS7_Msk (0x1UL << TSFSR_SFS7_Pos) /*!< 0x00000080 */ +#define TSFSR_SFS7 TSFSR_SFS7_Msk +#define TSFSR_SFS7_0 (0x1UL << TSFSR_SFS7_Pos) /*!< 0x00000080 */ +#define TSFSR_SFS6_Pos (6U) +#define TSFSR_SFS6_Msk (0x1UL << TSFSR_SFS6_Pos) /*!< 0x00000040 */ +#define TSFSR_SFS6 TSFSR_SFS6_Msk +#define TSFSR_SFS6_0 (0x1UL << TSFSR_SFS6_Pos) /*!< 0x00000040 */ +#define TSFSR_SFS5_Pos (5U) +#define TSFSR_SFS5_Msk (0x1UL << TSFSR_SFS5_Pos) /*!< 0x00000020 */ +#define TSFSR_SFS5 TSFSR_SFS5_Msk +#define TSFSR_SFS5_0 (0x1UL << TSFSR_SFS5_Pos) /*!< 0x00000020 */ +#define TSFSR_SFS4_Pos (4U) +#define TSFSR_SFS4_Msk (0x1UL << TSFSR_SFS4_Pos) /*!< 0x00000010 */ +#define TSFSR_SFS4 TSFSR_SFS4_Msk +#define TSFSR_SFS4_0 (0x1UL << TSFSR_SFS4_Pos) /*!< 0x00000010 */ +#define TSFSR_SFS3_Pos (3U) +#define TSFSR_SFS3_Msk (0x1UL << TSFSR_SFS3_Pos) /*!< 0x00000008 */ +#define TSFSR_SFS3 TSFSR_SFS3_Msk +#define TSFSR_SFS3_0 (0x1UL << TSFSR_SFS3_Pos) /*!< 0x00000008 */ +#define TSFSR_SFS2_Pos (2U) +#define TSFSR_SFS2_Msk (0x1UL << TSFSR_SFS2_Pos) /*!< 0x00000004 */ +#define TSFSR_SFS2 TSFSR_SFS2_Msk +#define TSFSR_SFS2_0 (0x1UL << TSFSR_SFS2_Pos) /*!< 0x00000004 */ +#define TSFSR_SFS1_Pos (1U) +#define TSFSR_SFS1_Msk (0x1UL << TSFSR_SFS1_Pos) /*!< 0x00000002 */ +#define TSFSR_SFS1 TSFSR_SFS1_Msk +#define TSFSR_SFS1_0 (0x1UL << TSFSR_SFS1_Pos) /*!< 0x00000002 */ +#define TSFSR_SFS0_Pos (0U) +#define TSFSR_SFS0_Msk (0x1UL << TSFSR_SFS0_Pos) /*!< 0x00000001 */ +#define TSFSR_SFS0 TSFSR_SFS0_Msk +#define TSFSR_SFS0_0 (0x1UL << TSFSR_SFS0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSFCR BASE+0x0208 *********/ +#define TSFCR_SFC7_Pos (7U) +#define TSFCR_SFC7_Msk (0x1UL << TSFCR_SFC7_Pos) /*!< 0x00000080 */ +#define TSFCR_SFC7 TSFCR_SFC7_Msk +#define TSFCR_SFC7_0 (0x1UL << TSFCR_SFC7_Pos) /*!< 0x00000080 */ +#define TSFCR_SFC6_Pos (6U) +#define TSFCR_SFC6_Msk (0x1UL << TSFCR_SFC6_Pos) /*!< 0x00000040 */ +#define TSFCR_SFC6 TSFCR_SFC6_Msk +#define TSFCR_SFC6_0 (0x1UL << TSFCR_SFC6_Pos) /*!< 0x00000040 */ +#define TSFCR_SFC5_Pos (5U) +#define TSFCR_SFC5_Msk (0x1UL << TSFCR_SFC5_Pos) /*!< 0x00000020 */ +#define TSFCR_SFC5 TSFCR_SFC5_Msk +#define TSFCR_SFC5_0 (0x1UL << TSFCR_SFC5_Pos) /*!< 0x00000020 */ +#define TSFCR_SFC4_Pos (4U) +#define TSFCR_SFC4_Msk (0x1UL << TSFCR_SFC4_Pos) /*!< 0x00000010 */ +#define TSFCR_SFC4 TSFCR_SFC4_Msk +#define TSFCR_SFC4_0 (0x1UL << TSFCR_SFC4_Pos) /*!< 0x00000010 */ +#define TSFCR_SFC3_Pos (3U) +#define TSFCR_SFC3_Msk (0x1UL << TSFCR_SFC3_Pos) /*!< 0x00000008 */ +#define TSFCR_SFC3 TSFCR_SFC3_Msk +#define TSFCR_SFC3_0 (0x1UL << TSFCR_SFC3_Pos) /*!< 0x00000008 */ +#define TSFCR_SFC2_Pos (2U) +#define TSFCR_SFC2_Msk (0x1UL << TSFCR_SFC2_Pos) /*!< 0x00000004 */ +#define TSFCR_SFC2 TSFCR_SFC2_Msk +#define TSFCR_SFC2_0 (0x1UL << TSFCR_SFC2_Pos) /*!< 0x00000004 */ +#define TSFCR_SFC1_Pos (1U) +#define TSFCR_SFC1_Msk (0x1UL << TSFCR_SFC1_Pos) /*!< 0x00000002 */ +#define TSFCR_SFC1 TSFCR_SFC1_Msk +#define TSFCR_SFC1_0 (0x1UL << TSFCR_SFC1_Pos) /*!< 0x00000002 */ +#define TSFCR_SFC0_Pos (0U) +#define TSFCR_SFC0_Msk (0x1UL << TSFCR_SFC0_Pos) /*!< 0x00000001 */ +#define TSFCR_SFC0 TSFCR_SFC0_Msk +#define TSFCR_SFC0_0 (0x1UL << TSFCR_SFC0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSMR BASE+0x0210 *********/ +#define TSMR_SMSK7_Pos (7U) +#define TSMR_SMSK7_Msk (0x1UL << TSMR_SMSK7_Pos) /*!< 0x00000080 */ +#define TSMR_SMSK7 TSMR_SMSK7_Msk +#define TSMR_SMSK7_0 (0x1UL << TSMR_SMSK7_Pos) /*!< 0x00000080 */ +#define TSMR_SMSK6_Pos (6U) +#define TSMR_SMSK6_Msk (0x1UL << TSMR_SMSK6_Pos) /*!< 0x00000040 */ +#define TSMR_SMSK6 TSMR_SMSK6_Msk +#define TSMR_SMSK6_0 (0x1UL << TSMR_SMSK6_Pos) /*!< 0x00000040 */ +#define TSMR_SMSK5_Pos (5U) +#define TSMR_SMSK5_Msk (0x1UL << TSMR_SMSK5_Pos) /*!< 0x00000020 */ +#define TSMR_SMSK5 TSMR_SMSK5_Msk +#define TSMR_SMSK5_0 (0x1UL << TSMR_SMSK5_Pos) /*!< 0x00000020 */ +#define TSMR_SMSK4_Pos (4U) +#define TSMR_SMSK4_Msk (0x1UL << TSMR_SMSK4_Pos) /*!< 0x00000010 */ +#define TSMR_SMSK4 TSMR_SMSK4_Msk +#define TSMR_SMSK4_0 (0x1UL << TSMR_SMSK4_Pos) /*!< 0x00000010 */ +#define TSMR_SMSK3_Pos (3U) +#define TSMR_SMSK3_Msk (0x1UL << TSMR_SMSK3_Pos) /*!< 0x00000008 */ +#define TSMR_SMSK3 TSMR_SMSK3_Msk +#define TSMR_SMSK3_0 (0x1UL << TSMR_SMSK3_Pos) /*!< 0x00000008 */ +#define TSMR_SMSK2_Pos (2U) +#define TSMR_SMSK2_Msk (0x1UL << TSMR_SMSK2_Pos) /*!< 0x00000004 */ +#define TSMR_SMSK2 TSMR_SMSK2_Msk +#define TSMR_SMSK2_0 (0x1UL << TSMR_SMSK2_Pos) /*!< 0x00000004 */ +#define TSMR_SMSK1_Pos (1U) +#define TSMR_SMSK1_Msk (0x1UL << TSMR_SMSK1_Pos) /*!< 0x00000002 */ +#define TSMR_SMSK1 TSMR_SMSK1_Msk +#define TSMR_SMSK1_0 (0x1UL << TSMR_SMSK1_Pos) /*!< 0x00000002 */ +#define TSMR_SMSK0_Pos (0U) +#define TSMR_SMSK0_Msk (0x1UL << TSMR_SMSK0_Pos) /*!< 0x00000001 */ +#define TSMR_SMSK0 TSMR_SMSK0_Msk +#define TSMR_SMSK0_0 (0x1UL << TSMR_SMSK0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSMSR BASE+0x0214 *********/ +#define TSMSR_SMSKS7_Pos (7U) +#define TSMSR_SMSKS7_Msk (0x1UL << TSMSR_SMSKS7_Pos) /*!< 0x00000080 */ +#define TSMSR_SMSKS7 TSMSR_SMSKS7_Msk +#define TSMSR_SMSKS7_0 (0x1UL << TSMSR_SMSKS7_Pos) /*!< 0x00000080 */ +#define TSMSR_SMSKS6_Pos (6U) +#define TSMSR_SMSKS6_Msk (0x1UL << TSMSR_SMSKS6_Pos) /*!< 0x00000040 */ +#define TSMSR_SMSKS6 TSMSR_SMSKS6_Msk +#define TSMSR_SMSKS6_0 (0x1UL << TSMSR_SMSKS6_Pos) /*!< 0x00000040 */ +#define TSMSR_SMSKS5_Pos (5U) +#define TSMSR_SMSKS5_Msk (0x1UL << TSMSR_SMSKS5_Pos) /*!< 0x00000020 */ +#define TSMSR_SMSKS5 TSMSR_SMSKS5_Msk +#define TSMSR_SMSKS5_0 (0x1UL << TSMSR_SMSKS5_Pos) /*!< 0x00000020 */ +#define TSMSR_SMSKS4_Pos (4U) +#define TSMSR_SMSKS4_Msk (0x1UL << TSMSR_SMSKS4_Pos) /*!< 0x00000010 */ +#define TSMSR_SMSKS4 TSMSR_SMSKS4_Msk +#define TSMSR_SMSKS4_0 (0x1UL << TSMSR_SMSKS4_Pos) /*!< 0x00000010 */ +#define TSMSR_SMSKS3_Pos (3U) +#define TSMSR_SMSKS3_Msk (0x1UL << TSMSR_SMSKS3_Pos) /*!< 0x00000008 */ +#define TSMSR_SMSKS3 TSMSR_SMSKS3_Msk +#define TSMSR_SMSKS3_0 (0x1UL << TSMSR_SMSKS3_Pos) /*!< 0x00000008 */ +#define TSMSR_SMSKS2_Pos (2U) +#define TSMSR_SMSKS2_Msk (0x1UL << TSMSR_SMSKS2_Pos) /*!< 0x00000004 */ +#define TSMSR_SMSKS2 TSMSR_SMSKS2_Msk +#define TSMSR_SMSKS2_0 (0x1UL << TSMSR_SMSKS2_Pos) /*!< 0x00000004 */ +#define TSMSR_SMSKS1_Pos (1U) +#define TSMSR_SMSKS1_Msk (0x1UL << TSMSR_SMSKS1_Pos) /*!< 0x00000002 */ +#define TSMSR_SMSKS1 TSMSR_SMSKS1_Msk +#define TSMSR_SMSKS1_0 (0x1UL << TSMSR_SMSKS1_Pos) /*!< 0x00000002 */ +#define TSMSR_SMSKS0_Pos (0U) +#define TSMSR_SMSKS0_Msk (0x1UL << TSMSR_SMSKS0_Pos) /*!< 0x00000001 */ +#define TSMSR_SMSKS0 TSMSR_SMSKS0_Msk +#define TSMSR_SMSKS0_0 (0x1UL << TSMSR_SMSKS0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSMCR BASE+0x0218 *********/ +#define TSMCR_SMSKC7_Pos (7U) +#define TSMCR_SMSKC7_Msk (0x1UL << TSMCR_SMSKC7_Pos) /*!< 0x00000080 */ +#define TSMCR_SMSKC7 TSMCR_SMSKC7_Msk +#define TSMCR_SMSKC7_0 (0x1UL << TSMCR_SMSKC7_Pos) /*!< 0x00000080 */ +#define TSMCR_SMSKC6_Pos (6U) +#define TSMCR_SMSKC6_Msk (0x1UL << TSMCR_SMSKC6_Pos) /*!< 0x00000040 */ +#define TSMCR_SMSKC6 TSMCR_SMSKC6_Msk +#define TSMCR_SMSKC6_0 (0x1UL << TSMCR_SMSKC6_Pos) /*!< 0x00000040 */ +#define TSMCR_SMSKC5_Pos (5U) +#define TSMCR_SMSKC5_Msk (0x1UL << TSMCR_SMSKC5_Pos) /*!< 0x00000020 */ +#define TSMCR_SMSKC5 TSMCR_SMSKC5_Msk +#define TSMCR_SMSKC5_0 (0x1UL << TSMCR_SMSKC5_Pos) /*!< 0x00000020 */ +#define TSMCR_SMSKC4_Pos (4U) +#define TSMCR_SMSKC4_Msk (0x1UL << TSMCR_SMSKC4_Pos) /*!< 0x00000010 */ +#define TSMCR_SMSKC4 TSMCR_SMSKC4_Msk +#define TSMCR_SMSKC4_0 (0x1UL << TSMCR_SMSKC4_Pos) /*!< 0x00000010 */ +#define TSMCR_SMSKC3_Pos (3U) +#define TSMCR_SMSKC3_Msk (0x1UL << TSMCR_SMSKC3_Pos) /*!< 0x00000008 */ +#define TSMCR_SMSKC3 TSMCR_SMSKC3_Msk +#define TSMCR_SMSKC3_0 (0x1UL << TSMCR_SMSKC3_Pos) /*!< 0x00000008 */ +#define TSMCR_SMSKC2_Pos (2U) +#define TSMCR_SMSKC2_Msk (0x1UL << TSMCR_SMSKC2_Pos) /*!< 0x00000004 */ +#define TSMCR_SMSKC2 TSMCR_SMSKC2_Msk +#define TSMCR_SMSKC2_0 (0x1UL << TSMCR_SMSKC2_Pos) /*!< 0x00000004 */ +#define TSMCR_SMSKC1_Pos (1U) +#define TSMCR_SMSKC1_Msk (0x1UL << TSMCR_SMSKC1_Pos) /*!< 0x00000002 */ +#define TSMCR_SMSKC1 TSMCR_SMSKC1_Msk +#define TSMCR_SMSKC1_0 (0x1UL << TSMCR_SMSKC1_Pos) /*!< 0x00000002 */ +#define TSMCR_SMSKC0_Pos (0U) +#define TSMCR_SMSKC0_Msk (0x1UL << TSMCR_SMSKC0_Pos) /*!< 0x00000001 */ +#define TSMCR_SMSKC0 TSMCR_SMSKC0_Msk +#define TSMCR_SMSKC0_0 (0x1UL << TSMCR_SMSKC0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TSVRn BASE+0x0220+(n*0x4) *********/ +#define TSVRn_STR_VALUE_Pos (0U) +#define TSVRn_STR_VALUE_Msk (0xffffUL << TSVRn_STR_VALUE_Pos) /*!< 0x0000ffff */ +#define TSVRn_STR_VALUE TSVRn_STR_VALUE_Msk +#define TSVRn_STR_VALUE_0 (0x1UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000001 */ +#define TSVRn_STR_VALUE_1 (0x2UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000002 */ +#define TSVRn_STR_VALUE_2 (0x4UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000004 */ +#define TSVRn_STR_VALUE_3 (0x8UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000008 */ +#define TSVRn_STR_VALUE_4 (0x10UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000010 */ +#define TSVRn_STR_VALUE_5 (0x20UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000020 */ +#define TSVRn_STR_VALUE_6 (0x40UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000040 */ +#define TSVRn_STR_VALUE_7 (0x80UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000080 */ +#define TSVRn_STR_VALUE_8 (0x100UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000100 */ +#define TSVRn_STR_VALUE_9 (0x200UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000200 */ +#define TSVRn_STR_VALUE_10 (0x400UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000400 */ +#define TSVRn_STR_VALUE_11 (0x800UL << TSVRn_STR_VALUE_Pos) /*!< 0x00000800 */ +#define TSVRn_STR_VALUE_12 (0x1000UL << TSVRn_STR_VALUE_Pos) /*!< 0x00001000 */ +#define TSVRn_STR_VALUE_13 (0x2000UL << TSVRn_STR_VALUE_Pos) /*!< 0x00002000 */ +#define TSVRn_STR_VALUE_14 (0x4000UL << TSVRn_STR_VALUE_Pos) /*!< 0x00004000 */ +#define TSVRn_STR_VALUE_15 (0x8000UL << TSVRn_STR_VALUE_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: TSFVRn BASE+0x0240+(n*0x4) *********/ +#define TSFVRn_STR_FIL_Pos (0U) +#define TSFVRn_STR_FIL_Msk (0x3ffUL << TSFVRn_STR_FIL_Pos) /*!< 0x000003ff */ +#define TSFVRn_STR_FIL TSFVRn_STR_FIL_Msk +#define TSFVRn_STR_FIL_0 (0x1UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000001 */ +#define TSFVRn_STR_FIL_1 (0x2UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000002 */ +#define TSFVRn_STR_FIL_2 (0x4UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000004 */ +#define TSFVRn_STR_FIL_3 (0x8UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000008 */ +#define TSFVRn_STR_FIL_4 (0x10UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000010 */ +#define TSFVRn_STR_FIL_5 (0x20UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000020 */ +#define TSFVRn_STR_FIL_6 (0x40UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000040 */ +#define TSFVRn_STR_FIL_7 (0x80UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000080 */ +#define TSFVRn_STR_FIL_8 (0x100UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000100 */ +#define TSFVRn_STR_FIL_9 (0x200UL << TSFVRn_STR_FIL_Pos) /*!< 0x00000200 */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus*/ +#endif /* __REG_TCU_H__ */ diff --git a/cpu/soc-x2600/include/x2600.h b/cpu/soc-x2600/include/x2600.h index ef0573c9c197b275f01253a9643c2263df0f185c..0d0beb3bfca6f3fd4c9317428304e831a45b939a 100755 --- a/cpu/soc-x2600/include/x2600.h +++ b/cpu/soc-x2600/include/x2600.h @@ -37,6 +37,7 @@ #include "uart.h" #include "interrupt.h" #include "pwm.h" +#include "tcu.h" #ifdef __cplusplus extern "C" { @@ -64,6 +65,8 @@ extern "C" { #define DMA_BASE 0x13420000 /*!< PDMA register base. */ #define MCU_DMA_BASE 0x13660000 /*!< Address base of MCU_DMA*/ #define RISC_CCU_BASE 0x12A00000 /*!< RiscV CCU base address */ +#define TCU0_BASE 0x13630000 /*!< Address base of TCU0 */ +#define TCU1_BASE 0x13640000 /*!< Address base of TCU1 */ #define SADC_BASE 0x13650000 /*!< Address base of SADC */ #define SFC_BASE 0x13440000 /*!< SPI Flash Controller */ #define SSI0_BASE 0x10043000 /*!< The SSI0's registers map base address */ @@ -103,7 +106,8 @@ extern "C" { #define MCU_DMA_Instance ((PDMA_TypeDef *) (MCU_DMA_BASE )) #define RISC_CCU_Instance ((RISCV_CCU_TypeDef *) (RISC_CCU_BASE)) #define SADC_Instance ((SADC_TypeDef *) (SADC_BASE)) - +#define TCU0_Instance ((TCU_TypeDef *) (TCU0_BASE)) +#define TCU1_Instance ((TCU_TypeDef *) (TCU1_BASE)) #define SFC_Instance ((SFC_TypeDef *) (SFC_BASE )) #define SSI0_Instance ((SSI_TypeDef *) (SSI0_BASE )) diff --git a/drivers/drivers-x2600/include/x2600_hal_conf.h b/drivers/drivers-x2600/include/x2600_hal_conf.h index aa9d4f562aefd8b146a7dd5f76c685a20c38c87d..8df87855991408b3ccb2382cd1549e4fdfdc3c2e 100644 --- a/drivers/drivers-x2600/include/x2600_hal_conf.h +++ b/drivers/drivers-x2600/include/x2600_hal_conf.h @@ -13,11 +13,11 @@ #define HAL_ADC_ENABLED #define HAL_I2C_ENABLED #define HAL_PWM_ENABLED +#define HAL_TCU_ENABLED #if 0 #define HAL_MSC_ENABLED #define HAL_SPI_ENABLED #define HAL_WDT_ENABLED -#define HAL_TCU_ENABLED #define HAL_RTC_ENABLED #define HAL_EFUSE_ENABLED #define HAL_GMAC_ENABLED diff --git a/drivers/drivers-x2600/include/x2600_hal_pdma.h b/drivers/drivers-x2600/include/x2600_hal_pdma.h index d9c6602c29973fdc7b125bc9105b403b0aed8be9..68ebe285c5ea1289005e12e3cc0f78b957c7fc3b 100755 --- a/drivers/drivers-x2600/include/x2600_hal_pdma.h +++ b/drivers/drivers-x2600/include/x2600_hal_pdma.h @@ -112,10 +112,10 @@ typedef enum { typedef enum{ DMA_RQ_SEQ1_TX =0x0, DMA_RQ_SEQ2_TX =0x1, - DMA_RQ_TCP_SHIFT_TX =0x2, - DMA_RQ_TCP_DEST_TX =0x3, - DMA_RQ_TCP_STEP0_TX =0x4, - DMA_RQ_TCP_STEP1_TX =0x5, + DMA_RQ_TPC_SHIFT_TX =0x2, + DMA_RQ_TPC_DEST_TX =0x3, + DMA_RQ_TPC_STEP0_TX =0x4, + DMA_RQ_TPC_STEP1_TX =0x5, DMA_RQ_PWM0_TX =0x2c, DMA_RQ_PWM1_TX =0x2d, DMA_RQ_PWM2_TX =0x2e, diff --git a/drivers/drivers-x2600/include/x2600_hal_tcu.h b/drivers/drivers-x2600/include/x2600_hal_tcu.h new file mode 100644 index 0000000000000000000000000000000000000000..426001a4080feaed9d33ed42b7e3efc35455e063 --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_hal_tcu.h @@ -0,0 +1,389 @@ +/** + * @file x2600_hal_tcu.h + * @author MPU系统软件部团队 + * @brief TCU HAl层驱动头文件 + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __X2600_HAL_TCU_H__ +#define __X2600_HAL_TCU_H__ + + +/** + * @addtogroup group_TCU + * @{ + */ + +/** + * @addtogroup g_X2600_TCU_HAL_Driver TCU HAL 驱动 + * @{ + */ + +/* 头文件 (Includes)----------------------------------------------- */ +#include "x2600_hal_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* 导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup TCU_exported_types TCU 导出类型 (Exported Types) + * @{ + */ + +/** +* @brief TCU 初始化结构体 +*/ +typedef struct { + uint32_t Channel; /*!< TCU 通道 */ + uint32_t Prescaler; /*!< TCU时钟分频比 */ + uint16_t Tdfr; /*!< TCU计数满值，用于跟Tcnt比较*/ + uint16_t Tdhr; /*!< TCU计数半满值，用于跟Tcnt比*/ + uint16_t Tcnt; /*!< TCU向上增加计数值*/ + +} TCU_InitTypeDef; + +/** +* @brief TCU 句柄结构体 +*/ +typedef struct __TCU_HandleTypeDef { + TCU_TypeDef *Instance; /*!< TCU 寄存器基地址 */ + TCU_InitTypeDef Init; /*!< TCU 初始化结构体 */ + HAL_StatusTypeDef State; /*!< HAL状态结构体 */ +} TCU_HandleTypeDef; +/** + * @} + */ + +/* 导出常量定义 Exported Constants ----------------------------------- */ +/** + * @defgroup TCU_exported_constants TCU 导出常量 (Exported Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 导出宏定义 Exported Macros --------------------------------------- */ +/** + * @defgroup TCU_exported_macros TCU 导出宏 (Exported Macros) + * @{ + */ +#define TCU_PRESCALE_DIV1 0 /*!< TCU时钟1分频 */ +#define TCU_PRESCALE_DIV4 1 /*!< TCU时钟4分频 */ +#define TCU_PRESCALE_DIV16 2 /*!< TCU时钟16分频 */ +#define TCU_PRESCALE_DIV64 3 /*!< TCU时钟64分频 */ +#define TCU_PRESCALE_DIV256 4 /*!< TCU时钟256分频 */ +#define TCU_PRESCALE_DIV1024 5 /*!< TCU时钟1024分频 */ +//!选择时钟源为内部时钟或gpio输入时钟 +#define SEL_INNER_CLOCK 0 /*!< TCU选择内部时钟>*/ +#define SEL_INPUT_GPIO0 1 /*!< TCU选择输入时钟gpio0>*/ +#define SEL_INPUT_GPIO1 2 /*!< TCU选择输入时钟gpop1>*/ +//!使能时钟或关闭时钟 +#define CLK_ON 1 /*!< 使能时钟源>*/ +#define CLK_OFF 0 /*!< 关闭时钟源>*/ +//!上升沿触发或下降沿触发 +#define EDGE_POS 0 /*!< 上升沿触发>*/ +#define EDGE_NEG 1 /*!< 下降沿触发>*/ +//!低电平触发或高电平沿触发 +#define GATE_HIGH 0 /*!< 高电平触发>*/ +#define GATE_LOW 1 /*!< 低电平触发>*/ +//!gate信号的来源 +#define NOR_GATE 0 /*!< gate 信号保持为0>*/ +#define INNER_GATE 1 /*!< 使用内部时钟作为gate信号>*/ +#define GPIO0_GATE 2 /*!< 使用gpio0输入时钟作为gate信号>*/ +#define GPIO1_GATE 3 /*!< 使用gpio1输入时钟作为gate信号>*/ +//!计数器的工作信号 +#define POLA_LOW 0 /*!< 计数器工作在gate信号为的低电平期间>*/ +#define POLA_HIGH 1 /*!< 计数器工作在gate信号为的高电平期间>*/ +//!direction信号的来源 +#define NOR_DIR 0 /*!< diretion信号保持为1>*/ +#define INNER_DIR 1 /*!< 使用内部时钟作为diretion信号>*/ +#define GPIO0_DIR 2 /*!< 使用gpio0输入时钟作为diretion信号>*/ +#define GPIO1_DIR 3 /*!< 使用gpio1输入时钟作为diretion信号>*/ +#define GPIO0_AND_GPIO1 4 /*!< 使用gpio0和gpio1输入时钟作为diretion信号>*/ +//!使能或禁止store功能 +#define STORE_DIS 0 /*!< 禁用store功能>*/ +#define STORE_EN 1 /*!< 使能store功能>*/ +//!store触发的边沿 +#define STORE_POS 0 /*!< 上升沿触发>*/ +#define STORE_NEG 1 /*!< 下降沿触发>*/ + +//!设置TCU使能寄存器 +#define __HAL_TCU_SET_ENABLE(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TESR)=(1 << __CHAN__) +//!清除TCU使能寄存器 +#define __HAL_TCU_CLEAR_ENABLE(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TECR)=(1 << __CHAN__) +//!设置TCU停止寄存器 +#define __HAL_TCU_SET_STOP(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TSSR)=(1 << __CHAN__) +//!清除TCU停止寄存器 +#define __HAL_TCU_CLEAR_STOP(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TSCR)=(1 << __CHAN__) +//!设置TCU半满标志位 +#define __HAL_TCU_SET_HALF_FLAG(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TFSR)=(1 << (__CHAN__+16)) +//!清除TCU半满标志位 +#define __HAL_TCU_CLEAR_HALF_FLAG(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TFCR)=(1 << (__CHAN__+16)) +//!设置TCU全满标志位 +#define __HAL_TCU_SET_FULL_FLAG(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TFSR)=(1 << __CHAN__) +//!清除TCU全满标志位 +#define __HAL_TCU_CLEAR_FULL_FLAG(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TFCR)=(1 << __CHAN__) +//!设置TCU半满掩码 +#define __HAL_TCU_SET_HALF_MASK(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TMSR)=(1 << (__CHAN__+16)) +//!清除TCU半满掩码 +#define __HAL_TCU_CLEAR_HALF_MASK(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TMCR)=(1 << (__CHAN__+16)) +//!设置TCU全满掩码 +#define __HAL_TCU_SET_FULL_MASK(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TMSR)=(1 << __CHAN__) +//!清除TCU全满掩码 +#define __HAL_TCU_CLEAR_FULL_MASK(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->TMCR)=(1 << __CHAN__) + +//!读取TCU是否使能 +#define __HAL_TCU_IS_ENABLE(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TER) & (1 << __CHAN__)) +//!读取TCU是否停止 +#define __HAL_TCU_IS_STOP(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TSR) & (1 << __CHAN__)) +//!读取TCU半满标志是否置位 +#define __HAL_TCU_IS_HALF_FLAG(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TFR) & (1 << (__CHAN__+16))) +//!读取TCU全满标志是否置位 +#define __HAL_TCU_IS_FULL_FLAG(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TFR) & (1 << __CHAN__)) +//! +//!读取TCU半满是否置位 +#define __HAL_TCU_IS_HALF_MASK(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TMR) & (1 << (__CHAN__+16))) +//! +//!读取TCU全满掩码是否置位 +#define __HAL_TCU_IS_FULL_MASK(__HANDLE__, __CHAN__) (((__HANDLE__)->Instance->TMR) & (1 << __CHAN__)) +//!读取TCU标志寄存器 +#define __HAL_TCU_GET_FLAG(__HANDLE__) ((__HANDLE__)->Instance->TFR) +//!读取TCU掩码寄存器 +#define __HAL_TCU_GET_MASK(__HANDLE__) ((__HANDLE__)->Instance->TMR) + +//!设置TCU半满计数值 +#define __HAL_TCU_SET_DATA_FULL(__HANDLE__, __CHAN__, __DATA__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TDFRn)=(__DATA__) +//!设置TCU全满计数值 +#define __HAL_TCU_SET_DATA_HALF(__HANDLE__, __CHAN__, __DATA__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TDHRn)=(__DATA__) +//!设置TCU计数寄存器的值 +#define __HAL_TCU_SET_TCNT(__HANDLE__, __CHAN__, __DATA__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TCNTn)=(__DATA__) +//!读取TCU全满寄存器计数值 +#define __HAL_TCU_GET_DATA_FULL(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TDFRn) +//!读取TCU半满寄存器计数值 +#define __HAL_TCU_GET_DATA_HALF(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TDHRn) +//!读取TCU计数寄存器的值 +#define __HAL_TCU_GET_TCNT(__HANDLE__, __CHAN__) ((__HANDLE__)->Instance->CHAN[__CHAN__].TCNTn) + +//!设置TCU时钟分频的分频比 +#define __HAL_TCU_SET_PRESCALE(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_PRESCALE_Msk, (__DATA__ << TCRn_PRESCALE_Pos)) +//!设置使用外部时钟做为TCU时钟源 +#define __HAL_TCU_SET_EXT_ENABLE(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_EXT_EN_Msk, (1<< TCRn_EXT_EN_Pos)) +//!设置不使用外部时钟做为TCU时钟源 +#define __HAL_TCU_SET_EXT_DISABLE(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_EXT_EN_Msk, (0<< TCRn_EXT_EN_Pos)) +//!设置TCU在时钟下降沿开始计数 +#define __HAL_TCU_SET_CLK_NEG(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_CLK_NEG_EN_Msk, (1<< TCRn_CLK_NEG_EN_Pos)) +//!设置TCU在时钟上升沿开始计数 +#define __HAL_TCU_SET_CLK_POS(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_CLK_POS_EN_Msk, (1<< TCRn_CLK_POS_EN_Pos)) +//!清除TCU在时钟下降沿开始计数 +#define __HAL_TCU_CLEAR_CLK_NEG(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_CLK_NEG_EN_Msk, (0<< TCRn_CLK_NEG_EN_Pos)) +//!清除TCU在时钟上升沿开始计数 +#define __HAL_TCU_CLEAR_CLK_POS(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_CLK_POS_EN_Msk, (0<< TCRn_CLK_POS_EN_Pos)) + +//!设置TCU的输入时钟 +#define __HAL_TCU_SELECT_CLK(__HANDLE__, __CHAN__, __MSK__, __POS__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (__DATA__ << __POS__)) + +//!设置TCU在时钟边沿开始计数 +#define __HAL_TCU_SET_CLK_EDGE(__HANDLE__, __CHAN__, __MSK__, __POS__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (1<< __POS__)) + +//!清除TCU在时钟边沿开始计数 +#define __HAL_TCU_CLEAR_CLK_EDGE(__HANDLE__, __CHAN__, __MSK__, __POS__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (0<< __POS__)) + +//!设置TCU在时钟水平模式开始计数 +#define __HAL_TCU_SET_CLK_GATE(__HANDLE__, __CHAN__, __MSK__, __POS__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (1<< __POS__)) + +//!清除TCU在时钟边沿开始计数 +#define __HAL_TCU_CLEAR_CLK_GATE(__HANDLE__, __CHAN__, __MSK__, __POS__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (0<< __POS__)) + +//!设置TCU的gate信号输入源 +#define __HAL_TCU_SEL_GATE_CLK(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_GATE_SEI_Msk, (__DATA__ << TCRn_GATE_SEI_Pos)) + +//!设置TCU的GATE_POLA位，设置计数器的工作电平 +#define __HAL_TCU_SEL_POLA(__HANDLE__, __CHAN__, __MSK__, __POS__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (__DATA__ << __POS__)) + +//!设置TCU的direction信号输入源 +#define __HAL_TCU_SEL_DIR_CLK(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_DIRECTION_SEL_Msk, (__DATA__ << TCRn_DIRECTION_SEL_Pos)) + +//!设置TCU的CAPTURE_NUM的值 +#define __HAL_TCU_SET_CAP_NUM(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CAPCRn[__CHAN__], CAPCRn_CAPTURE_NUM_Msk, (__DATA__ << CAPCRn_CAPTURE_NUM_Pos)) + +//!获取CAPCRN寄存器的值 +#define __HAL_TCU_GET_CAPCRN(__HANDLE__, __CHAN__) (READ_REG((__HANDLE__)->Instance->CAPCRn[__CHAN__])) + +//!设置TCU要CAPTURE的时钟 +#define __HAL_TCU_SEL_CAP_CLK(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CAPCRn[__CHAN__], CAPCRn_CAPTURE_SEL_Msk, (__DATA__ << CAPCRn_CAPTURE_SEL_Pos)) + +//!获取整个CAPTURE期间的时间 +#define __HAL_TCU_GET_CAP_ALL(__HANDLE__, __CHAN__) ((READ_REG((__HANDLE__)->Instance->CAPVR4) & CAPVRn_CAPTURE_ALL_Msk) >> CAPVRn_CAPTURE_ALL_Pos) + +//!获取CAPTURE期间高电平的时间 +#define __HAL_TCU_GET_CAP_HEIGHT(__HANDLE__, __CHAN__) (READ_REG((__HANDLE__)->Instance->CAPVR##__CHAN__ ) & CAPVRn_CAPTURE_HEIGHT_Msk) + +//!设置filter寄存器的值 +#define __HAL_TCU_SET_FILRVR(__HANDLE__, __CHAN__, __MSK__, __POS__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->FIRVRn[__CHAN__], __MSK__, (__DATA__ << __POS__)) + +//!使能TCU的store功能 +#define __HAL_TCU_SET_STORE(__HANDLE__, __CHAN__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, TCRn_STORE_EN_Msk, (__DATA__ << TCRn_STORE_EN_Pos)) + +//!设置TCU的store功能的触发边沿 +#define __HAL_TCU_SET_STORE_EDGE(__HANDLE__, __CHAN__, __MSK__, __POS__, __DATA__) MODIFY_REG((__HANDLE__)->Instance->CHAN[__CHAN__].TCRn, __MSK__, (__DATA__ << __POS__)) + +//!清除TCU的store功能的中断 +#define __HAL_TCU_CLEAR_STORE_INTERRUPT(__HANDLE__, __CHAN__) MODIFY_REG((__HANDLE__)->Instance->TSMCR, (1 << __CHAN__) , (1 << __CHAN__)) + +//!获取TSVR寄存器的值 +#define __HAL_TCU_GET_TSVR(__HANDLE__, __CHAN__) (READ_REG((__HANDLE__)->Instance->TSVRn[__CHAN__]) & TSVRn_STR_VALUE_Msk) + + +/** + * @} + */ +/* 导出函数申明 Exported Funcs --------------------------------------- */ +/** + * @defgroup TCU_exported_funcs TCU 导出函数申明 (Exported Funcs) + * @{ + */ + +HAL_StatusTypeDef HAL_TCU_Base_Init(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_DeInit(TCU_HandleTypeDef *htcu); +void HAL_TCU_Base_MspInit(TCU_HandleTypeDef *htcu); +void HAL_TCU_Base_MspDeInit(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_Start(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_Stop(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_Start_HALF_IT(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_Start_FULL_IT(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_Base_Stop_IT(TCU_HandleTypeDef *htcu); +void HAL_TCU_IRQHandler(int irq, void *data); +void HAL_TCU_HALF_Callback(TCU_HandleTypeDef *htcu); +void HAL_TCU_FULL_Callback(TCU_HandleTypeDef *htcu); +int HAL_TCU_GET_TCNT(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_SET_CLOCK(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int status); +HAL_StatusTypeDef HAL_TCU_SET_EDGE_MODE(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int data); +HAL_StatusTypeDef HAL_TCU_SEL_GATE_SRC(TCU_HandleTypeDef *htcu, unsigned int clk); +HAL_StatusTypeDef HAL_TCU_SET_GATE_POLA(TCU_HandleTypeDef *htcu, unsigned int data); +HAL_StatusTypeDef HAL_TCU_SEL_DIR_SRC(TCU_HandleTypeDef *htcu, unsigned int clk); +HAL_StatusTypeDef HAL_TCU_SET_DIR_POLA(TCU_HandleTypeDef *htcu, unsigned int data); +int HAL_TCU_GET_CAPCRN(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_SET_CAP_NUM(TCU_HandleTypeDef *htcu, unsigned int data); +HAL_StatusTypeDef HAL_TCU_SEL_CAP_CLK(TCU_HandleTypeDef *htcu, unsigned int clk); +int HAL_TCU_GET_CAP_ALL(TCU_HandleTypeDef *htcu); +int HAL_TCU_GET_CAP_HEIGHT(TCU_HandleTypeDef *htcu); +HAL_StatusTypeDef HAL_TCU_SET_FIRVR(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int data); +HAL_StatusTypeDef HAL_TCU_SET_STORE(TCU_HandleTypeDef *htcu, unsigned int status); +HAL_StatusTypeDef HAL_TCU_SET_STORE_EDGE(TCU_HandleTypeDef *htcu, unsigned int edge); +HAL_StatusTypeDef HAL_TCU_CLEAR_STORE_INTERRUPT(TCU_HandleTypeDef *htcu); +int HAL_TCU_GET_TSVR(TCU_HandleTypeDef *htcu); + +/** + * @} + */ +/* 导出变量申明 (Exported Variables) --------------------------------- */ +/** + * @defgroup TCU_exported_var TCU 导出变量申明 (Exported Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @defgroup TCU_private_types TCU 私有类型定义 (Private Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 私有常量定义Private Constants ------------------------------------- */ +/** + * @defgroup TCU_private_constants TCU 私有常量定义 (Private Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @defgroup TCU_private_macros TCU 私有宏定义 (Private Macros) + * @{ + */ + +/*! 判断TCU基地址是否有效 */ +#define IS_TCU_INSTANCE(INSTANCE) ((INSTANCE) == TCU1_Instance || (INSTANCE) == TCU0_Instance) + +/*! 判断TCU时钟分频比是否有效*/ +#define IS_TCU_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TCU_PRESCALE_DIV1) || \ + ((__PRESCALER__) == TCU_PRESCALE_DIV4) || \ + ((__PRESCALER__) == TCU_PRESCALE_DIV16) || \ + ((__PRESCALER__) == TCU_PRESCALE_DIV64) || \ + ((__PRESCALER__) == TCU_PRESCALE_DIV256) || \ + ((__PRESCALER__) == TCU_PRESCALE_DIV1024)) + +/*! 判断TCU计数半满值是否有效*/ +#define IS_TCU_TDHR(__DATA__) (((__DATA__) > 0) || ((__DATA__) < 0xffff)) +/*! 判断TCU计数全满值是否有效 */ +#define IS_TCU_TDFR(__DATA__) (((__DATA__) > 0) || ((__DATA__) < 0xffff)) +/*! 判断TCU计数值是否有效*/ +#define IS_TCU_TCNT(__DATA__) (((__DATA__) > 0) || ((__DATA__) < 0xffff)) +/*! 判断TCU通道是否有效*/ +#define IS_TCU_CHANNEL(__CHAN__) (((__CHAN__) >= 0) || ((__CHAN__) < 8)) + + +/** + * @} + */ +/* 私有函数申明 (Private Funcs) ------------------------------------- */ +/** + * @defgroup TCU_private_funcs TCU 私有函数申明 (Private Funcs) + * @{ + */ + +/** + * @} + */ +/* 11. 私有变量申明 (Private Variables) ----------------------------- */ +/** + * @defgroup TCU_private_var TCU 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X16XX_HAL_TCU_H__ */ diff --git a/drivers/drivers-x2600/include/x2600_ll_tcu.h b/drivers/drivers-x2600/include/x2600_ll_tcu.h new file mode 100644 index 0000000000000000000000000000000000000000..cd11614c668bcca26854e0ee856fd060e07e5266 --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_ll_tcu.h @@ -0,0 +1,192 @@ +/** + * @file x2600_ll_tcu.h + * @author MPU系统软件部团队 + * @brief x2600_ll_tcu.c的头文件 + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* template lowlevel source files. */ +#ifndef __X2600_LL_TCU_H__ +#define __X2600_LL_TCU_H__ + + +/** + * @addtogroup group_TCU + * @{ + */ + +/** + * @addtogroup g_X2600_TCU_LL_Driver TCU LL 驱动 + * @{ + */ + +/* 头文件 (Includes) ----------------------------------------------- */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t Channel; + uint32_t Prescaler; + uint16_t Tdfr; + uint16_t Tdhr; + uint16_t Tcnt; +} LL_TCU_InitTypeDef; + +/* 私有函数实现 (Private Funcs) ------------------------------------- */ +/** + * @defgroup TCU_private_funcs_impl TCU 私有函数实现 (Private Funcs) + * @{ + */ +static inline void LL_TCU_SET_ENABLE(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TESR, 1 << Channel); +} + +static inline void LL_TCU_CLEAR_ENABLE(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TECR, 1 << Channel); +} + +static inline void LL_TCU_SET_STOP(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TSSR, 1 << Channel); +} + +static inline void LL_TCU_CLEAR_STOP(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TSCR, 1 << Channel); +} + +static inline void LL_TCU_SET_HALF_FLAG(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TFSR, 1 << (Channel + 16)); +} + +static inline void LL_TCU_CLEAR_HALF_FLAG(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TFCR, 1 << (Channel + 16)); +} + +static inline void LL_TCU_SET_FULL_FLAG(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TFSR, 1 << Channel); +} + +static inline void LL_TCU_CLEAR_FULL_FLAG(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TFCR, 1 << Channel); +} + +static inline void LL_TCU_SET_HALF_MASK(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TMSR, 1 << (Channel + 16)); +} + +static inline void LL_TCU_CLEAR_HALF_MASK(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TMCR, 1 << (Channel + 16)); +} + +static inline void LL_TCU_SET_FULL_MASK(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TMSR, 1 << Channel); +} + +static inline void LL_TCU_CLEAR_FULL_MASK(TCU_TypeDef *TCUx, uint32_t Channel) +{ + SET_BIT(TCUx->TMCR, 1 << Channel); +} + + +static inline void LL_TCU_CLEAR_WDT_FLAG(TCU_TypeDef *TCUx) +{ + SET_BIT(TCUx->TFCR, 1 << TFCR_HFCLW_Pos); +} + +static inline int LL_TCU_GET_WDT_FLAG(TCU_TypeDef *TCUx) +{ + return READ_REG(TCUx->TFR) & (1 << TFR_HFALGW_Pos); +} + +static inline void LL_TCU_SET_WDT_MASK(TCU_TypeDef *TCUx) +{ + SET_BIT(TCUx->TMSR, 1 << TMSR_HMSKW_Pos); +} + +static inline void LL_TCU_CLEAR_WDT_MASK(TCU_TypeDef *TCUx) +{ + SET_BIT(TCUx->TMCR, 1 << TMCR_HMCLW_Pos); + +} + +static inline int LL_TCU_GET_WDT_MASK(TCU_TypeDef *TCUx) +{ + return READ_REG(TCUx->TMR) & (1 << TMR_HMASKW_Pos); +} + +static inline void LL_TCU_SET_WDT_STOP(TCU_TypeDef *TCUx) +{ + SET_BIT(TCUx->TSSR, 1 << TSSR_WDTSS_Pos); +} + +static inline void LL_TCU_CLEAR_WDT_STOP(TCU_TypeDef *TCUx) +{ + SET_BIT(TCUx->TSCR, 1 << TSCR_WDTSC_Pos); +} + +static inline int LL_TCU_GET_WDT_STOP(TCU_TypeDef *TCUx) +{ + return READ_REG(TCUx->TSR) & (1 << TSR_WDTS_Pos); +} + + +static inline void LL_TCU_DATA_FULL(TCU_TypeDef *TCUx, uint32_t Channel, uint32_t data) +{ + WRITE_REG(TCUx->CHAN[Channel].TDFRn, data); +} + +static inline void LL_TCU_DATA_HALF(TCU_TypeDef *TCUx, uint32_t Channel, uint32_t data) +{ + WRITE_REG(TCUx->CHAN[Channel].TDHRn, data); +} + +static inline void LL_TCU_COUNTER(TCU_TypeDef *TCUx, uint32_t Channel, uint32_t data) +{ + WRITE_REG(TCUx->CHAN[Channel].TCNTn, data); +} + +static inline void LL_TCU_SET_PRESCALE(TCU_TypeDef *TCUx, uint32_t Channel, uint32_t Prescaler) +{ + uint32_t val; + val = READ_REG(TCUx->CHAN[Channel].TCRn); + val &= ~TCRn_PRESCALE_Msk; + val |= Prescaler << TCRn_PRESCALE_Pos; + WRITE_REG(TCUx->CHAN[Channel].TCRn, val); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_LL_TCU_H__ */ diff --git a/drivers/drivers-x2600/src/x2600_hal_tcu.c b/drivers/drivers-x2600/src/x2600_hal_tcu.c new file mode 100644 index 0000000000000000000000000000000000000000..b9472d6b1d4058cfe6771e22c5b19ce7260d36e8 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_hal_tcu.c @@ -0,0 +1,1161 @@ +/** + * @file x2600_hal_tcu.c + * @author MPU系统软件部团队 + * @brief TCU HAL层驱动代码 + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + TCU HAL层驱动．实现tcu模块基本计数功能 + @endverbatim + */ + +/* 1.头文件 (Includes)------------------------------------------------ */ +#include "x2600_hal.h" + +/** @addtogroup g_X16XX_TCU_HAL_Driver + * @{ + */ + +#define HAL_TCU_MODULE_ENABLED +#ifdef HAL_TCU_MODULE_ENABLED + +/* 2.私有常量定义Private Constants -------------------------------------- */ +/** + * @addtogroup TCU_private_constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @addtogroup TCU_private_types + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 4. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @addtogroup TCU_private_macros + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 5. 私有变量申明 Private Variables ------------------------------------ */ +/** + * @addtogroup TCU_private_var + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6. 私有函数申明 (Private Funcs) -------------------------------------- */ +/** + * @addtogroup TCU_private_funcs + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7. 私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup TCU_private_funcs_impl TCU 私有函数实现 (Private Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 8. 导出函数实现------------------------------------------------------- */ +/** + * @defgroup TCU_exported_funcs_impl TCU 导出函数实现 (Exported Funcs) + * @{ + */ + +/** + * @brief TCU初始化函数 + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_Base_Init(TCU_HandleTypeDef *htcu) +{ + /* Check the TCU handle allocation */ + if (htcu == NULL) { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + assert_param(IS_TCU_PRESCALER(htcu->Init.Prescaler)); + assert_param(IS_TCU_TDHR(htcu->Init.Tdhr)); + assert_param(IS_TCU_TDFR(htcu->Init.Tdfr)); + assert_param(IS_TCU_TCNT(htcu->Init.Tcnt)); + assert_param(IS_TCU_CHANNEL(htcu->Init.Channel)); + + HAL_TCU_Base_MspInit(htcu); + + __HAL_TCU_SET_DATA_FULL(htcu, htcu->Init.Channel, htcu->Init.Tdfr); + __HAL_TCU_SET_DATA_HALF(htcu, htcu->Init.Channel, htcu->Init.Tdhr); + __HAL_TCU_SET_TCNT(htcu, htcu->Init.Channel, htcu->Init.Tcnt); + + + __HAL_TCU_SET_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_SET_FULL_MASK(htcu, htcu->Init.Channel); + + __HAL_TCU_SET_PRESCALE(htcu, htcu->Init.Channel, TCU_PRESCALE_DIV4); + + __HAL_TCU_SET_EXT_ENABLE(htcu, htcu->Init.Channel); + //__HAL_TCU_SET_CLK_POS(htcu, htcu->Init.Channel); + + + /* Initialize the TCU state*/ + htcu->State = HAL_OK; + + return HAL_OK; +} + +/** + * @brief TCU去初始化函数 + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK + */ +HAL_StatusTypeDef HAL_TCU_Base_DeInit(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + assert_param(IS_TCU_PRESCALER(htcu->Init.Prescaler)); + assert_param(IS_TCU_TDHR(htcu->Init.Tdhr)); + assert_param(IS_TCU_TDFR(htcu->Init.Tdfr)); + assert_param(IS_TCU_TCNT(htcu->Init.Tcnt)); + assert_param(IS_TCU_CHANNEL(htcu->Init.Channel)); + + + __HAL_TCU_CLEAR_ENABLE(htcu, htcu->Init.Channel); + __HAL_TCU_SET_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_SET_FULL_MASK(htcu, htcu->Init.Channel); + + HAL_TCU_Base_MspDeInit(htcu); + + return HAL_OK; +} + +/** + * @brief TCU板级特有的初始化函数 + * + * @param htcu tcu句柄 + * + * @return 无返回值 + */ +__weak void HAL_TCU_Base_MspInit(TCU_HandleTypeDef *htcu) +{ + UNUSED(htcu); + +} + +/** + * @brief TCU板级特有的去初始化函数 + * + * @param htcu tcu句柄 + * + * @return 无返回值 + */ +__weak void HAL_TCU_Base_MspDeInit(TCU_HandleTypeDef *htcu) +{ + UNUSED(htcu); + +} + + +/** + * @brief 启动TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_Base_Start(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + __HAL_TCU_SET_ENABLE(htcu, htcu->Init.Channel); + + htcu->State = HAL_OK; + + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief 停止TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK + */ +HAL_StatusTypeDef HAL_TCU_Base_Stop(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Disable the Peripheral */ + __HAL_TCU_CLEAR_ENABLE(htcu, htcu->Init.Channel); + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief TCU使能半满中断，启动TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_Base_Start_HALF_IT(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + __HAL_TCU_CLEAR_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_SET_FULL_MASK(htcu, htcu->Init.Channel); + + __HAL_TCU_SET_ENABLE(htcu, htcu->Init.Channel); + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief TCU使能全满中断，启动TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_Base_Start_FULL_IT(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + __HAL_TCU_SET_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_CLEAR_FULL_MASK(htcu, htcu->Init.Channel); + + __HAL_TCU_SET_ENABLE(htcu, htcu->Init.Channel); + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief TCU使能半满和全满中断，启动TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_Base_Start_HALF_FULL_IT(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + __HAL_TCU_CLEAR_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_CLEAR_FULL_MASK(htcu, htcu->Init.Channel); + + __HAL_TCU_SET_ENABLE(htcu, htcu->Init.Channel); + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief TCU关闭半满和全满中断,清中断标志，停止TCU + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK + */ +HAL_StatusTypeDef HAL_TCU_Base_Stop_IT(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + __HAL_TCU_CLEAR_ENABLE(htcu, htcu->Init.Channel); + + __HAL_TCU_CLEAR_HALF_FLAG(htcu, htcu->Init.Channel); + __HAL_TCU_CLEAR_FULL_FLAG(htcu, htcu->Init.Channel); + + __HAL_TCU_SET_HALF_MASK(htcu, htcu->Init.Channel); + __HAL_TCU_SET_FULL_MASK(htcu, htcu->Init.Channel); + + + /* Set the TCU state */ + htcu->State = HAL_OK; + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief TCU中断处理函数 + * + * @param irq　中断号 + * @param data　中断处理函数私有数据 + */ +void HAL_TCU_IRQHandler(int irq, void *data) +{ + TCU_HandleTypeDef *htcu = (TCU_HandleTypeDef *)data; + uint32_t flag = __HAL_TCU_GET_FLAG(htcu); + uint32_t mask = __HAL_TCU_GET_MASK(htcu); + uint32_t is_half_interrupt = (flag & ~mask) & 0xff0000; + uint32_t is_full_interrupt = (flag & ~mask) & 0xff; + + if (is_half_interrupt) { + __HAL_TCU_CLEAR_HALF_FLAG(htcu, htcu->Init.Channel); + HAL_TCU_HALF_Callback(htcu); + } else if (is_full_interrupt) { + __HAL_TCU_CLEAR_FULL_FLAG(htcu, htcu->Init.Channel); + HAL_TCU_FULL_Callback(htcu); + } else { + + } +} + +/** + * @brief TCU半满中断回调函数 + * + * @param htcu tcu句柄 + * + * @return 无返回值 + */ +__weak void HAL_TCU_HALF_Callback(TCU_HandleTypeDef *htcu) +{ + UNUSED(htcu); +} + +/** + * @brief TCU全满中断回调函数 + * + * @param htcu tcu句柄 + * + * @return 无返回值 + */ +__weak void HAL_TCU_FULL_Callback(TCU_HandleTypeDef *htcu) +{ + UNUSED(htcu); +} + +/** + * @brief 获取计数器的值 + * + * @param htcu tcu句柄 + * + * @return 成功返回TCNT的值，失败返回HAL_ERROR + */ +int HAL_TCU_GET_TCNT(TCU_HandleTypeDef *htcu) +{ + int ret = 0; + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + ret = __HAL_TCU_GET_TCNT(htcu, htcu->Init.Channel); + + htcu->State = HAL_OK; + return ret; +} + +/** + * @brief TCU时钟设置函数 + * 用于选择时钟源，并使能或关闭该时钟源 + * + * @param htcu tcu句柄 + * @param clk 选择哪个时钟源 + * @param status 设置该时钟源的状态 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_CLOCK(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int status) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk > 2) + { + prom_printk("%s-%s-%d:clk is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + if (status > 1) + { + prom_printk("%s-%s-%d:status is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(clk) + { + case SEL_INNER_CLOCK: + + break; + case SEL_INPUT_GPIO0: + + __HAL_TCU_SELECT_CLK(htcu, htcu->Init.Channel, TCRn_GPIO0_EN_Msk, TCRn_GPIO0_EN_Pos, status); + break; + case SEL_INPUT_GPIO1: + + __HAL_TCU_SELECT_CLK(htcu, htcu->Init.Channel, TCRn_GPIO1_EN_Msk, TCRn_GPIO1_EN_Pos, status); + break; + } + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief TCU时钟边沿触发模式函数 + * 用于设置时钟源触发方式及上升沿触发还是下降沿 + * + * @param htcu tcu句柄 + * @param clk 设置哪个时钟源 + * @param data 设置触发方式 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_EDGE_MODE(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int data) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk > 2) + { + prom_printk("%s-%s-%d:clk is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + if (data > 1) + { + prom_printk("%s-%s-%d:Edge is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(clk) + { + case SEL_INNER_CLOCK: + if (EDGE_POS == data) + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_CLK_POS_EN_Msk, TCRn_CLK_POS_EN_Pos); + else + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_CLK_NEG_EN_Msk, TCRn_CLK_NEG_EN_Pos); + break; + case SEL_INPUT_GPIO0: + if (EDGE_POS == data) + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_GPIO0_POS_EN_Msk, TCRn_GPIO0_POS_EN_Pos); + else + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_GPIO0_NEG_EN_Msk, TCRn_GPIO0_NEG_EN_Pos); + break; + case SEL_INPUT_GPIO1: + if (EDGE_POS == data) + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_GPIO1_POS_EN_Msk, TCRn_GPIO1_POS_EN_Pos); + else + __HAL_TCU_SET_CLK_EDGE(htcu, htcu->Init.Channel, TCRn_GPIO1_NEG_EN_Msk, TCRn_GPIO1_NEG_EN_Pos); + break; + default: + prom_printk("%s-%s-%d: The clock source does not exist!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + break; + } + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于选择gate信号的来源 + * + * @param htcu tcu句柄 + * @param clk 选择哪个时钟源 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SEL_GATE_SRC(TCU_HandleTypeDef *htcu, unsigned int clk) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk > 3) + { + prom_printk("%s-%s-%d:clock is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(clk) + { + case NOR_GATE: + __HAL_TCU_SEL_GATE_CLK(htcu, htcu->Init.Channel, NOR_GATE); + break; + case INNER_GATE: + __HAL_TCU_SEL_GATE_CLK(htcu, htcu->Init.Channel, INNER_GATE); + break; + case GPIO0_GATE: + __HAL_TCU_SEL_GATE_CLK(htcu, htcu->Init.Channel, GPIO0_GATE); + break; + case GPIO1_GATE: + __HAL_TCU_SEL_GATE_CLK(htcu, htcu->Init.Channel, GPIO1_GATE); + break; + } + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于设置计数器工作在gate信号的高低电平 + * + * @param htcu tcu句柄 + * @param data 设置工作的高低电平 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_GATE_POLA(TCU_HandleTypeDef *htcu,unsigned int data) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (data > 1) + { + prom_printk("%s-%s-%d:POLA mode is error!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + __HAL_TCU_SEL_POLA(htcu, htcu->Init.Channel, TCRn_GATE_POLA_Msk, TCRn_GATE_POLA_Pos, data); + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于选择direction信号的来源 + * + * @param htcu tcu句柄 + * @param clk 选择哪个时钟源 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SEL_DIR_SRC(TCU_HandleTypeDef *htcu, unsigned int clk) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk > 4) + { + prom_printk("%s-%s-%d:clock is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(clk) + { + case NOR_DIR: + __HAL_TCU_SEL_DIR_CLK(htcu, htcu->Init.Channel, NOR_DIR); + break; + case INNER_DIR: + __HAL_TCU_SEL_DIR_CLK(htcu, htcu->Init.Channel, INNER_DIR); + break; + case GPIO0_DIR: + __HAL_TCU_SEL_DIR_CLK(htcu, htcu->Init.Channel, GPIO0_DIR); + break; + case GPIO1_DIR: + __HAL_TCU_SEL_DIR_CLK(htcu, htcu->Init.Channel, GPIO1_DIR); + case GPIO0_AND_GPIO1: + __HAL_TCU_SEL_DIR_CLK(htcu, htcu->Init.Channel, GPIO0_AND_GPIO1); + break; + } + + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于设置计数器在direction信号的高电平或低电平进行减操作 + * + * @param htcu tcu句柄 + * @param data 设置工作的高低电平 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_DIR_POLA(TCU_HandleTypeDef *htcu, unsigned int data) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (POLA_LOW != data && POLA_HIGH != data) + { + prom_printk("%s-%s-%d:POLA mode is error!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + __HAL_TCU_SEL_POLA(htcu, htcu->Init.Channel, TCRn_DIRECTION_POLA_Msk, TCRn_DIRECTION_POLA_Pos, data); + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于设置捕获次数 + * + * @param htcu tcu句柄 + * @param data 捕获次数 + 当data >= 128时，tcu保持在capture模式， + 当data < 128时，tcu进入capture模式，但CAPTURE_NUM会在捕获到时钟源变化时减1 + 当data == 0时，tcu进入pos模式 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_CAP_NUM(TCU_HandleTypeDef *htcu, unsigned int data) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (data > 255) + { + prom_printk("%s-%s-%d:data is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + __HAL_TCU_SET_CAP_NUM(htcu, htcu->Init.Channel, data); + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于获取CAPCRN寄存器值 + * + * @param htcu tcu句柄 + * + * @return 成功返回CAPCRN寄存器值, 失败返回HAL_ERROR + */ +int HAL_TCU_GET_CAPCRN(TCU_HandleTypeDef *htcu) +{ + int ret = 0; + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + ret =__HAL_TCU_GET_CAPCRN(htcu, htcu->Init.Channel); + + htcu->State = HAL_OK; + return ret; +} + +/** + * @brief 用于选择捕获时钟 + * + * @param htcu tcu句柄 + * @param clk 选择哪个时钟源 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SEL_CAP_CLK(TCU_HandleTypeDef *htcu, unsigned int clk) +{ + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk >= 3) + { + prom_printk("%s-%s-%d:clk is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(clk) + { + case SEL_INNER_CLOCK: + __HAL_TCU_SEL_CAP_CLK(htcu, htcu->Init.Channel, SEL_INNER_CLOCK); + break; + case SEL_INPUT_GPIO0: + __HAL_TCU_SEL_CAP_CLK(htcu, htcu->Init.Channel, SEL_INPUT_GPIO0); + break; + case SEL_INPUT_GPIO1: + __HAL_TCU_SEL_CAP_CLK(htcu, htcu->Init.Channel, SEL_INPUT_GPIO1); + break; + + } + + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 用于获取捕获到的周期的大小 + * + * @param htcu tcu句柄 + * + * @return 成功返回捕获到的周期的大小, 失败返回HAL_ERROR + */ +int HAL_TCU_GET_CAP_ALL(TCU_HandleTypeDef *htcu) +{ + int ret = 0; + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + switch(htcu->Init.Channel) + { + case 0: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 0); + break; + case 1: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 1); + break; + case 2: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 2); + break; + case 3: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 3); + break; + case 4: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 4); + break; + case 5: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 5); + break; + case 6: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 6); + break; + case 7: + ret = __HAL_TCU_GET_CAP_ALL(htcu, 7); + break; + } + + + htcu->State = HAL_OK; + return ret; +} + +/** + * @brief 用于获取捕获到的一个周期中高电平持续时间 + * + * @param htcu tcu句柄 + * + * @return 成功返回高电平持续时间, 失败返回HAL_ERROR + */ +int HAL_TCU_GET_CAP_HEIGHT(TCU_HandleTypeDef *htcu) +{ + int ret = 0; + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + switch(htcu->Init.Channel) + { + case 0: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 0); + break; + case 1: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 1); + break; + case 2: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 2); + break; + case 3: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 3); + break; + case 4: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 4); + break; + case 5: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 5); + break; + case 6: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 6); + break; + case 7: + ret = __HAL_TCU_GET_CAP_HEIGHT(htcu, 7); + break; + } + + htcu->State = HAL_OK; + return ret; +} + +/** + * @brief 用于设置过滤阈值 + * + * @param htcu tcu句柄 + * @param clk 要过滤的时钟源 + * @param data　过滤阈值，不能超过1023 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_FIRVR(TCU_HandleTypeDef *htcu, unsigned int clk, unsigned int data) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (clk >= 3 || clk == 0) + { + prom_printk("%s-%s-%d:clk is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + if (data > 1023) + { + prom_printk("%s-%s-%d:data is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + + switch(clk) + { + case SEL_INPUT_GPIO0: + __HAL_TCU_SET_FILRVR(htcu, htcu->Init.Channel, FIRVRn_FIL_A_Msk, FIRVRn_FIL_A_Pos, data); + break; + case SEL_INPUT_GPIO1: + __HAL_TCU_SET_FILRVR(htcu, htcu->Init.Channel, FIRVRn_FIL_B_Msk, FIRVRn_FIL_B_Pos, data); + break; + + } + + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 设置store功能 + * + * @param htcu tcu句柄 + * @param status　使能或关闭store功能 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_STORE(TCU_HandleTypeDef *htcu, unsigned int status) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (status > 2) + { + prom_printk("%s-%s-%d:status is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + __HAL_TCU_SET_STORE(htcu, htcu->Init.Channel, status); + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 设置store触发边沿 + * + * @param htcu tcu句柄 + * @param edge　上升沿触发或下降沿触发 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_SET_STORE_EDGE(TCU_HandleTypeDef *htcu, unsigned int edge) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + if (edge > 1) + { + prom_printk("%s-%s-%d:edge is out of range!\n", __FILE__, __func__, __LINE__); + return HAL_ERROR; + } + + switch(edge) + { + case STORE_POS: + __HAL_TCU_SET_STORE_EDGE(htcu, htcu->Init.Channel, TCRn_STORE_POS_EN_Msk, TCRn_STORE_POS_EN_Pos, 1); + break; + case STORE_NEG: + __HAL_TCU_SET_STORE_EDGE(htcu, htcu->Init.Channel, TCRn_STORE_NEG_EN_Msk, TCRn_STORE_NEG_EN_Pos, 1); + break; + } + + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 清除store中断 + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_TCU_CLEAR_STORE_INTERRUPT(TCU_HandleTypeDef *htcu) +{ + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + __HAL_TCU_CLEAR_STORE_INTERRUPT(htcu, htcu->Init.Channel); + + + htcu->State = HAL_OK; + return HAL_OK; +} + +/** + * @brief 获取TSVR寄存值，即存储的计数值 + * + * @param htcu tcu句柄 + * + * @return 成功返回HAL_OK, 失败返回HAL_ERROR + */ +int HAL_TCU_GET_TSVR(TCU_HandleTypeDef *htcu) +{ + int ret = 0; + + /* Check the parameters */ + assert_param(IS_TCU_INSTANCE(htcu->Instance)); + + /* Check the TCU state */ + if (htcu->State != HAL_OK) { + return HAL_ERROR; + } + + /* Set the TCU state */ + htcu->State = HAL_BUSY; + + ret = __HAL_TCU_GET_TSVR(htcu, htcu->Init.Channel); + + htcu->State = HAL_OK; + return ret; +} + + +/** + * @} + */ + +#endif /* HAL_TCU_MODULE_ENABLED */ + + +/** + * @} + */ diff --git a/drivers/drivers-x2600/src/x2600_ll_tcu.c b/drivers/drivers-x2600/src/x2600_ll_tcu.c new file mode 100644 index 0000000000000000000000000000000000000000..f400ca310186b298b78e1dd69cea97362872e846 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_ll_tcu.c @@ -0,0 +1,58 @@ +/** + * @file x2600_ll_tcu.c + * @author MPU系统软件部团队 + * @brief TCU LL模块驱动程序 + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + + +ErrorStatus LL_TIM_DeInit(TCU_TypeDef *TCUx) +{ + ErrorStatus result = SUCCESS; + + assert_param(IS_TCU_INSTANCE(TCUx)); + + return result; +} + + +void LL_TIM_StructInit(LL_TCU_InitTypeDef *TCU_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = 0; + TIM_InitStruct->Channel = 0; + TIM_InitStruct->Tdfr = 10; + TIM_InitStruct->Tdhr = 5; + TIM_InitStruct->Tcnt = 0; +} + + +ErrorStatus LL_TCU_Init(TCU_TypeDef *TCUx, LL_TCU_InitTypeDef *TCU_InitStruct) +{ + + + assert_param(IS_TCU_INSTANCE(TCUx)); + assert_param(IS_TCU_CHANNEL(TCU_InitStruct->Channel)); + assert_param(IS_TCU_PRESCALER(TCU_InitStruct->Prescaler)); + assert_param(IS_TCU_TDFR(TCU_InitStruct->Tdfr)); + assert_param(IS_TCU_TDHR(TCU_InitStruct->Tdhr)); + assert_param(IS_TCU_TCNT(TCU_InitStruct->Tcnt)); + + LL_TCU_DATA_FULL(TCUx, TCU_InitStruct->Tdfr); + LL_TCU_DATA_HALF(TCUx, TCU_InitStruct->Tdhr); + LL_TCU_CLEAR_FULL_MASK(TCUx, TCU_InitStruct->Channel); + LL_TCU_CLEAR_HALF_MASK(TCUx, TCU_InitStruct->Channel); + + LL_TCU_COUNTER(TCUx, TCU_InitStruct->Tcnt); + LL_TCU_SET_PRESCALE(TCUx, TCU_InitStruct->Prescaler); + + LL_TCU_SET_ENABLE(TCUx, TCU_InitStruct->Channel); +} + diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/cmake-kits.json b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/cmake-kits.json new file mode 100644 index 0000000000000000000000000000000000000000..e9582fe33014473bf341fbc830ad74c0aa07a2c3 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/cmake-kits.json @@ -0,0 +1,18 @@ +[ + { + "name": "RISCV GCC for ingenic cross compile on Windows", + + "toolchainFile": "riscv32-gcc.cmake", + "preferredGenerator": { + "name":"MinGW Makefiles" + } + }, + { + "name": "RISCV GCC for ingenic cross compile on Linux", + "toolchainFile": "riscv32-gcc.cmake", + "preferredGenerator": { + "name":"Unix Makefiles" + } + } +] + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/launch.json b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/launch.json new file mode 100644 index 0000000000000000000000000000000000000000..617a05ab10014630b8e312aaf86f2ff06444a181 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/launch.json @@ -0,0 +1,55 @@ +{ + "version": "0.2.0", + "configurations": [ + // GDB Debugging: + { + "program": "${command:cmake.launchTargetPath}", + "name": "Launch (gdb)", + "request": "launch", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "console": "integratedTerminal", + "internalConsoleOptions": "openOnSessionStart", + "type": "cppdbg", + "MIMode": "gdb", + "miDebuggerPath": "riscv32-ingenicv0-elf-gdb", + "miDebuggerArgs": "", + "miDebuggerServerAddress": "localhost:3333", + "targetArchitecture": "mips", + "preLaunchTask": "adb forward", + "customLaunchSetupCommands": [ + { + "description": "gdb 启用整齐打印", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "text":"cd ${workspaceFolder}", + "ignoreFailures": false + }, + { + "text":"file build/${command:cmake.buildType}/${command:cmake.launchTargetFilename}", + "ignoreFailures": false + }, + { + "text": "target remote localhost:3333", + "ignoreFailures": false + }, + { + "text": "monitor reset halt", + "ignoreFailures": false + }, + { + "text": "load", + "ignoreFailures": false + } + ], + "logging": { + "engineLogging": false, + "programOutput": true + } + } + ] + } + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/settings.json b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..872b961e85cbaa315c582bff1c82e4e5070e9f89 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/settings.json @@ -0,0 +1,8 @@ +{ + "cmake.buildDirectory": "${workspaceFolder}/build/${buildType}", + "files.associations": { + "*.build": "makefile", + "*.mk": "makefile", + "Makefile*": "makefile" + } +} diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/tasks.json b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/tasks.json new file mode 100644 index 0000000000000000000000000000000000000000..53b4731ee6a20f793285233363f06a966abe8d27 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/.vscode/tasks.json @@ -0,0 +1,12 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "adb forward", + "type": "shell", + "command": "adb forward tcp:3333 tcp:3333", + }, + ] +} \ No newline at end of file diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/CMakeLists.txt b/projects/x2660-halley/Examples/tcu/tcu_it/CMakeLists.txt new file mode 100755 index 0000000000000000000000000000000000000000..0f10687c1a23b31ec2fcc3c3e296d0e59bbf36db --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/CMakeLists.txt @@ -0,0 +1,107 @@ +cmake_minimum_required(VERSION 3.8) +# +# Core project settings +# +Project(template) # Modified +enable_language(C CXX ASM) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS ON) +set(PROJ_PATH ${CMAKE_CURRENT_SOURCE_DIR}) +set(SDK_PATH ${PROJ_PATH}/../../../../) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Set linker script +set(linker_script_SRC ${SDK_PATH}/cpu/core-riscv/ld.lds) # Modified +set(EXECUTABLE ${CMAKE_PROJECT_NAME}) +set(CPU_PARAMETERS "-march=rv32imc -mabi=ilp32 -Wno-abi") + +set(CMAKE_ASM_FLAGS "${CPU_PARAMETERS} -D_ASSEMBLER_ -D__ASSEMBLY__") + +set(CMAKE_C_FLAGS "${CPU_PARAMETERS} -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Wall -fdata-sections -ffunction-sections") + +# Compiler options + +if(CMAKE_BUILD_TYPE STREQUAL Debug) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 -g -ggdb -DDEBUG") +else() + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O2") +endif() + +set(CMAKE_CXX_FLAGS ${CMAKE_C_FLAGS}) + +set(CMAKE_LD_FLAGS "${CPU_PARAMETERS}") + + +set(sources_SRCS # Modified + ${SDK_PATH}/cpu/core-riscv/spinlock.c + ${SDK_PATH}/cpu/core-riscv/start.S + ${SDK_PATH}/cpu/core-riscv/genex.S + ${SDK_PATH}/cpu/core-riscv/traps.c + ${SDK_PATH}/cpu/soc-x2600/src/interrupt.c + ${SDK_PATH}/cpu/soc-x2600/src/serial.c + ${SDK_PATH}/cpu/soc-x2600/src/startup.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_def.c + ${SDK_PATH}/lib/libc/minimal/ctype.c + ${SDK_PATH}/lib/libc/minimal/div64.c + ${SDK_PATH}/lib/libc/minimal/string.c + ${SDK_PATH}/lib/libc/minimal/vsprintf.c + main.c + +) + +if(CMAKE_EXPORT_COMPILE_COMMANDS) + set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) + set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) +endif() + +# +# Include directories +# +#set(include_path_DIRS +# Modified + +include_directories( + ${PROJ_PATH}/include + ${SDK_PATH}/lib/libc/minimal/include + ${SDK_PATH}/drivers/drivers-x2600/include + ${SDK_PATH}/cpu/core-riscv/include + ${SDK_PATH}/cpu/soc-x2600/include + +) + +# +# -L libdirs. +# +link_directories( +#path/to/lib +) + +# Executable files +add_executable(${EXECUTABLE} ${sources_SRCS}) + +# Linker options +target_link_libraries(${EXECUTABLE} PRIVATE + -T${linker_script_SRC} + ${CMAKE_LD_FLAGS} + -Wl,-Map=${CMAKE_PROJECT_NAME}.map,--cref + -Wl,--gc-sections + -Wl,--start-group + -Wl,--end-group + -Wl,--print-memory-usage +) + +# Execute post-build to print size +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_SIZE} $ +) + +# Convert output to hex and binary +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin + ) diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/Makefile b/projects/x2660-halley/Examples/tcu/tcu_it/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..cea126dff978da899befd3571e6cb67d140f1f41 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/Makefile @@ -0,0 +1,174 @@ +###################################### +# target +###################################### +TARGET = tcu + +SDK_PATH = ../../../../../ + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Werror-implicit-function-declaration + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/traps.c \ +$(SDK_PATH)/cpu/core-riscv/spinlock.c \ +$(SDK_PATH)/cpu/soc-x2600/src/startup.c \ +$(SDK_PATH)/cpu/soc-x2600/src/serial.c \ +$(SDK_PATH)/cpu/soc-x2600/src/interrupt.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_def.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_cpm.c \ +$(SDK_PATH)/lib/libc/minimal/vsprintf.c \ +$(SDK_PATH)/lib/libc/minimal/string.c \ +$(SDK_PATH)/lib/libc/minimal/ctype.c \ +$(SDK_PATH)/lib/libc/minimal/div64.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_tcu.c \ +main.c + +# ASM sources +ASM_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/start.S \ +$(SDK_PATH)/cpu/core-riscv/genex.S + + +####################################### +# binaries +####################################### +PREFIX = riscv32-ingenicv0-elf- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)as +LD = $(GCC_PATH)/$(PREFIX)ld +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)as +LD = $(PREFIX)ld +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -march=rv32imc -mabi=ilp32 -Wno-abi + +# fpu +FPU = + +# float-abi +FLOAT-ABI = + +# mcu +#MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) +MCU = $(CPU) $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = -D_ASSEMBLER_ -D__ASSEMBLY__ + +# C defines +C_DEFS = + + +# AS includes +AS_INCLUDES = \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ + +# C includes +C_INCLUDES = \ +-Iinclude \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/cpu/soc-x2600/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ +-I$(SDK_PATH)/drivers/drivers-x2600/include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 -O0 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = $(SDK_PATH)/cpu/core-riscv/ld.lds + +# libraries +#LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -nostdlib + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(CC) -c $(ASFLAGS) -o $@ $< + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/README.md b/projects/x2660-halley/Examples/tcu/tcu_it/README.md new file mode 100644 index 0000000000000000000000000000000000000000..220afc6bf1fd280cfbef957af0e73e5bd547e5f6 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/README.md @@ -0,0 +1,46 @@ + +1. Linux 命令行编译 + +a. 基于Makefile + +``` +$ make +``` +会在build目录生成template.elf, template.bin文件. + + +b. 基于cmake + +``` +$ mkdir build +$ cd build +$ cmake -DCMAKE_TOOLCHAIN_FILE=../mips-gcc-sde-elf.cmake .. +$ make + +``` +会在build目录下生成template.elf，template.bin文件. + + +2. windows 编译. + +2.1 基于vscode + +a. vscode 大概projects/template 文件夹 +b. 选择cmake-kits "GCC for ingenic cross compile on Windows" +c. lunch(F5) 运行编译、调试 +d. 或者选择状态栏，build，仅编译. + + + +2.2 基于命令行 + +前提： 系统必须安装msys - mingw64-make 工具. + +``` +$ mkdir build +$ cd build +$ cmake -DCMAKE_TOOLCHAIN_FILE=../mips-gcc-sde-elf.cmake -G "MinGW Makefiles" ../ +$ mingw32-make +``` + + diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/include/board_eth_phy_conf.h b/projects/x2660-halley/Examples/tcu/tcu_it/include/board_eth_phy_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..c907ead4a2298d34794f0491a29781cf67ffdb68 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/include/board_eth_phy_conf.h @@ -0,0 +1,75 @@ +#ifndef __ETH_PHY_CONF_H +#define __ETH_PHY_CONF_H + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 0x00U +#define MAC_ADDR1 0x11U +#define MAC_ADDR2 0x22U +#define MAC_ADDR3 0x33U +#define MAC_ADDR4 0x44U +#define MAC_ADDR5 0x55U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2600U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2600U) /*!< PHY link status interrupt mask */ + +/* ################## Ethernet peripheral configuration ##################### */ + + + +#endif // __ETH_PHY_CONF_H + diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_hal_conf.h b/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..f923376aa637735d8836ac675e3ce7a8d9edead2 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_hal_conf.h @@ -0,0 +1,118 @@ +#ifndef __X2600_HAL_CONF_H__ +#define __X2600_HAL_CONF_H__ +/* TODO： 本文件应该通过工具生成，在配置工程中选择不同的组件时，在此处包含不同的头文件 + 暂时包含全部头文件. +*/ + + +/* 1. Includes ---------------------------------------------------- */ + + +/* Hal Module selections. */ +#if 0 +#define HAL_MSC_ENABLED +#define HAL_I2C_ENABLED +#define HAL_UART_ENABLED +#define HAL_ADC_ENABLED +#define HAL_SPI_ENABLED +#define HAL_WDT_ENABLED +#define HAL_TCU_ENABLED +#define HAL_RTC_ENABLED +#define HAL_EFUSE_ENABLED +#define HAL_PWM_ENABLED +#define HAL_GMAC_ENABLED +#define HAL_USB_ENABLED +#endif + +/* 系统时钟配配置，通过工具生成，随开发板或者平台变化.*/ +#include +#include + +#include "x2600_hal_tick.h" +#include "x2600_ll_ost_core.h" +#include "x2600_ll_ost_global.h" +#include "x2600_ll_cpm.h" +#include "x2600_ll_gpio.h" + +#include "x2600_hal_pdma.h" + +//#include "x2600_hal_sfcnor.h" + +#ifdef HAL_MSC_ENABLED + +#endif + +#ifdef HAL_I2C_ENABLED +#include "x2600_hal_i2c.h" +#endif + +#ifdef HAL_UART_ENABLED +#include "x2600_hal_uart.h" +#endif + +#ifdef HAL_ADC_ENABLED +#include "x2600_hal_adc.h" +#endif + +#ifdef HAL_SPI_ENABLED +#include "x2600_hal_spi.h" +#endif + +#ifdef HAL_WDT_ENABLED +#include "x2600_hal_wdt.h" +#endif + +#ifdef HAL_TCU_ENABLED +#include "x2600_hal_tcu.h" +#endif + +#ifdef HAL_RTC_ENABLED +#include "x2600_hal_rtc.h" +#endif + +#ifdef HAL_EFUSE_ENABLED +#include "x2600_ll_efuse.h" +#include "x2600_hal_efuse.h" +#endif + +#ifdef HAL_PWM_ENABLED +#include "x2600_hal_pwm.h" +#endif + +#ifdef HAL_GMAC_ENABLED +#include "x2600_hal_gmac.h" +#endif + +#ifdef HAL_USB_ENABLED +#include "x2600_hal_pcd.h" +#include "x2600_hal_pcd_ex.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* 2. Exported Types ---------------------------------------------- */ + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_H__ */ diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_sysclk_conf.h b/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_sysclk_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..3c4888de77815e51f6a20b70226fc73892421676 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/include/x2600_sysclk_conf.h @@ -0,0 +1,68 @@ +/** + * @file x2600_sysclk_conf.h + * @author MPU系统软件部团队 + * @brief + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_SYSCLK_CONF_H__ +#define __X2600_SYSCLK_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* 1. Includes ---------------------------------------------------- */ + +/* 2. Exported Types ---------------------------------------------- */ + + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ +#define SYSCLK_EXTAL (24000000) +#define SYSCLK_APLL (1200000000) +#define SYSCLK_MPLL (1200000000) + +#define SystemCoreClock SYSCLK_APLL + +#define CGU_CONFIG_MSC_APLL_24M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 24, \ + .Config = 0 } + +#define CGU_CONFIG_MSC_APLL_48M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 11, \ + .Config = 0 } + + +#define CGU_CONFIG_SSI_MPLL_500K { \ + .PLLMux = SSICDR_MPLL, \ + .Div = 15, \ + .Config = 0 } + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_ADC_H__ */ diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/main.c b/projects/x2660-halley/Examples/tcu/tcu_it/main.c new file mode 100644 index 0000000000000000000000000000000000000000..db0e5fca2a9536fece99d648fb8a4b10b98e7d46 --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/main.c @@ -0,0 +1,42 @@ +#include + +TCU_HandleTypeDef tcu = {0}; + +int main(void) +{ + prom_printk("hello world %s, %d\n", __func__, __LINE__); + + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_TCU1); + + tcu.Instance = TCU1_Instance; + tcu.Init.Channel = 1; + tcu.Init.Prescaler = TCU_PRESCALE_DIV4; + tcu.Init.Tdfr = 0x8fff; + tcu.Init.Tdhr = 0x1fff; + tcu.Init.Tcnt = 0x2; + HAL_TCU_Base_Init(&tcu); + + HAL_TCU_SET_EDGE_MODE(&tcu, SEL_INNER_CLOCK, EDGE_POS); + + HAL_TCU_Base_Start_FULL_IT(&tcu); + + + ll_request_irq(IRQ_INTC0_TCU1, HAL_TCU_IRQHandler, &tcu); + + while (1); + + return 0; +} + + +void HAL_TCU_HALF_Callback(TCU_HandleTypeDef *htcu) +{ + prom_printk("half\n"); +} + +void HAL_TCU_FULL_Callback(TCU_HandleTypeDef *htcu) +{ + prom_printk("full\n"); +} + + diff --git a/projects/x2660-halley/Examples/tcu/tcu_it/riscv32-gcc.cmake b/projects/x2660-halley/Examples/tcu/tcu_it/riscv32-gcc.cmake new file mode 100644 index 0000000000000000000000000000000000000000..d09813df61ac4d343b4b4890668528bf54e9cedc --- /dev/null +++ b/projects/x2660-halley/Examples/tcu/tcu_it/riscv32-gcc.cmake @@ -0,0 +1,18 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv32) + +# Some default GCC settings +set(TOOLCHAIN_PREFIX "riscv32-ingenicv0-elf-") + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++) + +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)