From 672d6c60980d079eede7fb9f083133b551b272a3 Mon Sep 17 00:00:00 2001 From: "lichao.ren" Date: Fri, 26 May 2023 10:33:34 +0800 Subject: [PATCH] [Add] Add dpu tft screen rdma mode --- cpu/core-riscv/ld.lds | 5 + cpu/soc-x2600/include/dpu.h | 742 +++++++++++++++++ cpu/soc-x2600/include/x2600.h | 4 + drivers/drivers-x2600/ChangeLog | 1 + .../drivers-x2600/include/x2600_hal_conf.h | 5 + drivers/drivers-x2600/include/x2600_hal_lcd.h | 632 ++++++++++++++ drivers/drivers-x2600/include/x2600_ll_cpm.h | 4 +- drivers/drivers-x2600/src/x2600_hal_lcd.c | 776 ++++++++++++++++++ drivers/drivers-x2600/src/x2600_ll_cpm.c | 88 +- .../Examples/lcd/.vscode/cmake-kits.json | 18 + .../Examples/lcd/.vscode/launch.json | 63 ++ .../Examples/lcd/.vscode/settings.json | 9 + .../Examples/lcd/.vscode/tasks.json | 12 + .../x2660-halley/Examples/lcd/CMakeLists.txt | 110 +++ projects/x2660-halley/Examples/lcd/Makefile | 175 ++++ .../Examples/lcd/include/board_eth_phy_conf.h | 75 ++ .../Examples/lcd/include/x2600_hal_conf.h | 118 +++ .../Examples/lcd/include/x2600_sysclk_conf.h | 73 ++ .../x2660-halley/Examples/lcd/kd050wvfpa029.c | 69 ++ projects/x2660-halley/Examples/lcd/main.c | 78 ++ .../Examples/lcd/riscv32-gcc.cmake | 18 + 21 files changed, 3029 insertions(+), 46 deletions(-) create mode 100755 cpu/soc-x2600/include/dpu.h create mode 100644 drivers/drivers-x2600/include/x2600_hal_lcd.h create mode 100644 drivers/drivers-x2600/src/x2600_hal_lcd.c create mode 100644 projects/x2660-halley/Examples/lcd/.vscode/cmake-kits.json create mode 100644 projects/x2660-halley/Examples/lcd/.vscode/launch.json create mode 100644 projects/x2660-halley/Examples/lcd/.vscode/settings.json create mode 100644 projects/x2660-halley/Examples/lcd/.vscode/tasks.json create mode 100644 projects/x2660-halley/Examples/lcd/CMakeLists.txt create mode 100644 projects/x2660-halley/Examples/lcd/Makefile create mode 100644 projects/x2660-halley/Examples/lcd/include/board_eth_phy_conf.h create mode 100644 projects/x2660-halley/Examples/lcd/include/x2600_hal_conf.h create mode 100644 projects/x2660-halley/Examples/lcd/include/x2600_sysclk_conf.h create mode 100644 projects/x2660-halley/Examples/lcd/kd050wvfpa029.c create mode 100644 projects/x2660-halley/Examples/lcd/main.c create mode 100644 projects/x2660-halley/Examples/lcd/riscv32-gcc.cmake diff --git a/cpu/core-riscv/ld.lds b/cpu/core-riscv/ld.lds index d13961ba..7e02ef17 100644 --- a/cpu/core-riscv/ld.lds +++ b/cpu/core-riscv/ld.lds @@ -19,6 +19,11 @@ MEMORY instrram : ORIGIN = 0x07f00000, LENGTH = 0x10000 dataram : ORIGIN = 0x07f10000, LENGTH = 0x20000 stack : ORIGIN = 0x07f30000, LENGTH = 0x20000 + /* + instrram : ORIGIN = 0x07300000, LENGTH = 0x10000 + dataram : ORIGIN = 0x07310000, LENGTH = 0xC20000 + stack : ORIGIN = 0x07f30000, LENGTH = 0x20000 + */ } /* Stack information variables */ diff --git a/cpu/soc-x2600/include/dpu.h b/cpu/soc-x2600/include/dpu.h new file mode 100755 index 00000000..9c62167a --- /dev/null +++ b/cpu/soc-x2600/include/dpu.h @@ -0,0 +1,742 @@ +#ifndef __REG_DPU_H__ +#define __REG_DPU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup group_DPU DPU控制器 + * @{ + */ + +/** + * @addtogroup g_DPU_reg DPU 寄存器定义 + * @{ + */ +/** +* @brief Registers for dpu +*/ +typedef struct { + ////TODO, 添加寄存器Reserved，填充地址空间 + unsigned long RESERVED_0x00[1024]; /*!< Reserved Memory Area start from 0x00 to 0x1000*/ + __IO unsigned long DC_SRD_CHAIN_ADDR; /*!< RDMA descriptor's address ,RW, 0x1000 */ + __O unsigned long DC_SRD_CHAIN_CTRL; /*!< RDMA descriptor's control , W, 0x1004 */ + unsigned long RESERVED_0x1008[1022]; /*!< Reserved Memory Area start from 0x1008 to 0x2000*/ + __O unsigned long DC_CTRL; /*!< DC control , W, 0x2000 */ + __I unsigned long DC_ST; /*!< DC status , R, 0x2004 */ + __O unsigned long DC_CLR_ST; /*!< DC clear status , W, 0x2008 */ + __IO unsigned long DC_INTC; /*!< DC interrupt mask ,RW, 0x200C */ + __I unsigned long DC_INT_FLAG; /*!< DC interrupt flag , R, 0x2010 */ + __IO unsigned long DC_COM_CONFIG; /*!< DC common config ,RW, 0x2014 */ + __IO unsigned long DC_PCFG_RD_CTRL; /*!< Back door for read channel's QoS,RW, 0x2018 */ + unsigned long RESERVED_0x201c[1]; /*!< Reserved Memory Area start from 0x201c to 0x2020*/ + __IO unsigned long DC_PCFG_OFIFO; /*!< Priority level threshold config when rdma,RW, 0x2020 */ + unsigned long RESERVED_0x2024[60]; /*!< Reserved Memory Area start from 0x2024 to 0x2114*/ + __I unsigned long DC_RDMA_DES; /*!< for debug , R, 0x2114 */ + unsigned long RESERVED_0x2118[59]; /*!< Reserved Memory Area start from 0x2118 to 0x2204*/ + __I unsigned long DC_RDMA_CHAIN_SITE; /*!< rdma descriptor's current site , R, 0x2204 */ + unsigned long RESERVED_0x2208[962]; /*!< Reserved Memory Area start from 0x2208 to 0x3110*/ + __I unsigned long DC_RDMA_SITE; /*!< rdma's current site , R, 0x3110 */ + unsigned long RESERVED_0x3114[5051]; /*!< Reserved Memory Area start from 0x3114 to 0x8000*/ + __IO unsigned long DISP_COM; /*!< display common configure ,RW, 0x8000 */ + unsigned long RESERVED_0x8004[1023]; /*!< Reserved Memory Area start from 0x8004 to 0x9000*/ + __IO unsigned long TFT_TIMING_HSYNC; /*!< TFT HSYNC ,RW, 0x9000 */ + __IO unsigned long TFT_TIMIING_VSYNC; /*!< TFT VSYNC ,RW, 0x9004 */ + __IO unsigned long TFT_TIMIING_HDE; /*!< TFT HDE ,RW, 0x9008 */ + __IO unsigned long TFT_TIMIING_VDE; /*!< TFT VDE ,RW, 0x900C */ + __IO unsigned long TFT_TRAN_CFG; /*!< TFT configure ,RW, 0x9010 */ + __I unsigned long TFT_ST; /*!< TFT status , R, 0x9014 */ + unsigned long RESERVED_0x9018[1018]; /*!< Reserved Memory Area start from 0x9018 to 0xa000*/ + __IO unsigned long SLCD_PANEL_CFG; /*!< SLCD configure ,RW, 0xA000 */ + __IO unsigned long SLCD_WR_DUTY; /*!< SLCD WR's duty ,RW, 0xA004 */ + __IO unsigned long SLCD_TIMING; /*!< SLCD timing ,RW, 0xA008 */ + __IO unsigned long SLCD_FRM_SIZE; /*!< frame size ,RW, 0xA00C */ + __IO unsigned long SLCD_SLOW_TIME; /*!< slow time ,RW, 0xA010 */ + __IO unsigned long SLCD_REG_IF; /*!< SLCD reg-op interface ,RW, 0xA014 */ + __I unsigned long SLCD_ST; /*!< SLCD status , R, 0xA018 */ + __O unsigned long SLCD_REG_CTRL; /*!< SLCD reg-op interface control , W, 0xA01C */ +} DPU_TypeDef; + +/********* Register BitField Details: REG_NAME BASE+0x0000 *********/ +#define REG_NAME_SLOW_TIME_Pos (0U) +#define REG_NAME_SLOW_TIME_Msk (0xffffUL << REG_NAME_SLOW_TIME_Pos) /*!< 0x0000ffff */ +#define REG_NAME_SLOW_TIME REG_NAME_SLOW_TIME_Msk +#define REG_NAME_SLOW_TIME_0 (0x1UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000001 */ +#define REG_NAME_SLOW_TIME_1 (0x2UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000002 */ +#define REG_NAME_SLOW_TIME_2 (0x4UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000004 */ +#define REG_NAME_SLOW_TIME_3 (0x8UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000008 */ +#define REG_NAME_SLOW_TIME_4 (0x10UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000010 */ +#define REG_NAME_SLOW_TIME_5 (0x20UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000020 */ +#define REG_NAME_SLOW_TIME_6 (0x40UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000040 */ +#define REG_NAME_SLOW_TIME_7 (0x80UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000080 */ +#define REG_NAME_SLOW_TIME_8 (0x100UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000100 */ +#define REG_NAME_SLOW_TIME_9 (0x200UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000200 */ +#define REG_NAME_SLOW_TIME_10 (0x400UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000400 */ +#define REG_NAME_SLOW_TIME_11 (0x800UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00000800 */ +#define REG_NAME_SLOW_TIME_12 (0x1000UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00001000 */ +#define REG_NAME_SLOW_TIME_13 (0x2000UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00002000 */ +#define REG_NAME_SLOW_TIME_14 (0x4000UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00004000 */ +#define REG_NAME_SLOW_TIME_15 (0x8000UL << REG_NAME_SLOW_TIME_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: DC_SRD_CHAIN_ADDR BASE+0x1000 *********/ +/* There is no BitField Details for SRD_CHAIN_ADDR */ + +/********* Register BitField Details: DC_SRD_CHAIN_CTRL BASE+0x1004 *********/ +#define DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_Pos (0U) +#define DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_Msk (0x1UL << DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_Pos) /*!< 0x00000001 */ +#define DC_SRD_CHAIN_CTRL_SRD_CHAIN_START DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_Msk +#define DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_0 (0x1UL << DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DC_CTRL BASE+0x2000 *********/ +#define DC_CTRL_GEN_STP_SRD_Pos (4U) +#define DC_CTRL_GEN_STP_SRD_Msk (0x1UL << DC_CTRL_GEN_STP_SRD_Pos) /*!< 0x00000010 */ +#define DC_CTRL_GEN_STP_SRD DC_CTRL_GEN_STP_SRD_Msk +#define DC_CTRL_GEN_STP_SRD_0 (0x1UL << DC_CTRL_GEN_STP_SRD_Pos) /*!< 0x00000010 */ +#define DC_CTRL_DES_CNT_RST_Pos (2U) +#define DC_CTRL_DES_CNT_RST_Msk (0x1UL << DC_CTRL_DES_CNT_RST_Pos) /*!< 0x00000004 */ +#define DC_CTRL_DES_CNT_RST DC_CTRL_DES_CNT_RST_Msk +#define DC_CTRL_DES_CNT_RST_0 (0x1UL << DC_CTRL_DES_CNT_RST_Pos) /*!< 0x00000004 */ +#define DC_CTRL_QCK_STP_SRD_Pos (1U) +#define DC_CTRL_QCK_STP_SRD_Msk (0x1UL << DC_CTRL_QCK_STP_SRD_Pos) /*!< 0x00000002 */ +#define DC_CTRL_QCK_STP_SRD DC_CTRL_QCK_STP_SRD_Msk +#define DC_CTRL_QCK_STP_SRD_0 (0x1UL << DC_CTRL_QCK_STP_SRD_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DC_ST BASE+0x2004 *********/ +#define DC_ST_DISP_END_Pos (17U) +#define DC_ST_DISP_END_Msk (0x1UL << DC_ST_DISP_END_Pos) /*!< 0x00020000 */ +#define DC_ST_DISP_END DC_ST_DISP_END_Msk +#define DC_ST_DISP_END_0 (0x1UL << DC_ST_DISP_END_Pos) /*!< 0x00020000 */ +#define DC_ST_TFT_UNDR_Pos (8U) +#define DC_ST_TFT_UNDR_Msk (0x1UL << DC_ST_TFT_UNDR_Pos) /*!< 0x00000100 */ +#define DC_ST_TFT_UNDR DC_ST_TFT_UNDR_Msk +#define DC_ST_TFT_UNDR_0 (0x1UL << DC_ST_TFT_UNDR_Pos) /*!< 0x00000100 */ +#define DC_ST_STOP_SRD_ACK_Pos (7U) +#define DC_ST_STOP_SRD_ACK_Msk (0x1UL << DC_ST_STOP_SRD_ACK_Pos) /*!< 0x00000080 */ +#define DC_ST_STOP_SRD_ACK DC_ST_STOP_SRD_ACK_Msk +#define DC_ST_STOP_SRD_ACK_0 (0x1UL << DC_ST_STOP_SRD_ACK_Pos) /*!< 0x00000080 */ +#define DC_ST_SRD_WORKING_Pos (3U) +#define DC_ST_SRD_WORKING_Msk (0x1UL << DC_ST_SRD_WORKING_Pos) /*!< 0x00000008 */ +#define DC_ST_SRD_WORKING DC_ST_SRD_WORKING_Msk +#define DC_ST_SRD_WORKING_0 (0x1UL << DC_ST_SRD_WORKING_Pos) /*!< 0x00000008 */ +#define DC_ST_SRD_START_Pos (2U) +#define DC_ST_SRD_START_Msk (0x1UL << DC_ST_SRD_START_Pos) /*!< 0x00000004 */ +#define DC_ST_SRD_START DC_ST_SRD_START_Msk +#define DC_ST_SRD_START_0 (0x1UL << DC_ST_SRD_START_Pos) /*!< 0x00000004 */ +#define DC_ST_SRD_END_Pos (1U) +#define DC_ST_SRD_END_Msk (0x1UL << DC_ST_SRD_END_Pos) /*!< 0x00000002 */ +#define DC_ST_SRD_END DC_ST_SRD_END_Msk +#define DC_ST_SRD_END_0 (0x1UL << DC_ST_SRD_END_Pos) /*!< 0x00000002 */ +#define DC_ST_WORKING_Pos (0U) +#define DC_ST_WORKING_Msk (0x1UL << DC_ST_WORKING_Pos) /*!< 0x00000001 */ +#define DC_ST_WORKING DC_ST_WORKING_Msk +#define DC_ST_WORKING_0 (0x1UL << DC_ST_WORKING_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DC_CLR_ST BASE+0x2008 *********/ +#define DC_CLR_ST_CLR_DISP_END_Pos (17U) +#define DC_CLR_ST_CLR_DISP_END_Msk (0x1UL << DC_CLR_ST_CLR_DISP_END_Pos) /*!< 0x00020000 */ +#define DC_CLR_ST_CLR_DISP_END DC_CLR_ST_CLR_DISP_END_Msk +#define DC_CLR_ST_CLR_DISP_END_0 (0x1UL << DC_CLR_ST_CLR_DISP_END_Pos) /*!< 0x00020000 */ +#define DC_CLR_ST_CLR_TFT_UNDR_Pos (8U) +#define DC_CLR_ST_CLR_TFT_UNDR_Msk (0x1UL << DC_CLR_ST_CLR_TFT_UNDR_Pos) /*!< 0x00000100 */ +#define DC_CLR_ST_CLR_TFT_UNDR DC_CLR_ST_CLR_TFT_UNDR_Msk +#define DC_CLR_ST_CLR_TFT_UNDR_0 (0x1UL << DC_CLR_ST_CLR_TFT_UNDR_Pos) /*!< 0x00000100 */ +#define DC_CLR_ST_CLR_STP_SRD_ACK_Pos (7U) +#define DC_CLR_ST_CLR_STP_SRD_ACK_Msk (0x1UL << DC_CLR_ST_CLR_STP_SRD_ACK_Pos) /*!< 0x00000080 */ +#define DC_CLR_ST_CLR_STP_SRD_ACK DC_CLR_ST_CLR_STP_SRD_ACK_Msk +#define DC_CLR_ST_CLR_STP_SRD_ACK_0 (0x1UL << DC_CLR_ST_CLR_STP_SRD_ACK_Pos) /*!< 0x00000080 */ +#define DC_CLR_ST_CLR_SRD_START_Pos (2U) +#define DC_CLR_ST_CLR_SRD_START_Msk (0x1UL << DC_CLR_ST_CLR_SRD_START_Pos) /*!< 0x00000004 */ +#define DC_CLR_ST_CLR_SRD_START DC_CLR_ST_CLR_SRD_START_Msk +#define DC_CLR_ST_CLR_SRD_START_0 (0x1UL << DC_CLR_ST_CLR_SRD_START_Pos) /*!< 0x00000004 */ +#define DC_CLR_ST_CLR_SRD_END_Pos (1U) +#define DC_CLR_ST_CLR_SRD_END_Msk (0x1UL << DC_CLR_ST_CLR_SRD_END_Pos) /*!< 0x00000002 */ +#define DC_CLR_ST_CLR_SRD_END DC_CLR_ST_CLR_SRD_END_Msk +#define DC_CLR_ST_CLR_SRD_END_0 (0x1UL << DC_CLR_ST_CLR_SRD_END_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DC_INTC BASE+0x200c *********/ +#define DC_INTC_EOD_MSK_Pos (17U) +#define DC_INTC_EOD_MSK_Msk (0x1UL << DC_INTC_EOD_MSK_Pos) /*!< 0x00020000 */ +#define DC_INTC_EOD_MSK DC_INTC_EOD_MSK_Msk +#define DC_INTC_EOD_MSK_0 (0x1UL << DC_INTC_EOD_MSK_Pos) /*!< 0x00020000 */ +#define DC_INTC_UOT_MSK_Pos (8U) +#define DC_INTC_UOT_MSK_Msk (0x1UL << DC_INTC_UOT_MSK_Pos) /*!< 0x00000100 */ +#define DC_INTC_UOT_MSK DC_INTC_UOT_MSK_Msk +#define DC_INTC_UOT_MSK_0 (0x1UL << DC_INTC_UOT_MSK_Pos) /*!< 0x00000100 */ +#define DC_INTC_SSA_MSK_Pos (7U) +#define DC_INTC_SSA_MSK_Msk (0x1UL << DC_INTC_SSA_MSK_Pos) /*!< 0x00000080 */ +#define DC_INTC_SSA_MSK DC_INTC_SSA_MSK_Msk +#define DC_INTC_SSA_MSK_0 (0x1UL << DC_INTC_SSA_MSK_Pos) /*!< 0x00000080 */ +#define DC_INTC_SOS_MSK_Pos (2U) +#define DC_INTC_SOS_MSK_Msk (0x1UL << DC_INTC_SOS_MSK_Pos) /*!< 0x00000004 */ +#define DC_INTC_SOS_MSK DC_INTC_SOS_MSK_Msk +#define DC_INTC_SOS_MSK_0 (0x1UL << DC_INTC_SOS_MSK_Pos) /*!< 0x00000004 */ +#define DC_INTC_EOS_MSK_Pos (1U) +#define DC_INTC_EOS_MSK_Msk (0x1UL << DC_INTC_EOS_MSK_Pos) /*!< 0x00000002 */ +#define DC_INTC_EOS_MSK DC_INTC_EOS_MSK_Msk +#define DC_INTC_EOS_MSK_0 (0x1UL << DC_INTC_EOS_MSK_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DC_INT_FLAG BASE+0x2010 *********/ +#define DC_INT_FLAG_INT_EOD_Pos (17U) +#define DC_INT_FLAG_INT_EOD_Msk (0x1UL << DC_INT_FLAG_INT_EOD_Pos) /*!< 0x00020000 */ +#define DC_INT_FLAG_INT_EOD DC_INT_FLAG_INT_EOD_Msk +#define DC_INT_FLAG_INT_EOD_0 (0x1UL << DC_INT_FLAG_INT_EOD_Pos) /*!< 0x00020000 */ +#define DC_INT_FLAG_INT_UOT_Pos (8U) +#define DC_INT_FLAG_INT_UOT_Msk (0x1UL << DC_INT_FLAG_INT_UOT_Pos) /*!< 0x00000100 */ +#define DC_INT_FLAG_INT_UOT DC_INT_FLAG_INT_UOT_Msk +#define DC_INT_FLAG_INT_UOT_0 (0x1UL << DC_INT_FLAG_INT_UOT_Pos) /*!< 0x00000100 */ +#define DC_INT_FLAG_INT_SSA_Pos (7U) +#define DC_INT_FLAG_INT_SSA_Msk (0x1UL << DC_INT_FLAG_INT_SSA_Pos) /*!< 0x00000080 */ +#define DC_INT_FLAG_INT_SSA DC_INT_FLAG_INT_SSA_Msk +#define DC_INT_FLAG_INT_SSA_0 (0x1UL << DC_INT_FLAG_INT_SSA_Pos) /*!< 0x00000080 */ +#define DC_INT_FLAG_INT_SOS_Pos (2U) +#define DC_INT_FLAG_INT_SOS_Msk (0x1UL << DC_INT_FLAG_INT_SOS_Pos) /*!< 0x00000004 */ +#define DC_INT_FLAG_INT_SOS DC_INT_FLAG_INT_SOS_Msk +#define DC_INT_FLAG_INT_SOS_0 (0x1UL << DC_INT_FLAG_INT_SOS_Pos) /*!< 0x00000004 */ +#define DC_INT_FLAG_INT_EOS_Pos (1U) +#define DC_INT_FLAG_INT_EOS_Msk (0x1UL << DC_INT_FLAG_INT_EOS_Pos) /*!< 0x00000002 */ +#define DC_INT_FLAG_INT_EOS DC_INT_FLAG_INT_EOS_Msk +#define DC_INT_FLAG_INT_EOS_0 (0x1UL << DC_INT_FLAG_INT_EOS_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DC_COM_CONFIG BASE+0x2014 *********/ +#define DC_COM_CONFIG_BURST_LEN_RDMA_Pos (4U) +#define DC_COM_CONFIG_BURST_LEN_RDMA_Msk (0x3UL << DC_COM_CONFIG_BURST_LEN_RDMA_Pos) /*!< 0x00000030 */ +#define DC_COM_CONFIG_BURST_LEN_RDMA DC_COM_CONFIG_BURST_LEN_RDMA_Msk +#define DC_COM_CONFIG_BURST_LEN_RDMA_0 (0x1UL << DC_COM_CONFIG_BURST_LEN_RDMA_Pos) /*!< 0x00000010 */ +#define DC_COM_CONFIG_BURST_LEN_RDMA_1 (0x2UL << DC_COM_CONFIG_BURST_LEN_RDMA_Pos) /*!< 0x00000020 */ +#define DC_COM_CONFIG_CH_SEL_Pos (1U) +#define DC_COM_CONFIG_RDMA_CH (0x1UL << DC_COM_CONFIG_CH_SEL_Pos) +/********* Register BitField Details: DC_PCFG_RD_CTRL BASE+0x2018 *********/ +#define DC_PCFG_RD_CTRL_ARQOS_VAL_Pos (1U) +#define DC_PCFG_RD_CTRL_ARQOS_VAL_Msk (0x3UL << DC_PCFG_RD_CTRL_ARQOS_VAL_Pos) /*!< 0x00000006 */ +#define DC_PCFG_RD_CTRL_ARQOS_VAL DC_PCFG_RD_CTRL_ARQOS_VAL_Msk +#define DC_PCFG_RD_CTRL_ARQOS_VAL_0 (0x1UL << DC_PCFG_RD_CTRL_ARQOS_VAL_Pos) /*!< 0x00000002 */ +#define DC_PCFG_RD_CTRL_ARQOS_VAL_1 (0x2UL << DC_PCFG_RD_CTRL_ARQOS_VAL_Pos) /*!< 0x00000004 */ +#define DC_PCFG_RD_CTRL_ARQOS_CTRL_Pos (0U) +#define DC_PCFG_RD_CTRL_ARQOS_CTRL_Msk (0x1UL << DC_PCFG_RD_CTRL_ARQOS_CTRL_Pos) /*!< 0x00000001 */ +#define DC_PCFG_RD_CTRL_ARQOS_CTRL DC_PCFG_RD_CTRL_ARQOS_CTRL_Msk +#define DC_PCFG_RD_CTRL_ARQOS_CTRL_0 (0x1UL << DC_PCFG_RD_CTRL_ARQOS_CTRL_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DC_OFIFO_PCFG BASE+0x2020 *********/ +#define DC_OFIFO_PCFG_PCFG2_Pos (18U) +#define DC_OFIFO_PCFG_PCFG2_Msk (0x1ffUL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x07fc0000 */ +#define DC_OFIFO_PCFG_PCFG2 DC_OFIFO_PCFG_PCFG2_Msk +#define DC_OFIFO_PCFG_PCFG2_0 (0x1UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00040000 */ +#define DC_OFIFO_PCFG_PCFG2_1 (0x2UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00080000 */ +#define DC_OFIFO_PCFG_PCFG2_2 (0x4UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00100000 */ +#define DC_OFIFO_PCFG_PCFG2_3 (0x8UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00200000 */ +#define DC_OFIFO_PCFG_PCFG2_4 (0x10UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00400000 */ +#define DC_OFIFO_PCFG_PCFG2_5 (0x20UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x00800000 */ +#define DC_OFIFO_PCFG_PCFG2_6 (0x40UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x01000000 */ +#define DC_OFIFO_PCFG_PCFG2_7 (0x80UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x02000000 */ +#define DC_OFIFO_PCFG_PCFG2_8 (0x100UL << DC_OFIFO_PCFG_PCFG2_Pos) /*!< 0x04000000 */ +#define DC_OFIFO_PCFG_PCFG1_Pos (9U) +#define DC_OFIFO_PCFG_PCFG1_Msk (0x1ffUL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x0003fe00 */ +#define DC_OFIFO_PCFG_PCFG1 DC_OFIFO_PCFG_PCFG1_Msk +#define DC_OFIFO_PCFG_PCFG1_0 (0x1UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00000200 */ +#define DC_OFIFO_PCFG_PCFG1_1 (0x2UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00000400 */ +#define DC_OFIFO_PCFG_PCFG1_2 (0x4UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00000800 */ +#define DC_OFIFO_PCFG_PCFG1_3 (0x8UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00001000 */ +#define DC_OFIFO_PCFG_PCFG1_4 (0x10UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00002000 */ +#define DC_OFIFO_PCFG_PCFG1_5 (0x20UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00004000 */ +#define DC_OFIFO_PCFG_PCFG1_6 (0x40UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00008000 */ +#define DC_OFIFO_PCFG_PCFG1_7 (0x80UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00010000 */ +#define DC_OFIFO_PCFG_PCFG1_8 (0x100UL << DC_OFIFO_PCFG_PCFG1_Pos) /*!< 0x00020000 */ +#define DC_OFIFO_PCFG_PCFG0_Pos (0U) +#define DC_OFIFO_PCFG_PCFG0_Msk (0x1ffUL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x000001ff */ +#define DC_OFIFO_PCFG_PCFG0 DC_OFIFO_PCFG_PCFG0_Msk +#define DC_OFIFO_PCFG_PCFG0_0 (0x1UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000001 */ +#define DC_OFIFO_PCFG_PCFG0_1 (0x2UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000002 */ +#define DC_OFIFO_PCFG_PCFG0_2 (0x4UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000004 */ +#define DC_OFIFO_PCFG_PCFG0_3 (0x8UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000008 */ +#define DC_OFIFO_PCFG_PCFG0_4 (0x10UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000010 */ +#define DC_OFIFO_PCFG_PCFG0_5 (0x20UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000020 */ +#define DC_OFIFO_PCFG_PCFG0_6 (0x40UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000040 */ +#define DC_OFIFO_PCFG_PCFG0_7 (0x80UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000080 */ +#define DC_OFIFO_PCFG_PCFG0_8 (0x100UL << DC_OFIFO_PCFG_PCFG0_Pos) /*!< 0x00000100 */ + +/********* Register BitField Details: DC_RDMA_DES BASE+0x2114 *********/ +/* There is no BitField Details for RDMA_DES */ + +/********* Register BitField Details: DC_RDMA_CHAIN_SITE BASE+0x2204 *********/ +/* There is no BitField Details for RDMA_CHAIN_SITE */ + +/********* Register BitField Details: DC_RDMA_SITE BASE+0x3110 *********/ +/* There is no BitField Details for RDMA_SITE */ + +/********* Register BitField Details: DISP_COM BASE+0x8000 *********/ +#define DISP_COM_DP_DITHER_DW_Pos (16U) +#define DISP_COM_DP_DITHER_DW_Msk (0x3fUL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x003f0000 */ +#define DISP_COM_DP_DITHER_DW DISP_COM_DP_DITHER_DW_Msk +#define DISP_COM_DP_DITHER_DW_0 (0x1UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00010000 */ +#define DISP_COM_DP_DITHER_DW_1 (0x2UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00020000 */ +#define DISP_COM_DP_DITHER_DW_2 (0x4UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00040000 */ +#define DISP_COM_DP_DITHER_DW_3 (0x8UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00080000 */ +#define DISP_COM_DP_DITHER_DW_4 (0x10UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00100000 */ +#define DISP_COM_DP_DITHER_DW_5 (0x20UL << DISP_COM_DP_DITHER_DW_Pos) /*!< 0x00200000 */ +#define DISP_COM_DITHER_CLKGATE_EN_Pos (7U) +#define DISP_COM_DITHER_CLKGATE_EN_Msk (0x1UL << DISP_COM_DITHER_CLKGATE_EN_Pos) /*!< 0x00000080 */ +#define DISP_COM_DITHER_CLKGATE_EN DISP_COM_DITHER_CLKGATE_EN_Msk +#define DISP_COM_DITHER_CLKGATE_EN_0 (0x1UL << DISP_COM_DITHER_CLKGATE_EN_Pos) /*!< 0x00000080 */ +#define DISP_COM_SLCD_CLKGATE_EN_Pos (6U) +#define DISP_COM_SLCD_CLKGATE_EN_Msk (0x1UL << DISP_COM_SLCD_CLKGATE_EN_Pos) /*!< 0x00000040 */ +#define DISP_COM_SLCD_CLKGATE_EN DISP_COM_SLCD_CLKGATE_EN_Msk +#define DISP_COM_SLCD_CLKGATE_EN_0 (0x1UL << DISP_COM_SLCD_CLKGATE_EN_Pos) /*!< 0x00000040 */ +#define DISP_COM_TFT_CLKGATE_EN_Pos (5U) +#define DISP_COM_TFT_CLKGATE_EN_Msk (0x1UL << DISP_COM_TFT_CLKGATE_EN_Pos) /*!< 0x00000020 */ +#define DISP_COM_TFT_CLKGATE_EN DISP_COM_TFT_CLKGATE_EN_Msk +#define DISP_COM_TFT_CLKGATE_EN_0 (0x1UL << DISP_COM_TFT_CLKGATE_EN_Pos) /*!< 0x00000020 */ +#define DISP_COM_DP_DITHER_EN_Pos (4U) +#define DISP_COM_DP_DITHER_EN_Msk (0x1UL << DISP_COM_DP_DITHER_EN_Pos) /*!< 0x00000010 */ +#define DISP_COM_DP_DITHER_EN DISP_COM_DP_DITHER_EN_Msk +#define DISP_COM_DP_DITHER_EN_0 (0x1UL << DISP_COM_DP_DITHER_EN_Pos) /*!< 0x00000010 */ +#define DISP_COM_DP_IF_SEL_Pos (0U) +#define DISP_COM_DP_IF_SEL_Msk (0x3UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000003 */ +#define DISP_COM_DP_IF_SEL DISP_COM_DP_IF_SEL_Msk +#define DISP_COM_DP_IF_SEL_0 (0x1UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000001 */ +#define DISP_COM_DP_IF_SEL_1 (0x2UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: TFT_TIMING_HSYNC BASE+0x9000 *********/ +#define TFT_TIMING_HSYNC_HPS_Pos (16U) +#define TFT_TIMING_HSYNC_HPS_Msk (0xfffUL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x0fff0000 */ +#define TFT_TIMING_HSYNC_HPS TFT_TIMING_HSYNC_HPS_Msk +#define TFT_TIMING_HSYNC_HPS_0 (0x1UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00010000 */ +#define TFT_TIMING_HSYNC_HPS_1 (0x2UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00020000 */ +#define TFT_TIMING_HSYNC_HPS_2 (0x4UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00040000 */ +#define TFT_TIMING_HSYNC_HPS_3 (0x8UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00080000 */ +#define TFT_TIMING_HSYNC_HPS_4 (0x10UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00100000 */ +#define TFT_TIMING_HSYNC_HPS_5 (0x20UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00200000 */ +#define TFT_TIMING_HSYNC_HPS_6 (0x40UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00400000 */ +#define TFT_TIMING_HSYNC_HPS_7 (0x80UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x00800000 */ +#define TFT_TIMING_HSYNC_HPS_8 (0x100UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x01000000 */ +#define TFT_TIMING_HSYNC_HPS_9 (0x200UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x02000000 */ +#define TFT_TIMING_HSYNC_HPS_10 (0x400UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x04000000 */ +#define TFT_TIMING_HSYNC_HPS_11 (0x800UL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x08000000 */ +#define TFT_TIMING_HSYNC_HPE_Pos (0U) +#define TFT_TIMING_HSYNC_HPE_Msk (0xfffUL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000fff */ +#define TFT_TIMING_HSYNC_HPE TFT_TIMING_HSYNC_HPE_Msk +#define TFT_TIMING_HSYNC_HPE_0 (0x1UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000001 */ +#define TFT_TIMING_HSYNC_HPE_1 (0x2UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000002 */ +#define TFT_TIMING_HSYNC_HPE_2 (0x4UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000004 */ +#define TFT_TIMING_HSYNC_HPE_3 (0x8UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000008 */ +#define TFT_TIMING_HSYNC_HPE_4 (0x10UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000010 */ +#define TFT_TIMING_HSYNC_HPE_5 (0x20UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000020 */ +#define TFT_TIMING_HSYNC_HPE_6 (0x40UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000040 */ +#define TFT_TIMING_HSYNC_HPE_7 (0x80UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000080 */ +#define TFT_TIMING_HSYNC_HPE_8 (0x100UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000100 */ +#define TFT_TIMING_HSYNC_HPE_9 (0x200UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000200 */ +#define TFT_TIMING_HSYNC_HPE_10 (0x400UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000400 */ +#define TFT_TIMING_HSYNC_HPE_11 (0x800UL << TFT_TIMING_HSYNC_HPE_Pos) /*!< 0x00000800 */ + +/********* Register BitField Details: TFT_TIMING_VSYNC BASE+0x9004 *********/ +#define TFT_TIMING_VSYNC_VPS_Pos (16U) +#define TFT_TIMING_VSYNC_VPS_Msk (0xfffUL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x0fff0000 */ +#define TFT_TIMING_VSYNC_VPS TFT_TIMING_VSYNC_VPS_Msk +#define TFT_TIMING_VSYNC_VPS_0 (0x1UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00010000 */ +#define TFT_TIMING_VSYNC_VPS_1 (0x2UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00020000 */ +#define TFT_TIMING_VSYNC_VPS_2 (0x4UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00040000 */ +#define TFT_TIMING_VSYNC_VPS_3 (0x8UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00080000 */ +#define TFT_TIMING_VSYNC_VPS_4 (0x10UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00100000 */ +#define TFT_TIMING_VSYNC_VPS_5 (0x20UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00200000 */ +#define TFT_TIMING_VSYNC_VPS_6 (0x40UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00400000 */ +#define TFT_TIMING_VSYNC_VPS_7 (0x80UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x00800000 */ +#define TFT_TIMING_VSYNC_VPS_8 (0x100UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x01000000 */ +#define TFT_TIMING_VSYNC_VPS_9 (0x200UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x02000000 */ +#define TFT_TIMING_VSYNC_VPS_10 (0x400UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x04000000 */ +#define TFT_TIMING_VSYNC_VPS_11 (0x800UL << TFT_TIMING_VSYNC_VPS_Pos) /*!< 0x08000000 */ +#define TFT_TIMING_VSYNC_VPE_Pos (0U) +#define TFT_TIMING_VSYNC_VPE_Msk (0xfffUL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000fff */ +#define TFT_TIMING_VSYNC_VPE TFT_TIMING_VSYNC_VPE_Msk +#define TFT_TIMING_VSYNC_VPE_0 (0x1UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000001 */ +#define TFT_TIMING_VSYNC_VPE_1 (0x2UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000002 */ +#define TFT_TIMING_VSYNC_VPE_2 (0x4UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000004 */ +#define TFT_TIMING_VSYNC_VPE_3 (0x8UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000008 */ +#define TFT_TIMING_VSYNC_VPE_4 (0x10UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000010 */ +#define TFT_TIMING_VSYNC_VPE_5 (0x20UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000020 */ +#define TFT_TIMING_VSYNC_VPE_6 (0x40UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000040 */ +#define TFT_TIMING_VSYNC_VPE_7 (0x80UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000080 */ +#define TFT_TIMING_VSYNC_VPE_8 (0x100UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000100 */ +#define TFT_TIMING_VSYNC_VPE_9 (0x200UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000200 */ +#define TFT_TIMING_VSYNC_VPE_10 (0x400UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000400 */ +#define TFT_TIMING_VSYNC_VPE_11 (0x800UL << TFT_TIMING_VSYNC_VPE_Pos) /*!< 0x00000800 */ + +/********* Register BitField Details: TFT_TIMING_HDE BASE+0x9008 *********/ +#define TFT_TIMING_HDE_HDS_Pos (16U) +#define TFT_TIMING_HDE_HDS_Msk (0x1fffUL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x1fff0000 */ +#define TFT_TIMING_HDE_HDS TFT_TIMING_HDE_HDS_Msk +#define TFT_TIMING_HDE_HDS_0 (0x1UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00010000 */ +#define TFT_TIMING_HDE_HDS_1 (0x2UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00020000 */ +#define TFT_TIMING_HDE_HDS_2 (0x4UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00040000 */ +#define TFT_TIMING_HDE_HDS_3 (0x8UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00080000 */ +#define TFT_TIMING_HDE_HDS_4 (0x10UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00100000 */ +#define TFT_TIMING_HDE_HDS_5 (0x20UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00200000 */ +#define TFT_TIMING_HDE_HDS_6 (0x40UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00400000 */ +#define TFT_TIMING_HDE_HDS_7 (0x80UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x00800000 */ +#define TFT_TIMING_HDE_HDS_8 (0x100UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x01000000 */ +#define TFT_TIMING_HDE_HDS_9 (0x200UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x02000000 */ +#define TFT_TIMING_HDE_HDS_10 (0x400UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x04000000 */ +#define TFT_TIMING_HDE_HDS_11 (0x800UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x08000000 */ +#define TFT_TIMING_HDE_HDS_12 (0x1000UL << TFT_TIMING_HDE_HDS_Pos) /*!< 0x10000000 */ +#define TFT_TIMING_HDE_HDE_Pos (0U) +#define TFT_TIMING_HDE_HDE_Msk (0xfffUL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000fff */ +#define TFT_TIMING_HDE_HDE TFT_TIMING_HDE_HDE_Msk +#define TFT_TIMING_HDE_HDE_0 (0x1UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000001 */ +#define TFT_TIMING_HDE_HDE_1 (0x2UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000002 */ +#define TFT_TIMING_HDE_HDE_2 (0x4UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000004 */ +#define TFT_TIMING_HDE_HDE_3 (0x8UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000008 */ +#define TFT_TIMING_HDE_HDE_4 (0x10UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000010 */ +#define TFT_TIMING_HDE_HDE_5 (0x20UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000020 */ +#define TFT_TIMING_HDE_HDE_6 (0x40UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000040 */ +#define TFT_TIMING_HDE_HDE_7 (0x80UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000080 */ +#define TFT_TIMING_HDE_HDE_8 (0x100UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000100 */ +#define TFT_TIMING_HDE_HDE_9 (0x200UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000200 */ +#define TFT_TIMING_HDE_HDE_10 (0x400UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000400 */ +#define TFT_TIMING_HDE_HDE_11 (0x800UL << TFT_TIMING_HDE_HDE_Pos) /*!< 0x00000800 */ + +/********* Register BitField Details: TFT_TIMING_VDE BASE+0x900C *********/ +#define TFT_TIMING_VDE_VDS_Pos (16U) +#define TFT_TIMING_VDE_VDS_Msk (0xfffUL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x0fff0000 */ +#define TFT_TIMING_VDE_VDS TFT_TIMING_VDE_VDS_Msk +#define TFT_TIMING_VDE_VDS_0 (0x1UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00010000 */ +#define TFT_TIMING_VDE_VDS_1 (0x2UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00020000 */ +#define TFT_TIMING_VDE_VDS_2 (0x4UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00040000 */ +#define TFT_TIMING_VDE_VDS_3 (0x8UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00080000 */ +#define TFT_TIMING_VDE_VDS_4 (0x10UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00100000 */ +#define TFT_TIMING_VDE_VDS_5 (0x20UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00200000 */ +#define TFT_TIMING_VDE_VDS_6 (0x40UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00400000 */ +#define TFT_TIMING_VDE_VDS_7 (0x80UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x00800000 */ +#define TFT_TIMING_VDE_VDS_8 (0x100UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x01000000 */ +#define TFT_TIMING_VDE_VDS_9 (0x200UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x02000000 */ +#define TFT_TIMING_VDE_VDS_10 (0x400UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x04000000 */ +#define TFT_TIMING_VDE_VDS_11 (0x800UL << TFT_TIMING_VDE_VDS_Pos) /*!< 0x08000000 */ +#define TFT_TIMING_VDE_VDE_Pos (0U) +#define TFT_TIMING_VDE_VDE_Msk (0xfffUL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000fff */ +#define TFT_TIMING_VDE_VDE TFT_TIMING_VDE_VDE_Msk +#define TFT_TIMING_VDE_VDE_0 (0x1UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000001 */ +#define TFT_TIMING_VDE_VDE_1 (0x2UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000002 */ +#define TFT_TIMING_VDE_VDE_2 (0x4UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000004 */ +#define TFT_TIMING_VDE_VDE_3 (0x8UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000008 */ +#define TFT_TIMING_VDE_VDE_4 (0x10UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000010 */ +#define TFT_TIMING_VDE_VDE_5 (0x20UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000020 */ +#define TFT_TIMING_VDE_VDE_6 (0x40UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000040 */ +#define TFT_TIMING_VDE_VDE_7 (0x80UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000080 */ +#define TFT_TIMING_VDE_VDE_8 (0x100UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000100 */ +#define TFT_TIMING_VDE_VDE_9 (0x200UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000200 */ +#define TFT_TIMING_VDE_VDE_10 (0x400UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000400 */ +#define TFT_TIMING_VDE_VDE_11 (0x800UL << TFT_TIMING_VDE_VDE_Pos) /*!< 0x00000800 */ + +/********* Register BitField Details: TFT_TRAN_CFG BASE+0x9010 *********/ +#define TFT_TRAN_CFG_COLOR_EVEN_Pos (19U) +#define TFT_TRAN_CFG_COLOR_EVEN_Msk (0x7UL << TFT_TRAN_CFG_COLOR_EVEN_Pos) /*!< 0x00380000 */ +#define TFT_TRAN_CFG_COLOR_EVEN TFT_TRAN_CFG_COLOR_EVEN_Msk +#define TFT_TRAN_CFG_COLOR_EVEN_0 (0x1UL << TFT_TRAN_CFG_COLOR_EVEN_Pos) /*!< 0x00080000 */ +#define TFT_TRAN_CFG_COLOR_EVEN_1 (0x2UL << TFT_TRAN_CFG_COLOR_EVEN_Pos) /*!< 0x00100000 */ +#define TFT_TRAN_CFG_COLOR_EVEN_2 (0x4UL << TFT_TRAN_CFG_COLOR_EVEN_Pos) /*!< 0x00200000 */ +#define TFT_TRAN_CFG_COLOR_ODD_Pos (16U) +#define TFT_TRAN_CFG_COLOR_ODD_Msk (0x7UL << TFT_TRAN_CFG_COLOR_ODD_Pos) /*!< 0x00070000 */ +#define TFT_TRAN_CFG_COLOR_ODD TFT_TRAN_CFG_COLOR_ODD_Msk +#define TFT_TRAN_CFG_COLOR_ODD_0 (0x1UL << TFT_TRAN_CFG_COLOR_ODD_Pos) /*!< 0x00010000 */ +#define TFT_TRAN_CFG_COLOR_ODD_1 (0x2UL << TFT_TRAN_CFG_COLOR_ODD_Pos) /*!< 0x00020000 */ +#define TFT_TRAN_CFG_COLOR_ODD_2 (0x4UL << TFT_TRAN_CFG_COLOR_ODD_Pos) /*!< 0x00040000 */ +#define TFT_TRAN_CFG_PIX_CLK_INV_Pos (10U) +#define TFT_TRAN_CFG_PIX_CLK_INV_Msk (0x1UL << TFT_TRAN_CFG_PIX_CLK_INV_Pos) /*!< 0x00000400 */ +#define TFT_TRAN_CFG_PIX_CLK_INV TFT_TRAN_CFG_PIX_CLK_INV_Msk +#define TFT_TRAN_CFG_PIX_CLK_INV_0 (0x1UL << TFT_TRAN_CFG_PIX_CLK_INV_Pos) /*!< 0x00000400 */ +#define TFT_TRAN_CFG_DE_DL_Pos (9U) +#define TFT_TRAN_CFG_DE_DL_Msk (0x1UL << TFT_TRAN_CFG_DE_DL_Pos) /*!< 0x00000200 */ +#define TFT_TRAN_CFG_DE_DL TFT_TRAN_CFG_DE_DL_Msk +#define TFT_TRAN_CFG_DE_DL_0 (0x1UL << TFT_TRAN_CFG_DE_DL_Pos) /*!< 0x00000200 */ +#define TFT_TRAN_CFG_HSYNC_DL_Pos (8U) +#define TFT_TRAN_CFG_HSYNC_DL_Msk (0x1UL << TFT_TRAN_CFG_HSYNC_DL_Pos) /*!< 0x00000100 */ +#define TFT_TRAN_CFG_HSYNC_DL TFT_TRAN_CFG_HSYNC_DL_Msk +#define TFT_TRAN_CFG_HSYNC_DL_0 (0x1UL << TFT_TRAN_CFG_HSYNC_DL_Pos) /*!< 0x00000100 */ +#define TFT_TRAN_CFG_VSYNC_DL_Pos (7U) +#define TFT_TRAN_CFG_VSYNC_DL_Msk (0x1UL << TFT_TRAN_CFG_VSYNC_DL_Pos) /*!< 0x00000080 */ +#define TFT_TRAN_CFG_VSYNC_DL TFT_TRAN_CFG_VSYNC_DL_Msk +#define TFT_TRAN_CFG_VSYNC_DL_0 (0x1UL << TFT_TRAN_CFG_VSYNC_DL_Pos) /*!< 0x00000080 */ +#define TFT_TRAN_CFG_MODE_Pos (0U) +#define TFT_TRAN_CFG_MODE_Msk (0x7UL << TFT_TRAN_CFG_MODE_Pos) /*!< 0x00000007 */ +#define TFT_TRAN_CFG_MODE TFT_TRAN_CFG_MODE_Msk +#define TFT_TRAN_CFG_MODE_0 (0x1UL << TFT_TRAN_CFG_MODE_Pos) /*!< 0x00000001 */ +#define TFT_TRAN_CFG_MODE_1 (0x2UL << TFT_TRAN_CFG_MODE_Pos) /*!< 0x00000002 */ +#define TFT_TRAN_CFG_MODE_2 (0x4UL << TFT_TRAN_CFG_MODE_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: TFT_ST BASE+0x9014 *********/ +#define TFT_ST_WORKING_Pos (1U) +#define TFT_ST_WORKING_Msk (0x1UL << TFT_ST_WORKING_Pos) /*!< 0x00000002 */ +#define TFT_ST_WORKING TFT_ST_WORKING_Msk +#define TFT_ST_WORKING_0 (0x1UL << TFT_ST_WORKING_Pos) /*!< 0x00000002 */ +#define TFT_ST_UNDER_Pos (0U) +#define TFT_ST_UNDER_Msk (0x1UL << TFT_ST_UNDER_Pos) /*!< 0x00000001 */ +#define TFT_ST_UNDER TFT_ST_UNDER_Msk +#define TFT_ST_UNDER_0 (0x1UL << TFT_ST_UNDER_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: SLCD_PANEL_CFG BASE+0xA000 *********/ +#define SLCD_PANEL_CFG_RDY_ANTI_JIT_Pos (27U) +#define SLCD_PANEL_CFG_RDY_ANTI_JIT_Msk (0x1UL << SLCD_PANEL_CFG_RDY_ANTI_JIT_Pos) /*!< 0x08000000 */ +#define SLCD_PANEL_CFG_RDY_ANTI_JIT SLCD_PANEL_CFG_RDY_ANTI_JIT_Msk +#define SLCD_PANEL_CFG_RDY_ANTI_JIT_0 (0x1UL << SLCD_PANEL_CFG_RDY_ANTI_JIT_Pos) /*!< 0x08000000 */ +#define SLCD_PANEL_CFG_FMT_EN_Pos (26U) +#define SLCD_PANEL_CFG_FMT_EN_Msk (0x1UL << SLCD_PANEL_CFG_FMT_EN_Pos) /*!< 0x04000000 */ +#define SLCD_PANEL_CFG_FMT_EN SLCD_PANEL_CFG_FMT_EN_Msk +#define SLCD_PANEL_CFG_FMT_EN_0 (0x1UL << SLCD_PANEL_CFG_FMT_EN_Pos) /*!< 0x04000000 */ +#define SLCD_PANEL_CFG_DBI_TYPE_Pos (23U) +#define SLCD_PANEL_CFG_DBI_TYPE_Msk (0x7UL << SLCD_PANEL_CFG_DBI_TYPE_Pos) /*!< 0x03800000 */ +#define SLCD_PANEL_CFG_DBI_TYPE SLCD_PANEL_CFG_DBI_TYPE_Msk +#define SLCD_PANEL_CFG_DBI_TYPE_0 (0x1UL << SLCD_PANEL_CFG_DBI_TYPE_Pos) /*!< 0x00800000 */ +#define SLCD_PANEL_CFG_DBI_TYPE_1 (0x2UL << SLCD_PANEL_CFG_DBI_TYPE_Pos) /*!< 0x01000000 */ +#define SLCD_PANEL_CFG_DBI_TYPE_2 (0x4UL << SLCD_PANEL_CFG_DBI_TYPE_Pos) /*!< 0x02000000 */ +#define SLCD_PANEL_CFG_PIX_FMT_Pos (21U) +#define SLCD_PANEL_CFG_PIX_FMT_Msk (0x3UL << SLCD_PANEL_CFG_PIX_FMT_Pos) /*!< 0x00600000 */ +#define SLCD_PANEL_CFG_PIX_FMT SLCD_PANEL_CFG_PIX_FMT_Msk +#define SLCD_PANEL_CFG_PIX_FMT_0 (0x1UL << SLCD_PANEL_CFG_PIX_FMT_Pos) /*!< 0x00200000 */ +#define SLCD_PANEL_CFG_PIX_FMT_1 (0x2UL << SLCD_PANEL_CFG_PIX_FMT_Pos) /*!< 0x00400000 */ +#define SLCD_PANEL_CFG_TE_ANTI_JIT_Pos (20U) +#define SLCD_PANEL_CFG_TE_ANTI_JIT_Msk (0x1UL << SLCD_PANEL_CFG_TE_ANTI_JIT_Pos) /*!< 0x00100000 */ +#define SLCD_PANEL_CFG_TE_ANTI_JIT SLCD_PANEL_CFG_TE_ANTI_JIT_Msk +#define SLCD_PANEL_CFG_TE_ANTI_JIT_0 (0x1UL << SLCD_PANEL_CFG_TE_ANTI_JIT_Pos) /*!< 0x00100000 */ +#define SLCD_PANEL_CFG_TE_MD_Pos (19U) +#define SLCD_PANEL_CFG_TE_MD_Msk (0x1UL << SLCD_PANEL_CFG_TE_MD_Pos) /*!< 0x00080000 */ +#define SLCD_PANEL_CFG_TE_MD SLCD_PANEL_CFG_TE_MD_Msk +#define SLCD_PANEL_CFG_TE_MD_0 (0x1UL << SLCD_PANEL_CFG_TE_MD_Pos) /*!< 0x00080000 */ +#define SLCD_PANEL_CFG_TE_SWITCH_Pos (18U) +#define SLCD_PANEL_CFG_TE_SWITCH_Msk (0x1UL << SLCD_PANEL_CFG_TE_SWITCH_Pos) /*!< 0x00040000 */ +#define SLCD_PANEL_CFG_TE_SWITCH SLCD_PANEL_CFG_TE_SWITCH_Msk +#define SLCD_PANEL_CFG_TE_SWITCH_0 (0x1UL << SLCD_PANEL_CFG_TE_SWITCH_Pos) /*!< 0x00040000 */ +#define SLCD_PANEL_CFG_RDY_SWITCH_Pos (17U) +#define SLCD_PANEL_CFG_RDY_SWITCH_Msk (0x1UL << SLCD_PANEL_CFG_RDY_SWITCH_Pos) /*!< 0x00020000 */ +#define SLCD_PANEL_CFG_RDY_SWITCH SLCD_PANEL_CFG_RDY_SWITCH_Msk +#define SLCD_PANEL_CFG_RDY_SWITCH_0 (0x1UL << SLCD_PANEL_CFG_RDY_SWITCH_Pos) /*!< 0x00020000 */ +#define SLCD_PANEL_CFG_CS_EN_Pos (16U) +#define SLCD_PANEL_CFG_CS_EN_Msk (0x1UL << SLCD_PANEL_CFG_CS_EN_Pos) /*!< 0x00010000 */ +#define SLCD_PANEL_CFG_CS_EN SLCD_PANEL_CFG_CS_EN_Msk +#define SLCD_PANEL_CFG_CS_EN_0 (0x1UL << SLCD_PANEL_CFG_CS_EN_Pos) /*!< 0x00010000 */ +#define SLCD_PANEL_CFG_CS_DP_Pos (11U) +#define SLCD_PANEL_CFG_CS_DP_Msk (0x1UL << SLCD_PANEL_CFG_CS_DP_Pos) /*!< 0x00000800 */ +#define SLCD_PANEL_CFG_CS_DP SLCD_PANEL_CFG_CS_DP_Msk +#define SLCD_PANEL_CFG_CS_DP_0 (0x1UL << SLCD_PANEL_CFG_CS_DP_Pos) /*!< 0x00000800 */ +#define SLCD_PANEL_CFG_RDY_DP_Pos (10U) +#define SLCD_PANEL_CFG_RDY_DP_Msk (0x1UL << SLCD_PANEL_CFG_RDY_DP_Pos) /*!< 0x00000400 */ +#define SLCD_PANEL_CFG_RDY_DP SLCD_PANEL_CFG_RDY_DP_Msk +#define SLCD_PANEL_CFG_RDY_DP_0 (0x1UL << SLCD_PANEL_CFG_RDY_DP_Pos) /*!< 0x00000400 */ +#define SLCD_PANEL_CFG_DC_MD_Pos (9U) +#define SLCD_PANEL_CFG_DC_MD_Msk (0x1UL << SLCD_PANEL_CFG_DC_MD_Pos) /*!< 0x00000200 */ +#define SLCD_PANEL_CFG_DC_MD SLCD_PANEL_CFG_DC_MD_Msk +#define SLCD_PANEL_CFG_DC_MD_0 (0x1UL << SLCD_PANEL_CFG_DC_MD_Pos) /*!< 0x00000200 */ +#define SLCD_PANEL_CFG_WR_MD_Pos (8U) +#define SLCD_PANEL_CFG_WR_MD_Msk (0x1UL << SLCD_PANEL_CFG_WR_MD_Pos) /*!< 0x00000100 */ +#define SLCD_PANEL_CFG_WR_MD SLCD_PANEL_CFG_WR_MD_Msk +#define SLCD_PANEL_CFG_WR_MD_0 (0x1UL << SLCD_PANEL_CFG_WR_MD_Pos) /*!< 0x00000100 */ +#define SLCD_PANEL_CFG_TE_DP_Pos (6U) +#define SLCD_PANEL_CFG_TE_DP_Msk (0x1UL << SLCD_PANEL_CFG_TE_DP_Pos) /*!< 0x00000040 */ +#define SLCD_PANEL_CFG_TE_DP SLCD_PANEL_CFG_TE_DP_Msk +#define SLCD_PANEL_CFG_TE_DP_0 (0x1UL << SLCD_PANEL_CFG_TE_DP_Pos) /*!< 0x00000040 */ +#define SLCD_PANEL_CFG_DWIDTH_Pos (3U) +#define SLCD_PANEL_CFG_DWIDTH_Msk (0x7UL << SLCD_PANEL_CFG_DWIDTH_Pos) /*!< 0x00000038 */ +#define SLCD_PANEL_CFG_DWIDTH SLCD_PANEL_CFG_DWIDTH_Msk +#define SLCD_PANEL_CFG_DWIDTH_0 (0x1UL << SLCD_PANEL_CFG_DWIDTH_Pos) /*!< 0x00000008 */ +#define SLCD_PANEL_CFG_DWIDTH_1 (0x2UL << SLCD_PANEL_CFG_DWIDTH_Pos) /*!< 0x00000010 */ +#define SLCD_PANEL_CFG_DWIDTH_2 (0x4UL << SLCD_PANEL_CFG_DWIDTH_Pos) /*!< 0x00000020 */ +#define SLCD_PANEL_CFG_CWIDTH_Pos (0U) +#define SLCD_PANEL_CFG_CWIDTH_Msk (0x7UL << SLCD_PANEL_CFG_CWIDTH_Pos) /*!< 0x00000007 */ +#define SLCD_PANEL_CFG_CWIDTH SLCD_PANEL_CFG_CWIDTH_Msk +#define SLCD_PANEL_CFG_CWIDTH_0 (0x1UL << SLCD_PANEL_CFG_CWIDTH_Pos) /*!< 0x00000001 */ +#define SLCD_PANEL_CFG_CWIDTH_1 (0x2UL << SLCD_PANEL_CFG_CWIDTH_Pos) /*!< 0x00000002 */ +#define SLCD_PANEL_CFG_CWIDTH_2 (0x4UL << SLCD_PANEL_CFG_CWIDTH_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: SLCD_WR_DUTY BASE+0xA004 *********/ +#define SLCD_WR_DUTY_DSTIME_Pos (24U) +#define SLCD_WR_DUTY_DSTIME_Msk (0xffUL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0xff000000 */ +#define SLCD_WR_DUTY_DSTIME SLCD_WR_DUTY_DSTIME_Msk +#define SLCD_WR_DUTY_DSTIME_0 (0x1UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x01000000 */ +#define SLCD_WR_DUTY_DSTIME_1 (0x2UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x02000000 */ +#define SLCD_WR_DUTY_DSTIME_2 (0x4UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x04000000 */ +#define SLCD_WR_DUTY_DSTIME_3 (0x8UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x08000000 */ +#define SLCD_WR_DUTY_DSTIME_4 (0x10UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x10000000 */ +#define SLCD_WR_DUTY_DSTIME_5 (0x20UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x20000000 */ +#define SLCD_WR_DUTY_DSTIME_6 (0x40UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x40000000 */ +#define SLCD_WR_DUTY_DSTIME_7 (0x80UL << SLCD_WR_DUTY_DSTIME_Pos) /*!< 0x80000000 */ +#define SLCD_WR_DUTY_DDTIME_Pos (16U) +#define SLCD_WR_DUTY_DDTIME_Msk (0xffUL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00ff0000 */ +#define SLCD_WR_DUTY_DDTIME SLCD_WR_DUTY_DDTIME_Msk +#define SLCD_WR_DUTY_DDTIME_0 (0x1UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00010000 */ +#define SLCD_WR_DUTY_DDTIME_1 (0x2UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00020000 */ +#define SLCD_WR_DUTY_DDTIME_2 (0x4UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00040000 */ +#define SLCD_WR_DUTY_DDTIME_3 (0x8UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00080000 */ +#define SLCD_WR_DUTY_DDTIME_4 (0x10UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00100000 */ +#define SLCD_WR_DUTY_DDTIME_5 (0x20UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00200000 */ +#define SLCD_WR_DUTY_DDTIME_6 (0x40UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00400000 */ +#define SLCD_WR_DUTY_DDTIME_7 (0x80UL << SLCD_WR_DUTY_DDTIME_Pos) /*!< 0x00800000 */ +#define SLCD_WR_DUTY_CSTIME_Pos (8U) +#define SLCD_WR_DUTY_CSTIME_Msk (0xffUL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x0000ff00 */ +#define SLCD_WR_DUTY_CSTIME SLCD_WR_DUTY_CSTIME_Msk +#define SLCD_WR_DUTY_CSTIME_0 (0x1UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00000100 */ +#define SLCD_WR_DUTY_CSTIME_1 (0x2UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00000200 */ +#define SLCD_WR_DUTY_CSTIME_2 (0x4UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00000400 */ +#define SLCD_WR_DUTY_CSTIME_3 (0x8UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00000800 */ +#define SLCD_WR_DUTY_CSTIME_4 (0x10UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00001000 */ +#define SLCD_WR_DUTY_CSTIME_5 (0x20UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00002000 */ +#define SLCD_WR_DUTY_CSTIME_6 (0x40UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00004000 */ +#define SLCD_WR_DUTY_CSTIME_7 (0x80UL << SLCD_WR_DUTY_CSTIME_Pos) /*!< 0x00008000 */ +#define SLCD_WR_DUTY_CDTIME_Pos (0U) +#define SLCD_WR_DUTY_CDTIME_Msk (0xffUL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x000000ff */ +#define SLCD_WR_DUTY_CDTIME SLCD_WR_DUTY_CDTIME_Msk +#define SLCD_WR_DUTY_CDTIME_0 (0x1UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000001 */ +#define SLCD_WR_DUTY_CDTIME_1 (0x2UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000002 */ +#define SLCD_WR_DUTY_CDTIME_2 (0x4UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000004 */ +#define SLCD_WR_DUTY_CDTIME_3 (0x8UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000008 */ +#define SLCD_WR_DUTY_CDTIME_4 (0x10UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000010 */ +#define SLCD_WR_DUTY_CDTIME_5 (0x20UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000020 */ +#define SLCD_WR_DUTY_CDTIME_6 (0x40UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000040 */ +#define SLCD_WR_DUTY_CDTIME_7 (0x80UL << SLCD_WR_DUTY_CDTIME_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: SLCD_TIMING BASE+0xA008 *********/ +#define SLCD_TIMING_TCH_Pos (24U) +#define SLCD_TIMING_TCH_Msk (0xffUL << SLCD_TIMING_TCH_Pos) /*!< 0xff000000 */ +#define SLCD_TIMING_TCH SLCD_TIMING_TCH_Msk +#define SLCD_TIMING_TCH_0 (0x1UL << SLCD_TIMING_TCH_Pos) /*!< 0x01000000 */ +#define SLCD_TIMING_TCH_1 (0x2UL << SLCD_TIMING_TCH_Pos) /*!< 0x02000000 */ +#define SLCD_TIMING_TCH_2 (0x4UL << SLCD_TIMING_TCH_Pos) /*!< 0x04000000 */ +#define SLCD_TIMING_TCH_3 (0x8UL << SLCD_TIMING_TCH_Pos) /*!< 0x08000000 */ +#define SLCD_TIMING_TCH_4 (0x10UL << SLCD_TIMING_TCH_Pos) /*!< 0x10000000 */ +#define SLCD_TIMING_TCH_5 (0x20UL << SLCD_TIMING_TCH_Pos) /*!< 0x20000000 */ +#define SLCD_TIMING_TCH_6 (0x40UL << SLCD_TIMING_TCH_Pos) /*!< 0x40000000 */ +#define SLCD_TIMING_TCH_7 (0x80UL << SLCD_TIMING_TCH_Pos) /*!< 0x80000000 */ +#define SLCD_TIMING_TCS_Pos (16U) +#define SLCD_TIMING_TCS_Msk (0xffUL << SLCD_TIMING_TCS_Pos) /*!< 0x00ff0000 */ +#define SLCD_TIMING_TCS SLCD_TIMING_TCS_Msk +#define SLCD_TIMING_TCS_0 (0x1UL << SLCD_TIMING_TCS_Pos) /*!< 0x00010000 */ +#define SLCD_TIMING_TCS_1 (0x2UL << SLCD_TIMING_TCS_Pos) /*!< 0x00020000 */ +#define SLCD_TIMING_TCS_2 (0x4UL << SLCD_TIMING_TCS_Pos) /*!< 0x00040000 */ +#define SLCD_TIMING_TCS_3 (0x8UL << SLCD_TIMING_TCS_Pos) /*!< 0x00080000 */ +#define SLCD_TIMING_TCS_4 (0x10UL << SLCD_TIMING_TCS_Pos) /*!< 0x00100000 */ +#define SLCD_TIMING_TCS_5 (0x20UL << SLCD_TIMING_TCS_Pos) /*!< 0x00200000 */ +#define SLCD_TIMING_TCS_6 (0x40UL << SLCD_TIMING_TCS_Pos) /*!< 0x00400000 */ +#define SLCD_TIMING_TCS_7 (0x80UL << SLCD_TIMING_TCS_Pos) /*!< 0x00800000 */ +#define SLCD_TIMING_TAH_Pos (8U) +#define SLCD_TIMING_TAH_Msk (0xffUL << SLCD_TIMING_TAH_Pos) /*!< 0x0000ff00 */ +#define SLCD_TIMING_TAH SLCD_TIMING_TAH_Msk +#define SLCD_TIMING_TAH_0 (0x1UL << SLCD_TIMING_TAH_Pos) /*!< 0x00000100 */ +#define SLCD_TIMING_TAH_1 (0x2UL << SLCD_TIMING_TAH_Pos) /*!< 0x00000200 */ +#define SLCD_TIMING_TAH_2 (0x4UL << SLCD_TIMING_TAH_Pos) /*!< 0x00000400 */ +#define SLCD_TIMING_TAH_3 (0x8UL << SLCD_TIMING_TAH_Pos) /*!< 0x00000800 */ +#define SLCD_TIMING_TAH_4 (0x10UL << SLCD_TIMING_TAH_Pos) /*!< 0x00001000 */ +#define SLCD_TIMING_TAH_5 (0x20UL << SLCD_TIMING_TAH_Pos) /*!< 0x00002000 */ +#define SLCD_TIMING_TAH_6 (0x40UL << SLCD_TIMING_TAH_Pos) /*!< 0x00004000 */ +#define SLCD_TIMING_TAH_7 (0x80UL << SLCD_TIMING_TAH_Pos) /*!< 0x00008000 */ +#define SLCD_TIMING_TAS_Pos (0U) +#define SLCD_TIMING_TAS_Msk (0xffUL << SLCD_TIMING_TAS_Pos) /*!< 0x000000ff */ +#define SLCD_TIMING_TAS SLCD_TIMING_TAS_Msk +#define SLCD_TIMING_TAS_0 (0x1UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000001 */ +#define SLCD_TIMING_TAS_1 (0x2UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000002 */ +#define SLCD_TIMING_TAS_2 (0x4UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000004 */ +#define SLCD_TIMING_TAS_3 (0x8UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000008 */ +#define SLCD_TIMING_TAS_4 (0x10UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000010 */ +#define SLCD_TIMING_TAS_5 (0x20UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000020 */ +#define SLCD_TIMING_TAS_6 (0x40UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000040 */ +#define SLCD_TIMING_TAS_7 (0x80UL << SLCD_TIMING_TAS_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: SLCD_FRM_SIZE BASE+0xA00C *********/ +#define SLCD_FRM_SIZE_V_SIZE_Pos (16U) +#define SLCD_FRM_SIZE_V_SIZE_Msk (0xffffUL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0xffff0000 */ +#define SLCD_FRM_SIZE_V_SIZE SLCD_FRM_SIZE_V_SIZE_Msk +#define SLCD_FRM_SIZE_V_SIZE_0 (0x1UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00010000 */ +#define SLCD_FRM_SIZE_V_SIZE_1 (0x2UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00020000 */ +#define SLCD_FRM_SIZE_V_SIZE_2 (0x4UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00040000 */ +#define SLCD_FRM_SIZE_V_SIZE_3 (0x8UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00080000 */ +#define SLCD_FRM_SIZE_V_SIZE_4 (0x10UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00100000 */ +#define SLCD_FRM_SIZE_V_SIZE_5 (0x20UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00200000 */ +#define SLCD_FRM_SIZE_V_SIZE_6 (0x40UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00400000 */ +#define SLCD_FRM_SIZE_V_SIZE_7 (0x80UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x00800000 */ +#define SLCD_FRM_SIZE_V_SIZE_8 (0x100UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x01000000 */ +#define SLCD_FRM_SIZE_V_SIZE_9 (0x200UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x02000000 */ +#define SLCD_FRM_SIZE_V_SIZE_10 (0x400UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x04000000 */ +#define SLCD_FRM_SIZE_V_SIZE_11 (0x800UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x08000000 */ +#define SLCD_FRM_SIZE_V_SIZE_12 (0x1000UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x10000000 */ +#define SLCD_FRM_SIZE_V_SIZE_13 (0x2000UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x20000000 */ +#define SLCD_FRM_SIZE_V_SIZE_14 (0x4000UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x40000000 */ +#define SLCD_FRM_SIZE_V_SIZE_15 (0x8000UL << SLCD_FRM_SIZE_V_SIZE_Pos) /*!< 0x80000000 */ +#define SLCD_FRM_SIZE_H_SIZE_Pos (0U) +#define SLCD_FRM_SIZE_H_SIZE_Msk (0xffffUL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x0000ffff */ +#define SLCD_FRM_SIZE_H_SIZE SLCD_FRM_SIZE_H_SIZE_Msk +#define SLCD_FRM_SIZE_H_SIZE_0 (0x1UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000001 */ +#define SLCD_FRM_SIZE_H_SIZE_1 (0x2UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000002 */ +#define SLCD_FRM_SIZE_H_SIZE_2 (0x4UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000004 */ +#define SLCD_FRM_SIZE_H_SIZE_3 (0x8UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000008 */ +#define SLCD_FRM_SIZE_H_SIZE_4 (0x10UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000010 */ +#define SLCD_FRM_SIZE_H_SIZE_5 (0x20UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000020 */ +#define SLCD_FRM_SIZE_H_SIZE_6 (0x40UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000040 */ +#define SLCD_FRM_SIZE_H_SIZE_7 (0x80UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000080 */ +#define SLCD_FRM_SIZE_H_SIZE_8 (0x100UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000100 */ +#define SLCD_FRM_SIZE_H_SIZE_9 (0x200UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000200 */ +#define SLCD_FRM_SIZE_H_SIZE_10 (0x400UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000400 */ +#define SLCD_FRM_SIZE_H_SIZE_11 (0x800UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00000800 */ +#define SLCD_FRM_SIZE_H_SIZE_12 (0x1000UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00001000 */ +#define SLCD_FRM_SIZE_H_SIZE_13 (0x2000UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00002000 */ +#define SLCD_FRM_SIZE_H_SIZE_14 (0x4000UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00004000 */ +#define SLCD_FRM_SIZE_H_SIZE_15 (0x8000UL << SLCD_FRM_SIZE_H_SIZE_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: SLCD_REG_IF BASE+0xA014 *********/ +#define SLCD_REG_IF_FLAG_Pos (30U) +#define SLCD_REG_IF_FLAG_Msk (0x3UL << SLCD_REG_IF_FLAG_Pos) /*!< 0xc0000000 */ +#define SLCD_REG_IF_FLAG SLCD_REG_IF_FLAG_Msk +#define SLCD_REG_IF_FLAG_0 (0x1UL << SLCD_REG_IF_FLAG_Pos) /*!< 0x40000000 */ +#define SLCD_REG_IF_FLAG_1 (0x2UL << SLCD_REG_IF_FLAG_Pos) /*!< 0x80000000 */ +#define SLCD_REG_IF_CMD_END_Pos (29U) +#define SLCD_REG_IF_CMD_END_Msk (0x1UL << SLCD_REG_IF_CMD_END_Pos) /*!< 0x20000000 */ +#define SLCD_REG_IF_CMD_END SLCD_REG_IF_CMD_END_Msk +#define SLCD_REG_IF_CMD_END_0 (0x1UL << SLCD_REG_IF_CMD_END_Pos) /*!< 0x20000000 */ +#define SLCD_REG_IF_CONTENT_Pos (0U) +#define SLCD_REG_IF_CONTENT_Msk (0xffffffUL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00ffffff */ +#define SLCD_REG_IF_CONTENT SLCD_REG_IF_CONTENT_Msk +#define SLCD_REG_IF_CONTENT_0 (0x1UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000001 */ +#define SLCD_REG_IF_CONTENT_1 (0x2UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000002 */ +#define SLCD_REG_IF_CONTENT_2 (0x4UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000004 */ +#define SLCD_REG_IF_CONTENT_3 (0x8UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000008 */ +#define SLCD_REG_IF_CONTENT_4 (0x10UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000010 */ +#define SLCD_REG_IF_CONTENT_5 (0x20UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000020 */ +#define SLCD_REG_IF_CONTENT_6 (0x40UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000040 */ +#define SLCD_REG_IF_CONTENT_7 (0x80UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000080 */ +#define SLCD_REG_IF_CONTENT_8 (0x100UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000100 */ +#define SLCD_REG_IF_CONTENT_9 (0x200UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000200 */ +#define SLCD_REG_IF_CONTENT_10 (0x400UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000400 */ +#define SLCD_REG_IF_CONTENT_11 (0x800UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00000800 */ +#define SLCD_REG_IF_CONTENT_12 (0x1000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00001000 */ +#define SLCD_REG_IF_CONTENT_13 (0x2000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00002000 */ +#define SLCD_REG_IF_CONTENT_14 (0x4000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00004000 */ +#define SLCD_REG_IF_CONTENT_15 (0x8000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00008000 */ +#define SLCD_REG_IF_CONTENT_16 (0x10000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00010000 */ +#define SLCD_REG_IF_CONTENT_17 (0x20000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00020000 */ +#define SLCD_REG_IF_CONTENT_18 (0x40000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00040000 */ +#define SLCD_REG_IF_CONTENT_19 (0x80000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00080000 */ +#define SLCD_REG_IF_CONTENT_20 (0x100000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00100000 */ +#define SLCD_REG_IF_CONTENT_21 (0x200000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00200000 */ +#define SLCD_REG_IF_CONTENT_22 (0x400000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00400000 */ +#define SLCD_REG_IF_CONTENT_23 (0x800000UL << SLCD_REG_IF_CONTENT_Pos) /*!< 0x00800000 */ + +/********* Register BitField Details: SLCD_ST BASE+0xA018 *********/ +#define SLCD_ST_BUSY_Pos (0U) +#define SLCD_ST_BUSY_Msk (0x1UL << SLCD_ST_BUSY_Pos) /*!< 0x00000001 */ +#define SLCD_ST_BUSY SLCD_ST_BUSY_Msk +#define SLCD_ST_BUSY_0 (0x1UL << SLCD_ST_BUSY_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: SLCD_REG_CTRL BASE+0xA01C *********/ +#define SLCD_REG_CTRL_RESET_3LINE_Pos (0U) +#define SLCD_REG_CTRL_RESET_3LINE_Msk (0x1UL << SLCD_REG_CTRL_RESET_3LINE_Pos) /*!< 0x00000001 */ +#define SLCD_REG_CTRL_RESET_3LINE SLCD_REG_CTRL_RESET_3LINE_Msk +#define SLCD_REG_CTRL_RESET_3LINE_0 (0x1UL << SLCD_REG_CTRL_RESET_3LINE_Pos) /*!< 0x00000001 */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus*/ +#endif /* __REG_DPU_H__ */ diff --git a/cpu/soc-x2600/include/x2600.h b/cpu/soc-x2600/include/x2600.h index 0d0beb3b..7d9dd27d 100755 --- a/cpu/soc-x2600/include/x2600.h +++ b/cpu/soc-x2600/include/x2600.h @@ -38,6 +38,7 @@ #include "interrupt.h" #include "pwm.h" #include "tcu.h" +#include "dpu.h" #ifdef __cplusplus extern "C" { @@ -80,6 +81,7 @@ extern "C" { #define UART6_BASE 0x10036000 /*!< Address base of UART 6 */ #define UART7_BASE 0x10037000 /*!< Address base of UART 7 */ #define PWM_BASE 0x13610000 /*!< Address base of PWM */ +#define DPU_BASE 0x13050000 /*!< Address base of PWM */ /*< Peripheral declarations */ #ifdef CORE_RISCV @@ -121,6 +123,7 @@ extern "C" { #define UART6_Instance ((UART_TypeDef *) (UART6_BASE )) #define UART7_Instance ((UART_TypeDef *) (UART7_BASE )) #define PWM_Instance ((PWM_TypeDef *) (PWM_BASE)) +#define DPU_Instance ((DPU_TypeDef *) (DPU_BASE)) #else #define CPM_Instance ((CPM_TypeDef *) (CPM_BASE | 0xa0000000)) @@ -156,6 +159,7 @@ extern "C" { #define UART6_Instance ((UART_TypeDef *) (UART6_BASE | 0xa0000000)) #define UART7_Instance ((UART_TypeDef *) (UART7_BASE | 0xa0000000)) #define PWM_Instance ((PWM_TypeDef *) (PWM_BASE | 0xa0000000)) +#define DPU_Instance ((DPU_TypeDef *) (DPU_BASE | 0xa0000000)) #endif diff --git a/drivers/drivers-x2600/ChangeLog b/drivers/drivers-x2600/ChangeLog index edf8ee24..1c916024 100644 --- a/drivers/drivers-x2600/ChangeLog +++ b/drivers/drivers-x2600/ChangeLog @@ -1,3 +1,4 @@ +2023-5-26 支持TFT屏RDMA模式 2023-5-19 支持PWM DMA模式 2023-5-12 支持PWM寄存器模式 PWM DMA模式尚未支持 2023-5-11 支持i2c轮询模式和中断模式 i2c DMA模式尚未支持 diff --git a/drivers/drivers-x2600/include/x2600_hal_conf.h b/drivers/drivers-x2600/include/x2600_hal_conf.h index 8df87855..7eb524f8 100644 --- a/drivers/drivers-x2600/include/x2600_hal_conf.h +++ b/drivers/drivers-x2600/include/x2600_hal_conf.h @@ -14,6 +14,7 @@ #define HAL_I2C_ENABLED #define HAL_PWM_ENABLED #define HAL_TCU_ENABLED +#define HAL_DPU_ENABLED #if 0 #define HAL_MSC_ENABLED #define HAL_SPI_ENABLED @@ -43,6 +44,10 @@ #endif +#ifdef HAL_DPU_ENABLED +#include "x2600_hal_lcd.h" +#endif + #ifdef HAL_I2C_ENABLED #include "x2600_hal_i2c.h" #endif diff --git a/drivers/drivers-x2600/include/x2600_hal_lcd.h b/drivers/drivers-x2600/include/x2600_hal_lcd.h new file mode 100644 index 00000000..ea6d03fe --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_hal_lcd.h @@ -0,0 +1,632 @@ +/** + * @file x26xx_hal_lcd.h + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_HAL_LCD_H__ +#define __X2600_HAL_LCD_H__ + + +/** + * @addtogroup group_LCD + * @{ + */ + +/** + * @addtogroup g_X26XX_LCD_HAL_Driver LCD HAL 驱动 + * @{ + */ + +/* 1.头文件 (Includes)------------------------------------------------- */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* 2.导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup LCD_exported_types LCD 导出的类型 (Exported Types) + * @{ + */ + +enum lcdc_out_format { + OUT_FORMAT_RGB565, + OUT_FORMAT_RGB666, + OUT_FORMAT_RGB888, + OUT_FORMAT_RGB444, + OUT_FORMAT_RGB555, +}; + +enum lcdc_mcu_data_width { + MCU_WIDTH_8BITS, + MCU_WIDTH_9BITS, + MCU_WIDTH_16BITS, + MCU_WIDTH_18BITS, + MCU_WIDTH_24BITS, +}; + +enum lcdc_out_order { + ORDER_RGB, + ORDER_RBG, + ORDER_GRB, + ORDER_BRG, + ORDER_GBR, + ORDER_BGR, +}; + +enum lcdc_lcd_mode { + TFT_24BITS, + TFT_8BITS_SERIAL = 2, + TFT_8BITS_DUMMY_SERIAL, + + SLCD_6800, + SLCD_8080, + SLCD_SPI_3LINE, + SLCD_SPI_4LINE, +}; + +enum lcdc_signal_polarity { + AT_FALLING_EDGE, + AT_RISING_EDGE, +}; + +enum lcdc_signal_level { + AT_LOW_LEVEL, + AT_HIGH_LEVEL, +}; + +enum lcdc_dc_pin { + CMD_LOW_DATA_HIGH, + CMD_HIGH_DATA_LOW, +}; + +enum lcdc_data_trans_mode { + LCD_PARALLEL_MODE, + LCD_SERIAL_MODE, +}; + +enum lcdc_te_type { + TE_NOT_EANBLE, + TE_GPIO_IRQ_TRIGGER, + TE_LCDC_TRIGGER, +}; + +enum smart_config_type { + SMART_CONFIG_DATA, + SMART_CONFIG_PRM, + SMART_CONFIG_CMD, + SMART_CONFIG_UDELAY, +}; + +struct smart_lcd_data_table { + enum smart_config_type type; + unsigned int value; +}; + +enum fb_fmt { + fb_fmt_RGB555, + fb_fmt_RGB565, + fb_fmt_RGB888, + fb_fmt_ARGB8888, + fb_fmt_NV12, + fb_fmt_NV21, + fb_fmt_yuv422, +}; + + +enum frame_state { + state_clear, + state_display_start, + state_display_end, + state_stop, +}; + +struct srdmadesc { + unsigned long RdmaNextCfgAddr; + unsigned long FrameBufferAddr; + unsigned long stride; + unsigned long FrameCtrl; + unsigned long InterruptControl; +}; + +#define EVEN_RGBTORGB 0x00000000U +#define EVEN_RGBTORBG ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0) +#define EVEN_RGBTOBGR ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_1) +#define EVEN_RGBTOBRG ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0 | TFT_TRAN_CFG_COLOR_EVEN_1) +#define EVEN_RGBTOGBR ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_2) +#define ENEN_RGBTOGRB ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0 | TFT_TRAN_CFG_COLOR_EVEN_2) + +#define ODD_RGBTORGB 0x00000000U +#define ODD_RGBTORBG ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0) +#define ODD_RGBTOBGR ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_1) +#define ODD_RGBTOBRG ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0 | TFT_TRAN_CFG_COLOR_ODD_1) +#define ODD_RGBTOGBR ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_2) +#define ODD_RGBTOGRB ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0 | TFT_TRAN_CFG_COLOR_ODD_2) + +struct tft_config{ + int even_line_order; + int odd_line_order; + enum lcdc_signal_polarity pix_clk_polarity; + enum lcdc_signal_level de_active_level; + enum lcdc_signal_level hsync_active_level; + enum lcdc_signal_level vsync_active_level; +}; + +struct slcd_config{ + unsigned int pixclock_when_init; + //int te_gpio; + int cmd_of_start_frame; + int mcu_data_width; + int mcu_cmd_width; + enum lcdc_signal_polarity wr_data_sample_edge; + enum lcdc_dc_pin dc_pin; + enum lcdc_signal_polarity te_data_transfered_edge; + enum lcdc_te_type te_pin_mode; + enum lcdc_signal_level rdy_cmd_send_level; + int enable_rdy_pin:1; + + struct smart_lcd_data_table *slcd_data_table; + unsigned int slcd_data_table_length; +}; + +struct lcd_data{ + const char *name; + unsigned int refresh; + unsigned int xres; + unsigned int yres; + unsigned int pixclock; + unsigned int left_margin; + unsigned int right_margin; + unsigned int upper_margin; + unsigned int lower_margin; + unsigned int hsync_len; + unsigned int vsync_len; + + enum fb_fmt fb_fmt; + enum lcdc_lcd_mode lcd_mode; + enum lcdc_out_format out_format; + + struct tft_config *tft; + struct slcd_config *slcd; + + int frame_status; + int frame_index; + uint32_t frame_mem; + uint32_t frame_size; + + int (*power_on)(void); + int (*power_off)(void); +}; + +typedef struct __LCD_HandleTypeDef { + DPU_TypeDef *Instance; + struct lcd_data *pdata; +#define MAX_SRDMA_DESC_NUM 3 + struct srdmadesc *desc[MAX_SRDMA_DESC_NUM]; + HAL_LockTypeDef lock; +} LCD_HandleTypeDef; + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3.导出常量定义 (Exported Constants) -------------------------------- */ +/** + * @defgroup LCD_exported_constants LCD 导出的常量 (Exported Constants) + * @{ + */ + +#define TFT_d0 4 +#define TFT_d1 5 +#define TFT_d2 6 +#define TFT_d3 7 +#define TFT_d4 8 +#define TFT_d5 9 +#define TFT_d6 10 +#define TFT_d7 11 +#define TFT_d8 12 +#define TFT_d9 13 +#define TFT_d10 14 +#define TFT_d11 15 +#define TFT_d12 16 +#define TFT_d13 17 +#define TFT_d14 18 +#define TFT_d15 19 +#define TFT_d16 20 +#define TFT_d17 21 +#define TFT_d18 22 +#define TFT_d19 23 +#define TFT_d20 24 +#define TFT_d21 25 +#define TFT_d22 26 +#define TFT_d23 27 + +#define TFT_pclk 28 +#define TFT_vsync 29 +#define TFT_hsync 30 +#define TFT_de 31 + +#define SLCD_CE 28 +#define SLCD_DC 29 +#define SLCD_WR 30 +#define SLCD_TE 31 + + +#define BURST_LEN_RDMA_4 0x00000000U /*读取DMA的最大长度4*/ +#define BURST_LEN_RDMA_8 0x00000001U/*读取DMA的最大长度8*/ +#define BURST_LEN_RDMA_16 0x00000002U/*读取DMA的最大长度16*/ +#define BURST_LEN_RDMA_32 0x00000003U/*读取DMA的最大长度32*/ + + +#define QoS_value_0 0x00000000U /*重置值为0*/ +#define QoS_value_1 0x00000001U /*重置值为1*/ +#define QoS_value_2 0x00000002U /*重置值为2*/ +#define QoS_value_3 0x00000003U /*重置值为3*/ + + +#define DISPLAY_SELECT_NO 0x00000000U +#define DISPLAY_SELECT_TFT 0x00000001U +#define DISPLAY_SELECT_SLCD 0x00000002U + + + +#define FLAG_DATA 0x00000000U +#define FLAG_PARAMETER 0x00000001U +#define FLAG_CMD_1 0x00000002U +#define FLAG_CMD_2 0x00000003U + +#define VIR_TO_PHY(add) (((uint32_t)add) & (~0x80000000)) +#define CPHYSADDR(add) (((uint32_t)add) & (0x1FFFFFFF)) +/** + * @} + */ +/* 4.导出宏定义 (Exported Macros) ------------------------------------- */ +/** + * @defgroup LCD_exported_macros LCD 导出宏 (Exported Macros) + * @{ + */ + +/** + * @defgroup LCD_exported_macros_group0 RDMA描述符地址 + * @{ + */ +#define __HAL_SRD_CHAIN_ADDR(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DC_SRD_CHAIN_ADDR, __VALUE__) + +/** + * @defgroup LCD_exported_macros_group1 RDMA描述符控制 + * @{ + */ +#define __HAL_SRD_CHAIN_START(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_SRD_CHAIN_CTRL, DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_0) +/** + * @defgroup LCD_exported_macros_group2 控件配置 + * @{ + */ +/*正常停止LCD显示*/ +#define __GEN_STP_SRD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_GEN_STP_SRD_0) +/*重置DMA计数器*/ +#define __DES_CNT_RST(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_DES_CNT_RST_0) +/*快速停止LCD显示*/ +#define __QCK_STP_SRD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_QCK_STP_SRD_0) +/** + * @defgroup LCD_exported_macros_group3 状态判断 + * @{ + */ +#define __HAL_DISP_END(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_DISP_END_0) +#define __HAL_TFT_UNDR(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_TFT_UNDR_0) +#define __HAL_STOP_SRD_ACK(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_STOP_SRD_ACK_0) +#define __HAL_SRD_WORKING(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_WORKING_0) +#define __HAL_SRD_START(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_START_0) +#define __HAL_SRD_END(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_END_0) +#define __HAL_WORKING(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_WORKING_0) +/** + * @defgroup LCD_exported_macros_group4 清除状态 + * @{ + */ +#define __GEN_CLR_DISP_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_DISP_END_0) +#define __GEN_CLR_TFT_UNDR(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_TFT_UNDR_0) +#define __GEN_CLR_STOP_SRD_ACK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_STP_SRD_ACK_0) +#define __GEN_CLR_SRD_START(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_SRD_START_0) +#define __GEN_CLR_SRD_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_SRD_END_0) +/** + * @defgroup LCD_exported_macros_group5 中断 + * @{ + */ +#define __HAL_EOD_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_EOD_MSK_0) +#define __HAL_UOT_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_UOT_MSK_0) +#define __HAL_SSA_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_SSA_MSK_0) +#define __HAL_SOS_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_SOS_MSK_0) +#define __HAL_EOS_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_EOS_MSK_0) +/** + * @defgroup LCD_exported_macros_group6 中断标志 + * @{ + */ +#define __HAL_INT_EOD(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_INT_FLAG, DC_INT_FLAG_INT_EOD_0) +#define __HAL_INT_UOT(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_INT_FLAG, DC_INT_FLAG_INT_UOT_0) +#define __HAL_INT_SSA(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_INT_FLAG, DC_INT_FLAG_INT_SSA_0) +#define __HAL_INT_SOS(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_INT_FLAG, DC_INT_FLAG_INT_SOS_0) +#define __HAL_INT_EOS(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_INT_FLAG, DC_INT_FLAG_INT_EOS_0) +/** + * @defgroup LCD_exported_macros_group7 读取DMA的最大长度 + * @{ + */ +#define __HAL_BURST_LEN_RDMA(__HANDLE__, __VALUE__) WRITE_REG((__HANDLE__)->Instance->DC_COM_CONFIG, (__VALUE__) << DC_COM_CONFIG_BURST_LEN_RDMA_Pos) +#define __HAL_SRD_CHAIN_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_COM_CONFIG, DC_COM_CONFIG_RDMA_CH) +/** + * @defgroup LCD_exported_macros_group8 优先级配置 + * @{ + */ +#define __HAL_ARQOS_VAL(__HANDLE__, __VALUE__) WRITE_REG((__HANDLE__)->Instance->DC_PCFG_RD_CTRL, (__VALUE__) << DC_PCFG_RD_CTRL_ARQOS_VAL_Pos) +#define __HAL_ARQOS_CTRL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_PCFG_RD_CTRL, DC_PCFG_RD_CTRL_ARQOS_CTRL_0) +/** + * @defgroup LCD_exported_macros_group9 显示页面配置 + * @{ + */ +#define __HAL_DP_DITHER_DW(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_DW_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__) << DISP_COM_DP_DITHER_DW_Pos) + +#define __HAL_DITHER_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_DITHER_CLKGATE_EN_0) + +#define __HAL_SLCD_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_SLCD_CLKGATE_EN_0) + +#define __HAL_TFT_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_TFT_CLKGATE_EN_0) + +#define __HAL_DP_DITHER_EN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_EN_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__) << DISP_COM_DP_DITHER_EN_Pos) + + +#define __HAL_DP_IF_SEL(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_DW_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group10 定时HSYNC + * @{ + */ +#define __HAL_HPS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC, ((~TFT_TIMING_HSYNC_HPS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC))) | (__VALUE__) << TFT_TIMING_HSYNC_HPS_Pos) + +#define __HAL_HPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC, ((~TFT_TIMING_HSYNC_HPE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group11 定时VSYNC + * @{ + */ +#define __HAL_VPS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC, ((~TFT_TIMING_VSYNC_VPS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC))) | (__VALUE__) << TFT_TIMING_VSYNC_VPS_Pos) + +#define __HAL_VPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC, ((~TFT_TIMING_VSYNC_VPE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group12 定时HDE + * @{ + */ +#define __HAL_HDS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE, ((~TFT_TIMING_HDE_HDS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE))) | (__VALUE__) << TFT_TIMING_HDE_HDS_Pos) + +#define __HAL_HDE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE, ((~TFT_TIMING_HDE_HDE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group12 定时VDE + * @{ + */ +#define __HAL_VDS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE, ((~TFT_TIMING_VDE_VDS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE))) | (__VALUE__) << TFT_TIMING_VDE_VDS_Pos) + +#define __HAL_VDE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE, ((~TFT_TIMING_VDE_VDE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group13 传输配置 + * @{ + */ +#define __HAL_COLOR_EVEN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_COLOR_EVEN_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__) << TFT_TRAN_CFG_COLOR_EVEN_Pos) + +#define __HAL_COLOR_ODD(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_COLOR_ODD_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__) << TFT_TRAN_CFG_COLOR_ODD_Pos) + +#define __HAL_SET_CLK_INV(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_PIX_CLK_INV_0) +#define __HAL_CLEAR_CLK_INV(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_PIX_CLK_INV_0) + +#define __HAL_SET_DE_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_DE_DL_0) +#define __HAL_CLEAR_DE_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_DE_DL_0) + +#define __HAL_SET_HSYNC_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) +#define __HAL_CLEAR_HSYNC_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) + +#define __HAL_SET_VSYNC_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_VSYNC_DL_0) +#define __HAL_CLEAR_VSYNC_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_VSYNC_DL_0) + +#define __HAL_TFAN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_MODE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group14 SLCD配置 + * @{ + */ +#define __HAL_RDY_PIXCLK_1(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_ANTI_JIT_0) +#define __RDY_PIXCLK_3(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_ANTI_JIT_0) + +#define __HAL_FMT_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_FMT_EN_0) +#define __HAL_FMT_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_FMT_EN_0) + +#define __HAL_DBI_TYPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_DBI_TYPE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_DBI_TYPE_Pos) + +#define __HAL_PIX_FMT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_PIX_FMT_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_PIX_FMT_Pos) + +#define __HAL_TE_ANTI_JIT_1(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_ANTI_JIT_0) +#define __HAL_TE_ANTI_JIT_3(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_ANTI_JIT_0) + +#define __HAL_TE_MD_FRONT(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_MD_0) +#define __HAL_TE_MD_BACK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_MD_0) + +#define __HAL_TE_SWITCH_NOWAIT(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_SWITCH_0) +#define __HAL_TE_SWITCH_WAIT(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_SWITCH_0) + +#define __HAL_RDY_SWITCH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_RDY_SWITCH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__)<Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_EN_0) +#define __HAL_CS_EN_SLCD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_EN_0) + +#define __HAL_CS_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_DP_0) +#define __HAL_CS_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_DP_0) + +#define __HAL_RDY_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_DP_0) +#define __HAL_RDY_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_DP_0) + +#define __HAL_DC_MD_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_DC_MD_0) +#define __HAL_DC_MD_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_DC_MD_0) + +#define __HAL_WR_MD_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_WR_MD_0) +#define __HAL_WR_MD_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_WR_MD_0) + +#define __HAL_TE_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_DP_0) +#define __HAL_TE_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_DP_0) + +#define __HAL_DWIDTH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_DWIDTH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_DWIDTH_Pos) + +#define __HAL_CWIDTH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_CWIDTH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group15 SLCD长度和宽度 + * @{ + */ + +#define __HAL_V_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE, ((~SLCD_FRM_SIZE_V_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE))) | (__VALUE__) << SLCD_FRM_SIZE_V_SIZE_Pos) + +#define __HAL_H_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE, ((~SLCD_FRM_SIZE_H_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group16 SLCD数据传输 + * @{ + */ +#define __HAL_SEND_CMD(__HANDLE__,__VALUE__) \ + WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, \ + (READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) \ + & (~(SLCD_REG_IF_FLAG_Msk | SLCD_REG_IF_CMD_END_Msk | SLCD_REG_IF_CONTENT_Msk))) \ + | ((FLAG_CMD_1 << SLCD_REG_IF_FLAG_Pos) | ((__VALUE__) << SLCD_REG_IF_CONTENT_Pos))) + +#define __HAL_SEND_DATA(__HANDLE__,__VALUE__) \ + WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, \ + (READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) \ + & (~(SLCD_REG_IF_FLAG_Msk | SLCD_REG_IF_CMD_END_Msk | SLCD_REG_IF_CONTENT_Msk))) \ + | ((FLAG_DATA << SLCD_REG_IF_FLAG_Pos) | ((__VALUE__) << SLCD_REG_IF_CONTENT_Pos))) + +#define __HAL_SEND_PRM(__HANDLE__,__VALUE__) \ + WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, \ + (READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) \ + & (~(SLCD_REG_IF_FLAG_Msk | SLCD_REG_IF_CMD_END_Msk | SLCD_REG_IF_CONTENT_Msk))) \ + | ((FLAG_PARAMETER << SLCD_REG_IF_FLAG_Pos) | ((__VALUE__) << SLCD_REG_IF_CONTENT_Pos))) + +#define __HAL_IF_CMD_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_REG_IF, SLCD_REG_IF_CMD_END_0) + +/** + * @defgroup LCD_exported_macros_group17 SLCD状态 + * @{ + */ +#define __HAL_ST_BUSY(__HANDLE__) READ_BIT((__HANDLE__)->Instance->SLCD_ST, SLCD_ST_BUSY_0) +/** + * @defgroup LCD_exported_macros_group17 SLCD长度和宽度 + * @{ + */ +#define __HAL_SLCD_REG_CTRL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_REG_CTRL, SLCD_REG_CTRL_RESET_3LINE_0) + +/** + * @} + */ +/* 5.导出函数申明 (Exported Funcs) ------------------------------------ */ +/** + * @defgroup LCD_exported_funcs LCD 导出函数申明 (Exported Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6.导出变量申明 (Exported Variables) -------------------------------- */ +/** + * @defgroup LCD_exported_var LCD 导出变量申明 (Exported Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7.私有类型定义 (Private Types) ------------------------------------- */ +/** + * @defgroup LCD_private_types LCD 私有类型定义 (Private Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 8.私有常量定义 (Private Constants) -------------------------------- */ +/** + * @defgroup LCD_private_constants LCD 私有常量定义 (Private Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 9.私有宏定义 (Private Macros) ------------------------------------- */ +/** + * @defgroup LCD_private_macros LCD 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 10.私有函数申明 (Private Funcs) ------------------------------------ */ +/** + * @defgroup LCD_private_funcs LCD 私有函数申明 (Private Funcs) + * @{ + */ +void HAL_LCDC_INIT(LCD_HandleTypeDef *hlcd); +void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd); +void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer); +void process_slcd_data_table(LCD_HandleTypeDef * hlcd, struct smart_lcd_data_table *table, unsigned int length); +void lcdc_irq_handler(int irq, void *data); +void HAL_SRDMA_START(LCD_HandleTypeDef *hlcd); +void HAL_PAN_DISPLAY(LCD_HandleTypeDef *hlcd, unsigned int frame_num); +void dump_rdma_desc_reg(LCD_HandleTypeDef *hlcd); +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 11.私有变量申明 Private Variables ---------------------------------- */ +/** + * @defgroup LCD_private_var LCD 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_LCD_H__ */ diff --git a/drivers/drivers-x2600/include/x2600_ll_cpm.h b/drivers/drivers-x2600/include/x2600_ll_cpm.h index 8a455960..f595860c 100755 --- a/drivers/drivers-x2600/include/x2600_ll_cpm.h +++ b/drivers/drivers-x2600/include/x2600_ll_cpm.h @@ -299,6 +299,8 @@ HAL_StatusTypeDef CPM_CGU_PWM_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef HAL_StatusTypeDef CPM_CGU_PWM_Stop(CPM_TypeDef *CPMx); HAL_StatusTypeDef CPM_CGU_SADC_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); HAL_StatusTypeDef CPM_CGU_SADC_Stop(CPM_TypeDef *CPMx); +HAL_StatusTypeDef CPM_CGU_LCD_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); +HAL_StatusTypeDef CPM_CGU_LCD_Stop(CPM_TypeDef *CPMx); #if 0 HAL_StatusTypeDef CPM_CGU_I2S0_Config(CPM_TypeDef *CPMx, LL_CPM_CGU_I2STypeDef *Config); HAL_StatusTypeDef CPM_CGU_I2S1_Config(CPM_TypeDef *CPMx, LL_CPM_CGU_I2STypeDef *Config); @@ -306,8 +308,6 @@ HAL_StatusTypeDef CPM_CGU_DDR_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef HAL_StatusTypeDef CPM_CGU_DDR_Stop(CPM_TypeDef *CPMx); HAL_StatusTypeDef CPM_CGU_MAC_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); HAL_StatusTypeDef CPM_CGU_MAC_Stop(CPM_TypeDef *CPMx); -HAL_StatusTypeDef CPM_CGU_LCD_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); -HAL_StatusTypeDef CPM_CGU_LCD_Stop(CPM_TypeDef *CPMx); HAL_StatusTypeDef CPM_CGU_MSC0_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); HAL_StatusTypeDef CPM_CGU_MSC0_Stop(CPM_TypeDef *CPMx); HAL_StatusTypeDef CPM_CGU_MSC1_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config); diff --git a/drivers/drivers-x2600/src/x2600_hal_lcd.c b/drivers/drivers-x2600/src/x2600_hal_lcd.c new file mode 100644 index 00000000..797f6377 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_hal_lcd.c @@ -0,0 +1,776 @@ +/** + * @file x2600_hal_template.c + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + [!!!!删除此内容，添加针对模块的使用方法说明，例如： 配置，启动/停止，状态，重点提醒等等.!!!!] + @endverbatim + */ + +/* 1.头文件 (Includes)--------------------------------------------------- */ +#include "x2600_hal.h" +/** @addtogroup g_X16XX_TEMPLATE_HAL_Driver + * @{ + */ + +/* 2.私有常量定义 (Private Constants) ----------------------------------- */ +/** + * @addtogroup TEMPLATE_private_constants TEMPLATE 私有常量定义 (Private Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3.私有类型定义 (Private Types) --------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_types TEMPLATE 私有类型定义 (Private Types) + * @{ + */ +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 4.私有宏定义 (Private Macros) ---------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_macros TEMPLATE 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 5.私有变量申明 (Private Variables) ----------------------------------- */ +/** + * @addtogroup TEMPLATE_private_var TEMPLATE 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6.私有函数申明 (Private Funcs) --------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_funcs TEMPLATE 私有函数申明 (Private Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7.私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup TEMPLATE_private_funcs_impl TEMPLATE 私有函数实现 (Private Funcs) + * @{ + */ +static void lcdc_dump_regs(LCD_HandleTypeDef *hlcd) +{ + prom_printk("==================================================================================\n"); + prom_printk("SRD_CHAIN_ADDR = %08x\n", hlcd->Instance->DC_SRD_CHAIN_ADDR); //0x1000 + prom_printk("SRD_CHAIN_CTRL = %08x\n", hlcd->Instance->DC_SRD_CHAIN_CTRL); //0x1004 + prom_printk("CTRL = %08x\n", hlcd->Instance->DC_CTRL); //0x2000 + prom_printk("ST = %08x\n", hlcd->Instance->DC_ST); //0x2004 + prom_printk("CLR_ST = %08x\n", hlcd->Instance->DC_CLR_ST); //0x2008 + prom_printk("INTC = %08x\n", hlcd->Instance->DC_INTC); //0x200C + prom_printk("INT_FLAG = %08x\n", hlcd->Instance->DC_INT_FLAG); //0x2010 + prom_printk("COM_CFG = %08x\n", hlcd->Instance->DC_COM_CONFIG); //0x2014 + prom_printk("PCFG_RD_CTRL = %08x\n", hlcd->Instance->DC_PCFG_RD_CTRL); //0x2018 + prom_printk("PCFG_OFIFO = %08x\n", hlcd->Instance->DC_PCFG_OFIFO); //0x2020 + prom_printk("RDMA_DES = %08x\n", hlcd->Instance->DC_RDMA_DES); //0x2114 + prom_printk("RDMA_CHAIN_SITE = %08x\n", hlcd->Instance->DC_RDMA_CHAIN_SITE);//0x2204 + prom_printk("RDMA_SITE = %08x\n", hlcd->Instance->DC_RDMA_SITE); //0x3110 + prom_printk("DISP_COM = %08x\n", hlcd->Instance->DISP_COM); //0x8000 + + prom_printk("SLCD_CFG = %08x\n", hlcd->Instance->SLCD_PANEL_CFG); //0xA000 + prom_printk("SLCD_WR_DUTY = %08x\n", hlcd->Instance->SLCD_WR_DUTY); //0xA004 + prom_printk("SLCD_TIMING = %08x\n", hlcd->Instance->SLCD_TIMING); //0xA008 + prom_printk("SLCD_FRM_SIZE = %08x\n", hlcd->Instance->SLCD_FRM_SIZE); //0xA00C + prom_printk("SLCD_SLOW_TIME = %08x\n", hlcd->Instance->SLCD_SLOW_TIME); //0xA010 + prom_printk("SLCD_REG_IF = %08x\n", hlcd->Instance->SLCD_REG_IF); //0xA014 + prom_printk("SLCD_ST = %08x\n", hlcd->Instance->SLCD_ST); //0xA018 + prom_printk("SLCD_REG_CTRL = %08x\n", hlcd->Instance->SLCD_REG_CTRL); //0xA01C + + prom_printk("TFT_HSYNC = %08x\n", hlcd->Instance->TFT_TIMING_HSYNC); //0x9000 + prom_printk("TFT_VSYNC = %08x\n", hlcd->Instance->TFT_TIMIING_VSYNC); //0x9004 + prom_printk("TFT_HDE = %08x\n", hlcd->Instance->TFT_TIMIING_HDE); //0x9008 + prom_printk("TFT_VDE = %08x\n", hlcd->Instance->TFT_TIMIING_VDE); //0x900C + prom_printk("TFT_CFG = %08x\n", hlcd->Instance->TFT_TRAN_CFG); //0x9010 + prom_printk("TFT_ST = %08x\n", hlcd->Instance->TFT_ST); //0x9014 + prom_printk("==================================================================================\n"); +} + +void dump_rdma_desc_reg(LCD_HandleTypeDef *hlcd) +{ + unsigned int ctrl; + ctrl = READ_REG(hlcd->Instance->DC_CTRL); + ctrl |= (1 << 2); + WRITE_REG(hlcd->Instance->DC_CTRL, ctrl); + + prom_printk("====================rdma Descriptor register======================\n"); + prom_printk("RdmaNextCfgAddr: %lx\n",*(volatile unsigned int *)(0xb3050000 + 0x2114)); + prom_printk("FrameBufferAddr: %lx\n",*(volatile unsigned int *)(0xb3050000 + 0x2114)); + prom_printk("Stride: %lx\n",*(volatile unsigned int *)(0xb3050000 + 0x2114)); + prom_printk("ChainCfg: %lx\n",*(volatile unsigned int *)(0xb3050000 + 0x2114)); + prom_printk("InterruptControl: %lx\n",*(volatile unsigned int *)(0xb3050000 + 0x2114)); + prom_printk("==================rdma Descriptor register end======================\n"); +} + +static void init_tft(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + int hps = pdata->hsync_len; + int hpe = hps + pdata->left_margin + pdata->xres + pdata->right_margin; + int vps = pdata->vsync_len; + int vpe = vps + pdata->upper_margin + pdata->yres + pdata->lower_margin; + int hds = pdata->hsync_len + pdata->left_margin; + int hde = hds + pdata->xres; + int vds = pdata->vsync_len + pdata->upper_margin; + int vde = vds + pdata->yres; + int mode = 0; + + __HAL_HPS(hlcd,hps); + __HAL_HPE(hlcd,hpe); + __HAL_VPS(hlcd,vps); + __HAL_VPE(hlcd,vpe); + __HAL_HDS(hlcd,hds); + __HAL_HDE(hlcd,hde); + __HAL_VDS(hlcd,vds); + __HAL_VDE(hlcd,vde); + + if(pdata->tft->pix_clk_polarity == AT_FALLING_EDGE){ + __HAL_SET_CLK_INV(hlcd); + }else{ + __HAL_CLEAR_CLK_INV(hlcd); + } + if(pdata->tft->de_active_level == AT_LOW_LEVEL){ + __HAL_SET_DE_DL(hlcd); + }else{ + __HAL_CLEAR_DE_DL(hlcd); + } + if(pdata->tft->hsync_active_level == AT_LOW_LEVEL){ + __HAL_SET_HSYNC_DL(hlcd); + }else{ + __HAL_CLEAR_HSYNC_DL(hlcd); + } + if(pdata->tft->vsync_active_level == AT_LOW_LEVEL){ + __HAL_SET_VSYNC_DL(hlcd); + }else{ + __HAL_CLEAR_VSYNC_DL(hlcd); + } + __HAL_COLOR_EVEN(hlcd,pdata->tft->even_line_order); + __HAL_COLOR_ODD(hlcd,pdata->tft->odd_line_order); + + if(pdata->lcd_mode == TFT_24BITS) { + if (pdata->out_format == OUT_FORMAT_RGB565) + mode = 2; + if (pdata->out_format == OUT_FORMAT_RGB666) + mode = 1; + if (pdata->out_format == OUT_FORMAT_RGB888) + mode = 0; + } else { + prom_printk("lcd is not support outformat %d\n",pdata->out_format); + } + __HAL_TFAN(hlcd,mode); + prom_printk("lcd outformat %x\n",hlcd->Instance->TFT_TRAN_CFG); +} + +static void init_slcd(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + int dbi_type = 2; + /* 判断传输格式 */ + if (pdata->lcd_mode == SLCD_6800) + dbi_type = 1; + if (pdata->lcd_mode == SLCD_8080) + dbi_type = 2; + if (pdata->lcd_mode == SLCD_SPI_3LINE) + dbi_type = 4; + if (pdata->lcd_mode == SLCD_SPI_4LINE) + dbi_type = 5; + + int pix_fmt = pdata->out_format; + if (pdata->out_format == OUT_FORMAT_RGB444) + pix_fmt = 1; + if (pdata->out_format == OUT_FORMAT_RGB555) + prom_printk("slcd outformat can't be 555\n"); + + __HAL_RDY_PIXCLK_1(hlcd); /* 设置RDY的抗抖动 */ + __HAL_FMT_DIS(hlcd); /* 通过REG_IF转换像素 */ + __HAL_DBI_TYPE(hlcd,dbi_type); /* 设置传输格式 */ + __HAL_PIX_FMT(hlcd,pix_fmt); /* 设置颜色(RGB)格式 */ + __HAL_TE_ANTI_JIT_3(hlcd); /* 使用3个pixclk周期对TE进行采样，以防抖动 */ + __HAL_TE_MD_BACK(hlcd); /* 设置TE的活动边沿 */ + /* 选择是否等待TE，再发送数据 */ + if(pdata->slcd->te_pin_mode == TE_LCDC_TRIGGER){ + __HAL_TE_SWITCH_WAIT(hlcd); + }else{ + __HAL_TE_SWITCH_NOWAIT(hlcd); + } + /* 选择是否等待RDY，再发送命令或数据*/ + __HAL_RDY_SWITCH(hlcd,pdata->slcd->enable_rdy_pin); + __HAL_CS_EN_GPIO(hlcd); /* 设置CS引脚由GPIO控制还是SLCD控制 */ + __HAL_CS_DP_HIGH(hlcd); /* 设置CS的默认极性 */ + /* 设置RDY的默认极性*/ + if(pdata->slcd->rdy_cmd_send_level == AT_HIGH_LEVEL){ + __HAL_RDY_DP_HIGH(hlcd); + }else{ + __HAL_RDY_DP_LOW(hlcd); + } + /* 设置命令和数据的默认电平值 */ + if(pdata->slcd->dc_pin == CMD_HIGH_DATA_LOW){ + __HAL_DC_MD_HIGH(hlcd); + }else{ + __HAL_DC_MD_LOW(hlcd); + } + /* */ + if(pdata->slcd->wr_data_sample_edge == AT_RISING_EDGE){ + __HAL_WR_MD_LOW(hlcd); + }else{ + __HAL_WR_MD_HIGH(hlcd); + } + /* 设置读写电平 */ + if(pdata->slcd->te_data_transfered_edge == AT_RISING_EDGE){ + __HAL_TE_DP_LOW(hlcd); + }else{ + __HAL_TE_DP_HIGH(hlcd); + } + __HAL_DWIDTH(hlcd,pdata->slcd->mcu_data_width); /* 设置屏幕数据总线宽度 */ + __HAL_CWIDTH(hlcd,pdata->slcd->mcu_cmd_width); /* 面板命令及其参数的宽度。单位bit */ + WRITE_REG(hlcd->Instance->SLCD_WR_DUTY, 0); /* */ + WRITE_REG(hlcd->Instance->SLCD_TIMING, 0); + __HAL_V_SIZE(hlcd,pdata->yres); /* 设置屏幕宽高 */ + __HAL_H_SIZE(hlcd,pdata->xres); + WRITE_REG(hlcd->Instance->SLCD_SLOW_TIME, 0); /* 设置延时 */ +// prom_printk("hlcd->Instance->SLCD_PANEL_CFG = %08x\n",hlcd->Instance->SLCD_PANEL_CFG); +} + +static inline unsigned long bit_field_mask(int start, int end) +{ + unsigned long e = (1ul << end); + unsigned long s = (1ul << start); + return (e - s) + e; +} + +static int tft_init_gpio(int r, int g, int b) +{ + int i; + unsigned int pins = + bit_field_mask(TFT_d7 - b + 1, TFT_d7) | + bit_field_mask(TFT_d15 - g + 1, TFT_d15) | + bit_field_mask(TFT_d23 - r + 1, TFT_d23) | + (1 << TFT_pclk) | (1 << TFT_de) | (1 << TFT_vsync) | (1 << TFT_hsync); + for (i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(PB_Instance, i, GPIO_MODE_FUNCTION0); + } + } + return 0; +} +static int tft_serial_init_gpio(void) +{ + unsigned int pins = + bit_field_mask(TFT_d0, TFT_d7) | + (1 << TFT_pclk) | (1 << TFT_de) | (1 << TFT_vsync) | (1 << TFT_hsync); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(PB_Instance, i, GPIO_MODE_FUNCTION0); + } + } + return 0; +} +static int slcd_init_gpio_data8(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d7) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(PB_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} +static int slcd_init_gpio_data9(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d8) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(PB_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} +static int slcd_init_gpio_data16(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d15) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(PB_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} + +static int init_lcd_gpio(struct lcd_data *pdata) +{ + int ret = -HAL_ERROR; + + switch (pdata->lcd_mode) { + case TFT_24BITS: + if (pdata->out_format == OUT_FORMAT_RGB444) + ret = tft_init_gpio(4, 4, 4); + if (pdata->out_format == OUT_FORMAT_RGB555) + ret = tft_init_gpio(5, 5, 5); + if (pdata->out_format == OUT_FORMAT_RGB565) + ret = tft_init_gpio(5, 6, 5); + if (pdata->out_format == OUT_FORMAT_RGB666) + ret = tft_init_gpio(6, 6, 6); + if (pdata->out_format == OUT_FORMAT_RGB888) + ret = tft_init_gpio(8, 8, 8); + break; + + case TFT_8BITS_SERIAL: + case TFT_8BITS_DUMMY_SERIAL: + ret = tft_serial_init_gpio(); + break; + + case SLCD_6800: + case SLCD_8080:{ + int width; + if(pdata->slcd->mcu_cmd_width > pdata->slcd->mcu_data_width){ + width = pdata->slcd->mcu_cmd_width; + }else{ + width = pdata->slcd->mcu_data_width; + } + if (width == MCU_WIDTH_8BITS) + ret = slcd_init_gpio_data8(); + if (width == MCU_WIDTH_9BITS) + ret = slcd_init_gpio_data9(); + if (width == MCU_WIDTH_16BITS) + ret = slcd_init_gpio_data16(); + break; + } + default: + prom_printk("This mode is not currently implemented: %d\n", pdata->lcd_mode); + break; + } + return ret; +} + +static int slcd_wait_busy(LCD_HandleTypeDef * hlcd, unsigned int count) +{ + int busy; + busy = __HAL_ST_BUSY(hlcd); + + while (count-- && busy) { + busy = __HAL_ST_BUSY(hlcd); + } + return busy; +} + +static void slcd_send_cmd(LCD_HandleTypeDef * hlcd, unsigned int cmd) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_CMD(hlcd, cmd); +} + +static void slcd_send_data(LCD_HandleTypeDef *hlcd, unsigned int data) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_DATA(hlcd, data); +} + +static void slcd_send_prm(LCD_HandleTypeDef *hlcd, unsigned int prm) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_PRM(hlcd, prm); +} + +void process_slcd_data_table(LCD_HandleTypeDef * hlcd, struct smart_lcd_data_table *table, unsigned int length) +{ + int i = 0; + for (; i < length; i++) { + switch (table[i].type) { + case SMART_CONFIG_CMD: + slcd_send_cmd(hlcd,table[i].value); + break; + case SMART_CONFIG_DATA: + slcd_send_data(hlcd,table[i].value); + break; + case SMART_CONFIG_PRM: + slcd_send_prm(hlcd,table[i].value); + break; + case SMART_CONFIG_UDELAY: + //HAL_uDelay(table[i].value); + break; + default: + prom_printk("why this type: %d\n", table[i].type); + break; + } + } + if (slcd_wait_busy(hlcd, 10 * 1000)) + prom_printk("lcdc busy\n"); +} + +static int check_scld_fmt(LCD_HandleTypeDef * hlcd) +{ + struct lcd_data *pdata = hlcd->pdata; + int pix_fmt = pdata->out_format; + + if (pdata->lcd_mode >= SLCD_SPI_3LINE) + return -1; + + int width = pdata->slcd->mcu_data_width; + if (width == MCU_WIDTH_8BITS) { + if (pix_fmt != OUT_FORMAT_RGB565 && pix_fmt != OUT_FORMAT_RGB888) + return -1; + } + if (width == MCU_WIDTH_9BITS) { + if (pix_fmt != OUT_FORMAT_RGB666) + return -1; + } + if (width == MCU_WIDTH_16BITS) { + if (pix_fmt != OUT_FORMAT_RGB565) + return -1; + } + + return 0; +} + +static inline int is_tft(struct lcd_data *pdata) +{ + return pdata->lcd_mode <= TFT_8BITS_DUMMY_SERIAL; +} + +static inline int is_slcd(struct lcd_data *pdata) +{ + return pdata->lcd_mode >= SLCD_6800; +} + +static int lcdc_tft_pan_display(LCD_HandleTypeDef *hlcd, struct srdmadesc *frame) +{ + WRITE_REG(hlcd->Instance->DC_SRD_CHAIN_ADDR, CPHYSADDR(frame)); + __HAL_SRD_CHAIN_START(hlcd); + + HAL_Delay(50); + return 0; +} + +static int lcdc_slcd_pan_display(LCD_HandleTypeDef *hlcd, struct srdmadesc *frame) +{ +#if 0 + int i = 10; + int ret = -1; + + while(i--){ + if(hlcd->pdata->frame_status != state_clear && + hlcd->pdata->frame_status != state_display_end){ + HAL_Delay(10); /* ms */ + } else if(hlcd->pdata->frame_status == state_display_end){ + ret = 0; + break; + } + } + + if(ret){ + prom_printk("lcd busy!\n"); + return ret; + } + hlcd->pdata->frame_status = state_display_start; +#endif +// HAL_Delay(50); + + WRITE_REG(hlcd->Instance->DC_SRD_CHAIN_ADDR, CPHYSADDR(frame)); + + if(hlcd->pdata->frame_status != state_display_start) { + __HAL_SRD_CHAIN_START(hlcd); + } + return 0; +} + +void HAL_PAN_DISPLAY(LCD_HandleTypeDef *hlcd, unsigned int frame_num) +{ + int ret; + struct srdmadesc *frame; + + frame = hlcd->desc[frame_num]; +// dump_rdma_desc_reg(hlcd); + + if (!is_tft(hlcd->pdata)) + ret = lcdc_slcd_pan_display(hlcd, frame); + else + ret = lcdc_tft_pan_display(hlcd, frame); + +} + +static void init_lcdc(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + + __HAL_EOD_MSK(hlcd); + __HAL_UOT_MSK(hlcd); + __HAL_SSA_MSK(hlcd); + __HAL_SOS_MSK(hlcd); + __HAL_EOS_MSK(hlcd); + + WRITE_REG(hlcd->Instance->DC_CLR_ST, READ_REG(hlcd->Instance->DC_INT_FLAG)); + __HAL_BURST_LEN_RDMA(hlcd, BURST_LEN_RDMA_32); + + int dither_en = 0; + int dither_dw = 0; + if (pdata->fb_fmt == fb_fmt_RGB888 || pdata->fb_fmt == fb_fmt_ARGB8888) { + if (pdata->out_format != OUT_FORMAT_RGB888) + dither_en = 1; + if (pdata->out_format == OUT_FORMAT_RGB444) + dither_dw = 0b111111; + if (pdata->out_format == OUT_FORMAT_RGB555) + dither_dw = 0b101010; + if (pdata->out_format == OUT_FORMAT_RGB565) + dither_dw = 0b100110; + if (pdata->out_format == OUT_FORMAT_RGB666) + dither_dw = 0b010101; + } + + __HAL_DP_DITHER_EN(hlcd, dither_en); + __HAL_DP_DITHER_DW(hlcd, dither_dw); + + __HAL_DITHER_CLKGATE_EN(hlcd); + __HAL_SLCD_CLKGATE_EN(hlcd); + __HAL_TFT_CLKGATE_EN(hlcd); + + if(is_slcd(pdata)) { + __HAL_DP_IF_SEL(hlcd, DISPLAY_SELECT_SLCD); + prom_printk("is_slcd \n"); + } else { + __HAL_DP_IF_SEL(hlcd, DISPLAY_SELECT_TFT); + prom_printk("is_tft \n"); + } + + if (is_tft(pdata)){ + init_tft(hlcd); + prom_printk("tft mode \n"); + } + if (is_slcd(pdata)){ + init_slcd(hlcd); + prom_printk("slcd mode \n"); + } + +} + +static int slcd_pixclock_cycle(struct lcd_data *pdata) +{ + + int cycle = 0; + int width = pdata->slcd->mcu_data_width; + int pix_fmt = pdata->out_format; + if (width == MCU_WIDTH_8BITS) { + if (pix_fmt == OUT_FORMAT_RGB565) + cycle = 2; + if (pix_fmt == OUT_FORMAT_RGB888) + cycle = 3; + } + if (width == MCU_WIDTH_9BITS) { + if (pix_fmt == OUT_FORMAT_RGB666) + cycle = 2; + } + if (width == MCU_WIDTH_16BITS) { + if (pix_fmt == OUT_FORMAT_RGB666) + cycle = 1; + } + + return cycle * 2 + 1; +} + +void auto_calculate_pixel_clock(struct lcd_data *pdata) +{ + int hps = pdata->hsync_len; + int hpe = hps + pdata->left_margin + pdata->xres + pdata->right_margin; + int vps = pdata->vsync_len; + int vpe = vps + pdata->upper_margin + pdata->yres + pdata->lower_margin; + + if (!pdata->refresh) + pdata->refresh = 40; + + if (is_tft(pdata)) { + if (!pdata->pixclock) + pdata->pixclock = hpe * vpe * pdata->refresh; + } + + if (is_slcd(pdata)) { + if (!pdata->pixclock) { + pdata->pixclock = pdata->xres * pdata->yres * pdata->refresh; + pdata->pixclock *= slcd_pixclock_cycle(pdata); + } + + if (!pdata->slcd->pixclock_when_init) + pdata->slcd->pixclock_when_init = pdata->xres * pdata->yres * 3; + } +} + +void HAL_LCDC_INIT(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd->pdata; + int ret; + + __HAL_Lock_Init(&hlcd->lock); + + if (is_slcd(pdata)){ + ret = check_scld_fmt(hlcd); + if(ret < 0) + prom_printk("slcd fmt error\n"); + } + + ret = init_lcd_gpio(pdata); + if(ret < 0) + prom_printk("init lcd gpio failed\n"); + + auto_calculate_pixel_clock(pdata); + +} + +void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + + init_lcdc(hlcd); + + if (pdata->power_on) + pdata->power_on(); + + if (is_slcd(pdata)){ + process_slcd_data_table(hlcd, pdata->slcd->slcd_data_table, pdata->slcd->slcd_data_table_length); +// __HAL_FMT_EN(hlcd); + } + + hlcd->pdata->frame_status = state_clear; +} + +void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer) +{ + int i; + int format; + for (i = 0; i < MAX_SRDMA_DESC_NUM; i++){ + if (hlcd->desc[i] == NULL) { + break; + } + switch (hlcd->pdata->fb_fmt) { + case fb_fmt_RGB555: + format = 0; break; + case fb_fmt_RGB565: + format = 2; break; + case fb_fmt_ARGB8888: + case fb_fmt_RGB888: + format = 4; break; + default: + prom_printk("format err:%d\n", hlcd->pdata->fb_fmt); break; + } + + hlcd->desc[i]->RdmaNextCfgAddr = CPHYSADDR(hlcd->desc[i]); + + hlcd->desc[i]->FrameCtrl = 0; + hlcd->desc[i]->FrameCtrl |= (format << 19); + hlcd->desc[i]->FrameCtrl |= (0 << 16); + hlcd->desc[i]->FrameCtrl &= ~(1); + + hlcd->desc[i]->InterruptControl = 0; + hlcd->desc[i]->InterruptControl |= 1 << 1; + hlcd->desc[i]->InterruptControl |= 1 << 2; + hlcd->desc[i]->InterruptControl |= 1 << 17; + + hlcd->desc[i]->stride = hlcd->pdata->xres; + + hlcd->desc[i]->FrameBufferAddr = CPHYSADDR(((unsigned long)buffer)); + //CPHYSADDR(((unsigned long)buffer) + format * i * hlcd->pdata->frame_mem); + Flush_Cache_AllAddr(); +// CleanDCache_by_Addr((unsigned long*)hlcd->desc[i], sizeof(struct srdmadesc)); + prom_printk("==================== rdma desc =====================\n"); + prom_printk("hlcd->desc[%d]->RdmaNextCfgAddr = 0x%x\n",i, hlcd->desc[i]->RdmaNextCfgAddr); + prom_printk("hlcd->desc[%d]->FrameCtrl = 0x%x\n",i, hlcd->desc[i]->FrameCtrl); + prom_printk("hlcd->desc[%d]->InterruptControl= 0x%x\n",i, hlcd->desc[i]->InterruptControl); + prom_printk("hlcd->desc[%d]->stride = 0x%x\n",i, hlcd->desc[i]->stride); + prom_printk("hlcd->desc[%d]->FrameBufferAddr = 0x%x\n",i, hlcd->desc[i]->FrameBufferAddr); + prom_printk("==================== rdma desc =====================\n"); + } +} + +void HAL_SRDMA_START(LCD_HandleTypeDef *hlcd) +{ + __HAL_SRD_CHAIN_SET(hlcd); + WRITE_REG(hlcd->Instance->DC_SRD_CHAIN_ADDR, CPHYSADDR(hlcd->desc[0])); + __HAL_SRD_CHAIN_START(hlcd); + //lcdc_dump_regs(hlcd); +} + +void lcdc_irq_handler(int irq, void *data) +{ + LCD_HandleTypeDef *hlcd = (LCD_HandleTypeDef*)data; + + __HAL_Lock(&hlcd->lock); + + if (__HAL_INT_EOD(hlcd)) { + //prom_printk("__HAL_INT_EOD\n"); + hlcd->pdata->frame_status = state_display_end; + __GEN_CLR_DISP_END(hlcd); + __HAL_UnLock(&hlcd->lock); + return; + } + if (__HAL_INT_SSA(hlcd)) { + prom_printk("__HAL_INT_SSA\n"); + __GEN_CLR_STOP_SRD_ACK(hlcd); + hlcd->pdata->frame_status = state_stop; + __HAL_UnLock(&hlcd->lock); + return; + } + + if (__HAL_INT_UOT(hlcd)) { + prom_printk("err: lcd underrun\n"); + __GEN_CLR_TFT_UNDR(hlcd); + __HAL_UnLock(&hlcd->lock); + return; + } + if (__HAL_INT_EOS(hlcd)) { + //prom_printk("RDMA END\n"); + __GEN_CLR_SRD_END(hlcd); + __HAL_UnLock(&hlcd->lock); + return; + } + if (__HAL_INT_SOS(hlcd)) { + __GEN_CLR_SRD_START(hlcd); + hlcd->pdata->frame_status = state_display_start; + //prom_printk("RDAM START\n"); + __HAL_UnLock(&hlcd->lock); + return; + } +} +/** + * @} + */ diff --git a/drivers/drivers-x2600/src/x2600_ll_cpm.c b/drivers/drivers-x2600/src/x2600_ll_cpm.c index a3c93c2d..443afec0 100755 --- a/drivers/drivers-x2600/src/x2600_ll_cpm.c +++ b/drivers/drivers-x2600/src/x2600_ll_cpm.c @@ -322,50 +322,6 @@ HAL_StatusTypeDef CPM_CGU_MAC_Stop(CPM_TypeDef *CPMx) return HAL_OK; } -/** - * @brief 配置LPCGU时钟分频比，并打开时钟 - * @param CPMx: 指向CPMx的基地址 - * @param Config: 描述配置内容 - * @retval HAL Status. - */ - -HAL_StatusTypeDef CPM_CGU_LCD_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config) -{ - uint32_t val; - uint32_t config; - uint32_t count; - /* 参数检查 */ - assert_param(IS_CPM_INSTALL(CPMx)); - assert_param(IS_LPCDR_CONFIG(Config->Config)); - assert_param(IS_LPCDR_DIV(Config->Div)); - assert_param(IS_LPCDR_PLLMUX(Config->PLLMux)); - /* 读取LPDR寄存器值*/ - val = READ_REG(CPMx->LPCDR); - val |= LPCDR_CE_LCD; - /* 如果已打开时钟，先关闭时钟*/ - if (val & LPCDR_LCD_STOP_Msk) { - val |= LPCDR_LCD_STOP; - WRITE_REG(CPMx->LPCDR, val); - count = SystemCoreClock / 8U / 1000U * 8; - /*等待BUSY. */ - while (--count && (READ_REG(CPMx->LPCDR) & LPCDR_LCD_BUSY)); - if (count == 0) { - return HAL_TIMEOUT; - } - } - /* 重新配时钟，并打开时钟*/ - config = Config->Div | Config->PLLMux | Config->Config; - WRITE_REG(CPMx->LPCDR, config | LPCDR_CE_LCD); - count = SystemCoreClock / 8U / 1000U * 8; - /* 等待时钟稳定 */ - while (--count && (READ_REG(CPMx->LPCDR) & LPCDR_LCD_BUSY)); - if (count == 0) { - return HAL_TIMEOUT; - } - /* 去掉CE_ENABLE.保护防止误操作 */ - WRITE_REG(CPMx->LPCDR, config); - return HAL_OK; -} /** * @brief 停止LPCGU的时钟 @@ -928,6 +884,50 @@ HAL_StatusTypeDef CPM_CGU_CAN1_Stop(CPM_TypeDef *CPMx) #endif +/** + * @brief 配置LPCGU时钟分频比，并打开时钟 + * @param CPMx: 指向CPMx的基地址 + * @param Config: 描述配置内容 + * @retval HAL Status. + */ + +HAL_StatusTypeDef CPM_CGU_LCD_Start(CPM_TypeDef *CPMx, LL_CPM_CGU_ConfigTypeDef *Config) +{ + uint32_t val; + uint32_t config; + uint32_t count; + /* 参数检查 */ + assert_param(IS_CPM_INSTALL(CPMx)); + assert_param(IS_LPCDR_CONFIG(Config->Config)); + assert_param(IS_LPCDR_DIV(Config->Div)); + assert_param(IS_LPCDR_PLLMUX(Config->PLLMux)); + /* 读取LPDR寄存器值*/ + val = READ_REG(CPMx->LPCDR); + val |= LPCDR_CE_LCD; + /* 如果已打开时钟，先关闭时钟*/ + if (val & LPCDR_LCD_STOP_Msk) { + val |= LPCDR_LCD_STOP; + WRITE_REG(CPMx->LPCDR, val); + count = SystemCoreClock / 8U / 1000U * 8; + /*等待BUSY. */ + while (--count && (READ_REG(CPMx->LPCDR) & LPCDR_LCD_BUSY)); + if (count == 0) { + return HAL_TIMEOUT; + } + } + /* 重新配时钟，并打开时钟*/ + config = Config->Div | Config->PLLMux | Config->Config; + WRITE_REG(CPMx->LPCDR, config | LPCDR_CE_LCD); + count = SystemCoreClock / 8U / 1000U * 8; + /* 等待时钟稳定 */ + while (--count && (READ_REG(CPMx->LPCDR) & LPCDR_LCD_BUSY)); + if (count == 0) { + return HAL_TIMEOUT; + } + /* 去掉CE_ENABLE.保护防止误操作 */ + WRITE_REG(CPMx->LPCDR, config); + return HAL_OK; +} /** * @brief 配置SADC CGU时钟分频比，并打开时钟 * @param CPMx: 指向CPMx的基地址 diff --git a/projects/x2660-halley/Examples/lcd/.vscode/cmake-kits.json b/projects/x2660-halley/Examples/lcd/.vscode/cmake-kits.json new file mode 100644 index 00000000..7c98a0d9 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/.vscode/cmake-kits.json @@ -0,0 +1,18 @@ +[ + { + "name": "GCC for ingenic cross compile on Windows", + + "toolchainFile": "mips-gcc-sde-elf.cmake", + "preferredGenerator": { + "name":"MinGW Makefiles" + } + }, + { + "name": "GCC for ingenic cross compile on Linux", + "toolchainFile": "mips-gcc-sde-elf.cmake", + "preferredGenerator": { + "name":"Unix Makefiles" + } + } +] + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd/.vscode/launch.json b/projects/x2660-halley/Examples/lcd/.vscode/launch.json new file mode 100644 index 00000000..8ddcfe12 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/.vscode/launch.json @@ -0,0 +1,63 @@ +{ + "version": "0.2.0", + "configurations": [ + // GDB Debugging: + { + "program": "${command:cmake.launchTargetPath}", + "name": "Launch (gdb)", + "request": "launch", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "console": "integratedTerminal", + "internalConsoleOptions": "openOnSessionStart", + "type": "cppdbg", + "MIMode": "gdb", + "miDebuggerPath": "mips-sde-elf-gdb", + "miDebuggerArgs": "", + "miDebuggerServerAddress": "localhost:3333", + "targetArchitecture": "mips", + "preLaunchTask": "adb forward", + "customLaunchSetupCommands": [ + { + "description": "gdb 启用整齐打印", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "text":"cd ${workspaceFolder}", + "ignoreFailures": false + }, + { + "text":"file build/${command:cmake.buildType}/${command:cmake.launchTargetFilename}", + "ignoreFailures": false + }, + { + "text": "target remote localhost:3333", + "ignoreFailures": false + }, + { + "text": "monitor reset halt", + "ignoreFailures": false + }, + { + "text": "monitor x1600_init", + "ignoreFailures": false + }, + { + "text": "load", + "ignoreFailures": false + }, + { + "text": "monitor mips32 invalidate all", + "ignoreFailures": false + } + ], + "logging": { + "engineLogging": false, + "programOutput": true + } + } + ] + } + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd/.vscode/settings.json b/projects/x2660-halley/Examples/lcd/.vscode/settings.json new file mode 100644 index 00000000..0537c076 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + "cmake.buildDirectory": "${workspaceFolder}/build/${buildType}", + "files.associations": { + "*.build": "makefile", + "*.mk": "makefile", + "Makefile*": "makefile", + "x16xx_hal.h": "c" + } +} \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd/.vscode/tasks.json b/projects/x2660-halley/Examples/lcd/.vscode/tasks.json new file mode 100644 index 00000000..53b4731e --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/.vscode/tasks.json @@ -0,0 +1,12 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "adb forward", + "type": "shell", + "command": "adb forward tcp:3333 tcp:3333", + }, + ] +} \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd/CMakeLists.txt b/projects/x2660-halley/Examples/lcd/CMakeLists.txt new file mode 100644 index 00000000..14ccb1b6 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/CMakeLists.txt @@ -0,0 +1,110 @@ +cmake_minimum_required(VERSION 3.8) +# +# Core project settings +# +Project(lcd) # Modified +enable_language(C CXX ASM) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS ON) +set(PROJ_PATH ${CMAKE_CURRENT_SOURCE_DIR}) +set(SDK_PATH ${PROJ_PATH}/../../../../) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Set linker script +set(linker_script_SRC ${SDK_PATH}/cpu/core-riscv/ld.lds) # Modified +set(EXECUTABLE ${CMAKE_PROJECT_NAME}) +set(CPU_PARAMETERS "-march=rv32imc -mabi=ilp32 -Wno-abi") + +set(CMAKE_ASM_FLAGS "${CPU_PARAMETERS} -D_ASSEMBLER_ -D__ASSEMBLY__") + +set(CMAKE_C_FLAGS "${CPU_PARAMETERS} -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Wall -fdata-sections -ffunction-sections") + +# Compiler options + +if(CMAKE_BUILD_TYPE STREQUAL Debug) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 -g -ggdb -DDEBUG") +else() + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O2") +endif() + +set(CMAKE_CXX_FLAGS ${CMAKE_C_FLAGS}) + +set(CMAKE_LD_FLAGS "${CPU_PARAMETERS}") + + +set(sources_SRCS # Modified + ${SDK_PATH}/cpu/core-riscv/spinlock.c + ${SDK_PATH}/cpu/core-riscv/start.S + ${SDK_PATH}/cpu/core-riscv/genex.S + ${SDK_PATH}/cpu/core-riscv/traps.c + ${SDK_PATH}/cpu/soc-x2600/src/interrupt.c + ${SDK_PATH}/cpu/soc-x2600/src/serial.c + ${SDK_PATH}/cpu/soc-x2600/src/startup.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_def.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_lcd.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_cpm.c + ${SDK_PATH}/lib/libc/minimal/ctype.c + ${SDK_PATH}/lib/libc/minimal/div64.c + ${SDK_PATH}/lib/libc/minimal/string.c + ${SDK_PATH}/lib/libc/minimal/vsprintf.c + main.c + kd050wvfpa029.c + +) + +if(CMAKE_EXPORT_COMPILE_COMMANDS) + set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) + set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) +endif() + +# +# Include directories +# +#set(include_path_DIRS +# Modified + +include_directories( + ${PROJ_PATH}/include + ${SDK_PATH}/lib/libc/minimal/include + ${SDK_PATH}/drivers/drivers-x2600/include + ${SDK_PATH}/cpu/core-riscv/include + ${SDK_PATH}/cpu/soc-x2600/include + +) + +# +# -L libdirs. +# +link_directories( +#path/to/lib +) + +# Executable files +add_executable(${EXECUTABLE} ${sources_SRCS}) + +# Linker options +target_link_libraries(${EXECUTABLE} PRIVATE + -T${linker_script_SRC} + ${CMAKE_LD_FLAGS} + -Wl,-Map=${CMAKE_PROJECT_NAME}.map,--cref + -Wl,--gc-sections + -Wl,--start-group + -Wl,--end-group + -Wl,--print-memory-usage +) + +# Execute post-build to print size +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_SIZE} $ +) + +# Convert output to hex and binary +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin + ) diff --git a/projects/x2660-halley/Examples/lcd/Makefile b/projects/x2660-halley/Examples/lcd/Makefile new file mode 100644 index 00000000..c48c0c33 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/Makefile @@ -0,0 +1,175 @@ +###################################### +# target +###################################### +TARGET = lcd + +SDK_PATH = ../../../../ + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Werror-implicit-function-declaration + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/traps.c \ +$(SDK_PATH)/cpu/core-riscv/spinlock.c \ +$(SDK_PATH)/cpu/soc-x2600/src/startup.c \ +$(SDK_PATH)/cpu/soc-x2600/src/serial.c \ +$(SDK_PATH)/cpu/soc-x2600/src/interrupt.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_def.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_lcd.c \ +$(SDK_PATH)/lib/libc/minimal/vsprintf.c \ +$(SDK_PATH)/lib/libc/minimal/string.c \ +$(SDK_PATH)/lib/libc/minimal/ctype.c \ +$(SDK_PATH)/lib/libc/minimal/div64.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_cpm.c \ +main.c \ +kd050wvfpa029.c + +# ASM sources +ASM_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/start.S \ +$(SDK_PATH)/cpu/core-riscv/genex.S + + +####################################### +# binaries +####################################### +PREFIX = riscv32-ingenicv0-elf- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)as +LD = $(GCC_PATH)/$(PREFIX)ld +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)as +LD = $(PREFIX)ld +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -march=rv32imc -mabi=ilp32 -Wno-abi + +# fpu +FPU = + +# float-abi +FLOAT-ABI = + +# mcu +#MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) +MCU = $(CPU) $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = -D_ASSEMBLER_ -D__ASSEMBLY__ + +# C defines +C_DEFS = + + +# AS includes +AS_INCLUDES = \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ + +# C includes +C_INCLUDES = \ +-Iinclude \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/cpu/soc-x2600/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ +-I$(SDK_PATH)/drivers/drivers-x2600/include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 -O0 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = $(SDK_PATH)/cpu/core-riscv/ld.lds + +# libraries +#LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -nostdlib + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(CC) -c $(ASFLAGS) -o $@ $< + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/projects/x2660-halley/Examples/lcd/include/board_eth_phy_conf.h b/projects/x2660-halley/Examples/lcd/include/board_eth_phy_conf.h new file mode 100644 index 00000000..c907ead4 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/include/board_eth_phy_conf.h @@ -0,0 +1,75 @@ +#ifndef __ETH_PHY_CONF_H +#define __ETH_PHY_CONF_H + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 0x00U +#define MAC_ADDR1 0x11U +#define MAC_ADDR2 0x22U +#define MAC_ADDR3 0x33U +#define MAC_ADDR4 0x44U +#define MAC_ADDR5 0x55U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2600U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2600U) /*!< PHY link status interrupt mask */ + +/* ################## Ethernet peripheral configuration ##################### */ + + + +#endif // __ETH_PHY_CONF_H + diff --git a/projects/x2660-halley/Examples/lcd/include/x2600_hal_conf.h b/projects/x2660-halley/Examples/lcd/include/x2600_hal_conf.h new file mode 100644 index 00000000..f923376a --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/include/x2600_hal_conf.h @@ -0,0 +1,118 @@ +#ifndef __X2600_HAL_CONF_H__ +#define __X2600_HAL_CONF_H__ +/* TODO： 本文件应该通过工具生成，在配置工程中选择不同的组件时，在此处包含不同的头文件 + 暂时包含全部头文件. +*/ + + +/* 1. Includes ---------------------------------------------------- */ + + +/* Hal Module selections. */ +#if 0 +#define HAL_MSC_ENABLED +#define HAL_I2C_ENABLED +#define HAL_UART_ENABLED +#define HAL_ADC_ENABLED +#define HAL_SPI_ENABLED +#define HAL_WDT_ENABLED +#define HAL_TCU_ENABLED +#define HAL_RTC_ENABLED +#define HAL_EFUSE_ENABLED +#define HAL_PWM_ENABLED +#define HAL_GMAC_ENABLED +#define HAL_USB_ENABLED +#endif + +/* 系统时钟配配置，通过工具生成，随开发板或者平台变化.*/ +#include +#include + +#include "x2600_hal_tick.h" +#include "x2600_ll_ost_core.h" +#include "x2600_ll_ost_global.h" +#include "x2600_ll_cpm.h" +#include "x2600_ll_gpio.h" + +#include "x2600_hal_pdma.h" + +//#include "x2600_hal_sfcnor.h" + +#ifdef HAL_MSC_ENABLED + +#endif + +#ifdef HAL_I2C_ENABLED +#include "x2600_hal_i2c.h" +#endif + +#ifdef HAL_UART_ENABLED +#include "x2600_hal_uart.h" +#endif + +#ifdef HAL_ADC_ENABLED +#include "x2600_hal_adc.h" +#endif + +#ifdef HAL_SPI_ENABLED +#include "x2600_hal_spi.h" +#endif + +#ifdef HAL_WDT_ENABLED +#include "x2600_hal_wdt.h" +#endif + +#ifdef HAL_TCU_ENABLED +#include "x2600_hal_tcu.h" +#endif + +#ifdef HAL_RTC_ENABLED +#include "x2600_hal_rtc.h" +#endif + +#ifdef HAL_EFUSE_ENABLED +#include "x2600_ll_efuse.h" +#include "x2600_hal_efuse.h" +#endif + +#ifdef HAL_PWM_ENABLED +#include "x2600_hal_pwm.h" +#endif + +#ifdef HAL_GMAC_ENABLED +#include "x2600_hal_gmac.h" +#endif + +#ifdef HAL_USB_ENABLED +#include "x2600_hal_pcd.h" +#include "x2600_hal_pcd_ex.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* 2. Exported Types ---------------------------------------------- */ + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_H__ */ diff --git a/projects/x2660-halley/Examples/lcd/include/x2600_sysclk_conf.h b/projects/x2660-halley/Examples/lcd/include/x2600_sysclk_conf.h new file mode 100644 index 00000000..333ffc6f --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/include/x2600_sysclk_conf.h @@ -0,0 +1,73 @@ +/** + * @file x2600_sysclk_conf.h + * @author MPU系统软件部团队 + * @brief + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_SYSCLK_CONF_H__ +#define __X2600_SYSCLK_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* 1. Includes ---------------------------------------------------- */ + +/* 2. Exported Types ---------------------------------------------- */ + + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ +#define SYSCLK_EXTAL (24000000) +#define SYSCLK_APLL (1200000000) +#define SYSCLK_MPLL (1200000000) + +#define SystemCoreClock SYSCLK_APLL + +#define CGU_CONFIG_MSC_APLL_24M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 24, \ + .Config = 0 } + +#define CGU_CONFIG_MSC_APLL_48M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 11, \ + .Config = 0 } + + +#define CGU_CONFIG_SSI_MPLL_500K { \ + .PLLMux = SSICDR_MPLL, \ + .Div = 15, \ + .Config = 0 } + +#define CGU_CONFIG_LCD_MPLL_28M { \ + .PLLMux = LPCDR_MPLL, \ + .Div = 64, \ + .Config = 0} + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_ADC_H__ */ diff --git a/projects/x2660-halley/Examples/lcd/kd050wvfpa029.c b/projects/x2660-halley/Examples/lcd/kd050wvfpa029.c new file mode 100644 index 00000000..5545c391 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/kd050wvfpa029.c @@ -0,0 +1,69 @@ +#include +#include +#include + + +//#define BUFSIZE 800*480 + +//LL_CPM_CGU_ConfigTypeDef LcdCguConfig = CGU_CONFIG_LCD_MPLL_28M; + +//__align(32) uint32_t framebuffer[BUFSIZE * MAX_SRDMA_DESC_NUM] = {0x0}; + +struct tft_config tft = { + .even_line_order = EVEN_RGBTORGB, + .odd_line_order = ODD_RGBTORGB, + .pix_clk_polarity = AT_RISING_EDGE, + .de_active_level = AT_HIGH_LEVEL, + .hsync_active_level = AT_HIGH_LEVEL, + .vsync_active_level = AT_HIGH_LEVEL, +}; + +int kd050wvfpa029_power_on(void); +int kd050wvfpa029_power_off(void); + +struct lcd_data lcdc_data = { + .name = "kd050wvfpa029", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 0, // 自动计算 + .left_margin = 48, + .right_margin = 48, + .upper_margin = 12, + .lower_margin = 12, + .hsync_len = 8, + .vsync_len = 8, + + .fb_fmt = fb_fmt_RGB888, + .lcd_mode = TFT_24BITS, + .out_format = OUT_FORMAT_RGB888, + + .tft = &tft, + .slcd = NULL, + + .frame_status = 0, + .frame_index = 0, + .frame_mem = 800*480, +// .frame_size = sizeof(framebuffer), + + .power_on = kd050wvfpa029_power_on, + .power_off = kd050wvfpa029_power_off, +}; + +int kd050wvfpa029_power_on(void) +{ +// LL_GPIO_setPinMode(PB_Instance, 3, GPIO_MODE_OUTPUT1); + LL_GPIO_setPinMode(PC_Instance, 11, GPIO_MODE_OUTPUT1); + + return 0; +} + +int kd050wvfpa029_power_off(void) +{ +// LL_GPIO_setPinMode(PB_Instance, 3, GPIO_MODE_OUTPUT0); + LL_GPIO_setPinMode(PC_Instance, 11, GPIO_MODE_OUTPUT0); + + return 0; +} + + diff --git a/projects/x2660-halley/Examples/lcd/main.c b/projects/x2660-halley/Examples/lcd/main.c new file mode 100644 index 00000000..d18347be --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/main.c @@ -0,0 +1,78 @@ +#include + +#define BUFSIZE 100*100 + +__align(32) uint32_t framebuffer[BUFSIZE] = {0x0}; + +LCD_HandleTypeDef LCD_Handle; +LL_CPM_CGU_ConfigTypeDef LcdCguConfig = CGU_CONFIG_LCD_MPLL_28M; + +__align(64) struct srdmadesc desc; +extern struct lcd_data lcdc_data; +extern void kd050wvfpa029_power_on(void); +__attribute__((unused)) static void lcdc_dump_regs(void); + + +int main(void) +{ + int i; + Flush_Cache_AllAddr(); + for(i = 0; i < BUFSIZE; i++){ + framebuffer[i] = 0x00FF0000; + } + + prom_printk("hello world %s, %d\n", __func__, __LINE__); + LCD_Handle.Instance = DPU_Instance; + LCD_Handle.pdata = &lcdc_data; + LCD_Handle.desc[0] = &desc; + + /*使能时钟*/ + CPM_CGU_LCD_Start(CPM_Instance, &LcdCguConfig); + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_LCD); + ll_request_irq(IRQ_INTC0_LCD, lcdc_irq_handler, (void *)&LCD_Handle); + /*初始化GPIO*/ + /*LCD初始化*/ + HAL_LCDC_INIT(&LCD_Handle); + /*配置RDMA参数*/ + HAL_LCDC_ENABLE(&LCD_Handle); + + HAL_SRDMA_INIT(&LCD_Handle, framebuffer); + HAL_SRDMA_START(&LCD_Handle); + while(1); + return 0; +} + + +__attribute__((unused)) static void lcdc_dump_regs(void) +{ + prom_printk("SRD_CHAIN_ADDR = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_SRD_CHAIN_ADDR)); + prom_printk("ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_ST)); + prom_printk("CLR_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_CLR_ST)); + prom_printk("INTC = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_INTC)); + prom_printk("INT_FLAG = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_INT_FLAG)); + prom_printk("COM_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_COM_CONFIG)); + prom_printk("RDMA_DES = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_DES)); + prom_printk("RDMA_CHAIN_SITE = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_CHAIN_SITE)); + prom_printk("RDMA_SITE = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_SITE)); + prom_printk("DISP_COM = 0x%08x\n", READ_REG(LCD_Handle.Instance->DISP_COM)); + prom_printk("PCFG_RD_CTRL = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_PCFG_RD_CTRL)); + + prom_printk("SLCD_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_PANEL_CFG)); + prom_printk("SLCD_WR_DUTY = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_WR_DUTY)); + prom_printk("SLCD_TIMING = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_TIMING)); + prom_printk("SLCD_FRM_SIZE = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_FRM_SIZE)); + prom_printk("SLCD_SLOW_TIME = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_SLOW_TIME)); + prom_printk("SLCD_REG_IF = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_REG_IF)); + prom_printk("SLCD_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_ST)); + prom_printk("SLCD_REG_CTRL = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_REG_CTRL)); + + prom_printk("TFT_HSYNC = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMING_HSYNC)); + prom_printk("TFT_VSYNC = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_VSYNC)); + prom_printk("TFT_HDE = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_HDE)); + prom_printk("TFT_VDE = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_VDE)); + prom_printk("TFT_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TRAN_CFG)); + prom_printk("TFT_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_ST)); +} + + + diff --git a/projects/x2660-halley/Examples/lcd/riscv32-gcc.cmake b/projects/x2660-halley/Examples/lcd/riscv32-gcc.cmake new file mode 100644 index 00000000..d09813df --- /dev/null +++ b/projects/x2660-halley/Examples/lcd/riscv32-gcc.cmake @@ -0,0 +1,18 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv32) + +# Some default GCC settings +set(TOOLCHAIN_PREFIX "riscv32-ingenicv0-elf-") + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++) + +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) -- Gitee