From 5e841c5af753b96b143882cee00531a7b245e96e Mon Sep 17 00:00:00 2001 From: "lichao.ren" Date: Wed, 31 May 2023 09:16:21 +0800 Subject: [PATCH] [Add] Add TFT MIPI function --- cpu/soc-x2600/include/dphy_tx.h | 989 +++++++++++ cpu/soc-x2600/include/dsi.h | 1457 +++++++++++++++++ cpu/soc-x2600/include/x2600.h | 8 + drivers/drivers-x2600/ChangeLog | 1 + .../drivers-x2600/include/x2600_hal_conf.h | 7 + drivers/drivers-x2600/include/x2600_hal_lcd.h | 65 +- .../include/x2600_hal_mipi_dsi.h | 177 ++ .../drivers-x2600/include/x2600_ll_mipi_dsi.h | 929 +++++++++++ drivers/drivers-x2600/src/x2600_hal_lcd.c | 61 +- .../drivers-x2600/src/x2600_hal_mipi_dsi.c | 395 +++++ drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c | 615 +++++++ .../Examples/lcd-mipi/.vscode/cmake-kits.json | 18 + .../Examples/lcd-mipi/.vscode/launch.json | 63 + .../Examples/lcd-mipi/.vscode/settings.json | 9 + .../Examples/lcd-mipi/.vscode/tasks.json | 12 + .../Examples/lcd-mipi/CMakeLists.txt | 113 ++ .../x2660-halley/Examples/lcd-mipi/Makefile | 178 ++ .../x2660-halley/Examples/lcd-mipi/hc050.c | 128 ++ .../lcd-mipi/include/board_eth_phy_conf.h | 75 + .../lcd-mipi/include/x2600_hal_conf.h | 118 ++ .../lcd-mipi/include/x2600_sysclk_conf.h | 82 + .../x2660-halley/Examples/lcd-mipi/main.c | 82 + .../Examples/lcd-mipi/riscv32-gcc.cmake | 18 + 23 files changed, 5578 insertions(+), 22 deletions(-) create mode 100755 cpu/soc-x2600/include/dphy_tx.h create mode 100755 cpu/soc-x2600/include/dsi.h create mode 100755 drivers/drivers-x2600/include/x2600_hal_mipi_dsi.h create mode 100755 drivers/drivers-x2600/include/x2600_ll_mipi_dsi.h create mode 100755 drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c create mode 100755 drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c create mode 100644 projects/x2660-halley/Examples/lcd-mipi/.vscode/cmake-kits.json create mode 100644 projects/x2660-halley/Examples/lcd-mipi/.vscode/launch.json create mode 100644 projects/x2660-halley/Examples/lcd-mipi/.vscode/settings.json create mode 100644 projects/x2660-halley/Examples/lcd-mipi/.vscode/tasks.json create mode 100644 projects/x2660-halley/Examples/lcd-mipi/CMakeLists.txt create mode 100644 projects/x2660-halley/Examples/lcd-mipi/Makefile create mode 100644 projects/x2660-halley/Examples/lcd-mipi/hc050.c create mode 100644 projects/x2660-halley/Examples/lcd-mipi/include/board_eth_phy_conf.h create mode 100644 projects/x2660-halley/Examples/lcd-mipi/include/x2600_hal_conf.h create mode 100644 projects/x2660-halley/Examples/lcd-mipi/include/x2600_sysclk_conf.h create mode 100644 projects/x2660-halley/Examples/lcd-mipi/main.c create mode 100644 projects/x2660-halley/Examples/lcd-mipi/riscv32-gcc.cmake diff --git a/cpu/soc-x2600/include/dphy_tx.h b/cpu/soc-x2600/include/dphy_tx.h new file mode 100755 index 00000000..240ae738 --- /dev/null +++ b/cpu/soc-x2600/include/dphy_tx.h @@ -0,0 +1,989 @@ +#ifndef __REG_DPHY_TX_H__ +#define __REG_DPHY_TX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup group_DPHY_TX DPHY_TX控制器 + * @{ + */ + +/** + * @addtogroup g_DPHY_TX_reg DPHY_TX 寄存器定义 + * @{ + */ +/** +* @brief Registers for dphy_tx +*/ +typedef struct { + ////TODO, 添加寄存器Reserved，填充地址空间 + __IO unsigned long XCFGI_D0_BLOCK_R_03_00; /*!< Configure Input D0 ,RW, 0x0000 */ + __IO unsigned long XCFGI_D0_BLOCK_R_07_04; /*!< Configure Input D0 ,RW, 0x0004 */ + __IO unsigned long XCFGI_D0_BLOCK_R_10_08 ; /*!< Configure Input D0 ,RW, 0x0008 */ + unsigned long RESERVED_0xc[1]; /*!< Reserved Memory Area start from 0xc to 0x10*/ + __IO unsigned long XCFGI_D1_BLOCK_R_03_00; /*!< Configure Input D1 ,RW, 0x0010 */ + __IO unsigned long XCFGI_D1_BLOCK_R_07_04; /*!< Configure Input D1 ,RW, 0x0014 */ + __IO unsigned long XCFGI_D1_BLOCK_R_10_08; /*!< Configure Input D1 ,RW, 0x0018 */ + unsigned long RESERVED_0x1c[1]; /*!< Reserved Memory Area start from 0x1c to 0x20*/ + __IO unsigned long XCFGI_CK_BLOCK_R_03_00; /*!< Configure Input CK ,RW, 0x0020 */ + __IO unsigned long XCFGI_CK_BLOCK_R_07_04; /*!< Configure Input CK ,RW, 0x0024 */ + __IO unsigned long XCFGI_CK_BLOCK_R_10_08; /*!< Configure Input CK ,RW, 0x0028 */ + unsigned long RESERVED_0x2c[1]; /*!< Reserved Memory Area start from 0x2c to 0x30*/ + __IO unsigned long XCFGI_GLO_BLOCK_R_03_00; /*!< Configure Input Global ,RW, 0x0030 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_07_04; /*!< Configure Input Global ,RW, 0x0034 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_11_08; /*!< Configure Input Global ,RW, 0x0038 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_15_12; /*!< Configure Input Global ,RW, 0x003C */ + __IO unsigned long XCFGI_GLO_BLOCK_R_19_16; /*!< Configure Input Global ,RW, 0x0040 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_23_20; /*!< Configure Input Global ,RW, 0x0044 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_27_24; /*!< Configure Input Global ,RW, 0x0048 */ + __IO unsigned long XCFGI_GLO_BLOCK_R_30_28; /*!< Configure Input Global ,RW, 0x004C */ + __IO unsigned long XCFGO_BLOCK_R_03_00; /*!< Configure Output ,RW, 0x0050 */ + __IO unsigned long XCFGO_BLOCK_R_07_04; /*!< Configure Output ,RW, 0x0054 */ + __IO unsigned long XCFGO_BLOCK_R_09_08; /*!< Configure Output ,RW, 0x0058 */ + unsigned long RESERVED_0x5c[1]; /*!< Reserved Memory Area start from 0x5c to 0x60*/ + __IO unsigned long DEBUG_SEL_R; /*!< Debug Select ,RW, 0x0060 */ + __IO unsigned long PLL_CLK_SEL_R; /*!< PLL Clock Select ,RW, 0x0064 */ + __IO unsigned long DEBUG_PORT_R; /*!< Debug Port ,RW, 0x0068 */ + unsigned long RESERVED_0x400[229]; /*!< Reserved Memory Area start from 0x68 to 0x400*/ + __IO unsigned long ANA_REG00; /*!< ,W, 0x0400*/ + __IO unsigned long ANA_REG01; /*!< ,W, 0x0404*/ + __IO unsigned long ANA_REG02; /*!< ,W, 0x0408*/ + __IO unsigned long ANA_REG03; /*!< ,W, 0x040C*/ + __IO unsigned long ANA_REG04; /*!< ,W, 0x0410*/ + __IO unsigned long ANA_REG05; /*!< ,W, 0x0414*/ + __IO unsigned long ANA_REG06; /*!< ,W, 0x0418*/ + __IO unsigned long ANA_REG07; /*!< ,W, 0x041C*/ + __IO unsigned long ANA_REG08; /*!< ,W, 0x0420*/ + unsigned long RESERVED_0x42C[2]; /*!< Reserved Memory Area start from 0x420 to 0x42c*/ + __IO unsigned long ANA_REG0B; /*!< ,W, 0x042C*/ + unsigned long RESERVED_0x444[5]; /*!< Reserved Memory Area start from 0x42c to 0x444*/ + __IO unsigned long ANA_REG11; /*!< ,W, 0x0444*/ + unsigned long RESERVED_0x478[12]; /*!< Reserved Memory Area start from 0x444 to 0x478*/ + __IO unsigned long ANA_REG1E; /*!< ,W, 0x0478*/ + unsigned long RESERVED_0x480[1]; /*!< Reserved Memory Area start from 0x478 to 0x480*/ + __IO unsigned long DIG_REG00; /*!< ,W, 0x0480*/ + __IO unsigned long DIG_REG01; /*!< ,W, 0x0484*/ + unsigned long RESERVED_0x5B0[74]; /*!< Reserved Memory Area start from 0x484 to 0x5B0*/ + __IO unsigned long LANG_REG0C; /*!< ,W, 0x05B0*/ + unsigned long RESERVED_0x780[115]; /*!< Reserved Memory Area start from 0x5B0 to 0x780*/ + __IO unsigned long LVDS_REG00; /*!< ,W, 0x0780*/ + __IO unsigned long LVDS_REG01; /*!< ,W, 0x0784*/ + __IO unsigned long LVDS_REG02; /*!< ,W, 0x0788*/ + __IO unsigned long LVDS_REG03; /*!< ,W, 0x078C*/ + __IO unsigned long LVDS_REG04; /*!< ,W, 0x0790*/ + unsigned long RESERVED_0x80C[6]; /*!< Reserved Memory Area start from 0x790 to 0x80C*/ + __IO unsigned long LVDS_REG0B; /*!< ,W, 0x080C*/ + __IO unsigned long LVDS_REG0C; /*!< ,W, 0x0710*/ + __IO unsigned long LVDS_REG0D; /*!< ,W, 0x0714*/ +} DPHY_TX_TypeDef; + +/********* Register BitField Details: XCFGI_D0_BLOCK_R_03_00 BASE+0x0000 *********/ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos (24U) +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Msk (0xffUL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0xff000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3 XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Msk +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_0 (0x1UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x01000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_1 (0x2UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x02000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_2 (0x4UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x04000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_3 (0x8UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x08000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_4 (0x10UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x10000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_5 (0x20UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x20000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_6 (0x40UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x40000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_7 (0x80UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R3_Pos) /*!< 0x80000000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos (16U) +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Msk (0xffUL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2 XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Msk +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_0 (0x1UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00010000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_1 (0x2UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00020000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_2 (0x4UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00040000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_3 (0x8UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00080000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_4 (0x10UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00100000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_5 (0x20UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00200000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_6 (0x40UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00400000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_7 (0x80UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R2_Pos) /*!< 0x00800000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos (8U) +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Msk (0xffUL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1 XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Msk +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_0 (0x1UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00000100 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_1 (0x2UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00000200 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_2 (0x4UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00000400 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_3 (0x8UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00000800 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_4 (0x10UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00001000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_5 (0x20UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00002000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_6 (0x40UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00004000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_7 (0x80UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R1_Pos) /*!< 0x00008000 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos (0U) +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Msk (0xffUL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x000000ff */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0 XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Msk +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_0 (0x1UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000001 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_1 (0x2UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000002 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_2 (0x4UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000004 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_3 (0x8UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000008 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_4 (0x10UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000010 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_5 (0x20UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000020 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_6 (0x40UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000040 */ +#define XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_7 (0x80UL << XCFGI_D0_BLOCK_R_03_00_XCFGI_D0_R0_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_D0_BLOCK_R_07_04 BASE+0x0004 *********/ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos (24U) +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Msk (0xffUL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0xff000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7 XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Msk +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_0 (0x1UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x01000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_1 (0x2UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x02000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_2 (0x4UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x04000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_3 (0x8UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x08000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_4 (0x10UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x10000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_5 (0x20UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x20000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_6 (0x40UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x40000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_7 (0x80UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R7_Pos) /*!< 0x80000000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos (16U) +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Msk (0xffUL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6 XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Msk +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_0 (0x1UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00010000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_1 (0x2UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00020000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_2 (0x4UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00040000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_3 (0x8UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00080000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_4 (0x10UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00100000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_5 (0x20UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00200000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_6 (0x40UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00400000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_7 (0x80UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R6_Pos) /*!< 0x00800000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos (8U) +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Msk (0xffUL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5 XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Msk +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_0 (0x1UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00000100 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_1 (0x2UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00000200 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_2 (0x4UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00000400 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_3 (0x8UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00000800 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_4 (0x10UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00001000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_5 (0x20UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00002000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_6 (0x40UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00004000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_7 (0x80UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R5_Pos) /*!< 0x00008000 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos (0U) +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Msk (0xffUL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x000000ff */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4 XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Msk +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_0 (0x1UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000001 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_1 (0x2UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000002 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_2 (0x4UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000004 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_3 (0x8UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000008 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_4 (0x10UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000010 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_5 (0x20UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000020 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_6 (0x40UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000040 */ +#define XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_7 (0x80UL << XCFGI_D0_BLOCK_R_07_04_XCFGI_D0_R4_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_D0_BLOCK_R_10_08 BASE+0x0008 *********/ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos (16U) +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Msk (0xffUL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10 XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Msk +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_0 (0x1UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00010000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_1 (0x2UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00020000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_2 (0x4UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00040000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_3 (0x8UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00080000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_4 (0x10UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00100000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_5 (0x20UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00200000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_6 (0x40UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00400000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_7 (0x80UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R10_Pos) /*!< 0x00800000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos (8U) +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Msk (0xffUL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9 XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Msk +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_0 (0x1UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00000100 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_1 (0x2UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00000200 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_2 (0x4UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00000400 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_3 (0x8UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00000800 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_4 (0x10UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00001000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_5 (0x20UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00002000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_6 (0x40UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00004000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_7 (0x80UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R9_Pos) /*!< 0x00008000 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos (0U) +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Msk (0xffUL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x000000ff */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8 XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Msk +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_0 (0x1UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000001 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_1 (0x2UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000002 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_2 (0x4UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000004 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_3 (0x8UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000008 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_4 (0x10UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000010 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_5 (0x20UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000020 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_6 (0x40UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000040 */ +#define XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_7 (0x80UL << XCFGI_D0_BLOCK_R_10_08_XCFGI_D0_R8_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_D1_BLOCK_R_03_00 BASE+0x0010 *********/ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos (24U) +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Msk (0xffUL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0xff000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3 XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Msk +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_0 (0x1UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x01000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_1 (0x2UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x02000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_2 (0x4UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x04000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_3 (0x8UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x08000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_4 (0x10UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x10000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_5 (0x20UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x20000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_6 (0x40UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x40000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_7 (0x80UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R3_Pos) /*!< 0x80000000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos (16U) +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Msk (0xffUL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2 XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Msk +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_0 (0x1UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00010000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_1 (0x2UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00020000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_2 (0x4UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00040000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_3 (0x8UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00080000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_4 (0x10UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00100000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_5 (0x20UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00200000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_6 (0x40UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00400000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_7 (0x80UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R2_Pos) /*!< 0x00800000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos (8U) +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Msk (0xffUL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1 XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Msk +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_0 (0x1UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00000100 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_1 (0x2UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00000200 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_2 (0x4UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00000400 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_3 (0x8UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00000800 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_4 (0x10UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00001000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_5 (0x20UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00002000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_6 (0x40UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00004000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_7 (0x80UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R1_Pos) /*!< 0x00008000 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos (0U) +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Msk (0xffUL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x000000ff */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0 XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Msk +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_0 (0x1UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000001 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_1 (0x2UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000002 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_2 (0x4UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000004 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_3 (0x8UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000008 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_4 (0x10UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000010 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_5 (0x20UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000020 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_6 (0x40UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000040 */ +#define XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_7 (0x80UL << XCFGI_D1_BLOCK_R_03_00_XCFGI_D1_R0_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_D1_BLOCK_R_07_04 BASE+0x0014 *********/ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos (24U) +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Msk (0xffUL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0xff000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7 XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Msk +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_0 (0x1UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x01000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_1 (0x2UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x02000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_2 (0x4UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x04000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_3 (0x8UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x08000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_4 (0x10UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x10000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_5 (0x20UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x20000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_6 (0x40UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x40000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_7 (0x80UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R7_Pos) /*!< 0x80000000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos (16U) +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Msk (0xffUL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6 XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Msk +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_0 (0x1UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00010000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_1 (0x2UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00020000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_2 (0x4UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00040000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_3 (0x8UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00080000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_4 (0x10UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00100000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_5 (0x20UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00200000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_6 (0x40UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00400000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_7 (0x80UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R6_Pos) /*!< 0x00800000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos (8U) +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Msk (0xffUL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5 XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Msk +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_0 (0x1UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00000100 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_1 (0x2UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00000200 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_2 (0x4UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00000400 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_3 (0x8UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00000800 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_4 (0x10UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00001000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_5 (0x20UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00002000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_6 (0x40UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00004000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_7 (0x80UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R5_Pos) /*!< 0x00008000 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos (0U) +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Msk (0xffUL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x000000ff */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4 XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Msk +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_0 (0x1UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000001 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_1 (0x2UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000002 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_2 (0x4UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000004 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_3 (0x8UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000008 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_4 (0x10UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000010 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_5 (0x20UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000020 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_6 (0x40UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000040 */ +#define XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_7 (0x80UL << XCFGI_D1_BLOCK_R_07_04_XCFGI_D1_R4_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_D1_BLOCK_R_10_08 BASE+0x0018 *********/ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos (16U) +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Msk (0xffUL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00ff0000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10 XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Msk +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_0 (0x1UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00010000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_1 (0x2UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00020000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_2 (0x4UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00040000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_3 (0x8UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00080000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_4 (0x10UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00100000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_5 (0x20UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00200000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_6 (0x40UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00400000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_7 (0x80UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R10_Pos) /*!< 0x00800000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos (8U) +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Msk (0xffUL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x0000ff00 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9 XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Msk +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_0 (0x1UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00000100 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_1 (0x2UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00000200 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_2 (0x4UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00000400 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_3 (0x8UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00000800 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_4 (0x10UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00001000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_5 (0x20UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00002000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_6 (0x40UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00004000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_7 (0x80UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R9_Pos) /*!< 0x00008000 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos (0U) +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Msk (0xffUL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x000000ff */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8 XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Msk +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_0 (0x1UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000001 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_1 (0x2UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000002 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_2 (0x4UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000004 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_3 (0x8UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000008 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_4 (0x10UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000010 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_5 (0x20UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000020 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_6 (0x40UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000040 */ +#define XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_7 (0x80UL << XCFGI_D1_BLOCK_R_10_08_XCFGI_D1_R8_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_CK_BLOCK_R_03_00 BASE+0x0020 *********/ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos (24U) +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Msk (0xffUL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0xff000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3 XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Msk +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_0 (0x1UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x01000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_1 (0x2UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x02000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_2 (0x4UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x04000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_3 (0x8UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x08000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_4 (0x10UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x10000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_5 (0x20UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x20000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_6 (0x40UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x40000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_7 (0x80UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R3_Pos) /*!< 0x80000000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos (16U) +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Msk (0xffUL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00ff0000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2 XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Msk +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_0 (0x1UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00010000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_1 (0x2UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00020000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_2 (0x4UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00040000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_3 (0x8UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00080000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_4 (0x10UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00100000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_5 (0x20UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00200000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_6 (0x40UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00400000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_7 (0x80UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R2_Pos) /*!< 0x00800000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos (8U) +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Msk (0xffUL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x0000ff00 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1 XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Msk +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_0 (0x1UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00000100 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_1 (0x2UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00000200 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_2 (0x4UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00000400 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_3 (0x8UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00000800 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_4 (0x10UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00001000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_5 (0x20UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00002000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_6 (0x40UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00004000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_7 (0x80UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R1_Pos) /*!< 0x00008000 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos (0U) +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Msk (0xffUL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x000000ff */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0 XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Msk +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_0 (0x1UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000001 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_1 (0x2UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000002 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_2 (0x4UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000004 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_3 (0x8UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000008 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_4 (0x10UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000010 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_5 (0x20UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000020 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_6 (0x40UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000040 */ +#define XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_7 (0x80UL << XCFGI_CK_BLOCK_R_03_00_XCFGI_CK_R0_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_CK_BLOCK_R_07_04 BASE+0x0024 *********/ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos (24U) +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Msk (0xffUL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0xff000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7 XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Msk +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_0 (0x1UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x01000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_1 (0x2UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x02000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_2 (0x4UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x04000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_3 (0x8UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x08000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_4 (0x10UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x10000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_5 (0x20UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x20000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_6 (0x40UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x40000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_7 (0x80UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R7_Pos) /*!< 0x80000000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos (16U) +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Msk (0xffUL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00ff0000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6 XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Msk +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_0 (0x1UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00010000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_1 (0x2UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00020000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_2 (0x4UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00040000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_3 (0x8UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00080000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_4 (0x10UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00100000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_5 (0x20UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00200000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_6 (0x40UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00400000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_7 (0x80UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R6_Pos) /*!< 0x00800000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos (8U) +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Msk (0xffUL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x0000ff00 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5 XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Msk +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_0 (0x1UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00000100 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_1 (0x2UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00000200 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_2 (0x4UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00000400 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_3 (0x8UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00000800 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_4 (0x10UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00001000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_5 (0x20UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00002000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_6 (0x40UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00004000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_7 (0x80UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R5_Pos) /*!< 0x00008000 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos (0U) +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Msk (0xffUL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x000000ff */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4 XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Msk +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_0 (0x1UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000001 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_1 (0x2UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000002 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_2 (0x4UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000004 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_3 (0x8UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000008 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_4 (0x10UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000010 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_5 (0x20UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000020 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_6 (0x40UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000040 */ +#define XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_7 (0x80UL << XCFGI_CK_BLOCK_R_07_04_XCFGI_CK_R4_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_CK_BLOCK_R_10_08 BASE+0x0028 *********/ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos (16U) +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Msk (0xffUL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00ff0000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10 XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Msk +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_0 (0x1UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00010000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_1 (0x2UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00020000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_2 (0x4UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00040000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_3 (0x8UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00080000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_4 (0x10UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00100000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_5 (0x20UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00200000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_6 (0x40UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00400000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_7 (0x80UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R10_Pos) /*!< 0x00800000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos (8U) +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Msk (0xffUL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x0000ff00 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9 XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Msk +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_0 (0x1UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00000100 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_1 (0x2UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00000200 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_2 (0x4UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00000400 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_3 (0x8UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00000800 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_4 (0x10UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00001000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_5 (0x20UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00002000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_6 (0x40UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00004000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_7 (0x80UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R9_Pos) /*!< 0x00008000 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos (0U) +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Msk (0xffUL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x000000ff */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8 XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Msk +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_0 (0x1UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000001 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_1 (0x2UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000002 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_2 (0x4UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000004 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_3 (0x8UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000008 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_4 (0x10UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000010 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_5 (0x20UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000020 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_6 (0x40UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000040 */ +#define XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_7 (0x80UL << XCFGI_CK_BLOCK_R_10_08_XCFGI_CK_R8_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_03_00 BASE+0x0030 *********/ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos (24U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R3_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos (16U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R2_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos (8U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R1_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos (0U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R0_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_07_04 BASE+0x0034 *********/ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos (24U) +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Msk (0xffUL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7 XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Msk +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_0 (0x1UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_1 (0x2UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_2 (0x4UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_3 (0x8UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_4 (0x10UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_5 (0x20UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_6 (0x40UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_7 (0x80UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R7_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos (16U) +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Msk (0xffUL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6 XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Msk +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_0 (0x1UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_1 (0x2UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_2 (0x4UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_3 (0x8UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_4 (0x10UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_5 (0x20UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_6 (0x40UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_7 (0x80UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R6_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos (8U) +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Msk (0xffUL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5 XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Msk +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_0 (0x1UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_1 (0x2UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_2 (0x4UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_3 (0x8UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_4 (0x10UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_5 (0x20UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_6 (0x40UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_7 (0x80UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R5_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos (0U) +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Msk (0xffUL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4 XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Msk +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_0 (0x1UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_1 (0x2UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_2 (0x4UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_3 (0x8UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_4 (0x10UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_5 (0x20UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_6 (0x40UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_7 (0x80UL << XCFGI_GLO_BLOCK_R_07_04_XCFGI_GLO_R4_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_03_00 BASE+0x0038 *********/ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos (24U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R11_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos (16U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R10_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos (8U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R9_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos (0U) +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Msk (0xffUL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8 XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Msk +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_0 (0x1UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_1 (0x2UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_2 (0x4UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_3 (0x8UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_4 (0x10UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_5 (0x20UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_6 (0x40UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_7 (0x80UL << XCFGI_GLO_BLOCK_R_03_00_XCFGI_GLO_R8_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_15_12 BASE+0x003C *********/ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos (24U) +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Msk (0xffUL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15 XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Msk +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_0 (0x1UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_1 (0x2UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_2 (0x4UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_3 (0x8UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_4 (0x10UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_5 (0x20UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_6 (0x40UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_7 (0x80UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R15_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos (16U) +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Msk (0xffUL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14 XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Msk +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_0 (0x1UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_1 (0x2UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_2 (0x4UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_3 (0x8UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_4 (0x10UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_5 (0x20UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_6 (0x40UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_7 (0x80UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R14_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos (8U) +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Msk (0xffUL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13 XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Msk +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_0 (0x1UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_1 (0x2UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_2 (0x4UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_3 (0x8UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_4 (0x10UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_5 (0x20UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_6 (0x40UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_7 (0x80UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R13_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos (0U) +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Msk (0xffUL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12 XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Msk +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_0 (0x1UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_1 (0x2UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_2 (0x4UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_3 (0x8UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_4 (0x10UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_5 (0x20UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_6 (0x40UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_7 (0x80UL << XCFGI_GLO_BLOCK_R_15_12_XCFGI_GLO_R12_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_19_16 BASE+0x0040 *********/ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos (24U) +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Msk (0xffUL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19 XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Msk +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_0 (0x1UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_1 (0x2UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_2 (0x4UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_3 (0x8UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_4 (0x10UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_5 (0x20UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_6 (0x40UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_7 (0x80UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R19_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos (16U) +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Msk (0xffUL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18 XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Msk +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_0 (0x1UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_1 (0x2UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_2 (0x4UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_3 (0x8UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_4 (0x10UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_5 (0x20UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_6 (0x40UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_7 (0x80UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R18_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos (8U) +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Msk (0xffUL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17 XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Msk +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_0 (0x1UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_1 (0x2UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_2 (0x4UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_3 (0x8UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_4 (0x10UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_5 (0x20UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_6 (0x40UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_7 (0x80UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R17_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos (0U) +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Msk (0xffUL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16 XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Msk +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_0 (0x1UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_1 (0x2UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_2 (0x4UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_3 (0x8UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_4 (0x10UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_5 (0x20UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_6 (0x40UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_7 (0x80UL << XCFGI_GLO_BLOCK_R_19_16_XCFGI_GLO_R16_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_23_20 BASE+0x0044 *********/ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos (24U) +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Msk (0xffUL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23 XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Msk +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_0 (0x1UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_1 (0x2UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_2 (0x4UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_3 (0x8UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_4 (0x10UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_5 (0x20UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_6 (0x40UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_7 (0x80UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R23_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos (16U) +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Msk (0xffUL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22 XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Msk +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_0 (0x1UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_1 (0x2UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_2 (0x4UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_3 (0x8UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_4 (0x10UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_5 (0x20UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_6 (0x40UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_7 (0x80UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R22_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos (8U) +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Msk (0xffUL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21 XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Msk +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_0 (0x1UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_1 (0x2UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_2 (0x4UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_3 (0x8UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_4 (0x10UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_5 (0x20UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_6 (0x40UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_7 (0x80UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R21_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos (0U) +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Msk (0xffUL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20 XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Msk +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_0 (0x1UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_1 (0x2UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_2 (0x4UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_3 (0x8UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_4 (0x10UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_5 (0x20UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_6 (0x40UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_7 (0x80UL << XCFGI_GLO_BLOCK_R_23_20_XCFGI_GLO_R20_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_27_24 BASE+0x0048 *********/ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos (24U) +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Msk (0xffUL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0xff000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27 XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Msk +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_0 (0x1UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x01000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_1 (0x2UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x02000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_2 (0x4UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x04000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_3 (0x8UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x08000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_4 (0x10UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x10000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_5 (0x20UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x20000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_6 (0x40UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x40000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_7 (0x80UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R27_Pos) /*!< 0x80000000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos (16U) +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Msk (0xffUL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26 XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Msk +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_0 (0x1UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_1 (0x2UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_2 (0x4UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_3 (0x8UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_4 (0x10UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_5 (0x20UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_6 (0x40UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_7 (0x80UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R26_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos (8U) +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Msk (0xffUL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25 XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Msk +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_0 (0x1UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_1 (0x2UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_2 (0x4UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_3 (0x8UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_4 (0x10UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_5 (0x20UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_6 (0x40UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_7 (0x80UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R25_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos (0U) +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Msk (0xffUL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24 XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Msk +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_0 (0x1UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_1 (0x2UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_2 (0x4UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_3 (0x8UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_4 (0x10UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_5 (0x20UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_6 (0x40UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_7 (0x80UL << XCFGI_GLO_BLOCK_R_27_24_XCFGI_GLO_R24_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_GLO_BLOCK_R_30_28 BASE+0x004C *********/ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos (16U) +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Msk (0xffUL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00ff0000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30 XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Msk +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_0 (0x1UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00010000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_1 (0x2UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00020000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_2 (0x4UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00040000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_3 (0x8UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00080000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_4 (0x10UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00100000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_5 (0x20UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00200000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_6 (0x40UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00400000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_7 (0x80UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R30_Pos) /*!< 0x00800000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos (8U) +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Msk (0xffUL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x0000ff00 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29 XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Msk +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_0 (0x1UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00000100 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_1 (0x2UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00000200 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_2 (0x4UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00000400 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_3 (0x8UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00000800 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_4 (0x10UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00001000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_5 (0x20UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00002000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_6 (0x40UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00004000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_7 (0x80UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R29_Pos) /*!< 0x00008000 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos (0U) +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Msk (0xffUL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x000000ff */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28 XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Msk +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_0 (0x1UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000001 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_1 (0x2UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000002 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_2 (0x4UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000004 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_3 (0x8UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000008 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_4 (0x10UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000010 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_5 (0x20UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000020 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_6 (0x40UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000040 */ +#define XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_7 (0x80UL << XCFGI_GLO_BLOCK_R_30_28_XCFGI_GLO_R28_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGO_BLOCK_R_03_00 BASE+0x0050 *********/ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos (24U) +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_Msk (0xffUL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0xff000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3 XCFGO_BLOCK_R_03_00_XCFGO_R3_Msk +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_0 (0x1UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x01000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_1 (0x2UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x02000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_2 (0x4UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x04000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_3 (0x8UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x08000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_4 (0x10UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x10000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_5 (0x20UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x20000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_6 (0x40UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x40000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R3_7 (0x80UL << XCFGO_BLOCK_R_03_00_XCFGO_R3_Pos) /*!< 0x80000000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos (16U) +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_Msk (0xffUL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00ff0000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2 XCFGO_BLOCK_R_03_00_XCFGO_R2_Msk +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_0 (0x1UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00010000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_1 (0x2UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00020000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_2 (0x4UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00040000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_3 (0x8UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00080000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_4 (0x10UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00100000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_5 (0x20UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00200000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_6 (0x40UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00400000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R2_7 (0x80UL << XCFGO_BLOCK_R_03_00_XCFGO_R2_Pos) /*!< 0x00800000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos (8U) +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_Msk (0xffUL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x0000ff00 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1 XCFGO_BLOCK_R_03_00_XCFGO_R1_Msk +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_0 (0x1UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00000100 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_1 (0x2UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00000200 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_2 (0x4UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00000400 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_3 (0x8UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00000800 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_4 (0x10UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00001000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_5 (0x20UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00002000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_6 (0x40UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00004000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R1_7 (0x80UL << XCFGO_BLOCK_R_03_00_XCFGO_R1_Pos) /*!< 0x00008000 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos (0U) +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_Msk (0xffUL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x000000ff */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0 XCFGO_BLOCK_R_03_00_XCFGO_R0_Msk +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_0 (0x1UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000001 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_1 (0x2UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000002 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_2 (0x4UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000004 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_3 (0x8UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000008 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_4 (0x10UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000010 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_5 (0x20UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000020 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_6 (0x40UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000040 */ +#define XCFGO_BLOCK_R_03_00_XCFGO_R0_7 (0x80UL << XCFGO_BLOCK_R_03_00_XCFGO_R0_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGO_BLOCK_R_07_04 BASE+0x0054 *********/ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos (24U) +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_Msk (0xffUL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0xff000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7 XCFGO_BLOCK_R_07_04_XCFGO_R7_Msk +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_0 (0x1UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x01000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_1 (0x2UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x02000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_2 (0x4UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x04000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_3 (0x8UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x08000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_4 (0x10UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x10000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_5 (0x20UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x20000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_6 (0x40UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x40000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R7_7 (0x80UL << XCFGO_BLOCK_R_07_04_XCFGO_R7_Pos) /*!< 0x80000000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos (16U) +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_Msk (0xffUL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00ff0000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6 XCFGO_BLOCK_R_07_04_XCFGO_R6_Msk +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_0 (0x1UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00010000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_1 (0x2UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00020000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_2 (0x4UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00040000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_3 (0x8UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00080000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_4 (0x10UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00100000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_5 (0x20UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00200000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_6 (0x40UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00400000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R6_7 (0x80UL << XCFGO_BLOCK_R_07_04_XCFGO_R6_Pos) /*!< 0x00800000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos (8U) +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_Msk (0xffUL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x0000ff00 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5 XCFGO_BLOCK_R_07_04_XCFGO_R5_Msk +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_0 (0x1UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00000100 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_1 (0x2UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00000200 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_2 (0x4UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00000400 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_3 (0x8UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00000800 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_4 (0x10UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00001000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_5 (0x20UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00002000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_6 (0x40UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00004000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R5_7 (0x80UL << XCFGO_BLOCK_R_07_04_XCFGO_R5_Pos) /*!< 0x00008000 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos (0U) +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_Msk (0xffUL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x000000ff */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4 XCFGO_BLOCK_R_07_04_XCFGO_R4_Msk +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_0 (0x1UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000001 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_1 (0x2UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000002 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_2 (0x4UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000004 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_3 (0x8UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000008 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_4 (0x10UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000010 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_5 (0x20UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000020 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_6 (0x40UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000040 */ +#define XCFGO_BLOCK_R_07_04_XCFGO_R4_7 (0x80UL << XCFGO_BLOCK_R_07_04_XCFGO_R4_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: XCFGI_BLOCK_R_91_88 BASE+0x0058 *********/ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos (8U) +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_Msk (0xffUL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x0000ff00 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9 XCFGI_BLOCK_R_91_88_XCFGO_R9_Msk +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_0 (0x1UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00000100 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_1 (0x2UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00000200 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_2 (0x4UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00000400 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_3 (0x8UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00000800 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_4 (0x10UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00001000 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_5 (0x20UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00002000 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_6 (0x40UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00004000 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R9_7 (0x80UL << XCFGI_BLOCK_R_91_88_XCFGO_R9_Pos) /*!< 0x00008000 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos (0U) +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_Msk (0xffUL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x000000ff */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8 XCFGI_BLOCK_R_91_88_XCFGO_R8_Msk +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_0 (0x1UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000001 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_1 (0x2UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000002 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_2 (0x4UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000004 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_3 (0x8UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000008 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_4 (0x10UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000010 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_5 (0x20UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000020 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_6 (0x40UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000040 */ +#define XCFGI_BLOCK_R_91_88_XCFGO_R8_7 (0x80UL << XCFGI_BLOCK_R_91_88_XCFGO_R8_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: DEBUG_SEL_R BASE+0x0060 *********/ +#define DEBUG_SEL_R_VCONTROL_Pos (16U) +#define DEBUG_SEL_R_VCONTROL_Msk (0x1fUL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x001f0000 */ +#define DEBUG_SEL_R_VCONTROL DEBUG_SEL_R_VCONTROL_Msk +#define DEBUG_SEL_R_VCONTROL_0 (0x1UL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x00010000 */ +#define DEBUG_SEL_R_VCONTROL_1 (0x2UL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x00020000 */ +#define DEBUG_SEL_R_VCONTROL_2 (0x4UL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x00040000 */ +#define DEBUG_SEL_R_VCONTROL_3 (0x8UL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x00080000 */ +#define DEBUG_SEL_R_VCONTROL_4 (0x10UL << DEBUG_SEL_R_VCONTROL_Pos) /*!< 0x00100000 */ +#define DEBUG_SEL_R_DEBUG_SEL_Pos (0U) +#define DEBUG_SEL_R_DEBUG_SEL_Msk (0x1fUL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x0000001f */ +#define DEBUG_SEL_R_DEBUG_SEL DEBUG_SEL_R_DEBUG_SEL_Msk +#define DEBUG_SEL_R_DEBUG_SEL_0 (0x1UL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x00000001 */ +#define DEBUG_SEL_R_DEBUG_SEL_1 (0x2UL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x00000002 */ +#define DEBUG_SEL_R_DEBUG_SEL_2 (0x4UL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x00000004 */ +#define DEBUG_SEL_R_DEBUG_SEL_3 (0x8UL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x00000008 */ +#define DEBUG_SEL_R_DEBUG_SEL_4 (0x10UL << DEBUG_SEL_R_DEBUG_SEL_Pos) /*!< 0x00000010 */ + +/********* Register BitField Details: PLL_CLK_SEL_R BASE+0x0064 *********/ +#define PLL_CLK_SEL_R_CFG_TXONLY_Pos (16U) +#define PLL_CLK_SEL_R_CFG_TXONLY_Msk (0x1UL << PLL_CLK_SEL_R_CFG_TXONLY_Pos) /*!< 0x00010000 */ +#define PLL_CLK_SEL_R_CFG_TXONLY PLL_CLK_SEL_R_CFG_TXONLY_Msk +#define PLL_CLK_SEL_R_CFG_TXONLY_0 (0x1UL << PLL_CLK_SEL_R_CFG_TXONLY_Pos) /*!< 0x00010000 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_Pos (0U) +#define PLL_CLK_SEL_R_PLL_CLK_SEL_Msk (0x3ffUL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x000003ff */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL PLL_CLK_SEL_R_PLL_CLK_SEL_Msk +#define PLL_CLK_SEL_R_PLL_CLK_SEL_0 (0x1UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000001 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_1 (0x2UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000002 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_2 (0x4UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000004 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_3 (0x8UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000008 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_4 (0x10UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000010 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_5 (0x20UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000020 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_6 (0x40UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000040 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_7 (0x80UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000080 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_8 (0x100UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000100 */ +#define PLL_CLK_SEL_R_PLL_CLK_SEL_9 (0x200UL << PLL_CLK_SEL_R_PLL_CLK_SEL_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: DEBUG_PORT_R BASE+0x0068 *********/ +/* There is no BitField Details for DEBUG_PORT */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus*/ +#endif /* __REG_DPHY_TX_H__ */ diff --git a/cpu/soc-x2600/include/dsi.h b/cpu/soc-x2600/include/dsi.h new file mode 100755 index 00000000..a2f9c90c --- /dev/null +++ b/cpu/soc-x2600/include/dsi.h @@ -0,0 +1,1457 @@ +#ifndef __REG_DSI_H__ +#define __REG_DSI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup group_DSI DSI控制器 + * @{ + */ + +/** + * @addtogroup g_DSI_reg DSI 寄存器定义 + * @{ + */ +/** +* @brief Registers for dsi +*/ +typedef struct { + ////TODO, 添加寄存器Reserved，填充地址空间 + __IO unsigned long VERSION; /*!< Version of the DSI host controller, , 0x0000 */ + __IO unsigned long PWR_UP; /*!< Core power-up , , 0x0004 */ + __IO unsigned long CLKMGR_CFG; /*!< Configuration of the internal clock dividers, , 0x0008 */ + __IO unsigned long DPI_VCID; /*!< DPI virtual channel id , , 0x000C */ + __IO unsigned long DPI_COLOR_CODING; /*!< DPI color coding , , 0x0010 */ + __IO unsigned long DPI_CFG_POL; /*!< DPI polarity configuration , , 0x0014 */ + __IO unsigned long DPI_LP_CMD_TIM; /*!< Low-power command timing configuration, , 0x0018 */ + unsigned long RESERVED_0x1c[4]; /*!< Reserved Memory Area start from 0x1c to 0x2c*/ + __IO unsigned long PCKHDL_CFG; /*!< Packet handler configuration , , 0x002C */ + __IO unsigned long GEN_VCID; /*!< Generic interface virtual channel id, , 0x0030 */ + __IO unsigned long MODE_CFG; /*!< Video or Command mode selection , , 0x0034 */ + __IO unsigned long VID_MODE_CFG; /*!< Video mode configuration , , 0x0038 */ + __IO unsigned long VID_PKT_SIZE; /*!< Video packet size , , 0x003C */ + __IO unsigned long VID_NUM_CHUNKS; /*!< Number of chunks , , 0x0040 */ + __IO unsigned long VID_NULL_SIZE; /*!< Null packet size , , 0x0044 */ + __IO unsigned long VID_HSA_TIME; /*!< Horizontal Sync Active time , , 0x0048 */ + __IO unsigned long VID_HBP_TIME; /*!< Horizontal Back Porch time , , 0x004C */ + __IO unsigned long VID_HLINE_TIME; /*!< Line time , , 0x0050 */ + __IO unsigned long VID_VSA_LINES; /*!< Vertical Sync Active period , , 0x0054 */ + __IO unsigned long VID_VBP_LINES; /*!< Vertical Back Porch period , , 0x0058 */ + __IO unsigned long VID_VFP_LINES; /*!< Vertical Front Porch period , , 0x005C */ + __IO unsigned long VID_VACTIVE_LINES; /*!< Vertical resolution , , 0x0060 */ + __IO unsigned long EDPI_CMD_SIZE; /*!< Size for eDPI packets , , 0x0064 */ + __IO unsigned long CMD_MODE_CFG; /*!< Command mode configuration , , 0x0068 */ + __IO unsigned long GEN_HDR; /*!< Generic packet header configuration, , 0x006C */ + __IO unsigned long GEN_PLD_DATA; /*!< Generic payload data in and out , , 0x0070 */ + __IO unsigned long CMD_PKT_STATUS; /*!< Command packet status , , 0x0074 */ + __IO unsigned long TO_CNT_CFG; /*!< Timeout timers configuration , , 0x0078 */ + __IO unsigned long HS_RD_TO_CNT; /*!< Peripheral response timeout definition after high-speed read operations, , 0x007C */ + __IO unsigned long LP_RD_TO_CNT; /*!< Peripheral response timeout definition after low-power read operations, , 0x0080 */ + __IO unsigned long HS_WR_TO_CNT; /*!< Peripheral response timeout definition after high-speed write operations, , 0x0084 */ + __IO unsigned long LP_WR_TO_CNT; /*!< Peripheral response timeout definition after low-power write operations, , 0x0088 */ + __IO unsigned long BTA_TO_CNT; /*!< Peripheral response timeout definition after bus turnaround, , 0x008C */ + __IO unsigned long SDF_3D; /*!< 3D control configuration , , 0x0090 */ + __IO unsigned long LPCLK_CTRL; /*!< Low-power in clock lane , , 0x0094 */ + __IO unsigned long PHY_TMR_LPCLK_CFG; /*!< D-PHY timing configuration for the clock lane, , 0x0098 */ + __IO unsigned long PHY_TMR_CFG; /*!< D-PHY timing configuration for data lanes, , 0x009C */ + __IO unsigned long PHY_RSTZ; /*!< D-PHY reset control , , 0x00A0 */ + __IO unsigned long PHY_IF_CFG; /*!< D-PHY interface configuration , , 0x00A4 */ + __IO unsigned long PHY_ULPS_CTRL; /*!< D-PHY Ultra Low-Power control , , 0x00A8 */ + __IO unsigned long PHY_TX_TRIGGERS; /*!< D-PHY transmit triggers , , 0x00AC */ + __IO unsigned long PHY_STATUS; /*!< D-PHY PPI status interface , , 0x00B0 */ + __IO unsigned long PHY_TST_CTRL0; /*!< D-PHY test interface control 0 , , 0x00B4 */ + __IO unsigned long PHY_TST_CTRL1; /*!< D-PHY test interface control 1 , , 0x00B8 */ + __IO unsigned long INT_ST0; /*!< Interrupt status register 0 , , 0x00BC */ + __IO unsigned long INT_ST1; /*!< Interrupt status register 1 , , 0x00C0 */ + __IO unsigned long INT_MSK0; /*!< Masks the interrupt generation triggered by the INT_ST0 register, , 0x00C4 */ + __IO unsigned long INT_MSK1; /*!< Masks the interrupt generation triggered by the INT_ST1 register, , 0x00C8 */ + unsigned long RESERVED_0xcc[3]; /*!< Reserved Memory Area start from 0xcc to 0xd8*/ + __IO unsigned long INT_FORCE0; /*!< Force interrupts that affect the INT_ST0 register, , 0x00D8 */ + __IO unsigned long INT_FORCE1; /*!< Force interrupts that affect the INT_ST1 register, , 0x00DC */ + unsigned long RESERVED_0xe0[8]; /*!< Reserved Memory Area start from 0xe0 to 0x100*/ + __IO unsigned long VID_SHADOW_CTRL; /*!< Controls DPI shadow register mechanism feature, , 0x0100 */ + unsigned long RESERVED_0x104[2]; /*!< Reserved Memory Area start from 0x104 to 0x10c*/ + __IO unsigned long DPI_VCID_ACT; /*!< Configures the virtual channel id for the DPI traffic, , 0x010C */ +} DSI_TypeDef; + +/********* Register BitField Details: VERSION BASE+0x0000 *********/ +/* There is no BitField Details for VERSION */ + +/********* Register BitField Details: PWR_UP BASE+0x0004 *********/ +#define PWR_UP_SHUTDOWNZ_Pos (0U) +#define PWR_UP_SHUTDOWNZ_Msk (0x1UL << PWR_UP_SHUTDOWNZ_Pos) /*!< 0x00000001 */ +#define PWR_UP_SHUTDOWNZ PWR_UP_SHUTDOWNZ_Msk +#define PWR_UP_SHUTDOWNZ_0 (0x1UL << PWR_UP_SHUTDOWNZ_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: CLKMGR_CFG BASE+0x0008 *********/ +#define CLKMGR_CFG_TO_CLK_DIVISION_Pos (8U) +#define CLKMGR_CFG_TO_CLK_DIVISION_Msk (0xffUL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x0000ff00 */ +#define CLKMGR_CFG_TO_CLK_DIVISION CLKMGR_CFG_TO_CLK_DIVISION_Msk +#define CLKMGR_CFG_TO_CLK_DIVISION_0 (0x1UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00000100 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_1 (0x2UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00000200 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_2 (0x4UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00000400 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_3 (0x8UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00000800 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_4 (0x10UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00001000 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_5 (0x20UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00002000 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_6 (0x40UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00004000 */ +#define CLKMGR_CFG_TO_CLK_DIVISION_7 (0x80UL << CLKMGR_CFG_TO_CLK_DIVISION_Pos) /*!< 0x00008000 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos (0U) +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_Msk (0xffUL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x000000ff */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION CLKMGR_CFG_TX_ESC_CLK_DIVISION_Msk +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_0 (0x1UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000001 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_1 (0x2UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000002 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_2 (0x4UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000004 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_3 (0x8UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000008 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_4 (0x10UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000010 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_5 (0x20UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000020 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_6 (0x40UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000040 */ +#define CLKMGR_CFG_TX_ESC_CLK_DIVISION_7 (0x80UL << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: DPI_VCID BASE+0x000C *********/ +#define DPI_VCID_DPI_VCID_Pos (0U) +#define DPI_VCID_DPI_VCID_Msk (0x3UL << DPI_VCID_DPI_VCID_Pos) /*!< 0x00000003 */ +#define DPI_VCID_DPI_VCID DPI_VCID_DPI_VCID_Msk +#define DPI_VCID_DPI_VCID_0 (0x1UL << DPI_VCID_DPI_VCID_Pos) /*!< 0x00000001 */ +#define DPI_VCID_DPI_VCID_1 (0x2UL << DPI_VCID_DPI_VCID_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DPI_COLOR_CODING BASE+0x0010 *********/ +#define DPI_COLOR_CODING_LOSE18_EN_Pos (8U) +#define DPI_COLOR_CODING_LOSE18_EN_Msk (0x1UL << DPI_COLOR_CODING_LOSE18_EN_Pos) /*!< 0x00000100 */ +#define DPI_COLOR_CODING_LOSE18_EN DPI_COLOR_CODING_LOSE18_EN_Msk +#define DPI_COLOR_CODING_LOSE18_EN_0 (0x1UL << DPI_COLOR_CODING_LOSE18_EN_Pos) /*!< 0x00000100 */ +#define DPI_COLOR_CODING_DPI_COLOR_CODING_Pos (0U) +#define DPI_COLOR_CODING_DPI_COLOR_CODING_Msk (0xfUL << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) /*!< 0x0000000f */ +#define DPI_COLOR_CODING_DPI_COLOR_CODING DPI_COLOR_CODING_DPI_COLOR_CODING_Msk +#define DPI_COLOR_CODING_DPI_COLOR_CODING_0 (0x1UL << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) /*!< 0x00000001 */ +#define DPI_COLOR_CODING_DPI_COLOR_CODING_1 (0x2UL << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) /*!< 0x00000002 */ +#define DPI_COLOR_CODING_DPI_COLOR_CODING_2 (0x4UL << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) /*!< 0x00000004 */ +#define DPI_COLOR_CODING_DPI_COLOR_CODING_3 (0x8UL << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: DPI_CFG_POL BASE+0x0014 *********/ +#define DPI_CFG_POL_COLORM_ACT_Pos (4U) +#define DPI_CFG_POL_COLORM_ACT_Msk (0x1UL << DPI_CFG_POL_COLORM_ACT_Pos) /*!< 0x00000010 */ +#define DPI_CFG_POL_COLORM_ACT DPI_CFG_POL_COLORM_ACT_Msk +#define DPI_CFG_POL_COLORM_ACT_0 (0x1UL << DPI_CFG_POL_COLORM_ACT_Pos) /*!< 0x00000010 */ +#define DPI_CFG_POL_SHUTD_ACT_Pos (3U) +#define DPI_CFG_POL_SHUTD_ACT_Msk (0x1UL << DPI_CFG_POL_SHUTD_ACT_Pos) /*!< 0x00000008 */ +#define DPI_CFG_POL_SHUTD_ACT DPI_CFG_POL_SHUTD_ACT_Msk +#define DPI_CFG_POL_SHUTD_ACT_0 (0x1UL << DPI_CFG_POL_SHUTD_ACT_Pos) /*!< 0x00000008 */ +#define DPI_CFG_POL_HSYNC_ACT_Pos (2U) +#define DPI_CFG_POL_HSYNC_ACT_Msk (0x1UL << DPI_CFG_POL_HSYNC_ACT_Pos) /*!< 0x00000004 */ +#define DPI_CFG_POL_HSYNC_ACT DPI_CFG_POL_HSYNC_ACT_Msk +#define DPI_CFG_POL_HSYNC_ACT_0 (0x1UL << DPI_CFG_POL_HSYNC_ACT_Pos) /*!< 0x00000004 */ +#define DPI_CFG_POL_VSYNC_ACT_Pos (1U) +#define DPI_CFG_POL_VSYNC_ACT_Msk (0x1UL << DPI_CFG_POL_VSYNC_ACT_Pos) /*!< 0x00000002 */ +#define DPI_CFG_POL_VSYNC_ACT DPI_CFG_POL_VSYNC_ACT_Msk +#define DPI_CFG_POL_VSYNC_ACT_0 (0x1UL << DPI_CFG_POL_VSYNC_ACT_Pos) /*!< 0x00000002 */ +#define DPI_CFG_POL_DATAEN_ACT_Pos (0U) +#define DPI_CFG_POL_DATAEN_ACT_Msk (0x1UL << DPI_CFG_POL_DATAEN_ACT_Pos) /*!< 0x00000001 */ +#define DPI_CFG_POL_DATAEN_ACT DPI_CFG_POL_DATAEN_ACT_Msk +#define DPI_CFG_POL_DATAEN_ACT_0 (0x1UL << DPI_CFG_POL_DATAEN_ACT_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DPI_LP_CMD_TIM BASE+0x0018 *********/ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos (16U) +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Msk (0xffUL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00ff0000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Msk +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_0 (0x1UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00010000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_1 (0x2UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00020000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_2 (0x4UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00040000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_3 (0x8UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00080000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_4 (0x10UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00100000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_5 (0x20UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00200000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_6 (0x40UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00400000 */ +#define DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_7 (0x80UL << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) /*!< 0x00800000 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos (0U) +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Msk (0xffUL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x000000ff */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Msk +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_0 (0x1UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000001 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_1 (0x2UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000002 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_2 (0x4UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000004 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_3 (0x8UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000008 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_4 (0x10UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000010 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_5 (0x20UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000020 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_6 (0x40UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000040 */ +#define DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_7 (0x80UL << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: PCKHDL_CFG BASE+0x002C *********/ +#define PCKHDL_CFG_CRC_RX_EN_Pos (4U) +#define PCKHDL_CFG_CRC_RX_EN_Msk (0x1UL << PCKHDL_CFG_CRC_RX_EN_Pos) /*!< 0x00000010 */ +#define PCKHDL_CFG_CRC_RX_EN PCKHDL_CFG_CRC_RX_EN_Msk +#define PCKHDL_CFG_CRC_RX_EN_0 (0x1UL << PCKHDL_CFG_CRC_RX_EN_Pos) /*!< 0x00000010 */ +#define PCKHDL_CFG_ECC_RX_EN_Pos (3U) +#define PCKHDL_CFG_ECC_RX_EN_Msk (0x1UL << PCKHDL_CFG_ECC_RX_EN_Pos) /*!< 0x00000008 */ +#define PCKHDL_CFG_ECC_RX_EN PCKHDL_CFG_ECC_RX_EN_Msk +#define PCKHDL_CFG_ECC_RX_EN_0 (0x1UL << PCKHDL_CFG_ECC_RX_EN_Pos) /*!< 0x00000008 */ +#define PCKHDL_CFG_BTA_EN_Pos (2U) +#define PCKHDL_CFG_BTA_EN_Msk (0x1UL << PCKHDL_CFG_BTA_EN_Pos) /*!< 0x00000004 */ +#define PCKHDL_CFG_BTA_EN PCKHDL_CFG_BTA_EN_Msk +#define PCKHDL_CFG_BTA_EN_0 (0x1UL << PCKHDL_CFG_BTA_EN_Pos) /*!< 0x00000004 */ +#define PCKHDL_CFG_EOTP_RX_EN_Pos (1U) +#define PCKHDL_CFG_EOTP_RX_EN_Msk (0x1UL << PCKHDL_CFG_EOTP_RX_EN_Pos) /*!< 0x00000002 */ +#define PCKHDL_CFG_EOTP_RX_EN PCKHDL_CFG_EOTP_RX_EN_Msk +#define PCKHDL_CFG_EOTP_RX_EN_0 (0x1UL << PCKHDL_CFG_EOTP_RX_EN_Pos) /*!< 0x00000002 */ +#define PCKHDL_CFG_EOTP_TX_EN_Pos (0U) +#define PCKHDL_CFG_EOTP_TX_EN_Msk (0x1UL << PCKHDL_CFG_EOTP_TX_EN_Pos) /*!< 0x00000001 */ +#define PCKHDL_CFG_EOTP_TX_EN PCKHDL_CFG_EOTP_TX_EN_Msk +#define PCKHDL_CFG_EOTP_TX_EN_0 (0x1UL << PCKHDL_CFG_EOTP_TX_EN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: GEN_VCID BASE+0x0030 *********/ +#define GEN_VCID_GEN_VCID_RX_Pos (0U) +#define GEN_VCID_GEN_VCID_RX_Msk (0x3UL << GEN_VCID_GEN_VCID_RX_Pos) /*!< 0x00000003 */ +#define GEN_VCID_GEN_VCID_RX GEN_VCID_GEN_VCID_RX_Msk +#define GEN_VCID_GEN_VCID_RX_0 (0x1UL << GEN_VCID_GEN_VCID_RX_Pos) /*!< 0x00000001 */ +#define GEN_VCID_GEN_VCID_RX_1 (0x2UL << GEN_VCID_GEN_VCID_RX_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: MODE_CFG BASE+0x0034 *********/ +#define MODE_CFG_CMD_VIDEO_MODE_Pos (0U) +#define MODE_CFG_CMD_VIDEO_MODE_Msk (0x1UL << MODE_CFG_CMD_VIDEO_MODE_Pos) /*!< 0x00000001 */ +#define MODE_CFG_CMD_VIDEO_MODE MODE_CFG_CMD_VIDEO_MODE_Msk +#define MODE_CFG_CMD_VIDEO_MODE_0 (0x1UL << MODE_CFG_CMD_VIDEO_MODE_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: VID_MODE_CFG BASE+0x0038 *********/ +#define VID_MODE_CFG_VPG_ORIENTATION_Pos (24U) +#define VID_MODE_CFG_VPG_ORIENTATION_Msk (0x1UL << VID_MODE_CFG_VPG_ORIENTATION_Pos) /*!< 0x01000000 */ +#define VID_MODE_CFG_VPG_ORIENTATION VID_MODE_CFG_VPG_ORIENTATION_Msk +#define VID_MODE_CFG_VPG_ORIENTATION_0 (0x1UL << VID_MODE_CFG_VPG_ORIENTATION_Pos) /*!< 0x01000000 */ +#define VID_MODE_CFG_VPG_MODE_Pos (20U) +#define VID_MODE_CFG_VPG_MODE_Msk (0x1UL << VID_MODE_CFG_VPG_MODE_Pos) /*!< 0x00100000 */ +#define VID_MODE_CFG_VPG_MODE VID_MODE_CFG_VPG_MODE_Msk +#define VID_MODE_CFG_VPG_MODE_0 (0x1UL << VID_MODE_CFG_VPG_MODE_Pos) /*!< 0x00100000 */ +#define VID_MODE_CFG_VPG_EN_Pos (16U) +#define VID_MODE_CFG_VPG_EN_Msk (0x1UL << VID_MODE_CFG_VPG_EN_Pos) /*!< 0x00010000 */ +#define VID_MODE_CFG_VPG_EN VID_MODE_CFG_VPG_EN_Msk +#define VID_MODE_CFG_VPG_EN_0 (0x1UL << VID_MODE_CFG_VPG_EN_Pos) /*!< 0x00010000 */ +#define VID_MODE_CFG_LP_CMD_EN_Pos (15U) +#define VID_MODE_CFG_LP_CMD_EN_Msk (0x1UL << VID_MODE_CFG_LP_CMD_EN_Pos) /*!< 0x00008000 */ +#define VID_MODE_CFG_LP_CMD_EN VID_MODE_CFG_LP_CMD_EN_Msk +#define VID_MODE_CFG_LP_CMD_EN_0 (0x1UL << VID_MODE_CFG_LP_CMD_EN_Pos) /*!< 0x00008000 */ +#define VID_MODE_CFG_FRAME_BTA_ACK_EN_Pos (14U) +#define VID_MODE_CFG_FRAME_BTA_ACK_EN_Msk (0x1UL << VID_MODE_CFG_FRAME_BTA_ACK_EN_Pos) /*!< 0x00004000 */ +#define VID_MODE_CFG_FRAME_BTA_ACK_EN VID_MODE_CFG_FRAME_BTA_ACK_EN_Msk +#define VID_MODE_CFG_FRAME_BTA_ACK_EN_0 (0x1UL << VID_MODE_CFG_FRAME_BTA_ACK_EN_Pos) /*!< 0x00004000 */ +#define VID_MODE_CFG_LP_HFP_EN_Pos (13U) +#define VID_MODE_CFG_LP_HFP_EN_Msk (0x1UL << VID_MODE_CFG_LP_HFP_EN_Pos) /*!< 0x00002000 */ +#define VID_MODE_CFG_LP_HFP_EN VID_MODE_CFG_LP_HFP_EN_Msk +#define VID_MODE_CFG_LP_HFP_EN_0 (0x1UL << VID_MODE_CFG_LP_HFP_EN_Pos) /*!< 0x00002000 */ +#define VID_MODE_CFG_LP_HBP_EN_Pos (12U) +#define VID_MODE_CFG_LP_HBP_EN_Msk (0x1UL << VID_MODE_CFG_LP_HBP_EN_Pos) /*!< 0x00001000 */ +#define VID_MODE_CFG_LP_HBP_EN VID_MODE_CFG_LP_HBP_EN_Msk +#define VID_MODE_CFG_LP_HBP_EN_0 (0x1UL << VID_MODE_CFG_LP_HBP_EN_Pos) /*!< 0x00001000 */ +#define VID_MODE_CFG_LP_VACT_EN_Pos (11U) +#define VID_MODE_CFG_LP_VACT_EN_Msk (0x1UL << VID_MODE_CFG_LP_VACT_EN_Pos) /*!< 0x00000800 */ +#define VID_MODE_CFG_LP_VACT_EN VID_MODE_CFG_LP_VACT_EN_Msk +#define VID_MODE_CFG_LP_VACT_EN_0 (0x1UL << VID_MODE_CFG_LP_VACT_EN_Pos) /*!< 0x00000800 */ +#define VID_MODE_CFG_LP_VFP_EN_Pos (10U) +#define VID_MODE_CFG_LP_VFP_EN_Msk (0x1UL << VID_MODE_CFG_LP_VFP_EN_Pos) /*!< 0x00000400 */ +#define VID_MODE_CFG_LP_VFP_EN VID_MODE_CFG_LP_VFP_EN_Msk +#define VID_MODE_CFG_LP_VFP_EN_0 (0x1UL << VID_MODE_CFG_LP_VFP_EN_Pos) /*!< 0x00000400 */ +#define VID_MODE_CFG_LP_VBP_EN_Pos (9U) +#define VID_MODE_CFG_LP_VBP_EN_Msk (0x1UL << VID_MODE_CFG_LP_VBP_EN_Pos) /*!< 0x00000200 */ +#define VID_MODE_CFG_LP_VBP_EN VID_MODE_CFG_LP_VBP_EN_Msk +#define VID_MODE_CFG_LP_VBP_EN_0 (0x1UL << VID_MODE_CFG_LP_VBP_EN_Pos) /*!< 0x00000200 */ +#define VID_MODE_CFG_LP_VSA_EN_Pos (8U) +#define VID_MODE_CFG_LP_VSA_EN_Msk (0x1UL << VID_MODE_CFG_LP_VSA_EN_Pos) /*!< 0x00000100 */ +#define VID_MODE_CFG_LP_VSA_EN VID_MODE_CFG_LP_VSA_EN_Msk +#define VID_MODE_CFG_LP_VSA_EN_0 (0x1UL << VID_MODE_CFG_LP_VSA_EN_Pos) /*!< 0x00000100 */ +#define VID_MODE_CFG_VID_MODE_TYPE_Pos (0U) +#define VID_MODE_CFG_VID_MODE_TYPE_Msk (0x3UL << VID_MODE_CFG_VID_MODE_TYPE_Pos) /*!< 0x00000003 */ +#define VID_MODE_CFG_VID_MODE_TYPE VID_MODE_CFG_VID_MODE_TYPE_Msk +#define VID_MODE_CFG_VID_MODE_TYPE_0 (0x1UL << VID_MODE_CFG_VID_MODE_TYPE_Pos) /*!< 0x00000001 */ +#define VID_MODE_CFG_VID_MODE_TYPE_1 (0x2UL << VID_MODE_CFG_VID_MODE_TYPE_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: VID_PKT_SIZE BASE+0x003C *********/ +#define VID_PKT_SIZE_VID_PKT_SIZE_Pos (0U) +#define VID_PKT_SIZE_VID_PKT_SIZE_Msk (0x3fffUL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00003fff */ +#define VID_PKT_SIZE_VID_PKT_SIZE VID_PKT_SIZE_VID_PKT_SIZE_Msk +#define VID_PKT_SIZE_VID_PKT_SIZE_0 (0x1UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000001 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_1 (0x2UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000002 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_2 (0x4UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000004 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_3 (0x8UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000008 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_4 (0x10UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000010 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_5 (0x20UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000020 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_6 (0x40UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000040 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_7 (0x80UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000080 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_8 (0x100UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000100 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_9 (0x200UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000200 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_10 (0x400UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000400 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_11 (0x800UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00000800 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_12 (0x1000UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00001000 */ +#define VID_PKT_SIZE_VID_PKT_SIZE_13 (0x2000UL << VID_PKT_SIZE_VID_PKT_SIZE_Pos) /*!< 0x00002000 */ + +/********* Register BitField Details: VID_NUM_CHUNKS BASE+0x0040 *********/ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos (0U) +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_Msk (0x1fffUL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00001fff */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS VID_NUM_CHUNKS_VID_NUM_CHUNKS_Msk +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_0 (0x1UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000001 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_1 (0x2UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000002 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_2 (0x4UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000004 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_3 (0x8UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000008 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_4 (0x10UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000010 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_5 (0x20UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000020 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_6 (0x40UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000040 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_7 (0x80UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000080 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_8 (0x100UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000100 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_9 (0x200UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000200 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_10 (0x400UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000400 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_11 (0x800UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00000800 */ +#define VID_NUM_CHUNKS_VID_NUM_CHUNKS_12 (0x1000UL << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) /*!< 0x00001000 */ + +/********* Register BitField Details: VID_NULL_SIZE BASE+0x0044 *********/ +#define VID_NULL_SIZE_VID_NULL_SIZE_Pos (0U) +#define VID_NULL_SIZE_VID_NULL_SIZE_Msk (0x1fffUL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00001fff */ +#define VID_NULL_SIZE_VID_NULL_SIZE VID_NULL_SIZE_VID_NULL_SIZE_Msk +#define VID_NULL_SIZE_VID_NULL_SIZE_0 (0x1UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000001 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_1 (0x2UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000002 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_2 (0x4UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000004 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_3 (0x8UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000008 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_4 (0x10UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000010 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_5 (0x20UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000020 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_6 (0x40UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000040 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_7 (0x80UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000080 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_8 (0x100UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000100 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_9 (0x200UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000200 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_10 (0x400UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000400 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_11 (0x800UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00000800 */ +#define VID_NULL_SIZE_VID_NULL_SIZE_12 (0x1000UL << VID_NULL_SIZE_VID_NULL_SIZE_Pos) /*!< 0x00001000 */ + +/********* Register BitField Details: VID_HSA_TIME BASE+0x0048 *********/ +#define VID_HSA_TIME_VID_HSA_TIME_Pos (0U) +#define VID_HSA_TIME_VID_HSA_TIME_Msk (0x1fffUL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00001fff */ +#define VID_HSA_TIME_VID_HSA_TIME VID_HSA_TIME_VID_HSA_TIME_Msk +#define VID_HSA_TIME_VID_HSA_TIME_0 (0x1UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000001 */ +#define VID_HSA_TIME_VID_HSA_TIME_1 (0x2UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000002 */ +#define VID_HSA_TIME_VID_HSA_TIME_2 (0x4UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000004 */ +#define VID_HSA_TIME_VID_HSA_TIME_3 (0x8UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000008 */ +#define VID_HSA_TIME_VID_HSA_TIME_4 (0x10UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000010 */ +#define VID_HSA_TIME_VID_HSA_TIME_5 (0x20UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000020 */ +#define VID_HSA_TIME_VID_HSA_TIME_6 (0x40UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000040 */ +#define VID_HSA_TIME_VID_HSA_TIME_7 (0x80UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000080 */ +#define VID_HSA_TIME_VID_HSA_TIME_8 (0x100UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000100 */ +#define VID_HSA_TIME_VID_HSA_TIME_9 (0x200UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000200 */ +#define VID_HSA_TIME_VID_HSA_TIME_10 (0x400UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000400 */ +#define VID_HSA_TIME_VID_HSA_TIME_11 (0x800UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00000800 */ +#define VID_HSA_TIME_VID_HSA_TIME_12 (0x1000UL << VID_HSA_TIME_VID_HSA_TIME_Pos) /*!< 0x00001000 */ + +/********* Register BitField Details: VID_HBP_TIME BASE+0x004C *********/ +#define VID_HBP_TIME_VID_HBP_TIME_Pos (0U) +#define VID_HBP_TIME_VID_HBP_TIME_Msk (0x1fffUL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00001fff */ +#define VID_HBP_TIME_VID_HBP_TIME VID_HBP_TIME_VID_HBP_TIME_Msk +#define VID_HBP_TIME_VID_HBP_TIME_0 (0x1UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000001 */ +#define VID_HBP_TIME_VID_HBP_TIME_1 (0x2UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000002 */ +#define VID_HBP_TIME_VID_HBP_TIME_2 (0x4UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000004 */ +#define VID_HBP_TIME_VID_HBP_TIME_3 (0x8UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000008 */ +#define VID_HBP_TIME_VID_HBP_TIME_4 (0x10UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000010 */ +#define VID_HBP_TIME_VID_HBP_TIME_5 (0x20UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000020 */ +#define VID_HBP_TIME_VID_HBP_TIME_6 (0x40UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000040 */ +#define VID_HBP_TIME_VID_HBP_TIME_7 (0x80UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000080 */ +#define VID_HBP_TIME_VID_HBP_TIME_8 (0x100UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000100 */ +#define VID_HBP_TIME_VID_HBP_TIME_9 (0x200UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000200 */ +#define VID_HBP_TIME_VID_HBP_TIME_10 (0x400UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000400 */ +#define VID_HBP_TIME_VID_HBP_TIME_11 (0x800UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00000800 */ +#define VID_HBP_TIME_VID_HBP_TIME_12 (0x1000UL << VID_HBP_TIME_VID_HBP_TIME_Pos) /*!< 0x00001000 */ + +/********* Register BitField Details: VID_HLINE_TIME BASE+0x0050 *********/ +#define VID_NULL_SIZE_VID_HLINE_TIME_Pos (0U) +#define VID_NULL_SIZE_VID_HLINE_TIME_Msk (0x7fffUL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00007fff */ +#define VID_NULL_SIZE_VID_HLINE_TIME VID_NULL_SIZE_VID_HLINE_TIME_Msk +#define VID_NULL_SIZE_VID_HLINE_TIME_0 (0x1UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000001 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_1 (0x2UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000002 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_2 (0x4UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000004 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_3 (0x8UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000008 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_4 (0x10UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000010 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_5 (0x20UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000020 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_6 (0x40UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000040 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_7 (0x80UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000080 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_8 (0x100UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000100 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_9 (0x200UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000200 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_10 (0x400UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000400 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_11 (0x800UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00000800 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_12 (0x1000UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00001000 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_13 (0x2000UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00002000 */ +#define VID_NULL_SIZE_VID_HLINE_TIME_14 (0x4000UL << VID_NULL_SIZE_VID_HLINE_TIME_Pos) /*!< 0x00004000 */ + +/********* Register BitField Details: VID_VSA_LINES BASE+0x0054 *********/ +#define VID_NULL_SIZE_VSA_LINES_Pos (0U) +#define VID_NULL_SIZE_VSA_LINES_Msk (0x3ffUL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x000003ff */ +#define VID_NULL_SIZE_VSA_LINES VID_NULL_SIZE_VSA_LINES_Msk +#define VID_NULL_SIZE_VSA_LINES_0 (0x1UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000001 */ +#define VID_NULL_SIZE_VSA_LINES_1 (0x2UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000002 */ +#define VID_NULL_SIZE_VSA_LINES_2 (0x4UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000004 */ +#define VID_NULL_SIZE_VSA_LINES_3 (0x8UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000008 */ +#define VID_NULL_SIZE_VSA_LINES_4 (0x10UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000010 */ +#define VID_NULL_SIZE_VSA_LINES_5 (0x20UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000020 */ +#define VID_NULL_SIZE_VSA_LINES_6 (0x40UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000040 */ +#define VID_NULL_SIZE_VSA_LINES_7 (0x80UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000080 */ +#define VID_NULL_SIZE_VSA_LINES_8 (0x100UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000100 */ +#define VID_NULL_SIZE_VSA_LINES_9 (0x200UL << VID_NULL_SIZE_VSA_LINES_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: VID_VBP_LINES BASE+0x0058 *********/ +#define VID_VBP_HLINES_VBP_LINES_Pos (0U) +#define VID_VBP_HLINES_VBP_LINES_Msk (0x3ffUL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x000003ff */ +#define VID_VBP_HLINES_VBP_LINES VID_VBP_HLINES_VBP_LINES_Msk +#define VID_VBP_HLINES_VBP_LINES_0 (0x1UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000001 */ +#define VID_VBP_HLINES_VBP_LINES_1 (0x2UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000002 */ +#define VID_VBP_HLINES_VBP_LINES_2 (0x4UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000004 */ +#define VID_VBP_HLINES_VBP_LINES_3 (0x8UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000008 */ +#define VID_VBP_HLINES_VBP_LINES_4 (0x10UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000010 */ +#define VID_VBP_HLINES_VBP_LINES_5 (0x20UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000020 */ +#define VID_VBP_HLINES_VBP_LINES_6 (0x40UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000040 */ +#define VID_VBP_HLINES_VBP_LINES_7 (0x80UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000080 */ +#define VID_VBP_HLINES_VBP_LINES_8 (0x100UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000100 */ +#define VID_VBP_HLINES_VBP_LINES_9 (0x200UL << VID_VBP_HLINES_VBP_LINES_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: VID_VFP_LINES BASE+0x005C *********/ +#define VID_VFP_LINES_VBP_LINES_Pos (0U) +#define VID_VFP_LINES_VBP_LINES_Msk (0x3ffUL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x000003ff */ +#define VID_VFP_LINES_VBP_LINES VID_VFP_LINES_VBP_LINES_Msk +#define VID_VFP_LINES_VBP_LINES_0 (0x1UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000001 */ +#define VID_VFP_LINES_VBP_LINES_1 (0x2UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000002 */ +#define VID_VFP_LINES_VBP_LINES_2 (0x4UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000004 */ +#define VID_VFP_LINES_VBP_LINES_3 (0x8UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000008 */ +#define VID_VFP_LINES_VBP_LINES_4 (0x10UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000010 */ +#define VID_VFP_LINES_VBP_LINES_5 (0x20UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000020 */ +#define VID_VFP_LINES_VBP_LINES_6 (0x40UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000040 */ +#define VID_VFP_LINES_VBP_LINES_7 (0x80UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000080 */ +#define VID_VFP_LINES_VBP_LINES_8 (0x100UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000100 */ +#define VID_VFP_LINES_VBP_LINES_9 (0x200UL << VID_VFP_LINES_VBP_LINES_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: VID_VACTIVE_LINES BASE+0x0060 *********/ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos (0U) +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_Msk (0x3fffUL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00003fff */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES VID_VACTIVE_LINES_V_ACTIVE_LINES_Msk +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_0 (0x1UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000001 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_1 (0x2UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000002 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_2 (0x4UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000004 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_3 (0x8UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000008 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_4 (0x10UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000010 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_5 (0x20UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000020 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_6 (0x40UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000040 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_7 (0x80UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000080 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_8 (0x100UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000100 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_9 (0x200UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000200 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_10 (0x400UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000400 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_11 (0x800UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00000800 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_12 (0x1000UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00001000 */ +#define VID_VACTIVE_LINES_V_ACTIVE_LINES_13 (0x2000UL << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) /*!< 0x00002000 */ + +/********* Register BitField Details: EDPI_CMD_SIZE BASE+0x0064 *********/ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos (0U) +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Msk (0xffffUL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x0000ffff */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Msk +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_0 (0x1UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000001 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_1 (0x2UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000002 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_2 (0x4UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000004 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_3 (0x8UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000008 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_4 (0x10UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000010 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_5 (0x20UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000020 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_6 (0x40UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000040 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_7 (0x80UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000080 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_8 (0x100UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000100 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_9 (0x200UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000200 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_10 (0x400UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000400 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_11 (0x800UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00000800 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_12 (0x1000UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00001000 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_13 (0x2000UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00002000 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_14 (0x4000UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00004000 */ +#define EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_15 (0x8000UL << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: CMD_MODE_CFG BASE+0x0068 *********/ +#define CMD_MODE_CFG_MAX_RD_PKT_SIZE_Pos (24U) +#define CMD_MODE_CFG_MAX_RD_PKT_SIZE_Msk (0x1UL << CMD_MODE_CFG_MAX_RD_PKT_SIZE_Pos) /*!< 0x01000000 */ +#define CMD_MODE_CFG_MAX_RD_PKT_SIZE CMD_MODE_CFG_MAX_RD_PKT_SIZE_Msk +#define CMD_MODE_CFG_MAX_RD_PKT_SIZE_0 (0x1UL << CMD_MODE_CFG_MAX_RD_PKT_SIZE_Pos) /*!< 0x01000000 */ +#define CMD_MODE_CFG_DCS_LW_TX_Pos (19U) +#define CMD_MODE_CFG_DCS_LW_TX_Msk (0x1UL << CMD_MODE_CFG_DCS_LW_TX_Pos) /*!< 0x00080000 */ +#define CMD_MODE_CFG_DCS_LW_TX CMD_MODE_CFG_DCS_LW_TX_Msk +#define CMD_MODE_CFG_DCS_LW_TX_0 (0x1UL << CMD_MODE_CFG_DCS_LW_TX_Pos) /*!< 0x00080000 */ +#define CMD_MODE_CFG_DCS_SR_0P_TX_Pos (18U) +#define CMD_MODE_CFG_DCS_SR_0P_TX_Msk (0x1UL << CMD_MODE_CFG_DCS_SR_0P_TX_Pos) /*!< 0x00040000 */ +#define CMD_MODE_CFG_DCS_SR_0P_TX CMD_MODE_CFG_DCS_SR_0P_TX_Msk +#define CMD_MODE_CFG_DCS_SR_0P_TX_0 (0x1UL << CMD_MODE_CFG_DCS_SR_0P_TX_Pos) /*!< 0x00040000 */ +#define CMD_MODE_CFG_DCS_SW_1P_TX_Pos (17U) +#define CMD_MODE_CFG_DCS_SW_1P_TX_Msk (0x1UL << CMD_MODE_CFG_DCS_SW_1P_TX_Pos) /*!< 0x00020000 */ +#define CMD_MODE_CFG_DCS_SW_1P_TX CMD_MODE_CFG_DCS_SW_1P_TX_Msk +#define CMD_MODE_CFG_DCS_SW_1P_TX_0 (0x1UL << CMD_MODE_CFG_DCS_SW_1P_TX_Pos) /*!< 0x00020000 */ +#define CMD_MODE_CFG_DCS_SW_0P_TX_Pos (16U) +#define CMD_MODE_CFG_DCS_SW_0P_TX_Msk (0x1UL << CMD_MODE_CFG_DCS_SW_0P_TX_Pos) /*!< 0x00010000 */ +#define CMD_MODE_CFG_DCS_SW_0P_TX CMD_MODE_CFG_DCS_SW_0P_TX_Msk +#define CMD_MODE_CFG_DCS_SW_0P_TX_0 (0x1UL << CMD_MODE_CFG_DCS_SW_0P_TX_Pos) /*!< 0x00010000 */ +#define CMD_MODE_CFG_GEN_LW_TX_Pos (14U) +#define CMD_MODE_CFG_GEN_LW_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_LW_TX_Pos) /*!< 0x00004000 */ +#define CMD_MODE_CFG_GEN_LW_TX CMD_MODE_CFG_GEN_LW_TX_Msk +#define CMD_MODE_CFG_GEN_LW_TX_0 (0x1UL << CMD_MODE_CFG_GEN_LW_TX_Pos) /*!< 0x00004000 */ +#define CMD_MODE_CFG_GEN_SR_2P_TX_Pos (13U) +#define CMD_MODE_CFG_GEN_SR_2P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SR_2P_TX_Pos) /*!< 0x00002000 */ +#define CMD_MODE_CFG_GEN_SR_2P_TX CMD_MODE_CFG_GEN_SR_2P_TX_Msk +#define CMD_MODE_CFG_GEN_SR_2P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SR_2P_TX_Pos) /*!< 0x00002000 */ +#define CMD_MODE_CFG_GEN_SR_1P_TX_Pos (12U) +#define CMD_MODE_CFG_GEN_SR_1P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SR_1P_TX_Pos) /*!< 0x00001000 */ +#define CMD_MODE_CFG_GEN_SR_1P_TX CMD_MODE_CFG_GEN_SR_1P_TX_Msk +#define CMD_MODE_CFG_GEN_SR_1P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SR_1P_TX_Pos) /*!< 0x00001000 */ +#define CMD_MODE_CFG_GEN_SR_0P_TX_Pos (11U) +#define CMD_MODE_CFG_GEN_SR_0P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SR_0P_TX_Pos) /*!< 0x00000800 */ +#define CMD_MODE_CFG_GEN_SR_0P_TX CMD_MODE_CFG_GEN_SR_0P_TX_Msk +#define CMD_MODE_CFG_GEN_SR_0P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SR_0P_TX_Pos) /*!< 0x00000800 */ +#define CMD_MODE_CFG_GEN_SW_2P_TX_Pos (10U) +#define CMD_MODE_CFG_GEN_SW_2P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SW_2P_TX_Pos) /*!< 0x00000400 */ +#define CMD_MODE_CFG_GEN_SW_2P_TX CMD_MODE_CFG_GEN_SW_2P_TX_Msk +#define CMD_MODE_CFG_GEN_SW_2P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SW_2P_TX_Pos) /*!< 0x00000400 */ +#define CMD_MODE_CFG_GEN_SW_1P_TX_Pos (9U) +#define CMD_MODE_CFG_GEN_SW_1P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SW_1P_TX_Pos) /*!< 0x00000200 */ +#define CMD_MODE_CFG_GEN_SW_1P_TX CMD_MODE_CFG_GEN_SW_1P_TX_Msk +#define CMD_MODE_CFG_GEN_SW_1P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SW_1P_TX_Pos) /*!< 0x00000200 */ +#define CMD_MODE_CFG_GEN_SW_0P_TX_Pos (8U) +#define CMD_MODE_CFG_GEN_SW_0P_TX_Msk (0x1UL << CMD_MODE_CFG_GEN_SW_0P_TX_Pos) /*!< 0x00000100 */ +#define CMD_MODE_CFG_GEN_SW_0P_TX CMD_MODE_CFG_GEN_SW_0P_TX_Msk +#define CMD_MODE_CFG_GEN_SW_0P_TX_0 (0x1UL << CMD_MODE_CFG_GEN_SW_0P_TX_Pos) /*!< 0x00000100 */ +#define CMD_MODE_CFG_ACK_RQST_EN_Pos (1U) +#define CMD_MODE_CFG_ACK_RQST_EN_Msk (0x1UL << CMD_MODE_CFG_ACK_RQST_EN_Pos) /*!< 0x00000002 */ +#define CMD_MODE_CFG_ACK_RQST_EN CMD_MODE_CFG_ACK_RQST_EN_Msk +#define CMD_MODE_CFG_ACK_RQST_EN_0 (0x1UL << CMD_MODE_CFG_ACK_RQST_EN_Pos) /*!< 0x00000002 */ +#define CMD_MODE_CFG_TEAR_FX_EN_Pos (0U) +#define CMD_MODE_CFG_TEAR_FX_EN_Msk (0x1UL << CMD_MODE_CFG_TEAR_FX_EN_Pos) /*!< 0x00000001 */ +#define CMD_MODE_CFG_TEAR_FX_EN CMD_MODE_CFG_TEAR_FX_EN_Msk +#define CMD_MODE_CFG_TEAR_FX_EN_0 (0x1UL << CMD_MODE_CFG_TEAR_FX_EN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: GEN_HDR BASE+0x006C *********/ +#define GEN_HDR_GEN_WC_MSBYTE_Pos (16U) +#define GEN_HDR_GEN_WC_MSBYTE_Msk (0xffUL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00ff0000 */ +#define GEN_HDR_GEN_WC_MSBYTE GEN_HDR_GEN_WC_MSBYTE_Msk +#define GEN_HDR_GEN_WC_MSBYTE_0 (0x1UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00010000 */ +#define GEN_HDR_GEN_WC_MSBYTE_1 (0x2UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00020000 */ +#define GEN_HDR_GEN_WC_MSBYTE_2 (0x4UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00040000 */ +#define GEN_HDR_GEN_WC_MSBYTE_3 (0x8UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00080000 */ +#define GEN_HDR_GEN_WC_MSBYTE_4 (0x10UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00100000 */ +#define GEN_HDR_GEN_WC_MSBYTE_5 (0x20UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00200000 */ +#define GEN_HDR_GEN_WC_MSBYTE_6 (0x40UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00400000 */ +#define GEN_HDR_GEN_WC_MSBYTE_7 (0x80UL << GEN_HDR_GEN_WC_MSBYTE_Pos) /*!< 0x00800000 */ +#define GEN_HDR_GEN_WC_LSBYTE_Pos (8U) +#define GEN_HDR_GEN_WC_LSBYTE_Msk (0xffUL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x0000ff00 */ +#define GEN_HDR_GEN_WC_LSBYTE GEN_HDR_GEN_WC_LSBYTE_Msk +#define GEN_HDR_GEN_WC_LSBYTE_0 (0x1UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00000100 */ +#define GEN_HDR_GEN_WC_LSBYTE_1 (0x2UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00000200 */ +#define GEN_HDR_GEN_WC_LSBYTE_2 (0x4UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00000400 */ +#define GEN_HDR_GEN_WC_LSBYTE_3 (0x8UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00000800 */ +#define GEN_HDR_GEN_WC_LSBYTE_4 (0x10UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00001000 */ +#define GEN_HDR_GEN_WC_LSBYTE_5 (0x20UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00002000 */ +#define GEN_HDR_GEN_WC_LSBYTE_6 (0x40UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00004000 */ +#define GEN_HDR_GEN_WC_LSBYTE_7 (0x80UL << GEN_HDR_GEN_WC_LSBYTE_Pos) /*!< 0x00008000 */ +#define GEN_HDR_GEN_VC_Pos (6U) +#define GEN_HDR_GEN_VC_Msk (0x3UL << GEN_HDR_GEN_VC_Pos) /*!< 0x000000c0 */ +#define GEN_HDR_GEN_VC GEN_HDR_GEN_VC_Msk +#define GEN_HDR_GEN_VC_0 (0x1UL << GEN_HDR_GEN_VC_Pos) /*!< 0x00000040 */ +#define GEN_HDR_GEN_VC_1 (0x2UL << GEN_HDR_GEN_VC_Pos) /*!< 0x00000080 */ +#define GEN_HDR_GEN_DT_Pos (0U) +#define GEN_HDR_GEN_DT_Msk (0x3fUL << GEN_HDR_GEN_DT_Pos) /*!< 0x0000003f */ +#define GEN_HDR_GEN_DT GEN_HDR_GEN_DT_Msk +#define GEN_HDR_GEN_DT_0 (0x1UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000001 */ +#define GEN_HDR_GEN_DT_1 (0x2UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000002 */ +#define GEN_HDR_GEN_DT_2 (0x4UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000004 */ +#define GEN_HDR_GEN_DT_3 (0x8UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000008 */ +#define GEN_HDR_GEN_DT_4 (0x10UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000010 */ +#define GEN_HDR_GEN_DT_5 (0x20UL << GEN_HDR_GEN_DT_Pos) /*!< 0x00000020 */ + +/********* Register BitField Details: GEN_PLD_DATA BASE+0x0070 *********/ +#define GEN_PLD_DATA_GEN_PLD_B4_Pos (24U) +#define GEN_PLD_DATA_GEN_PLD_B4_Msk (0xffUL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0xff000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4 GEN_PLD_DATA_GEN_PLD_B4_Msk +#define GEN_PLD_DATA_GEN_PLD_B4_0 (0x1UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x01000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_1 (0x2UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x02000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_2 (0x4UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x04000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_3 (0x8UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x08000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_4 (0x10UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x10000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_5 (0x20UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x20000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_6 (0x40UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x40000000 */ +#define GEN_PLD_DATA_GEN_PLD_B4_7 (0x80UL << GEN_PLD_DATA_GEN_PLD_B4_Pos) /*!< 0x80000000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_Pos (16U) +#define GEN_PLD_DATA_GEN_PLD_B3_Msk (0xffUL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00ff0000 */ +#define GEN_PLD_DATA_GEN_PLD_B3 GEN_PLD_DATA_GEN_PLD_B3_Msk +#define GEN_PLD_DATA_GEN_PLD_B3_0 (0x1UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00010000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_1 (0x2UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00020000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_2 (0x4UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00040000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_3 (0x8UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00080000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_4 (0x10UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00100000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_5 (0x20UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00200000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_6 (0x40UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00400000 */ +#define GEN_PLD_DATA_GEN_PLD_B3_7 (0x80UL << GEN_PLD_DATA_GEN_PLD_B3_Pos) /*!< 0x00800000 */ +#define GEN_PLD_DATA_GEN_PLD_B2_Pos (8U) +#define GEN_PLD_DATA_GEN_PLD_B2_Msk (0xffUL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x0000ff00 */ +#define GEN_PLD_DATA_GEN_PLD_B2 GEN_PLD_DATA_GEN_PLD_B2_Msk +#define GEN_PLD_DATA_GEN_PLD_B2_0 (0x1UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00000100 */ +#define GEN_PLD_DATA_GEN_PLD_B2_1 (0x2UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00000200 */ +#define GEN_PLD_DATA_GEN_PLD_B2_2 (0x4UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00000400 */ +#define GEN_PLD_DATA_GEN_PLD_B2_3 (0x8UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00000800 */ +#define GEN_PLD_DATA_GEN_PLD_B2_4 (0x10UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00001000 */ +#define GEN_PLD_DATA_GEN_PLD_B2_5 (0x20UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00002000 */ +#define GEN_PLD_DATA_GEN_PLD_B2_6 (0x40UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00004000 */ +#define GEN_PLD_DATA_GEN_PLD_B2_7 (0x80UL << GEN_PLD_DATA_GEN_PLD_B2_Pos) /*!< 0x00008000 */ +#define GEN_PLD_DATA_GEN_PLD_B1_Pos (0U) +#define GEN_PLD_DATA_GEN_PLD_B1_Msk (0xffUL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x000000ff */ +#define GEN_PLD_DATA_GEN_PLD_B1 GEN_PLD_DATA_GEN_PLD_B1_Msk +#define GEN_PLD_DATA_GEN_PLD_B1_0 (0x1UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000001 */ +#define GEN_PLD_DATA_GEN_PLD_B1_1 (0x2UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000002 */ +#define GEN_PLD_DATA_GEN_PLD_B1_2 (0x4UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000004 */ +#define GEN_PLD_DATA_GEN_PLD_B1_3 (0x8UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000008 */ +#define GEN_PLD_DATA_GEN_PLD_B1_4 (0x10UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000010 */ +#define GEN_PLD_DATA_GEN_PLD_B1_5 (0x20UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000020 */ +#define GEN_PLD_DATA_GEN_PLD_B1_6 (0x40UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000040 */ +#define GEN_PLD_DATA_GEN_PLD_B1_7 (0x80UL << GEN_PLD_DATA_GEN_PLD_B1_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: CMD_PKT_STATUS BASE+0x0074 *********/ +#define CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Pos (6U) +#define CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Msk (0x1UL << CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Pos) /*!< 0x00000040 */ +#define CMD_PKT_STATUS_GEN_RD_CMD_BUSY CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Msk +#define CMD_PKT_STATUS_GEN_RD_CMD_BUSY_0 (0x1UL << CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Pos) /*!< 0x00000040 */ +#define CMD_PKT_STATUS_GEN_PLD_R_FULL_Pos (5U) +#define CMD_PKT_STATUS_GEN_PLD_R_FULL_Msk (0x1UL << CMD_PKT_STATUS_GEN_PLD_R_FULL_Pos) /*!< 0x00000020 */ +#define CMD_PKT_STATUS_GEN_PLD_R_FULL CMD_PKT_STATUS_GEN_PLD_R_FULL_Msk +#define CMD_PKT_STATUS_GEN_PLD_R_FULL_0 (0x1UL << CMD_PKT_STATUS_GEN_PLD_R_FULL_Pos) /*!< 0x00000020 */ +#define CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Pos (4U) +#define CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Msk (0x1UL << CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Pos) /*!< 0x00000010 */ +#define CMD_PKT_STATUS_GEN_PLD_R_EMPTY CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Msk +#define CMD_PKT_STATUS_GEN_PLD_R_EMPTY_0 (0x1UL << CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Pos) /*!< 0x00000010 */ +#define CMD_PKT_STATUS_GEN_PLD_W_FULL_Pos (3U) +#define CMD_PKT_STATUS_GEN_PLD_W_FULL_Msk (0x1UL << CMD_PKT_STATUS_GEN_PLD_W_FULL_Pos) /*!< 0x00000008 */ +#define CMD_PKT_STATUS_GEN_PLD_W_FULL CMD_PKT_STATUS_GEN_PLD_W_FULL_Msk +#define CMD_PKT_STATUS_GEN_PLD_W_FULL_0 (0x1UL << CMD_PKT_STATUS_GEN_PLD_W_FULL_Pos) /*!< 0x00000008 */ +#define CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Pos (2U) +#define CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Msk (0x1UL << CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Pos) /*!< 0x00000004 */ +#define CMD_PKT_STATUS_GEN_PLD_W_EMPTY CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Msk +#define CMD_PKT_STATUS_GEN_PLD_W_EMPTY_0 (0x1UL << CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Pos) /*!< 0x00000004 */ +#define CMD_PKT_STATUS_GEN_CMD_FULL_Pos (1U) +#define CMD_PKT_STATUS_GEN_CMD_FULL_Msk (0x1UL << CMD_PKT_STATUS_GEN_CMD_FULL_Pos) /*!< 0x00000002 */ +#define CMD_PKT_STATUS_GEN_CMD_FULL CMD_PKT_STATUS_GEN_CMD_FULL_Msk +#define CMD_PKT_STATUS_GEN_CMD_FULL_0 (0x1UL << CMD_PKT_STATUS_GEN_CMD_FULL_Pos) /*!< 0x00000002 */ +#define CMD_PKT_STATUS_GEN_CMD_EMPTY_Pos (0U) +#define CMD_PKT_STATUS_GEN_CMD_EMPTY_Msk (0x1UL << CMD_PKT_STATUS_GEN_CMD_EMPTY_Pos) /*!< 0x00000001 */ +#define CMD_PKT_STATUS_GEN_CMD_EMPTY CMD_PKT_STATUS_GEN_CMD_EMPTY_Msk +#define CMD_PKT_STATUS_GEN_CMD_EMPTY_0 (0x1UL << CMD_PKT_STATUS_GEN_CMD_EMPTY_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: TO_CNT_CFG BASE+0x0078 *********/ +#define TO_CNT_CFG_HSTX_TO_CNT_Pos (16U) +#define TO_CNT_CFG_HSTX_TO_CNT_Msk (0xffffUL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0xffff0000 */ +#define TO_CNT_CFG_HSTX_TO_CNT TO_CNT_CFG_HSTX_TO_CNT_Msk +#define TO_CNT_CFG_HSTX_TO_CNT_0 (0x1UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00010000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_1 (0x2UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00020000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_2 (0x4UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00040000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_3 (0x8UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00080000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_4 (0x10UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00100000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_5 (0x20UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00200000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_6 (0x40UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00400000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_7 (0x80UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x00800000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_8 (0x100UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x01000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_9 (0x200UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x02000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_10 (0x400UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x04000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_11 (0x800UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x08000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_12 (0x1000UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x10000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_13 (0x2000UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x20000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_14 (0x4000UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x40000000 */ +#define TO_CNT_CFG_HSTX_TO_CNT_15 (0x8000UL << TO_CNT_CFG_HSTX_TO_CNT_Pos) /*!< 0x80000000 */ +#define TO_CNT_CFG_LPRX_TO_CNT_Pos (0U) +#define TO_CNT_CFG_LPRX_TO_CNT_Msk (0xffffUL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x0000ffff */ +#define TO_CNT_CFG_LPRX_TO_CNT TO_CNT_CFG_LPRX_TO_CNT_Msk +#define TO_CNT_CFG_LPRX_TO_CNT_0 (0x1UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000001 */ +#define TO_CNT_CFG_LPRX_TO_CNT_1 (0x2UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000002 */ +#define TO_CNT_CFG_LPRX_TO_CNT_2 (0x4UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000004 */ +#define TO_CNT_CFG_LPRX_TO_CNT_3 (0x8UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000008 */ +#define TO_CNT_CFG_LPRX_TO_CNT_4 (0x10UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000010 */ +#define TO_CNT_CFG_LPRX_TO_CNT_5 (0x20UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000020 */ +#define TO_CNT_CFG_LPRX_TO_CNT_6 (0x40UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000040 */ +#define TO_CNT_CFG_LPRX_TO_CNT_7 (0x80UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000080 */ +#define TO_CNT_CFG_LPRX_TO_CNT_8 (0x100UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000100 */ +#define TO_CNT_CFG_LPRX_TO_CNT_9 (0x200UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000200 */ +#define TO_CNT_CFG_LPRX_TO_CNT_10 (0x400UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000400 */ +#define TO_CNT_CFG_LPRX_TO_CNT_11 (0x800UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00000800 */ +#define TO_CNT_CFG_LPRX_TO_CNT_12 (0x1000UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00001000 */ +#define TO_CNT_CFG_LPRX_TO_CNT_13 (0x2000UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00002000 */ +#define TO_CNT_CFG_LPRX_TO_CNT_14 (0x4000UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00004000 */ +#define TO_CNT_CFG_LPRX_TO_CNT_15 (0x8000UL << TO_CNT_CFG_LPRX_TO_CNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: HS_RD_TO_CNT BASE+0x007C *********/ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_Pos (0U) +#define HS_RD_TO_CNT_HS_RD_TO_CNT_Msk (0xffffUL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x0000ffff */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT HS_RD_TO_CNT_HS_RD_TO_CNT_Msk +#define HS_RD_TO_CNT_HS_RD_TO_CNT_0 (0x1UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000001 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_1 (0x2UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000002 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_2 (0x4UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000004 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_3 (0x8UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000008 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_4 (0x10UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000010 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_5 (0x20UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000020 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_6 (0x40UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000040 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_7 (0x80UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000080 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_8 (0x100UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000100 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_9 (0x200UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000200 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_10 (0x400UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000400 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_11 (0x800UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00000800 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_12 (0x1000UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00001000 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_13 (0x2000UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00002000 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_14 (0x4000UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00004000 */ +#define HS_RD_TO_CNT_HS_RD_TO_CNT_15 (0x8000UL << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: LP_RD_TO_CNT BASE+0x0080 *********/ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_Pos (0U) +#define LP_RD_TO_CNT_LP_RD_TO_CNT_Msk (0xffffUL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x0000ffff */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT LP_RD_TO_CNT_LP_RD_TO_CNT_Msk +#define LP_RD_TO_CNT_LP_RD_TO_CNT_0 (0x1UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000001 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_1 (0x2UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000002 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_2 (0x4UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000004 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_3 (0x8UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000008 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_4 (0x10UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000010 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_5 (0x20UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000020 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_6 (0x40UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000040 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_7 (0x80UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000080 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_8 (0x100UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000100 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_9 (0x200UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000200 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_10 (0x400UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000400 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_11 (0x800UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00000800 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_12 (0x1000UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00001000 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_13 (0x2000UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00002000 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_14 (0x4000UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00004000 */ +#define LP_RD_TO_CNT_LP_RD_TO_CNT_15 (0x8000UL << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: HS_WR_TO_CNT BASE+0x0084 *********/ +#define HS_WR_TO_CNT_PRESP_TO_MODE_Pos (24U) +#define HS_WR_TO_CNT_PRESP_TO_MODE_Msk (0x1UL << HS_WR_TO_CNT_PRESP_TO_MODE_Pos) /*!< 0x01000000 */ +#define HS_WR_TO_CNT_PRESP_TO_MODE HS_WR_TO_CNT_PRESP_TO_MODE_Msk +#define HS_WR_TO_CNT_PRESP_TO_MODE_0 (0x1UL << HS_WR_TO_CNT_PRESP_TO_MODE_Pos) /*!< 0x01000000 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_Pos (0U) +#define HS_WR_TO_CNT_HS_WR_TO_CNT_Msk (0xffffUL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x0000ffff */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT HS_WR_TO_CNT_HS_WR_TO_CNT_Msk +#define HS_WR_TO_CNT_HS_WR_TO_CNT_0 (0x1UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000001 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_1 (0x2UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000002 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_2 (0x4UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000004 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_3 (0x8UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000008 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_4 (0x10UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000010 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_5 (0x20UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000020 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_6 (0x40UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000040 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_7 (0x80UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000080 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_8 (0x100UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000100 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_9 (0x200UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000200 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_10 (0x400UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000400 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_11 (0x800UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00000800 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_12 (0x1000UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00001000 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_13 (0x2000UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00002000 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_14 (0x4000UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00004000 */ +#define HS_WR_TO_CNT_HS_WR_TO_CNT_15 (0x8000UL << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: BTA_TO_CNT BASE+0x008C *********/ +#define BTA_TO_CNT_BTA_TO_CNT_Pos (0U) +#define BTA_TO_CNT_BTA_TO_CNT_Msk (0xffffUL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x0000ffff */ +#define BTA_TO_CNT_BTA_TO_CNT BTA_TO_CNT_BTA_TO_CNT_Msk +#define BTA_TO_CNT_BTA_TO_CNT_0 (0x1UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000001 */ +#define BTA_TO_CNT_BTA_TO_CNT_1 (0x2UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000002 */ +#define BTA_TO_CNT_BTA_TO_CNT_2 (0x4UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000004 */ +#define BTA_TO_CNT_BTA_TO_CNT_3 (0x8UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000008 */ +#define BTA_TO_CNT_BTA_TO_CNT_4 (0x10UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000010 */ +#define BTA_TO_CNT_BTA_TO_CNT_5 (0x20UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000020 */ +#define BTA_TO_CNT_BTA_TO_CNT_6 (0x40UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000040 */ +#define BTA_TO_CNT_BTA_TO_CNT_7 (0x80UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000080 */ +#define BTA_TO_CNT_BTA_TO_CNT_8 (0x100UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000100 */ +#define BTA_TO_CNT_BTA_TO_CNT_9 (0x200UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000200 */ +#define BTA_TO_CNT_BTA_TO_CNT_10 (0x400UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000400 */ +#define BTA_TO_CNT_BTA_TO_CNT_11 (0x800UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00000800 */ +#define BTA_TO_CNT_BTA_TO_CNT_12 (0x1000UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00001000 */ +#define BTA_TO_CNT_BTA_TO_CNT_13 (0x2000UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00002000 */ +#define BTA_TO_CNT_BTA_TO_CNT_14 (0x4000UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00004000 */ +#define BTA_TO_CNT_BTA_TO_CNT_15 (0x8000UL << BTA_TO_CNT_BTA_TO_CNT_Pos) /*!< 0x00008000 */ + +/********* Register BitField Details: SOF_3D BASE+0x0090 *********/ +#define SOF_3D_SEND_3D_CFG_Pos (16U) +#define SOF_3D_SEND_3D_CFG_Msk (0x1UL << SOF_3D_SEND_3D_CFG_Pos) /*!< 0x00010000 */ +#define SOF_3D_SEND_3D_CFG SOF_3D_SEND_3D_CFG_Msk +#define SOF_3D_SEND_3D_CFG_0 (0x1UL << SOF_3D_SEND_3D_CFG_Pos) /*!< 0x00010000 */ +#define SOF_3D_RIGHT_FIRST_Pos (5U) +#define SOF_3D_RIGHT_FIRST_Msk (0x1UL << SOF_3D_RIGHT_FIRST_Pos) /*!< 0x00000020 */ +#define SOF_3D_RIGHT_FIRST SOF_3D_RIGHT_FIRST_Msk +#define SOF_3D_RIGHT_FIRST_0 (0x1UL << SOF_3D_RIGHT_FIRST_Pos) /*!< 0x00000020 */ +#define SOF_3D_SECOND_VSYNC_Pos (4U) +#define SOF_3D_SECOND_VSYNC_Msk (0x1UL << SOF_3D_SECOND_VSYNC_Pos) /*!< 0x00000010 */ +#define SOF_3D_SECOND_VSYNC SOF_3D_SECOND_VSYNC_Msk +#define SOF_3D_SECOND_VSYNC_0 (0x1UL << SOF_3D_SECOND_VSYNC_Pos) /*!< 0x00000010 */ +#define SOF_3D_FORMAT_3D_Pos (2U) +#define SOF_3D_FORMAT_3D_Msk (0x3UL << SOF_3D_FORMAT_3D_Pos) /*!< 0x0000000c */ +#define SOF_3D_FORMAT_3D SOF_3D_FORMAT_3D_Msk +#define SOF_3D_FORMAT_3D_0 (0x1UL << SOF_3D_FORMAT_3D_Pos) /*!< 0x00000004 */ +#define SOF_3D_FORMAT_3D_1 (0x2UL << SOF_3D_FORMAT_3D_Pos) /*!< 0x00000008 */ +#define SOF_3D_MODE_3D_Pos (0U) +#define SOF_3D_MODE_3D_Msk (0x3UL << SOF_3D_MODE_3D_Pos) /*!< 0x00000003 */ +#define SOF_3D_MODE_3D SOF_3D_MODE_3D_Msk +#define SOF_3D_MODE_3D_0 (0x1UL << SOF_3D_MODE_3D_Pos) /*!< 0x00000001 */ +#define SOF_3D_MODE_3D_1 (0x2UL << SOF_3D_MODE_3D_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: HS_WR_TO_CNT BASE+0x0094 *********/ +#define HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_Pos (1U) +#define HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_Msk (0x1UL << HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_Pos) /*!< 0x00000002 */ +#define HS_WR_TO_CNT_AUTO_CLKLANE_CTRL HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_Msk +#define HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_0 (0x1UL << HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_Pos) /*!< 0x00000002 */ +#define HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_Pos (0U) +#define HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_Msk (0x1UL << HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_Pos) /*!< 0x00000001 */ +#define HS_WR_TO_CNT_PHY_TXREQUESTCLKHS HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_Msk +#define HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_0 (0x1UL << HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: PHY_TMR_LPCLK_CFG BASE+0x0098 *********/ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos (16U) +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Msk (0x3ffUL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x03ff0000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Msk +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_0 (0x1UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00010000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_1 (0x2UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00020000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_2 (0x4UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00040000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_3 (0x8UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00080000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_4 (0x10UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00100000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_5 (0x20UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00200000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_6 (0x40UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00400000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_7 (0x80UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x00800000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_8 (0x100UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x01000000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_9 (0x200UL << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) /*!< 0x02000000 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos (0U) +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Msk (0x3ffUL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x000003ff */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Msk +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_0 (0x1UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000001 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_1 (0x2UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000002 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_2 (0x4UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000004 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_3 (0x8UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000008 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_4 (0x10UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000010 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_5 (0x20UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000020 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_6 (0x40UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000040 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_7 (0x80UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000080 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_8 (0x100UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000100 */ +#define PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_9 (0x200UL << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) /*!< 0x00000200 */ + +/********* Register BitField Details: PHY_TMR_CFG BASE+0x009C *********/ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_Pos (24U) +#define PHY_TMR_CFG_PHY_HS2LP_TIME_Msk (0xffUL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0xff000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME PHY_TMR_CFG_PHY_HS2LP_TIME_Msk +#define PHY_TMR_CFG_PHY_HS2LP_TIME_0 (0x1UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x01000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_1 (0x2UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x02000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_2 (0x4UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x04000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_3 (0x8UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x08000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_4 (0x10UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x10000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_5 (0x20UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x20000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_6 (0x40UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x40000000 */ +#define PHY_TMR_CFG_PHY_HS2LP_TIME_7 (0x80UL << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) /*!< 0x80000000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_Pos (16U) +#define PHY_TMR_CFG_PHY_LP2HS_TIME_Msk (0xffUL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00ff0000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME PHY_TMR_CFG_PHY_LP2HS_TIME_Msk +#define PHY_TMR_CFG_PHY_LP2HS_TIME_0 (0x1UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00010000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_1 (0x2UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00020000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_2 (0x4UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00040000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_3 (0x8UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00080000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_4 (0x10UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00100000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_5 (0x20UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00200000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_6 (0x40UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00400000 */ +#define PHY_TMR_CFG_PHY_LP2HS_TIME_7 (0x80UL << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) /*!< 0x00800000 */ +#define PHY_TMR_CFG_MAX_RD_TIME_Pos (0U) +#define PHY_TMR_CFG_MAX_RD_TIME_Msk (0x7fffUL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00007fff */ +#define PHY_TMR_CFG_MAX_RD_TIME PHY_TMR_CFG_MAX_RD_TIME_Msk +#define PHY_TMR_CFG_MAX_RD_TIME_0 (0x1UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000001 */ +#define PHY_TMR_CFG_MAX_RD_TIME_1 (0x2UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000002 */ +#define PHY_TMR_CFG_MAX_RD_TIME_2 (0x4UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000004 */ +#define PHY_TMR_CFG_MAX_RD_TIME_3 (0x8UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000008 */ +#define PHY_TMR_CFG_MAX_RD_TIME_4 (0x10UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000010 */ +#define PHY_TMR_CFG_MAX_RD_TIME_5 (0x20UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000020 */ +#define PHY_TMR_CFG_MAX_RD_TIME_6 (0x40UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000040 */ +#define PHY_TMR_CFG_MAX_RD_TIME_7 (0x80UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000080 */ +#define PHY_TMR_CFG_MAX_RD_TIME_8 (0x100UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000100 */ +#define PHY_TMR_CFG_MAX_RD_TIME_9 (0x200UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000200 */ +#define PHY_TMR_CFG_MAX_RD_TIME_10 (0x400UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000400 */ +#define PHY_TMR_CFG_MAX_RD_TIME_11 (0x800UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00000800 */ +#define PHY_TMR_CFG_MAX_RD_TIME_12 (0x1000UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00001000 */ +#define PHY_TMR_CFG_MAX_RD_TIME_13 (0x2000UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00002000 */ +#define PHY_TMR_CFG_MAX_RD_TIME_14 (0x4000UL << PHY_TMR_CFG_MAX_RD_TIME_Pos) /*!< 0x00004000 */ + +/********* Register BitField Details: PHY_RSTZ BASE+0x00A0 *********/ +#define PHY_RSTZ_PHY_FORCEPLL_Pos (3U) +#define PHY_RSTZ_PHY_FORCEPLL_Msk (0x1UL << PHY_RSTZ_PHY_FORCEPLL_Pos) /*!< 0x00000008 */ +#define PHY_RSTZ_PHY_FORCEPLL PHY_RSTZ_PHY_FORCEPLL_Msk +#define PHY_RSTZ_PHY_FORCEPLL_0 (0x1UL << PHY_RSTZ_PHY_FORCEPLL_Pos) /*!< 0x00000008 */ +#define PHY_RSTZ_PHY_ENABLECLK_Pos (2U) +#define PHY_RSTZ_PHY_ENABLECLK_Msk (0x1UL << PHY_RSTZ_PHY_ENABLECLK_Pos) /*!< 0x00000004 */ +#define PHY_RSTZ_PHY_ENABLECLK PHY_RSTZ_PHY_ENABLECLK_Msk +#define PHY_RSTZ_PHY_ENABLECLK_0 (0x1UL << PHY_RSTZ_PHY_ENABLECLK_Pos) /*!< 0x00000004 */ +#define PHY_RSTZ_PHY_RSTZ_Pos (1U) +#define PHY_RSTZ_PHY_RSTZ_Msk (0x1UL << PHY_RSTZ_PHY_RSTZ_Pos) /*!< 0x00000002 */ +#define PHY_RSTZ_PHY_RSTZ PHY_RSTZ_PHY_RSTZ_Msk +#define PHY_RSTZ_PHY_RSTZ_0 (0x1UL << PHY_RSTZ_PHY_RSTZ_Pos) /*!< 0x00000002 */ +#define PHY_RSTZ_PHY_SHUTDOWNZ_Pos (0U) +#define PHY_RSTZ_PHY_SHUTDOWNZ_Msk (0x1UL << PHY_RSTZ_PHY_SHUTDOWNZ_Pos) /*!< 0x00000001 */ +#define PHY_RSTZ_PHY_SHUTDOWNZ PHY_RSTZ_PHY_SHUTDOWNZ_Msk +#define PHY_RSTZ_PHY_SHUTDOWNZ_0 (0x1UL << PHY_RSTZ_PHY_SHUTDOWNZ_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: PHY_IF_CFG BASE+0x00A4 *********/ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos (8U) +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_Msk (0xffUL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x0000ff00 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME PHY_IF_CFG_PHY_STOP_WAIT_TIME_Msk +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_0 (0x1UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00000100 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_1 (0x2UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00000200 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_2 (0x4UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00000400 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_3 (0x8UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00000800 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_4 (0x10UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00001000 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_5 (0x20UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00002000 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_6 (0x40UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00004000 */ +#define PHY_IF_CFG_PHY_STOP_WAIT_TIME_7 (0x80UL << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) /*!< 0x00008000 */ +#define PHY_IF_CFG_N_LANES_Pos (0U) +#define PHY_IF_CFG_N_LANES_Msk (0x3UL << PHY_IF_CFG_N_LANES_Pos) /*!< 0x00000003 */ +#define PHY_IF_CFG_N_LANES PHY_IF_CFG_N_LANES_Msk +#define PHY_IF_CFG_N_LANES_0 (0x1UL << PHY_IF_CFG_N_LANES_Pos) /*!< 0x00000001 */ +#define PHY_IF_CFG_N_LANES_1 (0x2UL << PHY_IF_CFG_N_LANES_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: PHY_ULPS_CTRL BASE+0x00A8 *********/ +#define PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Pos (3U) +#define PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Msk (0x1UL << PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Pos) /*!< 0x00000008 */ +#define PHY_ULPS_CTRL_PHY_TXEXITULPSLAN PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Msk +#define PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_0 (0x1UL << PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Pos) /*!< 0x00000008 */ +#define PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Pos (2U) +#define PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Msk (0x1UL << PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Pos) /*!< 0x00000004 */ +#define PHY_ULPS_CTRL_PHY_TXREQULPSLAN PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Msk +#define PHY_ULPS_CTRL_PHY_TXREQULPSLAN_0 (0x1UL << PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Pos) /*!< 0x00000004 */ +#define PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Pos (1U) +#define PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Msk (0x1UL << PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Pos) /*!< 0x00000002 */ +#define PHY_ULPS_CTRL_PHY_TXEXITULPSCLK PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Msk +#define PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_0 (0x1UL << PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Pos) /*!< 0x00000002 */ +#define PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Pos (0U) +#define PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Msk (0x1UL << PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Pos) /*!< 0x00000001 */ +#define PHY_ULPS_CTRL_PHY_TXREQULPSCLK PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Msk +#define PHY_ULPS_CTRL_PHY_TXREQULPSCLK_0 (0x1UL << PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: PHY_TX_TRIGGERS BASE+0x00AC *********/ +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos (0U) +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Msk (0xfUL << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) /*!< 0x0000000f */ +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Msk +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_0 (0x1UL << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) /*!< 0x00000001 */ +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_1 (0x2UL << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) /*!< 0x00000002 */ +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_2 (0x4UL << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) /*!< 0x00000004 */ +#define PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_3 (0x8UL << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: PHY_STATUS BASE+0x00B0 *********/ +#define PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Pos (8U) +#define PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Msk (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Pos) /*!< 0x00000100 */ +#define PHY_STATUS_PHY_ULPSACTIVENOT1LANE PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Msk +#define PHY_STATUS_PHY_ULPSACTIVENOT1LANE_0 (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Pos) /*!< 0x00000100 */ +#define PHY_STATUS_PHY_STOPSTATE1LANE_Pos (7U) +#define PHY_STATUS_PHY_STOPSTATE1LANE_Msk (0x1UL << PHY_STATUS_PHY_STOPSTATE1LANE_Pos) /*!< 0x00000080 */ +#define PHY_STATUS_PHY_STOPSTATE1LANE PHY_STATUS_PHY_STOPSTATE1LANE_Msk +#define PHY_STATUS_PHY_STOPSTATE1LANE_0 (0x1UL << PHY_STATUS_PHY_STOPSTATE1LANE_Pos) /*!< 0x00000080 */ +#define PHY_STATUS_PHY_RXULPSESC0LANE_Pos (6U) +#define PHY_STATUS_PHY_RXULPSESC0LANE_Msk (0x1UL << PHY_STATUS_PHY_RXULPSESC0LANE_Pos) /*!< 0x00000040 */ +#define PHY_STATUS_PHY_RXULPSESC0LANE PHY_STATUS_PHY_RXULPSESC0LANE_Msk +#define PHY_STATUS_PHY_RXULPSESC0LANE_0 (0x1UL << PHY_STATUS_PHY_RXULPSESC0LANE_Pos) /*!< 0x00000040 */ +#define PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Pos (5U) +#define PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Msk (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Pos) /*!< 0x00000020 */ +#define PHY_STATUS_PHY_ULPSACTIVENOT0LANE PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Msk +#define PHY_STATUS_PHY_ULPSACTIVENOT0LANE_0 (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Pos) /*!< 0x00000020 */ +#define PHY_STATUS_PHY_STOPSTATE0LANE_Pos (4U) +#define PHY_STATUS_PHY_STOPSTATE0LANE_Msk (0x1UL << PHY_STATUS_PHY_STOPSTATE0LANE_Pos) /*!< 0x00000010 */ +#define PHY_STATUS_PHY_STOPSTATE0LANE PHY_STATUS_PHY_STOPSTATE0LANE_Msk +#define PHY_STATUS_PHY_STOPSTATE0LANE_0 (0x1UL << PHY_STATUS_PHY_STOPSTATE0LANE_Pos) /*!< 0x00000010 */ +#define PHY_STATUS_PHY_ULPSACTIVENOTCLK_Pos (3U) +#define PHY_STATUS_PHY_ULPSACTIVENOTCLK_Msk (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOTCLK_Pos) /*!< 0x00000008 */ +#define PHY_STATUS_PHY_ULPSACTIVENOTCLK PHY_STATUS_PHY_ULPSACTIVENOTCLK_Msk +#define PHY_STATUS_PHY_ULPSACTIVENOTCLK_0 (0x1UL << PHY_STATUS_PHY_ULPSACTIVENOTCLK_Pos) /*!< 0x00000008 */ +#define PHY_STATUS_PHY_STOPSTATECLKLANE_Pos (2U) +#define PHY_STATUS_PHY_STOPSTATECLKLANE_Msk (0x1UL << PHY_STATUS_PHY_STOPSTATECLKLANE_Pos) /*!< 0x00000004 */ +#define PHY_STATUS_PHY_STOPSTATECLKLANE PHY_STATUS_PHY_STOPSTATECLKLANE_Msk +#define PHY_STATUS_PHY_STOPSTATECLKLANE_0 (0x1UL << PHY_STATUS_PHY_STOPSTATECLKLANE_Pos) /*!< 0x00000004 */ +#define PHY_STATUS_PHY_DIRECTION_Pos (1U) +#define PHY_STATUS_PHY_DIRECTION_Msk (0x1UL << PHY_STATUS_PHY_DIRECTION_Pos) /*!< 0x00000002 */ +#define PHY_STATUS_PHY_DIRECTION PHY_STATUS_PHY_DIRECTION_Msk +#define PHY_STATUS_PHY_DIRECTION_0 (0x1UL << PHY_STATUS_PHY_DIRECTION_Pos) /*!< 0x00000002 */ +#define PHY_STATUS_PHY_LOCK_Pos (0U) +#define PHY_STATUS_PHY_LOCK_Msk (0x1UL << PHY_STATUS_PHY_LOCK_Pos) /*!< 0x00000001 */ +#define PHY_STATUS_PHY_LOCK PHY_STATUS_PHY_LOCK_Msk +#define PHY_STATUS_PHY_LOCK_0 (0x1UL << PHY_STATUS_PHY_LOCK_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: PHY_TST_CTRL0 BASE+0x00B4 *********/ +#define PHY_TST_CTRL0_PHY_TESTCLK_Pos (1U) +#define PHY_TST_CTRL0_PHY_TESTCLK_Msk (0x1UL << PHY_TST_CTRL0_PHY_TESTCLK_Pos) /*!< 0x00000002 */ +#define PHY_TST_CTRL0_PHY_TESTCLK PHY_TST_CTRL0_PHY_TESTCLK_Msk +#define PHY_TST_CTRL0_PHY_TESTCLK_0 (0x1UL << PHY_TST_CTRL0_PHY_TESTCLK_Pos) /*!< 0x00000002 */ +#define PHY_TST_CTRL0_PHY_TESTCLR_Pos (0U) +#define PHY_TST_CTRL0_PHY_TESTCLR_Msk (0x1UL << PHY_TST_CTRL0_PHY_TESTCLR_Pos) /*!< 0x00000001 */ +#define PHY_TST_CTRL0_PHY_TESTCLR PHY_TST_CTRL0_PHY_TESTCLR_Msk +#define PHY_TST_CTRL0_PHY_TESTCLR_0 (0x1UL << PHY_TST_CTRL0_PHY_TESTCLR_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: PHY_TST_CTRL1 BASE+0x00B8 *********/ +#define PHY_TST_CTRL1_PHY_TESTEN_Pos (16U) +#define PHY_TST_CTRL1_PHY_TESTEN_Msk (0x1UL << PHY_TST_CTRL1_PHY_TESTEN_Pos) /*!< 0x00010000 */ +#define PHY_TST_CTRL1_PHY_TESTEN PHY_TST_CTRL1_PHY_TESTEN_Msk +#define PHY_TST_CTRL1_PHY_TESTEN_0 (0x1UL << PHY_TST_CTRL1_PHY_TESTEN_Pos) /*!< 0x00010000 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_Pos (8U) +#define PHY_TST_CTRL1_PHY_TESTDOUT_Msk (0xffUL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x0000ff00 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT PHY_TST_CTRL1_PHY_TESTDOUT_Msk +#define PHY_TST_CTRL1_PHY_TESTDOUT_0 (0x1UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00000100 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_1 (0x2UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00000200 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_2 (0x4UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00000400 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_3 (0x8UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00000800 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_4 (0x10UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00001000 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_5 (0x20UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00002000 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_6 (0x40UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00004000 */ +#define PHY_TST_CTRL1_PHY_TESTDOUT_7 (0x80UL << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) /*!< 0x00008000 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_Pos (0U) +#define PHY_TST_CTRL1_PHY_TESTDIN_Msk (0xffUL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x000000ff */ +#define PHY_TST_CTRL1_PHY_TESTDIN PHY_TST_CTRL1_PHY_TESTDIN_Msk +#define PHY_TST_CTRL1_PHY_TESTDIN_0 (0x1UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000001 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_1 (0x2UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000002 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_2 (0x4UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000004 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_3 (0x8UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000008 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_4 (0x10UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000010 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_5 (0x20UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000020 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_6 (0x40UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000040 */ +#define PHY_TST_CTRL1_PHY_TESTDIN_7 (0x80UL << PHY_TST_CTRL1_PHY_TESTDIN_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: INT_ST0 BASE+0x00BC *********/ +#define INT_ST0_DPHY_ERRORS_4_Pos (20U) +#define INT_ST0_DPHY_ERRORS_4_Msk (0x1UL << INT_ST0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_ST0_DPHY_ERRORS_4 INT_ST0_DPHY_ERRORS_4_Msk +#define INT_ST0_DPHY_ERRORS_4_0 (0x1UL << INT_ST0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_ST0_DPHY_ERRORS_3_Pos (19U) +#define INT_ST0_DPHY_ERRORS_3_Msk (0x1UL << INT_ST0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_ST0_DPHY_ERRORS_3 INT_ST0_DPHY_ERRORS_3_Msk +#define INT_ST0_DPHY_ERRORS_3_0 (0x1UL << INT_ST0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_ST0_DPHY_ERRORS_2_Pos (18U) +#define INT_ST0_DPHY_ERRORS_2_Msk (0x1UL << INT_ST0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_ST0_DPHY_ERRORS_2 INT_ST0_DPHY_ERRORS_2_Msk +#define INT_ST0_DPHY_ERRORS_2_0 (0x1UL << INT_ST0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_ST0_DPHY_ERRORS_1_Pos (17U) +#define INT_ST0_DPHY_ERRORS_1_Msk (0x1UL << INT_ST0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_ST0_DPHY_ERRORS_1 INT_ST0_DPHY_ERRORS_1_Msk +#define INT_ST0_DPHY_ERRORS_1_0 (0x1UL << INT_ST0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_ST0_DPHY_ERRORS_0_Pos (16U) +#define INT_ST0_DPHY_ERRORS_0_Msk (0x1UL << INT_ST0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_ST0_DPHY_ERRORS_0 INT_ST0_DPHY_ERRORS_0_Msk +#define INT_ST0_DPHY_ERRORS_0_0 (0x1UL << INT_ST0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_ST0_ACK_WITH_ERR_15_Pos (15U) +#define INT_ST0_ACK_WITH_ERR_15_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_ST0_ACK_WITH_ERR_15 INT_ST0_ACK_WITH_ERR_15_Msk +#define INT_ST0_ACK_WITH_ERR_15_0 (0x1UL << INT_ST0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_ST0_ACK_WITH_ERR_14_Pos (14U) +#define INT_ST0_ACK_WITH_ERR_14_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_ST0_ACK_WITH_ERR_14 INT_ST0_ACK_WITH_ERR_14_Msk +#define INT_ST0_ACK_WITH_ERR_14_0 (0x1UL << INT_ST0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_ST0_ACK_WITH_ERR_13_Pos (13U) +#define INT_ST0_ACK_WITH_ERR_13_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_ST0_ACK_WITH_ERR_13 INT_ST0_ACK_WITH_ERR_13_Msk +#define INT_ST0_ACK_WITH_ERR_13_0 (0x1UL << INT_ST0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_ST0_ACK_WITH_ERR_12_Pos (12U) +#define INT_ST0_ACK_WITH_ERR_12_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_ST0_ACK_WITH_ERR_12 INT_ST0_ACK_WITH_ERR_12_Msk +#define INT_ST0_ACK_WITH_ERR_12_0 (0x1UL << INT_ST0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_ST0_ACK_WITH_ERR_11_Pos (11U) +#define INT_ST0_ACK_WITH_ERR_11_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_ST0_ACK_WITH_ERR_11 INT_ST0_ACK_WITH_ERR_11_Msk +#define INT_ST0_ACK_WITH_ERR_11_0 (0x1UL << INT_ST0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_ST0_ACK_WITH_ERR_10_Pos (10U) +#define INT_ST0_ACK_WITH_ERR_10_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_ST0_ACK_WITH_ERR_10 INT_ST0_ACK_WITH_ERR_10_Msk +#define INT_ST0_ACK_WITH_ERR_10_0 (0x1UL << INT_ST0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_ST0_ACK_WITH_ERR_9_Pos (9U) +#define INT_ST0_ACK_WITH_ERR_9_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_ST0_ACK_WITH_ERR_9 INT_ST0_ACK_WITH_ERR_9_Msk +#define INT_ST0_ACK_WITH_ERR_9_0 (0x1UL << INT_ST0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_ST0_ACK_WITH_ERR_8_Pos (8U) +#define INT_ST0_ACK_WITH_ERR_8_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_ST0_ACK_WITH_ERR_8 INT_ST0_ACK_WITH_ERR_8_Msk +#define INT_ST0_ACK_WITH_ERR_8_0 (0x1UL << INT_ST0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_ST0_ACK_WITH_ERR_7_Pos (7U) +#define INT_ST0_ACK_WITH_ERR_7_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_ST0_ACK_WITH_ERR_7 INT_ST0_ACK_WITH_ERR_7_Msk +#define INT_ST0_ACK_WITH_ERR_7_0 (0x1UL << INT_ST0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_ST0_ACK_WITH_ERR_6_Pos (6U) +#define INT_ST0_ACK_WITH_ERR_6_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_ST0_ACK_WITH_ERR_6 INT_ST0_ACK_WITH_ERR_6_Msk +#define INT_ST0_ACK_WITH_ERR_6_0 (0x1UL << INT_ST0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_ST0_ACK_WITH_ERR_5_Pos (5U) +#define INT_ST0_ACK_WITH_ERR_5_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_ST0_ACK_WITH_ERR_5 INT_ST0_ACK_WITH_ERR_5_Msk +#define INT_ST0_ACK_WITH_ERR_5_0 (0x1UL << INT_ST0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_ST0_ACK_WITH_ERR_4_Pos (4U) +#define INT_ST0_ACK_WITH_ERR_4_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_ST0_ACK_WITH_ERR_4 INT_ST0_ACK_WITH_ERR_4_Msk +#define INT_ST0_ACK_WITH_ERR_4_0 (0x1UL << INT_ST0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_ST0_ACK_WITH_ERR_3_Pos (3U) +#define INT_ST0_ACK_WITH_ERR_3_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_ST0_ACK_WITH_ERR_3 INT_ST0_ACK_WITH_ERR_3_Msk +#define INT_ST0_ACK_WITH_ERR_3_0 (0x1UL << INT_ST0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_ST0_ACK_WITH_ERR_2_Pos (2U) +#define INT_ST0_ACK_WITH_ERR_2_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_ST0_ACK_WITH_ERR_2 INT_ST0_ACK_WITH_ERR_2_Msk +#define INT_ST0_ACK_WITH_ERR_2_0 (0x1UL << INT_ST0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_ST0_ACK_WITH_ERR_1_Pos (1U) +#define INT_ST0_ACK_WITH_ERR_1_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_ST0_ACK_WITH_ERR_1 INT_ST0_ACK_WITH_ERR_1_Msk +#define INT_ST0_ACK_WITH_ERR_1_0 (0x1UL << INT_ST0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_ST0_ACK_WITH_ERR_0_Pos (0U) +#define INT_ST0_ACK_WITH_ERR_0_Msk (0x1UL << INT_ST0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ +#define INT_ST0_ACK_WITH_ERR_0 INT_ST0_ACK_WITH_ERR_0_Msk +#define INT_ST0_ACK_WITH_ERR_0_0 (0x1UL << INT_ST0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: INT_ST1 BASE+0x00C0 *********/ +#define INT_ST1_GEN_PLD_RECEV_ERR_Pos (12U) +#define INT_ST1_GEN_PLD_RECEV_ERR_Msk (0x1UL << INT_ST1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_ST1_GEN_PLD_RECEV_ERR INT_ST1_GEN_PLD_RECEV_ERR_Msk +#define INT_ST1_GEN_PLD_RECEV_ERR_0 (0x1UL << INT_ST1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_ST1_GEN_PLD_RD_ERR_Pos (11U) +#define INT_ST1_GEN_PLD_RD_ERR_Msk (0x1UL << INT_ST1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_ST1_GEN_PLD_RD_ERR INT_ST1_GEN_PLD_RD_ERR_Msk +#define INT_ST1_GEN_PLD_RD_ERR_0 (0x1UL << INT_ST1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_ST1_GEN_PLD_SEND_ERR_Pos (10U) +#define INT_ST1_GEN_PLD_SEND_ERR_Msk (0x1UL << INT_ST1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_ST1_GEN_PLD_SEND_ERR INT_ST1_GEN_PLD_SEND_ERR_Msk +#define INT_ST1_GEN_PLD_SEND_ERR_0 (0x1UL << INT_ST1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_ST1_GEN_PLD_WR_ERR_Pos (9U) +#define INT_ST1_GEN_PLD_WR_ERR_Msk (0x1UL << INT_ST1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_ST1_GEN_PLD_WR_ERR INT_ST1_GEN_PLD_WR_ERR_Msk +#define INT_ST1_GEN_PLD_WR_ERR_0 (0x1UL << INT_ST1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_ST1_GEN_CMD_WR_ERR_Pos (8U) +#define INT_ST1_GEN_CMD_WR_ERR_Msk (0x1UL << INT_ST1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_ST1_GEN_CMD_WR_ERR INT_ST1_GEN_CMD_WR_ERR_Msk +#define INT_ST1_GEN_CMD_WR_ERR_0 (0x1UL << INT_ST1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_ST1_DPI_PLD_WR_ERR_Pos (7U) +#define INT_ST1_DPI_PLD_WR_ERR_Msk (0x1UL << INT_ST1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_ST1_DPI_PLD_WR_ERR INT_ST1_DPI_PLD_WR_ERR_Msk +#define INT_ST1_DPI_PLD_WR_ERR_0 (0x1UL << INT_ST1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_ST1_EOTP_ERR_Pos (6U) +#define INT_ST1_EOTP_ERR_Msk (0x1UL << INT_ST1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_ST1_EOTP_ERR INT_ST1_EOTP_ERR_Msk +#define INT_ST1_EOTP_ERR_0 (0x1UL << INT_ST1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_ST1_PKT_SIZE_ERR_Pos (5U) +#define INT_ST1_PKT_SIZE_ERR_Msk (0x1UL << INT_ST1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_ST1_PKT_SIZE_ERR INT_ST1_PKT_SIZE_ERR_Msk +#define INT_ST1_PKT_SIZE_ERR_0 (0x1UL << INT_ST1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_ST1_CRC_ERR_Pos (4U) +#define INT_ST1_CRC_ERR_Msk (0x1UL << INT_ST1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_ST1_CRC_ERR INT_ST1_CRC_ERR_Msk +#define INT_ST1_CRC_ERR_0 (0x1UL << INT_ST1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_ST1_ECC_MULTI_ERR_Pos (3U) +#define INT_ST1_ECC_MULTI_ERR_Msk (0x1UL << INT_ST1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_ST1_ECC_MULTI_ERR INT_ST1_ECC_MULTI_ERR_Msk +#define INT_ST1_ECC_MULTI_ERR_0 (0x1UL << INT_ST1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_ST1_ECC_SINGLE_ERR_Pos (2U) +#define INT_ST1_ECC_SINGLE_ERR_Msk (0x1UL << INT_ST1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_ST1_ECC_SINGLE_ERR INT_ST1_ECC_SINGLE_ERR_Msk +#define INT_ST1_ECC_SINGLE_ERR_0 (0x1UL << INT_ST1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_ST1_TO_LP_RX_Pos (1U) +#define INT_ST1_TO_LP_RX_Msk (0x1UL << INT_ST1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_ST1_TO_LP_RX INT_ST1_TO_LP_RX_Msk +#define INT_ST1_TO_LP_RX_0 (0x1UL << INT_ST1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_ST1_TO_HS_TX_Pos (0U) +#define INT_ST1_TO_HS_TX_Msk (0x1UL << INT_ST1_TO_HS_TX_Pos) /*!< 0x00000001 */ +#define INT_ST1_TO_HS_TX INT_ST1_TO_HS_TX_Msk +#define INT_ST1_TO_HS_TX_0 (0x1UL << INT_ST1_TO_HS_TX_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: INT_MSK0 BASE+0x00C4 *********/ +#define INT_MSK0_DPHY_ERRORS_4_Pos (20U) +#define INT_MSK0_DPHY_ERRORS_4_Msk (0x1UL << INT_MSK0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_MSK0_DPHY_ERRORS_4 INT_MSK0_DPHY_ERRORS_4_Msk +#define INT_MSK0_DPHY_ERRORS_4_0 (0x1UL << INT_MSK0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_MSK0_DPHY_ERRORS_3_Pos (19U) +#define INT_MSK0_DPHY_ERRORS_3_Msk (0x1UL << INT_MSK0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_MSK0_DPHY_ERRORS_3 INT_MSK0_DPHY_ERRORS_3_Msk +#define INT_MSK0_DPHY_ERRORS_3_0 (0x1UL << INT_MSK0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_MSK0_DPHY_ERRORS_2_Pos (18U) +#define INT_MSK0_DPHY_ERRORS_2_Msk (0x1UL << INT_MSK0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_MSK0_DPHY_ERRORS_2 INT_MSK0_DPHY_ERRORS_2_Msk +#define INT_MSK0_DPHY_ERRORS_2_0 (0x1UL << INT_MSK0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_MSK0_DPHY_ERRORS_1_Pos (17U) +#define INT_MSK0_DPHY_ERRORS_1_Msk (0x1UL << INT_MSK0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_MSK0_DPHY_ERRORS_1 INT_MSK0_DPHY_ERRORS_1_Msk +#define INT_MSK0_DPHY_ERRORS_1_0 (0x1UL << INT_MSK0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_MSK0_DPHY_ERRORS_0_Pos (16U) +#define INT_MSK0_DPHY_ERRORS_0_Msk (0x1UL << INT_MSK0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_MSK0_DPHY_ERRORS_0 INT_MSK0_DPHY_ERRORS_0_Msk +#define INT_MSK0_DPHY_ERRORS_0_0 (0x1UL << INT_MSK0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_MSK0_ACK_WITH_ERR_15_Pos (15U) +#define INT_MSK0_ACK_WITH_ERR_15_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_MSK0_ACK_WITH_ERR_15 INT_MSK0_ACK_WITH_ERR_15_Msk +#define INT_MSK0_ACK_WITH_ERR_15_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_MSK0_ACK_WITH_ERR_14_Pos (14U) +#define INT_MSK0_ACK_WITH_ERR_14_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_MSK0_ACK_WITH_ERR_14 INT_MSK0_ACK_WITH_ERR_14_Msk +#define INT_MSK0_ACK_WITH_ERR_14_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_MSK0_ACK_WITH_ERR_13_Pos (13U) +#define INT_MSK0_ACK_WITH_ERR_13_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_MSK0_ACK_WITH_ERR_13 INT_MSK0_ACK_WITH_ERR_13_Msk +#define INT_MSK0_ACK_WITH_ERR_13_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_MSK0_ACK_WITH_ERR_12_Pos (12U) +#define INT_MSK0_ACK_WITH_ERR_12_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_MSK0_ACK_WITH_ERR_12 INT_MSK0_ACK_WITH_ERR_12_Msk +#define INT_MSK0_ACK_WITH_ERR_12_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_MSK0_ACK_WITH_ERR_11_Pos (11U) +#define INT_MSK0_ACK_WITH_ERR_11_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_MSK0_ACK_WITH_ERR_11 INT_MSK0_ACK_WITH_ERR_11_Msk +#define INT_MSK0_ACK_WITH_ERR_11_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_MSK0_ACK_WITH_ERR_10_Pos (10U) +#define INT_MSK0_ACK_WITH_ERR_10_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_MSK0_ACK_WITH_ERR_10 INT_MSK0_ACK_WITH_ERR_10_Msk +#define INT_MSK0_ACK_WITH_ERR_10_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_MSK0_ACK_WITH_ERR_9_Pos (9U) +#define INT_MSK0_ACK_WITH_ERR_9_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_MSK0_ACK_WITH_ERR_9 INT_MSK0_ACK_WITH_ERR_9_Msk +#define INT_MSK0_ACK_WITH_ERR_9_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_MSK0_ACK_WITH_ERR_8_Pos (8U) +#define INT_MSK0_ACK_WITH_ERR_8_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_MSK0_ACK_WITH_ERR_8 INT_MSK0_ACK_WITH_ERR_8_Msk +#define INT_MSK0_ACK_WITH_ERR_8_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_MSK0_ACK_WITH_ERR_7_Pos (7U) +#define INT_MSK0_ACK_WITH_ERR_7_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_MSK0_ACK_WITH_ERR_7 INT_MSK0_ACK_WITH_ERR_7_Msk +#define INT_MSK0_ACK_WITH_ERR_7_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_MSK0_ACK_WITH_ERR_6_Pos (6U) +#define INT_MSK0_ACK_WITH_ERR_6_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_MSK0_ACK_WITH_ERR_6 INT_MSK0_ACK_WITH_ERR_6_Msk +#define INT_MSK0_ACK_WITH_ERR_6_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_MSK0_ACK_WITH_ERR_5_Pos (5U) +#define INT_MSK0_ACK_WITH_ERR_5_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_MSK0_ACK_WITH_ERR_5 INT_MSK0_ACK_WITH_ERR_5_Msk +#define INT_MSK0_ACK_WITH_ERR_5_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_MSK0_ACK_WITH_ERR_4_Pos (4U) +#define INT_MSK0_ACK_WITH_ERR_4_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_MSK0_ACK_WITH_ERR_4 INT_MSK0_ACK_WITH_ERR_4_Msk +#define INT_MSK0_ACK_WITH_ERR_4_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_MSK0_ACK_WITH_ERR_3_Pos (3U) +#define INT_MSK0_ACK_WITH_ERR_3_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_MSK0_ACK_WITH_ERR_3 INT_MSK0_ACK_WITH_ERR_3_Msk +#define INT_MSK0_ACK_WITH_ERR_3_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_MSK0_ACK_WITH_ERR_2_Pos (2U) +#define INT_MSK0_ACK_WITH_ERR_2_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_MSK0_ACK_WITH_ERR_2 INT_MSK0_ACK_WITH_ERR_2_Msk +#define INT_MSK0_ACK_WITH_ERR_2_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_MSK0_ACK_WITH_ERR_1_Pos (1U) +#define INT_MSK0_ACK_WITH_ERR_1_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_MSK0_ACK_WITH_ERR_1 INT_MSK0_ACK_WITH_ERR_1_Msk +#define INT_MSK0_ACK_WITH_ERR_1_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_MSK0_ACK_WITH_ERR_0_Pos (0U) +#define INT_MSK0_ACK_WITH_ERR_0_Msk (0x1UL << INT_MSK0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ +#define INT_MSK0_ACK_WITH_ERR_0 INT_MSK0_ACK_WITH_ERR_0_Msk +#define INT_MSK0_ACK_WITH_ERR_0_0 (0x1UL << INT_MSK0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: INT_MSK1 BASE+0x00C8 *********/ +#define INT_MSK1_GEN_PLD_RECEV_ERR_Pos (12U) +#define INT_MSK1_GEN_PLD_RECEV_ERR_Msk (0x1UL << INT_MSK1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_MSK1_GEN_PLD_RECEV_ERR INT_MSK1_GEN_PLD_RECEV_ERR_Msk +#define INT_MSK1_GEN_PLD_RECEV_ERR_0 (0x1UL << INT_MSK1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_MSK1_GEN_PLD_RD_ERR_Pos (11U) +#define INT_MSK1_GEN_PLD_RD_ERR_Msk (0x1UL << INT_MSK1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_MSK1_GEN_PLD_RD_ERR INT_MSK1_GEN_PLD_RD_ERR_Msk +#define INT_MSK1_GEN_PLD_RD_ERR_0 (0x1UL << INT_MSK1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_MSK1_GEN_PLD_SEND_ERR_Pos (10U) +#define INT_MSK1_GEN_PLD_SEND_ERR_Msk (0x1UL << INT_MSK1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_MSK1_GEN_PLD_SEND_ERR INT_MSK1_GEN_PLD_SEND_ERR_Msk +#define INT_MSK1_GEN_PLD_SEND_ERR_0 (0x1UL << INT_MSK1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_MSK1_GEN_PLD_WR_ERR_Pos (9U) +#define INT_MSK1_GEN_PLD_WR_ERR_Msk (0x1UL << INT_MSK1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_MSK1_GEN_PLD_WR_ERR INT_MSK1_GEN_PLD_WR_ERR_Msk +#define INT_MSK1_GEN_PLD_WR_ERR_0 (0x1UL << INT_MSK1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_MSK1_GEN_CMD_WR_ERR_Pos (8U) +#define INT_MSK1_GEN_CMD_WR_ERR_Msk (0x1UL << INT_MSK1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_MSK1_GEN_CMD_WR_ERR INT_MSK1_GEN_CMD_WR_ERR_Msk +#define INT_MSK1_GEN_CMD_WR_ERR_0 (0x1UL << INT_MSK1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_MSK1_DPI_PLD_WR_ERR_Pos (7U) +#define INT_MSK1_DPI_PLD_WR_ERR_Msk (0x1UL << INT_MSK1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_MSK1_DPI_PLD_WR_ERR INT_MSK1_DPI_PLD_WR_ERR_Msk +#define INT_MSK1_DPI_PLD_WR_ERR_0 (0x1UL << INT_MSK1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_MSK1_EOTP_ERR_Pos (6U) +#define INT_MSK1_EOTP_ERR_Msk (0x1UL << INT_MSK1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_MSK1_EOTP_ERR INT_MSK1_EOTP_ERR_Msk +#define INT_MSK1_EOTP_ERR_0 (0x1UL << INT_MSK1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_MSK1_PKT_SIZE_ERR_Pos (5U) +#define INT_MSK1_PKT_SIZE_ERR_Msk (0x1UL << INT_MSK1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_MSK1_PKT_SIZE_ERR INT_MSK1_PKT_SIZE_ERR_Msk +#define INT_MSK1_PKT_SIZE_ERR_0 (0x1UL << INT_MSK1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_MSK1_CRC_ERR_Pos (4U) +#define INT_MSK1_CRC_ERR_Msk (0x1UL << INT_MSK1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_MSK1_CRC_ERR INT_MSK1_CRC_ERR_Msk +#define INT_MSK1_CRC_ERR_0 (0x1UL << INT_MSK1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_MSK1_ECC_MULTI_ERR_Pos (3U) +#define INT_MSK1_ECC_MULTI_ERR_Msk (0x1UL << INT_MSK1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_MSK1_ECC_MULTI_ERR INT_MSK1_ECC_MULTI_ERR_Msk +#define INT_MSK1_ECC_MULTI_ERR_0 (0x1UL << INT_MSK1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_MSK1_ECC_SINGLE_ERR_Pos (2U) +#define INT_MSK1_ECC_SINGLE_ERR_Msk (0x1UL << INT_MSK1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_MSK1_ECC_SINGLE_ERR INT_MSK1_ECC_SINGLE_ERR_Msk +#define INT_MSK1_ECC_SINGLE_ERR_0 (0x1UL << INT_MSK1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_MSK1_TO_LP_RX_Pos (1U) +#define INT_MSK1_TO_LP_RX_Msk (0x1UL << INT_MSK1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_MSK1_TO_LP_RX INT_MSK1_TO_LP_RX_Msk +#define INT_MSK1_TO_LP_RX_0 (0x1UL << INT_MSK1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_MSK1_TO_HS_TX_Pos (0U) +#define INT_MSK1_TO_HS_TX_Msk (0x1UL << INT_MSK1_TO_HS_TX_Pos) /*!< 0x00000001 */ +#define INT_MSK1_TO_HS_TX INT_MSK1_TO_HS_TX_Msk +#define INT_MSK1_TO_HS_TX_0 (0x1UL << INT_MSK1_TO_HS_TX_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: INT_FORCE0 BASE+0x00D8 *********/ +#define INT_FORCE0_DPHY_ERRORS_4_Pos (20U) +#define INT_FORCE0_DPHY_ERRORS_4_Msk (0x1UL << INT_FORCE0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_FORCE0_DPHY_ERRORS_4 INT_FORCE0_DPHY_ERRORS_4_Msk +#define INT_FORCE0_DPHY_ERRORS_4_0 (0x1UL << INT_FORCE0_DPHY_ERRORS_4_Pos) /*!< 0x00100000 */ +#define INT_FORCE0_DPHY_ERRORS_3_Pos (19U) +#define INT_FORCE0_DPHY_ERRORS_3_Msk (0x1UL << INT_FORCE0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_FORCE0_DPHY_ERRORS_3 INT_FORCE0_DPHY_ERRORS_3_Msk +#define INT_FORCE0_DPHY_ERRORS_3_0 (0x1UL << INT_FORCE0_DPHY_ERRORS_3_Pos) /*!< 0x00080000 */ +#define INT_FORCE0_DPHY_ERRORS_2_Pos (18U) +#define INT_FORCE0_DPHY_ERRORS_2_Msk (0x1UL << INT_FORCE0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_FORCE0_DPHY_ERRORS_2 INT_FORCE0_DPHY_ERRORS_2_Msk +#define INT_FORCE0_DPHY_ERRORS_2_0 (0x1UL << INT_FORCE0_DPHY_ERRORS_2_Pos) /*!< 0x00040000 */ +#define INT_FORCE0_DPHY_ERRORS_1_Pos (17U) +#define INT_FORCE0_DPHY_ERRORS_1_Msk (0x1UL << INT_FORCE0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_FORCE0_DPHY_ERRORS_1 INT_FORCE0_DPHY_ERRORS_1_Msk +#define INT_FORCE0_DPHY_ERRORS_1_0 (0x1UL << INT_FORCE0_DPHY_ERRORS_1_Pos) /*!< 0x00020000 */ +#define INT_FORCE0_DPHY_ERRORS_0_Pos (16U) +#define INT_FORCE0_DPHY_ERRORS_0_Msk (0x1UL << INT_FORCE0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_FORCE0_DPHY_ERRORS_0 INT_FORCE0_DPHY_ERRORS_0_Msk +#define INT_FORCE0_DPHY_ERRORS_0_0 (0x1UL << INT_FORCE0_DPHY_ERRORS_0_Pos) /*!< 0x00010000 */ +#define INT_FORCE0_ACK_WITH_ERR_15_Pos (15U) +#define INT_FORCE0_ACK_WITH_ERR_15_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_FORCE0_ACK_WITH_ERR_15 INT_FORCE0_ACK_WITH_ERR_15_Msk +#define INT_FORCE0_ACK_WITH_ERR_15_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_15_Pos) /*!< 0x00008000 */ +#define INT_FORCE0_ACK_WITH_ERR_14_Pos (14U) +#define INT_FORCE0_ACK_WITH_ERR_14_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_FORCE0_ACK_WITH_ERR_14 INT_FORCE0_ACK_WITH_ERR_14_Msk +#define INT_FORCE0_ACK_WITH_ERR_14_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_14_Pos) /*!< 0x00004000 */ +#define INT_FORCE0_ACK_WITH_ERR_13_Pos (13U) +#define INT_FORCE0_ACK_WITH_ERR_13_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_FORCE0_ACK_WITH_ERR_13 INT_FORCE0_ACK_WITH_ERR_13_Msk +#define INT_FORCE0_ACK_WITH_ERR_13_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_13_Pos) /*!< 0x00002000 */ +#define INT_FORCE0_ACK_WITH_ERR_12_Pos (12U) +#define INT_FORCE0_ACK_WITH_ERR_12_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_FORCE0_ACK_WITH_ERR_12 INT_FORCE0_ACK_WITH_ERR_12_Msk +#define INT_FORCE0_ACK_WITH_ERR_12_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_12_Pos) /*!< 0x00001000 */ +#define INT_FORCE0_ACK_WITH_ERR_11_Pos (11U) +#define INT_FORCE0_ACK_WITH_ERR_11_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_FORCE0_ACK_WITH_ERR_11 INT_FORCE0_ACK_WITH_ERR_11_Msk +#define INT_FORCE0_ACK_WITH_ERR_11_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_11_Pos) /*!< 0x00000800 */ +#define INT_FORCE0_ACK_WITH_ERR_10_Pos (10U) +#define INT_FORCE0_ACK_WITH_ERR_10_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_FORCE0_ACK_WITH_ERR_10 INT_FORCE0_ACK_WITH_ERR_10_Msk +#define INT_FORCE0_ACK_WITH_ERR_10_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_10_Pos) /*!< 0x00000400 */ +#define INT_FORCE0_ACK_WITH_ERR_9_Pos (9U) +#define INT_FORCE0_ACK_WITH_ERR_9_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_FORCE0_ACK_WITH_ERR_9 INT_FORCE0_ACK_WITH_ERR_9_Msk +#define INT_FORCE0_ACK_WITH_ERR_9_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_9_Pos) /*!< 0x00000200 */ +#define INT_FORCE0_ACK_WITH_ERR_8_Pos (8U) +#define INT_FORCE0_ACK_WITH_ERR_8_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_FORCE0_ACK_WITH_ERR_8 INT_FORCE0_ACK_WITH_ERR_8_Msk +#define INT_FORCE0_ACK_WITH_ERR_8_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_8_Pos) /*!< 0x00000100 */ +#define INT_FORCE0_ACK_WITH_ERR_7_Pos (7U) +#define INT_FORCE0_ACK_WITH_ERR_7_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_FORCE0_ACK_WITH_ERR_7 INT_FORCE0_ACK_WITH_ERR_7_Msk +#define INT_FORCE0_ACK_WITH_ERR_7_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_7_Pos) /*!< 0x00000080 */ +#define INT_FORCE0_ACK_WITH_ERR_6_Pos (6U) +#define INT_FORCE0_ACK_WITH_ERR_6_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_FORCE0_ACK_WITH_ERR_6 INT_FORCE0_ACK_WITH_ERR_6_Msk +#define INT_FORCE0_ACK_WITH_ERR_6_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_6_Pos) /*!< 0x00000040 */ +#define INT_FORCE0_ACK_WITH_ERR_5_Pos (5U) +#define INT_FORCE0_ACK_WITH_ERR_5_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_FORCE0_ACK_WITH_ERR_5 INT_FORCE0_ACK_WITH_ERR_5_Msk +#define INT_FORCE0_ACK_WITH_ERR_5_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_5_Pos) /*!< 0x00000020 */ +#define INT_FORCE0_ACK_WITH_ERR_4_Pos (4U) +#define INT_FORCE0_ACK_WITH_ERR_4_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_FORCE0_ACK_WITH_ERR_4 INT_FORCE0_ACK_WITH_ERR_4_Msk +#define INT_FORCE0_ACK_WITH_ERR_4_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_4_Pos) /*!< 0x00000010 */ +#define INT_FORCE0_ACK_WITH_ERR_3_Pos (3U) +#define INT_FORCE0_ACK_WITH_ERR_3_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_FORCE0_ACK_WITH_ERR_3 INT_FORCE0_ACK_WITH_ERR_3_Msk +#define INT_FORCE0_ACK_WITH_ERR_3_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_3_Pos) /*!< 0x00000008 */ +#define INT_FORCE0_ACK_WITH_ERR_2_Pos (2U) +#define INT_FORCE0_ACK_WITH_ERR_2_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_FORCE0_ACK_WITH_ERR_2 INT_FORCE0_ACK_WITH_ERR_2_Msk +#define INT_FORCE0_ACK_WITH_ERR_2_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_2_Pos) /*!< 0x00000004 */ +#define INT_FORCE0_ACK_WITH_ERR_1_Pos (1U) +#define INT_FORCE0_ACK_WITH_ERR_1_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_FORCE0_ACK_WITH_ERR_1 INT_FORCE0_ACK_WITH_ERR_1_Msk +#define INT_FORCE0_ACK_WITH_ERR_1_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_1_Pos) /*!< 0x00000002 */ +#define INT_FORCE0_ACK_WITH_ERR_0_Pos (0U) +#define INT_FORCE0_ACK_WITH_ERR_0_Msk (0x1UL << INT_FORCE0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ +#define INT_FORCE0_ACK_WITH_ERR_0 INT_FORCE0_ACK_WITH_ERR_0_Msk +#define INT_FORCE0_ACK_WITH_ERR_0_0 (0x1UL << INT_FORCE0_ACK_WITH_ERR_0_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: INT_FORCE1 BASE+0x00DC *********/ +#define INT_FORCE1_GEN_PLD_RECEV_ERR_Pos (12U) +#define INT_FORCE1_GEN_PLD_RECEV_ERR_Msk (0x1UL << INT_FORCE1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_FORCE1_GEN_PLD_RECEV_ERR INT_FORCE1_GEN_PLD_RECEV_ERR_Msk +#define INT_FORCE1_GEN_PLD_RECEV_ERR_0 (0x1UL << INT_FORCE1_GEN_PLD_RECEV_ERR_Pos) /*!< 0x00001000 */ +#define INT_FORCE1_GEN_PLD_RD_ERR_Pos (11U) +#define INT_FORCE1_GEN_PLD_RD_ERR_Msk (0x1UL << INT_FORCE1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_FORCE1_GEN_PLD_RD_ERR INT_FORCE1_GEN_PLD_RD_ERR_Msk +#define INT_FORCE1_GEN_PLD_RD_ERR_0 (0x1UL << INT_FORCE1_GEN_PLD_RD_ERR_Pos) /*!< 0x00000800 */ +#define INT_FORCE1_GEN_PLD_SEND_ERR_Pos (10U) +#define INT_FORCE1_GEN_PLD_SEND_ERR_Msk (0x1UL << INT_FORCE1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_FORCE1_GEN_PLD_SEND_ERR INT_FORCE1_GEN_PLD_SEND_ERR_Msk +#define INT_FORCE1_GEN_PLD_SEND_ERR_0 (0x1UL << INT_FORCE1_GEN_PLD_SEND_ERR_Pos) /*!< 0x00000400 */ +#define INT_FORCE1_GEN_PLD_WR_ERR_Pos (9U) +#define INT_FORCE1_GEN_PLD_WR_ERR_Msk (0x1UL << INT_FORCE1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_FORCE1_GEN_PLD_WR_ERR INT_FORCE1_GEN_PLD_WR_ERR_Msk +#define INT_FORCE1_GEN_PLD_WR_ERR_0 (0x1UL << INT_FORCE1_GEN_PLD_WR_ERR_Pos) /*!< 0x00000200 */ +#define INT_FORCE1_GEN_CMD_WR_ERR_Pos (8U) +#define INT_FORCE1_GEN_CMD_WR_ERR_Msk (0x1UL << INT_FORCE1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_FORCE1_GEN_CMD_WR_ERR INT_FORCE1_GEN_CMD_WR_ERR_Msk +#define INT_FORCE1_GEN_CMD_WR_ERR_0 (0x1UL << INT_FORCE1_GEN_CMD_WR_ERR_Pos) /*!< 0x00000100 */ +#define INT_FORCE1_DPI_PLD_WR_ERR_Pos (7U) +#define INT_FORCE1_DPI_PLD_WR_ERR_Msk (0x1UL << INT_FORCE1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_FORCE1_DPI_PLD_WR_ERR INT_FORCE1_DPI_PLD_WR_ERR_Msk +#define INT_FORCE1_DPI_PLD_WR_ERR_0 (0x1UL << INT_FORCE1_DPI_PLD_WR_ERR_Pos) /*!< 0x00000080 */ +#define INT_FORCE1_EOTP_ERR_Pos (6U) +#define INT_FORCE1_EOTP_ERR_Msk (0x1UL << INT_FORCE1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_FORCE1_EOTP_ERR INT_FORCE1_EOTP_ERR_Msk +#define INT_FORCE1_EOTP_ERR_0 (0x1UL << INT_FORCE1_EOTP_ERR_Pos) /*!< 0x00000040 */ +#define INT_FORCE1_PKT_SIZE_ERR_Pos (5U) +#define INT_FORCE1_PKT_SIZE_ERR_Msk (0x1UL << INT_FORCE1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_FORCE1_PKT_SIZE_ERR INT_FORCE1_PKT_SIZE_ERR_Msk +#define INT_FORCE1_PKT_SIZE_ERR_0 (0x1UL << INT_FORCE1_PKT_SIZE_ERR_Pos) /*!< 0x00000020 */ +#define INT_FORCE1_CRC_ERR_Pos (4U) +#define INT_FORCE1_CRC_ERR_Msk (0x1UL << INT_FORCE1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_FORCE1_CRC_ERR INT_FORCE1_CRC_ERR_Msk +#define INT_FORCE1_CRC_ERR_0 (0x1UL << INT_FORCE1_CRC_ERR_Pos) /*!< 0x00000010 */ +#define INT_FORCE1_ECC_MULTI_ERR_Pos (3U) +#define INT_FORCE1_ECC_MULTI_ERR_Msk (0x1UL << INT_FORCE1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_FORCE1_ECC_MULTI_ERR INT_FORCE1_ECC_MULTI_ERR_Msk +#define INT_FORCE1_ECC_MULTI_ERR_0 (0x1UL << INT_FORCE1_ECC_MULTI_ERR_Pos) /*!< 0x00000008 */ +#define INT_FORCE1_ECC_SINGLE_ERR_Pos (2U) +#define INT_FORCE1_ECC_SINGLE_ERR_Msk (0x1UL << INT_FORCE1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_FORCE1_ECC_SINGLE_ERR INT_FORCE1_ECC_SINGLE_ERR_Msk +#define INT_FORCE1_ECC_SINGLE_ERR_0 (0x1UL << INT_FORCE1_ECC_SINGLE_ERR_Pos) /*!< 0x00000004 */ +#define INT_FORCE1_TO_LP_RX_Pos (1U) +#define INT_FORCE1_TO_LP_RX_Msk (0x1UL << INT_FORCE1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_FORCE1_TO_LP_RX INT_FORCE1_TO_LP_RX_Msk +#define INT_FORCE1_TO_LP_RX_0 (0x1UL << INT_FORCE1_TO_LP_RX_Pos) /*!< 0x00000002 */ +#define INT_FORCE1_TO_HS_TX_Pos (0U) +#define INT_FORCE1_TO_HS_TX_Msk (0x1UL << INT_FORCE1_TO_HS_TX_Pos) /*!< 0x00000001 */ +#define INT_FORCE1_TO_HS_TX INT_FORCE1_TO_HS_TX_Msk +#define INT_FORCE1_TO_HS_TX_0 (0x1UL << INT_FORCE1_TO_HS_TX_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: VID_SHADOW_CTRL BASE+0x0100 *********/ +#define VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Pos (16U) +#define VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Msk (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Pos) /*!< 0x00010000 */ +#define VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Msk +#define VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_0 (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Pos) /*!< 0x00010000 */ +#define VID_SHADOW_CTRL_VID_SHADOW_REQ_Pos (8U) +#define VID_SHADOW_CTRL_VID_SHADOW_REQ_Msk (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_REQ_Pos) /*!< 0x00000100 */ +#define VID_SHADOW_CTRL_VID_SHADOW_REQ VID_SHADOW_CTRL_VID_SHADOW_REQ_Msk +#define VID_SHADOW_CTRL_VID_SHADOW_REQ_0 (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_REQ_Pos) /*!< 0x00000100 */ +#define VID_SHADOW_CTRL_VID_SHADOW_EN_Pos (0U) +#define VID_SHADOW_CTRL_VID_SHADOW_EN_Msk (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_EN_Pos) /*!< 0x00000001 */ +#define VID_SHADOW_CTRL_VID_SHADOW_EN VID_SHADOW_CTRL_VID_SHADOW_EN_Msk +#define VID_SHADOW_CTRL_VID_SHADOW_EN_0 (0x1UL << VID_SHADOW_CTRL_VID_SHADOW_EN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DPI_VCID_ACT BASE+0x010C *********/ +#define DPI_VCID_ACT_DPI_VCID_Pos (0U) +#define DPI_VCID_ACT_DPI_VCID_Msk (0x3UL << DPI_VCID_ACT_DPI_VCID_Pos) /*!< 0x00000003 */ +#define DPI_VCID_ACT_DPI_VCID DPI_VCID_ACT_DPI_VCID_Msk +#define DPI_VCID_ACT_DPI_VCID_0 (0x1UL << DPI_VCID_ACT_DPI_VCID_Pos) /*!< 0x00000001 */ +#define DPI_VCID_ACT_DPI_VCID_1 (0x2UL << DPI_VCID_ACT_DPI_VCID_Pos) /*!< 0x00000002 */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus*/ +#endif /* __REG_DSI_H__ */ diff --git a/cpu/soc-x2600/include/x2600.h b/cpu/soc-x2600/include/x2600.h index 3753ab6f..b7bfe8bd 100755 --- a/cpu/soc-x2600/include/x2600.h +++ b/cpu/soc-x2600/include/x2600.h @@ -40,6 +40,8 @@ #include "tcu.h" #include "dpu.h" #include "aic.h" +#include "dsi.h" +#include "dphy_tx.h" #ifdef __cplusplus extern "C" { @@ -84,6 +86,8 @@ extern "C" { #define PWM_BASE 0x13610000 /*!< Address base of PWM */ #define DPU_BASE 0x13050000 /*!< Address base of PWM */ #define AIC_BASE 0x10020000 /*!< Address base of AIC */ +#define MIPI_DSI_BASE 0x10023000 /*!< Address base of MIPI DSI controller */ +#define MIPI_DPHY_TX_BASE 0x10024000 /*!< The MIPI-TX-PHY's registers map base address */ /*< Peripheral declarations */ #ifdef CORE_RISCV @@ -126,7 +130,9 @@ extern "C" { #define UART7_Instance ((UART_TypeDef *) (UART7_BASE )) #define PWM_Instance ((PWM_TypeDef *) (PWM_BASE)) #define DPU_Instance ((DPU_TypeDef *) (DPU_BASE)) +#define MIPI_DSI_Instance ((DSI_TypeDef *) (MIPI_DSI_BASE)) #define AIC_Instance ((AIC_TypeDef *) (AIC_BASE)) +#define MIPI_DPHY_TX_Instance ((DPHY_TX_TypeDef *) (MIPI_DPHY_TX_BASE)) #else #define CPM_Instance ((CPM_TypeDef *) (CPM_BASE | 0xa0000000)) @@ -167,6 +173,8 @@ extern "C" { #define PWM_Instance ((PWM_TypeDef *) (PWM_BASE | 0xa0000000)) #define DPU_Instance ((DPU_TypeDef *) (DPU_BASE | 0xa0000000)) #define AIC_Instance ((AIC_TypeDef *) (AIC_BASE | 0xa0000000)) +#define MIPI_DSI_Instance ((DSI_TypeDef *) (MIPI_DSI_BASE | 0xa0000000)) +#define MIPI_DPHY_TX_Instance ((DPHY_TX_TypeDef *) (MIPI_DPHY_TX_BASE | 0xa0000000)) #endif diff --git a/drivers/drivers-x2600/ChangeLog b/drivers/drivers-x2600/ChangeLog index 8d8256e7..ecfdfb68 100644 --- a/drivers/drivers-x2600/ChangeLog +++ b/drivers/drivers-x2600/ChangeLog @@ -1,3 +1,4 @@ +2023-5-30 支持TFT-MIPI接口 2023-5-30 支持spi轮询模式、中断模式和dma模式 2023-5-26 支持TFT屏RDMA模式 2023-5-19 支持PWM DMA模式 diff --git a/drivers/drivers-x2600/include/x2600_hal_conf.h b/drivers/drivers-x2600/include/x2600_hal_conf.h index b6bdc831..d629d302 100644 --- a/drivers/drivers-x2600/include/x2600_hal_conf.h +++ b/drivers/drivers-x2600/include/x2600_hal_conf.h @@ -15,6 +15,7 @@ #define HAL_PWM_ENABLED #define HAL_TCU_ENABLED #define HAL_DPU_ENABLED +#define HAL_DPU_MIPI_ENABLED #define HAL_AIC_ENABLED #define HAL_SPI_ENABLED #if 0 @@ -49,6 +50,12 @@ #include "x2600_hal_lcd.h" #endif +#ifdef HAL_DPU_MIPI_ENABLED +#include "x2600_ll_mipi_dsi.h" +#include "x2600_hal_mipi_dsi.h" +#endif + + #ifdef HAL_I2C_ENABLED #include "x2600_hal_i2c.h" #endif diff --git a/drivers/drivers-x2600/include/x2600_hal_lcd.h b/drivers/drivers-x2600/include/x2600_hal_lcd.h index ea6d03fe..6389391a 100644 --- a/drivers/drivers-x2600/include/x2600_hal_lcd.h +++ b/drivers/drivers-x2600/include/x2600_hal_lcd.h @@ -39,6 +39,12 @@ extern "C" { * @defgroup LCD_exported_types LCD 导出的类型 (Exported Types) * @{ */ +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +typedef enum stop_mode { + QCK_STOP, + GEN_STOP, +} stop_mode_t; enum lcdc_out_format { OUT_FORMAT_RGB565, @@ -69,7 +75,8 @@ enum lcdc_lcd_mode { TFT_24BITS, TFT_8BITS_SERIAL = 2, TFT_8BITS_DUMMY_SERIAL, - + TFT_MIPI, + SLCD_MIPI, SLCD_6800, SLCD_8080, SLCD_SPI_3LINE, @@ -113,6 +120,32 @@ struct smart_lcd_data_table { enum smart_config_type type; unsigned int value; }; +enum dsi_video_mode { + VIDEO_NON_BURST_WITH_SYNC_PULSES = 0, + VIDEO_NON_BURST_WITH_SYNC_EVENTS, + VIDEO_BURST_WITH_SYNC_PULSES +}; + +enum dsi_color_coding { + COLOR_CODE_16BIT_CONFIG1, + COLOR_CODE_16BIT_CONFIG2, + COLOR_CODE_16BIT_CONFIG3, + COLOR_CODE_18BIT_CONFIG1, + COLOR_CODE_18BIT_CONFIG2, + COLOR_CODE_24BIT +}; + +enum mipi_dsi_18bit_type { + PACKED18, + LOOSELY18, +}; + +struct dsi_cmd_packet { + unsigned char packet_type; + unsigned char cmd0_or_wc_lsb; + unsigned char cmd1_or_wc_msb; + unsigned char *cmd_data; +}; enum fb_fmt { fb_fmt_RGB555, @@ -180,6 +213,30 @@ struct slcd_config{ unsigned int slcd_data_table_length; }; +/*mipi*/ +struct mipi_dsi_config{ + unsigned char num_of_lanes; + unsigned char virtual_channel; + unsigned int byte_clock; + unsigned char max_hs_to_lp_cycles; + unsigned char max_lp_to_hs_cycles; + unsigned short max_bta_cycles; + enum dsi_color_coding color_coding; + enum lcdc_signal_polarity data_en_polarity; + + enum lcdc_signal_level hsync_active_level; + enum lcdc_signal_level vsync_active_level; + + enum dsi_video_mode video_mode; + enum lcdc_signal_polarity color_mode_polarity; + enum lcdc_signal_polarity shut_down_polarity; + + enum mipi_dsi_18bit_type color_type_18bit; + + enum lcdc_te_type slcd_te_pin_mode; + enum lcdc_signal_polarity slcd_te_data_transfered_edge; +}; + struct lcd_data{ const char *name; unsigned int refresh; @@ -199,14 +256,16 @@ struct lcd_data{ struct tft_config *tft; struct slcd_config *slcd; + struct mipi_dsi_config *mipi; int frame_status; int frame_index; uint32_t frame_mem; uint32_t frame_size; - int (*power_on)(void); - int (*power_off)(void); + void (*power_on)(void); + void (*power_off)(void); + void (*lcd_init)(void); }; typedef struct __LCD_HandleTypeDef { diff --git a/drivers/drivers-x2600/include/x2600_hal_mipi_dsi.h b/drivers/drivers-x2600/include/x2600_hal_mipi_dsi.h new file mode 100755 index 00000000..87adb256 --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_hal_mipi_dsi.h @@ -0,0 +1,177 @@ +/** + * @file x2600_hal_mipi_dsi.h + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_HAL_MIPI_DSI_H__ +#define __X2600_HAL_MIPI_DSI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @addtogroup group_MIPI_DSI + * @{ + */ + +/** + * @addtogroup g_X2600_MIPI_DSI_HAL_Driver MIPI DSI HAL 驱动 + * @{ + */ + +/* 1. 头文件 (Includes)----------------------------------------------- */ +#include "x2600_hal.h" +#include "x2600_hal_def.h" +#include "x2600_ll_mipi_dsi.h" +/* 2. 导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_types MIPI DSI 导出的类型 (Exported Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3. 导出常量定义 Exported Constants ----------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_constants MIPI DSI 导出的常量 Exported Constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 4. 导出宏定义 Exported Macros --------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_macros MIPI DSI 导出宏 Exported Macros + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 5. 导出函数申明 Exported Funcs --------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_funcs MIPI DSI 导出函数申明 Exported Funcs + * @{ + */ +int dsi_write_cmd(struct dsi_cmd_packet *cmd_data); + +int dsi_read_cmd(struct dsi_cmd_packet *cmd_data, int bytes, unsigned char *rd_buf); + +int jz_mipi_dsi_data_init(struct lcd_data *lcd_data); + +void jz_dsi_command_cfg(void); + +void jz_dsi_video_cfg(void); + +void jz_enable_mipi_dsi(void); + +void jz_disable_mipi_dsi(void); + +/** + * @} + */ +/* 6. 导出变量申明 (Exported Variables) --------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_var MIPI DSI 导出变量申明 (Exported Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_types MIPI DSI 私有类型定义 (Private Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 8. 私有常量定义Private Constants ------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_constants MIPI DSI 私有常量定义Private Constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 9. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_macros MIPI DSI 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 10. 私有函数申明 (Private Funcs) ------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_funcs MIPI DSI 私有函数申明 (Private Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 11. 私有变量申明 Private Variables ----------------------------------- */ +/** + * @defgroup MIPI_DSI_private_var MIPI DSI 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_MIPI_DSI_H__ */ diff --git a/drivers/drivers-x2600/include/x2600_ll_mipi_dsi.h b/drivers/drivers-x2600/include/x2600_ll_mipi_dsi.h new file mode 100755 index 00000000..08036520 --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_ll_mipi_dsi.h @@ -0,0 +1,929 @@ +/** + * @file x2600_ll_mipi_dsi.h + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_LL_MIPI_DSI_H__ +#define __X2600_LL_MIPI_DSI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @addtogroup group_MIPI_DSI + * @{ + */ + +/** + * @addtogroup g_X2600_MIPI_DSI_LL_Driver MIPI DSI LL 驱动 + * @{ + */ + +/* 1. 头文件 (Includes)----------------------------------------------- */ +#include "x2600_hal.h" +/* 2. 导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_types MIPI DSI 导出的类型 (Exported Types) + * @{ + */ + +struct video_config { + unsigned char virtual_channel; + enum dsi_video_mode video_mode; + unsigned int receive_ack_packets; + + enum lcdc_signal_polarity data_en_polarity; + + enum lcdc_signal_level h_polarity; + unsigned short h_active_pixels; /* hadr */ + unsigned short hs; + unsigned short hbp; /* hbp */ + unsigned short h_total_pixels; /* h_total */ + + enum lcdc_signal_level v_polarity; + unsigned short v_active_lines; /* vadr */ + unsigned short vs; + unsigned short vbp; /* vbp */ + unsigned short vfp; /* v_total */ + + unsigned int byte_clock; + unsigned int pixel_clock; + + unsigned int chunk; + unsigned int null_size; + unsigned int video_size; + + unsigned int bpp_info; +}; + +struct dsi_config { + unsigned char num_of_lanes; + unsigned char max_hs_to_lp_cycles; + unsigned char max_lp_to_hs_cycles; + unsigned short max_bta_cycles; + enum lcdc_signal_polarity color_mode_polarity; + enum lcdc_signal_polarity shut_down_polarity; + enum dsi_color_coding color_coding; + enum mipi_dsi_18bit_type color_type_18bit; + int te_mipi_en; +}; + +struct jz_dsi{ + DSI_TypeDef *Instance; + struct video_config video_config; + struct dsi_config dsi_config; + int dsi_en; + DPHY_TX_TypeDef * DPHY_TX_Instance; + unsigned int real_mipiclk; +}; + +/** + * @} + */ +/* 3. 导出常量定义 Exported Constants ----------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_constants MIPI DSI 导出的常量 Exported Constants + * @{ + */ + +/********* Register BitField Details: VERSION BASE+0x0000 *********/ +#define __HAL_DSI_VERSION(__HANDLE__) READ_REG((__HANDLE__)->Instance->VERSION) + +/********* Register BitField Details: PWR_UP BASE+0x0004 *********/ +#define __HAL_DSI_PWR_UP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PWR_UP, PWR_UP_SHUTDOWNZ_0) + +#define __HAL_DSI_RESET(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PWR_UP, PWR_UP_SHUTDOWNZ_0) + +/********* Register BitField Details: CLKMGR_CFG BASE+0x0008 *********/ +#define __HAL_DSI_TO_CLK_DIV(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->CLKMGR_CFG, ((~CLKMGR_CFG_TO_CLK_DIVISION_Msk) & (READ_REG((__HANDLE__)->Instance->CLKMGR_CFG))) | (__VALUE__) << CLKMGR_CFG_TO_CLK_DIVISION_Pos) + +#define __HAL_DSI_TX_ESC_CLK_DIV(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->CLKMGR_CFG, ((~CLKMGR_CFG_TX_ESC_CLK_DIVISION_Msk) & (READ_REG((__HANDLE__)->Instance->CLKMGR_CFG))) | (__VALUE__) << CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos) + +/********* Register BitField Details: DPI_VCID BASE+0x000C *********/ +#define __HAL_DSI_DPI_VCID(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DPI_VCID, ((~DPI_VCID_DPI_VCID_Msk) & (READ_REG((__HANDLE__)->Instance->DPI_VCID))) | (__VALUE__) << DPI_VCID_DPI_VCID_Pos) + +/********* Register BitField Details: DPI_COLOR_CODING BASE+0x0010 *********/ +#define __HAL_DSI_DPI_COLOR_CODING(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DPI_COLOR_CODING, ((~DPI_COLOR_CODING_DPI_COLOR_CODING_Msk) & (READ_REG((__HANDLE__)->Instance->DPI_COLOR_CODING))) | (__VALUE__) << DPI_COLOR_CODING_DPI_COLOR_CODING_Pos) + +#define __HAL_DSI_LOSE18_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_COLOR_CODING, DPI_COLOR_CODING_LOSE18_EN_0) + +#define __HAL_DSI_LOSE18_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_COLOR_CODING, DPI_COLOR_CODING_LOSE18_EN_0) + +/********* Register BitField Details: DPI_CFG_POL BASE+0x0014 *********/ +#define __HAL_DSI_COLORMODE_ACTIVE_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_COLORM_ACT_0) + +#define __HAL_DSI_COLORMODE_ACTIVE_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_COLORM_ACT_0) + +#define __HAL_DSI_SHUTDOWN_ACTIVE_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_SHUTD_ACT_0) + +#define __HAL_DSI_SHUTDOWN_ACTIVE_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_SHUTD_ACT_0) + +#define __HAL_DSI_HSYNC_ACTIVE_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_HSYNC_ACT_0) + +#define __HAL_DSI_HSYNC_ACTIVE_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_HSYNC_ACT_0) + +#define __HAL_DSI_VSYNC_ACTIVE_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_VSYNC_ACT_0) + +#define __HAL_DSI_VSYNC_ACTIVE_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_VSYNC_ACT_0) + +#define __HAL_DSI_DATAEN_ACTIVE_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_DATAEN_ACT_0) + +#define __HAL_DSI_DATAEN_ACTIVE_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DPI_CFG_POL, DPI_CFG_POL_DATAEN_ACT_0) + +/********* Register BitField Details: DPI_LP_CMD_TIM BASE+0x0018 *********/ +#define __HAL_DSI_OUTVACT_LPCMD_LINE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DPI_LP_CMD_TIM, ((~DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Msk) & (READ_REG((__HANDLE__)->Instance->DPI_LP_CMD_TIM))) | (__VALUE__) << DPI_LP_CMD_TIM_OUTVACT_LPCMD_LINE_Pos) + +#define __HAL_DSI_INVACT_LPCMD_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DPI_LP_CMD_TIM, ((~DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->DPI_LP_CMD_TIM))) | (__VALUE__) << DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos) + +/********* Register BitField Details: PCKHDL_CFG BASE+0x002C *********/ +#define __HAL_DSI_CRC_RX_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_CRC_RX_EN_0) + +#define __HAL_DSI_CRC_RX_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_CRC_RX_EN_0) + +#define __HAL_DSI_ECC_RX_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_ECC_RX_EN_0) + +#define __HAL_DSI_ECC_RX_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_ECC_RX_EN_0) + +#define __HAL_DSI_BTA_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_BTA_EN_0) + +#define __HAL_DSI_BTA_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_BTA_EN_0) + +#define __HAL_DSI_EOTP_RX_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_EOTP_RX_EN_0) + +#define __HAL_DSI_EOTP_RX_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_EOTP_RX_EN_0) + +#define __HAL_DSI_EOTP_TX_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_EOTP_TX_EN_0) + +#define __HAL_DSI_EOTP_TX_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PCKHDL_CFG, PCKHDL_CFG_EOTP_TX_EN_0) + +/********* Register BitField Details: GEN_VCID BASE+0x0030 *********/ +#define __HAL_DSI_GEN_VCID_RX(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_VCID, ((~GEN_VCID_GEN_VCID_RX_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_VCID))) | (__VALUE__) << GEN_VCID_GEN_VCID_RX_Pos) + +/********* Register BitField Details: MODE_CFG BASE+0x0034 *********/ +#define __HAL_DSI_CMD_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MODE_CFG, MODE_CFG_CMD_VIDEO_MODE_0) + +#define __HAL_DSI_VIDEO_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MODE_CFG, MODE_CFG_CMD_VIDEO_MODE_0) + +/********* Register BitField Details: VID_MODE_CFG BASE+0x0038 *********/ +#define __HAL_DSI_HORIZONTAL_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_ORIENTATION_0) + +#define __HAL_DSI_VERTICAL_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_ORIENTATION_0) + +#define __HAL_DSI_HORIZONTAL_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_ORIENTATION_0) + +#define __HAL_DSI_VERTICAL_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_ORIENTATION_0) + +#define __HAL_DSI_BER_PATTERN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_MODE_0) + +#define __HAL_DSI_COLOR_BAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_MODE_0) + +#define __HAL_DSI_VPG_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_EN_0) + +#define __HAL_DSI_VPG_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_VPG_EN_0) + +#define __HAL_DSI_LP_CMD_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_CMD_EN_0) + +#define __HAL_DSI_LP_CMD_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_CMD_EN_0) + +#define __HAL_DSI_FRAME_BTA_ACK_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_FRAME_BTA_ACK_EN_0) + +#define __HAL_DSI_FRAME_BTA_ACK_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_FRAME_BTA_ACK_EN_0) + +#define __HAL_DSI_LP_HFP_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_HFP_EN_0) + +#define __HAL_DSI_LP_HFP_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_HFP_EN_0) + +#define __HAL_DSI_LP_HBP_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_HBP_EN_0) + +#define __HAL_DSI_LP_HBP_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_HBP_EN_0) + +#define __HAL_DSI_LP_VACT_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VACT_EN_0) + +#define __HAL_DSI_LP_VACT_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VACT_EN_0) + +#define __HAL_DSI_LP_VFP_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VFP_EN_0) + +#define __HAL_DSI_LP_VFP_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VFP_EN_0) + +#define __HAL_DSI_LP_VBP_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VBP_EN_0) + +#define __HAL_DSI_LP_VBP_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VBP_EN_0) + +#define __HAL_DSI_LP_VSA_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VSA_EN_0) + +#define __HAL_DSI_LP_VSA_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_MODE_CFG, VID_MODE_CFG_LP_VSA_EN_0) + +#define __HAL_DSI_VID_MODE_TYPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_MODE_CFG, ((~VID_MODE_CFG_VID_MODE_TYPE_Msk) & (READ_REG((__HANDLE__)->Instance->VID_MODE_CFG))) | (__VALUE__) << VID_MODE_CFG_VID_MODE_TYPE_Pos) + +/********* Register BitField Details: VID_PKT_SIZE BASE+0x003C *********/ +#define __HAL_DSI_VID_PKT_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_PKT_SIZE, ((~VID_PKT_SIZE_VID_PKT_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->VID_PKT_SIZE))) | (__VALUE__) << VID_PKT_SIZE_VID_PKT_SIZE_Pos) + +/********* Register BitField Details: VID_NUM_CHUNKS BASE+0x0040 *********/ +#define __HAL_DSI_VID_NUM_CHUNKS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_NUM_CHUNKS, ((~VID_NUM_CHUNKS_VID_NUM_CHUNKS_Msk) & (READ_REG((__HANDLE__)->Instance->VID_NUM_CHUNKS))) | (__VALUE__) << VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos) + +/********* Register BitField Details: VID_NULL_SIZE BASE+0x0044 *********/ +#define __HAL_DSI_VID_NULL_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_NULL_SIZE, ((~VID_NULL_SIZE_VID_NULL_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->VID_NULL_SIZE))) | (__VALUE__) << VID_NULL_SIZE_VID_NULL_SIZE_Pos) + +/********* Register BitField Details: VID_HSA_TIME BASE+0x0048 *********/ +#define __HAL_DSI_VID_HSA_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_HSA_TIME, ((~VID_HSA_TIME_VID_HSA_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->VID_HSA_TIME))) | (__VALUE__) << VID_HSA_TIME_VID_HSA_TIME_Pos) + +/********* Register BitField Details: VID_HBP_TIME BASE+0x004C *********/ +#define __HAL_DSI_VID_HBP_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_HBP_TIME, ((~VID_HBP_TIME_VID_HBP_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->VID_HBP_TIME))) | (__VALUE__) << VID_HBP_TIME_VID_HBP_TIME_Pos) + +/********* Register BitField Details: VID_HLINE_TIME BASE+0x0050 *********/ +#define __HAL_DSI_VID_HLINE_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_HLINE_TIME, ((~VID_NULL_SIZE_VID_HLINE_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->VID_HLINE_TIME))) | (__VALUE__) << VID_NULL_SIZE_VID_HLINE_TIME_Pos) + +/********* Register BitField Details: VID_VSA_LINES BASE+0x0054 *********/ +#define __HAL_DSI_VID_VSA_LINES(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_VSA_LINES, ((~VID_NULL_SIZE_VSA_LINES_Msk) & (READ_REG((__HANDLE__)->Instance->VID_VSA_LINES))) | (__VALUE__) << VID_NULL_SIZE_VSA_LINES_Pos) + +/********* Register BitField Details: VID_VBP_LINES BASE+0x0058 *********/ +#define __HAL_DSI_VID_VBP_LINES(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_VBP_LINES, ((~VID_VBP_HLINES_VBP_LINES_Msk) & (READ_REG((__HANDLE__)->Instance->VID_VBP_LINES))) | (__VALUE__) << VID_VBP_HLINES_VBP_LINES_Pos) + +/********* Register BitField Details: VID_VFP_LINES BASE+0x005C *********/ +#define __HAL_DSI_VID_VFP_LINES(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_VFP_LINES, ((~VID_VFP_LINES_VBP_LINES_Msk) & (READ_REG((__HANDLE__)->Instance->VID_VFP_LINES))) | (__VALUE__) << VID_VFP_LINES_VBP_LINES_Pos) + +/********* Register BitField Details: VID_VACTIVE_LINES BASE+0x0060 *********/ +#define __HAL_DSI_VID_VACTIVE_LINES(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->VID_VACTIVE_LINES, ((~VID_VACTIVE_LINES_V_ACTIVE_LINES_Msk) & (READ_REG((__HANDLE__)->Instance->VID_VACTIVE_LINES))) | (__VALUE__) << VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos) + +/********* Register BitField Details: EDPI_CMD_SIZE BASE+0x0064 *********/ +#define __HAL_DSI_EDPI_CMD_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->EDPI_CMD_SIZE, ((~EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->EDPI_CMD_SIZE))) | (__VALUE__) << EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos) + +/********* Register BitField Details: CMD_MODE_CFG BASE+0x0068 *********/ +#define __HAL_DSI_MAX_RD_PKT_SIZE_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_MAX_RD_PKT_SIZE_0) + +#define __HAL_DSI_MAX_RD_PKT_SIZE_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_MAX_RD_PKT_SIZE_0) + +#define __HAL_DSI_DCS_LW_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_LW_TX_0) + +#define __HAL_DSI_DCS_LW_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_LW_TX_0) + +#define __HAL_DSI_DCS_SR_0P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SR_0P_TX_0) + +#define __HAL_DSI_DCS_SR_0P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SR_0P_TX_0) + +#define __HAL_DSI_DCS_SW_1P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SW_1P_TX_0) + +#define __HAL_DSI_DCS_SW_1P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SW_1P_TX_0) + +#define __HAL_DSI_DCS_SW_0P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SW_0P_TX_0) + +#define __HAL_DSI_DCS_SW_0P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_DCS_SW_0P_TX_0) + +#define __HAL_DSI_GEN_LW_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_LW_TX_0) + +#define __HAL_DSI_GEN_LW_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_LW_TX_0) + +#define __HAL_DSI_GEN_SR_2P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_2P_TX_0) + +#define __HAL_DSI_GEN_SR_2P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_2P_TX_0) + +#define __HAL_DSI_GEN_SR_1P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_1P_TX_0) + +#define __HAL_DSI_GEN_SR_1P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_1P_TX_0) + +#define __HAL_DSI_GEN_SR_0P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_0P_TX_0) + +#define __HAL_DSI_GEN_SR_0P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SR_0P_TX_0) + +#define __HAL_DSI_GEN_SW_2P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_2P_TX_0) + +#define __HAL_DSI_GEN_SW_2P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_2P_TX_0) + +#define __HAL_DSI_GEN_SW_1P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_1P_TX_0) + +#define __HAL_DSI_GEN_SW_1P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_1P_TX_0) + +#define __HAL_DSI_GEN_SW_0P_TX_LP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_0P_TX_0) + +#define __HAL_DSI_GEN_SW_0P_TX_HS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_GEN_SW_0P_TX_0) + +#define __HAL_DSI_ACK_RQST_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_ACK_RQST_EN_0) + +#define __HAL_DSI_ACK_RQST_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_ACK_RQST_EN_0) + +#define __HAL_DSI_TEAR_FX_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_TEAR_FX_EN_0) + +#define __HAL_DSI_TEAR_FX_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CMD_MODE_CFG, CMD_MODE_CFG_TEAR_FX_EN_0) + +/********* Register BitField Details: GEN_HDR BASE+0x006C *********/ +#define __HAL_DSI_GEN_WC_MSBYTE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_HDR, ((~GEN_HDR_GEN_WC_MSBYTE_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_HDR))) | (__VALUE__) << GEN_HDR_GEN_WC_MSBYTE_Pos) + +#define __HAL_DSI_GEN_WC_LSBYTE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_HDR, ((~GEN_HDR_GEN_WC_LSBYTE_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_HDR))) | (__VALUE__) << GEN_HDR_GEN_WC_LSBYTE_Pos) + +#define __HAL_DSI_GEN_VC(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_HDR, ((~GEN_HDR_GEN_VC_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_HDR))) | (__VALUE__) << GEN_HDR_GEN_VC_Pos) + +#define __HAL_DSI_GEN_DT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_HDR, ((~GEN_HDR_GEN_DT_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_HDR))) | (__VALUE__) << GEN_HDR_GEN_DT_Pos) + +/********* Register BitField Details: GEN_PLD_DATA BASE+0x0070 *********/ +#define __HAL_DSI_GEN_PLD_B4(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_PLD_DATA, ((~GEN_PLD_DATA_GEN_PLD_B4_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_PLD_DATA))) | (__VALUE__) << GEN_PLD_DATA_GEN_PLD_B4_Pos) + +#define __HAL_DSI_GEN_PLD_B3(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_PLD_DATA, ((~GEN_PLD_DATA_GEN_PLD_B3_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_PLD_DATA))) | (__VALUE__) << GEN_PLD_DATA_GEN_PLD_B3_Pos) + +#define __HAL_DSI_GEN_PLD_B2(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_PLD_DATA, ((~GEN_PLD_DATA_GEN_PLD_B2_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_PLD_DATA))) | (__VALUE__) << GEN_PLD_DATA_GEN_PLD_B2_Pos) + +#define __HAL_DSI_GEN_PLD_B1(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->GEN_PLD_DATA, ((~GEN_PLD_DATA_GEN_PLD_B1_Msk) & (READ_REG((__HANDLE__)->Instance->GEN_PLD_DATA))) | (__VALUE__) << GEN_PLD_DATA_GEN_PLD_B1_Pos) + +/********* Register BitField Details: TO_CNT_CFG BASE+0x0078 *********/ +#define __HAL_DSI_HSTX_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TO_CNT_CFG, ((~TO_CNT_CFG_HSTX_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->TO_CNT_CFG))) | (__VALUE__) << TO_CNT_CFG_HSTX_TO_CNT_Pos) + +#define __HAL_DSI_LPRX_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TO_CNT_CFG, ((~TO_CNT_CFG_LPRX_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->TO_CNT_CFG))) | (__VALUE__) << TO_CNT_CFG_LPRX_TO_CNT_Pos) + +/********* Register BitField Details: HS_RD_TO_CNT BASE+0x007C *********/ +#define __HAL_DSI_HS_RD_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->HS_RD_TO_CNT, ((~HS_RD_TO_CNT_HS_RD_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->HS_RD_TO_CNT))) | (__VALUE__) << HS_RD_TO_CNT_HS_RD_TO_CNT_Pos) + +/********* Register BitField Details: LP_RD_TO_CNT BASE+0x0080 *********/ +#define __HAL_DSI_LP_RD_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->LP_RD_TO_CNT, ((~LP_RD_TO_CNT_LP_RD_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->LP_RD_TO_CNT))) | (__VALUE__) << LP_RD_TO_CNT_LP_RD_TO_CNT_Pos) + +/********* Register BitField Details: HS_WR_TO_CNT BASE+0x0084 *********/ +#define __HAL_DSI_PRESP_TO_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->HS_WR_TO_CNT, HS_WR_TO_CNT_PRESP_TO_MODE_0) + +#define __HAL_DSI_HS_WR_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->HS_WR_TO_CNT, ((~HS_WR_TO_CNT_HS_WR_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->HS_WR_TO_CNT))) | (__VALUE__) << HS_WR_TO_CNT_HS_WR_TO_CNT_Pos) + +/********* Register BitField Details: BTA_TO_CNT BASE+0x008C *********/ +#define __HAL_DSI_BTA_TO_CNT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->BTA_TO_CNT, ((~BTA_TO_CNT_BTA_TO_CNT_Msk) & (READ_REG((__HANDLE__)->Instance->BTA_TO_CNT))) | (__VALUE__) << BTA_TO_CNT_BTA_TO_CNT_Pos) + +/********* Register BitField Details: SOF_3D BASE+0x0090 *********/ +#define __HAL_DSI_SET_SEND_3D_CFG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_SEND_3D_CFG_0) + +#define __HAL_DSI_CLEAR_SEND_3D_CFG(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_SEND_3D_CFG_0) + +#define __HAL_DSI_RIGHT_FIRST(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_RIGHT_FIRST_0) + +#define __HAL_DSI_LEFT_FIRST(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_RIGHT_FIRST_0) + +#define __HAL_DSI_SET_SECOND_VSYNC(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_SECOND_VSYNC_0) + +#define __HAL_DSI_CLEAR_SECOND_VSYNC(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SDF_3D, SOF_3D_SECOND_VSYNC_0) + +#define __HAL_DSI_FORMAT_3D(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SDF_3D, ((~SOF_3D_FORMAT_3D_Msk) & (READ_REG((__HANDLE__)->Instance->SDF_3D))) | (__VALUE__) << SOF_3D_FORMAT_3D_Pos) + +#define __HAL_DSI_MODE_3D(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SDF_3D, ((~SOF_3D_MODE_3D_Msk) & (READ_REG((__HANDLE__)->Instance->SDF_3D))) | (__VALUE__) << SOF_3D_MODE_3D_Pos) + +/********* Register BitField Details: LPCLK_CTRL BASE+0x0094 *********/ +#define __HAL_DSI_SET_AUTO_CLKLANE_CTRL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->LPCLK_CTRL, HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_0) + +#define __HAL_DSI_CLEAR_AUTO_CLKLANE_CTRL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->LPCLK_CTRL, HS_WR_TO_CNT_AUTO_CLKLANE_CTRL_0) + +#define __HAL_DSI_SET_PHY_TXREQUESTCLKHS(__HANDLE__) SET_BIT((__HANDLE__)->Instance->LPCLK_CTRL, HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_0) + +#define __HAL_DSI_CLEAR_PHY_TXREQUESTCLKHS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->LPCLK_CTRL, HS_WR_TO_CNT_PHY_TXREQUESTCLKHS_0) + +/********* Register BitField Details: PHY_TMR_LPCLK_CFG BASE+0x0098 *********/ +#define __HAL_DSI_PHY_CLKHS2LP_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TMR_LPCLK_CFG, ((~PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TMR_LPCLK_CFG))) | (__VALUE__) << PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos) + +#define __HAL_DSI_PHY_CLKLP2HS_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TMR_LPCLK_CFG, ((~PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TMR_LPCLK_CFG))) | (__VALUE__) << PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos) + +/********* Register BitField Details: PHY_TMR_CFG BASE+0x009C *********/ +#define __HAL_DSI_PHY_HS2LP_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TMR_CFG, ((~PHY_TMR_CFG_PHY_HS2LP_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TMR_CFG))) | (__VALUE__) << PHY_TMR_CFG_PHY_HS2LP_TIME_Pos) + +#define __HAL_DSI_PHY_LP2HS_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TMR_CFG, ((~PHY_TMR_CFG_PHY_LP2HS_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TMR_CFG))) | (__VALUE__) << PHY_TMR_CFG_PHY_LP2HS_TIME_Pos) + +#define __HAL_DSI_PHY_MAX_RD_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TMR_CFG, ((~PHY_TMR_CFG_MAX_RD_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TMR_CFG))) | (__VALUE__) << PHY_TMR_CFG_MAX_RD_TIME_Pos) + +/********* Register BitField Details: PHY_RSTZ BASE+0x00A0 *********/ +#define __HAL_DSI_SET_PHY_FORCEPLL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_FORCEPLL_0) + +#define __HAL_DSI_CLEAR_PHY_FORCEPLL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_FORCEPLL_0) + +#define __HAL_DSI_SET_PHY_ENABLECLK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_ENABLECLK_0) + +#define __HAL_DSI_CLEAR_PHY_ENABLECLK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_ENABLECLK_0) + +#define __HAL_DSI_SET_PHY_RSTZ(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_RSTZ_0) + +#define __HAL_DSI_CLEAR_PHY_RSTZ(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_RSTZ_0) + +#define __HAL_DSI_SET_PHY_SHUTDOWNZ(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_SHUTDOWNZ_0) + +#define __HAL_DSI_CLEAR_PHY_SHUTDOWNZ(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_RSTZ, PHY_RSTZ_PHY_SHUTDOWNZ_0) + +/********* Register BitField Details: PHY_IF_CFG BASE+0x00A4 *********/ +#define __HAL_DSI_PHY_STOP_WAIT_TIME(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_IF_CFG, ((~PHY_IF_CFG_PHY_STOP_WAIT_TIME_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_IF_CFG))) | (__VALUE__) << PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos) + +#define __HAL_DSI_N_LANES(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_IF_CFG, ((~PHY_IF_CFG_N_LANES_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_IF_CFG))) | (__VALUE__) << PHY_IF_CFG_N_LANES_Pos) + +/********* Register BitField Details: PHY_ULPS_CTRL BASE+0x00A8 *********/ +#define __HAL_DSI_SET_PHY_TXEXITULPSLAN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_0) + +#define __HAL_DSI_CLEAR_PHY_TXEXITULPSLAN(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_0) + +#define __HAL_DSI_SET_PHY_TXREQULPSLAN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXREQULPSLAN_0) + +#define __HAL_DSI_CLEAR_PHY_TXREQULPSLAN(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXREQULPSLAN_0) + +#define __HAL_DSI_SET_PHY_TXEXITULPSCLK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_0) + +#define __HAL_DSI_CLEAR_PHY_TXEXITULPSCLK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_0) + +#define __HAL_DSI_SET_PHY_TXREQULPSCLK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXREQULPSCLK_0) + +#define __HAL_DSI_CLEAR_PHY_TXREQULPSCLK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_ULPS_CTRL, PHY_ULPS_CTRL_PHY_TXREQULPSCLK_0) + +/********* Register BitField Details: PHY_TX_TRIGGERS BASE+0x00AC *********/ +#define __HAL_DSI_PHY_TX_TRIGGERS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TX_TRIGGERS, ((~PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TX_TRIGGERS))) | (__VALUE__) << PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos) + +/********* Register BitField Details: PHY_STATUS BASE+0x00B0 *********/ +#define __HAL_DSI_SET_PHY_ULPSACTIVENOT1LANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOT1LANE_0) + +#define __HAL_DSI_CLEAR_PHY_ULPSACTIVENOT1LANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOT1LANE_0) + +#define __HAL_DSI_SET_PHY_STOPSTATE1LANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATE1LANE_0) + +#define __HAL_DSI_CLEAR_PHY_STOPSTATE1LANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATE1LANE_0) + +#define __HAL_DSI_SET_PHY_RXULPSESC0LANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_RXULPSESC0LANE_0) + +#define __HAL_DSI_CLEAR_PHY_RXULPSESC0LANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_RXULPSESC0LANE_0) + +#define __HAL_DSI_SET_PHY_ULPSACTIVENOT0LANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOT0LANE_0) + +#define __HAL_DSI_CLEAR_PHY_ULPSACTIVENOT0LANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOT0LANE_0) + +#define __HAL_DSI_SET_PHY_STOPSTATE0LANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATE0LANE_0) + +#define __HAL_DSI_CLEAR_PHY_STOPSTATE0LANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATE0LANE_0) + +#define __HAL_DSI_SET_PHY_ULPSACTIVENOTCLK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOTCLK_0) + +#define __HAL_DSI_CLEAR_PHY_ULPSACTIVENOTCLK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_ULPSACTIVENOTCLK_0) + +#define __HAL_DSI_SET_PHY_STOPSTATECLKLANE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATECLKLANE_0) + +#define __HAL_DSI_CLEAR_PHY_STOPSTATECLKLANE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_STOPSTATECLKLANE_0) + +#define __HAL_DSI_SET_PHY_DIRECTION(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_DIRECTION_0) + +#define __HAL_DSI_CLEAR_PHY_DIRECTION(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_DIRECTION_0) + +#define __HAL_DSI_SET_PHY_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_LOCK_0) + +#define __HAL_DSI_CLEAR_PHY_LOCK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_STATUS, PHY_STATUS_PHY_LOCK_0) + +/********* Register BitField Details: PHY_TST_CTRL0 BASE+0x00B4 *********/ +#define __HAL_DSI_SET_PHY_TESTCLK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_TST_CTRL0, PHY_TST_CTRL0_PHY_TESTCLK_0) + +#define __HAL_DSI_CLEAR_PHY_TESTCLK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_TST_CTRL0, PHY_TST_CTRL0_PHY_TESTCLK_0) + +#define __HAL_DSI_SET_PHY_TESTCLR(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_TST_CTRL0, PHY_TST_CTRL0_PHY_TESTCLR_0) + +#define __HAL_DSI_CLEAR_PHY_TESTCLR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_TST_CTRL0, PHY_TST_CTRL0_PHY_TESTCLR_0) + +/********* Register BitField Details: PHY_TST_CTRL1 BASE+0x00B8 *********/ +#define __HAL_DSI_SET_PHY_TESTEN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->PHY_TST_CTRL1, PHY_TST_CTRL1_PHY_TESTEN_0) + +#define __HAL_DSI_CLEAR_PHY_TESTEN(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->PHY_TST_CTRL1, PHY_TST_CTRL1_PHY_TESTEN_0) + +#define __HAL_DSI_PHY_TESTDOUT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TST_CTRL1, ((~PHY_TST_CTRL1_PHY_TESTDOUT_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TST_CTRL1))) | (__VALUE__) << PHY_TST_CTRL1_PHY_TESTDOUT_Pos) + +#define __HAL_DSI_PHY_TESTDIN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->PHY_TST_CTRL1, ((~PHY_TST_CTRL1_PHY_TESTDIN_Msk) & (READ_REG((__HANDLE__)->Instance->PHY_TST_CTRL1))) | (__VALUE__) << PHY_TST_CTRL1_PHY_TESTDIN_Pos) + +/********* Register BitField Details: INT_MSK0 BASE+0x00C4 *********/ +#define __HAL_DSI_SET_DPHY_ERRORS_4_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_4_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_4_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_4_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_3_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_3_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_3_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_3_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_2_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_2_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_2_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_2_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_1_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_1_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_1_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_1_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_0_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_0_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_0_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_DPHY_ERRORS_0_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_15_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_15_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_15_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_15_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_14_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_14_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_14_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_14_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_13_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_13_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_13_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_13_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_12_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_12_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_12_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_12_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_11_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_11_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_11_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_11_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_10_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_10_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_10_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_10_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_9_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_9_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_9_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_9_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_8_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_8_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_8_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_8_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_7_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_7_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_7_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_7_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_6_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_6_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_6_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_6_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_5_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_5_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_5_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_5_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_4_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_4_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_4_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_4_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_3_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_3_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_3_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_3_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_2_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_2_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_2_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_2_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_1_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_1_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_1_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_1_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_0_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_0_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_0_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK0, INT_MSK0_ACK_WITH_ERR_0_0) + +/********* Register BitField Details: INT_MSK1 BASE+0x00C8 *********/ +#define __HAL_DSI_SET_GEN_PLD_RECEV_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_RECEV_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_RECEV_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_RECEV_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_RD_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_RD_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_RD_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_RD_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_SEND_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_SEND_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_SEND_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_SEND_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_WR_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_WR_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_PLD_WR_ERR_0) + +#define __HAL_DSI_SET_GEN_CMD_WR_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_CMD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_CMD_WR_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_GEN_CMD_WR_ERR_0) + +#define __HAL_DSI_SET_DPI_PLD_WR_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_DPI_PLD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_DPI_PLD_WR_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_DPI_PLD_WR_ERR_0) + +#define __HAL_DSI_SET_EOPT_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_EOTP_ERR_0) + +#define __HAL_DSI_CLEAR_EOPT_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_EOTP_ERR_0) + +#define __HAL_DSI_SET_PKT_SIZE_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_PKT_SIZE_ERR_0) + +#define __HAL_DSI_CLEAR_PKT_SIZE_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_PKT_SIZE_ERR_0) + +#define __HAL_DSI_SET_CRC_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_CRC_ERR_0) + +#define __HAL_DSI_CLEAR_CRC_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_CRC_ERR_0) + +#define __HAL_DSI_SET_ECC_MULTI_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_ECC_MULTI_ERR_0) + +#define __HAL_DSI_CLEAR_ECC_MULTI_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_ECC_MULTI_ERR_0) + +#define __HAL_DSI_SET_ECC_SINGLE_ERR_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_ECC_SINGLE_ERR_0) + +#define __HAL_DSI_CLEAR_ECC_SINGLE_ERR_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_ECC_SINGLE_ERR_0) + +#define __HAL_DSI_SET_TO_LP_RX_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_TO_LP_RX_0) + +#define __HAL_DSI_CLEAR_TO_LP_RX_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_TO_LP_RX_0) + +#define __HAL_DSI_SET_TO_HS_TX_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_TO_HS_TX_0) + +#define __HAL_DSI_CLEAR_TO_HS_TX_MSK(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_MSK1, INT_MSK1_TO_HS_TX_0) + +/********* Register BitField Details: INT_FORCE0 BASE+0x00D8 *********/ +/* FORCE 只写寄存器 作用:强制触发中断*/ +#define __HAL_DSI_SET_DPHY_ERRORS_4_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_4_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_4_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_4_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_3_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_3_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_3_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_3_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_2_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_2_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_2_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_2_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_1_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_1_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_1_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_1_0) + +#define __HAL_DSI_SET_DPHY_ERRORS_0_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_0_0) + +#define __HAL_DSI_CLEAR_DPHY_ERRORS_0_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_DPHY_ERRORS_0_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_15_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_15_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_15_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_15_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_14_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_14_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_14_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_14_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_13_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_13_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_13_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_13_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_12_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_12_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_12_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_12_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_11_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_11_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_11_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_11_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_10_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_10_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_10_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_10_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_9_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_9_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_9_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_9_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_8_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_8_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_8_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_8_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_7_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_7_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_7_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_7_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_6_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_6_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_6_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_6_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_5_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_5_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_5_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_5_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_4_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_4_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_4_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_4_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_3_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_3_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_3_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_3_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_2_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_2_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_2_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_2_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_1_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_1_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_1_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_1_0) + +#define __HAL_DSI_SET_ACK_WITH_ERR_0_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_0_0) + +#define __HAL_DSI_CLEAR_ACK_WITH_ERR_0_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE0, INT_FORCE0_ACK_WITH_ERR_0_0) + +/********* Register BitField Details: INT_FORCE1 BASE+0x00DC *********/ +#define __HAL_DSI_SET_GEN_PLD_RECEV_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_RECEV_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_RECEV_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_RECEV_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_RD_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_RD_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_RD_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_RD_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_SEND_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_SEND_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_SEND_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_SEND_ERR_0) + +#define __HAL_DSI_SET_GEN_PLD_WR_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_PLD_WR_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_PLD_WR_ERR_0) + +#define __HAL_DSI_SET_GEN_CMD_WR_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_CMD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_GEN_CMD_WR_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_GEN_CMD_WR_ERR_0) + +#define __HAL_DSI_SET_DPI_PLD_WR_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_DPI_PLD_WR_ERR_0) + +#define __HAL_DSI_CLEAR_DPI_PLD_WR_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_DPI_PLD_WR_ERR_0) + +#define __HAL_DSI_SET_EOPT_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_EOTP_ERR_0) + +#define __HAL_DSI_CLEAR_EOPT_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_EOTP_ERR_0) + +#define __HAL_DSI_SET_PKT_SIZE_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_PKT_SIZE_ERR_0) + +#define __HAL_DSI_CLEAR_PKT_SIZE_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_PKT_SIZE_ERR_0) + +#define __HAL_DSI_SET_CRC_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_CRC_ERR_0) + +#define __HAL_DSI_CLEAR_CRC_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_CRC_ERR_0) + +#define __HAL_DSI_SET_ECC_MULTI_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_ECC_MULTI_ERR_0) + +#define __HAL_DSI_CLEAR_ECC_MULTI_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_ECC_MULTI_ERR_0) + +#define __HAL_DSI_SET_ECC_SINGLE_ERR_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_ECC_SINGLE_ERR_0) + +#define __HAL_DSI_CLEAR_ECC_SINGLE_ERR_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_ECC_SINGLE_ERR_0) + +#define __HAL_DSI_SET_TO_LP_RX_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_TO_LP_RX_0) + +#define __HAL_DSI_CLEAR_TO_LP_RX_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_TO_LP_RX_0) + +#define __HAL_DSI_SET_TO_HS_TX_FORCE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_TO_HS_TX_0) + +#define __HAL_DSI_CLEAR_TO_HS_TX_FORCE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->INT_FORCE1, INT_FORCE1_TO_HS_TX_0) + +/********* Register BitField Details: VID_SHADOW_CTRL BASE+0x0100 *********/ +#define __HAL_DSI_SET_VID_SHADOW_PIN_REQ(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_0) + +#define __HAL_DSI_CLEAR_VID_SHADOW_PIN_REQ(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_0) + +#define __HAL_DSI_SET_VID_SHADOW_REQ(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_REQ_0) + +#define __HAL_DSI_CLEAR_VID_SHADOW_REQ(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_REQ_0) + +#define __HAL_DSI_SET_VID_SHADOW_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_EN_0) + +#define __HAL_DSI_CLEAR_VID_SHADOW_EN(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->VID_SHADOW_CTRL, VID_SHADOW_CTRL_VID_SHADOW_EN_0) + +/********* Register BitField Details: DPI_VCID_ACT BASE+0x010C *********/ +#define __HAL_DSI_DPI_VCID_ACK(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DPI_VCID_ACT, ((~DPI_VCID_ACT_DPI_VCID_Msk) & (READ_REG((__HANDLE__)->Instance->DPI_VCID_ACT))) | (__VALUE__) << DPI_VCID_ACT_DPI_VCID_Pos) + + +/** + * @} + */ +/* 4. 导出宏定义 Exported Macros --------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_macros MIPI DSI 导出宏 Exported Macros + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 5. 导出函数申明 Exported Funcs --------------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_funcs MIPI DSI 导出函数申明 Exported Funcs + * @{ + */ + +unsigned int dsi_read_phy_clk(struct jz_dsi *dsi); + +void dsi_delay(uint32_t d); + +void set_bit_field(unsigned long *reg, int start, int end, unsigned long val); + +void set_bit_field_v(volatile unsigned long *reg, int start, int end, unsigned long val); + +unsigned long get_bit_field_v(volatile unsigned long *reg, int start, int end); + +unsigned int dsi_get_phy_status(struct jz_dsi *dsi); + +void dsi_set_bit(unsigned int reg, int start, int end, unsigned int val); + +int dsi_write_short_packet(struct jz_dsi *dsi, unsigned char vc, unsigned char packet_type, unsigned short cmd_data); + +int dsi_write_long_packet(struct jz_dsi *dsi, unsigned char vc, unsigned char packet_type, unsigned char *cmd_data, unsigned short word_count); + +int dsi_read_packet(struct jz_dsi *dsi, int bytes, unsigned char *rd_buf); + +void dsi_set_transfer_mode(struct jz_dsi *dsi, int mode); + +void dsi_set_cmd_mode(struct jz_dsi *dsi); + +void dsi_set_edpi_cmd_size(struct jz_dsi *dsi, unsigned short size); + +void dsi_set_power(struct jz_dsi *dsi, unsigned int power); + +void dsi_set_edpi_cmd_size(struct jz_dsi *dsi, unsigned short size); + +int jz_dsi_video_init(struct jz_dsi *dsi); + +int jz_dsi_set_clock(struct jz_dsi *dsi, unsigned int clk); + +void jz_dsi_dphy_init(struct jz_dsi *dsi); + +void jz_dsi_gen_init(struct jz_dsi *dsi); +void dump_dsi_reg(void ); +/** + * @} + */ +/* 6. 导出变量申明 (Exported Variables) --------------------------------- */ +/** + * @defgroup MIPI_DSI_exported_var MIPI DSI 导出变量申明 (Exported Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_types MIPI DSI 私有类型定义 (Private Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 8. 私有常量定义Private Constants ------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_constants MIPI DSI 私有常量定义Private Constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 9. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_macros MIPI DSI 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 10. 私有函数申明 (Private Funcs) ------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_funcs MIPI DSI 私有函数申明 (Private Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 11. 私有变量申明 Private Variables ----------------------------------- */ +/** + * @defgroup MIPI_DSI_private_var MIPI DSI 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X2600_LL_MIPI_DSI_H__ */ diff --git a/drivers/drivers-x2600/src/x2600_hal_lcd.c b/drivers/drivers-x2600/src/x2600_hal_lcd.c index 797f6377..2fef76b4 100644 --- a/drivers/drivers-x2600/src/x2600_hal_lcd.c +++ b/drivers/drivers-x2600/src/x2600_hal_lcd.c @@ -185,7 +185,7 @@ static void init_tft(LCD_HandleTypeDef *hlcd) __HAL_COLOR_EVEN(hlcd,pdata->tft->even_line_order); __HAL_COLOR_ODD(hlcd,pdata->tft->odd_line_order); - if(pdata->lcd_mode == TFT_24BITS) { + if(pdata->lcd_mode == TFT_24BITS || pdata->lcd_mode == TFT_MIPI) { if (pdata->out_format == OUT_FORMAT_RGB565) mode = 2; if (pdata->out_format == OUT_FORMAT_RGB666) @@ -476,6 +476,16 @@ static inline int is_slcd(struct lcd_data *pdata) return pdata->lcd_mode >= SLCD_6800; } +static inline int is_slcd_mipi(struct lcd_data *pdata) +{ + return pdata->lcd_mode == SLCD_MIPI; +} + +static inline int is_tft_mipi(struct lcd_data *pdata) +{ + return pdata->lcd_mode == TFT_MIPI; +} + static int lcdc_tft_pan_display(LCD_HandleTypeDef *hlcd, struct srdmadesc *frame) { WRITE_REG(hlcd->Instance->DC_SRD_CHAIN_ADDR, CPHYSADDR(frame)); @@ -519,17 +529,17 @@ static int lcdc_slcd_pan_display(LCD_HandleTypeDef *hlcd, struct srdmadesc *fram void HAL_PAN_DISPLAY(LCD_HandleTypeDef *hlcd, unsigned int frame_num) { - int ret; struct srdmadesc *frame; + struct lcd_data *pdata = hlcd->pdata; + int ret = 0; frame = hlcd->desc[frame_num]; // dump_rdma_desc_reg(hlcd); - if (!is_tft(hlcd->pdata)) - ret = lcdc_slcd_pan_display(hlcd, frame); - else + if (is_tft(pdata) || is_tft_mipi(pdata)) ret = lcdc_tft_pan_display(hlcd, frame); - + else + ret = lcdc_slcd_pan_display(hlcd, frame); } static void init_lcdc(LCD_HandleTypeDef *hlcd) @@ -575,15 +585,17 @@ static void init_lcdc(LCD_HandleTypeDef *hlcd) prom_printk("is_tft \n"); } - if (is_tft(pdata)){ + if (is_tft(pdata) || is_tft_mipi(pdata)){ init_tft(hlcd); prom_printk("tft mode \n"); } - if (is_slcd(pdata)){ + if (is_slcd(pdata) || is_slcd_mipi(pdata)){ init_slcd(hlcd); prom_printk("slcd mode \n"); } - + if (is_tft_mipi(pdata) || is_slcd_mipi(pdata)){ + jz_enable_mipi_dsi(); + } } static int slcd_pixclock_cycle(struct lcd_data *pdata) @@ -620,7 +632,7 @@ void auto_calculate_pixel_clock(struct lcd_data *pdata) if (!pdata->refresh) pdata->refresh = 40; - if (is_tft(pdata)) { + if (is_tft(pdata) || is_tft_mipi(pdata)) { if (!pdata->pixclock) pdata->pixclock = hpe * vpe * pdata->refresh; } @@ -649,12 +661,17 @@ void HAL_LCDC_INIT(LCD_HandleTypeDef *hlcd) prom_printk("slcd fmt error\n"); } - ret = init_lcd_gpio(pdata); - if(ret < 0) - prom_printk("init lcd gpio failed\n"); auto_calculate_pixel_clock(pdata); - + if (is_slcd_mipi(pdata) || is_tft_mipi(pdata)) { + int ret = jz_mipi_dsi_data_init(pdata); + if(ret < 0) + prom_printk("init dsi data error\n"); + }else { + ret = init_lcd_gpio(pdata); + if(ret < 0) + prom_printk("init lcd gpio failed\n"); + } } void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd) @@ -666,10 +683,18 @@ void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd) if (pdata->power_on) pdata->power_on(); + if (pdata->lcd_init) + pdata->lcd_init(); + if (is_slcd(pdata)){ process_slcd_data_table(hlcd, pdata->slcd->slcd_data_table, pdata->slcd->slcd_data_table_length); // __HAL_FMT_EN(hlcd); } + if (is_tft_mipi(pdata)) + jz_dsi_video_cfg(); + + if (is_slcd_mipi(pdata)) + jz_dsi_command_cfg(); hlcd->pdata->frame_status = state_clear; } @@ -679,8 +704,8 @@ void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer) int i; int format; for (i = 0; i < MAX_SRDMA_DESC_NUM; i++){ - if (hlcd->desc[i] == NULL) { - break; + if (hlcd->desc[i] == NULL){ + break; } switch (hlcd->pdata->fb_fmt) { case fb_fmt_RGB555: @@ -709,9 +734,7 @@ void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer) hlcd->desc[i]->stride = hlcd->pdata->xres; hlcd->desc[i]->FrameBufferAddr = CPHYSADDR(((unsigned long)buffer)); - //CPHYSADDR(((unsigned long)buffer) + format * i * hlcd->pdata->frame_mem); - Flush_Cache_AllAddr(); -// CleanDCache_by_Addr((unsigned long*)hlcd->desc[i], sizeof(struct srdmadesc)); + Flush_Cache_AllAddr(); prom_printk("==================== rdma desc =====================\n"); prom_printk("hlcd->desc[%d]->RdmaNextCfgAddr = 0x%x\n",i, hlcd->desc[i]->RdmaNextCfgAddr); prom_printk("hlcd->desc[%d]->FrameCtrl = 0x%x\n",i, hlcd->desc[i]->FrameCtrl); diff --git a/drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c b/drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c new file mode 100755 index 00000000..9d9bfad0 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c @@ -0,0 +1,395 @@ +/** + * @file x2600_ll_intc.c + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + [!!!!删除此内容，添加针对模块的使用方法说明，例如： 配置，启动/停止，状态，重点提醒等等.!!!!] + @endverbatim + */ + +/* 1.头文件 (Includes)------------------------------------------------ */ +//#include "x2600_hal.h" +#include "x2600_ll_mipi_dsi.h" +#include "x2600_hal_mipi_dsi.h" +#include +#include +/** @addtogroup g_X2600_INTC_LL_Driver + * @{ + */ + +/* 2.私有常量定义Private Constants -------------------------------------- */ +/** + * @addtogroup INTC_private_constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @addtogroup INTC_private_types + * @{ + */ + +/** + * @} + */ +/* 4. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @addtogroup INTC_private_macros + * @{ + */ + +#define mipi_error_if(_cond) \ + do { \ + if (_cond) { \ + prom_printk("jz_mipi_dsi: failed to check: %s\n", #_cond); \ + ret = -1; \ + return ret; \ + } \ + } while (0) + +/** + * @} + */ +/* 5. 私有变量申明 Private Variables ------------------------------------ */ +/** + * @addtogroup INTC_private_var + * @{ + */ +static struct jz_dsi *jz_dsi; + +/**> + * @} + */ +/* 6. 私有函数申明 (Private Funcs) -------------------------------------- */ +/** + * @addtogroup INTC_private_funcs + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7. 私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup INTC_private_funcs_impl INTC 私有函数实现 + * @{ + */ + +static inline int mipi_bpp_per_pixel(struct lcd_data *data) +{ + switch (data->mipi->color_coding) { + case COLOR_CODE_16BIT_CONFIG1: + case COLOR_CODE_16BIT_CONFIG2: + case COLOR_CODE_16BIT_CONFIG3: + return 16; + + case COLOR_CODE_18BIT_CONFIG1: + case COLOR_CODE_18BIT_CONFIG2: + return 18; + + case COLOR_CODE_24BIT: + return 24; + default: + break; + } + + prom_printk("no support this color coding\n"); + return 0; +} + +static void calculate_video_mode_chunck(void) +{ + //burst mode + if (jz_dsi->video_config.video_mode == VIDEO_BURST_WITH_SYNC_PULSES) { + jz_dsi->video_config.null_size = 0; + jz_dsi->video_config.chunk = 0; + jz_dsi->video_config.video_size = jz_dsi->video_config.h_active_pixels; + + if((jz_dsi->dsi_config.color_coding == COLOR_CODE_18BIT_CONFIG1 || + jz_dsi->dsi_config.color_coding == COLOR_CODE_18BIT_CONFIG2) && + jz_dsi->dsi_config.color_type_18bit != LOOSELY18) { + + jz_dsi->video_config.video_size = ALIGN(jz_dsi->video_config.video_size, 4); + } + + return; + } + + //not burst mode + +} + +/** + * @} + */ +/* 8. 导出函数实现------------------------------------------------------- */ +/** + * @defgroup INTC_exported_funcs_impl INTC 导出函数实现 + * @{ + */ + +int dsi_write_cmd(struct dsi_cmd_packet *cmd_data) +{ + unsigned int packet_type; + unsigned short word_count = 0; + unsigned int ret; + /*word count*/ + packet_type = cmd_data->packet_type; + word_count = ((cmd_data->cmd1_or_wc_msb << 8 ) | cmd_data->cmd0_or_wc_lsb); + + if (packet_type == 0x39) { + ret = dsi_write_long_packet(jz_dsi, jz_dsi->video_config.virtual_channel, packet_type, cmd_data->cmd_data, word_count); + if (ret < 0) + return -1; + } + + if (packet_type == 0x05 || packet_type == 0x15 || packet_type == 0x23) { + ret = dsi_write_short_packet(jz_dsi, jz_dsi->video_config.virtual_channel, packet_type, word_count); + if (ret < 0) + return -1; + } + + dsi_delay(30000); + return 0; +} + +int dsi_read_cmd(struct dsi_cmd_packet *cmd_data, int bytes, unsigned char *rd_buf) +{ + unsigned int packet_type; + unsigned short short_data = 0; + unsigned int ret; + + __HAL_DSI_GEN_VCID_RX(jz_dsi, jz_dsi->video_config.virtual_channel); + + packet_type = cmd_data->packet_type; + short_data = ((cmd_data->cmd1_or_wc_msb << 8 ) | cmd_data->cmd0_or_wc_lsb); + + if (packet_type != 0x04 && packet_type != 0x14 && packet_type != 0x24 && packet_type != 0x06) { + prom_printk("dsi_read :not suport this packet_type = %x\n", packet_type); + return -1; + } + + ret = dsi_write_short_packet(jz_dsi, jz_dsi->video_config.virtual_channel, packet_type, short_data); + if (ret < 0) + return -1; + + ret = dsi_read_packet(jz_dsi, bytes, rd_buf); + if (ret < 0) + return -1; + + return 0; +} + +int jz_mipi_dsi_data_init(struct lcd_data *lcd_data) +{ + int ret; +prom_printk("dsi phy address = 0x%p\n", jz_dsi->DPHY_TX_Instance); + + int hs = lcd_data->hsync_len; + int hbp = lcd_data->left_margin; + int hfp = lcd_data->right_margin; + int vs = lcd_data->vsync_len; + int vbp = lcd_data->upper_margin; + int vfp = lcd_data->lower_margin; + + int v_total_lines; + + jz_dsi->Instance = MIPI_DSI_Instance; + jz_dsi->DPHY_TX_Instance = MIPI_DPHY_TX_Instance; + + jz_dsi->dsi_config.color_coding = lcd_data->mipi->color_coding; + jz_dsi->dsi_config.num_of_lanes = lcd_data->mipi->num_of_lanes; + jz_dsi->dsi_config.color_mode_polarity = lcd_data->mipi->color_mode_polarity; + jz_dsi->dsi_config.shut_down_polarity = lcd_data->mipi->shut_down_polarity; + jz_dsi->dsi_config.max_bta_cycles = lcd_data->mipi->max_bta_cycles; + jz_dsi->dsi_config.max_hs_to_lp_cycles = lcd_data->mipi->max_hs_to_lp_cycles; + jz_dsi->dsi_config.max_lp_to_hs_cycles = lcd_data->mipi->max_lp_to_hs_cycles; + jz_dsi->dsi_config.color_type_18bit = lcd_data->mipi->color_type_18bit; + + jz_dsi->video_config.virtual_channel = lcd_data->mipi->virtual_channel; + jz_dsi->video_config.video_mode = lcd_data->mipi->video_mode; + jz_dsi->video_config.data_en_polarity = lcd_data->mipi->data_en_polarity; + + jz_dsi->video_config.h_active_pixels = lcd_data->xres; + jz_dsi->video_config.hs = hs; + jz_dsi->video_config.hbp = hbp; + jz_dsi->video_config.h_total_pixels = hs + hbp + lcd_data->xres + hfp; + + jz_dsi->video_config.vs = vs; + jz_dsi->video_config.vbp = vbp; + jz_dsi->video_config.v_active_lines = lcd_data->yres; + jz_dsi->video_config.vfp = vfp; + + v_total_lines = vs + vbp + lcd_data->yres + vfp; + jz_dsi->video_config.h_polarity = lcd_data->mipi->hsync_active_level; + jz_dsi->video_config.v_polarity = lcd_data->mipi->vsync_active_level; + jz_dsi->video_config.pixel_clock = lcd_data->pixclock / 1000; + jz_dsi->video_config.bpp_info = mipi_bpp_per_pixel(lcd_data); + + + jz_dsi->video_config.byte_clock = jz_dsi->video_config.h_total_pixels * v_total_lines * lcd_data->refresh * 24 / jz_dsi->dsi_config.num_of_lanes / 8 / 1000 * 6 / 5; + + jz_dsi->real_mipiclk = jz_dsi->video_config.byte_clock * 8 * 1000; + + if (lcd_data->mipi->slcd_te_pin_mode != TE_NOT_EANBLE) + jz_dsi->dsi_config.te_mipi_en = 1; + + calculate_video_mode_chunck(); + + return 0; +} + +void jz_dsi_command_cfg(void) +{ + dsi_set_edpi_cmd_size(jz_dsi, 1024); + __HAL_DSI_SET_PHY_TXREQUESTCLKHS(jz_dsi); + __HAL_DSI_SET_AUTO_CLKLANE_CTRL(jz_dsi); + + // high speed + dsi_set_transfer_mode(jz_dsi, 0); + + __HAL_DSI_FRAME_BTA_ACK_DIS(jz_dsi); + __HAL_DSI_BTA_DIS(jz_dsi); + + if (jz_dsi->dsi_config.te_mipi_en) + __HAL_DSI_CMD_MODE(jz_dsi); + else + __HAL_DSI_VIDEO_MODE(jz_dsi); + + dsi_set_cmd_mode(jz_dsi); +} + +void jz_dsi_video_cfg(void) +{ + dsi_set_power(jz_dsi, 1); + jz_dsi_video_init(jz_dsi); + dsi_set_power(jz_dsi, 1); +} + +void jz_enable_mipi_dsi(void) +{ + int st_mask = 0; + int retry = 5; + jz_dsi_dphy_init(jz_dsi); + + //LP mode + dsi_set_transfer_mode(jz_dsi, 1); + dsi_set_cmd_mode(jz_dsi); + dsi_set_edpi_cmd_size(jz_dsi, 0x6); + + jz_dsi_set_clock(jz_dsi, jz_dsi->video_config.byte_clock); + + dsi_set_power(jz_dsi, 0); + dsi_set_power(jz_dsi, 1); + + jz_dsi_gen_init(jz_dsi); + + dsi_set_power(jz_dsi, 0); + dsi_set_power(jz_dsi, 1); + + if(jz_dsi->dsi_config.num_of_lanes == 2) + st_mask = 0x95; + else + st_mask = 0x15; + + HAL_Delay(10); + + while((dsi_get_phy_status(jz_dsi) & st_mask) != st_mask && --retry) + prom_printk("phy status = %08x\n", dsi_get_phy_status(jz_dsi)); + + if(!retry) + prom_printk("wait for phy config failed!\n"); +} + +void jz_disable_mipi_dsi(void) +{ + __HAL_DSI_CLEAR_PHY_ENABLECLK(jz_dsi); + __HAL_DSI_CLEAR_PHY_SHUTDOWNZ(jz_dsi); + dsi_set_power(jz_dsi, 0); +} + +void dump_dsi_reg(void) +{ + printf("===========>dump dsi reg\n"); + printf("VERSION------------:%08x\n", READ_REG(jz_dsi->Instance->VERSION)); + printf("PWR_UP:------------:%08x\n", READ_REG(jz_dsi->Instance->PWR_UP)); + printf("CLKMGR_CFG---------:%08x\n", READ_REG(jz_dsi->Instance->CLKMGR_CFG)); + printf("DPI_VCID-----------:%08x\n", READ_REG(jz_dsi->Instance->DPI_VCID)); + printf("DPI_COLOR_CODING---:%08x\n", READ_REG(jz_dsi->Instance->DPI_COLOR_CODING)); + printf("DPI_CFG_POL--------:%08x\n", READ_REG(jz_dsi->Instance->DPI_CFG_POL)); + printf("DPI_LP_CMD_TIM-----:%08x\n", READ_REG(jz_dsi->Instance->DPI_LP_CMD_TIM)); + printf("PCKHDL_CFG---------:%08x\n", READ_REG(jz_dsi->Instance->PCKHDL_CFG)); + printf("GEN_VCID-----------:%08x\n", READ_REG(jz_dsi->Instance->GEN_VCID)); + printf("MODE_CFG-----------:%08x\n", READ_REG(jz_dsi->Instance->MODE_CFG)); + printf("VID_MODE_CFG-------:%08x\n", READ_REG(jz_dsi->Instance->VID_MODE_CFG)); + printf("VID_PKT_SIZE-------:%08x\n", READ_REG(jz_dsi->Instance->VID_PKT_SIZE)); + printf("VID_NUM_CHUNKS-----:%08x\n", READ_REG(jz_dsi->Instance->VID_NUM_CHUNKS)); + printf("VID_NULL_SIZE------:%08x\n", READ_REG(jz_dsi->Instance->VID_NULL_SIZE)); + printf("VID_HSA_TIME-------:%08x\n", READ_REG(jz_dsi->Instance->VID_HSA_TIME)); + printf("VID_HBP_TIME-------:%08x\n", READ_REG(jz_dsi->Instance->VID_HBP_TIME)); + printf("VID_HLINE_TIME-----:%08x\n", READ_REG(jz_dsi->Instance->VID_HLINE_TIME)); + printf("VID_VSA_LINES------:%08x\n", READ_REG(jz_dsi->Instance->VID_VSA_LINES)); + printf("VID_VBP_LINES------:%08x\n", READ_REG(jz_dsi->Instance->VID_VBP_LINES)); + printf("VID_VFP_LINES------:%08x\n", READ_REG(jz_dsi->Instance->VID_VFP_LINES)); + printf("VID_VACTIVE_LINES--:%08x\n", READ_REG(jz_dsi->Instance->VID_VACTIVE_LINES)); + printf("EDPI_CMD_SIZE------:%08x\n", READ_REG(jz_dsi->Instance->EDPI_CMD_SIZE)); + printf("CMD_MODE_CFG-------:%08x\n", READ_REG(jz_dsi->Instance->CMD_MODE_CFG)); + printf("GEN_HDR------------:%08x\n", READ_REG(jz_dsi->Instance->GEN_HDR)); + printf("GEN_PLD_DATA-------:%08x\n", READ_REG(jz_dsi->Instance->GEN_PLD_DATA)); + printf("CMD_PKT_STATUS-----:%08x\n", READ_REG(jz_dsi->Instance->CMD_PKT_STATUS)); + printf("TO_CNT_CFG---------:%08x\n", READ_REG(jz_dsi->Instance->TO_CNT_CFG)); + printf("HS_RD_TO_CNT-------:%08x\n", READ_REG(jz_dsi->Instance->HS_RD_TO_CNT)); + printf("LP_RD_TO_CNT-------:%08x\n", READ_REG(jz_dsi->Instance->LP_RD_TO_CNT)); + printf("HS_WR_TO_CNT-------:%08x\n", READ_REG(jz_dsi->Instance->HS_WR_TO_CNT)); + printf("LP_WR_TO_CNT-------:%08x\n", READ_REG(jz_dsi->Instance->LP_WR_TO_CNT)); + printf("BTA_TO_CNT---------:%08x\n", READ_REG(jz_dsi->Instance->BTA_TO_CNT)); + printf("SDF_3D-------------:%08x\n", READ_REG(jz_dsi->Instance->SDF_3D)); + printf("LPCLK_CTRL---------:%08x\n", READ_REG(jz_dsi->Instance->LPCLK_CTRL)); + printf("PHY_TMR_LPCLK_CFG--:%08x\n", READ_REG(jz_dsi->Instance->PHY_TMR_LPCLK_CFG)); + printf("PHY_TMR_CFG--------:%08x\n", READ_REG(jz_dsi->Instance->PHY_TMR_CFG)); + printf("PHY_RSTZ-----------:%08x\n", READ_REG(jz_dsi->Instance->PHY_RSTZ)); + printf("PHY_IF_CFG---------:%08x\n", READ_REG(jz_dsi->Instance->PHY_IF_CFG)); + printf("PHY_ULPS_CTRL------:%08x\n", READ_REG(jz_dsi->Instance->PHY_ULPS_CTRL)); + printf("PHY_TX_TRIGGERS----:%08x\n", READ_REG(jz_dsi->Instance->PHY_TX_TRIGGERS)); + printf("PHY_STATUS---------:%08x\n", READ_REG(jz_dsi->Instance->PHY_STATUS)); + printf("PHY_TST_CTRL0------:%08x\n", READ_REG(jz_dsi->Instance->PHY_TST_CTRL0)); + printf("PHY_TST_CTRL1------:%08x\n", READ_REG(jz_dsi->Instance->PHY_TST_CTRL1)); + printf("INT_ST0------------:%08x\n", READ_REG(jz_dsi->Instance->INT_ST0)); + printf("INT_ST1------------:%08x\n", READ_REG(jz_dsi->Instance->INT_ST1)); + printf("INT_MSK0-----------:%08x\n", READ_REG(jz_dsi->Instance->INT_MSK0)); + printf("INT_MSK1-----------:%08x\n", READ_REG(jz_dsi->Instance->INT_MSK1)); + printf("INT_FORCE0---------:%08x\n", READ_REG(jz_dsi->Instance->INT_FORCE0)); + printf("INT_FORCE1---------:%08x\n", READ_REG(jz_dsi->Instance->INT_FORCE1)); + printf("VID_SHADOW_CTRL----:%08x\n", READ_REG(jz_dsi->Instance->VID_SHADOW_CTRL)); + printf("DPI_VCID_ACT-------:%08x\n", READ_REG(jz_dsi->Instance->DPI_VCID_ACT)); + printf("===================================================\n"); + printf("PLL_CLK_SEL_R------:%08x\n", dsi_read_phy_clk(jz_dsi)); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c b/drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c new file mode 100755 index 00000000..a65d1c40 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c @@ -0,0 +1,615 @@ +/** + * @file x2600_ll_intc.c + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + [!!!!删除此内容，添加针对模块的使用方法说明，例如： 配置，启动/停止，状态，重点提醒等等.!!!!] + @endverbatim + */ + +/* 1.头文件 (Includes)------------------------------------------------ */ +#include +/** @addtogroup g_X2600_INTC_LL_Driver + * @{ + */ + +/* 2.私有常量定义Private Constants -------------------------------------- */ +/** + * @addtogroup INTC_private_constants + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @addtogroup INTC_private_types + * @{ + */ + +/** + * @} + */ +/* 4. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @addtogroup INTC_private_macros + * @{ + */ +//#ifndef ARRAY_SIZE(x) +#define ARRAY_SIZE(x) (int)( sizeof(x) / sizeof(x)[0] ) +//#endif +/** + * @} + */ +/* 5. 私有变量申明 Private Variables ------------------------------------ */ +/** + * @addtogroup INTC_private_var + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6. 私有函数申明 (Private Funcs) -------------------------------------- */ +/** + * @addtogroup INTC_private_funcs + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7. 私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup MIPI_DSI_private_funcs_impl INTC 私有函数实现 + * @{ + */ + +/* + * 位字段控制函数 + */ +#if 0 +static void dsi_write_phy_clk(struct jz_dsi *dsi, unsigned int val) +{ + WRITE_REG(dsi->DPHY_TX_Instance->PLL_CLK_SEL_R, val); +} +#endif +unsigned int dsi_read_phy_clk(struct jz_dsi *dsi) +{ + return READ_REG(dsi->DPHY_TX_Instance->PLL_CLK_SEL_R); +} + +static int dsi_set_dphy_hs2lp_time(struct jz_dsi *dsi, unsigned char time) +{ + __HAL_DSI_PHY_HS2LP_TIME(dsi, time); + + return 0; +} + +static int dsi_set_dphy_lp2hs_time(struct jz_dsi *dsi, unsigned char time) +{ + __HAL_DSI_PHY_LP2HS_TIME(dsi, time); + + return 0; + +} + +static void dsi_set_dphy_bta_time(struct jz_dsi *dsi, unsigned short time) +{ + __HAL_DSI_PHY_MAX_RD_TIME(dsi, time); +} + +static int dsi_get_cmd_full(struct jz_dsi *dsi) +{ + return READ_BIT(dsi->Instance->CMD_PKT_STATUS, CMD_PKT_STATUS_GEN_CMD_FULL); +} + +static int dsi_get_pld_w_full(struct jz_dsi *dsi) +{ + return READ_BIT(dsi->Instance->CMD_PKT_STATUS, CMD_PKT_STATUS_GEN_PLD_W_FULL); +} + +static int dsi_get_rd_cmd_busy(struct jz_dsi *dsi) +{ + return READ_BIT(dsi->Instance->CMD_PKT_STATUS, CMD_PKT_STATUS_GEN_RD_CMD_BUSY); +} + +static int dsi_get_rd_empty(struct jz_dsi *dsi) +{ + return READ_BIT(dsi->Instance->CMD_PKT_STATUS, CMD_PKT_STATUS_GEN_PLD_R_EMPTY); +} + +static int dsi_wait_pld_w_not_full(struct jz_dsi *dsi, int count) +{ + int status; + status = dsi_get_pld_w_full(dsi); + + while (count-- && status) { + status = dsi_get_pld_w_full(dsi); + } + + return status; +} + +static int dsi_wait_cmd_not_full(struct jz_dsi *dsi, int count) +{ + int status; + status = dsi_get_cmd_full(dsi); + + while (count-- && status) { + status = dsi_get_cmd_full(dsi); + } + + return status; +} + +static int dsi_wait_rd_cmd_busy(struct jz_dsi *dsi, int count) +{ + int status; + status = dsi_get_rd_cmd_busy(dsi); + + while (count-- && status) { + status = dsi_get_rd_cmd_busy(dsi); + } + + return status; +} + +static int dsi_wait_rd_fifo_empty(struct jz_dsi *dsi, int count) +{ + int status; + status = dsi_get_rd_empty(dsi); + + while (count-- && status) { + status = dsi_get_rd_empty(dsi); + } + + return status; +} + +static void dsi_set_video_mode(struct jz_dsi *dsi) +{ + __HAL_DSI_VIDEO_MODE(dsi); +} + +static unsigned char calc_inno_dphy_fbdiv(struct jz_dsi* dsi) +{ + unsigned int real_mipi_clk = 0; + real_mipi_clk = dsi->real_mipiclk / 1000000; // hz --- Mhz + unsigned char fbdiv = 0; + unsigned int prediv = 1; //Fix value + unsigned int ref = 12; //12Mhz fix value + fbdiv = (real_mipi_clk * 2) / (ref / prediv); + + prom_printk("%s real_mipi_clk = %d >>>>>>>>>>>>>>>>>>>>>>>>>>> \n",__func__,real_mipi_clk); + return fbdiv; +} + +static int jz_dsih_dphy_configure_x2600(struct jz_dsi *dsi){ + unsigned int temp = 0xffffffff; + prom_printk("dsi phy address = 0x%p\n", dsi->DPHY_TX_Instance); + //S1 set prediv + temp = READ_REG(dsi->DPHY_TX_Instance->ANA_REG03); + temp &= ~0xff; + temp |= 0x01; + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG03, temp); + prom_printk("ANA_REG03 : 0x%x\n",dsi->DPHY_TX_Instance->ANA_REG03); + + //S2 set fbdiv + temp = READ_REG(dsi->DPHY_TX_Instance->ANA_REG04); + temp &= ~0xff; + temp |= calc_inno_dphy_fbdiv(dsi); //fbdiv + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG04, temp); + prom_printk("ANA_REG04 : 0x%x\n",dsi->DPHY_TX_Instance->ANA_REG04); + + //S3 PLL LDO + temp = READ_REG(dsi->DPHY_TX_Instance->ANA_REG01); + temp &= ~0xff; + temp |= 0xE4; + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG01, temp); + prom_printk("ANA_REG01 : 0x%x\n",dsi->DPHY_TX_Instance->ANA_REG01); + + //S4 set lane num + temp = READ_REG(dsi->DPHY_TX_Instance->ANA_REG00); + temp &= ~0xff; + if (dsi->dsi_config.num_of_lanes == 4) { + temp |= 0x7d; + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG00, temp); + } else { + temp |= 0x4d; + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG00, temp); + } + prom_printk("ANA_REG00 : 0x%x\n",dsi->DPHY_TX_Instance->ANA_REG00); + + //S5 reset analog + temp = READ_REG(dsi->DPHY_TX_Instance->ANA_REG01); + temp &= ~0xff; + temp |= 0xe0; + WRITE_REG(dsi->DPHY_TX_Instance->ANA_REG01, temp); + prom_printk("ANA_REG01 : 0x%x\n",dsi->DPHY_TX_Instance->ANA_REG01); + + // S6 + // msleep(20); + HAL_Delay(20); + //S7 reset digital + temp = READ_REG(dsi->DPHY_TX_Instance->DIG_REG00); + temp &= ~0xff; + temp |= 0x1e; + WRITE_REG(dsi->DPHY_TX_Instance->DIG_REG00, temp); + prom_printk("DIG_REG00 : 0x%x\n",dsi->DPHY_TX_Instance->DIG_REG00); + HAL_Delay(5); + // S8 digital normal + temp = READ_REG(dsi->DPHY_TX_Instance->DIG_REG00); + temp &= ~0xff; + temp |= 0x1f; + WRITE_REG(dsi->DPHY_TX_Instance->DIG_REG00, temp); + prom_printk("DIG_REG00 : 0x%x\n",dsi->DPHY_TX_Instance->DIG_REG00); + + // S9 Func Mode select + temp = READ_REG(dsi->DPHY_TX_Instance->LVDS_REG03); + temp &= ~0xff; + temp |= 0x01; + WRITE_REG(dsi->DPHY_TX_Instance->LVDS_REG03, temp); + prom_printk("LVDS_REG03 : 0x%x\n",dsi->DPHY_TX_Instance->LVDS_REG03); + + // S9-1 LPDT LANE0 PPI SYNC may not need + temp = READ_REG(dsi->DPHY_TX_Instance->LANG_REG0C); + temp |= 0x4; + WRITE_REG(dsi->DPHY_TX_Instance->LANG_REG0C, temp); + prom_printk("LANG_REG0C : 0x%x\n",dsi->DPHY_TX_Instance->LANG_REG0C); + + return 0; +} +static int dsi_write_gen_data(struct jz_dsi *dsi, unsigned int data) +{ + if (dsi_wait_pld_w_not_full(dsi, 500)) { + printf("pld_w_fifo full!\n"); + return -1; + } + + WRITE_REG(dsi->Instance->GEN_PLD_DATA, data); + + return 0; +} + +static void jz_dsi_dpi_config(struct jz_dsi *dsi) +{ + unsigned int hs_timeout; + int counter; + struct video_config *video_config = &dsi->video_config; + + unsigned int temp; + + temp = video_config->byte_clock * 1000 / (video_config->pixel_clock); + + __HAL_DSI_VID_HBP_TIME(dsi, video_config->hbp * temp / 1000); + __HAL_DSI_VID_HSA_TIME(dsi, video_config->hs * temp / 1000); + __HAL_DSI_VID_HLINE_TIME(dsi, video_config->h_total_pixels * temp / 1000); + + __HAL_DSI_VID_VBP_LINES(dsi, video_config->vbp); + __HAL_DSI_VID_VFP_LINES(dsi, video_config->vfp); + __HAL_DSI_VID_VSA_LINES(dsi, video_config->vs); + __HAL_DSI_VID_VACTIVE_LINES(dsi, video_config->v_active_lines); + + if(video_config->data_en_polarity) + __HAL_DSI_DATAEN_ACTIVE_HIGH(dsi); + else + __HAL_DSI_DATAEN_ACTIVE_LOW(dsi); + + __HAL_DSI_VSYNC_ACTIVE_LOW(dsi); + __HAL_DSI_HSYNC_ACTIVE_LOW(dsi); + + dsi_delay(10000); + + hs_timeout = (video_config->h_total_pixels * video_config->v_active_lines) \ + + (2 * (video_config->bpp_info * 100 / 8) / 100); + + for (counter = 0x80; (counter < hs_timeout) && (counter > 2); counter--) { + if ((hs_timeout % counter) == 0) { + __HAL_DSI_TO_CLK_DIV(dsi, counter); + __HAL_DSI_HSTX_TO_CNT(dsi, (unsigned short)(hs_timeout / counter)); + __HAL_DSI_LPRX_TO_CNT(dsi, (unsigned short)(hs_timeout / counter)); + break; + } + } + +} + +/** + * @} + */ +/* 8. 导出函数实现------------------------------------------------------- */ +/** + * @defgroup INTC_exported_funcs_impl INTC 导出函数实现 + * @{ + */ +/* 延时函数 */ +void dsi_delay(uint32_t d) +{ + while(d--){ + asm volatile("nop\n\t"); + } +} + +unsigned int dsi_get_phy_status(struct jz_dsi *dsi) +{ + int val; + val = READ_REG(dsi->Instance->PHY_STATUS); + return val; +} + +void dsi_set_power(struct jz_dsi *dsi, unsigned int power) +{ + if(power) + __HAL_DSI_PWR_UP(dsi); + else + __HAL_DSI_RESET(dsi); +} + +void dsi_set_transfer_mode(struct jz_dsi *dsi, int mode)//high speed: 0 / low power: 1 +{ + if(mode){/* low power */ + __HAL_DSI_MAX_RD_PKT_SIZE_LP(dsi); + __HAL_DSI_DCS_SW_0P_TX_LP(dsi); + __HAL_DSI_DCS_SW_1P_TX_LP(dsi); + __HAL_DSI_DCS_SR_0P_TX_LP(dsi); + __HAL_DSI_DCS_LW_TX_LP(dsi); + + __HAL_DSI_GEN_SW_0P_TX_LP(dsi); + __HAL_DSI_GEN_SW_1P_TX_LP(dsi); + __HAL_DSI_GEN_SW_2P_TX_LP(dsi); + __HAL_DSI_GEN_LW_TX_LP(dsi); + __HAL_DSI_GEN_SR_0P_TX_LP(dsi); + __HAL_DSI_GEN_SR_1P_TX_LP(dsi); + __HAL_DSI_GEN_SR_2P_TX_LP(dsi); + }else{ + __HAL_DSI_MAX_RD_PKT_SIZE_HS(dsi); + __HAL_DSI_DCS_SW_0P_TX_HS(dsi); + __HAL_DSI_DCS_SW_1P_TX_HS(dsi); + __HAL_DSI_DCS_SR_0P_TX_HS(dsi); + __HAL_DSI_DCS_LW_TX_HS(dsi); + + __HAL_DSI_GEN_SW_0P_TX_HS(dsi); + __HAL_DSI_GEN_SW_1P_TX_HS(dsi); + __HAL_DSI_GEN_SW_2P_TX_HS(dsi); + __HAL_DSI_GEN_LW_TX_HS(dsi); + __HAL_DSI_GEN_SR_0P_TX_HS(dsi); + __HAL_DSI_GEN_SR_1P_TX_HS(dsi); + __HAL_DSI_GEN_SR_2P_TX_HS(dsi); + } +} + +void dsi_set_cmd_mode(struct jz_dsi *dsi) +{ + __HAL_DSI_CMD_MODE(dsi); +} + +void dsi_set_edpi_cmd_size(struct jz_dsi *dsi, unsigned short size) +{ + __HAL_DSI_EDPI_CMD_SIZE(dsi, size); +} + +int jz_dsi_set_clock(struct jz_dsi *dsi, unsigned int clk) +{ + int ret; + ret = jz_dsih_dphy_configure_x2600(dsi); + if (ret < 0) { + printf("set dphy clock error!!\n"); + return -1; + } + + __HAL_DSI_PHY_STOP_WAIT_TIME(dsi, 0x1C); + + __HAL_DSI_SET_PHY_ENABLECLK(dsi); + __HAL_DSI_SET_PHY_SHUTDOWNZ(dsi); + __HAL_DSI_SET_PHY_RSTZ(dsi); + + __HAL_DSI_TX_ESC_CLK_DIV(dsi, 7); + + return 0; +} + +void jz_dsi_dphy_init(struct jz_dsi *dsi) +{ + struct dsi_config * dsi_config = &dsi->dsi_config; + + __HAL_DSI_CLEAR_PHY_RSTZ(dsi); + __HAL_DSI_PHY_STOP_WAIT_TIME(dsi, 0x1C); + __HAL_DSI_N_LANES(dsi, dsi_config->num_of_lanes - 1); + __HAL_DSI_SET_PHY_ENABLECLK(dsi); + __HAL_DSI_SET_PHY_SHUTDOWNZ(dsi); + __HAL_DSI_SET_PHY_RSTZ(dsi); +} + +void jz_dsi_gen_init(struct jz_dsi *dsi) +{ + struct dsi_config *dsi_config = &dsi->dsi_config; + + if(dsi_config->color_mode_polarity) + __HAL_DSI_COLORMODE_ACTIVE_HIGH(dsi); + else + __HAL_DSI_COLORMODE_ACTIVE_LOW(dsi); + + if(dsi_config->shut_down_polarity) + __HAL_DSI_SHUTDOWN_ACTIVE_HIGH(dsi); + else + __HAL_DSI_SHUTDOWN_ACTIVE_LOW(dsi); + + dsi_set_dphy_hs2lp_time(dsi, dsi_config->max_hs_to_lp_cycles); + dsi_set_dphy_lp2hs_time(dsi, dsi_config->max_lp_to_hs_cycles); + dsi_set_dphy_bta_time(dsi, dsi_config->max_bta_cycles); + + __HAL_DSI_GEN_VCID_RX(dsi, 0); + + __HAL_DSI_EOTP_RX_DIS(dsi); + __HAL_DSI_EOTP_TX_DIS(dsi); + __HAL_DSI_BTA_DIS(dsi); + __HAL_DSI_ECC_RX_DIS(dsi); + __HAL_DSI_CRC_RX_DIS(dsi); + __HAL_DSI_DPI_COLOR_CODING(dsi, dsi_config->color_coding); + if(dsi_config->color_type_18bit) + __HAL_DSI_LOSE18_EN(dsi); + else + __HAL_DSI_LOSE18_DIS(dsi); + +} + +int dsi_write_short_packet(struct jz_dsi *dsi, unsigned char vc, unsigned char packet_type, unsigned short cmd_data) +{ + if (dsi_wait_cmd_not_full(dsi, 10*1000)) { + printf("cmd fifo full!\n"); + return -1; + } + + unsigned char data[2]; + data[0] = cmd_data; + data[1] = cmd_data >> 8; + + unsigned long gen_hdr = 0; + gen_hdr = (packet_type << GEN_HDR_GEN_DT_Pos) | (vc << GEN_HDR_GEN_VC_Pos) | + (data[0] << GEN_HDR_GEN_WC_LSBYTE_Pos) | (data[1] << GEN_HDR_GEN_WC_MSBYTE_Pos); + + WRITE_REG(dsi->Instance->GEN_HDR, gen_hdr); + HAL_Delay(2); + return 0; + +} + +int dsi_write_long_packet(struct jz_dsi *dsi, unsigned char vc, unsigned char packet_type, unsigned char *cmd_data, unsigned short word_count) +{ + int ret; + int i; + + unsigned int gen_pld_data = 0; + for (i = 0; i < word_count; i++) { + gen_pld_data |= cmd_data[i] << (i % 4) * 8; + if ((i + 1) % 4 == 0 && i != 0) { + ret = dsi_write_gen_data(dsi, gen_pld_data); + if (ret < 0) + return -1; + + gen_pld_data = 0; + } + } + + if (word_count % 4 != 0) { + ret = dsi_write_gen_data(dsi, gen_pld_data); + if (ret < 0) + return -1; + } + + ret = dsi_write_short_packet(dsi, vc, packet_type, word_count); + if (ret < 0) + return -1; + + + return 0; +} + +int dsi_read_packet(struct jz_dsi *dsi, int bytes, unsigned char *rd_buf) +{ + int i; + int off = 0; + __HAL_DSI_CMD_MODE(dsi); + __HAL_DSI_BTA_EN(dsi); + __HAL_DSI_GEN_VCID_RX(dsi,1); + if (dsi_wait_rd_cmd_busy(dsi, 10*1000)) { + printf("read cmd busy!\n"); + return -1; + } + + if (dsi_wait_rd_fifo_empty(dsi, 10*1000)) { + printf("read fifo is empty!\n"); + return -1; + } + + for (i = 0; i < bytes; i++) { + rd_buf[i] = READ_REG(dsi->Instance->GEN_PLD_DATA) & (0xff << off); + off += 8; + + if ((i + 1) % 4 == 0 && i != 0) { + off = 0; + } + } + + return 0; +} + +int jz_dsi_video_init(struct jz_dsi *dsi) +{ + struct video_config *video_config = &dsi->video_config; + + //high speed + dsi_set_transfer_mode(dsi, 0); + + //set video mode + dsi_set_video_mode(dsi); + + __HAL_DSI_VID_MODE_TYPE(dsi, video_config->video_mode); + __HAL_DSI_LP_VSA_EN(dsi); + __HAL_DSI_LP_VBP_EN(dsi); + __HAL_DSI_LP_VFP_EN(dsi); + __HAL_DSI_LP_VACT_EN(dsi); + __HAL_DSI_LP_HBP_EN(dsi); + __HAL_DSI_LP_HFP_EN(dsi); + + __HAL_DSI_VPG_DIS(dsi); + __HAL_DSI_COLOR_BAR(dsi); + __HAL_DSI_VERTICAL_MODE(dsi); + + //dpi config + jz_dsi_dpi_config(dsi); + + //set R_DSI_HOST_CLKMGR_CFG tx_esc_clk_division???? + __HAL_DSI_TX_ESC_CLK_DIV(dsi, 7); + + __HAL_DSI_VID_NUM_CHUNKS(dsi, video_config->chunk); + __HAL_DSI_VID_PKT_SIZE(dsi, video_config->video_size); + __HAL_DSI_VID_NULL_SIZE(dsi, video_config->null_size); + + __HAL_DSI_DPI_VCID(dsi, video_config->virtual_channel); + + __HAL_DSI_SET_PHY_TXREQUESTCLKHS(dsi); + +#ifdef MIPI_DEBUG + __HAL_DSI_VPG_EN(dsi); + __HAL_DSI_COLOR_BAR(dsi); + __HAL_DSI_HORIZONTAL_MODE(dsi); + __HAL_DSI_VERTICAL_MODE(dsi); +#endif + + return 0; + +} + +/********************************/ + +/********************************/ +/** + * @} + */ + +/** + * @} + */ diff --git a/projects/x2660-halley/Examples/lcd-mipi/.vscode/cmake-kits.json b/projects/x2660-halley/Examples/lcd-mipi/.vscode/cmake-kits.json new file mode 100644 index 00000000..7c98a0d9 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/.vscode/cmake-kits.json @@ -0,0 +1,18 @@ +[ + { + "name": "GCC for ingenic cross compile on Windows", + + "toolchainFile": "mips-gcc-sde-elf.cmake", + "preferredGenerator": { + "name":"MinGW Makefiles" + } + }, + { + "name": "GCC for ingenic cross compile on Linux", + "toolchainFile": "mips-gcc-sde-elf.cmake", + "preferredGenerator": { + "name":"Unix Makefiles" + } + } +] + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd-mipi/.vscode/launch.json b/projects/x2660-halley/Examples/lcd-mipi/.vscode/launch.json new file mode 100644 index 00000000..8ddcfe12 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/.vscode/launch.json @@ -0,0 +1,63 @@ +{ + "version": "0.2.0", + "configurations": [ + // GDB Debugging: + { + "program": "${command:cmake.launchTargetPath}", + "name": "Launch (gdb)", + "request": "launch", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "console": "integratedTerminal", + "internalConsoleOptions": "openOnSessionStart", + "type": "cppdbg", + "MIMode": "gdb", + "miDebuggerPath": "mips-sde-elf-gdb", + "miDebuggerArgs": "", + "miDebuggerServerAddress": "localhost:3333", + "targetArchitecture": "mips", + "preLaunchTask": "adb forward", + "customLaunchSetupCommands": [ + { + "description": "gdb 启用整齐打印", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "text":"cd ${workspaceFolder}", + "ignoreFailures": false + }, + { + "text":"file build/${command:cmake.buildType}/${command:cmake.launchTargetFilename}", + "ignoreFailures": false + }, + { + "text": "target remote localhost:3333", + "ignoreFailures": false + }, + { + "text": "monitor reset halt", + "ignoreFailures": false + }, + { + "text": "monitor x1600_init", + "ignoreFailures": false + }, + { + "text": "load", + "ignoreFailures": false + }, + { + "text": "monitor mips32 invalidate all", + "ignoreFailures": false + } + ], + "logging": { + "engineLogging": false, + "programOutput": true + } + } + ] + } + \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd-mipi/.vscode/settings.json b/projects/x2660-halley/Examples/lcd-mipi/.vscode/settings.json new file mode 100644 index 00000000..0537c076 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/.vscode/settings.json @@ -0,0 +1,9 @@ +{ + "cmake.buildDirectory": "${workspaceFolder}/build/${buildType}", + "files.associations": { + "*.build": "makefile", + "*.mk": "makefile", + "Makefile*": "makefile", + "x16xx_hal.h": "c" + } +} \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd-mipi/.vscode/tasks.json b/projects/x2660-halley/Examples/lcd-mipi/.vscode/tasks.json new file mode 100644 index 00000000..53b4731e --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/.vscode/tasks.json @@ -0,0 +1,12 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "adb forward", + "type": "shell", + "command": "adb forward tcp:3333 tcp:3333", + }, + ] +} \ No newline at end of file diff --git a/projects/x2660-halley/Examples/lcd-mipi/CMakeLists.txt b/projects/x2660-halley/Examples/lcd-mipi/CMakeLists.txt new file mode 100644 index 00000000..a1832543 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/CMakeLists.txt @@ -0,0 +1,113 @@ +cmake_minimum_required(VERSION 3.8) +# +# Core project settings +# +Project(lcd) # Modified +enable_language(C CXX ASM) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS ON) +set(PROJ_PATH ${CMAKE_CURRENT_SOURCE_DIR}) +set(SDK_PATH ${PROJ_PATH}/../../../../) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Set linker script +set(linker_script_SRC ${SDK_PATH}/cpu/core-riscv/ld.lds) # Modified +set(EXECUTABLE ${CMAKE_PROJECT_NAME}) +set(CPU_PARAMETERS "-march=rv32imc -mabi=ilp32 -Wno-abi") + +set(CMAKE_ASM_FLAGS "${CPU_PARAMETERS} -D_ASSEMBLER_ -D__ASSEMBLY__") + +set(CMAKE_C_FLAGS "${CPU_PARAMETERS} -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Wall -fdata-sections -ffunction-sections") + +# Compiler options + +if(CMAKE_BUILD_TYPE STREQUAL Debug) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 -g -ggdb -DDEBUG") +else() + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O2") +endif() + +set(CMAKE_CXX_FLAGS ${CMAKE_C_FLAGS}) + +set(CMAKE_LD_FLAGS "${CPU_PARAMETERS}") + + +set(sources_SRCS # Modified + ${SDK_PATH}/cpu/core-riscv/spinlock.c + ${SDK_PATH}/cpu/core-riscv/start.S + ${SDK_PATH}/cpu/core-riscv/genex.S + ${SDK_PATH}/cpu/core-riscv/traps.c + ${SDK_PATH}/cpu/soc-x2600/src/interrupt.c + ${SDK_PATH}/cpu/soc-x2600/src/serial.c + ${SDK_PATH}/cpu/soc-x2600/src/startup.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_def.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_lcd.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_tick_risc_ccu.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_cpm.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_risc_ccu.c + ${SDK_PATH}/lib/libc/minimal/ctype.c + ${SDK_PATH}/lib/libc/minimal/div64.c + ${SDK_PATH}/lib/libc/minimal/string.c + ${SDK_PATH}/lib/libc/minimal/vsprintf.c + main.c + hc050.c +) + +if(CMAKE_EXPORT_COMPILE_COMMANDS) + set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) + set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) +endif() + +# +# Include directories +# +#set(include_path_DIRS +# Modified + +include_directories( + ${PROJ_PATH}/include + ${SDK_PATH}/lib/libc/minimal/include + ${SDK_PATH}/drivers/drivers-x2600/include + ${SDK_PATH}/cpu/core-riscv/include + ${SDK_PATH}/cpu/soc-x2600/include + +) + +# +# -L libdirs. +# +link_directories( +#path/to/lib +) + +# Executable files +add_executable(${EXECUTABLE} ${sources_SRCS}) + +# Linker options +target_link_libraries(${EXECUTABLE} PRIVATE + -T${linker_script_SRC} + ${CMAKE_LD_FLAGS} + -Wl,-Map=${CMAKE_PROJECT_NAME}.map,--cref + -Wl,--gc-sections + -Wl,--start-group + -Wl,--end-group + -Wl,--print-memory-usage +) + +# Execute post-build to print size +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_SIZE} $ +) + +# Convert output to hex and binary +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin + ) diff --git a/projects/x2660-halley/Examples/lcd-mipi/Makefile b/projects/x2660-halley/Examples/lcd-mipi/Makefile new file mode 100644 index 00000000..89ce113f --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/Makefile @@ -0,0 +1,178 @@ +###################################### +# target +###################################### +TARGET = lcd + +SDK_PATH = ../../../../ + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Werror-implicit-function-declaration + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/traps.c \ +$(SDK_PATH)/cpu/core-riscv/spinlock.c \ +$(SDK_PATH)/cpu/soc-x2600/src/startup.c \ +$(SDK_PATH)/cpu/soc-x2600/src/serial.c \ +$(SDK_PATH)/cpu/soc-x2600/src/interrupt.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_def.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_lcd.c \ +$(SDK_PATH)/lib/libc/minimal/vsprintf.c \ +$(SDK_PATH)/lib/libc/minimal/string.c \ +$(SDK_PATH)/lib/libc/minimal/ctype.c \ +$(SDK_PATH)/lib/libc/minimal/div64.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_cpm.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_mipi_dsi.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_mipi_dsi.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_tick_risc_ccu.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_risc_ccu.c \ +main.c \ +hc050.c + +ASM_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/start.S \ +$(SDK_PATH)/cpu/core-riscv/genex.S + + +####################################### +# binaries +####################################### +PREFIX = riscv32-ingenicv0-elf- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)as +LD = $(GCC_PATH)/$(PREFIX)ld +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)as +LD = $(PREFIX)ld +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -march=rv32imc -mabi=ilp32 -Wno-abi + +# fpu +FPU = + +# float-abi +FLOAT-ABI = + +# mcu +#MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) +MCU = $(CPU) $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = -D_ASSEMBLER_ -D__ASSEMBLY__ + +# C defines +C_DEFS = + + +# AS includes +AS_INCLUDES = \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ + +# C includes +C_INCLUDES = \ +-Iinclude \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/cpu/soc-x2600/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ +-I$(SDK_PATH)/drivers/drivers-x2600/include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 -O0 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = $(SDK_PATH)/cpu/core-riscv/ld.lds + +# libraries +#LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -nostdlib + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(CC) -c $(ASFLAGS) -o $@ $< + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/projects/x2660-halley/Examples/lcd-mipi/hc050.c b/projects/x2660-halley/Examples/lcd-mipi/hc050.c new file mode 100644 index 00000000..30a445ab --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/hc050.c @@ -0,0 +1,128 @@ +#include +#include + +#include +#include +#include + +#define ARRAY_SIZE(x) (int)( sizeof(x) / sizeof(x)[0] ) +#define DELAY_CMD 0x89 +static struct dsi_cmd_packet hc050_cmd_list[] = { + {0x15,0x00, 0x00}, + {0x23,0xB0, 0x04}, + {0x23,0xD6, 0x01}, + + {DELAY_CMD, 120, 0x00}, // delay 10ms + {0x05,0x29, 0x00}, + {0x05,0x11, 0x00}, + + {DELAY_CMD, 120, 0x00}, // delay 10ms + + {0x15,0x51, 0xFF}, + + {0x15,0x53, 0x2c}, + + {0x15,0x54, 0x2c}, + + {0x15,0x55, 0x02}, + + +}; +static void hc050_init(void); +static void hc050_power_on(void); +static void hc050_power_off(void); + +struct tft_config tft = { + .even_line_order = EVEN_RGBTORGB, + .odd_line_order = ODD_RGBTORGB, + .pix_clk_polarity = AT_RISING_EDGE, + .de_active_level = AT_HIGH_LEVEL, + .hsync_active_level = AT_LOW_LEVEL, + .vsync_active_level = AT_LOW_LEVEL, + +}; + +struct mipi_dsi_config mipi = { + .num_of_lanes = 4, + .virtual_channel = 0, + .color_coding = COLOR_CODE_24BIT, + .data_en_polarity = AT_RISING_EDGE, + .byte_clock = 0, + .max_hs_to_lp_cycles = 200, + .max_lp_to_hs_cycles = 80, + .max_bta_cycles = 4095, + .color_mode_polarity = AT_RISING_EDGE, + .shut_down_polarity = AT_RISING_EDGE, + .video_mode = VIDEO_BURST_WITH_SYNC_PULSES, + + .hsync_active_level = AT_LOW_LEVEL, + .vsync_active_level = AT_LOW_LEVEL, +}; + +struct lcd_data lcdc_data = { + .name = "hc050", + .refresh = 60, + .xres = 1080, + .yres = 1920, + //.pixclock = 0, // 自动计算 + .left_margin = 52, + //.right_margin = 100, + .right_margin = 216, + .upper_margin = 5, + .lower_margin = 7, + .hsync_len = 8, + .vsync_len = 2, + + .fb_fmt = fb_fmt_ARGB8888, + .lcd_mode = TFT_MIPI, + .out_format = OUT_FORMAT_RGB888, + + .mipi = &mipi, + + .tft = &tft, + .frame_status = 0, + .frame_index = 0, +// .frame_mem = 1080 * 1920, +// .frame_size = 1080 * 1920 * MAX_SRDMA_DESC_NUM, + + .power_on = hc050_power_on, + .power_off = hc050_power_off, + .lcd_init = hc050_init, +}; + +static void hc050_init(void) +{ + int i; + //struct dsi_cmd_packet hc050_sleep_out = {0x05, 0x11, 0x00}; + //struct dsi_cmd_packet hc050_display_on = {0x05, 0x29, 0x00}; + + for (i = 0; i < ARRAY_SIZE(hc050_cmd_list); i++) { + if(hc050_cmd_list[i].packet_type == DELAY_CMD){ + HAL_Delay(120); + } else { + dsi_write_cmd(&hc050_cmd_list[i]); + } + } + + //dsi_write_cmd(&hc050_sleep_out); + HAL_Delay(120); + //dsi_write_cmd(&hc050_display_on); +} + +static void hc050_power_on(void) +{ + // LL_GPIO_setPinMode(PC_Instance, 3, GPIO_MODE_OUTPUT0);//power en + // LL_GPIO_setPinMode(PC_Instance, 1, GPIO_MODE_OUTPUT1);//pwm1 + + // LL_GPIO_setPinMode(PC_Instance, 4, GPIO_MODE_OUTPUT0);//reset + // lcd_delay(20000000); + // LL_GPIO_setPinMode(PC_Instance, 4, GPIO_MODE_OUTPUT1); + // lcd_delay(500000); +} + +static void hc050_power_off(void) +{ + // LL_GPIO_setPinMode(PC_Instance, 3, GPIO_MODE_OUTPUT1); + // LL_GPIO_setPinMode(PC_Instance, 1, GPIO_MODE_OUTPUT0); +} + diff --git a/projects/x2660-halley/Examples/lcd-mipi/include/board_eth_phy_conf.h b/projects/x2660-halley/Examples/lcd-mipi/include/board_eth_phy_conf.h new file mode 100644 index 00000000..c907ead4 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/include/board_eth_phy_conf.h @@ -0,0 +1,75 @@ +#ifndef __ETH_PHY_CONF_H +#define __ETH_PHY_CONF_H + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 0x00U +#define MAC_ADDR1 0x11U +#define MAC_ADDR2 0x22U +#define MAC_ADDR3 0x33U +#define MAC_ADDR4 0x44U +#define MAC_ADDR5 0x55U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2600U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2600U) /*!< PHY link status interrupt mask */ + +/* ################## Ethernet peripheral configuration ##################### */ + + + +#endif // __ETH_PHY_CONF_H + diff --git a/projects/x2660-halley/Examples/lcd-mipi/include/x2600_hal_conf.h b/projects/x2660-halley/Examples/lcd-mipi/include/x2600_hal_conf.h new file mode 100644 index 00000000..f923376a --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/include/x2600_hal_conf.h @@ -0,0 +1,118 @@ +#ifndef __X2600_HAL_CONF_H__ +#define __X2600_HAL_CONF_H__ +/* TODO： 本文件应该通过工具生成，在配置工程中选择不同的组件时，在此处包含不同的头文件 + 暂时包含全部头文件. +*/ + + +/* 1. Includes ---------------------------------------------------- */ + + +/* Hal Module selections. */ +#if 0 +#define HAL_MSC_ENABLED +#define HAL_I2C_ENABLED +#define HAL_UART_ENABLED +#define HAL_ADC_ENABLED +#define HAL_SPI_ENABLED +#define HAL_WDT_ENABLED +#define HAL_TCU_ENABLED +#define HAL_RTC_ENABLED +#define HAL_EFUSE_ENABLED +#define HAL_PWM_ENABLED +#define HAL_GMAC_ENABLED +#define HAL_USB_ENABLED +#endif + +/* 系统时钟配配置，通过工具生成，随开发板或者平台变化.*/ +#include +#include + +#include "x2600_hal_tick.h" +#include "x2600_ll_ost_core.h" +#include "x2600_ll_ost_global.h" +#include "x2600_ll_cpm.h" +#include "x2600_ll_gpio.h" + +#include "x2600_hal_pdma.h" + +//#include "x2600_hal_sfcnor.h" + +#ifdef HAL_MSC_ENABLED + +#endif + +#ifdef HAL_I2C_ENABLED +#include "x2600_hal_i2c.h" +#endif + +#ifdef HAL_UART_ENABLED +#include "x2600_hal_uart.h" +#endif + +#ifdef HAL_ADC_ENABLED +#include "x2600_hal_adc.h" +#endif + +#ifdef HAL_SPI_ENABLED +#include "x2600_hal_spi.h" +#endif + +#ifdef HAL_WDT_ENABLED +#include "x2600_hal_wdt.h" +#endif + +#ifdef HAL_TCU_ENABLED +#include "x2600_hal_tcu.h" +#endif + +#ifdef HAL_RTC_ENABLED +#include "x2600_hal_rtc.h" +#endif + +#ifdef HAL_EFUSE_ENABLED +#include "x2600_ll_efuse.h" +#include "x2600_hal_efuse.h" +#endif + +#ifdef HAL_PWM_ENABLED +#include "x2600_hal_pwm.h" +#endif + +#ifdef HAL_GMAC_ENABLED +#include "x2600_hal_gmac.h" +#endif + +#ifdef HAL_USB_ENABLED +#include "x2600_hal_pcd.h" +#include "x2600_hal_pcd_ex.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* 2. Exported Types ---------------------------------------------- */ + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_H__ */ diff --git a/projects/x2660-halley/Examples/lcd-mipi/include/x2600_sysclk_conf.h b/projects/x2660-halley/Examples/lcd-mipi/include/x2600_sysclk_conf.h new file mode 100644 index 00000000..ee3e7e49 --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/include/x2600_sysclk_conf.h @@ -0,0 +1,82 @@ +/** + * @file x2600_sysclk_conf.h + * @author MPU系统软件部团队 + * @brief + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_SYSCLK_CONF_H__ +#define __X2600_SYSCLK_CONF_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/* 1. Includes ---------------------------------------------------- */ + +/* 2. Exported Types ---------------------------------------------- */ + + +/* 3. Exported Constants ------------------------------------------ */ + +/* 4. Exported Macros --------------------------------------------- */ +#define SYSCLK_EXTAL (24000000) +#define SYSCLK_APLL (1200000000) +#define SYSCLK_MPLL (1200000000) + +#define SystemCoreClock SYSCLK_APLL + +#define CGU_CONFIG_MSC_APLL_24M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 24, \ + .Config = 0 } + +#define CGU_CONFIG_MSC_APLL_48M { \ + .PLLMux = MSC1CDR_SCLK_A, \ + .Div = 11, \ + .Config = 0 } + + +#define CGU_CONFIG_SSI_MPLL_500K { \ + .PLLMux = SSICDR_MPLL, \ + .Div = 15, \ + .Config = 0 } + +#define CGU_CONFIG_LCD_MPLL_28M { \ + .PLLMux = LPCDR_MPLL, \ + .Div = 64, \ + .Config = 0} + +#define CGU_CONFIG_LCD_MPLL_158M { \ + .PLLMux = LPCDR_MPLL, \ + .Div = 10, \ + .Config = 0} +#define CGU_CONFIG_LCD_MPLL_52M { \ + .PLLMux = LPCDR_MPLL, \ + .Div = 33, \ + .Config = 0} + +/* 5. Exported Funcs ---------------------------------------------- */ + +/* 6. Exported Variables ------------------------------------------ */ + +/* 7. Private Types ----------------------------------------------- */ + +/* 8. Private Constants ------------------------------------------- */ + +/* 9. Private Macros ---------------------------------------------- */ + +/* 10. Private Funcs ---------------------------------------------- */ + +/* 11. Private Variables ------------------------------------------ */ + +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_ADC_H__ */ diff --git a/projects/x2660-halley/Examples/lcd-mipi/main.c b/projects/x2660-halley/Examples/lcd-mipi/main.c new file mode 100644 index 00000000..6e8341de --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/main.c @@ -0,0 +1,82 @@ +#include + +#define BUFSIZE 1080*1920 +__align(32) uint32_t framebuffer[BUFSIZE] = {0x0}; +//__align(32) uint32_t framebuffer = 0x7300000; + +LCD_HandleTypeDef LCD_Handle; +LL_CPM_CGU_ConfigTypeDef LcdCguConfig = CGU_CONFIG_LCD_MPLL_158M; + +__align(64) struct srdmadesc desc; +extern struct lcd_data lcdc_data; +__attribute__((unused)) static void lcdc_dump_regs(void); + + +int main(void) +{ + int i; + Flush_Cache_AllAddr(); + for(i = 0; i < BUFSIZE; i++){ + if((i / 360) % 3 == 2) + framebuffer[i] = 0x0000FF; + if((i / 360) % 3 == 1) + framebuffer[i] = 0x00FF00; + if((i / 360) % 3 == 0) + framebuffer[i] = 0xFF0000; + } + HAL_Delay(1000); + LCD_Handle.Instance = DPU_Instance; + LCD_Handle.pdata = &lcdc_data; + LCD_Handle.desc[0] = &desc; + /*使能时钟*/ + CPM_CGU_LCD_Start(CPM_Instance, &LcdCguConfig); + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_LCD); + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_MIPI_DSI); + ll_request_irq(IRQ_INTC0_LCD, lcdc_irq_handler, (void *)&LCD_Handle); + /*初始化GPIO*/ + /*LCD初始化*/ + HAL_LCDC_INIT(&LCD_Handle); + /*配置RDMA参数*/ + HAL_LCDC_ENABLE(&LCD_Handle); + + HAL_SRDMA_INIT(&LCD_Handle, framebuffer); + HAL_SRDMA_START(&LCD_Handle); + + while(1); + return 0; +} + + +__attribute__((unused)) static void lcdc_dump_regs(void) +{ + prom_printk("SRD_CHAIN_ADDR = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_SRD_CHAIN_ADDR)); + prom_printk("ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_ST)); + prom_printk("CLR_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_CLR_ST)); + prom_printk("INTC = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_INTC)); + prom_printk("INT_FLAG = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_INT_FLAG)); + prom_printk("COM_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_COM_CONFIG)); + prom_printk("RDMA_DES = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_DES)); + prom_printk("RDMA_CHAIN_SITE = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_CHAIN_SITE)); + prom_printk("RDMA_SITE = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_RDMA_SITE)); + prom_printk("DISP_COM = 0x%08x\n", READ_REG(LCD_Handle.Instance->DISP_COM)); + prom_printk("PCFG_RD_CTRL = 0x%08x\n", READ_REG(LCD_Handle.Instance->DC_PCFG_RD_CTRL)); + + prom_printk("SLCD_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_PANEL_CFG)); + prom_printk("SLCD_WR_DUTY = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_WR_DUTY)); + prom_printk("SLCD_TIMING = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_TIMING)); + prom_printk("SLCD_FRM_SIZE = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_FRM_SIZE)); + prom_printk("SLCD_SLOW_TIME = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_SLOW_TIME)); + prom_printk("SLCD_REG_IF = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_REG_IF)); + prom_printk("SLCD_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_ST)); + prom_printk("SLCD_REG_CTRL = 0x%08x\n", READ_REG(LCD_Handle.Instance->SLCD_REG_CTRL)); + + prom_printk("TFT_HSYNC = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMING_HSYNC)); + prom_printk("TFT_VSYNC = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_VSYNC)); + prom_printk("TFT_HDE = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_HDE)); + prom_printk("TFT_VDE = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TIMIING_VDE)); + prom_printk("TFT_CFG = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_TRAN_CFG)); + prom_printk("TFT_ST = 0x%08x\n", READ_REG(LCD_Handle.Instance->TFT_ST)); +} + + + diff --git a/projects/x2660-halley/Examples/lcd-mipi/riscv32-gcc.cmake b/projects/x2660-halley/Examples/lcd-mipi/riscv32-gcc.cmake new file mode 100644 index 00000000..d09813df --- /dev/null +++ b/projects/x2660-halley/Examples/lcd-mipi/riscv32-gcc.cmake @@ -0,0 +1,18 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv32) + +# Some default GCC settings +set(TOOLCHAIN_PREFIX "riscv32-ingenicv0-elf-") + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++) + +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) -- Gitee