diff --git a/cpu/soc-x2600/include/icodec.h b/cpu/soc-x2600/include/icodec.h new file mode 100644 index 0000000000000000000000000000000000000000..061dbb1dc8b41c99732e908a48748acb6f0b89c4 --- /dev/null +++ b/cpu/soc-x2600/include/icodec.h @@ -0,0 +1,612 @@ +#ifndef __REG_ICODEC_H__ +#define __REG_ICODEC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup group_ICODEC ICODEC控制器 + * @{ + */ + +/** + * @addtogroup g_ICODEC_reg ICODEC 寄存器定义 + * @{ + */ +/** +* @brief Registers for icodec +*/ +typedef struct { + ////TODO, 添加寄存器Reserved，填充地址空间 + __IO unsigned long RSTR; /*!< Reset register ,RW, 0x000 */ + __IO unsigned long DACCR1; /*!< DAC Control Register1 ,RW, 0x004 */ + __IO unsigned long DACCR2; /*!< DAC Control Register2 ,RW, 0x008 */ + __IO unsigned long DACCR3; /*!< DAC Control Register3 ,RW, 0x00C */ + __IO unsigned long DACCR4; /*!< DAC Control Register4 ,RW, 0x010 */ + __IO unsigned long DACCR5; /*!< DAC Control Register5 ,RW, 0x014 */ + __IO unsigned long DACDGR; /*!< DAC Digital Gain Register ,RW, 0x018 */ + unsigned long RESERVED_0x1c[2]; /*!< Reserved Memory Area start from 0x1c to 0x24*/ + __IO unsigned long ADCCR1; /*!< ADC Control Register1 ,RW, 0x024 */ + __IO unsigned long ADCCR2; /*!< ADC Control Register2 ,RW, 0x028 */ + __IO unsigned long ADCCR3; /*!< ADC Control Register3 ,RW, 0x02C */ + __IO unsigned long ADCCR4; /*!< ADC Control Register4 ,RW, 0x030 */ + __IO unsigned long ADCDGR; /*!< ADC Digital Gain Register ,RW, 0x034 */ + unsigned long RESERVED_0x38[18]; /*!< Reserved Memory Area start from 0x38 to 0x80*/ + __IO unsigned long BIASCR1; /*!< BIAS Control Register1 ,RW, 0x080 */ + __IO unsigned long BIASCR2; /*!< BIAS Control Register2 ,RW, 0x084 */ + __IO unsigned long BIASCR3; /*!< BIAS Control Register3 ,RW, 0x088 */ + unsigned long RESERVED_0x8c[5]; /*!< Reserved Memory Area start from 0x8c to 0xa0*/ + __IO unsigned long DACLCR; /*!< DACL Control Register ,RW, 0x0A0 */ + __IO unsigned long HPCR; /*!< HP Control Register ,RW, 0x0A4 */ + __IO unsigned long HPDSR; /*!< HP Driver Strength Register ,RW, 0x0A8 */ + __IO unsigned long HPGR; /*!< HP GAIN Register ,RW, 0x0AC */ + unsigned long RESERVED_0xb0[4]; /*!< Reserved Memory Area start from 0xb0 to 0xc0*/ + __IO unsigned long ADCLCR; /*!< ADCL Control Register ,RW, 0x0C0 */ + __IO unsigned long MICCR; /*!< MIC Control Register ,RW, 0x0C4 */ + __IO unsigned long ALCGR; /*!< ALC GAIN Register ,RW, 0x0C8 */ + __IO unsigned long MICGR; /*!< MIC GAIN Register ,RW, 0x0CC */ + unsigned long RESERVED_0xd0[12]; /*!< Reserved Memory Area start from 0xd0 to 0x100*/ + __IO unsigned long AGCCR1; /*!< AGC Control Register1 ,RW, 0x100 */ + __IO unsigned long AGCCR2; /*!< AGC Control Register2 ,RW, 0x104 */ + __IO unsigned long AGCCR3; /*!< AGC Control Register3 ,RW, 0x108 */ + __IO unsigned long PGAGR; /*!< PGA GAIN Register ,RW, 0x10C */ + __IO unsigned long AGCSRR; /*!< AGC Sample Rate Register ,RW, 0x110 */ + __IO unsigned long AGCMAXLR; /*!< AGC Max Lower Register ,RW, 0x114 */ + __IO unsigned long AGCMAXHR; /*!< AGC Max Higher Register ,RW, 0x118 */ + __IO unsigned long AGCMINLR; /*!< AGC Min Lower Register ,RW, 0x11C */ + __IO unsigned long AGCMINHR; /*!< AGC Min Higher Register ,RW, 0x120 */ + __IO unsigned long AGCGR; /*!< AGC Gain Register ,RW, 0x124 */ + unsigned long RESERVED_0x128[4]; /*!< Reserved Memory Area start from 0x128 to 0x138*/ + __I unsigned long ALCOGR; /*!< ALC Observe Gain Register , R, 0x138 */ +} ICODEC_TypeDef; + +/********* Register BitField Details: RSTR BASE+0x000 *********/ +#define RSTR_ADCRST_Pos (5U) +#define RSTR_ADCRST_Msk (0x1UL << RSTR_ADCRST_Pos) /*!< 0x00000020 */ +#define RSTR_ADCRST RSTR_ADCRST_Msk +#define RSTR_ADCRST_0 (0x1UL << RSTR_ADCRST_Pos) /*!< 0x00000020 */ +#define RSTR_DACRST_Pos (4U) +#define RSTR_DACRST_Msk (0x1UL << RSTR_DACRST_Pos) /*!< 0x00000010 */ +#define RSTR_DACRST RSTR_DACRST_Msk +#define RSTR_DACRST_0 (0x1UL << RSTR_DACRST_Pos) /*!< 0x00000010 */ +#define RSTR_BISTEN_Pos (1U) +#define RSTR_BISTEN_Msk (0x1UL << RSTR_BISTEN_Pos) /*!< 0x00000002 */ +#define RSTR_BISTEN RSTR_BISTEN_Msk +#define RSTR_BISTEN_0 (0x1UL << RSTR_BISTEN_Pos) /*!< 0x00000002 */ +#define RSTR_SYSRST_Pos (0U) +#define RSTR_SYSRST_Msk (0x1UL << RSTR_SYSRST_Pos) /*!< 0x00000001 */ +#define RSTR_SYSRST RSTR_SYSRST_Msk +#define RSTR_SYSRST_0 (0x1UL << RSTR_SYSRST_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DACCR1 BASE+0x004 *********/ +#define DACCR1_I2SWL_Pos (4U) +#define DACCR1_I2SWL_Msk (0x3UL << DACCR1_I2SWL_Pos) /*!< 0x00000030 */ +#define DACCR1_I2SWL DACCR1_I2SWL_Msk +#define DACCR1_I2SWL_0 (0x1UL << DACCR1_I2SWL_Pos) /*!< 0x00000010 */ +#define DACCR1_I2SWL_1 (0x2UL << DACCR1_I2SWL_Pos) /*!< 0x00000020 */ +#define DACCR1_I2SFMT_Pos (2U) +#define DACCR1_I2SFMT_Msk (0x3UL << DACCR1_I2SFMT_Pos) /*!< 0x0000000c */ +#define DACCR1_I2SFMT DACCR1_I2SFMT_Msk +#define DACCR1_I2SFMT_0 (0x1UL << DACCR1_I2SFMT_Pos) /*!< 0x00000004 */ +#define DACCR1_I2SFMT_1 (0x2UL << DACCR1_I2SFMT_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: DACCR2 BASE+0x008 *********/ +#define DACCR2_I2SLRP_Pos (7U) +#define DACCR2_I2SLRP_Msk (0x1UL << DACCR2_I2SLRP_Pos) /*!< 0x00000080 */ +#define DACCR2_I2SLRP DACCR2_I2SLRP_Msk +#define DACCR2_I2SLRP_0 (0x1UL << DACCR2_I2SLRP_Pos) /*!< 0x00000080 */ +#define DACCR2_I2SLRSW_Pos (6U) +#define DACCR2_I2SLRSW_Msk (0x1UL << DACCR2_I2SLRSW_Pos) /*!< 0x00000040 */ +#define DACCR2_I2SLRSW DACCR2_I2SLRSW_Msk +#define DACCR2_I2SLRSW_0 (0x1UL << DACCR2_I2SLRSW_Pos) /*!< 0x00000040 */ +#define DACCR2_FUNCMSTEN_Pos (5U) +#define DACCR2_FUNCMSTEN_Msk (0x1UL << DACCR2_FUNCMSTEN_Pos) /*!< 0x00000020 */ +#define DACCR2_FUNCMSTEN DACCR2_FUNCMSTEN_Msk +#define DACCR2_FUNCMSTEN_0 (0x1UL << DACCR2_FUNCMSTEN_Pos) /*!< 0x00000020 */ +#define DACCR2_PINMSTEN_Pos (4U) +#define DACCR2_PINMSTEN_Msk (0x1UL << DACCR2_PINMSTEN_Pos) /*!< 0x00000010 */ +#define DACCR2_PINMSTEN DACCR2_PINMSTEN_Msk +#define DACCR2_PINMSTEN_0 (0x1UL << DACCR2_PINMSTEN_Pos) /*!< 0x00000010 */ +#define DACCR2_I2SRST_Pos (0U) +#define DACCR2_I2SRST_Msk (0x1UL << DACCR2_I2SRST_Pos) /*!< 0x00000001 */ +#define DACCR2_I2SRST DACCR2_I2SRST_Msk +#define DACCR2_I2SRST_0 (0x1UL << DACCR2_I2SRST_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DACCR3 BASE+0x00C *********/ +#define DACCR3_MUTEN_Pos (7U) +#define DACCR3_MUTEN_Msk (0x1UL << DACCR3_MUTEN_Pos) /*!< 0x00000080 */ +#define DACCR3_MUTEN DACCR3_MUTEN_Msk +#define DACCR3_MUTEN_0 (0x1UL << DACCR3_MUTEN_Pos) /*!< 0x00000080 */ +#define DACCR3_MUTSR_Pos (4U) +#define DACCR3_MUTSR_Msk (0x7UL << DACCR3_MUTSR_Pos) /*!< 0x00000070 */ +#define DACCR3_MUTSR DACCR3_MUTSR_Msk +#define DACCR3_MUTSR_0 (0x1UL << DACCR3_MUTSR_Pos) /*!< 0x00000010 */ +#define DACCR3_MUTSR_1 (0x2UL << DACCR3_MUTSR_Pos) /*!< 0x00000020 */ +#define DACCR3_MUTSR_2 (0x4UL << DACCR3_MUTSR_Pos) /*!< 0x00000040 */ +#define DACCR3_DAEN_Pos (3U) +#define DACCR3_DAEN_Msk (0x1UL << DACCR3_DAEN_Pos) /*!< 0x00000008 */ +#define DACCR3_DAEN DACCR3_DAEN_Msk +#define DACCR3_DAEN_0 (0x1UL << DACCR3_DAEN_Pos) /*!< 0x00000008 */ +#define DACCR3_DITHEREN_Pos (2U) +#define DACCR3_DITHEREN_Msk (0x1UL << DACCR3_DITHEREN_Pos) /*!< 0x00000004 */ +#define DACCR3_DITHEREN DACCR3_DITHEREN_Msk +#define DACCR3_DITHEREN_0 (0x1UL << DACCR3_DITHEREN_Pos) /*!< 0x00000004 */ +#define DACCR3_DITHERLVL_Pos (1U) +#define DACCR3_DITHERLVL_Msk (0x1UL << DACCR3_DITHERLVL_Pos) /*!< 0x00000002 */ +#define DACCR3_DITHERLVL DACCR3_DITHERLVL_Msk +#define DACCR3_DITHERLVL_0 (0x1UL << DACCR3_DITHERLVL_Pos) /*!< 0x00000002 */ +#define DACCR3_DITHERSIGN_Pos (0U) +#define DACCR3_DITHERSIGN_Msk (0x1UL << DACCR3_DITHERSIGN_Pos) /*!< 0x00000001 */ +#define DACCR3_DITHERSIGN DACCR3_DITHERSIGN_Msk +#define DACCR3_DITHERSIGN_0 (0x1UL << DACCR3_DITHERSIGN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DACCR4 BASE+0x010 *********/ +#define DACCR4_DEEMPSEL_Pos (0U) +#define DACCR4_DEEMPSEL_Msk (0x3UL << DACCR4_DEEMPSEL_Pos) /*!< 0x00000003 */ +#define DACCR4_DEEMPSEL DACCR4_DEEMPSEL_Msk +#define DACCR4_DEEMPSEL_0 (0x1UL << DACCR4_DEEMPSEL_Pos) /*!< 0x00000001 */ +#define DACCR4_DEEMPSEL_1 (0x2UL << DACCR4_DEEMPSEL_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: DACCR5 BASE+0x014 *********/ +#define DACCR5_BISTSELL_Pos (2U) +#define DACCR5_BISTSELL_Msk (0x3UL << DACCR5_BISTSELL_Pos) /*!< 0x0000000c */ +#define DACCR5_BISTSELL DACCR5_BISTSELL_Msk +#define DACCR5_BISTSELL_0 (0x1UL << DACCR5_BISTSELL_Pos) /*!< 0x00000004 */ +#define DACCR5_BISTSELL_1 (0x2UL << DACCR5_BISTSELL_Pos) /*!< 0x00000008 */ +#define DACCR5_MUTEL_Pos (0U) +#define DACCR5_MUTEL_Msk (0x1UL << DACCR5_MUTEL_Pos) /*!< 0x00000001 */ +#define DACCR5_MUTEL DACCR5_MUTEL_Msk +#define DACCR5_MUTEL_0 (0x1UL << DACCR5_MUTEL_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: DACDGR BASE+0x018 *********/ +#define DACDGR_DIGGAIN_Pos (0U) +#define DACDGR_DIGGAIN_Msk (0xffUL << DACDGR_DIGGAIN_Pos) /*!< 0x000000ff */ +#define DACDGR_DIGGAIN DACDGR_DIGGAIN_Msk +#define DACDGR_DIGGAIN_0 (0x1UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000001 */ +#define DACDGR_DIGGAIN_1 (0x2UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000002 */ +#define DACDGR_DIGGAIN_2 (0x4UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000004 */ +#define DACDGR_DIGGAIN_3 (0x8UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000008 */ +#define DACDGR_DIGGAIN_4 (0x10UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000010 */ +#define DACDGR_DIGGAIN_5 (0x20UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000020 */ +#define DACDGR_DIGGAIN_6 (0x40UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000040 */ +#define DACDGR_DIGGAIN_7 (0x80UL << DACDGR_DIGGAIN_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: ADCCR1 BASE+0x024 *********/ +#define ADCCR1_I2SDATSEL_Pos (6U) +#define ADCCR1_I2SDATSEL_Msk (0x3UL << ADCCR1_I2SDATSEL_Pos) /*!< 0x000000c0 */ +#define ADCCR1_I2SDATSEL ADCCR1_I2SDATSEL_Msk +#define ADCCR1_I2SDATSEL_0 (0x1UL << ADCCR1_I2SDATSEL_Pos) /*!< 0x00000040 */ +#define ADCCR1_I2SDATSEL_1 (0x2UL << ADCCR1_I2SDATSEL_Pos) /*!< 0x00000080 */ +#define ADCCR1_I2SWL_Pos (4U) +#define ADCCR1_I2SWL_Msk (0x3UL << ADCCR1_I2SWL_Pos) /*!< 0x00000030 */ +#define ADCCR1_I2SWL ADCCR1_I2SWL_Msk +#define ADCCR1_I2SWL_0 (0x1UL << ADCCR1_I2SWL_Pos) /*!< 0x00000010 */ +#define ADCCR1_I2SWL_1 (0x2UL << ADCCR1_I2SWL_Pos) /*!< 0x00000020 */ +#define ADCCR1_I2SFMT_Pos (2U) +#define ADCCR1_I2SFMT_Msk (0x3UL << ADCCR1_I2SFMT_Pos) /*!< 0x0000000c */ +#define ADCCR1_I2SFMT ADCCR1_I2SFMT_Msk +#define ADCCR1_I2SFMT_0 (0x1UL << ADCCR1_I2SFMT_Pos) /*!< 0x00000004 */ +#define ADCCR1_I2SFMT_1 (0x2UL << ADCCR1_I2SFMT_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: ADCCR2 BASE+0x028 *********/ +#define ADCCR2_I2SLRP_Pos (7U) +#define ADCCR2_I2SLRP_Msk (0x1UL << ADCCR2_I2SLRP_Pos) /*!< 0x00000080 */ +#define ADCCR2_I2SLRP ADCCR2_I2SLRP_Msk +#define ADCCR2_I2SLRP_0 (0x1UL << ADCCR2_I2SLRP_Pos) /*!< 0x00000080 */ +#define ADCCR2_FUNCMSTEN_Pos (5U) +#define ADCCR2_FUNCMSTEN_Msk (0x1UL << ADCCR2_FUNCMSTEN_Pos) /*!< 0x00000020 */ +#define ADCCR2_FUNCMSTEN ADCCR2_FUNCMSTEN_Msk +#define ADCCR2_FUNCMSTEN_0 (0x1UL << ADCCR2_FUNCMSTEN_Pos) /*!< 0x00000020 */ +#define ADCCR2_PINMSTEN_Pos (4U) +#define ADCCR2_PINMSTEN_Msk (0x1UL << ADCCR2_PINMSTEN_Pos) /*!< 0x00000010 */ +#define ADCCR2_PINMSTEN ADCCR2_PINMSTEN_Msk +#define ADCCR2_PINMSTEN_0 (0x1UL << ADCCR2_PINMSTEN_Pos) /*!< 0x00000010 */ +#define ADCCR2_SCKINV_Pos (1U) +#define ADCCR2_SCKINV_Msk (0x1UL << ADCCR2_SCKINV_Pos) /*!< 0x00000002 */ +#define ADCCR2_SCKINV ADCCR2_SCKINV_Msk +#define ADCCR2_SCKINV_0 (0x1UL << ADCCR2_SCKINV_Pos) /*!< 0x00000002 */ +#define ADCCR2_I2SRST_Pos (0U) +#define ADCCR2_I2SRST_Msk (0x1UL << ADCCR2_I2SRST_Pos) /*!< 0x00000001 */ +#define ADCCR2_I2SRST ADCCR2_I2SRST_Msk +#define ADCCR2_I2SRST_0 (0x1UL << ADCCR2_I2SRST_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: ADCCR3 BASE+0x02C *********/ +#define ADCCR3_HPFMODE_Pos (2U) +#define ADCCR3_HPFMODE_Msk (0x3UL << ADCCR3_HPFMODE_Pos) /*!< 0x0000000c */ +#define ADCCR3_HPFMODE ADCCR3_HPFMODE_Msk +#define ADCCR3_HPFMODE_0 (0x1UL << ADCCR3_HPFMODE_Pos) /*!< 0x00000004 */ +#define ADCCR3_HPFMODE_1 (0x2UL << ADCCR3_HPFMODE_Pos) /*!< 0x00000008 */ +#define ADCCR3_POLL_Pos (0U) +#define ADCCR3_POLL_Msk (0x1UL << ADCCR3_POLL_Pos) /*!< 0x00000001 */ +#define ADCCR3_POLL ADCCR3_POLL_Msk +#define ADCCR3_POLL_0 (0x1UL << ADCCR3_POLL_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: ADCCR4 BASE+0x030 *********/ +#define ADCCR4_BISTSELL_Pos (2U) +#define ADCCR4_BISTSELL_Msk (0x3UL << ADCCR4_BISTSELL_Pos) /*!< 0x0000000c */ +#define ADCCR4_BISTSELL ADCCR4_BISTSELL_Msk +#define ADCCR4_BISTSELL_0 (0x1UL << ADCCR4_BISTSELL_Pos) /*!< 0x00000004 */ +#define ADCCR4_BISTSELL_1 (0x2UL << ADCCR4_BISTSELL_Pos) /*!< 0x00000008 */ +#define ADCCR4_PGAGAINENL_Pos (0U) +#define ADCCR4_PGAGAINENL_Msk (0x1UL << ADCCR4_PGAGAINENL_Pos) /*!< 0x00000001 */ +#define ADCCR4_PGAGAINENL ADCCR4_PGAGAINENL_Msk +#define ADCCR4_PGAGAINENL_0 (0x1UL << ADCCR4_PGAGAINENL_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: ADCDGR BASE+0x034 *********/ +#define ADCDGR_DIGGAIN_Pos (0U) +#define ADCDGR_DIGGAIN_Msk (0xffUL << ADCDGR_DIGGAIN_Pos) /*!< 0x000000ff */ +#define ADCDGR_DIGGAIN ADCDGR_DIGGAIN_Msk +#define ADCDGR_DIGGAIN_0 (0x1UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000001 */ +#define ADCDGR_DIGGAIN_1 (0x2UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000002 */ +#define ADCDGR_DIGGAIN_2 (0x4UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000004 */ +#define ADCDGR_DIGGAIN_3 (0x8UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000008 */ +#define ADCDGR_DIGGAIN_4 (0x10UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000010 */ +#define ADCDGR_DIGGAIN_5 (0x20UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000020 */ +#define ADCDGR_DIGGAIN_6 (0x40UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000040 */ +#define ADCDGR_DIGGAIN_7 (0x80UL << ADCDGR_DIGGAIN_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: BIASCR1 BASE+0x080 *********/ +#define BIASCR1_MICBIASGAIN_Pos (5U) +#define BIASCR1_MICBIASGAIN_Msk (0x7UL << BIASCR1_MICBIASGAIN_Pos) /*!< 0x000000e0 */ +#define BIASCR1_MICBIASGAIN BIASCR1_MICBIASGAIN_Msk +#define BIASCR1_MICBIASGAIN_0 (0x1UL << BIASCR1_MICBIASGAIN_Pos) /*!< 0x00000020 */ +#define BIASCR1_MICBIASGAIN_1 (0x2UL << BIASCR1_MICBIASGAIN_Pos) /*!< 0x00000040 */ +#define BIASCR1_MICBIASGAIN_2 (0x4UL << BIASCR1_MICBIASGAIN_Pos) /*!< 0x00000080 */ +#define BIASCR1_MICBIASEN_Pos (3U) +#define BIASCR1_MICBIASEN_Msk (0x1UL << BIASCR1_MICBIASEN_Pos) /*!< 0x00000008 */ +#define BIASCR1_MICBIASEN BIASCR1_MICBIASEN_Msk +#define BIASCR1_MICBIASEN_0 (0x1UL << BIASCR1_MICBIASEN_Pos) /*!< 0x00000008 */ +#define BIASCR1_ADCIBIASEN_Pos (2U) +#define BIASCR1_ADCIBIASEN_Msk (0x1UL << BIASCR1_ADCIBIASEN_Pos) /*!< 0x00000004 */ +#define BIASCR1_ADCIBIASEN BIASCR1_ADCIBIASEN_Msk +#define BIASCR1_ADCIBIASEN_0 (0x1UL << BIASCR1_ADCIBIASEN_Pos) /*!< 0x00000004 */ +#define BIASCR1_DACIBIASEN_Pos (1U) +#define BIASCR1_DACIBIASEN_Msk (0x1UL << BIASCR1_DACIBIASEN_Pos) /*!< 0x00000002 */ +#define BIASCR1_DACIBIASEN BIASCR1_DACIBIASEN_Msk +#define BIASCR1_DACIBIASEN_0 (0x1UL << BIASCR1_DACIBIASEN_Pos) /*!< 0x00000002 */ +#define BIASCR1_VREFEN_Pos (0U) +#define BIASCR1_VREFEN_Msk (0x1UL << BIASCR1_VREFEN_Pos) /*!< 0x00000001 */ +#define BIASCR1_VREFEN BIASCR1_VREFEN_Msk +#define BIASCR1_VREFEN_0 (0x1UL << BIASCR1_VREFEN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: BIASCR2 BASE+0x084 *********/ +#define BIASCR2_SELVREF_Pos (0U) +#define BIASCR2_SELVREF_Msk (0xffUL << BIASCR2_SELVREF_Pos) /*!< 0x000000ff */ +#define BIASCR2_SELVREF BIASCR2_SELVREF_Msk +#define BIASCR2_SELVREF_0 (0x1UL << BIASCR2_SELVREF_Pos) /*!< 0x00000001 */ +#define BIASCR2_SELVREF_1 (0x2UL << BIASCR2_SELVREF_Pos) /*!< 0x00000002 */ +#define BIASCR2_SELVREF_2 (0x4UL << BIASCR2_SELVREF_Pos) /*!< 0x00000004 */ +#define BIASCR2_SELVREF_3 (0x8UL << BIASCR2_SELVREF_Pos) /*!< 0x00000008 */ +#define BIASCR2_SELVREF_4 (0x10UL << BIASCR2_SELVREF_Pos) /*!< 0x00000010 */ +#define BIASCR2_SELVREF_5 (0x20UL << BIASCR2_SELVREF_Pos) /*!< 0x00000020 */ +#define BIASCR2_SELVREF_6 (0x40UL << BIASCR2_SELVREF_Pos) /*!< 0x00000040 */ +#define BIASCR2_SELVREF_7 (0x80UL << BIASCR2_SELVREF_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: BIASCR3 BASE+0x088 *********/ +#define BIASCR3_IBIASADC_Pos (4U) +#define BIASCR3_IBIASADC_Msk (0xfUL << BIASCR3_IBIASADC_Pos) /*!< 0x000000f0 */ +#define BIASCR3_IBIASADC BIASCR3_IBIASADC_Msk +#define BIASCR3_IBIASADC_0 (0x1UL << BIASCR3_IBIASADC_Pos) /*!< 0x00000010 */ +#define BIASCR3_IBIASADC_1 (0x2UL << BIASCR3_IBIASADC_Pos) /*!< 0x00000020 */ +#define BIASCR3_IBIASADC_2 (0x4UL << BIASCR3_IBIASADC_Pos) /*!< 0x00000040 */ +#define BIASCR3_IBIASADC_3 (0x8UL << BIASCR3_IBIASADC_Pos) /*!< 0x00000080 */ +#define BIASCR3_IBIASDAC_Pos (0U) +#define BIASCR3_IBIASDAC_Msk (0xfUL << BIASCR3_IBIASDAC_Pos) /*!< 0x0000000f */ +#define BIASCR3_IBIASDAC BIASCR3_IBIASDAC_Msk +#define BIASCR3_IBIASDAC_0 (0x1UL << BIASCR3_IBIASDAC_Pos) /*!< 0x00000001 */ +#define BIASCR3_IBIASDAC_1 (0x2UL << BIASCR3_IBIASDAC_Pos) /*!< 0x00000002 */ +#define BIASCR3_IBIASDAC_2 (0x4UL << BIASCR3_IBIASDAC_Pos) /*!< 0x00000004 */ +#define BIASCR3_IBIASDAC_3 (0x8UL << BIASCR3_IBIASDAC_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: DACLCR BASE+0x0A0 *********/ +#define DACLCR_POPCTRL_Pos (5U) +#define DACLCR_POPCTRL_Msk (0x3UL << DACLCR_POPCTRL_Pos) /*!< 0x00000060 */ +#define DACLCR_POPCTRL DACLCR_POPCTRL_Msk +#define DACLCR_POPCTRL_0 (0x1UL << DACLCR_POPCTRL_Pos) /*!< 0x00000020 */ +#define DACLCR_POPCTRL_1 (0x2UL << DACLCR_POPCTRL_Pos) /*!< 0x00000040 */ +#define DACLCR_DACLINITIAL_Pos (4U) +#define DACLCR_DACLINITIAL_Msk (0x1UL << DACLCR_DACLINITIAL_Pos) /*!< 0x00000010 */ +#define DACLCR_DACLINITIAL DACLCR_DACLINITIAL_Msk +#define DACLCR_DACLINITIAL_0 (0x1UL << DACLCR_DACLINITIAL_Pos) /*!< 0x00000010 */ +#define DACLCR_DACLVREFEN_Pos (3U) +#define DACLCR_DACLVREFEN_Msk (0x1UL << DACLCR_DACLVREFEN_Pos) /*!< 0x00000008 */ +#define DACLCR_DACLVREFEN DACLCR_DACLVREFEN_Msk +#define DACLCR_DACLVREFEN_0 (0x1UL << DACLCR_DACLVREFEN_Pos) /*!< 0x00000008 */ +#define DACLCR_DACLBUFEN_Pos (2U) +#define DACLCR_DACLBUFEN_Msk (0x1UL << DACLCR_DACLBUFEN_Pos) /*!< 0x00000004 */ +#define DACLCR_DACLBUFEN DACLCR_DACLBUFEN_Msk +#define DACLCR_DACLBUFEN_0 (0x1UL << DACLCR_DACLBUFEN_Pos) /*!< 0x00000004 */ +#define DACLCR_DACLCLKEN_Pos (1U) +#define DACLCR_DACLCLKEN_Msk (0x1UL << DACLCR_DACLCLKEN_Pos) /*!< 0x00000002 */ +#define DACLCR_DACLCLKEN DACLCR_DACLCLKEN_Msk +#define DACLCR_DACLCLKEN_0 (0x1UL << DACLCR_DACLCLKEN_Pos) /*!< 0x00000002 */ +#define DACLCR_DACLEN_Pos (0U) +#define DACLCR_DACLEN_Msk (0x1UL << DACLCR_DACLEN_Pos) /*!< 0x00000001 */ +#define DACLCR_DACLEN DACLCR_DACLEN_Msk +#define DACLCR_DACLEN_0 (0x1UL << DACLCR_DACLEN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: HPCR BASE+0x0A4 *********/ +#define HPCR_HPLMUTE_Pos (5U) +#define HPCR_HPLMUTE_Msk (0x1UL << HPCR_HPLMUTE_Pos) /*!< 0x00000020 */ +#define HPCR_HPLMUTE HPCR_HPLMUTE_Msk +#define HPCR_HPLMUTE_0 (0x1UL << HPCR_HPLMUTE_Pos) /*!< 0x00000020 */ +#define HPCR_HPLINITIAL_Pos (4U) +#define HPCR_HPLINITIAL_Msk (0x1UL << HPCR_HPLINITIAL_Pos) /*!< 0x00000010 */ +#define HPCR_HPLINITIAL HPCR_HPLINITIAL_Msk +#define HPCR_HPLINITIAL_0 (0x1UL << HPCR_HPLINITIAL_Pos) /*!< 0x00000010 */ +#define HPCR_HPLEN_Pos (0U) +#define HPCR_HPLEN_Msk (0x1UL << HPCR_HPLEN_Pos) /*!< 0x00000001 */ +#define HPCR_HPLEN HPCR_HPLEN_Msk +#define HPCR_HPLEN_0 (0x1UL << HPCR_HPLEN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: HPDSR BASE+0x0A8 *********/ +#define HPDSR_HPLDRV_Pos (0U) +#define HPDSR_HPLDRV_Msk (0xfUL << HPDSR_HPLDRV_Pos) /*!< 0x0000000f */ +#define HPDSR_HPLDRV HPDSR_HPLDRV_Msk +#define HPDSR_HPLDRV_0 (0x1UL << HPDSR_HPLDRV_Pos) /*!< 0x00000001 */ +#define HPDSR_HPLDRV_1 (0x2UL << HPDSR_HPLDRV_Pos) /*!< 0x00000002 */ +#define HPDSR_HPLDRV_2 (0x4UL << HPDSR_HPLDRV_Pos) /*!< 0x00000004 */ +#define HPDSR_HPLDRV_3 (0x8UL << HPDSR_HPLDRV_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: HPGR BASE+0x0AC *********/ +#define HPGR_HPLGAIN_Pos (0U) +#define HPGR_HPLGAIN_Msk (0x1fUL << HPGR_HPLGAIN_Pos) /*!< 0x0000001f */ +#define HPGR_HPLGAIN HPGR_HPLGAIN_Msk +#define HPGR_HPLGAIN_0 (0x1UL << HPGR_HPLGAIN_Pos) /*!< 0x00000001 */ +#define HPGR_HPLGAIN_1 (0x2UL << HPGR_HPLGAIN_Pos) /*!< 0x00000002 */ +#define HPGR_HPLGAIN_2 (0x4UL << HPGR_HPLGAIN_Pos) /*!< 0x00000004 */ +#define HPGR_HPLGAIN_3 (0x8UL << HPGR_HPLGAIN_Pos) /*!< 0x00000008 */ +#define HPGR_HPLGAIN_4 (0x10UL << HPGR_HPLGAIN_Pos) /*!< 0x00000010 */ + +/********* Register BitField Details: ADCLCR BASE+0x0C0 *********/ +#define ADCLCR_ADCLSRC_Pos (5U) +#define ADCLCR_ADCLSRC_Msk (0x3UL << ADCLCR_ADCLSRC_Pos) /*!< 0x00000060 */ +#define ADCLCR_ADCLSRC ADCLCR_ADCLSRC_Msk +#define ADCLCR_ADCLSRC_0 (0x1UL << ADCLCR_ADCLSRC_Pos) /*!< 0x00000020 */ +#define ADCLCR_ADCLSRC_1 (0x2UL << ADCLCR_ADCLSRC_Pos) /*!< 0x00000040 */ +#define ADCLCR_ADCLINITIAL_Pos (4U) +#define ADCLCR_ADCLINITIAL_Msk (0x1UL << ADCLCR_ADCLINITIAL_Pos) /*!< 0x00000010 */ +#define ADCLCR_ADCLINITIAL ADCLCR_ADCLINITIAL_Msk +#define ADCLCR_ADCLINITIAL_0 (0x1UL << ADCLCR_ADCLINITIAL_Pos) /*!< 0x00000010 */ +#define ADCLCR_ZERODETEN_Pos (3U) +#define ADCLCR_ZERODETEN_Msk (0x1UL << ADCLCR_ZERODETEN_Pos) /*!< 0x00000008 */ +#define ADCLCR_ZERODETEN ADCLCR_ZERODETEN_Msk +#define ADCLCR_ZERODETEN_0 (0x1UL << ADCLCR_ZERODETEN_Pos) /*!< 0x00000008 */ +#define ADCLCR_ADCLBUFEN_Pos (2U) +#define ADCLCR_ADCLBUFEN_Msk (0x1UL << ADCLCR_ADCLBUFEN_Pos) /*!< 0x00000004 */ +#define ADCLCR_ADCLBUFEN ADCLCR_ADCLBUFEN_Msk +#define ADCLCR_ADCLBUFEN_0 (0x1UL << ADCLCR_ADCLBUFEN_Pos) /*!< 0x00000004 */ +#define ADCLCR_ADCLCLKEN_Pos (1U) +#define ADCLCR_ADCLCLKEN_Msk (0x1UL << ADCLCR_ADCLCLKEN_Pos) /*!< 0x00000002 */ +#define ADCLCR_ADCLCLKEN ADCLCR_ADCLCLKEN_Msk +#define ADCLCR_ADCLCLKEN_0 (0x1UL << ADCLCR_ADCLCLKEN_Pos) /*!< 0x00000002 */ +#define ADCLCR_ADCLEN_Pos (0U) +#define ADCLCR_ADCLEN_Msk (0x1UL << ADCLCR_ADCLEN_Pos) /*!< 0x00000001 */ +#define ADCLCR_ADCLEN ADCLCR_ADCLEN_Msk +#define ADCLCR_ADCLEN_0 (0x1UL << ADCLCR_ADCLEN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: MICCR BASE+0x0C4 *********/ +#define MICCR_SEEN_Pos (5U) +#define MICCR_SEEN_Msk (0x1UL << MICCR_SEEN_Pos) /*!< 0x00000020 */ +#define MICCR_SEEN MICCR_SEEN_Msk +#define MICCR_SEEN_0 (0x1UL << MICCR_SEEN_Pos) /*!< 0x00000020 */ +#define MICCR_MICLMUTE_Pos (4U) +#define MICCR_MICLMUTE_Msk (0x1UL << MICCR_MICLMUTE_Pos) /*!< 0x00000010 */ +#define MICCR_MICLMUTE MICCR_MICLMUTE_Msk +#define MICCR_MICLMUTE_0 (0x1UL << MICCR_MICLMUTE_Pos) /*!< 0x00000010 */ +#define MICCR_MICLINITIAL_Pos (3U) +#define MICCR_MICLINITIAL_Msk (0x1UL << MICCR_MICLINITIAL_Pos) /*!< 0x00000008 */ +#define MICCR_MICLINITIAL MICCR_MICLINITIAL_Msk +#define MICCR_MICLINITIAL_0 (0x1UL << MICCR_MICLINITIAL_Pos) /*!< 0x00000008 */ +#define MICCR_ALCLINITIAL_Pos (2U) +#define MICCR_ALCLINITIAL_Msk (0x1UL << MICCR_ALCLINITIAL_Pos) /*!< 0x00000004 */ +#define MICCR_ALCLINITIAL MICCR_ALCLINITIAL_Msk +#define MICCR_ALCLINITIAL_0 (0x1UL << MICCR_ALCLINITIAL_Pos) /*!< 0x00000004 */ +#define MICCR_MICLEN_Pos (1U) +#define MICCR_MICLEN_Msk (0x1UL << MICCR_MICLEN_Pos) /*!< 0x00000002 */ +#define MICCR_MICLEN MICCR_MICLEN_Msk +#define MICCR_MICLEN_0 (0x1UL << MICCR_MICLEN_Pos) /*!< 0x00000002 */ +#define MICCR_ALCLEN_Pos (0U) +#define MICCR_ALCLEN_Msk (0x1UL << MICCR_ALCLEN_Pos) /*!< 0x00000001 */ +#define MICCR_ALCLEN MICCR_ALCLEN_Msk +#define MICCR_ALCLEN_0 (0x1UL << MICCR_ALCLEN_Pos) /*!< 0x00000001 */ + +/********* Register BitField Details: ALCGR BASE+0x0C8 *********/ +#define ALCGR_ALCLGAIN_Pos (0U) +#define ALCGR_ALCLGAIN_Msk (0x1fUL << ALCGR_ALCLGAIN_Pos) /*!< 0x0000001f */ +#define ALCGR_ALCLGAIN ALCGR_ALCLGAIN_Msk +#define ALCGR_ALCLGAIN_0 (0x1UL << ALCGR_ALCLGAIN_Pos) /*!< 0x00000001 */ +#define ALCGR_ALCLGAIN_1 (0x2UL << ALCGR_ALCLGAIN_Pos) /*!< 0x00000002 */ +#define ALCGR_ALCLGAIN_2 (0x4UL << ALCGR_ALCLGAIN_Pos) /*!< 0x00000004 */ +#define ALCGR_ALCLGAIN_3 (0x8UL << ALCGR_ALCLGAIN_Pos) /*!< 0x00000008 */ +#define ALCGR_ALCLGAIN_4 (0x10UL << ALCGR_ALCLGAIN_Pos) /*!< 0x00000010 */ + +/********* Register BitField Details: MICGR BASE+0x0CC *********/ +#define MICGR_MICLGAIN_Pos (0U) +#define MICGR_MICLGAIN_Msk (0x3UL << MICGR_MICLGAIN_Pos) /*!< 0x00000003 */ +#define MICGR_MICLGAIN MICGR_MICLGAIN_Msk +#define MICGR_MICLGAIN_0 (0x1UL << MICGR_MICLGAIN_Pos) /*!< 0x00000001 */ +#define MICGR_MICLGAIN_1 (0x2UL << MICGR_MICLGAIN_Pos) /*!< 0x00000002 */ + +/********* Register BitField Details: AGCCR1 BASE+0x100 *********/ +#define AGCCR1_GAINATTACK_Pos (6U) +#define AGCCR1_GAINATTACK_Msk (0x1UL << AGCCR1_GAINATTACK_Pos) /*!< 0x00000040 */ +#define AGCCR1_GAINATTACK AGCCR1_GAINATTACK_Msk +#define AGCCR1_GAINATTACK_0 (0x1UL << AGCCR1_GAINATTACK_Pos) /*!< 0x00000040 */ +#define AGCCR1_CTRLMETH_Pos (4U) +#define AGCCR1_CTRLMETH_Msk (0x3UL << AGCCR1_CTRLMETH_Pos) /*!< 0x00000030 */ +#define AGCCR1_CTRLMETH AGCCR1_CTRLMETH_Msk +#define AGCCR1_CTRLMETH_0 (0x1UL << AGCCR1_CTRLMETH_Pos) /*!< 0x00000010 */ +#define AGCCR1_CTRLMETH_1 (0x2UL << AGCCR1_CTRLMETH_Pos) /*!< 0x00000020 */ +#define AGCCR1_HOLDTIME_Pos (0U) +#define AGCCR1_HOLDTIME_Msk (0xfUL << AGCCR1_HOLDTIME_Pos) /*!< 0x0000000f */ +#define AGCCR1_HOLDTIME AGCCR1_HOLDTIME_Msk +#define AGCCR1_HOLDTIME_0 (0x1UL << AGCCR1_HOLDTIME_Pos) /*!< 0x00000001 */ +#define AGCCR1_HOLDTIME_1 (0x2UL << AGCCR1_HOLDTIME_Pos) /*!< 0x00000002 */ +#define AGCCR1_HOLDTIME_2 (0x4UL << AGCCR1_HOLDTIME_Pos) /*!< 0x00000004 */ +#define AGCCR1_HOLDTIME_3 (0x8UL << AGCCR1_HOLDTIME_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: AGCCR2 BASE+0x104 *********/ +#define AGCCR2_DECAYTIME_Pos (4U) +#define AGCCR2_DECAYTIME_Msk (0xfUL << AGCCR2_DECAYTIME_Pos) /*!< 0x000000f0 */ +#define AGCCR2_DECAYTIME AGCCR2_DECAYTIME_Msk +#define AGCCR2_DECAYTIME_0 (0x1UL << AGCCR2_DECAYTIME_Pos) /*!< 0x00000010 */ +#define AGCCR2_DECAYTIME_1 (0x2UL << AGCCR2_DECAYTIME_Pos) /*!< 0x00000020 */ +#define AGCCR2_DECAYTIME_2 (0x4UL << AGCCR2_DECAYTIME_Pos) /*!< 0x00000040 */ +#define AGCCR2_DECAYTIME_3 (0x8UL << AGCCR2_DECAYTIME_Pos) /*!< 0x00000080 */ +#define AGCCR2_ATTACKTIME_Pos (0U) +#define AGCCR2_ATTACKTIME_Msk (0xfUL << AGCCR2_ATTACKTIME_Pos) /*!< 0x0000000f */ +#define AGCCR2_ATTACKTIME AGCCR2_ATTACKTIME_Msk +#define AGCCR2_ATTACKTIME_0 (0x1UL << AGCCR2_ATTACKTIME_Pos) /*!< 0x00000001 */ +#define AGCCR2_ATTACKTIME_1 (0x2UL << AGCCR2_ATTACKTIME_Pos) /*!< 0x00000002 */ +#define AGCCR2_ATTACKTIME_2 (0x4UL << AGCCR2_ATTACKTIME_Pos) /*!< 0x00000004 */ +#define AGCCR2_ATTACKTIME_3 (0x8UL << AGCCR2_ATTACKTIME_Pos) /*!< 0x00000008 */ + +/********* Register BitField Details: AGCCR3 BASE+0x108 *********/ +#define AGCCR3_AGMODE_Pos (7U) +#define AGCCR3_AGMODE_Msk (0x1UL << AGCCR3_AGMODE_Pos) /*!< 0x00000080 */ +#define AGCCR3_AGMODE AGCCR3_AGMODE_Msk +#define AGCCR3_AGMODE_0 (0x1UL << AGCCR3_AGMODE_Pos) /*!< 0x00000080 */ +#define AGCCR3_ZECREN_Pos (6U) +#define AGCCR3_ZECREN_Msk (0x1UL << AGCCR3_ZECREN_Pos) /*!< 0x00000040 */ +#define AGCCR3_ZECREN AGCCR3_ZECREN_Msk +#define AGCCR3_ZECREN_0 (0x1UL << AGCCR3_ZECREN_Pos) /*!< 0x00000040 */ +#define AGCCR3_REMODE_Pos (5U) +#define AGCCR3_REMODE_Msk (0x1UL << AGCCR3_REMODE_Pos) /*!< 0x00000020 */ +#define AGCCR3_REMODE AGCCR3_REMODE_Msk +#define AGCCR3_REMODE_0 (0x1UL << AGCCR3_REMODE_Pos) /*!< 0x00000020 */ +#define AGCCR3_FASTDEC_Pos (4U) +#define AGCCR3_FASTDEC_Msk (0x1UL << AGCCR3_FASTDEC_Pos) /*!< 0x00000010 */ +#define AGCCR3_FASTDEC AGCCR3_FASTDEC_Msk +#define AGCCR3_FASTDEC_0 (0x1UL << AGCCR3_FASTDEC_Pos) /*!< 0x00000010 */ +#define AGCCR3_NSGATE_Pos (3U) +#define AGCCR3_NSGATE_Msk (0x1UL << AGCCR3_NSGATE_Pos) /*!< 0x00000008 */ +#define AGCCR3_NSGATE AGCCR3_NSGATE_Msk +#define AGCCR3_NSGATE_0 (0x1UL << AGCCR3_NSGATE_Pos) /*!< 0x00000008 */ +#define AGCCR3_NSTHRE_Pos (0U) +#define AGCCR3_NSTHRE_Msk (0x7UL << AGCCR3_NSTHRE_Pos) /*!< 0x00000007 */ +#define AGCCR3_NSTHRE AGCCR3_NSTHRE_Msk +#define AGCCR3_NSTHRE_0 (0x1UL << AGCCR3_NSTHRE_Pos) /*!< 0x00000001 */ +#define AGCCR3_NSTHRE_1 (0x2UL << AGCCR3_NSTHRE_Pos) /*!< 0x00000002 */ +#define AGCCR3_NSTHRE_2 (0x4UL << AGCCR3_NSTHRE_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: PGAGR BASE+0x10C *********/ +#define PGAGR_LPGAZECR_Pos (5U) +#define PGAGR_LPGAZECR_Msk (0x1UL << PGAGR_LPGAZECR_Pos) /*!< 0x00000020 */ +#define PGAGR_LPGAZECR PGAGR_LPGAZECR_Msk +#define PGAGR_LPGAZECR_0 (0x1UL << PGAGR_LPGAZECR_Pos) /*!< 0x00000020 */ +#define PGAGR_LPGAGAIN_Pos (0U) +#define PGAGR_LPGAGAIN_Msk (0x1fUL << PGAGR_LPGAGAIN_Pos) /*!< 0x0000001f */ +#define PGAGR_LPGAGAIN PGAGR_LPGAGAIN_Msk +#define PGAGR_LPGAGAIN_0 (0x1UL << PGAGR_LPGAGAIN_Pos) /*!< 0x00000001 */ +#define PGAGR_LPGAGAIN_1 (0x2UL << PGAGR_LPGAGAIN_Pos) /*!< 0x00000002 */ +#define PGAGR_LPGAGAIN_2 (0x4UL << PGAGR_LPGAGAIN_Pos) /*!< 0x00000004 */ +#define PGAGR_LPGAGAIN_3 (0x8UL << PGAGR_LPGAGAIN_Pos) /*!< 0x00000008 */ +#define PGAGR_LPGAGAIN_4 (0x10UL << PGAGR_LPGAGAIN_Pos) /*!< 0x00000010 */ + +/********* Register BitField Details: AGCSRR BASE+0x110 *********/ +#define AGCSRR_SLOWCLK_Pos (3U) +#define AGCSRR_SLOWCLK_Msk (0x1UL << AGCSRR_SLOWCLK_Pos) /*!< 0x00000008 */ +#define AGCSRR_SLOWCLK AGCSRR_SLOWCLK_Msk +#define AGCSRR_SLOWCLK_0 (0x1UL << AGCSRR_SLOWCLK_Pos) /*!< 0x00000008 */ +#define AGCSRR_APPRSR_Pos (0U) +#define AGCSRR_APPRSR_Msk (0x7UL << AGCSRR_APPRSR_Pos) /*!< 0x00000007 */ +#define AGCSRR_APPRSR AGCSRR_APPRSR_Msk +#define AGCSRR_APPRSR_0 (0x1UL << AGCSRR_APPRSR_Pos) /*!< 0x00000001 */ +#define AGCSRR_APPRSR_1 (0x2UL << AGCSRR_APPRSR_Pos) /*!< 0x00000002 */ +#define AGCSRR_APPRSR_2 (0x4UL << AGCSRR_APPRSR_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: AGCMAXLR BASE+0x114 *********/ +#define AGCMAXLR_MAXLOW_Pos (0U) +#define AGCMAXLR_MAXLOW_Msk (0xffUL << AGCMAXLR_MAXLOW_Pos) /*!< 0x000000ff */ +#define AGCMAXLR_MAXLOW AGCMAXLR_MAXLOW_Msk +#define AGCMAXLR_MAXLOW_0 (0x1UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000001 */ +#define AGCMAXLR_MAXLOW_1 (0x2UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000002 */ +#define AGCMAXLR_MAXLOW_2 (0x4UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000004 */ +#define AGCMAXLR_MAXLOW_3 (0x8UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000008 */ +#define AGCMAXLR_MAXLOW_4 (0x10UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000010 */ +#define AGCMAXLR_MAXLOW_5 (0x20UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000020 */ +#define AGCMAXLR_MAXLOW_6 (0x40UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000040 */ +#define AGCMAXLR_MAXLOW_7 (0x80UL << AGCMAXLR_MAXLOW_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: AGCMAXHR BASE+0x118 *********/ +#define AGCMAXHR_MAXHIGH_Pos (0U) +#define AGCMAXHR_MAXHIGH_Msk (0xffUL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x000000ff */ +#define AGCMAXHR_MAXHIGH AGCMAXHR_MAXHIGH_Msk +#define AGCMAXHR_MAXHIGH_0 (0x1UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000001 */ +#define AGCMAXHR_MAXHIGH_1 (0x2UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000002 */ +#define AGCMAXHR_MAXHIGH_2 (0x4UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000004 */ +#define AGCMAXHR_MAXHIGH_3 (0x8UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000008 */ +#define AGCMAXHR_MAXHIGH_4 (0x10UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000010 */ +#define AGCMAXHR_MAXHIGH_5 (0x20UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000020 */ +#define AGCMAXHR_MAXHIGH_6 (0x40UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000040 */ +#define AGCMAXHR_MAXHIGH_7 (0x80UL << AGCMAXHR_MAXHIGH_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: AGCMINLR BASE+0x11C *********/ +#define AGCMINLR_MINLOW_Pos (0U) +#define AGCMINLR_MINLOW_Msk (0xffUL << AGCMINLR_MINLOW_Pos) /*!< 0x000000ff */ +#define AGCMINLR_MINLOW AGCMINLR_MINLOW_Msk +#define AGCMINLR_MINLOW_0 (0x1UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000001 */ +#define AGCMINLR_MINLOW_1 (0x2UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000002 */ +#define AGCMINLR_MINLOW_2 (0x4UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000004 */ +#define AGCMINLR_MINLOW_3 (0x8UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000008 */ +#define AGCMINLR_MINLOW_4 (0x10UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000010 */ +#define AGCMINLR_MINLOW_5 (0x20UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000020 */ +#define AGCMINLR_MINLOW_6 (0x40UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000040 */ +#define AGCMINLR_MINLOW_7 (0x80UL << AGCMINLR_MINLOW_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: AGCMINHR BASE+0x120 *********/ +#define AGCMINHR_MINHIGH_Pos (0U) +#define AGCMINHR_MINHIGH_Msk (0xffUL << AGCMINHR_MINHIGH_Pos) /*!< 0x000000ff */ +#define AGCMINHR_MINHIGH AGCMINHR_MINHIGH_Msk +#define AGCMINHR_MINHIGH_0 (0x1UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000001 */ +#define AGCMINHR_MINHIGH_1 (0x2UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000002 */ +#define AGCMINHR_MINHIGH_2 (0x4UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000004 */ +#define AGCMINHR_MINHIGH_3 (0x8UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000008 */ +#define AGCMINHR_MINHIGH_4 (0x10UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000010 */ +#define AGCMINHR_MINHIGH_5 (0x20UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000020 */ +#define AGCMINHR_MINHIGH_6 (0x40UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000040 */ +#define AGCMINHR_MINHIGH_7 (0x80UL << AGCMINHR_MINHIGH_Pos) /*!< 0x00000080 */ + +/********* Register BitField Details: AGCGR BASE+0x124 *********/ +#define AGCGR_AGCEN_Pos (6U) +#define AGCGR_AGCEN_Msk (0x1UL << AGCGR_AGCEN_Pos) /*!< 0x00000040 */ +#define AGCGR_AGCEN AGCGR_AGCEN_Msk +#define AGCGR_AGCEN_0 (0x1UL << AGCGR_AGCEN_Pos) /*!< 0x00000040 */ +#define AGCGR_PGAINMAX_Pos (3U) +#define AGCGR_PGAINMAX_Msk (0x7UL << AGCGR_PGAINMAX_Pos) /*!< 0x00000038 */ +#define AGCGR_PGAINMAX AGCGR_PGAINMAX_Msk +#define AGCGR_PGAINMAX_0 (0x1UL << AGCGR_PGAINMAX_Pos) /*!< 0x00000008 */ +#define AGCGR_PGAINMAX_1 (0x2UL << AGCGR_PGAINMAX_Pos) /*!< 0x00000010 */ +#define AGCGR_PGAINMAX_2 (0x4UL << AGCGR_PGAINMAX_Pos) /*!< 0x00000020 */ +#define AGCGR_PGAINMIN_Pos (0U) +#define AGCGR_PGAINMIN_Msk (0x7UL << AGCGR_PGAINMIN_Pos) /*!< 0x00000007 */ +#define AGCGR_PGAINMIN AGCGR_PGAINMIN_Msk +#define AGCGR_PGAINMIN_0 (0x1UL << AGCGR_PGAINMIN_Pos) /*!< 0x00000001 */ +#define AGCGR_PGAINMIN_1 (0x2UL << AGCGR_PGAINMIN_Pos) /*!< 0x00000002 */ +#define AGCGR_PGAINMIN_2 (0x4UL << AGCGR_PGAINMIN_Pos) /*!< 0x00000004 */ + +/********* Register BitField Details: ALCOGR BASE+0x138 *********/ +#define ALCOGR_ALCOGAIN_Pos (0U) +#define ALCOGR_ALCOGAIN_Msk (0xfUL << ALCOGR_ALCOGAIN_Pos) /*!< 0x0000000f */ +#define ALCOGR_ALCOGAIN ALCOGR_ALCOGAIN_Msk +#define ALCOGR_ALCOGAIN_0 (0x1UL << ALCOGR_ALCOGAIN_Pos) /*!< 0x00000001 */ +#define ALCOGR_ALCOGAIN_1 (0x2UL << ALCOGR_ALCOGAIN_Pos) /*!< 0x00000002 */ +#define ALCOGR_ALCOGAIN_2 (0x4UL << ALCOGR_ALCOGAIN_Pos) /*!< 0x00000004 */ +#define ALCOGR_ALCOGAIN_3 (0x8UL << ALCOGR_ALCOGAIN_Pos) /*!< 0x00000008 */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus*/ +#endif /* __REG_ICODEC_H__ */ diff --git a/cpu/soc-x2600/include/x2600.h b/cpu/soc-x2600/include/x2600.h index b7bfe8bdd3cef90a6ca964815e7ce8fcd778dbca..6e539f8c708ca37f2011ca5d0ddab7558015a1e1 100755 --- a/cpu/soc-x2600/include/x2600.h +++ b/cpu/soc-x2600/include/x2600.h @@ -22,6 +22,7 @@ #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas /* Include IP regs， 应用所有的模块寄存器定义. */ +#include "icodec.h" #include "cpm.h" #include "gpio.h" #include "i2c.h" @@ -48,6 +49,7 @@ extern "C" { #endif /*< Peripheral memory map */ +#define ICODEC_BASE 0x10021000 /*!< Address base of ICODEC */ #define CPM_BASE 0x10000000 /*!< Address base of CPM */ #define PA_BASE 0x13601000 /*!< Address base of GPIO Port A */ #define PB_BASE 0x13602000 /*!< Address base of GPIO Port B */ @@ -92,6 +94,7 @@ extern "C" { /*< Peripheral declarations */ #ifdef CORE_RISCV +#define ICODEC_Instance ((ICODEC_TypeDef *) (ICODEC_BASE)) #define CPM_Instance ((CPM_TypeDef *) (CPM_BASE )) #define PA_Instance ((GPIO_TypeDef *) (PA_BASE )) #define PB_Instance ((GPIO_TypeDef *) (PB_BASE )) @@ -135,6 +138,7 @@ extern "C" { #define MIPI_DPHY_TX_Instance ((DPHY_TX_TypeDef *) (MIPI_DPHY_TX_BASE)) #else +#define ICODEC_Instance ((ICODEC_TypeDef *) (ICODEC_BASE | 0xa0000000)) #define CPM_Instance ((CPM_TypeDef *) (CPM_BASE | 0xa0000000)) #define PA_Instance ((GPIO_TypeDef *) (PA_BASE | 0xa0000000)) #define PB_Instance ((GPIO_TypeDef *) (PB_BASE | 0xa0000000)) diff --git a/drivers/drivers-x2600/include/x2600_hal_conf.h b/drivers/drivers-x2600/include/x2600_hal_conf.h index d629d302878e0cbbd4c63f025f22df366126768c..16a38380588e27f1595ec4c6e42bdaee91676157 100644 --- a/drivers/drivers-x2600/include/x2600_hal_conf.h +++ b/drivers/drivers-x2600/include/x2600_hal_conf.h @@ -18,6 +18,7 @@ #define HAL_DPU_MIPI_ENABLED #define HAL_AIC_ENABLED #define HAL_SPI_ENABLED +#define HAL_ICODEC_ENABLED #if 0 #define HAL_MSC_ENABLED #define HAL_WDT_ENABLED @@ -106,6 +107,10 @@ #include "x2600_hal_aic.h" #endif +#ifdef HAL_ICODEC_ENABLED +#include "x2600_hal_icodec.h" +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/drivers/drivers-x2600/include/x2600_hal_icodec.h b/drivers/drivers-x2600/include/x2600_hal_icodec.h new file mode 100644 index 0000000000000000000000000000000000000000..574264d15809143c3a33b4735c9b7882045719f4 --- /dev/null +++ b/drivers/drivers-x2600/include/x2600_hal_icodec.h @@ -0,0 +1,416 @@ +/** + * @file x2600_hal_icodec.h + * @author MPU系统软件部团队 + * @brief [X2600 HAL ICODEC驱动头文件] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X2600_HAL_ICODEC_H__ +#define __X2600_HAL_ICODEC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @addtogroup group_ICODEC + * @{ + */ + +/** + * @addtogroup g_X2600_ICODEC_HAL_Driver ICODEC HAL 驱动 + * @{ + */ + +/* 1. 头文件 (Includes)----------------------------------------------- */ +#include "x2600_hal_def.h" + +/* 2. 导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup ICODEC_exported_types ICODEC 导出的类型 (Exported Types) + * @{ + */ + +/** + * @brief ICODEC 操作模式选择 + */ +typedef enum { + HAL_ICODEC_OPERATION_MODE_I2S = 0x00U, /*!< 选择I2S操作模式 */ + HAL_ICODEC_OPERATION_MODE_MSB_JUSTIFIED = 0x01U, /*!< 选择MSB_JUSTIFIED操作模式 */ +} HAL_ICODECOperationModeTypeDef; + +/** + * @brief ICODEC 录/放音选择 + */ +typedef enum { + HAL_ICODEC_STREAM_ONLY_PLAYBACK = 0x00U, /*!< 仅放音 */ + HAL_ICODEC_STREAM_ONLY_CAPTURE = 0x01U, /*!< 仅录音 */ + HAL_ICODEC_STREAM_PLAYBACK_CAPTURE = 0x02U, /*!< 录音和放音 */ +} HAL_ICODECStreamTypeDef; + + +/** + * @brief ICODEC 采样速率 + */ +typedef enum { + HAL_ICODEC_SAMPLE_RATE_8000 = 0x00U, + HAL_ICODEC_SAMPLE_RATE_16000 = 0x01U, + HAL_ICODEC_SAMPLE_RATE_24000 = 0x02U, + HAL_ICODEC_SAMPLE_RATE_32000 = 0x03U, + HAL_ICODEC_SAMPLE_RATE_44100 = 0x04U, + HAL_ICODEC_SAMPLE_RATE_48000 = 0x05U, + HAL_ICODEC_SAMPLE_RATE_88200 = 0x06U, + HAL_ICODEC_SAMPLE_RATE_96000 = 0x07U, + HAL_ICODEC_SAMPLE_RATE_NUMS = 0x08U, +} HAL_ICODECSampleRateTypeDef; + +/** + * @brief ICODEC 数据格式 + */ +typedef enum { + HAL_ICODEC_DATA_FMT_S16LE = 0x00U, + HAL_ICODEC_DATA_FMT_S20LE = 0x01U, + HAL_ICODEC_DATA_FMT_S24LE = 0x02U, + HAL_ICODEC_DATA_FMT_NUMS = 0x03U, +} HAL_ICODECDataFormatTypeDef; + + +/** + * @brief ICODEC 通道选择 + */ +typedef enum { + HAL_ICODEC_MONO_LEFT = 0x00U, /*!< 左通道数据 */ + HAL_ICODEC_MONO_RIGHT = 0x01U, /*!< 右通道数据 */ + HAL_ICODEC_STEREO = 0x02U, /*!< 双声道 */ +} HAL_ICODECChannelSelectTypeDef; + +/** + * @brief ICODEC 放音配置信息结构体 + */ +typedef struct __ICODEC_DACConfInfoTypeDef { + HAL_ICODECSampleRateTypeDef SampleRates; /*!< 采样速率 */ + HAL_ICODECDataFormatTypeDef Format; /*!< 数据格式 */ + unsigned int dgain; /*!< 数字增益值 */ +} HAL_ICODEC_DACConfInfoTypeDef; + +/** + * @brief ICODEC 录音配置信息结构体 + */ +typedef struct __ICODEC_ADCConfInfoTypeDef { + HAL_ICODECChannelSelectTypeDef channel; /*!< 通道选择 */ + HAL_ICODECDataFormatTypeDef Format; /*!< 数据格式 */ + unsigned int dgain; /*!< 数字增益值 */ +} HAL_ICODEC_ADCConfInfoTypeDef; + + +/** + * @brief ICODEC 句柄 + */ +typedef struct __ICODEC_HandleTypeDef { + ICODEC_TypeDef *Instance; /*!< ICODEC寄存器基地址 */ + // __IO HAL_ICODECStateTypeDef state; /*!< ICODEC状态结构体 */ + HAL_ICODECOperationModeTypeDef Interface; /*!< ICODEC操作模式选择 */ + HAL_ICODECStreamTypeDef Stream; /*!< ICODEC流选择 */ + + HAL_ICODEC_DACConfInfoTypeDef Playback; /*!< ICODEC放音配置信息 */ + HAL_ICODEC_ADCConfInfoTypeDef Capture; /*!< ICODEC录音配置信息 */ +} ICODEC_HandleTypeDef; + +/** + * @} + */ +/* 3. 导出常量定义 Exported Constants ----------------------------------- */ +/** + * @defgroup ICODEC_exported_constants ICODEC 导出的常量 Exported Constants + * @{ + */ + + + + +/** + * @} + */ +/* 4. 导出宏定义 Exported Macros --------------------------------------- */ +/** + * @defgroup ICODEC_exported_macros ICODEC 导出宏 Exported Macros + * @{ + */ +#define ICODEC_READ_BITS(REG, MASK, OFFSET) ((READ_REG(REG) & MASK) >> OFFSET) + +#define ICODEC_WRITE_BITS(REG, VAL, MASK, OFFSET) \ + do { \ + volatile unsigned int reg_tmp; \ + reg_tmp = READ_REG(REG); \ + reg_tmp &= ~(MASK); \ + reg_tmp |= ((VAL) << OFFSET) & MASK; \ + WRITE_REG(REG, reg_tmp); \ + } while(0) + +/* RSTR */ +#define __HAL_ICODEC_ADC_RST(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->RSTR, RSTR_ADCRST) +#define __HAL_ICODEC_ADC_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->RSTR, RSTR_ADCRST) + +#define __HAL_ICODEC_DAC_RST(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->RSTR, RSTR_DACRST) +#define __HAL_ICODEC_DAC_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->RSTR, RSTR_DACRST) + +#define __HAL_ICODEC_SYS_RST(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->RSTR, RSTR_SYSRST) +#define __HAL_ICODEC_SYS_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->RSTR, RSTR_SYSRST) + +/* DACCR1 */ +#define I2S_WL2REG(WL) (((WL) > 16 ? (WL) / 12 : (WL) / 20)) /* WL : 16、20、24 */ +#define __HAL_ICODEC_DAC_SET_I2SWL(__HANDLE__, WL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACCR1, I2S_WL2REG(WL), DACCR1_I2SWL_Msk, DACCR1_I2SWL_Pos) + +#define __HAL_ICODEC_DAC_SELECT_I2S_MODE(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACCR1, 0x2, DACCR1_I2SFMT_Msk, DACCR1_I2SFMT_Pos) +#define __HAL_ICODEC_DAC_SELECT_MSB_MODE(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACCR1, 0x1, DACCR1_I2SFMT_Msk, DACCR1_I2SFMT_Pos) + +/* DACCR2 */ +#define __HAL_ICODEC_DAC_SEL_FUNC_SLAVE_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACCR2, DACCR2_FUNCMSTEN) +#define __HAL_ICODEC_DAC_SEL_FUNC_MASTER_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACCR2, DACCR2_FUNCMSTEN) +#define __HAL_ICODEC_DAC_SEL_PIN_SLAVE_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACCR2, DACCR2_PINMSTEN) +#define __HAL_ICODEC_DAC_SEL_PIN_MASTER_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACCR2, DACCR2_PINMSTEN) + +/* DACCR3 */ +#define MUTE_SR2REG(SR) (((SR) > 48000 ? (SR) / 13000 : (SR) / 9000))/* SR : 8k、16k、24k、32k、44.1k、48k、88.2k、96k */ +#define __HAL_ICODEC_DAC_SET_MUTESR(__HANDLE__, SR) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACCR3, MUTE_SR2REG(SR), DACCR3_MUTSR_Msk, DACCR3_MUTSR_Pos) + +/* DACCR5 */ +#define __HAL_ICODEC_DAC_MUTE_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACCR5, DACCR5_MUTEL) +#define __HAL_ICODEC_DAC_MUTE_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACCR5, DACCR5_MUTEL) + +/* DACDGR */ +#define __HAL_ICODEC_DAC_SET_DIGGAIN(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACDGR, VAL, DACDGR_DIGGAIN_Msk, DACDGR_DIGGAIN_Pos) +#define __HAL_ICODEC_DAC_GET_DIGGAIN(__HANDLE__) ICODEC_READ_BITS((__HANDLE__)->Instance->DACDGR, DACDGR_DIGGAIN_Msk, DACDGR_DIGGAIN_Pos) + +/* ADCCR1 */ +#define __HAL_ICODEC_ADC_SETLET_RIGHT_DATA(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, 0x3, ADCCR1_I2SDATSEL_Msk, ADCCR1_I2SDATSEL_Pos) +#define __HAL_ICODEC_ADC_SETLET_STEREO_DATA(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, 0x1, ADCCR1_I2SDATSEL_Msk, ADCCR1_I2SDATSEL_Pos) +#define __HAL_ICODEC_ADC_SETLET_LEFT_DATA(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, 0x0, ADCCR1_I2SDATSEL_Msk, ADCCR1_I2SDATSEL_Pos) + +#define __HAL_ICODEC_ADC_SET_I2SWL(__HANDLE__, WL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, I2S_WL2REG(WL), ADCCR1_I2SWL_Msk, ADCCR1_I2SWL_Pos) + +#define __HAL_ICODEC_ADC_SELECT_I2S_MODE(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, 0x2, ADCCR1_I2SFMT_Msk, ADCCR1_I2SFMT_Pos) +#define __HAL_ICODEC_ADC_SELECT_MSB_MODE(__HANDLE__) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCCR1, 0x1, ADCCR1_I2SFMT_Msk, ADCCR1_I2SFMT_Pos) + +/* ADCCR2 */ +#define __HAL_ICODEC_ADC_SEL_FUNC_SLAVE_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCCR2, ADCCR2_FUNCMSTEN) +#define __HAL_ICODEC_ADC_SEL_FUNC_MASTER_MODE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCCR2, ADCCR2_FUNCMSTEN) +#define __HAL_ICODEC_ADC_SEL_PIN_SLAVE_MODE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCCR2, ADCCR2_PINMSTEN) +#define __HAL_ICODEC_ADC_SEL_PIN_MASTER_MDOE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCCR2, ADCCR2_PINMSTEN) + +/* ADCDGR */ +#define __HAL_ICODEC_ADC_SET_DIGGAIN(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ADCDGR, VAL, ADCDGR_DIGGAIN_Msk, ADCDGR_DIGGAIN_Pos) +#define __HAL_ICODEC_ADC_GET_DIGGAIN(__HANDLE__) ICODEC_READ_BITS((__HANDLE__)->Instance->ADCDGR, ADCDGR_DIGGAIN_Msk, ADCDGR_DIGGAIN_Pos) + +/* BIASCR1 */ +#define __HAL_ICODEC_ADCIBIAS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_ADCIBIASEN) +#define __HAL_ICODEC_ADCIBIAS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_ADCIBIASEN) + +#define __HAL_ICODEC_DACIBIAS_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_DACIBIASEN) +#define __HAL_ICODEC_DACIBIAS_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_DACIBIASEN) + +#define __HAL_ICODEC_VREF_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_VREFEN) +#define __HAL_ICODEC_VREF_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->BIASCR1, BIASCR1_VREFEN) + +/* BIASCR2 */ +#define __HAL_ICODEC_SET_SELVREF(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->BIASCR2, VAL, BIASCR2_SELVREF_Msk, BIASCR2_SELVREF_Pos) + +/* BIASCR3 */ + + +/* DACLCR */ +#define __HAL_ICODEC_DACL_POP_CTRL(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->DACLCR, VAL, DACLCR_POPCTRL_Msk, DACLCR_POPCTRL_Pos) + +#define __HAL_ICODEC_DACL_ININIAL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLINITIAL) +#define __HAL_ICODEC_DACL_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLINITIAL) + +#define __HAL_ICODEC_DACLVREF_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLVREFEN) +#define __HAL_ICODEC_DACLVREF_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLVREFEN) + +#define __HAL_ICODEC_DACLBUF_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLBUFEN) +#define __HAL_ICODEC_DACLBUF_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLBUFEN) + +#define __HAL_ICODEC_DACLCLK_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLCLKEN) +#define __HAL_ICODEC_DACLCLK_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLCLKEN) + +#define __HAL_ICODEC_DACL_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLEN) +#define __HAL_ICODEC_DACL_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DACLCR, DACLCR_DACLEN) + +/* HPCR */ +#define __HAL_ICODEC_HPOUTL_MUTE_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLMUTE) +#define __HAL_ICODEC_HPOUTL_MUTE_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLMUTE) + +#define __HAL_ICODEC_HPOUTL_INITIAL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLINITIAL) +#define __HAL_ICODEC_HPOUTL_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLINITIAL) + +#define __HAL_ICODEC_HPOUTL_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLEN) +#define __HAL_ICODEC_HPOUTL_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->HPCR, HPCR_HPLEN) + +/* HPGR */ +#define __HAL_ICODEC_SET_HPLGAIN(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->HPGR, VAL, HPGR_HPLGAIN_Msk, HPGR_HPLGAIN_Pos) + +/* ADCLCR */ +#define __HAL_ICODEC_SEL_ADCL_INPUT_FROM_MIC(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLSRC) +#define __HAL_ICODEC_SEL_ADCL_INPUT_FROM_DAC(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLSRC) + +#define __HAL_ICODEC_ADCL_INITIAL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLINITIAL) +#define __HAL_ICODEC_ADCL_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLINITIAL) + +#define __HAL_ICODEC_ADCL_ZERODET_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ZERODETEN) +#define __HAL_ICODEC_ADCL_ZERODET_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ZERODETEN) + +#define __HAL_ICODEC_ADCLBUF_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLBUFEN) +#define __HAL_ICODEC_ADCLBUF_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLBUFEN) + +#define __HAL_ICODEC_ADCLCLK_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLCLKEN) +#define __HAL_ICODEC_ADCLCLK_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLCLKEN) + +#define __HAL_ICODEC_ADCL_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLEN) +#define __HAL_ICODEC_ADCL_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->ADCLCR, ADCLCR_ADCLEN) + +/* MICCR */ +#define __HAL_ICODEC_MICL_MUTE_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLMUTE) +#define __HAL_ICODEC_MICL_MUTE_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLMUTE) +#define __HAL_ICODEC_MICL_INITIAL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLINITIAL) +#define __HAL_ICODEC_MICL_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLINITIAL) +#define __HAL_ICODEC_ALCL_INITIAL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MICCR, MICCR_ALCLINITIAL) +#define __HAL_ICODEC_ALCL_WORK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MICCR, MICCR_ALCLINITIAL) +#define __HAL_ICODEC_MICL_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLEN) +#define __HAL_ICODEC_MICL_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MICCR, MICCR_MICLEN) +#define __HAL_ICODEC_ALCL_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->MICCR, MICCR_ALCLEN) +#define __HAL_ICODEC_ALCL_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->MICCR, MICCR_ALCLEN) + +/* ALCGR */ +#define __HAL_ICODEC_SET_ALCLGAIN(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->ALCGR, VAL, ALCGR_ALCLGAIN_Msk, HPGR_HPLGAIN_Pos) + +/* MICGR */ +#define __HAL_ICODEC_SET_MICLGAIN(__HANDLE__, VAL) ICODEC_WRITE_BITS((__HANDLE__)->Instance->MICGR, VAL, MICGR_MICLGAIN_Msk, MICGR_MICLGAIN_Pos) + +/** + * @} + */ +/* 5. 导出函数申明 Exported Funcs --------------------------------------- */ +/** + * @defgroup ICODEC_exported_funcs ICODEC 导出函数申明 Exported Funcs + * @{ + */ +HAL_StatusTypeDef HAL_ICODEC_PowerOn(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_PowerOff(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_Configure(ICODEC_HandleTypeDef* hicodec); +HAL_StatusTypeDef HAL_ICODEC_DAC_Enable(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_DAC_Disable(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_DAC_SetDigGain(ICODEC_HandleTypeDef* hicodec, unsigned int dgain); +unsigned int HAL_ICODEC_DAC_GetDigGain(ICODEC_HandleTypeDef* hicodec); +HAL_StatusTypeDef HAL_ICODEC_ADC_Enable(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_ADC_Disable(ICODEC_HandleTypeDef *hicodec); +HAL_StatusTypeDef HAL_ICODEC_ADC_SetDigGain(ICODEC_HandleTypeDef* hicodec, unsigned int dgain); +unsigned int HAL_ICODEC_ADC_GetDigGain(ICODEC_HandleTypeDef* hicodec); +HAL_StatusTypeDef HAL_ICODEC_DumpRegisters(ICODEC_HandleTypeDef *hicodec); + +/** + * @} + */ +/* 6. 导出变量申明 (Exported Variables) --------------------------------- */ +/** + * @defgroup ICODEC_exported_var ICODEC 导出变量申明 (Exported Variables) + * @{ + */ + +/** + * @} + */ +/* 7. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @defgroup ICODEC_private_types ICODEC 私有类型定义 (Private Types) + * @{ + */ + +/** + * @} + */ +/* 8. 私有常量定义Private Constants ------------------------------------- */ +/** + * @defgroup ICODEC_private_constants ICODEC 私有常量定义Private Constants + * @{ + */ + +/** + * @} + */ +/* 9. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @defgroup ICODEC_private_macros ICODEC 私有宏定义 (Private Macros) + * @{ + */ + +#define IS_ICODEC_INSTANCE(INSTANCE) (((INSTANCE) == ICODEC_Instance)) + +#define IS_ICODEC_I2SFMT(__I2SFMT__) (((__I2SFMT__) == HAL_ICODEC_OPERATION_MODE_I2S) || \ + ((__I2SFMT__) == HAL_ICODEC_OPERATION_MODE_MSB_JUSTIFIED)) + +#define IS_ICODEC_SAMPLE_RATE(__RATE__) (((__RATE__) == HAL_ICODEC_SAMPLE_RATE_8000) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_16000) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_24000) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_32000) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_44100) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_48000) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_88200) || \ + ((__RATE__) == HAL_ICODEC_SAMPLE_RATE_96000)) + +#define IS_ICODEC_DATA_FORMAT(__FMT__) (((__FMT__) == HAL_ICODEC_DATA_FMT_S16LE) || \ + ((__FMT__) == HAL_ICODEC_DATA_FMT_S20LE) || \ + ((__FMT__) == HAL_ICODEC_DATA_FMT_S24LE)) + +#define IS_ICODEC_CHANNEL(__CH__) (((__CH__) == HAL_ICODEC_MONO_LEFT) || \ + ((__CH__) == HAL_ICODEC_MONO_RIGHT) || \ + ((__CH__) == HAL_ICODEC_STEREO)) + +#define IS_ICODEC_DAC_DIGGAIN(__DGAIN__) (0 <= (__DGAIN__) <= 255) + +#define IS_ICODEC_ADC_DIGGAIN(__DGAIN__) (0 <= (__DGAIN__) <= 255) + +/** + * @} + */ +/* 10. 私有函数申明 (Private Funcs) ------------------------------------- */ +/** + * @defgroup ICODEC_private_funcs ICODEC 私有函数申明 (Private Funcs) + * @{ + */ + + + + +/** + * @} + */ +/* 11. 私有变量申明 Private Variables ----------------------------------- */ +/** + * @defgroup ICODEC_private_var ICODEC 私有变量申明 (Private Variables) + * @{ + */ + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X2600_HAL_ICODEC_H__ */ diff --git a/drivers/drivers-x2600/src/x2600_hal_icodec.c b/drivers/drivers-x2600/src/x2600_hal_icodec.c new file mode 100644 index 0000000000000000000000000000000000000000..5c1b04c4c9c852733aebef988bd7955928da5598 --- /dev/null +++ b/drivers/drivers-x2600/src/x2600_hal_icodec.c @@ -0,0 +1,781 @@ +/** + * @file x2600_hal_icodec.c + * @author MPU系统软件部团队 + * @brief ICODEC HAL 驱动源文件 + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + [特点] + (#) 支持16、20、24位音频样本数据. + (#) 支持I2S或MSB-Justified格式. + + [快速编程] + (#) 1. 定义全局ICODEC句柄 + (#) 2. ICODEC上电 + (#) 3. 根据需求配置ICODEC（ADC/DAC） + (#) 4. 使能ADC/DAC + (#) 5. 录音或放音操作 + + [注意事项] + (#) 1. ICODEC上电时会复位CODEC，所以在上电后需要对ICODEC进行配置（ADC/DAC） + + @endverbatim + */ + + +/* 1.头文件 (Includes)------------------------------------------------ */ +#include "x2600_hal.h" + +/** @addtogroup g_X2600_ICODEC_HAL_Driver + * @{ + */ + +/* 2.私有常量定义Private Constants -------------------------------------- */ +/** + * @addtogroup ICODEC_private_constants ICODEC私有常量定义（Private Constants） + * @{ + */ + +/** + * @} + */ +/* 3. 私有类型定义 (Private Types) -------------------------------------- */ +/** + * @addtogroup ICODEC_private_types ICODEC私有类型定义（Private Types） + * @{ + */ + +/** + * @} + */ +/* 4. 私有宏定义 (Private Macros) -------------------------------------- */ +/** + * @addtogroup ICODEC_private_macros ICODEC 私有宏定义（Private Macros） + * @{ + */ + +/** + * @} + */ +/* 5. 私有变量申明 Private Variables ------------------------------------ */ +/** + * @addtogroup ICODEC_private_var ICODEC 私有变量声明（Private Variables） + * @{ + */ + +/** + * @} + */ +/* 6. 私有函数申明 (Private Funcs) -------------------------------------- */ +/** + * @addtogroup ICODEC_private_funcs ICODEC 私有函数声明（Private Funcs） + * @{ + */ +static int ICODEC_Get_FmtWidth(HAL_ICODECDataFormatTypeDef format); +static unsigned int ICODEC_Get_SampleRate(HAL_ICODECSampleRateTypeDef SRate); +static HAL_StatusTypeDef ICODEC_DAC_Configure(ICODEC_HandleTypeDef *hicodec); +static HAL_StatusTypeDef ICODEC_ADC_Configure(ICODEC_HandleTypeDef *hicodec); + +/** + * @} + */ +/* 7. 私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup ICODEC_private_funcs_impl ICODEC 私有函数实现 (Private Funcs) + * @{ + */ + +/** + * @brief ICODEC 获取数据格式对应的字节宽度 + * + * @param format 采样格式 + * + * @return 成功返回字节宽度，失败返回 -1 + */ +static int ICODEC_Get_FmtWidth(HAL_ICODECDataFormatTypeDef format) +{ + int fmt_width = 0; + + switch (format) { + case HAL_ICODEC_DATA_FMT_S16LE: + fmt_width = 16; + break; + case HAL_ICODEC_DATA_FMT_S20LE: + fmt_width = 20; + break; + case HAL_ICODEC_DATA_FMT_S24LE: + fmt_width = 24; + break; + default: + prom_printk(" format error \n"); + fmt_width = -1; + break; + } + + return fmt_width; +} + +/** + * @brief ICODEC 计算采样率的实际值 + * + * @param SRate 采样速率 + * + * @return 成功返回采样率的实际值，失败返回0 + */ +static unsigned int ICODEC_Get_SampleRate(HAL_ICODECSampleRateTypeDef SRate) +{ + unsigned int sample_rate = 0; + + switch (SRate) { + case HAL_ICODEC_SAMPLE_RATE_8000: + sample_rate = 8000; + break; + case HAL_ICODEC_SAMPLE_RATE_16000: + sample_rate = 16000; + break; + case HAL_ICODEC_SAMPLE_RATE_24000: + sample_rate = 24000; + break; + case HAL_ICODEC_SAMPLE_RATE_32000: + sample_rate = 32000; + break; + case HAL_ICODEC_SAMPLE_RATE_44100: + sample_rate = 44100; + break; + case HAL_ICODEC_SAMPLE_RATE_48000: + sample_rate = 48000; + break; + case HAL_ICODEC_SAMPLE_RATE_88200: + sample_rate = 88200; + break; + case HAL_ICODEC_SAMPLE_RATE_96000: + sample_rate = 96000; + break; + default: + break; + } + + return sample_rate; +} + +/** + * @brief ICODEC DAC配置 + * + * @param hicodec ICODEC 句柄 + * + * @return 成功返回0，失败返回1 + */ +static HAL_StatusTypeDef ICODEC_DAC_Configure(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + assert_param(IS_ICODEC_I2SFMT(hicodec->Interface)); + assert_param(IS_ICODEC_SAMPLE_RATE(hicodec->Playback.SampleRates)); + assert_param(IS_ICODEC_DATA_FORMAT(hicodec->Playback.Format)); + assert_param(IS_ICODEC_DAC_DIGGAIN(hicodec->Playback.dgain)); + + int fmt_width = 0; + unsigned int sample_rate = 0; + + fmt_width = ICODEC_Get_FmtWidth(hicodec->Playback.Format); + sample_rate = ICODEC_Get_SampleRate(hicodec->Playback.SampleRates); + + if (-1 == fmt_width || 0 == sample_rate) { + prom_printk("DAC configuration information error.\r\n"); + return HAL_ERROR; + } + + /* dac master mode */ + __HAL_ICODEC_DAC_SEL_PIN_MASTER_MODE(hicodec); + __HAL_ICODEC_DAC_SEL_FUNC_MASTER_MODE(hicodec); + + /* configure dac i2sfmt */ + switch (hicodec->Interface) { + case HAL_ICODEC_OPERATION_MODE_I2S: + __HAL_ICODEC_DAC_SELECT_I2S_MODE(hicodec); + break; + case HAL_ICODEC_OPERATION_MODE_MSB_JUSTIFIED: + __HAL_ICODEC_DAC_SELECT_MSB_MODE(hicodec); + break; + default: + return HAL_ERROR; + } + + /* configure audio sample depth */ + __HAL_ICODEC_DAC_SET_I2SWL(hicodec, fmt_width); + + /* configure mute sample rate. */ + __HAL_ICODEC_DAC_SET_MUTESR(hicodec, sample_rate); + + /* configure dac digital gain */ + __HAL_ICODEC_DAC_SET_DIGGAIN(hicodec, hicodec->Playback.dgain); + + return HAL_OK; +} + +/** + * @brief ICODEC ADC配置 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回0，失败返回1 + */ +static HAL_StatusTypeDef ICODEC_ADC_Configure(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + assert_param(IS_ICODEC_CHANNEL(hicodec->Capture.channel)); + assert_param(IS_ICODEC_DATA_FORMAT(hicodec->Capture.Format)); + assert_param(IS_ICODEC_ADC_DIGGAIN(hicodec->Capture.dgain)); + + int fmt_width = 0; + fmt_width = ICODEC_Get_FmtWidth(hicodec->Capture.Format); + if (-1 == fmt_width) { + prom_printk("ADC configuration information error.\r\n"); + return HAL_ERROR; + } + + /* adc master mode */ + __HAL_ICODEC_ADC_SEL_PIN_MASTER_MDOE(hicodec); + __HAL_ICODEC_ADC_SEL_FUNC_MASTER_MODE(hicodec); + + /* configure adc i2sfmt */ + switch (hicodec->Interface) { + case HAL_ICODEC_OPERATION_MODE_I2S: + __HAL_ICODEC_ADC_SELECT_I2S_MODE(hicodec); + break; + case HAL_ICODEC_OPERATION_MODE_MSB_JUSTIFIED: + __HAL_ICODEC_ADC_SELECT_MSB_MODE(hicodec); + break; + default: + return HAL_ERROR; + } + + /* configure adc i2s data select */ + switch (hicodec->Capture.channel) { + case HAL_ICODEC_MONO_LEFT: + __HAL_ICODEC_ADC_SETLET_LEFT_DATA(hicodec); + break; + case HAL_ICODEC_MONO_RIGHT: + __HAL_ICODEC_ADC_SETLET_RIGHT_DATA(hicodec); + break; + case HAL_ICODEC_STEREO: + __HAL_ICODEC_ADC_SETLET_STEREO_DATA(hicodec); + break; + default: + return HAL_ERROR; + } + + /* Configure Audio Sample Depth. */ + __HAL_ICODEC_ADC_SET_I2SWL(hicodec, fmt_width); + + /* Configure adc digital gain */ + __HAL_ICODEC_ADC_SET_DIGGAIN(hicodec, hicodec->Capture.dgain); + + return HAL_OK; +} + +/** + * @} + */ +/* 8. 导出函数实现------------------------------------------------------- */ +/** + * @defgroup ICODEC_exported_funcs_impl ICODEC 导出函数实现（Exported Funcs） + * @{ + */ + +/** + * @brief ICODEC上电函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_PowerOn(ICODEC_HandleTypeDef *hicodec) +{ + if(NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Supply the power of the digital part and reset the audio codec. */ + __HAL_ICODEC_SYS_RST(hicodec); + __HAL_ICODEC_DAC_RST(hicodec); + __HAL_ICODEC_ADC_RST(hicodec); + HAL_Delay(10); + __HAL_ICODEC_ADC_WORK(hicodec); + __HAL_ICODEC_DAC_WORK(hicodec); + __HAL_ICODEC_SYS_WORK(hicodec); + + /* step2: setup the output DC voltage of DAC left channel*/ + __HAL_ICODEC_DACL_POP_CTRL(hicodec, 0x1); + + /* step3: Configure the register BIASCR2.SELVREF to 0x01. */ + __HAL_ICODEC_SET_SELVREF(hicodec, 0x1); + + /* step4: Supply the power of the analog part. */ + __HAL_ICODEC_ADC_WORK(hicodec); + __HAL_ICODEC_DAC_WORK(hicodec); + __HAL_ICODEC_SYS_WORK(hicodec); + + /* step5: setup reference voltage. */ + __HAL_ICODEC_VREF_ENABLE(hicodec); + + /* step6: Increase the register BIASCR2.SELVREF from 0x01 to 0xff step by step, or configure this register to 0xff directly. */ + __HAL_ICODEC_SET_SELVREF(hicodec, 0xff); + HAL_Delay(20); + + /* step7: Wait until the voltage of VCM keeps stable at the AVDD/2. */ + HAL_Delay(20); + + /* step8: Configure the register BIASCR2.SELVREF to the appropriate value (except 0x00) for reducing power. */ + __HAL_ICODEC_SET_SELVREF(hicodec, 0x2); + + return HAL_OK; +} + +/** + * @brief ICODEC掉电函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_PowerOff(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Keep the power on and disable the DAC and ADC path. */ + + /* step2: Configure the register BIASCR2.SELVREF to 0x01. */ + __HAL_ICODEC_SET_SELVREF(hicodec, 0x01); + + /* step3: Configure the register BIASCR1.VREFEN to 0 for disable reference voltage. */ + __HAL_ICODEC_VREF_DISABLE(hicodec); + + /* step4: Increase the register BIASCR2.SELVREF from 0x01 to 0xff step by step, or configure this register to 0xff directly. The suggestion slot time of the step is 20ms.*/ + __HAL_ICODEC_SET_SELVREF(hicodec, 0xff); + HAL_Delay(20); + + /* step5: Wait until the voltage of VCM keep stable at AGND */ + HAL_Delay(20); + + /* step6: Power off the analog power supply. */ + + /* step7: Power off the digital power supply. */ + + return HAL_OK; +} + +/** + * @brief ICODEC DAC与ADC配置函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_Configure(ICODEC_HandleTypeDef* hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + switch (hicodec->Stream) { + case HAL_ICODEC_STREAM_ONLY_PLAYBACK: + ICODEC_DAC_Configure(hicodec); + break; + case HAL_ICODEC_STREAM_ONLY_CAPTURE: + ICODEC_ADC_Configure(hicodec); + break; + case HAL_ICODEC_STREAM_PLAYBACK_CAPTURE: + ICODEC_DAC_Configure(hicodec); + ICODEC_ADC_Configure(hicodec); + break; + default: + prom_printk("ICodec stream type wrong.\r\n"); + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief ICODEC DAC使能函数 + * + * @ param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_DAC_Enable(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Power up the CODEC and input the mute signal. */ + + /* step2: enable the current source of DAC. */ + __HAL_ICODEC_DACIBIAS_ENABLE(hicodec); + + /* step3: enable the reference voltage buffer of the DAC left channel.*/ + __HAL_ICODEC_DACLBUF_ENABLE(hicodec); + + /* step4: enable POP sound in the DAC left channel.*/ + __HAL_ICODEC_DACL_POP_CTRL(hicodec, 0x2); + + /* step5: enable the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_ENABLE(hicodec); + + /* step6: end the initialization of the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_WORK(hicodec); + + /* step7: enable the reference voltage of DACL module. */ + __HAL_ICODEC_DACLVREF_ENABLE(hicodec); + + /* step8: enable the clock module of DACL module. */ + __HAL_ICODEC_DACLCLK_ENABLE(hicodec); + + /* step9: enable the DACL module. */ + __HAL_ICODEC_DACL_ENABLE(hicodec); + + /* step10: end the initialization of the DACL module. */ + __HAL_ICODEC_DACL_WORK(hicodec); + + /* step11: end the mute station of the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_MUTE_DISABLE(hicodec); + + /* step12: select the gain of DRVL module in the DAC left channel. */ + __HAL_ICODEC_SET_HPLGAIN(hicodec, 0x1a); + + /* step13: Play the music. */ + + return HAL_OK; +} + +/** + * @brief ICODEC DAC禁用函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_DAC_Disable(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Keep the DAC channel work and input the mute signal. */ + + /* step2: select the gain of the DRVL in the DAC left channel.*/ + __HAL_ICODEC_SET_HPLGAIN(hicodec, 0x0); + + /* step3: mute the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_MUTE_ENABLE(hicodec); + + /* step4: begin the initialization of the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_INITIAL(hicodec); + + /* step5: disable the DRVL module in the DAC left channel. */ + __HAL_ICODEC_HPOUTL_DISABLE(hicodec); + + /* step6: disable the DACL module. */ + __HAL_ICODEC_DACL_DISABLE(hicodec); + + /* step7: disable the clock module of DACL module. */ + __HAL_ICODEC_DACLCLK_DISABLE(hicodec); + + /* step8: disable the reference voltage of DACL module. */ + __HAL_ICODEC_DACLVREF_DISABLE(hicodec); + + /* step9: initialize the POP sound in the DAC left channel. */ + __HAL_ICODEC_DACL_POP_CTRL(hicodec, 0x1); + + /* step10: disable the reference voltage buffer of the DAC left channel. */ + __HAL_ICODEC_DACLBUF_DISABLE(hicodec); + + /* step11: disable the current source of DAC. */ + __HAL_ICODEC_DACIBIAS_DISABLE(hicodec); + + /* step12: begin the initialization of the DACL module. */ + __HAL_ICODEC_DACL_ININIAL(hicodec); + + return HAL_OK; +} + +/** + * @brief ICODEC DAC数字增益设置函数 + * + * @param hicodec ICODEC句柄 + * @param dgain 数字增益值[0 - 255] + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_DAC_SetDigGain(ICODEC_HandleTypeDef* hicodec, unsigned int dgain) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + if (dgain > 255) { + prom_printk("Digital gain value out of range.\r\n"); + return HAL_ERROR; + } + + __HAL_ICODEC_DAC_SET_DIGGAIN(hicodec, dgain); + + return HAL_OK; +} + +/** + * @brief ICODEC DAC数字增益获取函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回数字增益值 + */ +unsigned int HAL_ICODEC_DAC_GetDigGain(ICODEC_HandleTypeDef* hicodec) +{ + assert_param(NULL == hicodec); + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + unsigned int dgain = 0; + + dgain = __HAL_ICODEC_DAC_GET_DIGGAIN(hicodec); + + return dgain; +} + +/** + * @brief ICODEC ADC使能函数 + * + * @ param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_ADC_Enable(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Power up the CODEC according to the section Power Up. */ + + /* step2: enable the current source of ADC. */ + __HAL_ICODEC_ADCIBIAS_ENABLE(hicodec); + + /* step3: enable the reference voltage buffer in ADC left channel. */ + __HAL_ICODEC_ADCLBUF_ENABLE(hicodec); + + /* step4: enable the reference voltage buffer in ADC left channel. */ + __HAL_ICODEC_MICL_ENABLE(hicodec); + + /* step5: enable the ALC module in ADC left channel. */ + __HAL_ICODEC_ALCL_ENABLE(hicodec); + + /* step6: enable the clock module in ADC left channel. */ + __HAL_ICODEC_ADCLCLK_ENABLE(hicodec); + + /* step7: enable the ADC module in ADC left channel. */ + __HAL_ICODEC_ADCL_ENABLE(hicodec); + + /* step8: end the initialization of the ADCL module. */ + __HAL_ICODEC_ADCL_WORK(hicodec); + + /* step9: end the initialization of the left ALC module. */ + __HAL_ICODEC_ALCL_WORK(hicodec); + + /* step10: end the initialization of the left MIC module. */ + __HAL_ICODEC_MICL_WORK(hicodec); + HAL_Delay(10); + + /* step11: end the mute station of the ADC left channel. */ + __HAL_ICODEC_MICL_MUTE_DISABLE(hicodec); + + /* step12: select the gain of the left MIC module. */ + __HAL_ICODEC_SET_MICLGAIN(hicodec, 0x0); + + /* step13: select the gain of the left ALC module. */ + __HAL_ICODEC_SET_ALCLGAIN(hicodec, 0x6); + + /* step14: enable the zero-crossing detection function in ADC left channel. */ + __HAL_ICODEC_ADCL_ZERODET_ENABLE(hicodec); + + /* step15: Begin recording. */ + + return HAL_OK; +} + +/** + * @brief ICODEC ADC禁用函数 + * + * @ param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_ADC_Disable(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + /* step1: Keep ADC channel work and stop recording. */ + + /* step2: disable the zero-crossing detection function in ADC left channel. */ + __HAL_ICODEC_ADCL_ZERODET_DISABLE(hicodec); + + /* step3: disable the ADC module in ADC left channel. */ + __HAL_ICODEC_ADCL_DISABLE(hicodec); + + /* step4: disable the clock module in ADC left channel. */ + __HAL_ICODEC_ADCLCLK_DISABLE(hicodec); + + /* step5: disable the ALC module in ADC left channel. */ + __HAL_ICODEC_ALCL_DISABLE(hicodec); + + /* step6: disable the MIC module in ADC left channel. */ + __HAL_ICODEC_MICL_DISABLE(hicodec); + + /* step7: disable the reference voltage buffer in ADC left channel. */ + __HAL_ICODEC_ADCLBUF_DISABLE(hicodec); + + /* step8: disable the current source of ADC. */ + __HAL_ICODEC_ADCIBIAS_DISABLE(hicodec); + + /* step9: begin the initialization of the ADCL module. */ + __HAL_ICODEC_ADCL_INITIAL(hicodec); + + /* step10: begin the initialization of the left ALC module. */ + __HAL_ICODEC_ALCL_INITIAL(hicodec); + + /* step11: begin the initialization of the left MIC module. */ + __HAL_ICODEC_MICL_INITIAL(hicodec); + + return HAL_OK; +} + + +/** + * @brief ICODEC ADC数字增益设置函数 + * + * @param hicodec ICODEC句柄 + * @param dgain 数字增益值[0 - 255] + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_ADC_SetDigGain(ICODEC_HandleTypeDef* hicodec, unsigned int dgain) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + if (dgain > 255) { + prom_printk("Digital gain value out of range.\r\n"); + return HAL_ERROR; + } + + __HAL_ICODEC_ADC_SET_DIGGAIN(hicodec, dgain); + + return HAL_OK; +} + +/** + * @brief ICODEC ADC数字增益获取函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回数字增益值 + */ +unsigned int HAL_ICODEC_ADC_GetDigGain(ICODEC_HandleTypeDef* hicodec) +{ + assert_param(NULL == hicodec); + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + unsigned int dgain = 0; + + dgain = __HAL_ICODEC_ADC_GET_DIGGAIN(hicodec); + + return dgain; +} + +/** + * @brief ICODEC寄存器Dump函数 + * + * @param hicodec ICODEC句柄 + * + * @return 成功返回HAL_OK，失败返回HAL_ERROR + */ +HAL_StatusTypeDef HAL_ICODEC_DumpRegisters(ICODEC_HandleTypeDef *hicodec) +{ + if (NULL == hicodec) + return HAL_ERROR; + + assert_param(IS_ICODEC_INSTANCE(hicodec->Instance)); + + prom_printk("---------- RSTR : = %#x\r\n", READ_REG(hicodec->Instance->RSTR)); + prom_printk("---------- DACCR1 : = %#x\r\n", READ_REG(hicodec->Instance->DACCR1)); + prom_printk("---------- DACCR2 : = %#x\r\n", READ_REG(hicodec->Instance->DACCR2)); + prom_printk("---------- DACCR3 : = %#x\r\n", READ_REG(hicodec->Instance->DACCR3)); + prom_printk("---------- DACCR4 : = %#x\r\n", READ_REG(hicodec->Instance->DACCR4)); + prom_printk("---------- DACCR5 : = %#x\r\n", READ_REG(hicodec->Instance->DACCR5)); + prom_printk("---------- DACDGR : = %#x\r\n", READ_REG(hicodec->Instance->DACDGR)); + prom_printk("---------- ADCCR1 : = %#x\r\n", READ_REG(hicodec->Instance->ADCCR1)); + prom_printk("---------- ADCCR2 : = %#x\r\n", READ_REG(hicodec->Instance->ADCCR2)); + prom_printk("---------- ADCCR3 : = %#x\r\n", READ_REG(hicodec->Instance->ADCCR3)); + prom_printk("---------- ADCCR4 : = %#x\r\n", READ_REG(hicodec->Instance->ADCCR4)); + prom_printk("---------- ADCDGR : = %#x\r\n", READ_REG(hicodec->Instance->ADCDGR)); + prom_printk("---------- BIASCR1 : = %#x\r\n", READ_REG(hicodec->Instance->BIASCR1)); + prom_printk("---------- BIASCR2 : = %#x\r\n", READ_REG(hicodec->Instance->BIASCR2)); + prom_printk("---------- BIASCR3 : = %#x\r\n", READ_REG(hicodec->Instance->BIASCR3)); + prom_printk("---------- DACLCR : = %#x\r\n", READ_REG(hicodec->Instance->DACLCR)); + prom_printk("---------- HPCR : = %#x\r\n", READ_REG(hicodec->Instance->HPCR)); + prom_printk("---------- HPDSR : = %#x\r\n", READ_REG(hicodec->Instance->HPDSR)); + prom_printk("---------- HPGR : = %#x\r\n", READ_REG(hicodec->Instance->HPGR)); + prom_printk("---------- ADCLCR : = %#x\r\n", READ_REG(hicodec->Instance->ADCLCR)); + prom_printk("---------- MICCR : = %#x\r\n", READ_REG(hicodec->Instance->MICCR)); + prom_printk("---------- ALCGR : = %#x\r\n", READ_REG(hicodec->Instance->ALCGR)); + prom_printk("---------- MICGR : = %#x\r\n", READ_REG(hicodec->Instance->MICGR)); + prom_printk("---------- AGCCR1 : = %#x\r\n", READ_REG(hicodec->Instance->AGCCR1)); + prom_printk("---------- AGCCR2 : = %#x\r\n", READ_REG(hicodec->Instance->AGCCR2)); + prom_printk("---------- AGCCR3 : = %#x\r\n", READ_REG(hicodec->Instance->AGCCR3)); + prom_printk("---------- PGAGR : = %#x\r\n", READ_REG(hicodec->Instance->PGAGR)); + prom_printk("---------- AGCSRR : = %#x\r\n", READ_REG(hicodec->Instance->AGCSRR)); + prom_printk("---------- AGCMAXLR : = %#x\r\n", READ_REG(hicodec->Instance->AGCMAXLR)); + prom_printk("---------- AGCMAXHR : = %#x\r\n", READ_REG(hicodec->Instance->AGCMAXHR)); + prom_printk("---------- AGCMINLR : = %#x\r\n", READ_REG(hicodec->Instance->AGCMINLR)); + prom_printk("---------- AGCMINHR : = %#x\r\n", READ_REG(hicodec->Instance->AGCMINHR)); + prom_printk("---------- AGCGR : = %#x\r\n", READ_REG(hicodec->Instance->AGCGR)); + prom_printk("---------- ALCOGR : = %#x\r\n", READ_REG(hicodec->Instance->ALCOGR)); + + return HAL_OK; +} + + +/** + * @} + */ + +/** + * @} + */ diff --git a/projects/x2660-halley/Examples/icodec/CMakeLists.txt b/projects/x2660-halley/Examples/icodec/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..97e2c8b639ed2cbba0305334297f7006a3a6c0fb --- /dev/null +++ b/projects/x2660-halley/Examples/icodec/CMakeLists.txt @@ -0,0 +1,111 @@ +cmake_minimum_required(VERSION 3.8) +# +# Core project settings +# +Project(icodec) # Modified +enable_language(C CXX ASM) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS ON) +set(PROJ_PATH ${CMAKE_CURRENT_SOURCE_DIR}) +set(SDK_PATH ${PROJ_PATH}/../../../../) +message("Build type: " ${CMAKE_BUILD_TYPE}) + +# Set linker script +set(linker_script_SRC ${SDK_PATH}/cpu/core-riscv/ld.lds) # Modified +set(EXECUTABLE ${CMAKE_PROJECT_NAME}) +set(CPU_PARAMETERS "-march=rv32imc -mabi=ilp32 -Wno-abi") + +set(CMAKE_ASM_FLAGS "${CPU_PARAMETERS} -D_ASSEMBLER_ -D__ASSEMBLY__") + +set(CMAKE_C_FLAGS "${CPU_PARAMETERS} -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Wall -fdata-sections -ffunction-sections") + +# Compiler options + +if(CMAKE_BUILD_TYPE STREQUAL Debug) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 -g -ggdb -DDEBUG") +else() + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O2") +endif() + +set(CMAKE_CXX_FLAGS ${CMAKE_C_FLAGS}) + +set(CMAKE_LD_FLAGS "${CPU_PARAMETERS}") + + +set(sources_SRCS # Modified + ${SDK_PATH}/cpu/core-riscv/spinlock.c + ${SDK_PATH}/cpu/core-riscv/start.S + ${SDK_PATH}/cpu/core-riscv/genex.S + ${SDK_PATH}/cpu/core-riscv/traps.c + ${SDK_PATH}/cpu/soc-x2600/src/interrupt.c + ${SDK_PATH}/cpu/soc-x2600/src/serial.c + ${SDK_PATH}/cpu/soc-x2600/src/startup.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_def.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_aic.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_icodec.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_cpm.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_gpio.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_hal_tick_risc_ccu.c + ${SDK_PATH}/drivers/drivers-x2600/src/x2600_ll_risc_ccu.c + ${SDK_PATH}/lib/libc/minimal/ctype.c + ${SDK_PATH}/lib/libc/minimal/div64.c + ${SDK_PATH}/lib/libc/minimal/string.c + ${SDK_PATH}/lib/libc/minimal/vsprintf.c + main.c +) + +if(CMAKE_EXPORT_COMPILE_COMMANDS) + set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES}) + set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES}) +endif() + +# +# Include directories +# +#set(include_path_DIRS +# Modified + +include_directories( + ${PROJ_PATH}/include + ${SDK_PATH}/lib/libc/minimal/include + ${SDK_PATH}/drivers/drivers-x2600/include + ${SDK_PATH}/cpu/core-riscv/include + ${SDK_PATH}/cpu/soc-x2600/include +) + +# +# -L libdirs. +# +link_directories( +#path/to/lib +) + +# Executable files +add_executable(${EXECUTABLE} ${sources_SRCS}) + +# Linker options +target_link_libraries(${EXECUTABLE} PRIVATE + -T${linker_script_SRC} + ${CMAKE_LD_FLAGS} + -Wl,-Map=${CMAKE_PROJECT_NAME}.map,--cref + -Wl,--gc-sections + -Wl,--start-group + -Wl,--end-group + -Wl,--print-memory-usage +) + +# Execute post-build to print size +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_SIZE} $ +) + +# Convert output to hex and binary +add_custom_command(TARGET ${EXECUTABLE} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin + ) diff --git a/projects/x2660-halley/Examples/icodec/Makefile b/projects/x2660-halley/Examples/icodec/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..9ec5dfcfd857301be363bd185ada2a9995289035 --- /dev/null +++ b/projects/x2660-halley/Examples/icodec/Makefile @@ -0,0 +1,179 @@ +###################################### +# target +###################################### +TARGET = icodec + +SDK_PATH = ../../../../ + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og -fno-pic -fno-builtin -fomit-frame-pointer -Wall -nostdlib -Werror-implicit-function-declaration + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/traps.c \ +$(SDK_PATH)/cpu/core-riscv/spinlock.c \ +$(SDK_PATH)/cpu/soc-x2600/src/startup.c \ +$(SDK_PATH)/cpu/soc-x2600/src/serial.c \ +$(SDK_PATH)/cpu/soc-x2600/src/interrupt.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_def.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_aic.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_icodec.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_pdma.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_cpm.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_gpio.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_hal_tick_risc_ccu.c \ +$(SDK_PATH)/drivers/drivers-x2600/src/x2600_ll_risc_ccu.c \ +$(SDK_PATH)/lib/libc/minimal/vsprintf.c \ +$(SDK_PATH)/lib/libc/minimal/string.c \ +$(SDK_PATH)/lib/libc/minimal/ctype.c \ +$(SDK_PATH)/lib/libc/minimal/div64.c \ +main.c + +# ASM sources +ASM_SOURCES = \ +$(SDK_PATH)/cpu/core-riscv/start.S \ +$(SDK_PATH)/cpu/core-riscv/genex.S + + +####################################### +# binaries +####################################### +PREFIX = riscv32-ingenicv0-elf- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)as +LD = $(GCC_PATH)/$(PREFIX)ld +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)as +LD = $(PREFIX)ld +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -march=rv32imc -mabi=ilp32 -Wno-abi + +# fpu +FPU = + +# float-abi +FLOAT-ABI = + +# mcu +#MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) +MCU = $(CPU) $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = -D_ASSEMBLER_ -D__ASSEMBLY__ + +# C defines +C_DEFS = + + +# AS includes +AS_INCLUDES = \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ + +# C includes +C_INCLUDES = \ +-Iinclude \ +-I$(SDK_PATH)/cpu/core-riscv/include \ +-I$(SDK_PATH)/cpu/soc-x2600/include \ +-I$(SDK_PATH)/lib/libc/minimal/include \ +-I$(SDK_PATH)/drivers/drivers-x2600/include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 -O0 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = $(SDK_PATH)/cpu/core-riscv/ld.lds + +# libraries +#LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -nostdlib + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(CC) -c $(ASFLAGS) -o $@ $< + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/projects/x2660-halley/Examples/icodec/main.c b/projects/x2660-halley/Examples/icodec/main.c new file mode 100644 index 0000000000000000000000000000000000000000..9e131cde7c28001dcc84fa711fa0e9977a5bf3f8 --- /dev/null +++ b/projects/x2660-halley/Examples/icodec/main.c @@ -0,0 +1,162 @@ +/** + * @file main.c + * @author MPU系统软件部团队 + * @brief [x2600 ICODEC 测试用例] + */ +#include + +AIC_HandleTypeDef AicHandle; +ICODEC_HandleTypeDef IcodecHandle; +/* CGU_CONFIG_I2S_APLL_8192K时钟配置支持8k、16k、32k采样频率 */ +LL_CPM_CGU_I2STypeDef AicCguConfig = CGU_CONFIG_I2S_APLL_8192K; + + +unsigned int pcm_playback[] = { + #include "pcm.txt" +}; + +#define BUF_LEN (200*1024) +unsigned int CapBuff[BUF_LEN]; + + +// #define TEST_AIC_DEBUG + +#ifdef TEST_AIC_DEBUG +static void dump_aic_regs(void); +#endif + +static void Error_Handler(void); + +int main(void) +{ + int times = 10; + + HAL_Delay(500); /* 用于将MCU的打印与kernel打印分开 */ + + prom_printk("hello world %s, %d\n", __func__, __LINE__); + + /* 使能Clock Gate */ + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_AUDIO); + CPM_GATE_Enable(CPM_Instance, CPM_CLKID_I2ST); + + /* 配置时钟分频 */ + CPM_CGU_I2S0_Config(CPM_Instance, &AicCguConfig); + +#if 0 + /* 配置GPIO引脚功能（I2S0 : PC15 ~ PC19 : FUNCTION1） */ + LL_GPIO_setPinMode(PC_Instance, 15, GPIO_MODE_FUNCTION1); + LL_GPIO_setPinMode(PC_Instance, 16, GPIO_MODE_FUNCTION1); + LL_GPIO_setPinMode(PC_Instance, 17, GPIO_MODE_FUNCTION1); + LL_GPIO_setPinMode(PC_Instance, 18, GPIO_MODE_FUNCTION1); + LL_GPIO_setPinMode(PC_Instance, 19, GPIO_MODE_FUNCTION1); +#endif + + /* 实例化AIC句柄，并初始化AIC外围设备 */ + AicHandle.Instance = AIC_Instance; + AicHandle.Stream = HAL_AIC_STREAM_PLAYBACK_CAPTURE; + + /* 设置录音相关参数 */ + AicHandle.Capture.SampleRates = HAL_AIC_SAMPLE_RATE_16000; + AicHandle.Capture.Format = HAL_AIC_DATA_FMT_S16LE; + AicHandle.Capture.Channels = 2; + + /* 设置放音相关参数 */ + AicHandle.Playback.SampleRates = HAL_AIC_SAMPLE_RATE_16000; + AicHandle.Playback.Format = HAL_AIC_DATA_FMT_S16LE; + AicHandle.Playback.Channels = 2; + + AicHandle.Interface = HAL_AIC_OPERATION_MODE_I2S; + AicHandle.LrFirst = HAL_AIC_FRAME_MODE_LR; + AicHandle.BclkDirection = HAL_AIC_BCLK_CODEC_SLAVE; + AicHandle.codec = HAL_AIC_CODEC_INTERNAL; + + if (HAL_AIC_Init(&AicHandle) != HAL_OK) { + Error_Handler(); + } + +#ifdef TEST_AIC_DEBUG + dump_aic_regs(); +#endif + + IcodecHandle.Instance = ICODEC_Instance; + IcodecHandle.Interface = HAL_ICODEC_OPERATION_MODE_I2S; + IcodecHandle.Stream = HAL_ICODEC_STREAM_PLAYBACK_CAPTURE; + + IcodecHandle.Playback.SampleRates = HAL_ICODEC_SAMPLE_RATE_16000; + IcodecHandle.Playback.Format = HAL_ICODEC_DATA_FMT_S16LE; + IcodecHandle.Playback.dgain = 200; + + IcodecHandle.Capture.channel = HAL_ICODEC_STEREO; + IcodecHandle.Capture.Format = HAL_ICODEC_DATA_FMT_S16LE; + IcodecHandle.Capture.dgain = 196; + + HAL_ICODEC_PowerOn(&IcodecHandle); + + HAL_ICODEC_Configure(&IcodecHandle); + + HAL_ICODEC_DAC_Enable(&IcodecHandle); + HAL_ICODEC_ADC_Enable(&IcodecHandle); + +#if 1 + HAL_AIC_CaptureStart(&AicHandle); + HAL_AIC_PlaybackStart(&AicHandle); + while (times--) { + prom_printk(">>>>>>>>>>>>>>>>>>>>>> capture start >>>>>>>>>>>>>>>>>>>>>>>>> \n"); + HAL_AIC_CaptureReadFrame(&AicHandle, CapBuff, BUF_LEN); + prom_printk(">>>>>>>>>>>>>>>>>>>>>> capture over >>>>>>>>>>>>>>>>>>>>>>>>> \n"); + prom_printk(">>>>>>>>>>>>>>>>>>>>>> playback start >>>>>>>>>>>>>>>>>>>>>>>>> \n"); + HAL_AIC_PlaybackWriteFrame(&AicHandle, CapBuff, BUF_LEN); + prom_printk(">>>>>>>>>>>>>>>>>>>>>> playback over >>>>>>>>>>>>>>>>>>>>>>>>> \n"); + } + HAL_AIC_CaptureStop(&AicHandle); + HAL_AIC_PlaybackStop(&AicHandle); +#endif + +#if 0 + prom_printk(">>>>>>>>>>>>>>>>>>>>>> playback start >>>>>>>>>>>>>>>>>>>>>>>>> \n"); + while (times--) { + HAL_AIC_PlaybackStart(&AicHandle); + HAL_AIC_PlaybackWriteFrame(&AicHandle, pcm_playback, sizeof(pcm_playback)); + HAL_AIC_PlaybackStop(&AicHandle); + } + prom_printk(">>>>>>>>>>>>>>>>>>>>>> playback over >>>>>>>>>>>>>>>>>>>>>>>>> \n"); +#endif + +#ifdef TEST_AIC_DEBUG + dump_aic_regs(); +#endif + + HAL_ICODEC_ADC_Disable(&IcodecHandle); + HAL_ICODEC_DAC_Disable(&IcodecHandle); + HAL_ICODEC_PowerOff(&IcodecHandle); + + while (1); + return 0; +} + + + +#ifdef TEST_AIC_DEBUG +static void dump_aic_regs(void) +{ + prom_printk("AICFR: 0x%08x\n", READ_REG(AicHandle.Instance->AICFR)); + prom_printk("AICCR: 0x%08x\n", READ_REG(AicHandle.Instance->AICCR)); + prom_printk("I2SCR: 0x%08x\n", READ_REG(AicHandle.Instance->I2SCR)); + prom_printk("AICSR: 0x%08x\n", READ_REG(AicHandle.Instance->AICSR)); + prom_printk("I2SSR: 0x%08x\n", READ_REG(AicHandle.Instance->I2SSR)); + prom_printk("I2SDIV: 0x%08x\n", READ_REG(AicHandle.Instance->I2SDIV)); + prom_printk("AICDR: 0x%08x\n", READ_REG(AicHandle.Instance->AICDR)); + prom_printk("AICLR: 0x%08x\n", READ_REG(AicHandle.Instance->AICLR)); + prom_printk("AICFR2: 0x%08x\n", READ_REG(AicHandle.Instance->AICFR2)); + prom_printk("CDCCR: 0x%08x\n", READ_REG(AicHandle.Instance->CDCCR)); +} +#endif + + +static void Error_Handler(void) +{ + prom_printk(">>>>>>>> %d have error !!! \n", __LINE__); +} + + + diff --git a/projects/x2660-halley/Examples/icodec/pcm.txt b/projects/x2660-halley/Examples/icodec/pcm.txt new file mode 100644 index 0000000000000000000000000000000000000000..d3cf2ea82b42a262fcc829247be1237b114d4f56 --- /dev/null +++ b/projects/x2660-halley/Examples/icodec/pcm.txt @@ -0,0 +1 @@ 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diff --git a/projects/x2660-halley/Examples/icodec/riscv32-gcc.cmake b/projects/x2660-halley/Examples/icodec/riscv32-gcc.cmake new file mode 100644 index 0000000000000000000000000000000000000000..d09813df61ac4d343b4b4890668528bf54e9cedc --- /dev/null +++ b/projects/x2660-halley/Examples/icodec/riscv32-gcc.cmake @@ -0,0 +1,18 @@ +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv32) + +# Some default GCC settings +set(TOOLCHAIN_PREFIX "riscv32-ingenicv0-elf-") + +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++) + +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) +set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) + +set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") +set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") + +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)