From 1ed1ba3eee580fc4900155bb99e1d8623ec0fd1a Mon Sep 17 00:00:00 2001 From: "jianzhen.guo" Date: Fri, 28 Oct 2022 17:42:40 +0800 Subject: [PATCH] [Add] Add MIPI DSI driver support. --- cpu/soc-x16xx/include/cpm.h | 8 + cpu/soc-x16xx/include/dpu.h | 4 + .../include/x16xx_hal_lcd_x2000.h | 694 +++++++++++++++ .../include/x16xx_hal_mipi_dsi.h | 22 + drivers/drivers-x16xx/include/x16xx_ll_cpm.h | 6 +- .../drivers-x16xx/include/x16xx_ll_mipi_dsi.h | 363 ++++++++ .../drivers-x16xx/src/x16xx_hal_lcd_x2000.c | 808 ++++++++++++++++++ .../drivers-x16xx/src/x16xx_hal_mipi_dsi.c | 244 ++++++ drivers/drivers-x16xx/src/x16xx_ll_mipi_dsi.c | 571 +++++++++++++ 9 files changed, 2719 insertions(+), 1 deletion(-) create mode 100644 drivers/drivers-x16xx/include/x16xx_hal_lcd_x2000.h create mode 100644 drivers/drivers-x16xx/include/x16xx_hal_mipi_dsi.h create mode 100644 drivers/drivers-x16xx/include/x16xx_ll_mipi_dsi.h create mode 100644 drivers/drivers-x16xx/src/x16xx_hal_lcd_x2000.c create mode 100644 drivers/drivers-x16xx/src/x16xx_hal_mipi_dsi.c create mode 100644 drivers/drivers-x16xx/src/x16xx_ll_mipi_dsi.c diff --git a/cpu/soc-x16xx/include/cpm.h b/cpu/soc-x16xx/include/cpm.h index c833ec5a..7b1d6930 100644 --- a/cpu/soc-x16xx/include/cpm.h +++ b/cpu/soc-x16xx/include/cpm.h @@ -590,6 +590,14 @@ typedef struct { #define CLKGR1_ARB_Msk (0x1UL << CLKGR1_ARB_Pos) /*!< 0x40000000 */ #define CLKGR1_ARB CLKGR1_ARB_Msk #define CLKGR1_ARB_0 (0x1UL << CLKGR1_ARB_Pos) /*!< 0x40000000 */ + +#ifdef HAL_MIPI_DSI_ENABLE +#define CLKGR1_MIPI_DSI_Pos (29U) +#define CLKGR1_MIPI_DSI_Msk (0x1UL << CLKGR1_MIPI_DSI_Pos) /*!< 0x10000000 */ +#define CLKGR1_MIPI_DSI CLKGR1_MIPI_DSI_Msk +#define CLKGR1_MIPI_DSI_0 (0x1UL << CLKGR1_MIPI_DSI_Pos) /*!< 0x10000000 */ +#endif + #define CLKGR1_MIPI_CSI_Pos (28U) #define CLKGR1_MIPI_CSI_Msk (0x1UL << CLKGR1_MIPI_CSI_Pos) /*!< 0x10000000 */ #define CLKGR1_MIPI_CSI CLKGR1_MIPI_CSI_Msk diff --git a/cpu/soc-x16xx/include/dpu.h b/cpu/soc-x16xx/include/dpu.h index 59248335..b04f049a 100755 --- a/cpu/soc-x16xx/include/dpu.h +++ b/cpu/soc-x16xx/include/dpu.h @@ -296,6 +296,10 @@ typedef struct { #define DISP_COM_DP_IF_SEL_0 (0x1UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000001 */ #define DISP_COM_DP_IF_SEL_1 (0x2UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000002 */ +#ifdef HAL_MIPI_DSI_ENABLE +#define DISP_COM_DP_IF_SEL_2 (0x3UL << DISP_COM_DP_IF_SEL_Pos) /*!< 0x00000003 */ +#endif + /********* Register BitField Details: TFT_TIMING_HSYNC BASE+0x9000 *********/ #define TFT_TIMING_HSYNC_HPS_Pos (16U) #define TFT_TIMING_HSYNC_HPS_Msk (0xfffUL << TFT_TIMING_HSYNC_HPS_Pos) /*!< 0x0fff0000 */ diff --git a/drivers/drivers-x16xx/include/x16xx_hal_lcd_x2000.h b/drivers/drivers-x16xx/include/x16xx_hal_lcd_x2000.h new file mode 100644 index 00000000..5dedc08b --- /dev/null +++ b/drivers/drivers-x16xx/include/x16xx_hal_lcd_x2000.h @@ -0,0 +1,694 @@ +/** + * @file x16xx_hal_lcd.h + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __X16XX_HAL_LCD_H__ +#define __X16XX_HAL_LCD_H__ + + +/** + * @addtogroup group_LCD + * @{ + */ + +/** + * @addtogroup g_X16XX_LCD_HAL_Driver LCD HAL 驱动 + * @{ + */ + +/* 1.头文件 (Includes)------------------------------------------------- */ +#include "x16xx_hal.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* 2.导出的类型 (Exported Types)--------------------------------------- */ +/** + * @defgroup LCD_exported_types LCD 导出的类型 (Exported Types) + * @{ + */ +typedef enum stop_mode { + QCK_STOP, + GEN_STOP, +} stop_mode_t; + +enum lcdc_out_format { + OUT_FORMAT_RGB565, + OUT_FORMAT_RGB666, + OUT_FORMAT_RGB888, + OUT_FORMAT_RGB444, + OUT_FORMAT_RGB555, +}; + +enum lcdc_mcu_data_width { + MCU_WIDTH_8BITS, + MCU_WIDTH_9BITS, + MCU_WIDTH_16BITS, + MCU_WIDTH_18BITS, + MCU_WIDTH_24BITS, +}; + +enum lcdc_out_order { + ORDER_RGB, + ORDER_RBG, + ORDER_GRB, + ORDER_BRG, + ORDER_GBR, + ORDER_BGR, +}; + +enum lcdc_lcd_mode { + TFT_24BITS, + TFT_8BITS_SERIAL = 2, + TFT_8BITS_DUMMY_SERIAL, + TFT_MIPI, + + SLCD_6800, + SLCD_8080, + SLCD_MIPI, + SLCD_SPI_3LINE, + SLCD_SPI_4LINE, +}; + +enum lcdc_signal_polarity { + AT_FALLING_EDGE, + AT_RISING_EDGE, +}; + +enum lcdc_signal_level { + AT_LOW_LEVEL, + AT_HIGH_LEVEL, +}; + +enum lcdc_dc_pin { + CMD_LOW_DATA_HIGH, + CMD_HIGH_DATA_LOW, +}; + +enum lcdc_data_trans_mode { + LCD_PARALLEL_MODE, + LCD_SERIAL_MODE, +}; + +enum lcdc_te_type { + TE_NOT_EANBLE, + TE_GPIO_IRQ_TRIGGER, + TE_LCDC_TRIGGER, +}; + +enum smart_config_type { + SMART_CONFIG_DATA, + SMART_CONFIG_PRM, + SMART_CONFIG_CMD, + SMART_CONFIG_UDELAY, +}; + +struct smart_lcd_data_table { + enum smart_config_type type; + unsigned int value; +}; + +enum dsi_video_mode { + VIDEO_NON_BURST_WITH_SYNC_PULSES = 0, + VIDEO_NON_BURST_WITH_SYNC_EVENTS, + VIDEO_BURST_WITH_SYNC_PULSES +}; + +enum dsi_color_coding { + COLOR_CODE_16BIT_CONFIG1, + COLOR_CODE_16BIT_CONFIG2, + COLOR_CODE_16BIT_CONFIG3, + COLOR_CODE_18BIT_CONFIG1, + COLOR_CODE_18BIT_CONFIG2, + COLOR_CODE_24BIT +}; + +enum mipi_dsi_18bit_type { + PACKED18, + LOOSELY18, +}; + +struct dsi_cmd_packet { + unsigned char packet_type; + unsigned char cmd0_or_wc_lsb; + unsigned char cmd1_or_wc_msb; + unsigned char *cmd_data; +}; + +enum fb_fmt { + fb_fmt_RGB555, + fb_fmt_RGB565, + fb_fmt_RGB888, + fb_fmt_ARGB8888, + fb_fmt_NV12, + fb_fmt_NV21, + fb_fmt_yuv422, +}; + +enum frame_state { + state_clear, + state_display_start, + state_display_end, + state_stop, +}; + +struct srdmadesc { + unsigned long RdmaNextCfgAddr; + unsigned long FrameBufferAddr; + unsigned long stride; + unsigned long FrameCtrl; + unsigned long InterruptControl; +}; + +struct lcdc_srdma_cfg { + enum fb_fmt fb_fmt; + void *fb_mem; + int is_video; + int stride; +}; + +#define EVEN_RGBTORGB 0x00000000U +#define EVEN_RGBTORBG ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0) +#define EVEN_RGBTOBGR ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_1) +#define EVEN_RGBTOBRG ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0 | TFT_TRAN_CFG_COLOR_EVEN_1) +#define EVEN_RGBTOGBR ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_2) +#define ENEN_RGBTOGRB ((uint32_t)TFT_TRAN_CFG_COLOR_EVEN_0 | TFT_TRAN_CFG_COLOR_EVEN_2) + +#define ODD_RGBTORGB 0x00000000U +#define ODD_RGBTORBG ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0) +#define ODD_RGBTOBGR ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_1) +#define ODD_RGBTOBRG ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0 | TFT_TRAN_CFG_COLOR_ODD_1) +#define ODD_RGBTOGBR ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_2) +#define ODD_RGBTOGRB ((uint32_t)TFT_TRAN_CFG_COLOR_ODD_0 | TFT_TRAN_CFG_COLOR_ODD_2) + +struct lcd_data{ + const char *name; + unsigned int refresh; + unsigned int xres; + unsigned int yres; + unsigned int pixclock; + unsigned int left_margin; + unsigned int right_margin; + unsigned int upper_margin; + unsigned int lower_margin; + unsigned int hsync_len; + unsigned int vsync_len; + + enum fb_fmt fb_fmt; + enum lcdc_lcd_mode lcd_mode; + enum lcdc_out_format out_format; + struct { + int even_line_order; + int odd_line_order; + enum lcdc_signal_polarity pix_clk_polarity; + enum lcdc_signal_level de_active_level; + enum lcdc_signal_level hsync_active_level; + enum lcdc_signal_level vsync_active_level; + } tft; + struct { + unsigned int pixclock_when_init; + int te_gpio; + int cmd_of_start_frame; + int mcu_data_width; + int mcu_cmd_width; + enum lcdc_signal_polarity wr_data_sample_edge; + enum lcdc_dc_pin dc_pin; + enum lcdc_signal_polarity te_data_transfered_edge; + enum lcdc_te_type te_pin_mode; + enum lcdc_signal_level rdy_cmd_send_level; + int enable_rdy_pin:1; + } slcd; + /*mipi*/ + struct { + unsigned char num_of_lanes; + unsigned char virtual_channel; + unsigned int byte_clock; + unsigned char max_hs_to_lp_cycles; + unsigned char max_lp_to_hs_cycles; + unsigned short max_bta_cycles; + enum dsi_color_coding color_coding; + enum lcdc_signal_polarity data_en_polarity; + + enum lcdc_signal_level hsync_active_level; + enum lcdc_signal_level vsync_active_level; + + enum dsi_video_mode video_mode; + enum lcdc_signal_polarity color_mode_polarity; + enum lcdc_signal_polarity shut_down_polarity; + + enum mipi_dsi_18bit_type color_type_18bit; + + enum lcdc_te_type slcd_te_pin_mode; + enum lcdc_signal_polarity slcd_te_data_transfered_edge; + } mipi; + + + int height; // 屏的物理高度,单位毫米 + int width; // 屏的物理宽度,单位毫米 + struct smart_lcd_data_table *slcd_data_table; + unsigned int slcd_data_table_length; + void (*power_on)(void); + void (*power_off)(void); + void (*lcd_init)(void); +}; + +typedef struct __LCD_HandleTypeDef { + DPU_TypeDef *Instance; + struct lcd_data *pdata; + struct srdmadesc *desc; + HAL_LockTypeDef *lock; +} LCD_HandleTypeDef; + +/** + * @} + */ +/* 3.导出常量定义 (Exported Constants) -------------------------------- */ +/** + * @defgroup LCD_exported_constants LCD 导出的常量 (Exported Constants) + * @{ + */ + +#define TFT_d0 0 +#define TFT_d1 1 +#define TFT_d2 2 +#define TFT_d3 3 +#define TFT_d4 4 +#define TFT_d5 5 +#define TFT_d6 6 +#define TFT_d7 7 +#define TFT_d8 8 +#define TFT_d9 9 +#define TFT_d10 10 +#define TFT_d11 11 +#define TFT_d12 12 +#define TFT_d13 13 +#define TFT_d14 14 +#define TFT_d15 15 +#define TFT_d16 16 +#define TFT_d17 17 +#define TFT_d18 18 +#define TFT_d19 19 +#define TFT_d20 20 +#define TFT_d21 21 +#define TFT_d22 22 +#define TFT_d23 23 + +#define TFT_pclk 24 +#define TFT_vsync 25 +#define TFT_hsync 26 +#define TFT_de 27 + +#define SLCD_CE 23 +#define SLCD_DC 25 +#define SLCD_WR 26 +#define SLCD_TE 27 + + +#define BURST_LEN_RDMA_4 0x00000000U /*读取DMA的最大长度4*/ +#define BURST_LEN_RDMA_8 0x00000001U/*读取DMA的最大长度8*/ +#define BURST_LEN_RDMA_16 0x00000002U/*读取DMA的最大长度16*/ +#define BURST_LEN_RDMA_32 0x00000003U/*读取DMA的最大长度32*/ + +#define BURST_LEN_BDMA_32 0x00000003U/*DMA的最大长度32*/ +#define BURST_LEN_WDMA_32 0x00000003U/*DMA的最大长度32*/ + +#define CH_SEL_CMP 0x00000000U +#define CH_SEL_SR 0x00000001U + +#define QoS_value_0 0x00000000U /*重置值为0*/ +#define QoS_value_1 0x00000001U /*重置值为1*/ +#define QoS_value_2 0x00000002U /*重置值为2*/ +#define QoS_value_3 0x00000003U /*重置值为3*/ + + +#define DISPLAY_SELECT_NO 0x00000000U +#define DISPLAY_SELECT_TFT 0x00000001U +#define DISPLAY_SELECT_SLCD 0x00000002U +#define DISPLAY_SELECT_SLCD_MIPI 0x00000003U + + + +#define FLAG_DATA 0x00000000U +#define FLAG_PARAMETER 0x00000001U +#define FLAG_CMD_1 0x00000002U +#define FLAG_CMD_2 0x00000003U + +#define VIR_TO_PHY(add) (((uint32_t)add) & (~0x80000000)) +/** + * @} + */ +/* 4.导出宏定义 (Exported Macros) ------------------------------------- */ +/** + * @defgroup LCD_exported_macros LCD 导出宏 (Exported Macros) + * @{ + */ + +/** + * @defgroup LCD_exported_macros_group0 RDMA描述符地址 + * @{ + */ +#define __HAL_SRD_CHAIN_ADDR(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DC_SRD_CHAIN_ADDR, __VALUE__) + +/** + * @defgroup LCD_exported_macros_group1 RDMA描述符控制 + * @{ + */ +#define __HAL_SRD_CHAIN_START(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_SRD_CHAIN_CTRL, DC_SRD_CHAIN_CTRL_SRD_CHAIN_START_0) +/** + * @defgroup LCD_exported_macros_group2 控件配置 + * @{ + */ +/*正常停止LCD显示*/ +#define __GEN_STP_SRD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_GEN_STP_SRD_0) +#define __GEN_STP_CMP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL, 1 << 3) +/*重置DMA计数器*/ +#define __DES_CNT_RST(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_DES_CNT_RST_0) +/*快速停止LCD显示*/ +#define __QCK_STP_SRD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL,DC_CTRL_QCK_STP_SRD_0) +#define __QCK_STP_CMP(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CTRL, 1 << 0) +/** + * @defgroup LCD_exported_macros_group3 状态判断 + * @{ + */ +#define __HAL_DISP_END(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_DISP_END_0) +#define __HAL_TFT_UNDR(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_TFT_UNDR_0) +#define __HAL_STOP_SRD_ACK(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_STOP_SRD_ACK_0) +#define __HAL_SRD_WORKING(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_WORKING_0) +#define __HAL_SRD_START(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_START_0) +#define __HAL_SRD_END(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_SRD_END_0) +#define __HAL_WORKING(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_ST_WORKING_0) +/** + * @defgroup LCD_exported_macros_group4 清除状态 + * @{ + */ +#define __GEN_CLR_DISP_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_DISP_END_0) +#define __GEN_CLR_TFT_UNDR(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_TFT_UNDR_0) +#define __GEN_CLR_STOP_SRD_ACK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_STP_SRD_ACK_0) +#define __GEN_CLR_SRD_START(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_SRD_START_0) +#define __GEN_CLR_SRD_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_CLR_ST, DC_CLR_ST_CLR_SRD_END_0) +/** + * @defgroup LCD_exported_macros_group5 中断 + * @{ + */ +#define __HAL_EOD_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_EOD_MSK_0) +#define __HAL_UOT_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_UOT_MSK_0) +#define __HAL_SSA_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_SSA_MSK_0) +#define __HAL_SOS_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_SOS_MSK_0) +#define __HAL_EOS_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, DC_INTC_EOS_MSK_0) +#define __HAL_EOW_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, 1 << 15) +#define __HAL_SCA_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, 1 << 6) +#define __HAL_SOC_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, 1 << 14) +#define __HAL_OOW_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, 1 << 16) +#define __HAL_EOC_MSK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_INTC, 1 << 9) + +/** + * @defgroup LCD_exported_macros_group6 中断标志 + * @{ + */ +#define __HAL_INT_EOD(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_INT_FLAG_INT_EOD_0) +#define __HAL_INT_UOT(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_INT_FLAG_INT_UOT_0) +#define __HAL_INT_SSA(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_INT_FLAG_INT_SSA_0) +#define __HAL_INT_SOS(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_INT_FLAG_INT_SOS_0) +#define __HAL_INT_EOS(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, DC_INT_FLAG_INT_EOS_0) +#define __HAL_INT_EOW(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, 1 << 15) +#define __HAL_INT_SCA(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, 1 << 6) +#define __HAL_INT_SOC(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, 1 << 14) +#define __HAL_INT_OOW(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, 1 << 16) +#define __HAL_INT_EOC(__HANDLE__) READ_BIT((__HANDLE__)->Instance->DC_ST, 1 << 9) +/** + * @defgroup LCD_exported_macros_group7 读取DMA的最大长度 + * @{ + */ +#define __HAL_BURST_LEN_WDMA(__HANDLE__, __VALUE__) SET_BIT((__HANDLE__)->Instance->DC_COM_CONFIG, (__VALUE__) << 6) +#define __HAL_BURST_LEN_RDMA(__HANDLE__, __VALUE__) SET_BIT((__HANDLE__)->Instance->DC_COM_CONFIG, (__VALUE__) << 4) +#define __HAL_BURST_LEN_BDMA(__HANDLE__, __VALUE__) SET_BIT((__HANDLE__)->Instance->DC_COM_CONFIG, (__VALUE__) << 2) +#define __HAL_CH_SEL(__HANDLE__, __VALUE__) SET_BIT((__HANDLE__)->Instance->DC_COM_CONFIG, (__VALUE__) << 1) +/** + * @defgroup LCD_exported_macros_group8 优先级配置 + * @{ + */ +#define __HAL_ARQOS_VAL(__HANDLE__, __VALUE__) WRITE_REG((__HANDLE__)->Instance->DC_PCFG_RD_CTRL, (__VALUE__) << DC_PCFG_RD_CTRL_ARQOS_VAL_Pos) +#define __HAL_ARQOS_CTRL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DC_PCFG_RD_CTRL, DC_PCFG_RD_CTRL_ARQOS_CTRL_0) +/** + * @defgroup LCD_exported_macros_group9 显示页面配置 + * @{ + */ +#define __HAL_DP_DITHER_DW(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_DW_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__) << DISP_COM_DP_DITHER_DW_Pos) + +#define __HAL_DITHER_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_DITHER_CLKGATE_EN_0) + +#define __HAL_SLCD_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_SLCD_CLKGATE_EN_0) + +#define __HAL_TFT_CLKGATE_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->DISP_COM, DISP_COM_TFT_CLKGATE_EN_0) + +#define __HAL_DP_DITHER_EN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_EN_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__) << DISP_COM_DP_DITHER_EN_Pos) + + +#define __HAL_DP_IF_SEL(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->DISP_COM, ((~DISP_COM_DP_DITHER_DW_Msk) & (READ_REG((__HANDLE__)->Instance->DISP_COM))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group10 定时HSYNC + * @{ + */ +#define __HAL_HPS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC, ((~TFT_TIMING_HSYNC_HPS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC))) | (__VALUE__) << TFT_TIMING_HSYNC_HPS_Pos) + +#define __HAL_HPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC, ((~TFT_TIMING_HSYNC_HPE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMING_HSYNC))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group11 定时VSYNC + * @{ + */ +#define __HAL_VPS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC, ((~TFT_TIMING_VSYNC_VPS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC))) | (__VALUE__) << TFT_TIMING_VSYNC_VPS_Pos) + +#define __HAL_VPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC, ((~TFT_TIMING_VSYNC_VPE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VSYNC))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group12 定时HDE + * @{ + */ +#define __HAL_HDS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE, ((~TFT_TIMING_HDE_HDS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE))) | (__VALUE__) << TFT_TIMING_HDE_HDS_Pos) + +#define __HAL_HDE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE, ((~TFT_TIMING_HDE_HDE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_HDE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group12 定时VDE + * @{ + */ +#define __HAL_VDS(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE, ((~TFT_TIMING_VDE_VDS_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE))) | (__VALUE__) << TFT_TIMING_VDE_VDS_Pos) + +#define __HAL_VDE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE, ((~TFT_TIMING_VDE_VDE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TIMIING_VDE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group13 传输配置 + * @{ + */ +#define __HAL_COLOR_EVEN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_COLOR_EVEN_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__) << TFT_TRAN_CFG_COLOR_EVEN_Pos) + +#define __HAL_COLOR_ODD(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_COLOR_ODD_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__) << TFT_TRAN_CFG_COLOR_ODD_Pos) + +#define __HAL_SET_CLK_INV(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_PIX_CLK_INV_0) +#define __HAL_CLEAR_CLK_INV(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_PIX_CLK_INV_0) + +#define __HAL_SET_DE_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_DE_DL_0) +#define __HAL_CLEAR_DE_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_DE_DL_0) + +#define __HAL_SET_HSYNC_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) +#define __HAL_CLEAR_HSYNC_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) + +#define __HAL_SET_VSYNC_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_VSYNC_DL_0) +#define __HAL_CLEAR_VSYNC_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_VSYNC_DL_0) + +/* jzguo add */ +#define __HAL_SET_SYNC_DL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) +#define __HAL_CLEAR_SYNC_DL(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TFT_TRAN_CFG, TFT_TRAN_CFG_HSYNC_DL_0) +/* jzguo end */ + +#define __HAL_TFAN(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->TFT_TRAN_CFG, ((~TFT_TRAN_CFG_MODE_Msk) & (READ_REG((__HANDLE__)->Instance->TFT_TRAN_CFG))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group14 SLCD配置 + * @{ + */ +#define __HAL_RDY_PIXCLK_1(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_ANTI_JIT_0) +#define __RDY_PIXCLK_3(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_ANTI_JIT_0) + +#define __HAL_FMT_DIS(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_FMT_EN_0) +#define __HAL_FMT_EN(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_FMT_EN_0) + +#define __HAL_DBI_TYPE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_DBI_TYPE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_DBI_TYPE_Pos) + +#define __HAL_PIX_FMT(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_PIX_FMT_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_PIX_FMT_Pos) + +#define __HAL_TE_ANTI_JIT_1(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_ANTI_JIT_0) +#define __HAL_TE_ANTI_JIT_3(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_ANTI_JIT_0) + +#define __HAL_TE_MD_FRONT(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_MD_0) +#define __HAL_TE_MD_BACK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_MD_0) + +#define __HAL_TE_SWITCH_NOWAIT(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_SWITCH_0) +#define __HAL_TE_SWITCH_WAIT(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_SWITCH_0) + +#define __HAL_RDY_SWITCH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_RDY_SWITCH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__)<Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_EN_0) +#define __HAL_CS_EN_SLCD(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_EN_0) + +#define __HAL_CS_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_DP_0) +#define __HAL_CS_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_CS_DP_0) + +#define __HAL_RDY_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_DP_0) +#define __HAL_RDY_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_RDY_DP_0) + +#define __HAL_DC_MD_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_DC_MD_0) +#define __HAL_DC_MD_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_DC_MD_0) + +#define __HAL_WR_MD_HIGH(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_WR_MD_0) +#define __HAL_WR_MD_LOW(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_WR_MD_0) + +#define __HAL_TE_DP_LOW(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_DP_0) +#define __HAL_TE_DP_HIGH(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_PANEL_CFG, SLCD_PANEL_CFG_TE_DP_0) + +#define __HAL_DWIDTH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_DWIDTH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__) << SLCD_PANEL_CFG_DWIDTH_Pos) + +#define __HAL_CWIDTH(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG, ((~SLCD_PANEL_CFG_CWIDTH_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_PANEL_CFG))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group15 SLCD长度和宽度 + * @{ + */ + +#define __HAL_V_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE, ((~SLCD_FRM_SIZE_V_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE))) | (__VALUE__) << SLCD_FRM_SIZE_V_SIZE_Pos) + +#define __HAL_H_SIZE(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE, ((~SLCD_FRM_SIZE_H_SIZE_Msk) & (READ_REG((__HANDLE__)->Instance->SLCD_FRM_SIZE))) | (__VALUE__)) +/** + * @defgroup LCD_exported_macros_group16 SLCD数据传输 + * @{ + */ +#define __HAL_SEND_CMD(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) & (~SLCD_REG_IF_Msk) | (FLAG_CMD_1 << SLCD_REG_IF_FLAG_Pos | __VALUE__)) + +#define __HAL_SEND_DATA(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) & (~SLCD_REG_IF_Msk) | (FLAG_DATA << SLCD_REG_IF_FLAG_Pos | __VALUE__)) + +#define __HAL_SEND_PRM(__HANDLE__,__VALUE__) WRITE_REG((__HANDLE__)->Instance->SLCD_REG_IF, READ_REG((__HANDLE__)->Instance->SLCD_REG_IF) & (~SLCD_REG_IF_Msk) | (FLAG_PARAMETER << SLCD_REG_IF_FLAG_Pos | __VALUE__)) + +#define __HAL_IF_CMD_END(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_REG_IF, SLCD_REG_IF_CMD_END_0) + +/** + * @defgroup LCD_exported_macros_group17 SLCD状态 + * @{ + */ +#define __HAL_ST_BUSY(__HANDLE__) READ_BIT((__HANDLE__)->Instance->SLCD_ST, SLCD_ST_BUSY_0) +/** + * @defgroup LCD_exported_macros_group17 SLCD长度和宽度 + * @{ + */ +#define __HAL_SLCD_REG_CTRL(__HANDLE__) SET_BIT((__HANDLE__)->Instance->SLCD_REG_CTRL, SLCD_REG_CTRL_RESET_3LINE_0) + +/** + * @} + */ +/* 5.导出函数申明 (Exported Funcs) ------------------------------------ */ +/** + * @defgroup LCD_exported_funcs LCD 导出函数申明 (Exported Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6.导出变量申明 (Exported Variables) -------------------------------- */ +/** + * @defgroup LCD_exported_var LCD 导出变量申明 (Exported Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7.私有类型定义 (Private Types) ------------------------------------- */ +/** + * @defgroup LCD_private_types LCD 私有类型定义 (Private Types) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 8.私有常量定义 (Private Constants) -------------------------------- */ +/** + * @defgroup LCD_private_constants LCD 私有常量定义 (Private Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 9.私有宏定义 (Private Macros) ------------------------------------- */ +/** + * @defgroup LCD_private_macros LCD 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 10.私有函数申明 (Private Funcs) ------------------------------------ */ +/** + * @defgroup LCD_private_funcs LCD 私有函数申明 (Private Funcs) + * @{ + */ +void HAL_LCDC_INIT(LCD_HandleTypeDef *hlcd); +void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd); +void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer); +void process_slcd_data_table(LCD_HandleTypeDef * hlcd, struct smart_lcd_data_table *table, unsigned int length); +void lcdc_irq_handler(int irq, void *data); +void HAL_SRDMA_START(LCD_HandleTypeDef *hlcd); +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 11.私有变量申明 Private Variables ---------------------------------- */ +/** + * @defgroup LCD_private_var LCD 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __X16XX_HAL_LCD_H__ */ diff --git a/drivers/drivers-x16xx/include/x16xx_hal_mipi_dsi.h b/drivers/drivers-x16xx/include/x16xx_hal_mipi_dsi.h new file mode 100644 index 00000000..d9e16d76 --- /dev/null +++ b/drivers/drivers-x16xx/include/x16xx_hal_mipi_dsi.h @@ -0,0 +1,22 @@ +#ifndef __X16XX_HAL_MIPI_DSI_H__ +#define __X16XX_HAL_MIPI_DSI_H__ + +#include "x16xx_hal.h" +#include "x16xx_hal_def.h" + +int dsi_write_cmd(struct dsi_cmd_packet *cmd_data); + +int dsi_read_cmd(struct dsi_cmd_packet *cmd_data, int bytes, unsigned char *rd_buf); + +int jz_mipi_dsi_data_init(struct lcd_data *lcd_data); + +void jz_dsi_command_cfg(void); + +void jz_dsi_video_cfg(void); + +void jz_enable_mipi_dsi(void); + +void jz_disable_mipi_dsi(void); + +#endif + diff --git a/drivers/drivers-x16xx/include/x16xx_ll_cpm.h b/drivers/drivers-x16xx/include/x16xx_ll_cpm.h index 0bfa1efc..2b9facba 100644 --- a/drivers/drivers-x16xx/include/x16xx_ll_cpm.h +++ b/drivers/drivers-x16xx/include/x16xx_ll_cpm.h @@ -262,6 +262,10 @@ typedef struct { #define CPM_CLKID_GMAC0 (32UL + 23UL) #define CPM_CLKID_INTC (32UL + 26UL) #define CPM_CLKID_MIPI_CSI (32UL + 28UL) + +/* 此位 x1600 无效*/ +#define CPM_CLKID_MIPI_DSI (32UL + 29UL) + #define CPM_CLKID_ARB (32UL + 30UL) @@ -316,7 +320,7 @@ FunctionalState CPM_GATE_IsEnable(CPM_TypeDef *CPMx, uint32_t Clkid); (clkid == CPM_CLKID_AHB0 ) || (clkid == CPM_CLKID_DDR ) || (clkid == CPM_CLKID_CAN0 ) || (clkid == CPM_CLKID_CAN1 ) || \ (clkid == CPM_CLKID_CDBUS ) || (clkid == CPM_CLKID_PWM ) || (clkid == CPM_CLKID_HASH ) || (clkid == CPM_CLKID_I2S_R ) || \ (clkid == CPM_CLKID_I2S_T ) || (clkid == CPM_CLKID_UART3 ) || (clkid == CPM_CLKID_GMAC0 ) || (clkid == CPM_CLKID_INTC ) || \ - (clkid == CPM_CLKID_MIPI_CSI ) || (clkid == CPM_CLKID_ARB)) + (clkid == CPM_CLKID_MIPI_CSI ) || (clkid == CPM_CLKID_MIPI_DSI) || (clkid == CPM_CLKID_ARB)) /** diff --git a/drivers/drivers-x16xx/include/x16xx_ll_mipi_dsi.h b/drivers/drivers-x16xx/include/x16xx_ll_mipi_dsi.h new file mode 100644 index 00000000..22216996 --- /dev/null +++ b/drivers/drivers-x16xx/include/x16xx_ll_mipi_dsi.h @@ -0,0 +1,363 @@ + +#ifndef __X16XX_LL_MIPI_DSI_H__ +#define __X16XX_LL_MIPI_DSI_H__ + +#include "x16xx_hal.h" +#include + +/* + * 寄存器偏移量 + */ +#define R_DSI_HOST_VERSION 0x000 +#define R_DSI_HOST_PWR_UP 0x004 +#define R_DSI_HOST_CLKMGR_CFG 0x008 +#define R_DSI_HOST_DPI_VCID 0x00c +#define R_DSI_HOST_DPI_COLOR_CODING 0x010 +#define R_DSI_HOST_DPI_CFG_POL 0x014 +#define R_DSI_HOST_DPI_LP_CMD_TIM 0x018 +#define R_DSI_HOST_DBI_VCID 0x01c +#define R_DSI_HOST_DBI_CFG 0x020 +#define R_DSI_HOST_DBI_PARTITIONING_EN 0x024 +#define R_DSI_HOST_DBI_CMDSIZE 0x028 +#define R_DSI_HOST_PCKHDL_CFG 0x02c +#define R_DSI_HOST_GEN_VCID 0x030 +#define R_DSI_HOST_MODE_CFG 0x034 +#define R_DSI_HOST_VID_MODE_CFG 0x038 +#define R_DSI_HOST_VID_PKT_SIZE 0x03c +#define R_DSI_HOST_VID_NUM_CHUNKS 0x040 +#define R_DSI_HOST_VID_NULL_SIZE 0x044 +#define R_DSI_HOST_VID_HSA_TIME 0x048 +#define R_DSI_HOST_VID_HBP_TIME 0x04c +#define R_DSI_HOST_VID_HLINE_TIME 0x050 +#define R_DSI_HOST_VID_VSA_LINES 0x054 +#define R_DSI_HOST_VID_VBP_LINES 0x058 +#define R_DSI_HOST_VID_VFP_LINES 0x05c +#define R_DSI_HOST_VID_VACTIVE_LINES 0x060 +#define R_DSI_HOST_EDPI_CMD_SIZE 0x064 +#define R_DSI_HOST_CMD_MODE_CFG 0x068 +#define R_DSI_HOST_GEN_HDR 0x06c +#define R_DSI_HOST_GEN_PLD_DATA 0x070 +#define R_DSI_HOST_CMD_PKT_STATUS 0x074 +#define R_DSI_HOST_TO_CNT_CFG 0x078 +#define R_DSI_HOST_HS_RD_TO_CNT 0x07c +#define R_DSI_HOST_LP_RD_TO_CNT 0x080 +#define R_DSI_HOST_HS_WR_TO_CNT 0x084 +#define R_DSI_HOST_LP_WR_TO_CNT 0x088 +#define R_DSI_HOST_BTA_TO_CNT 0x08c +#define R_DSI_HOST_SDF_3D 0x090 +#define R_DSI_HOST_LPCLK_CTRL 0x094 +#define R_DSI_HOST_PHY_TMR_LPCLK_CFG 0x098 +#define R_DSI_HOST_PHY_TMR_CFG 0x09c +#define R_DSI_HOST_PHY_RSTZ 0x0a0 +#define R_DSI_HOST_PHY_IF_CFG 0x0a4 +#define R_DSI_HOST_PHY_ULPS_CTRL 0x0a8 +#define R_DSI_HOST_PHY_TX_TRIGGERS 0x0ac +#define R_DSI_HOST_PHY_STATUS 0x0b0 +#define R_DSI_HOST_PHY_TST_CTRL0 0x0b4 +#define R_DSI_HOST_PHY_TST_CTRL1 0x0b8 +#define R_DSI_HOST_INT_ST0 0x0bC +#define R_DSI_HOST_INT_ST1 0x0C0 +#define R_DSI_HOST_INT_MSK0 0x0C4 +#define R_DSI_HOST_INT_MSK1 0x0C8 +#define R_DSI_HOST_INT_FORCE0 0x0D8 +#define R_DSI_HOST_INT_FORCE1 0x0DC +#define R_DSI_HOST_VID_SHADOW_CTRL 0x100 +#define R_DSI_HOST_DPI_VCID_ACT 0x10C +#define R_DSI_HOST_DPI_COLOR_CODING_ACT 0x110 +#define R_DSI_HOST_DPI_LP_CMD_TIM_ACT 0x118 +#define R_DSI_HOST_VID_MODE_CFG_ACT 0x138 +#define R_DSI_HOST_VID_PKT_SIZE_ACT 0x13C +#define R_DSI_HOST_VID_NUM_CHUNKS_ACT 0x140 +#define R_DSI_HOST_VID_NULL_SIZE_ACT 0x144 +#define R_DSI_HOST_VID_HSA_TIME_ACT 0x148 +#define R_DSI_HOST_VID_HBP_TIME_ACT 0x14C +#define R_DSI_HOST_VID_HLINE_TIME_ACT 0x150 +#define R_DSI_HOST_VID_VSA_LINES_ACT 0x154 +#define R_DSI_HOST_VID_VBP_LINES_ACT 0x158 +#define R_DSI_HOST_VID_VFP_LINES_ACT 0x15C +#define R_DSI_HOST_VID_VACTIVE_LINES_ACT 0x160 +#define R_DSI_HOST_SDF_3D_ACT 0x190 + +/* + * 寄存器位字段 + */ +#define VERSION 0, 31 + +#define SHUTDOWNZ 0, 0 + +#define TX_ESC_CLK_DIV 0, 7 +#define TO_CLK_DIV 8, 15 + +#define DPI_VCID 0, 1 + +#define DIP_COLOR_CODING 0, 3 +#define LOOSELY18_EN 8, 8 + +#define DATAEN_ACTIVE_LOW 0, 0 +#define VSYNC_ACTIVE_LOW 1, 1 +#define HSYNC_ACTIVE_LOW 2, 2 +#define SHUTD_ACTIVE_LOW 3, 3 +#define COLORM_ACTIVE_LOW 4, 4 + +#define INVACT_LPCMD_TIME 0, 7 +#define OUTVACT_LPCMD_TIME 16, 23 + +#define ETOP_TX_EN 0, 0 +#define ETOP_RX_EN 1, 1 +#define BAT_EN 2, 2 +#define ECC_RX_EN 3, 3 +#define CRC_RX_EN 4, 4 + +#define GEN_VICD_RX 0, 1 + +#define CMD_VIDEO_MODE 0, 0 + +#define VID_MODE_TYPE 0, 1 +#define LP_VSA_EN 8, 8 +#define LP_VBP_EN 9, 9 +#define LP_VFP_EN 10, 10 +#define LP_VACT_EN 11, 11 +#define LP_HBP_EN 12, 12 +#define LP_HFP_EN 13, 13 +#define FRAME_BTA_ACK_EN 14, 14 +#define LP_CMD_EN 15, 15 +#define VPG_EN 16, 16 +#define VPG_MODE 20, 20 +#define VPG_ORIENTATION 24, 24 + +#define VID_PKT_SIZE 0, 13 + +#define VID_NUM_CHUNKS 0, 12 + +#define VID_NULL_SIZE 0, 12 + +#define VID_HSA_TIME 0, 11 + +#define VID_HBP_TIME 0, 11 + +#define VID_HLINE_TIME 0, 14 + +#define VSA_LINES 0, 9 + +#define VBP_LINES 0, 9 + +#define VFP_LINES 0, 9 + +#define V_ACTIVE_LINES 0, 13 + +#define EDPI_ALLOWED_CMD_SIZE 0, 15 + +#define TEAR_FX_EN 0, 0 +#define ACK_RQST_EN 1, 1 +#define GEN_SW_0P_TX 8, 8 +#define GEN_SW_1P_TX 9, 9 +#define GEN_SW_2P_TX 10, 10 +#define GEN_SR_0P_TX 11, 11 +#define GEN_SR_1P_TX 12, 12 +#define GEN_SR_2P_TX 13, 13 +#define GEN_LW_TX 14, 14 +#define DCS_SW_0P_TX 16, 16 +#define DCS_SW_1P_TX 17, 17 +#define DCS_SR_0P_TX 18, 18 +#define DCS_LW_TX 19, 19 +#define MAX_RD_PKT_SIZE 24, 24 + +#define GEN_DT 0, 5 +#define GEN_VC 6, 7 +#define GEN_WC_LSBYTE 8, 15 +#define GEN_WC_MSBYTE 16, 23 + +#define GEN_PLD_B1 0, 7 +#define GEN_PLD_B2 8, 15 +#define GEN_PLD_B3 16, 23 +#define GEN_PLD_B4 24, 31 + +#define GEN_CMD_EMPTY 0, 0 +#define GEN_CMD_FULL 1, 1 +#define GEN_CMD_PLD_WEMPTY 2, 2 +#define GEN_PLD_W_FUL 3, 3 +#define GEN_PLD_R_EMPTY 4, 4 +#define GEN_PLD_R_FULL 5, 5 +#define GEN_RD_CMD_BUSY 6, 6 + +#define LPRX_TO_CNT 0, 15 +#define HSTX_TO_CNT 16, 31 + +#define HS_RD_TO_CNT 0, 15 + +#define LP_RD_TO_CNT 0, 0 + +#define HS_WR_TO_CNT 0, 15 +#define PRESP_TO_MODE 24, 24 + +#define LP_WR_TO_CNT 0, 15 + +#define BAT_TO_CNT 0, 15 + +#define MODE_3D 0, 1 +#define FORMAT_3D 2, 3 +#define SECOND_VSYNC 4, 4 +#define RIGHT_FIRST 5, 5 +#define SEND_3D_CFG 16, 16 + +#define PHY_TXREQUESTCLKHS 0, 0 +#define AUTO_CLKLANE_CTRL 1, 1 + +#define PHY_CLKLP2HS_TIME 0, 9 +#define PHY_CLKHS2PLP_TIME 16, 25 + +#define MAX_RD_TIME 0, 14 +#define PHY_LP2HS_TIME 16, 23 +#define PHY_HS2LP_TIME 24, 31 + +#define PHY_SHUTDOWMZ 0, 0 +#define PHY_RSTZ 1, 1 +#define PHY_ENABLECLK 2, 2 +#define PHY_FORCEPLL 3, 3 + +#define N_LANES 0, 1 +#define PHY_STOP_WAIT_TIME 8, 15 + +#define PHY_TXREQULPSCLK 0, 0 +#define PHY_TXEXITULPSCLK 1, 1 +#define PHY_TXREQULPSLAN 2, 2 +#define PHY_TXEXITULPSLAN 3, 3 + +#define PHY_TX_TRIGGERS 0, 3 + +#define PHY_LOCK 0, 0 +#define PHY_DIRECTION 1, 1 +#define PHY_STOPSTATECLKLANE 2, 2 +#define PHY_ULPSACTIVENOTCLK 3, 3 +#define PHY_STOPSTATE0LANE 4, 4 +#define PHY_ULPSACTIVENOT0LANE 5, 5 +#define PHY_RXULPSESC0LANE 6, 6 +#define PHY_STOPSTATE1LANE 7, 7 +#define PHY_ULPSACTIVENOT1LANE 8, 8 + +#define PHY_TESTCLR 0, 0 +#define PHY_TESTCLK 1, 1 + +#define PHY_TESTDIN 0, 7 +#define PHT_TESTDOUT 8, 15 +#define PHY_TESTEN 16, 16 + +#define ACK_WITH_ERR_0 0, 0 +#define ACK_WITH_ERR_1 1, 1 +#define ACK_WITH_ERR_2 2, 2 +#define ACK_WITH_ERR_3 3, 3 +#define ACK_WITH_ERR_4 4, 4 +#define ACK_WITH_ERR_5 5, 5 +#define ACK_WITH_ERR_6 6, 6 +#define ACK_WITH_ERR_7 7, 7 +#define ACK_WITH_ERR_8 8, 8 +#define ACK_WITH_ERR_9 9, 9 +#define ACK_WITH_ERR_10 10, 10 +#define ACK_WITH_ERR_11 11, 11 +#define ACK_WITH_ERR_12 12, 12 +#define ACK_WITH_ERR_13 13, 13 +#define ACK_WITH_ERR_14 14, 14 +#define ACK_WITH_ERR_15 15, 15 +#define DPHY_ERRORS_0 16, 16 +#define DPHY_ERRORS_1 17, 17 +#define DPHY_ERRORS_2 18, 18 +#define DPHY_ERRORS_3 19, 19 +#define DPHY_ERRORS_4 20, 20 + +#define TO_HS_TX 0, 0 +#define TO_LP_RX 1, 1 +#define ECC_SINGLE_ERR 2, 2 +#define ECC_MULTI_ERR 3, 3 +#define CRC_ERR 4, 4 +#define PKR_SIZE_ERR 5, 5 +#define EOPT_ERR 6, 6 +#define DPI_PID_WR_ERR 7, 7 +#define GEN_CMD_WR_ERR 8, 8 +#define GEN_PLD_WR_ERR 9, 9 +#define GEN_PLD_SEND_WRR 10, 10 +#define GEN_PLD_RD_ERR 11, 11 +#define GEN_PLD_RECEV_ERR 12, 12 + +#define VID_SHADOW_EN 0, 0 +#define VID_SHADOW_REQ 8, 8 +#define VID_SHADOW_PIN_REQ 16, 16 + +#define DPI_VCID 0, 1 + +struct video_config { + unsigned char virtual_channel; + enum dsi_video_mode video_mode; + unsigned int receive_ack_packets; + + enum lcdc_signal_polarity data_en_polarity; + + enum lcdc_signal_level h_polarity; + unsigned short h_active_pixels; /* hadr */ + unsigned short hs; + unsigned short hbp; /* hbp */ + unsigned short h_total_pixels; /* h_total */ + + enum lcdc_signal_level v_polarity; + unsigned short v_active_lines; /* vadr */ + unsigned short vs; + unsigned short vbp; /* vbp */ + unsigned short vfp; /* v_total */ + + unsigned int byte_clock; + unsigned int pixel_clock; + + unsigned int chunk; + unsigned int null_size; + unsigned int video_size; + + unsigned int bpp_info; +}; + +struct dsi_config { + unsigned char num_of_lanes; + unsigned char max_hs_to_lp_cycles; + unsigned char max_lp_to_hs_cycles; + unsigned short max_bta_cycles; + enum lcdc_signal_polarity color_mode_polarity; + enum lcdc_signal_polarity shut_down_polarity; + enum dsi_color_coding color_coding; + enum mipi_dsi_18bit_type color_type_18bit; + int te_mipi_en; +}; +void dsi_delay(uint32_t d); + +void set_bit_field(unsigned long *reg, int start, int end, unsigned long val); + +void set_bit_field_v(volatile unsigned long *reg, int start, int end, unsigned long val); + +unsigned long get_bit_field_v(volatile unsigned long *reg, int start, int end); + +unsigned int dsi_get_phy_status(void); + +void dsi_set_bit(unsigned int reg, int start, int end, unsigned int val); + +int dsi_write_short_packet(unsigned char vc, unsigned char packet_type, unsigned short cmd_data); + +int dsi_write_long_packet(unsigned char vc, unsigned char packet_type, unsigned char *cmd_data, unsigned short word_count); + +int dsi_read_packet(int bytes, unsigned char *rd_buf); + +void dsi_set_transfer_mode(int mode); + +void dsi_set_cmd_mode(void); + +void dsi_set_edpi_cmd_size(unsigned short size); + +void dsi_set_power(unsigned int power); + +void dsi_set_edpi_cmd_size(unsigned short size); + +int jz_dsi_video_init(struct video_config *video_config); + +int jz_dsi_set_clock(unsigned int clk); + +void jz_dsi_dphy_init(struct dsi_config *dsi_config); + +void jz_dsi_gen_init(struct dsi_config *dsi_config); +#endif + diff --git a/drivers/drivers-x16xx/src/x16xx_hal_lcd_x2000.c b/drivers/drivers-x16xx/src/x16xx_hal_lcd_x2000.c new file mode 100644 index 00000000..62c38325 --- /dev/null +++ b/drivers/drivers-x16xx/src/x16xx_hal_lcd_x2000.c @@ -0,0 +1,808 @@ +/** + * @file x16xx_hal_template.c + * @author MPU系统软件部团队 + * @brief [!!!!删除此内容，添加文件简介!!!!] + * + * @copyright 版权所有 (北京君正集成电路股份有限公司) {2022} + * @copyright Copyright© 2022 Ingenic Semiconductor Co.,Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + @verbatim + ============================================================================== + ##### 使用说明 ##### + ============================================================================== + [!!!!删除此内容，添加针对模块的使用方法说明，例如： 配置，启动/停止，状态，重点提醒等等.!!!!] + @endverbatim + */ + +/* 1.头文件 (Includes)--------------------------------------------------- */ +#include "x16xx_hal.h" +/** @addtogroup g_X16XX_TEMPLATE_HAL_Driver + * @{ + */ + +/* 2.私有常量定义 (Private Constants) ----------------------------------- */ +/** + * @addtogroup TEMPLATE_private_constants TEMPLATE 私有常量定义 (Private Constants) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 3.私有类型定义 (Private Types) --------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_types TEMPLATE 私有类型定义 (Private Types) + * @{ + */ +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 4.私有宏定义 (Private Macros) ---------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_macros TEMPLATE 私有宏定义 (Private Macros) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 5.私有变量申明 (Private Variables) ----------------------------------- */ +/** + * @addtogroup TEMPLATE_private_var TEMPLATE 私有变量申明 (Private Variables) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 6.私有函数申明 (Private Funcs) --------------------------------------- */ +/** + * @addtogroup TEMPLATE_private_funcs TEMPLATE 私有函数申明 (Private Funcs) + * @{ + */ + +// 删除此行, 添加内容 +// 删除此行, 添加内容 + +/** + * @} + */ +/* 7.私有函数实现 (Private Funcs) -------------------------------------- */ +/** + * @defgroup TEMPLATE_private_funcs_impl TEMPLATE 私有函数实现 (Private Funcs) + * @{ + */ +static void lcdc_dump_regs(LCD_HandleTypeDef *hlcd) +{ + prom_printk("==================================================================================\n"); + prom_printk("SRD_CHAIN_ADDR = %08x\n", hlcd->Instance->DC_SRD_CHAIN_ADDR); //0x1000 + prom_printk("SRD_CHAIN_CTRL = %08x\n", hlcd->Instance->DC_SRD_CHAIN_CTRL); //0x1004 + prom_printk("CTRL = %08x\n", hlcd->Instance->DC_CTRL); //0x2000 + prom_printk("ST = %08x\n", hlcd->Instance->DC_ST); //0x2004 + prom_printk("CLR_ST = %08x\n", hlcd->Instance->DC_CLR_ST); //0x2008 + prom_printk("INTC = %08x\n", hlcd->Instance->DC_INTC); //0x200C + prom_printk("INT_FLAG = %08x\n", hlcd->Instance->DC_INT_FLAG); //0x2010 + prom_printk("COM_CFG = %08x\n", hlcd->Instance->DC_COM_CONFIG); //0x2014 + prom_printk("PCFG_RD_CTRL = %08x\n", hlcd->Instance->DC_PCFG_RD_CTRL); //0x2018 + prom_printk("PCFG_OFIFO = %08x\n", hlcd->Instance->DC_PCFG_OFIFO); //0x2020 + prom_printk("RDMA_DES = %08x\n", hlcd->Instance->DC_RDMA_DES); //0x2114 + prom_printk("RDMA_CHAIN_SITE = %08x\n", hlcd->Instance->DC_RDMA_CHAIN_SITE);//0x2204 + prom_printk("RDMA_SITE = %08x\n", hlcd->Instance->DC_RDMA_SITE); //0x3110 + prom_printk("DISP_COM = %08x\n", hlcd->Instance->DISP_COM); //0x8000 + + prom_printk("SLCD_CFG = %08x\n", hlcd->Instance->SLCD_PANEL_CFG); //0xA000 + prom_printk("SLCD_WR_DUTY = %08x\n", hlcd->Instance->SLCD_WR_DUTY); //0xA004 + prom_printk("SLCD_TIMING = %08x\n", hlcd->Instance->SLCD_TIMING); //0xA008 + prom_printk("SLCD_FRM_SIZE = %08x\n", hlcd->Instance->SLCD_FRM_SIZE); //0xA00C + prom_printk("SLCD_SLOW_TIME = %08x\n", hlcd->Instance->SLCD_SLOW_TIME); //0xA010 + prom_printk("SLCD_REG_IF = %08x\n", hlcd->Instance->SLCD_REG_IF); //0xA014 + prom_printk("SLCD_ST = %08x\n", hlcd->Instance->SLCD_ST); //0xA018 + prom_printk("SLCD_REG_CTRL = %08x\n", hlcd->Instance->SLCD_REG_CTRL); //0xA01C + + prom_printk("TFT_HSYNC = %08x\n", hlcd->Instance->TFT_TIMING_HSYNC); //0x9000 + prom_printk("TFT_VSYNC = %08x\n", hlcd->Instance->TFT_TIMIING_VSYNC); //0x9004 + prom_printk("TFT_HDE = %08x\n", hlcd->Instance->TFT_TIMIING_HDE); //0x9008 + prom_printk("TFT_VDE = %08x\n", hlcd->Instance->TFT_TIMIING_VDE); //0x900C + prom_printk("TFT_CFG = %08x\n", hlcd->Instance->TFT_TRAN_CFG); //0x9010 + prom_printk("TFT_ST = %08x\n", hlcd->Instance->TFT_ST); //0x9014 + prom_printk("==================================================================================\n"); +} + +static void init_tft(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + int hps = pdata->hsync_len; + int hpe = hps + pdata->left_margin + pdata->xres + pdata->right_margin; + int vps = pdata->vsync_len; + int vpe = vps + pdata->upper_margin + pdata->yres + pdata->lower_margin; + int hds = pdata->hsync_len + pdata->left_margin; + int hde = hds + pdata->xres; + int vds = pdata->vsync_len + pdata->upper_margin; + int vde = vds + pdata->yres; + + __HAL_HPS(hlcd,hps); + __HAL_HPE(hlcd,hpe); + __HAL_VPS(hlcd,vps); + __HAL_VPE(hlcd,vpe); + __HAL_HDS(hlcd,hds); + __HAL_HDE(hlcd,hde); + __HAL_VDS(hlcd,vds); + __HAL_VDE(hlcd,vde); + + if(pdata->tft.pix_clk_polarity == AT_FALLING_EDGE){ + __HAL_SET_CLK_INV(hlcd); + }else{ + __HAL_CLEAR_CLK_INV(hlcd); + } + if(pdata->tft.de_active_level == AT_LOW_LEVEL){ + __HAL_SET_DE_DL(hlcd); + }else{ + __HAL_CLEAR_DE_DL(hlcd); + } + if(pdata->tft.hsync_active_level == AT_LOW_LEVEL){ + __HAL_SET_HSYNC_DL(hlcd); + }else{ + __HAL_CLEAR_HSYNC_DL(hlcd); + } + if(pdata->tft.vsync_active_level == AT_LOW_LEVEL){ + __HAL_SET_VSYNC_DL(hlcd); + }else{ + __HAL_CLEAR_VSYNC_DL(hlcd); + } + __HAL_COLOR_EVEN(hlcd,pdata->tft.even_line_order); + __HAL_COLOR_ODD(hlcd,pdata->tft.odd_line_order); + __HAL_TFAN(hlcd,pdata->lcd_mode); +} + +static void init_tft_mipi(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + int hps = pdata->hsync_len; + int hpe = hps + pdata->left_margin + pdata->xres + pdata->right_margin; + int vps = pdata->vsync_len; + int vpe = vps + pdata->upper_margin + pdata->yres + pdata->lower_margin; + int hds = pdata->hsync_len + pdata->left_margin; + int hde = hds + pdata->xres; + int vds = pdata->vsync_len + pdata->upper_margin; + int vde = vds + pdata->yres; + + __HAL_HPS(hlcd,hps); + __HAL_HPE(hlcd,hpe); + __HAL_VPS(hlcd,vps); + __HAL_VPE(hlcd,vpe); + __HAL_HDS(hlcd,hds); + __HAL_HDE(hlcd,hde); + __HAL_VDS(hlcd,vds); + __HAL_VDE(hlcd,vde); + + __HAL_CLEAR_CLK_INV(hlcd); + __HAL_CLEAR_DE_DL(hlcd); + __HAL_CLEAR_SYNC_DL(hlcd); + __HAL_COLOR_EVEN(hlcd, 0); + __HAL_COLOR_ODD(hlcd, 0); + switch (pdata->out_format) { + case OUT_FORMAT_RGB888: + __HAL_TFAN(hlcd, 0); + break; + case OUT_FORMAT_RGB666: + __HAL_TFAN(hlcd, 1); + break; + case OUT_FORMAT_RGB565: + __HAL_TFAN(hlcd, 2); + break; + default: + break; + } +} + +static void init_slcd(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + int dbi_type = 2; + /* 判断传输格式 */ + if (pdata->lcd_mode == SLCD_6800) + dbi_type = 1; + if (pdata->lcd_mode == SLCD_8080) + dbi_type = 2; + if (pdata->lcd_mode == SLCD_SPI_3LINE) + dbi_type = 4; + if (pdata->lcd_mode == SLCD_SPI_4LINE) + dbi_type = 5; + + int pix_fmt = pdata->out_format; + if (pdata->out_format == OUT_FORMAT_RGB444) + pix_fmt = 1; + if (pdata->out_format == OUT_FORMAT_RGB555) + prom_printk("slcd outformat can't be 555\n"); + + __HAL_RDY_PIXCLK_1(hlcd); /* 设置RDY的抗抖动 */ + __HAL_FMT_DIS(hlcd); /* 通过REG_IF转换像素 */ + __HAL_DBI_TYPE(hlcd,dbi_type); /* 设置传输格式 */ + __HAL_PIX_FMT(hlcd,pix_fmt); /* 设置颜色(RGB)格式 */ + __HAL_TE_ANTI_JIT_3(hlcd); /* 使用3个pixclk周期对TE进行采样，以防抖动 */ + __HAL_TE_MD_FRONT(hlcd); /* 设置TE的活动边沿 */ + /* 选择是否等待TE，再发送数据 */ + if(pdata->slcd.te_pin_mode == TE_LCDC_TRIGGER){ + __HAL_TE_SWITCH_WAIT(hlcd); + }else{ + __HAL_TE_SWITCH_NOWAIT(hlcd); + } + /* 选择是否等待RDY，再发送命令或数据*/ + __HAL_RDY_SWITCH(hlcd,pdata->slcd.enable_rdy_pin); + __HAL_CS_EN_GPIO(hlcd); /* 设置CS引脚由GPIO控制还是SLCD控制 */ + __HAL_CS_DP_HIGH(hlcd); /* 设置CS的默认极性 */ + /* 设置RDY的默认极性*/ + if(pdata->slcd.rdy_cmd_send_level == AT_HIGH_LEVEL){ + __HAL_RDY_DP_HIGH(hlcd); + }else{ + __HAL_RDY_DP_LOW(hlcd); + } + /* 设置命令和数据的默认电平值 */ + if(pdata->slcd.dc_pin == CMD_HIGH_DATA_LOW){ + __HAL_DC_MD_HIGH(hlcd); + }else{ + __HAL_DC_MD_LOW(hlcd); + } + /* */ + if(pdata->slcd.wr_data_sample_edge == AT_RISING_EDGE){ + __HAL_WR_MD_LOW(hlcd); + }else{ + __HAL_WR_MD_HIGH(hlcd); + } + /* 设置读写电平 */ + if(pdata->slcd.te_data_transfered_edge == AT_RISING_EDGE){ + __HAL_TE_DP_HIGH(hlcd); + }else{ + __HAL_TE_DP_LOW(hlcd); + } + __HAL_DWIDTH(hlcd,pdata->slcd.mcu_data_width); /* 设置屏幕数据总线宽度 */ + __HAL_CWIDTH(hlcd,pdata->slcd.mcu_cmd_width); /* 面板命令及其参数的宽度。单位bit */ + WRITE_REG(hlcd->Instance->SLCD_WR_DUTY, 0); /* */ + WRITE_REG(hlcd->Instance->SLCD_TIMING, 0); + __HAL_V_SIZE(hlcd,pdata->yres); /* 设置屏幕宽高 */ + __HAL_H_SIZE(hlcd,pdata->xres); + WRITE_REG(hlcd->Instance->SLCD_SLOW_TIME, 0); /* 设置延时 */ + //prom_printk("hlcd->Instance->SLCD_PANEL_CFG = %08x\n",hlcd->Instance->SLCD_PANEL_CFG); +} + +static void inline init_slcd_mipi(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + + if(pdata->slcd.te_pin_mode == TE_LCDC_TRIGGER){ + __HAL_TE_SWITCH_WAIT(hlcd); + }else{ + __HAL_TE_SWITCH_NOWAIT(hlcd); + } + + if(pdata->slcd.te_data_transfered_edge == AT_RISING_EDGE){ + __HAL_TE_DP_HIGH(hlcd); + }else{ + __HAL_TE_DP_LOW(hlcd); + } + __HAL_DWIDTH(hlcd,pdata->slcd.mcu_data_width); + __HAL_CWIDTH(hlcd,pdata->slcd.mcu_cmd_width); + + WRITE_REG(hlcd->Instance->SLCD_WR_DUTY, 0); + WRITE_REG(hlcd->Instance->SLCD_TIMING, 0); + + __HAL_V_SIZE(hlcd,pdata->yres); + __HAL_H_SIZE(hlcd,pdata->xres); + WRITE_REG(hlcd->Instance->SLCD_SLOW_TIME, 0); +} + +static inline unsigned long bit_field_mask(int start, int end) +{ + unsigned long e = (1ul << end); + unsigned long s = (1ul << start); + return (e - s) + e; +} + +static int tft_init_gpio(int r, int g, int b) +{ + int i; + unsigned int pins = + bit_field_mask(TFT_d7 - b + 1, TFT_d7) | + bit_field_mask(TFT_d15 - g + 1, TFT_d15) | + bit_field_mask(TFT_d23 - r + 1, TFT_d23) | + (1 << TFT_pclk) | (1 << TFT_de) | (1 << TFT_vsync) | (1 << TFT_hsync); + for (i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(GPIOA_Instance, i, GPIO_MODE_FUNCTION0); + } + } + return 0; +} +static int tft_serial_init_gpio(void) +{ + unsigned int pins = + bit_field_mask(TFT_d0, TFT_d7) | + (1 << TFT_pclk) | (1 << TFT_de) | (1 << TFT_vsync) | (1 << TFT_hsync); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(GPIOA_Instance, i, GPIO_MODE_FUNCTION0); + } + } + return 0; +} +static int slcd_init_gpio_data8(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d7) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(GPIOA_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} +static int slcd_init_gpio_data9(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d8) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(GPIOA_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} +static int slcd_init_gpio_data16(void) +{ + unsigned int pins = bit_field_mask(TFT_d0, TFT_d15) | (1 << SLCD_DC) | (1 << SLCD_WR) | (1 << SLCD_TE); + for (int i = 0; i < 32; i++) { + if(pins & (1 << i)){ + LL_GPIO_setPinMode(GPIOA_Instance, i, GPIO_MODE_FUNCTION1); + } + } + return 0; +} + +static int init_lcd_gpio(struct lcd_data *pdata) +{ + int ret = -HAL_ERROR; + + switch (pdata->lcd_mode) { + case TFT_24BITS: + if (pdata->out_format == OUT_FORMAT_RGB444) + ret = tft_init_gpio(4, 4, 4); + if (pdata->out_format == OUT_FORMAT_RGB555) + ret = tft_init_gpio(5, 5, 5); + if (pdata->out_format == OUT_FORMAT_RGB565) + ret = tft_init_gpio(5, 6, 5); + if (pdata->out_format == OUT_FORMAT_RGB666) + ret = tft_init_gpio(6, 6, 6); + if (pdata->out_format == OUT_FORMAT_RGB888) + ret = tft_init_gpio(8, 8, 8); + break; + + case TFT_8BITS_SERIAL: + case TFT_8BITS_DUMMY_SERIAL: + ret = tft_serial_init_gpio(); + break; + + case TFT_MIPI: + ret = 0; + break; + + case SLCD_6800: + case SLCD_8080:{ + int width; + if(pdata->slcd.mcu_cmd_width > pdata->slcd.mcu_data_width){ + width = pdata->slcd.mcu_cmd_width; + }else{ + width = pdata->slcd.mcu_data_width; + } + if (width == MCU_WIDTH_8BITS) + ret = slcd_init_gpio_data8(); + if (width == MCU_WIDTH_9BITS) + ret = slcd_init_gpio_data9(); + if (width == MCU_WIDTH_16BITS) + ret = slcd_init_gpio_data16(); + break; + } + case SLCD_MIPI: + ret = 0;//待实现 + break; + + default: + prom_printk("This mode is not currently implemented: %d\n", pdata->lcd_mode); + break; + } + return ret; +} + +static int slcd_wait_busy(LCD_HandleTypeDef * hlcd, unsigned int count) +{ + int busy; + busy = __HAL_ST_BUSY(hlcd); + + while (count-- && busy) { + busy = __HAL_ST_BUSY(hlcd); + } + return busy; +} + +static void slcd_send_cmd(LCD_HandleTypeDef * hlcd, unsigned int cmd) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_CMD(hlcd, cmd); +} + +static void slcd_send_data(LCD_HandleTypeDef *hlcd, unsigned int data) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_DATA(hlcd, data); +} + +static void slcd_send_prm(LCD_HandleTypeDef *hlcd, unsigned int prm) +{ + if (slcd_wait_busy(hlcd,10 * 1000)) + prom_printk("lcdc busy\n"); + + __HAL_SEND_PRM(hlcd, prm); +} + +void process_slcd_data_table(LCD_HandleTypeDef * hlcd, struct smart_lcd_data_table *table, unsigned int length) +{ + int i = 0; + for (; i < length; i++) { + switch (table[i].type) { + case SMART_CONFIG_CMD: + slcd_send_cmd(hlcd,table[i].value); + break; + case SMART_CONFIG_DATA: + slcd_send_data(hlcd,table[i].value); + break; + case SMART_CONFIG_PRM: + slcd_send_prm(hlcd,table[i].value); + break; + case SMART_CONFIG_UDELAY: + HAL_uDelay(table[i].value); + break; + default: + prom_printk("why this type: %d\n", table[i].type); + break; + } + } + if (slcd_wait_busy(hlcd, 10 * 1000)) + prom_printk("lcdc busy\n"); +} + +static int check_scld_fmt(LCD_HandleTypeDef * hlcd) +{ + struct lcd_data *pdata = hlcd->pdata; + int pix_fmt = pdata->out_format; + + if (pdata->lcd_mode >= SLCD_SPI_3LINE) + return -1; + + int width = pdata->slcd.mcu_data_width; + if (width == MCU_WIDTH_8BITS) { + if (pix_fmt != OUT_FORMAT_RGB565 && pix_fmt != OUT_FORMAT_RGB888) + return -1; + } + if (width == MCU_WIDTH_9BITS) { + if (pix_fmt != OUT_FORMAT_RGB666) + return -1; + } + if (width == MCU_WIDTH_16BITS) { + if (pix_fmt != OUT_FORMAT_RGB565) + return -1; + } + + return 0; +} + +static inline int is_tft(struct lcd_data *pdata) +{ + return pdata->lcd_mode <= TFT_8BITS_DUMMY_SERIAL; +} + +static inline int is_slcd(struct lcd_data *pdata) +{ + return pdata->lcd_mode >= SLCD_6800 && pdata->lcd_mode != SLCD_MIPI; +} + +static inline int is_slcd_mipi(struct lcd_data *pdata) +{ + return pdata->lcd_mode == SLCD_MIPI; +} + +static inline int is_tft_mipi(struct lcd_data *pdata) +{ + return pdata->lcd_mode == TFT_MIPI; +} + +static int wait_dc_state(LCD_HandleTypeDef *hlcd, uint32_t state, uint32_t flag) +{ + unsigned long timeout = 20000; + while(((!(READ_REG(hlcd->Instance->DC_ST) & state)) == flag) && timeout) { + timeout--; + HAL_uDelay(10); + } + if(timeout <= 0) { + prom_printk("LCD wait state timeout! state = 0x%08x, DC_ST = 0x%08x\n", state, READ_REG(hlcd->Instance->DC_ST)); + return -1; + } + + return 0; +} + +static void init_lcdc(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + + __HAL_EOD_MSK(hlcd); + __HAL_SOC_MSK(hlcd); + __HAL_SCA_MSK(hlcd); + __HAL_SSA_MSK(hlcd); + __HAL_UOT_MSK(hlcd); + __HAL_SOS_MSK(hlcd); + __HAL_EOW_MSK(hlcd); + __HAL_OOW_MSK(hlcd); + + WRITE_REG(hlcd->Instance->DC_CLR_ST, READ_REG(hlcd->Instance->DC_INT_FLAG)); + + __HAL_BURST_LEN_WDMA(hlcd, BURST_LEN_WDMA_32); + __HAL_BURST_LEN_RDMA(hlcd, BURST_LEN_RDMA_32); + __HAL_BURST_LEN_BDMA(hlcd, BURST_LEN_BDMA_32); + __HAL_CH_SEL(hlcd, CH_SEL_SR); + + int dither_en = 0; + int dither_dw = 0; + if (pdata->fb_fmt == fb_fmt_RGB888 || pdata->fb_fmt == fb_fmt_ARGB8888) { + if (pdata->out_format != OUT_FORMAT_RGB888) + dither_en = 1; + if (pdata->out_format == OUT_FORMAT_RGB444) + dither_dw = 0b111111; + if (pdata->out_format == OUT_FORMAT_RGB555) + dither_dw = 0b101010; + if (pdata->out_format == OUT_FORMAT_RGB565) + dither_dw = 0b100110; + if (pdata->out_format == OUT_FORMAT_RGB666) + dither_dw = 0b010101; + } + + __HAL_DP_DITHER_EN(hlcd, dither_en); + __HAL_DP_DITHER_DW(hlcd, dither_dw); + + __HAL_DITHER_CLKGATE_EN(hlcd); + __HAL_SLCD_CLKGATE_EN(hlcd); + __HAL_TFT_CLKGATE_EN(hlcd); + + if(is_slcd_mipi(pdata)) { + __HAL_DP_IF_SEL(hlcd, DISPLAY_SELECT_SLCD_MIPI); + prom_printk("is_slcd_mipi \n"); + } else if(is_slcd(pdata)) { + __HAL_DP_IF_SEL(hlcd, DISPLAY_SELECT_SLCD); + prom_printk("is_slcd \n"); + } else { + __HAL_DP_IF_SEL(hlcd, DISPLAY_SELECT_TFT); + prom_printk("is_tft \n"); + } + + if (is_tft_mipi(pdata)){ + init_tft_mipi(hlcd); + prom_printk("tft_mipi mode \n"); + } + if(is_slcd_mipi(pdata)) { + init_slcd_mipi(hlcd); + prom_printk("slcd_mipi mode \n"); + } + if (is_tft(pdata)){ + init_tft(hlcd); + prom_printk("tft mode \n"); + } + if (is_slcd(pdata)){ + init_slcd(hlcd); + prom_printk("slcd mode \n"); + } + + if (is_tft_mipi(pdata) || is_slcd_mipi(pdata)) + jz_enable_mipi_dsi(); + +} + +static int slcd_pixclock_cycle(struct lcd_data *pdata) +{ + + int cycle = 0; + int width = pdata->slcd.mcu_data_width; + int pix_fmt = pdata->out_format; + if (width == MCU_WIDTH_8BITS) { + if (pix_fmt == OUT_FORMAT_RGB565) + cycle = 2; + if (pix_fmt == OUT_FORMAT_RGB888) + cycle = 3; + } + if (width == MCU_WIDTH_9BITS) { + if (pix_fmt == OUT_FORMAT_RGB666) + cycle = 2; + } + if (width == MCU_WIDTH_16BITS) { + if (pix_fmt == OUT_FORMAT_RGB666) + cycle = 1; + } + + return cycle * 2 + 1; +} + +void auto_calculate_pixel_clock(struct lcd_data *pdata) +{ + int hps = pdata->hsync_len; + int hpe = hps + pdata->left_margin + pdata->xres + pdata->right_margin; + int vps = pdata->vsync_len; + int vpe = vps + pdata->upper_margin + pdata->yres + pdata->lower_margin; + + if (!pdata->refresh) + pdata->refresh = 40; + + if (is_tft(pdata) || is_tft_mipi(pdata)) { + if (!pdata->pixclock) + pdata->pixclock = hpe * vpe * pdata->refresh; + } + + if (is_slcd(pdata)) { + if (!pdata->pixclock) { + pdata->pixclock = pdata->xres * pdata->yres * pdata->refresh; + pdata->pixclock *= slcd_pixclock_cycle(pdata); + } + + if (!pdata->slcd.pixclock_when_init) + pdata->slcd.pixclock_when_init = pdata->xres * pdata->yres * 3; + } + + if (is_slcd_mipi(pdata)) { + if (!pdata->pixclock) { + pdata->pixclock = pdata->xres * pdata->yres * pdata->refresh * 4; + } + } +} + +void HAL_LCDC_INIT(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd->pdata; + int ret; + + __HAL_Lock_Init(hlcd->lock); + + if (is_slcd(pdata)){ + ret = check_scld_fmt(hlcd); + if(ret < 0) + prom_printk("slcd fmt error\n"); + } + + ret = init_lcd_gpio(pdata); + if(ret < 0) + prom_printk("init lcd gpio failed\n"); + + auto_calculate_pixel_clock(pdata); + + if (is_slcd_mipi(pdata) || is_tft_mipi(pdata)) { + int ret = jz_mipi_dsi_data_init(pdata); + if(ret < 0) + prom_printk("init dsi data error\n"); + } +} + +void HAL_LCDC_ENABLE(LCD_HandleTypeDef *hlcd) +{ + struct lcd_data *pdata = hlcd -> pdata; + + init_lcdc(hlcd); + + if (pdata->power_on){ + pdata->power_on(); + } + if (pdata->lcd_init){ + pdata->lcd_init(); + } + + if (is_slcd(pdata)){ + process_slcd_data_table(hlcd, pdata->slcd_data_table, pdata->slcd_data_table_length); + __HAL_FMT_EN(hlcd); + } + if (is_tft_mipi(pdata)) + jz_dsi_video_cfg(); + + if (is_slcd_mipi(pdata)) + jz_dsi_command_cfg(); +} + +void HAL_SRDMA_INIT(LCD_HandleTypeDef *hlcd, uint32_t *buffer) +{ + int format; + switch (hlcd->pdata->fb_fmt) { + case fb_fmt_RGB555: + format = 0; break; + case fb_fmt_RGB565: + format = 2; break; + case fb_fmt_ARGB8888: + case fb_fmt_RGB888: + format = 4; break; + default: + prom_printk("format err:%d\n", hlcd->pdata->fb_fmt); break; + } + + hlcd->desc->RdmaNextCfgAddr = CPHYSADDR(hlcd->desc); + + hlcd->desc->FrameCtrl = 0; + hlcd->desc->FrameCtrl |= (format << 19); + hlcd->desc->FrameCtrl |= (0 << 16); + hlcd->desc->FrameCtrl &= ~(1); + hlcd->desc->FrameCtrl |= (1 << 1); + + hlcd->desc->InterruptControl = 0; + __HAL_EOS_MSK(hlcd); + + hlcd->desc->stride = hlcd->pdata->xres; + hlcd->desc->FrameBufferAddr = CPHYSADDR(buffer); + + CleanDCache_by_Addr((unsigned long*)hlcd->desc, sizeof(struct srdmadesc)); + + WRITE_REG(hlcd->Instance->DC_SRD_CHAIN_ADDR, CPHYSADDR(hlcd->desc)); +} + +void HAL_SRDMA_START(LCD_HandleTypeDef *hlcd) +{ + __HAL_SRD_CHAIN_START(hlcd); +} + +void lcdc_irq_handler(int irq, void *data) +{ + LCD_HandleTypeDef *hlcd = (LCD_HandleTypeDef*)data; + + __HAL_Lock(hlcd->lock); + + if (__HAL_INT_EOD(hlcd)) { + prom_printk("__HAL_INT_EOD\n"); + __GEN_CLR_DISP_END(hlcd); + __HAL_UnLock(hlcd->lock); + return; + } + if (__HAL_INT_SSA(hlcd)) { + prom_printk("__HAL_INT_SSA\n"); + __GEN_CLR_STOP_SRD_ACK(hlcd); + __HAL_UnLock(hlcd->lock); + return; + } + + if (__HAL_INT_UOT(hlcd)) { + prom_printk("err: lcd underrun\n"); + __GEN_CLR_TFT_UNDR(hlcd); + __HAL_UnLock(hlcd->lock); + return; + } + if (__HAL_INT_EOS(hlcd)) { + prom_printk("RDMA END\n"); + __GEN_CLR_SRD_END(hlcd); + __HAL_UnLock(hlcd->lock); + return; + } + if (__HAL_INT_SOS(hlcd)) { + __GEN_CLR_SRD_START(hlcd); + prom_printk("RDAM START\n"); + __HAL_UnLock(hlcd->lock); + return; + } +} + diff --git a/drivers/drivers-x16xx/src/x16xx_hal_mipi_dsi.c b/drivers/drivers-x16xx/src/x16xx_hal_mipi_dsi.c new file mode 100644 index 00000000..efeae2d5 --- /dev/null +++ b/drivers/drivers-x16xx/src/x16xx_hal_mipi_dsi.c @@ -0,0 +1,244 @@ +#include "x16xx_hal.h" +#include "x16xx_ll_mipi_dsi.h" + +static struct { + struct video_config video_config; + struct dsi_config dsi_config; + int dsi_en; +}jz_dsi; + +static inline int mipi_bpp_per_pixel(struct lcd_data *data) +{ + switch (data->mipi.color_coding) { + case COLOR_CODE_16BIT_CONFIG1: + case COLOR_CODE_16BIT_CONFIG2: + case COLOR_CODE_16BIT_CONFIG3: + return 16; + + case COLOR_CODE_18BIT_CONFIG1: + case COLOR_CODE_18BIT_CONFIG2: + return 18; + + case COLOR_CODE_24BIT: + return 24; + default: + break; + } + + prom_printk("no support this color coding\n"); + return 0; +} + +int dsi_write_cmd(struct dsi_cmd_packet *cmd_data) +{ + unsigned int packet_type; + unsigned short word_count = 0; + unsigned int ret; + /*word count*/ + packet_type = cmd_data->packet_type; + word_count = ((cmd_data->cmd1_or_wc_msb << 8 ) | cmd_data->cmd0_or_wc_lsb); + + if (packet_type == 0x39) { + ret = dsi_write_long_packet(jz_dsi.video_config.virtual_channel, packet_type, cmd_data->cmd_data, word_count); + if (ret < 0) + return -1; + } + + if (packet_type == 0x05 || packet_type == 0x15) { + ret = dsi_write_short_packet(jz_dsi.video_config.virtual_channel, packet_type, word_count); + if (ret < 0) + return -1; + } + + dsi_delay(30000); + return 0; +} + +int dsi_read_cmd(struct dsi_cmd_packet *cmd_data, int bytes, unsigned char *rd_buf) +{ + unsigned int packet_type; + unsigned short short_data = 0; + unsigned int ret; + + dsi_set_bit(R_DSI_HOST_GEN_VCID, GEN_VICD_RX, jz_dsi.video_config.virtual_channel); + + packet_type = cmd_data->packet_type; + short_data = ((cmd_data->cmd1_or_wc_msb << 8 ) | cmd_data->cmd0_or_wc_lsb); + + if (packet_type != 0x04 && packet_type != 0x14 && packet_type != 0x24 && packet_type != 0x06) { + prom_printk("dsi_read :not suport this packet_type = %x\n", packet_type); + return -1; + } + + ret = dsi_write_short_packet(jz_dsi.video_config.virtual_channel, packet_type, short_data); + if (ret < 0) + return -1; + + ret = dsi_read_packet(bytes, rd_buf); + if (ret < 0) + return -1; + + return 0; +} + + +static void calculate_video_mode_chunck(void) +{ + //burst mode + if (jz_dsi.video_config.video_mode == VIDEO_BURST_WITH_SYNC_PULSES) { + jz_dsi.video_config.null_size = 0; + jz_dsi.video_config.chunk = 0; + jz_dsi.video_config.video_size = jz_dsi.video_config.h_active_pixels; + + if((jz_dsi.dsi_config.color_coding == COLOR_CODE_18BIT_CONFIG1 || + jz_dsi.dsi_config.color_coding == COLOR_CODE_18BIT_CONFIG2) && + jz_dsi.dsi_config.color_type_18bit != LOOSELY18) { + + jz_dsi.video_config.video_size = ALIGN(jz_dsi.video_config.video_size, 4); + } + + return; + } + + //not burst mode + +} + +#define mipi_error_if(_cond) \ + do { \ + if (_cond) { \ + prom_printk("jz_mipi_dsi: failed to check: %s\n", #_cond); \ + ret = -1; \ + return ret; \ + } \ + } while (0) + +int jz_mipi_dsi_data_init(struct lcd_data *lcd_data) +{ + int ret; + + mipi_error_if(lcd_data == NULL); + mipi_error_if(lcd_data->mipi.num_of_lanes > 2); + mipi_error_if(lcd_data->mipi.num_of_lanes < 1); + mipi_error_if(lcd_data->mipi.video_mode > VIDEO_BURST_WITH_SYNC_PULSES); + mipi_error_if(lcd_data->mipi.color_coding > COLOR_CODE_24BIT); + + int hs = lcd_data->hsync_len; + int hbp = lcd_data->left_margin; + int hfp = lcd_data->right_margin; + int vs = lcd_data->vsync_len; + int vbp = lcd_data->upper_margin; + int vfp = lcd_data->lower_margin; + + int v_total_lines; + + jz_dsi.dsi_config.color_coding = lcd_data->mipi.color_coding; + jz_dsi.dsi_config.num_of_lanes = lcd_data->mipi.num_of_lanes; + jz_dsi.dsi_config.color_mode_polarity = lcd_data->mipi.color_mode_polarity; + jz_dsi.dsi_config.shut_down_polarity = lcd_data->mipi.shut_down_polarity; + jz_dsi.dsi_config.max_bta_cycles = lcd_data->mipi.max_bta_cycles; + jz_dsi.dsi_config.max_hs_to_lp_cycles = lcd_data->mipi.max_hs_to_lp_cycles; + jz_dsi.dsi_config.max_lp_to_hs_cycles = lcd_data->mipi.max_lp_to_hs_cycles; + jz_dsi.dsi_config.color_type_18bit = lcd_data->mipi.color_type_18bit; + + jz_dsi.video_config.virtual_channel = lcd_data->mipi.virtual_channel; + jz_dsi.video_config.video_mode = lcd_data->mipi.video_mode; + jz_dsi.video_config.data_en_polarity = lcd_data->mipi.data_en_polarity; + + jz_dsi.video_config.h_active_pixels = lcd_data->xres; + jz_dsi.video_config.hs = hs; + jz_dsi.video_config.hbp = hbp; + jz_dsi.video_config.h_total_pixels = hs + hbp + lcd_data->xres + hfp; + + jz_dsi.video_config.vs = vs; + jz_dsi.video_config.vbp = vbp; + jz_dsi.video_config.v_active_lines = lcd_data->yres; + jz_dsi.video_config.vfp = vfp; + + v_total_lines = vs + vbp + lcd_data->yres + vfp; + + jz_dsi.video_config.h_polarity = lcd_data->mipi.hsync_active_level; + jz_dsi.video_config.v_polarity = lcd_data->mipi.vsync_active_level; + jz_dsi.video_config.pixel_clock = lcd_data->pixclock / 1000; + jz_dsi.video_config.bpp_info = mipi_bpp_per_pixel(lcd_data); + + + jz_dsi.video_config.byte_clock = jz_dsi.video_config.h_total_pixels * v_total_lines * lcd_data->refresh * 32 / jz_dsi.dsi_config.num_of_lanes / 8 / 1000 * 6 / 5; + + + if (lcd_data->mipi.slcd_te_pin_mode != TE_NOT_EANBLE) + jz_dsi.dsi_config.te_mipi_en = 1; + + calculate_video_mode_chunck(); + + return 0; +} + +void jz_dsi_command_cfg(void) +{ + dsi_set_edpi_cmd_size(1024); + dsi_set_bit(R_DSI_HOST_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 1); + dsi_set_bit(R_DSI_HOST_LPCLK_CTRL, AUTO_CLKLANE_CTRL, 1); + + // high speed + dsi_set_transfer_mode(0); + + dsi_set_bit(R_DSI_HOST_VID_MODE_CFG, FRAME_BTA_ACK_EN, 0); + dsi_set_bit(R_DSI_HOST_PCKHDL_CFG, BAT_EN, 0); + + if (jz_dsi.dsi_config.te_mipi_en) + dsi_set_bit(R_DSI_HOST_CMD_MODE_CFG, TEAR_FX_EN, 1); + else + dsi_set_bit(R_DSI_HOST_CMD_MODE_CFG, TEAR_FX_EN, 0); + + dsi_set_cmd_mode(); +} + +void jz_dsi_video_cfg(void) +{ + dsi_set_power(0); + jz_dsi_video_init(&jz_dsi.video_config); + dsi_set_power(1); +} + +void jz_enable_mipi_dsi(void) +{ + int st_mask = 0; + int retry = 5; + jz_dsi_dphy_init(&jz_dsi.dsi_config); + + //LP mode + dsi_set_transfer_mode(1); + dsi_set_cmd_mode(); + dsi_set_edpi_cmd_size(0x6); + + jz_dsi_set_clock(jz_dsi.video_config.byte_clock); + + dsi_set_power(0); + dsi_set_power(1); + + jz_dsi_gen_init(&jz_dsi.dsi_config); + + dsi_set_power(0); + dsi_set_power(1); + + if(jz_dsi.dsi_config.num_of_lanes == 2) + st_mask = 0x95; + else + st_mask = 0x15; + + dsi_delay(10); + + while((dsi_get_phy_status() & st_mask) != st_mask && --retry) + prom_printk("phy status = %08x\n", dsi_get_phy_status()); + + if(!retry) + prom_printk("wait for phy config failed!\n"); +} + +void jz_disable_mipi_dsi(void) +{ + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_ENABLECLK, 0); + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_SHUTDOWMZ, 0); + dsi_set_power(0); +} diff --git a/drivers/drivers-x16xx/src/x16xx_ll_mipi_dsi.c b/drivers/drivers-x16xx/src/x16xx_ll_mipi_dsi.c new file mode 100644 index 00000000..1af58567 --- /dev/null +++ b/drivers/drivers-x16xx/src/x16xx_ll_mipi_dsi.c @@ -0,0 +1,571 @@ +/* 1.头文件 (Includes)------------------------------------------------ */ +#include +#include +#include +#include +#include +#include + +#define ARRAY_SIZE(x) (int)( sizeof(x) / sizeof(x)[0] ) +#define io_addr(addr) ((volatile unsigned long *)KSEG1ADDR(addr)) + +#define MIPI_DSI_IOBASE 0x10075000 +#define MIPI_DSI_PHY_IOBASE 0x10077000 +#define MIPI_DSI_ADDR(reg) io_addr(MIPI_DSI_IOBASE + reg) +#define MIPI_DSI_PHY_ADDR(reg) io_addr(MIPI_DSI_PHY_IOBASE + reg) + +#define CMP_IOBASE 0x10000000 +#define CPM_ADDR(reg) io_addr(CMP_IOBASE + reg) +/* 延时函数 */ +void dsi_delay(uint32_t d) +{ + while(d--){ + asm volatile("ssnop\n\t"); + } +} + +/* + * 位字段控制函数 + */ +static inline unsigned long bit_field_mask(int start, int end) +{ + unsigned long e = (1ul << end); + unsigned long s = (1ul << start); + return (e - s) + e; +} + +void set_bit_field(unsigned long *reg, int start, int end, unsigned long val) +{ + unsigned long mask = bit_field_mask(start, end); + *reg = (*reg & ~mask) | ((val << start) & mask); +} + +void set_bit_field_v(volatile unsigned long *reg, int start, int end, unsigned long val) +{ + unsigned long mask = bit_field_mask(start, end); + *reg = (*reg & ~mask) | ((val << start) & mask); +} + +unsigned long get_bit_field_v(volatile unsigned long *reg, int start, int end) +{ + return (*reg & bit_field_mask(start, end)) >> start; +} +/* 位字段控制函数 end*/ + +static void dsi_write(unsigned int reg, unsigned int val) +{ + *MIPI_DSI_ADDR(reg) = val; +} + +static inline unsigned int dsi_read(unsigned int reg) +{ + return *MIPI_DSI_ADDR(reg); +} + +static void dsi_write_phy_clk(unsigned int val) +{ + *MIPI_DSI_PHY_ADDR(0x64) = val; +} + +static inline unsigned int dsi_read_phy_clk(void) +{ + return *MIPI_DSI_PHY_ADDR(0x64); +} + +unsigned int dsi_get_phy_status(void) +{ + return dsi_read(R_DSI_HOST_PHY_STATUS); +} + +void dsi_set_bit(unsigned int reg, int start, int end, unsigned int val) +{ + set_bit_field_v(MIPI_DSI_ADDR(reg), start, end, val); +} + +static inline unsigned int dsi_get_bit(unsigned int reg, int start, int end) +{ + return get_bit_field_v(MIPI_DSI_ADDR(reg), start, end); +} + +void dsi_set_power(unsigned int power) +{ + dsi_set_bit(R_DSI_HOST_PWR_UP, SHUTDOWNZ, power); +} + +static int dsi_set_dphy_hs2lp_time(unsigned char time) +{ + dsi_set_bit(R_DSI_HOST_PHY_TMR_CFG, PHY_HS2LP_TIME, time); + + return 0; +} + +static int dsi_set_dphy_lp2hs_time(unsigned char time) +{ + dsi_set_bit(R_DSI_HOST_PHY_TMR_CFG, PHY_LP2HS_TIME, time); + + return 0; + +} + +static void dsi_set_dphy_bta_time(unsigned short time) +{ + dsi_set_bit(R_DSI_HOST_PHY_TMR_CFG, MAX_RD_TIME, time); +} + +static int dsi_get_cmd_full(void) +{ + return dsi_get_bit(R_DSI_HOST_CMD_PKT_STATUS, GEN_CMD_FULL); +} + +static int dsi_get_pld_w_full(void) +{ + return dsi_get_bit(R_DSI_HOST_CMD_PKT_STATUS, GEN_PLD_W_FUL); +} + +static int dsi_get_rd_cmd_busy(void) +{ + return dsi_get_bit(R_DSI_HOST_CMD_PKT_STATUS, GEN_RD_CMD_BUSY); +} + +static int dsi_get_rd_empty(void) +{ + return dsi_get_bit(R_DSI_HOST_CMD_PKT_STATUS, GEN_PLD_R_EMPTY); +} + +static int dsi_wait_pld_w_not_full(int count) +{ + int status; + status = dsi_get_pld_w_full(); + + while (count-- && status) { + status = dsi_get_pld_w_full(); + } + + return status; +} + +static int dsi_wait_cmd_not_full(int count) +{ + int status; + status = dsi_get_cmd_full(); + + while (count-- && status) { + status = dsi_get_cmd_full(); + } + + return status; +} + +static int dsi_wait_rd_cmd_busy(int count) +{ + int status; + status = dsi_get_rd_cmd_busy(); + + while (count-- && status) { + status = dsi_get_rd_cmd_busy(); + } + + return status; +} + +static int dsi_wait_rd_fifo_empty(int count) +{ + int status; + status = dsi_get_rd_empty(); + + while (count-- && status) { + status = dsi_get_rd_empty(); + } + + return status; +} + +void dsi_set_transfer_mode(int mode)//high speed: 0 / low power: 1 +{ + unsigned long cmd_mode_cfg = dsi_read(R_DSI_HOST_CMD_MODE_CFG);//0x68 + set_bit_field(&cmd_mode_cfg, MAX_RD_PKT_SIZE, mode); + set_bit_field(&cmd_mode_cfg, DCS_SW_0P_TX, mode); + set_bit_field(&cmd_mode_cfg, DCS_SW_1P_TX, mode); + set_bit_field(&cmd_mode_cfg, DCS_SR_0P_TX, mode); + set_bit_field(&cmd_mode_cfg, DCS_LW_TX, mode); + + set_bit_field(&cmd_mode_cfg, GEN_SW_0P_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_SW_1P_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_SW_2P_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_LW_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_SR_0P_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_SR_1P_TX, mode); + set_bit_field(&cmd_mode_cfg, GEN_SR_2P_TX, mode); + + dsi_write(R_DSI_HOST_CMD_MODE_CFG, cmd_mode_cfg); +} + +void dsi_set_cmd_mode(void) +{ + dsi_set_bit(R_DSI_HOST_MODE_CFG, CMD_VIDEO_MODE, 1); +} + +static void dsi_set_video_mode(void) +{ + dsi_set_bit(R_DSI_HOST_MODE_CFG, CMD_VIDEO_MODE, 0); +} + +void dsi_set_edpi_cmd_size(unsigned short size) +{ + dsi_set_bit(R_DSI_HOST_EDPI_CMD_SIZE, EDPI_ALLOWED_CMD_SIZE, size); +} + +struct dphy_pll_range { + unsigned int start_clk_sel; + unsigned int output_freq0; /*start freq in same resolution*/ + unsigned int output_freq1; /*end freq in same resolution*/ + unsigned int resolution; +}; + +struct dphy_pll_range dphy_pll_table[] = { + {0, 63750000, 93125000, 312500}, + {95, 93750000, 186250000, 625000}, + {244, 187500000, 372500000, 1250000}, + {393, 375000000, 745000000, 2500000}, + {542, 750000000, 2750000000UL, 5000000}, +}; + +static int jz_dsih_dphy_configure_x2000(unsigned int output_freq) +{ + int i; + struct dphy_pll_range *pll; + unsigned int pll_clk_sel = 0xffffffff; + + for(i = 0; i < ARRAY_SIZE(dphy_pll_table); i++) { + pll = &dphy_pll_table[i]; + if(output_freq >= pll->output_freq0 && output_freq <= pll->output_freq1) { + pll_clk_sel = pll->start_clk_sel + (output_freq - pll->output_freq0) / pll->resolution; + break; + } + } + if(pll_clk_sel == 0xffffffff) { + printf("can not find appropriate pll freq set for dsi phy! output_freq: %u\n", output_freq); + return -1; + } + dsi_delay(50000); + dsi_write_phy_clk(pll_clk_sel); + return 0; +} + +int jz_dsi_set_clock(unsigned int clk) +{ + int ret; + ret = jz_dsih_dphy_configure_x2000(clk * 1000 * 8); + if (ret < 0) { + printf("set dphy clock error!!\n"); + return -1; + } + + dsi_set_bit(R_DSI_HOST_PHY_IF_CFG, PHY_STOP_WAIT_TIME, 0x1C); + + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_ENABLECLK, 1); + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_SHUTDOWMZ, 1); + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_RSTZ, 1); + + //why 7???? + dsi_set_bit(R_DSI_HOST_CLKMGR_CFG, TX_ESC_CLK_DIV, 7); + + return 0; +} + +void jz_dsi_dphy_init(struct dsi_config *dsi_config) +{ + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_RSTZ, 0); + + dsi_set_bit(R_DSI_HOST_PHY_IF_CFG, PHY_STOP_WAIT_TIME, 0x1c); + + dsi_set_bit(R_DSI_HOST_PHY_IF_CFG, N_LANES, dsi_config->num_of_lanes - 1); + + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_ENABLECLK, 1); + + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_SHUTDOWMZ, 1); + + dsi_set_bit(R_DSI_HOST_PHY_RSTZ, PHY_RSTZ, 1); +} + +void jz_dsi_gen_init(struct dsi_config *dsi_config) +{ + dsi_set_bit(R_DSI_HOST_DPI_CFG_POL, COLORM_ACTIVE_LOW, !dsi_config->color_mode_polarity); + dsi_set_bit(R_DSI_HOST_DPI_CFG_POL, SHUTD_ACTIVE_LOW, !dsi_config->shut_down_polarity); + + dsi_set_dphy_hs2lp_time(dsi_config->max_hs_to_lp_cycles); + dsi_set_dphy_lp2hs_time(dsi_config->max_lp_to_hs_cycles); + dsi_set_dphy_bta_time(dsi_config->max_bta_cycles); + + dsi_set_bit(R_DSI_HOST_GEN_VCID, GEN_VICD_RX, 0); + + unsigned long pckhdl_cfg = dsi_read(R_DSI_HOST_PCKHDL_CFG); + + set_bit_field(&pckhdl_cfg, ETOP_RX_EN, 1); + set_bit_field(&pckhdl_cfg, ETOP_TX_EN, 0); + set_bit_field(&pckhdl_cfg, BAT_EN, 0); + set_bit_field(&pckhdl_cfg, ECC_RX_EN, 1); + set_bit_field(&pckhdl_cfg, CRC_RX_EN, 1); + dsi_write(R_DSI_HOST_PCKHDL_CFG, pckhdl_cfg); + + dsi_set_bit(R_DSI_HOST_DPI_COLOR_CODING, DIP_COLOR_CODING, dsi_config->color_coding); + dsi_set_bit(R_DSI_HOST_DPI_COLOR_CODING, LOOSELY18_EN, dsi_config->color_type_18bit); +} + +static int dsi_write_gen_data(unsigned int data) +{ + if (dsi_wait_pld_w_not_full(500)) { + printf("pld_w_fifo full!\n"); + return -1; + } + + dsi_write(R_DSI_HOST_GEN_PLD_DATA, data); + + return 0; +} + +int dsi_write_short_packet(unsigned char vc, unsigned char packet_type, unsigned short cmd_data) +{ + if (dsi_wait_cmd_not_full(10*1000)) { + printf("cmd fifo full!\n"); + return -1; + } + + unsigned char data[2]; + data[0] = cmd_data; + data[1] = cmd_data >> 8; + + unsigned long gen_hdr = 0; + set_bit_field(&gen_hdr, GEN_DT, packet_type); + set_bit_field(&gen_hdr, GEN_VC, vc); + set_bit_field(&gen_hdr, GEN_WC_LSBYTE, data[0]); + set_bit_field(&gen_hdr, GEN_WC_MSBYTE, data[1]); + dsi_write(R_DSI_HOST_GEN_HDR, gen_hdr); + + return 0; + +} + +int dsi_write_long_packet(unsigned char vc, unsigned char packet_type, unsigned char *cmd_data, unsigned short word_count) +{ + int ret; + int i; + + unsigned int gen_pld_data = 0; + for (i = 0; i < word_count; i++) { + gen_pld_data |= cmd_data[i] << (i % 4) * 8; + if ((i + 1) % 4 == 0 && i != 0) { + ret = dsi_write_gen_data(gen_pld_data); + if (ret < 0) + return -1; + + gen_pld_data = 0; + } + } + + if (word_count % 4 != 0) { + ret = dsi_write_gen_data(gen_pld_data); + if (ret < 0) + return -1; + } + + ret = dsi_write_short_packet(vc, packet_type, word_count); + if (ret < 0) + return -1; + + + return 0; +} + +int dsi_read_packet(int bytes, unsigned char *rd_buf) +{ + int i; + int off = 0; + if (dsi_wait_rd_cmd_busy(10*1000)) { + printf("read cmd busy!\n"); + return -1; + } + + if (dsi_wait_rd_fifo_empty(10*1000)) { + printf("read fifo is empty!\n"); + return -1; + } + + for (i = 0; i < bytes; i++) { + rd_buf[i] = dsi_get_bit(R_DSI_HOST_GEN_PLD_DATA, off, off + 7); + off += 8; + + if ((i + 1) % 4 == 0 && i != 0) { + off = 0; + } + } + + return 0; +} + + +static void jz_dsi_dpi_config(struct video_config *video_config) +{ + unsigned int hs_timeout; + int counter; + + unsigned int temp; + + temp = video_config->byte_clock * 1000 / (video_config->pixel_clock); + dsi_write(R_DSI_HOST_VID_HBP_TIME, video_config->hbp * temp / 1000); + dsi_write(R_DSI_HOST_VID_HSA_TIME, video_config->hs * temp / 1000); + dsi_write(R_DSI_HOST_VID_HLINE_TIME, video_config->h_total_pixels * temp / 1000); + + dsi_write(R_DSI_HOST_VID_VBP_LINES, video_config->vbp); + dsi_write(R_DSI_HOST_VID_VFP_LINES, video_config->vfp); + dsi_write(R_DSI_HOST_VID_VSA_LINES, video_config->vs); + dsi_write(R_DSI_HOST_VID_VACTIVE_LINES, video_config->v_active_lines); + + unsigned long dpi_cfg_pol = dsi_read(R_DSI_HOST_DPI_CFG_POL); + set_bit_field(&dpi_cfg_pol, DATAEN_ACTIVE_LOW, !video_config->data_en_polarity); + set_bit_field(&dpi_cfg_pol, VSYNC_ACTIVE_LOW, 1); + set_bit_field(&dpi_cfg_pol, HSYNC_ACTIVE_LOW, 1); + dsi_write(R_DSI_HOST_DPI_CFG_POL, dpi_cfg_pol); + + //timeout ??? + hs_timeout = (video_config->h_total_pixels * video_config->v_active_lines) \ + + (2 * (video_config->bpp_info * 100 / 8) / 100); + + for (counter = 0x80; (counter < hs_timeout) && (counter > 2); counter--) { + if ((hs_timeout % counter) == 0) { + dsi_set_bit(R_DSI_HOST_CLKMGR_CFG, TO_CLK_DIV, counter); + dsi_set_bit(R_DSI_HOST_TO_CNT_CFG, HSTX_TO_CNT, (unsigned short)(hs_timeout / counter)); + dsi_set_bit(R_DSI_HOST_TO_CNT_CFG, LPRX_TO_CNT, (unsigned short)(hs_timeout / counter)); + break; + } + } + +} + + +int jz_dsi_video_init(struct video_config *video_config) +{ + //high speed + dsi_set_transfer_mode(0); + + //set video mode + dsi_set_video_mode(); + + unsigned long vid_mode_cfg = dsi_read(R_DSI_HOST_VID_MODE_CFG); + + set_bit_field(&vid_mode_cfg, VID_MODE_TYPE, video_config->video_mode); + set_bit_field(&vid_mode_cfg, LP_VSA_EN, 1); + set_bit_field(&vid_mode_cfg, LP_VBP_EN, 1); + set_bit_field(&vid_mode_cfg, LP_VFP_EN, 1); + set_bit_field(&vid_mode_cfg, LP_VACT_EN, 1); + set_bit_field(&vid_mode_cfg, LP_HBP_EN, 1); + set_bit_field(&vid_mode_cfg, LP_HFP_EN, 1); + + set_bit_field(&vid_mode_cfg, VPG_EN, 0); + set_bit_field(&vid_mode_cfg, VPG_MODE, 0); + set_bit_field(&vid_mode_cfg, VPG_ORIENTATION, 0); + + dsi_write(R_DSI_HOST_VID_MODE_CFG, vid_mode_cfg); + + //dpi config + jz_dsi_dpi_config(video_config); + + + //set R_DSI_HOST_CLKMGR_CFG tx_esc_clk_division???? + dsi_set_bit(R_DSI_HOST_CLKMGR_CFG, TX_ESC_CLK_DIV, 7); + + + //pack_size chun_no null_size???? + dsi_set_bit(R_DSI_HOST_VID_NUM_CHUNKS, VID_NUM_CHUNKS, video_config->chunk); + dsi_set_bit(R_DSI_HOST_VID_PKT_SIZE, VID_PKT_SIZE, video_config->video_size); + dsi_set_bit(R_DSI_HOST_VID_NULL_SIZE, VID_NULL_SIZE, video_config->null_size); + + //set dpi channel + dsi_set_bit(R_DSI_HOST_DPI_VCID, DPI_VCID, video_config->virtual_channel); + + //enable hs clk + dsi_set_bit(R_DSI_HOST_LPCLK_CTRL, PHY_TXREQUESTCLKHS, 1); + + return 0; + +} + +/********************************/ + +/********************************/ +void dump_dsi_reg(void) +{ + printf("===========>dump dsi reg\n"); + printf("VERSION------------:%08x\n", dsi_read(R_DSI_HOST_VERSION)); + printf("PWR_UP:------------:%08x\n", dsi_read(R_DSI_HOST_PWR_UP)); + printf("CLKMGR_CFG---------:%08x\n", dsi_read(R_DSI_HOST_CLKMGR_CFG)); + printf("DPI_VCID-----------:%08x\n", dsi_read(R_DSI_HOST_DPI_VCID)); + printf("DPI_COLOR_CODING---:%08x\n", dsi_read(R_DSI_HOST_DPI_COLOR_CODING)); + printf("DPI_CFG_POL--------:%08x\n", dsi_read(R_DSI_HOST_DPI_CFG_POL)); + printf("DPI_LP_CMD_TIM-----:%08x\n", dsi_read(R_DSI_HOST_DPI_LP_CMD_TIM)); + printf("DBI_VCID-----------:%08x\n", dsi_read(R_DSI_HOST_DBI_VCID)); + printf("DBI_CFG------------:%08x\n", dsi_read(R_DSI_HOST_DBI_CFG)); + printf("DBI_PARTITIONING_EN:%08x\n", dsi_read(R_DSI_HOST_DBI_PARTITIONING_EN)); + printf("DBI_CMDSIZE--------:%08x\n", dsi_read(R_DSI_HOST_DBI_CMDSIZE)); + printf("PCKHDL_CFG---------:%08x\n", dsi_read(R_DSI_HOST_PCKHDL_CFG)); + printf("GEN_VCID-----------:%08x\n", dsi_read(R_DSI_HOST_GEN_VCID)); + printf("MODE_CFG-----------:%08x\n", dsi_read(R_DSI_HOST_MODE_CFG)); + printf("VID_MODE_CFG-------:%08x\n", dsi_read(R_DSI_HOST_VID_MODE_CFG)); + printf("VID_PKT_SIZE-------:%08x\n", dsi_read(R_DSI_HOST_VID_PKT_SIZE)); + printf("VID_NUM_CHUNKS-----:%08x\n", dsi_read(R_DSI_HOST_VID_NUM_CHUNKS)); + printf("VID_NULL_SIZE------:%08x\n", dsi_read(R_DSI_HOST_VID_NULL_SIZE)); + printf("VID_HSA_TIME-------:%08x\n", dsi_read(R_DSI_HOST_VID_HSA_TIME)); + printf("VID_HBP_TIME-------:%08x\n", dsi_read(R_DSI_HOST_VID_HBP_TIME)); + printf("VID_HLINE_TIME-----:%08x\n", dsi_read(R_DSI_HOST_VID_HLINE_TIME)); + printf("VID_VSA_LINES------:%08x\n", dsi_read(R_DSI_HOST_VID_VSA_LINES)); + printf("VID_VBP_LINES------:%08x\n", dsi_read(R_DSI_HOST_VID_VBP_LINES)); + printf("VID_VFP_LINES------:%08x\n", dsi_read(R_DSI_HOST_VID_VFP_LINES)); + printf("VID_VACTIVE_LINES--:%08x\n", dsi_read(R_DSI_HOST_VID_VACTIVE_LINES)); + printf("EDPI_CMD_SIZE------:%08x\n", dsi_read(R_DSI_HOST_EDPI_CMD_SIZE)); + printf("CMD_MODE_CFG-------:%08x\n", dsi_read(R_DSI_HOST_CMD_MODE_CFG)); + printf("GEN_HDR------------:%08x\n", dsi_read(R_DSI_HOST_GEN_HDR)); + printf("GEN_PLD_DATA-------:%08x\n", dsi_read(R_DSI_HOST_GEN_PLD_DATA)); + printf("CMD_PKT_STATUS-----:%08x\n", dsi_read(R_DSI_HOST_CMD_PKT_STATUS)); + printf("TO_CNT_CFG---------:%08x\n", dsi_read(R_DSI_HOST_TO_CNT_CFG)); + printf("HS_RD_TO_CNT-------:%08x\n", dsi_read(R_DSI_HOST_HS_RD_TO_CNT)); + printf("LP_RD_TO_CNT-------:%08x\n", dsi_read(R_DSI_HOST_LP_RD_TO_CNT)); + printf("HS_WR_TO_CNT-------:%08x\n", dsi_read(R_DSI_HOST_HS_WR_TO_CNT)); + printf("LP_WR_TO_CNT_CFG---:%08x\n", dsi_read(R_DSI_HOST_LP_WR_TO_CNT)); + printf("BTA_TO_CNT---------:%08x\n", dsi_read(R_DSI_HOST_BTA_TO_CNT)); + printf("SDF_3D-------------:%08x\n", dsi_read(R_DSI_HOST_SDF_3D)); + printf("LPCLK_CTRL---------:%08x\n", dsi_read(R_DSI_HOST_LPCLK_CTRL)); + printf("PHY_TMR_LPCLK_CFG--:%08x\n", dsi_read(R_DSI_HOST_PHY_TMR_LPCLK_CFG)); + printf("PHY_TMR_CFG--------:%08x\n", dsi_read(R_DSI_HOST_PHY_TMR_CFG)); + printf("PHY_RSTZ-----------:%08x\n", dsi_read(R_DSI_HOST_PHY_RSTZ)); + printf("PHY_IF_CFG---------:%08x\n", dsi_read(R_DSI_HOST_PHY_IF_CFG)); + printf("PHY_ULPS_CTRL------:%08x\n", dsi_read(R_DSI_HOST_PHY_ULPS_CTRL)); + printf("PHY_TX_TRIGGERS----:%08x\n", dsi_read(R_DSI_HOST_PHY_TX_TRIGGERS)); + printf("PHY_STATUS---------:%08x\n", dsi_read(R_DSI_HOST_PHY_STATUS)); + printf("PHY_TST_CTRL0------:%08x\n", dsi_read(R_DSI_HOST_PHY_TST_CTRL0)); + printf("PHY_TST_CTRL1------:%08x\n", dsi_read(R_DSI_HOST_PHY_TST_CTRL1)); + printf("INT_ST0------------:%08x\n", dsi_read(R_DSI_HOST_INT_ST0)); + printf("INT_ST1------------:%08x\n", dsi_read(R_DSI_HOST_INT_ST1)); + printf("INT_MSK0-----------:%08x\n", dsi_read(R_DSI_HOST_INT_MSK0)); + printf("INT_MSK1-----------:%08x\n", dsi_read(R_DSI_HOST_INT_MSK1)); + printf("INT_FORCE0---------:%08x\n", dsi_read(R_DSI_HOST_INT_FORCE0)); + printf("INT_FORCE1---------:%08x\n", dsi_read(R_DSI_HOST_INT_FORCE1)); + printf("VID_SHADOW_CTRL----:%08x\n", dsi_read(R_DSI_HOST_VID_SHADOW_CTRL)); + printf("DPI_VCID_ACT-------:%08x\n", dsi_read(R_DSI_HOST_DPI_VCID_ACT)); + printf("DPI_COLOR_CODING_AC:%08x\n", dsi_read(R_DSI_HOST_DPI_COLOR_CODING_ACT)); + printf("DPI_LP_CMD_TIM_ACT-:%08x\n", dsi_read(R_DSI_HOST_DPI_LP_CMD_TIM_ACT)); + printf("VID_MODE_CFG_ACT---:%08x\n", dsi_read(R_DSI_HOST_VID_MODE_CFG_ACT)); + printf("VID_PKT_SIZE_ACT---:%08x\n", dsi_read(R_DSI_HOST_VID_PKT_SIZE_ACT)); + printf("VID_NUM_CHUNKS_ACT-:%08x\n", dsi_read(R_DSI_HOST_VID_NUM_CHUNKS_ACT)); + printf("VID_HSA_TIME_ACT---:%08x\n", dsi_read(R_DSI_HOST_VID_HSA_TIME_ACT)); + printf("VID_HBP_TIME_ACT---:%08x\n", dsi_read(R_DSI_HOST_VID_HBP_TIME_ACT)); + printf("VID_HLINE_TIME_ACT-:%08x\n", dsi_read(R_DSI_HOST_VID_HLINE_TIME_ACT)); + printf("VID_VSA_LINES_ACT--:%08x\n", dsi_read(R_DSI_HOST_VID_VSA_LINES_ACT)); + printf("VID_VBP_LINES_ACT--:%08x\n", dsi_read(R_DSI_HOST_VID_VBP_LINES_ACT)); + printf("VID_VFP_LINES_ACT--:%08x\n", dsi_read(R_DSI_HOST_VID_VFP_LINES_ACT)); + printf("VID_VACTIVE_LINES_ACT:%08x\n", dsi_read(R_DSI_HOST_VID_VACTIVE_LINES_ACT)); + printf("SDF_3D_ACT---------:%08x\n", dsi_read(R_DSI_HOST_SDF_3D_ACT)); + printf("===================================================\n"); + printf("PLL_CLK_SEL_R------:%08x\n", dsi_read_phy_clk()); +} + + -- Gitee