From 101a5cc95faa0002004e76880b2efce373297b93 Mon Sep 17 00:00:00 2001 From: anan_bj Date: Thu, 27 Apr 2023 15:03:04 +0800 Subject: [PATCH] [Add] add riscv systick & irq --- cpu/core-riscv/include/riscv_irq.h | 10 ++++ cpu/core-riscv/include/riscv_sys.h | 9 ++++ cpu/core-riscv/src/riscv_irq.c | 82 ++++++++++++++++++++++++++++++ cpu/core-riscv/src/riscv_sys.c | 48 +++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 cpu/core-riscv/include/riscv_irq.h create mode 100644 cpu/core-riscv/include/riscv_sys.h create mode 100644 cpu/core-riscv/src/riscv_irq.c create mode 100644 cpu/core-riscv/src/riscv_sys.c diff --git a/cpu/core-riscv/include/riscv_irq.h b/cpu/core-riscv/include/riscv_irq.h new file mode 100644 index 00000000..aa9ac91a --- /dev/null +++ b/cpu/core-riscv/include/riscv_irq.h @@ -0,0 +1,10 @@ +#ifndef __RISCV_MAILBOX_H +#define __RISCV_MAILBOX_H + +#include + +void ingenic_mbx_sendmsg(uint32_t data); +uint32_t ingenic_mbx_readmsg(void); +void enable_irq(void); + +#endif diff --git a/cpu/core-riscv/include/riscv_sys.h b/cpu/core-riscv/include/riscv_sys.h new file mode 100644 index 00000000..20ef3f8b --- /dev/null +++ b/cpu/core-riscv/include/riscv_sys.h @@ -0,0 +1,9 @@ +#ifndef __RISKV_SYSY_H +#define __RISKV_SYSY_H + +void init_systick(void); +void systick_delay_ms(unsigned int ms); +void riscv_sys_init(void); +void riscv_sys_deinit(void); + +#endif diff --git a/cpu/core-riscv/src/riscv_irq.c b/cpu/core-riscv/src/riscv_irq.c new file mode 100644 index 00000000..783bdd44 --- /dev/null +++ b/cpu/core-riscv/src/riscv_irq.c @@ -0,0 +1,82 @@ +#include +#include "riscv_irq.h" + +#ifdef RPMSG +#include "rpmsg_platform.h" +#endif + + +void ingenic_mbx_sendmsg(uint32_t data) +{ + *CCU_TO_HOST = data; +} + +uint32_t ingenic_mbx_readmsg(void) +{ + return *CCU_FROM_HOST; +} + +void soft_handler(void) { + //prom_printk("soft_handler\n"); + if(*CCU_SOFT_PEND & 0x1){ + *CCU_SOFT_PEND = 0x0; + prom_printk("recevied soft irq\n"); + } + +} + +void mailbox_handler(void) { + uint32_t msg = *CCU_FROM_HOST; + *CCU_FROM_HOST = 0x0; +#ifdef RPMSG + rpmsg_handler(msg); +#endif +} + +void ext_handler(void) { + unsigned int pending_l = 0; + unsigned int pending_h = 0; + //prom_printk("ext_handler\n"); + //prom_printk("PEND_L:%x\n", *CCU_INTC_PEND_L); + //prom_printk("PEND_H:%x\n", *CCU_INTC_PEND_H); + *CCU_INTC_PEND_H = 0; + *CCU_INTC_PEND_L = 0; +} + +void ost_handler(void) { + //prom_printk("ost_handler\n"); + *CCU_TIME_CMP_H = 0xfffffff; + *CCU_TIME_CMP_L = 0xfffffff; + *CCU_CCSR = *CCU_CCSR & ~(1 << 5); // Disable timer +} + +void exc_handler(void) { +// prom_printk("exc_handler\n"); + uint32_t cause, mip; + CSR_READ(MCAUSE, cause); + if(cause >> 31){ + CSR_READ(MIP, mip); +// prom_printk("mip = %x\n", mip); + if (mip & MIP_MEIP) ext_handler(); + else if (mip & MIP_MSIP) soft_handler(); + else if (mip & MIP_MTIP) ost_handler(); + else if (mip & MIP_MFIP_0) mailbox_handler(); + else{ + prom_printk("64 error\n"); + } + }else{ + //prom_printk("mcause = %x\n", cause); + CSR_READ(MIP, mip); + //prom_printk("mip = %x\n", mip); + } +} + +void enable_irq(){ + CSR_SET(MIE, MIE_MSIE); + CSR_SET(MIE, MIE_MTIE); + CSR_SET(MIE, MIE_MEIE); + CSR_SET(MIE, MIE_MFIE_0); + CSR_SET(MSTATUS, MSTATUS_MIE); + +} + diff --git a/cpu/core-riscv/src/riscv_sys.c b/cpu/core-riscv/src/riscv_sys.c new file mode 100644 index 00000000..1266ed1d --- /dev/null +++ b/cpu/core-riscv/src/riscv_sys.c @@ -0,0 +1,48 @@ +#include +#include "riscv_sys.h" + +void init_systick() +{ + *CCU_CCSR = *CCU_CCSR & ~(1 << 5); // Disable timer + *CCU_TIME_L = 0; + *CCU_TIME_H = 0; + *CCU_TIME_CMP_H = 0x0fffffff; + *CCU_TIME_CMP_L = 0x0fffffff; + +} + +void systick_delay_ms(unsigned int ms) +{ + unsigned int time_count=0; + *CCU_TIME_L = 0; + *CCU_TIME_H = 0; + *CCU_TIME_CMP_H = 0x0fffffff; + *CCU_TIME_CMP_L = 0x0fffffff; + + *CCU_CCSR = *CCU_CCSR | (1 << 5); //Enable timer + + while(time_count