# verilog-utils

**Repository Path**: joy20182018/verilog-utils

## Basic Information

- **Project Name**: verilog-utils
- **Description**: No description available
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-05-20
- **Last Updated**: 2021-05-23

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# verilog-utils README

verilog utility functions.

## Features

There is only one feature now.
- Make instatiation code
- Command Name : "Verilog Utils - Instation"

## Examples
![instantiate 1](images/instantiate.gif)

## TODO
- Verilog snippet
- instantiate Align