# uvm_debug

**Repository Path**: justin371/uvm_debug

## Basic Information

- **Project Name**: uvm_debug
- **Description**: UVM interactive debug library
- **Primary Language**: Unknown
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2020-09-08
- **Last Updated**: 2024-05-31

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

#UVM interactive debug library (uvm_debug)
**Horace Chan (horace.chan@microsemi.com)**

uvm_debug library is a free, open-source library writter in SystemVerilog and C (SV-DPI).  uvm_debug is provided under MIT license and it available on GitHub.

##Documents:
The PDF of the DVCON2017 titled "UVM Interactive Debug Library: Shortening the Debug Turnaround Time" is availabled at `doc/dvcon2017_uvm_debug_lib_final.pdf`

##Installation:
1. `git clone https://github.com/uvmdebug/uvm_debug`
2. Compile the .sv and .c files with the testbench
3. Instantiate the uvm_debug_module as a top level module

##Testbench Setup:
- See Section B of the PDF 

##Demo (ncsim only):
Run `>./demo.sh`