# simt

**Repository Path**: khtsoi/simt

## Basic Information

- **Project Name**: simt
- **Description**: Single Instruction Multiple Threads
- **Primary Language**: Verilog
- **License**: MIT
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2023-11-20
- **Last Updated**: 2023-12-02

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Single Instruction Multiple Threads

Implementation should be in Verilog HDL format and the source code should be verified by the `iverilog` tool from the [Icarus project](https://bleyer.org/icarus/).

Each module has its own directory in the SIMT repository following a common directory structure.

| directory or file   | contents
| ------------------  | -------------------------------------------------------
| `./`                | the current version directory
| `README.txt`        | the description of the module's features and releases
| `doc/`              | (optional) all related document
| `hdl/`              | RTL files for synthesis
| `module.f`          | the list of synthesis design files
| `tb/`               | (optional) testbench and test cases for direct test