# axi_spi_master

**Repository Path**: litial/axi_spi_master

## Basic Information

- **Project Name**: axi_spi_master
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2022-10-21
- **Last Updated**: 2022-10-21

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# AXI SPI Master

This is an implementation of an SPI master that is controlled via an AXI bus.
It has FIFOs for transmitting and receiving data.  It supports both the normal
SPI mode and QPI mode with 4 data lines.
This IP was written for the use in the [PULP platform](http://pulp.ethz.ch/).