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此仓库是为了提升国内下载速度的镜像仓库,每日同步一次。 原始仓库: https://github.com/lowrisc/lowrisc-chip
lowRISC 目的是开发一个完全开放的硬件平台,从处理器到开发版 spread retract

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# See LICENSE for license details.
# check RISCV environment variable
ifndef RISCV
$(error Please set environment variable RISCV. Please take a look at README)
endif
MODEL := Top
PROJECT := lowrisc_chip
CXX := g++
CXXFLAGS := -O1
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar
SHELL := /bin/bash
CHISEL_ARGS := $(PROJECT) $(MODEL) $(PROJECT) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
# specify source files
src_path = src/main/scala
default_submodules = . junctions uncore hardfloat rocket
chisel_srcs := $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules)))
osd_base = $(base_dir)/opensocdebug/hardware
include $(osd_base)/Makefrag
chisel_srcs += $(osd_srcs)
# translate trace files generated by C++/Verilog simulation
disasm := >
which_disasm := $(shell which spike-dasm 2> /dev/null)
ifneq ($(which_disasm),)
disasm := | $(which_disasm) $(DISASM_EXTENSION) >
endif
# define time-out for different types of simulation
timeout_cycles = 10000000
long_timeout_cycles = 50000000
linux_timeout_cycles = 5000000000
# emacs local variable
# Local Variables:
# mode: makefile
# End:

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