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此仓库是为了提升国内下载速度的镜像仓库,每日同步一次。 原始仓库: https://github.com/riscv/riscv-isa-sim
Spike RISC-V ISA模拟器,它实现了一个或多个RISC-V harts的功能模型 spread retract

https://www.oschina.net/p/riscv-isa-sim

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Version 1.0.1-dev

  • Preliminary support for a subset of the Vector Extension, v0.7.1.
  • Support S-mode vectored interrupts (i.e. stvec[0] is now writable).
  • Added support for dynamic linking of libraries containing MMIO devices.
  • Added --priv flag to control which privilege modes are available.
  • When the commit log is enabled at configure time (--enable-commitlog), it must also be enabled at runtime with the --log-commits option.
  • Several debug-related additions and changes:
    • Added hasel debug feature.
    • Added --dm-no-abstract-csr command-line option.
    • Added --dm-no-halt-groups command line option.
    • Renamed --progsize to --dm-progsize.
    • Renamed --debug-sba to --dm-sba.
    • Renamed --debug-auth to --dm-auth.
    • Renamed --abstract-rti to --dm-abstract-rti.
    • Renamed --without-hasel to --dm-no-hasel.

Version 1.0.0 (2019-03-30)

  • First versioned release.

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