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码云极速下载 / riscv-isa-simC/C++

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Andrew Waterman 77b98bf v[f]merge: allow v0 overlap if LMUL = 1
Megan Wachs 6b90a45 FESVR: Can't read a DM register when DMACTIVE=0
kritik bhimani 90a04da fesvr: decrease DTM idle cycles
Udit Khanna 70063de MSTATUS.SUM hardwired to 0 if no S-Mode
Clifford Wolf 5b042d7 [riscv-bitmanip] Add sh[123]add[u.w] instruction
Albert Ou cb5cc42 rvv: Fix INT_ROUNDING compliance
Andrew Waterman 88a8528 Set vtype.vill correctly; also reset it to true
Andrew Waterman f49618c Add fesvr; only globally install fesvr headers/libs
Tim Newsome 9a2904a Clean up/optimize Debug ROM.
rvv
Colin Schmidt e9ebc5a WIP: scale memory immeadiates and add reamining variants
Megan Wachs cc6a9c9 Debug ROM: Adjust debug ROM to have fewer icache flushes
Andrew Waterman 74554e7 Implement cycleh/instreth CSRs for RV32
Tim Newsome 8b1cca8 Passes smoke tests with --progsize=0
Tim Newsome 2ccca5c Passes smoke tests with --progsize=0
Tim Newsome 1a90465 Reset to "success" instead of "error."
Tim Newsome 290115a `make clean && make` works again in debug_rom
Andrew Waterman 68c721b minNum -> minimumNumber
Andrew Waterman f222966 WIP on FP encoding
Andrew Waterman 6bb4f12 Only allow SIP.SSIP to be toggled if the interrupt is delegated
Tim Newsome 73be8ba Remove generic debug tests.
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