# benchmark

**Repository Path**: nlwmode_personal/benchmark

## Basic Information

- **Project Name**: benchmark
- **Description**: collections for some public benchmarks.
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2021-11-29
- **Last Updated**: 2023-09-30

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

Here are benchmarks from internet.  
[IWLS_bechmarks_2005_V_1.0](IWLS_bechmarks_2005_V_1.0): https://iwls.org/iwls2005/benchmarks.html  
[MCNC91](MCNC91): https://github.com/growly/fpga_benchmarks/tree/master/mcnc91  
[LGSynth91](LGSynth91): https://people.engr.ncsu.edu/brglez/CBL/benchmarks/LGSynth91/

[verilog](verilog): these are verilog files converted from blif files above, by yosys command:
>yosys -p "read_blif {bfile}; write_verilog {vfile}"

[combinational](combinational): these are combinational verilog/aig files extracted from files in [verilog](verilog).