From 567decae91e15fe0a56c33099f2b4d731ef31d6b Mon Sep 17 00:00:00 2001 From: luoyuncong Date: Thu, 28 Mar 2024 11:54:10 +0800 Subject: [PATCH] rk3588: add rockchip hal driver. add driver files include clock, pinctrl, gpio, uart. Signed-off-by: luoyuncong luoyuncong@ncti-gba.cn --- demos/rk3588/CMakeLists.txt | 7 +- demos/rk3588/bsp/CMakeLists.txt | 2 + demos/rk3588/bsp/hal/CMakeLists.txt | 10 + demos/rk3588/bsp/hal/cmsis_compiler.h | 213 + demos/rk3588/bsp/hal/cmsis_cp15.h | 515 + demos/rk3588/bsp/hal/cmsis_gcc.h | 913 + demos/rk3588/bsp/hal/core_ca.h | 2614 +++ demos/rk3588/bsp/hal/hal_base.c | 29 + demos/rk3588/bsp/hal/hal_base.h | 41 + demos/rk3588/bsp/hal/hal_canfd.c | 484 + demos/rk3588/bsp/hal/hal_canfd.h | 106 + demos/rk3588/bsp/hal/hal_conf.h | 161 + demos/rk3588/bsp/hal/hal_cru.c | 1528 ++ demos/rk3588/bsp/hal/hal_cru.h | 452 + demos/rk3588/bsp/hal/hal_cru_rk3588.c | 1422 ++ demos/rk3588/bsp/hal/hal_debug.h | 81 + demos/rk3588/bsp/hal/hal_def.h | 206 + demos/rk3588/bsp/hal/hal_driver.h | 277 + demos/rk3588/bsp/hal/hal_gpio.c | 577 + demos/rk3588/bsp/hal/hal_gpio.h | 170 + demos/rk3588/bsp/hal/hal_i2c.c | 926 + demos/rk3588/bsp/hal/hal_i2c.h | 156 + demos/rk3588/bsp/hal/hal_list.h | 181 + demos/rk3588/bsp/hal/hal_pinctrl.c | 754 + demos/rk3588/bsp/hal/hal_pinctrl.h | 733 + demos/rk3588/bsp/hal/hal_spi.c | 837 + demos/rk3588/bsp/hal/hal_spi.h | 173 + demos/rk3588/bsp/hal/hal_timer.c | 266 + demos/rk3588/bsp/hal/hal_timer.h | 61 + demos/rk3588/bsp/hal/hal_uart.c | 501 + demos/rk3588/bsp/hal/hal_uart.h | 277 + demos/rk3588/bsp/hal/rk3588.h | 21736 ++++++++++++++++++++++++ demos/rk3588/bsp/hal/soc.h | 732 + demos/rk3588/bsp/print.c | 8 +- 34 files changed, 37141 insertions(+), 8 deletions(-) create mode 100755 demos/rk3588/bsp/hal/CMakeLists.txt create mode 100755 demos/rk3588/bsp/hal/cmsis_compiler.h create mode 100755 demos/rk3588/bsp/hal/cmsis_cp15.h create mode 100755 demos/rk3588/bsp/hal/cmsis_gcc.h create mode 100755 demos/rk3588/bsp/hal/core_ca.h create mode 100755 demos/rk3588/bsp/hal/hal_base.c create mode 100755 demos/rk3588/bsp/hal/hal_base.h create mode 100755 demos/rk3588/bsp/hal/hal_canfd.c create mode 100755 demos/rk3588/bsp/hal/hal_canfd.h create mode 100755 demos/rk3588/bsp/hal/hal_conf.h create mode 100755 demos/rk3588/bsp/hal/hal_cru.c create mode 100755 demos/rk3588/bsp/hal/hal_cru.h create mode 100755 demos/rk3588/bsp/hal/hal_cru_rk3588.c create mode 100755 demos/rk3588/bsp/hal/hal_debug.h create mode 100755 demos/rk3588/bsp/hal/hal_def.h create mode 100755 demos/rk3588/bsp/hal/hal_driver.h create mode 100755 demos/rk3588/bsp/hal/hal_gpio.c create mode 100755 demos/rk3588/bsp/hal/hal_gpio.h create mode 100755 demos/rk3588/bsp/hal/hal_i2c.c create mode 100755 demos/rk3588/bsp/hal/hal_i2c.h create mode 100755 demos/rk3588/bsp/hal/hal_list.h create mode 100755 demos/rk3588/bsp/hal/hal_pinctrl.c create mode 100755 demos/rk3588/bsp/hal/hal_pinctrl.h create mode 100755 demos/rk3588/bsp/hal/hal_spi.c create mode 100755 demos/rk3588/bsp/hal/hal_spi.h create mode 100755 demos/rk3588/bsp/hal/hal_timer.c create mode 100755 demos/rk3588/bsp/hal/hal_timer.h create mode 100755 demos/rk3588/bsp/hal/hal_uart.c create mode 100755 demos/rk3588/bsp/hal/hal_uart.h create mode 100755 demos/rk3588/bsp/hal/rk3588.h create mode 100755 demos/rk3588/bsp/hal/soc.h diff --git a/demos/rk3588/CMakeLists.txt b/demos/rk3588/CMakeLists.txt index f14d3dae..fc3f9de6 100755 --- a/demos/rk3588/CMakeLists.txt +++ b/demos/rk3588/CMakeLists.txt @@ -24,6 +24,7 @@ include_directories( ${CMAKE_CURRENT_SOURCE_DIR}/include ${CMAKE_CURRENT_SOURCE_DIR}/config ${CMAKE_CURRENT_SOURCE_DIR}/bsp + ${CMAKE_CURRENT_SOURCE_DIR}/bsp/hal ${CMAKE_CURRENT_SOURCE_DIR}/bsp/rk3588 ${CMAKE_CURRENT_SOURCE_DIR}/apps/openamp ${HOME_PATH}/output/libc/include @@ -52,7 +53,7 @@ if (${APP} STREQUAL "UniPorton_test_posix_time_interface" OR ${APP} STREQUAL "UniPorton_test_posix_signal_interface") add_subdirectory(${HOME_PATH}/testsuites/posixtestsuite/conformance tmp) target_compile_options(openamp PUBLIC -DTESTSUITE_CASE) - list(APPEND OBJS $ $ $ $) + list(APPEND OBJS $ $ $ $ $) add_executable(${APP} ${OBJS}) elseif(${APP} STREQUAL "task-switch" OR ${APP} STREQUAL "task-preempt" OR @@ -62,9 +63,9 @@ elseif(${APP} STREQUAL "task-switch" OR ${APP} STREQUAL "message-latency") add_subdirectory(${HOME_PATH}/testsuites/rhealstone tmp) target_compile_options(openamp PUBLIC -DTESTSUITE_CASE) - list(APPEND OBJS $ $ $ $) + list(APPEND OBJS $ $ $ $ $) add_executable(${APP} ${OBJS}) else() - list(APPEND OBJS $ $ $) + list(APPEND OBJS $ $ $ $) add_executable(${APP} ${OBJS}) endif() diff --git a/demos/rk3588/bsp/CMakeLists.txt b/demos/rk3588/bsp/CMakeLists.txt index 159d4f9b..6dd7124f 100755 --- a/demos/rk3588/bsp/CMakeLists.txt +++ b/demos/rk3588/bsp/CMakeLists.txt @@ -5,3 +5,5 @@ if (${CONFIG_OS_GDB_STUB}) endif() add_library(bsp OBJECT ${SRCS}) + +add_subdirectory(hal) diff --git a/demos/rk3588/bsp/hal/CMakeLists.txt b/demos/rk3588/bsp/hal/CMakeLists.txt new file mode 100755 index 00000000..289298ff --- /dev/null +++ b/demos/rk3588/bsp/hal/CMakeLists.txt @@ -0,0 +1,10 @@ +set(SRCS + hal_base.c + hal_cru.c + hal_cru_rk3588.c + hal_gpio.c + hal_pinctrl.c + hal_uart.c + ) + +add_library(hal OBJECT ${SRCS}) diff --git a/demos/rk3588/bsp/hal/cmsis_compiler.h b/demos/rk3588/bsp/hal/cmsis_compiler.h new file mode 100755 index 00000000..dfd07a26 --- /dev/null +++ b/demos/rk3588/bsp/hal/cmsis_compiler.h @@ -0,0 +1,213 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/demos/rk3588/bsp/hal/cmsis_cp15.h b/demos/rk3588/bsp/hal/cmsis_cp15.h new file mode 100755 index 00000000..d68266bb --- /dev/null +++ b/demos/rk3588/bsp/hal/cmsis_cp15.h @@ -0,0 +1,515 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; +// __get_CP(15, 0, result, 0, 0, 5); + __ASM volatile("MRS %0, MPIDR_EL1" : "=r"(result)::"memory", "cc"); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/demos/rk3588/bsp/hal/cmsis_gcc.h b/demos/rk3588/bsp/hal/cmsis_gcc.h new file mode 100755 index 00000000..23d61205 --- /dev/null +++ b/demos/rk3588/bsp/hal/cmsis_gcc.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.3.0 + * @date 17. December 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/demos/rk3588/bsp/hal/core_ca.h b/demos/rk3588/bsp/hal/core_ca.h new file mode 100755 index 00000000..b698fda1 --- /dev/null +++ b/demos/rk3588/bsp/hal/core_ca.h @@ -0,0 +1,2614 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.3 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((uint32_t)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((uint32_t)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demos/rk3588/bsp/hal/hal_base.c b/demos/rk3588/bsp/hal/hal_base.c new file mode 100755 index 00000000..7c72b5b6 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_base.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_CRU_MODULE_ENABLED) +static struct CRU_BANK_INFO cruBanks[] = { + CRU_BANK_CFG_FLAGS(CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(PHPTOPCRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(SECURECRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(SBUSCRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(PMU1SCRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(PMU1CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(DDR0CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(DDR1CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(DDR2CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(DDR3CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(BIGCORE0CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(BIGCORE1CRU_BASE, 0x300, 0x800, 0xa00), + CRU_BANK_CFG_FLAGS(DSUCRU_BASE, 0x300, 0x800, 0xa00), +}; + +const struct HAL_CRU_DEV g_cruDev = { + .banks = cruBanks, + .banksNum = HAL_ARRAY_SIZE(cruBanks), +}; +#endif diff --git a/demos/rk3588/bsp/hal/hal_base.h b/demos/rk3588/bsp/hal/hal_base.h new file mode 100755 index 00000000..78260854 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_base.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_BASE + * @{ + */ + +#ifndef _HAL_BASE_H_ +#define _HAL_BASE_H_ + +#include "hal_conf.h" +#include "hal_driver.h" +#include "hal_debug.h" +#include "prt_clk.h" + +static inline HAL_Status HAL_DelayMs(uint32_t ms) +{ + PRT_ClkDelayMs(ms); + return HAL_OK; +} + +static inline HAL_Status HAL_DelayUs(uint32_t us) +{ + PRT_ClkDelayUs(us); + return HAL_OK; +} + +static inline HAL_Status HAL_CPUDelayUs(uint32_t us) +{ + PRT_ClkDelayUs(us); + return HAL_OK; +} + +#endif + diff --git a/demos/rk3588/bsp/hal/hal_canfd.c b/demos/rk3588/bsp/hal/hal_canfd.c new file mode 100755 index 00000000..e10765e6 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_canfd.c @@ -0,0 +1,484 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_CANFD_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CANFD + * @{ + */ + +/** @defgroup CANFD_How_To_Use How To Use + * @{ + + The CANFD driver can be used as follows: + + - Init: set work mode: HAL_CANFD_Init() + + - Start: start can bus: HAL_CANFD_Start() + + - Stop: stop can bus: HAL_CANFD_Stop() + + - Tx: HAL_CANFD_Transmit() + + - Rx: HAL_CANFD_Receive() + + @} */ + +/** @defgroup CANFD_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ +/********************* Private Variable Definition ***************************/ + +static const uint8_t dlc2len[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + +static const uint8_t len2dlc[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, /* 0 - 8 */ + 9, 9, 9, 9, /* 9 - 12 */ + 10, 10, 10, 10, /* 13 - 16 */ + 11, 11, 11, 11, /* 17 - 20 */ + 12, 12, 12, 12, /* 21 - 24 */ + 13, 13, 13, 13, 13, 13, 13, 13, /* 25 - 32 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* 33 - 40 */ + 14, 14, 14, 14, 14, 14, 14, 14, /* 41 - 48 */ + 15, 15, 15, 15, 15, 15, 15, 15, /* 49 - 56 */ + 15, 15, 15, 15, 15, 15, 15, 15}; /* 57 - 64 */ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Get data length from can_dlc with sanitized can_dlc. + * @param dlc: can_dlc + * @return length. + */ +static uint8_t CANFD_Dlc2Len(uint8_t dlc) +{ + return dlc2len[dlc & 0x0F]; +} + +/** + * @brief Map the sanitized data length to an appropriate data length code. + * @param len: can length + * @return dlc. + */ +static uint8_t CANFD_Len2Dlc(uint8_t len) +{ + if (len > 64) + { + return 0xF; + } + + return len2dlc[len]; +} + +/** + * @brief Set can to reset mode. + * @param pReg: can base + * @return HAL_OK. + */ +static HAL_Status CANFD_SetResetMode(struct CAN_REG *pReg) +{ + pReg->MODE = 0; + WRITE_REG(pReg->INT_MASK0, 0xffff); + + return HAL_OK; +} + +/** + * @brief Set can to normal mode. + * @param pReg: can base + * @return HAL_OK. + */ +static HAL_Status CANFD_SetNormalMode(struct CAN_REG *pReg) +{ + SET_BIT(pReg->MODE, CAN_MODE_WORK_MODE_MASK); + + return HAL_OK; +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CANFD_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief CANFD get normal bps. + * @param pReg: can base + * @param bps: can BaudRate + * @return HAL_OK. + * How to calculate the can bit rate: + * BaudRate= clk_can/(2*(brq+1)/(1+(tseg1+1)+(tseg2+1))) + * TDC = 0 + * For example(clk_can=200M): + * CLK_CAN BPS BRQ TSEG1 TSEG2 TDC + * 200M 1M 4 13 4 0 + * 200M 800K 4 18 4 0 + * 200M 500K 4 33 4 0 + * 200M 250K 4 68 9 0 + * 200M 200K 9 43 4 0 + * 200M 125K 9 68 9 0 + * 200M 100K 24 33 4 0 + * 200M 50K 24 68 9 0 + */ +HAL_Status HAL_CANFD_SetBps(struct CAN_REG *pReg, eCANFD_Bps bps) +{ + uint32_t sjw, brq, tseg1, tseg2; + + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + + switch (bps) + { + case CANFD_BPS_1MBAUD: + brq = 4; + tseg1 = 13; + tseg2 = 4; + break; + case CANFD_BPS_800KBAUD: + brq = 4; + tseg1 = 18; + tseg2 = 4; + break; + case CANFD_BPS_500KBAUD: + brq = 4; + tseg1 = 33; + tseg2 = 4; + break; + case CANFD_BPS_250KBAUD: + brq = 4; + tseg1 = 68; + tseg2 = 9; + break; + case CANFD_BPS_200KBAUD: + brq = 9; + tseg1 = 43; + tseg2 = 4; + break; + case CANFD_BPS_125KBAUD: + brq = 9; + tseg1 = 68; + tseg2 = 9; + break; + case CANFD_BPS_100KBAUD: + brq = 24; + tseg1 = 33; + tseg2 = 4; + break; + case CANFD_BPS_50KBAUD: + brq = 24; + tseg1 = 68; + tseg2 = 9; + break; + default: + brq = 4; + tseg1 = 13; + tseg2 = 4; + break; + } + sjw = 0; + + CLEAR_BIT(pReg->BITTIMING, + CAN_BITTIMING_SJW_MASK | + CAN_BITTIMING_BRP_MASK | + CAN_BITTIMING_TSEG1_MASK | + CAN_BITTIMING_TSEG2_MASK); + + SET_BIT(pReg->BITTIMING, + (sjw << CAN_BITTIMING_SJW_SHIFT) | + (brq << CAN_BITTIMING_BRP_SHIFT) | + (tseg1 << CAN_BITTIMING_TSEG1_SHIFT) | + (tseg2 << CAN_BITTIMING_TSEG2_SHIFT)); + + return HAL_OK; +} + +/** + * 描述：设置CAN时钟为200MHz + * 备注：此例程仅适用于GPLL=1200MHz的条件 +*/ +static HAL_Status HAL_CANFD_SetClock(struct CAN_REG *pReg) +{ + if (pReg == CAN0) + { + MODIFY_REG(CRU->CLKSEL_CON[39], + CRU_CLKSEL_CON39_CLK_CAN0_DIV_MASK | + CRU_CLKSEL_CON39_CLK_CAN0_SEL_MASK, + (5 << CRU_CLKSEL_CON39_CLK_CAN0_DIV_SHIFT) | + (0 << CRU_CLKSEL_CON39_CLK_CAN0_SEL_SHIFT) | 0xFFFF0000); + } + else if (pReg == CAN1) + { + MODIFY_REG(CRU->CLKSEL_CON[39], + CRU_CLKSEL_CON39_CLK_CAN1_DIV_MASK | + CRU_CLKSEL_CON39_CLK_CAN1_SEL_MASK, + (5 << CRU_CLKSEL_CON39_CLK_CAN1_DIV_SHIFT) | + (0 << CRU_CLKSEL_CON39_CLK_CAN1_SEL_SHIFT) | 0xFFFF0000); + + } + else if (pReg == CAN2) + { + MODIFY_REG(CRU->CLKSEL_CON[40], + CRU_CLKSEL_CON40_CLK_CAN2_DIV_MASK | + CRU_CLKSEL_CON40_CLK_CAN2_SEL_MASK, + (5 << CRU_CLKSEL_CON40_CLK_CAN2_DIV_SHIFT) | + (0 << CRU_CLKSEL_CON40_CLK_CAN2_SEL_SHIFT) | 0xFFFF0000); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief CANFD init. + * @param pReg: can base + * @param initStrust: can init parameter + * @return HAL_OK. + */ +HAL_Status HAL_CANFD_Init(struct CAN_REG *pReg, struct CANFD_CONFIG *initStrust) +{ + uint32_t mask = 0x1fffffff; + + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + HAL_ASSERT(initStrust != NULL); + + HAL_CANFD_SetClock(pReg); + + CANFD_SetResetMode(pReg); + pReg->INT_MASK0 = 0; + + pReg->AFR_CTRL = 0x1f; + pReg->IDCODE0 = initStrust->canfdFilterId[0]; + pReg->IDMASK0 = initStrust->canfdFilterMask[0] & mask; + pReg->IDCODE1 = initStrust->canfdFilterId[1]; + pReg->IDMASK1 = initStrust->canfdFilterMask[1] & mask; + pReg->IDCODE2 = initStrust->canfdFilterId[2]; + pReg->IDMASK2 = initStrust->canfdFilterMask[2] & mask; + pReg->IDCODE3 = initStrust->canfdFilterId[3]; + pReg->IDMASK3 = initStrust->canfdFilterMask[3] & mask; + pReg->IDCODE4 = initStrust->canfdFilterId[4]; + pReg->IDMASK4 = initStrust->canfdFilterMask[4] & mask; + pReg->IDCODE = initStrust->canfdFilterId[5]; + pReg->IDMASK = initStrust->canfdFilterMask[5] & mask; + + // pReg->RX_FIFO_CTRL |= CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_MASK; + + if ((initStrust->canfdMode & CANFD_MODE_LOOPBACK) == CANFD_MODE_LOOPBACK) + { + SET_BIT(pReg->MODE, CAN_MODE_LBACK_MODE_MASK | CAN_MODE_SELF_TEST_MASK); + } + if ((initStrust->canfdMode & CANFD_MODE_LISTENONLY) == CANFD_MODE_LISTENONLY) + { + SET_BIT(pReg->MODE, CAN_MODE_SILENT_MODE_MASK); + } + if ((initStrust->canfdMode & CANFD_MODE_3_SAMPLES) == CANFD_MODE_3_SAMPLES) + { + SET_BIT(pReg->BITTIMING, CAN_BITTIMING_SAMPLE_MODE_MASK); + } + else + { + CLEAR_BIT(pReg->BITTIMING, CAN_BITTIMING_SAMPLE_MODE_MASK); + } + + SET_BIT(pReg->MODE, CAN_MODE_AUTO_RETX_MODE_MASK | CAN_MODE_AUTO_BUS_ON_MASK); + + HAL_CANFD_SetBps(pReg, initStrust->bps); + + return HAL_OK; +} + +/** + * @brief CANFD start. + * @param pReg: can base + * @return HAL_OK. + */ +HAL_Status HAL_CANFD_Start(struct CAN_REG *pReg) +{ + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + + CANFD_SetNormalMode(pReg); + + return HAL_OK; +} + +/** + * @brief CANFD stop. + * @param pReg: can base + * @return HAL_OK. + */ +HAL_Status HAL_CANFD_Stop(struct CAN_REG *pReg) +{ + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + + CANFD_SetResetMode(pReg); + WRITE_REG(pReg->INT_MASK0, 0xffff); + + return HAL_OK; +} + +/** + * @brief CANFD tx. + * @param pReg: can base + * @param TxMsg: Tx message + * @return HAL_OK. + */ +HAL_Status HAL_CANFD_Transmit(struct CAN_REG *pReg, struct CANFD_MSG *TxMsg) +{ + uint8_t cmd = CAN_CMD_TX0_REQ_MASK; + int i; + + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + HAL_ASSERT(TxMsg != NULL); + + if (READ_BIT(pReg->CMD, CAN_CMD_TX0_REQ_MASK)) + { + cmd = CAN_CMD_TX1_REQ_MASK; + } + + if (TxMsg->ide == CANFD_ID_EXTENDED) + { + WRITE_REG(pReg->TXID, TxMsg->extId); + SET_BIT(pReg->TXFRAMEINFO, CAN_TXFRAMEINFO_TXFRAME_FORMAT_MASK); + } + else + { + WRITE_REG(pReg->TXID, TxMsg->stdId); + CLEAR_BIT(pReg->TXFRAMEINFO, CAN_TXFRAMEINFO_TXFRAME_FORMAT_MASK); + } + + if (TxMsg->rtr == CANFD_RTR_REMOTE) + { + TxMsg->dlc = 0; + SET_BIT(pReg->TXFRAMEINFO, CAN_TXFRAMEINFO_TX_RTR_MASK); + } + else + { + CLEAR_BIT(pReg->TXFRAMEINFO, CAN_TXFRAMEINFO_TX_RTR_MASK); + } + + SET_BIT(pReg->TXFRAMEINFO, CANFD_Len2Dlc(TxMsg->dlc)); + + pReg->TXDATA0 = *(uint32_t *)&TxMsg->data[0]; + pReg->TXDATA1 = *(uint32_t *)&TxMsg->data[4]; + + WRITE_REG(pReg->CMD, cmd); + + return HAL_OK; +} + +/** + * @brief CANFD rx. + * @param pReg: can base + * @param RxMsg: Rx message + * @return HAL_OK. + */ +HAL_Status HAL_CANFD_Receive(struct CAN_REG *pReg, struct CANFD_MSG *RxMsg) +{ + uint32_t info, id, len, data[16]; + int i = 0; + + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + + int ret = HAL_OK; + if(!(pReg->STATE & CAN_STATE_RX_BUFFER_FULL_MASK)) + { + ret = HAL_ERROR; + } + + info = READ_REG(pReg->RXFRAMEINFO); + id = READ_REG(pReg->RXID); + + data[0] = READ_REG(pReg->RXDATA0); + data[1] = READ_REG(pReg->RXDATA1); + + len = info & CAN_RXFRAMEINFO_RXDATA_LENGTH_MASK; + RxMsg->ide = (info & CAN_RXFRAMEINFO_RXFRAME_FORMAT_MASK) >> CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT; + RxMsg->rtr = (info & CAN_RXFRAMEINFO_RX_RTR_MASK) >> CAN_RXFRAMEINFO_RX_RTR_SHIFT; + RxMsg->dlc = CANFD_Dlc2Len(len); + if (RxMsg->ide == CANFD_ID_EXTENDED) + { + RxMsg->extId = id & CAN_FD_RXID_RX_ID_MASK; + } + else + { + RxMsg->stdId = id & 0x3ff; + } + + *(uint32_t *)&RxMsg->data[0] = data[0]; + *(uint32_t *)&RxMsg->data[4] = data[1]; + + return ret; +} + +/** + * @brief CANFD get interrupt. + * @param pReg: can base + * @return interrupt status. + */ +uint32_t HAL_CANFD_GetInterrupt(struct CAN_REG *pReg) +{ + uint32_t isr; + + HAL_ASSERT(IS_CAN_INSTANCE(pReg)); + + isr = READ_REG(pReg->INT); + + /* set 1 to clear interrupt */ + WRITE_REG(pReg->INT, isr); + + return isr; +} + +/** + * @brief CANFD get interrupt mask combin. + * @param type: interrupt type + * @return err interrupt mask combin. + */ +uint32_t HAL_CANFD_GetErrInterruptMaskCombin(eCANFD_IntType type) +{ + uint32_t isr = 0; + + switch (type) + { + case CANFD_INT_ERR: + isr = CAN_INT_BUS_OFF_INT_MASK | + CAN_INT_ERROR_INT_MASK | + CAN_INT_TX_ARBIT_FAIL_INT_MASK | + CAN_INT_PASSIVE_ERROR_INT_MASK | + CAN_INT_OVERLOAD_INT_MASK | + CAN_INT_ERROR_WARNING_INT_MASK; + break; + case CANFD_INT_RX_OF: + isr = CAN_INT_RX_FIFO_OVERFLOW_INT_MASK | CAN_INT_RX_FIFO_FULL_INT_MASK; + break; + case CANFD_INT_TX_FINISH: + isr = CAN_INT_TX_FINISH_INT_MASK; + break; + case CANFD_INT_RX_FINISH: + isr = CAN_INT_RX_FINISH_INT_MASK; + break; + default: + break; + } + + return isr; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif diff --git a/demos/rk3588/bsp/hal/hal_canfd.h b/demos/rk3588/bsp/hal/hal_canfd.h new file mode 100755 index 00000000..bbb52b70 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_canfd.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_CANFD_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CANFD + * @{ + */ + +#ifndef _HAL_CANFD_H_ +#define _HAL_CANFD_H_ + +#include "hal_def.h" + +/*************************** MACRO Definition ****************************/ +/** @defgroup CANFD_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define CANFD_ID_STANDARD 0 +#define CANFD_ID_EXTENDED 1 +#define CANFD_RTR_DATA 0 +#define CANFD_RTR_REMOTE 1 + +typedef enum { + CANFD_BPS_1MBAUD = 1, + CANFD_BPS_800KBAUD, + CANFD_BPS_500KBAUD, + CANFD_BPS_250KBAUD, + CANFD_BPS_200KBAUD, + CANFD_BPS_125KBAUD, + CANFD_BPS_100KBAUD, + CANFD_BPS_50KBAUD, +} eCANFD_Bps; + +typedef enum { + CANFD_INT_ERR = 1, + CANFD_INT_RX_OF, + CANFD_INT_TX_FINISH, + CANFD_INT_RX_FINISH, +} eCANFD_IntType; + +typedef enum { + CANFD_MODE_LOOPBACK = 0x1, + CANFD_MODE_LISTENONLY = 0x2, + CANFD_MODE_3_SAMPLES = 0x4, +} eCANFD_Mode; + +struct CANFD_BPS { + uint32_t sjw; + uint32_t brq; + uint32_t tseg1; + uint32_t tseg2; + uint32_t tdc; +}; + +struct CANFD_CONFIG { + uint32_t canfdMode; + uint32_t canfdFilterId[6]; + uint32_t canfdFilterMask[6]; + eCANFD_Bps bps; +}; + +struct CANFD_MSG { + uint16_t stdId; + uint32_t extId; + uint8_t ide; + uint8_t rtr; + uint8_t dlc; + uint8_t data[8]; +}; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup CANFD_Public_Function_Declare Public Function Declare + * @{ + */ +HAL_Status HAL_CANFD_Init(struct CAN_REG *pReg, struct CANFD_CONFIG *initStrust); +HAL_Status HAL_CANFD_Start(struct CAN_REG *pReg); +HAL_Status HAL_CANFD_Stop(struct CAN_REG *pReg); +HAL_Status HAL_CANFD_SetNBps(struct CAN_REG *pReg, eCANFD_Bps bsp); +HAL_Status HAL_CANFD_SetDBps(struct CAN_REG *pReg, eCANFD_Bps bps); +HAL_Status HAL_CANFD_Transmit(struct CAN_REG *pReg, struct CANFD_MSG *TxMsg); +HAL_Status HAL_CANFD_Receive(struct CAN_REG *pReg, struct CANFD_MSG *RxMsg); +uint32_t HAL_CANFD_GetInterrupt(struct CAN_REG *pReg); +uint32_t HAL_CANFD_GetErrInterruptMaskCombin(eCANFD_IntType type); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_CANFD_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_conf.h b/demos/rk3588/bsp/hal/hal_conf.h new file mode 100755 index 00000000..d7611be7 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_conf.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_CONF_H_ +#define _HAL_CONF_H_ + +/* + * The file hal_conf.h.template is the summary of all the driver modules in + * the HAL, the hal_conf of each specific chip only needs to extract the + * macro definition of the corresponding module. + * Rules: + * 1.Including three part: soc config, driver config and driver sub config. + * 2.For the optional configuration, add a prominent note. + */ + +/************************ HAL SOC Config **************************************/ + +//#define RKMCU_KOALA +//#define RKMCU_PISCES +//#define RKMCU_RK2106 +//#define RKMCU_RK2108 +//#define RKMCU_RK2206 +//#define SOC_RK1808 +//#define SOC_RK3568 +#define SOC_RK3588 +//#define SOC_RV1108 +//#define SOC_RV1126 +//#define SOC_SWALLOW + +#define HAL_AP_CORE /**< Only be defined in Asymmetric Multi-Processing AP project */ +//#define HAL_MCU_CORE /**< Only be defined in Asymmetric Multi-Processing MCU project */ + +// #define SYS_TIMER TIMER10 /**< System timer designation (RK TIMER) */ + +/************************ HAL Driver Config ***********************************/ + +// #define HAL_ACDCDIG_MODULE_ENABLED +// #define HAL_ACODEC_MODULE_ENABLED +// #define HAL_ARCHTIMER_MODULE_ENABLED +// #define HAL_AUDIOPWM_MODULE_ENABLED +// #define HAL_BUFMGR_MODULE_ENABLED +// #define HAL_CACHE_ECC_MODULE_ENABLED +// #define HAL_CANFD_MODULE_ENABLED +// #define HAL_CKCAL_MODULE_ENABLED +// #define HAL_CPU_TOPOLOGY_MODULE_ENABLED +#define HAL_CRU_MODULE_ENABLED +// #define HAL_CRYPTO_MODULE_ENABLED +// #define HAL_DCACHE_MODULE_ENABLED +// #define HAL_DDR_ECC_MODULE_ENABLED +// #define HAL_DEMO_MODULE_ENABLED +// #define HAL_DSI_MODULE_ENABLED +// #define HAL_DSP_MODULE_ENABLED +// #define HAL_DWDMA_MODULE_ENABLED +// #define HAL_EFUSE_MODULE_ENABLED +// #define HAL_EHCI_MODULE_ENABLED +// #define HAL_FSPI_MODULE_ENABLED +// #define HAL_GIC_MODULE_ENABLED +// #define HAL_GMAC_MODULE_ENABLED +// #define HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +// #define HAL_HCD_MODULE_ENABLED +// #define HAL_HWSPINLOCK_MODULE_ENABLED +// #define HAL_HYPERPSRAM_MODULE_ENABLED +// #define HAL_I2C_MODULE_ENABLED +// #define HAL_I2S_MODULE_ENABLED +// #define HAL_I2STDM_MODULE_ENABLED +// #define HAL_ICACHE_MODULE_ENABLED +// #define HAL_INTC_MODULE_ENABLED +// #define HAL_IRQ_HANDLER_MODULE_ENABLED +// #define HAL_KEYCTRL_MODULE_ENABLED +// #define HAL_MBOX_MODULE_ENABLED +// #define HAL_NVIC_MODULE_ENABLED +// #define HAL_OHCI_MODULE_ENABLED +// #define HAL_PCD_MODULE_ENABLED +// #define HAL_PCIE_MODULE_ENABLED +// #define HAL_PDM_MODULE_ENABLED +#define HAL_PINCTRL_MODULE_ENABLED +// #define HAL_PL330_MODULE_ENABLED +// #define HAL_PM_CPU_SLEEP_MODULE_ENABLED +// #define HAL_PM_RUNTIME_MODULE_ENABLED +// #define HAL_PM_SLEEP_MODULE_ENABLED +// #define HAL_PMU_MODULE_ENABLED +// #define HAL_PVTM_MODULE_ENABLED +// #define HAL_PWM_MODULE_ENABLED +// #define HAL_PWR_INTBUS_MODULE_ENABLED +// #define HAL_PWR_MODULE_ENABLED +// #define HAL_QPIPSRAM_MODULE_ENABLED +// #define HAL_RISCVIC_MODULE_ENABLED +// #define HAL_SARADC_MODULE_ENABLED +// #define HAL_SDIO_MODULE_ENABLED +// #define HAL_SFC_MODULE_ENABLED +// #define HAL_SMCCC_MODULE_ENABLED +// #define HAL_SNOR_MODULE_ENABLED +// #define HAL_SPI2APB_MODULE_ENABLED +// #define HAL_SPI_MODULE_ENABLED +// #define HAL_SPINAND_MODULE_ENABLED +// #define HAL_SPINLOCK_MODULE_ENABLED +// #define HAL_SYSTICK_MODULE_ENABLED +// #define HAL_TIMER_MODULE_ENABLED +// #define HAL_TOUCHKEY_MODULE_ENABLED +// #define HAL_TSADC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +// #define HAL_VAD_MODULE_ENABLED +// #define HAL_VICAP_MODULE_ENABLED +// #define HAL_VOP_MODULE_ENABLED +// #define HAL_WDT_MODULE_ENABLED + +/************************ HAL Driver Sub Config *******************************/ + +//#define HAL_DBG_USING_RTT_SERIAL +//#define HAL_DBG_USING_LIBC_PRINTF +// #define HAL_DBG_ON +// #define HAL_DBG_INFO_ON +// #define HAL_DBG_WRN_ON +// #define HAL_DBG_ERR_ON +// #define HAL_ASSERT_ON + +#ifdef HAL_CRU_MODULE_ENABLED +#define HAL_CRU_AS_FEATURE_ENABLED +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +#define HAL_FSPI_XIP_ENABLE /**< FSPI supports XIP by default */ +// #define HAL_FSPI_ALIGNED_CHECK_BYPASS /**< Disable memery unalighed check if these behavior is support */ +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#define HAL_GIC_AMP_FEATURE_ENABLED +#define HAL_GIC_PREEMPT_FEATURE_ENABLED +#define HAL_GIC_WAIT_LINUX_INIT_ENABLED +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#define HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#define HAL_GPIO_IRQ_GROUP_PRIO_LEVEL_MAX (3) /**< max priority level */ +#endif + +#ifdef HAL_HWSPINLOCK_MODULE_ENABLED +#define HAL_HWSPINLOCK_OWNER_ID 1 +#endif + +#ifdef HAL_QPIPSRAM_MODULE_ENABLED +#define HAL_QPIPSRAM_HALF_SLEEP_ENABLED /**< If support half sleep, configure it */ +#endif + +#ifdef HAL_SNOR_MODULE_ENABLED +#define HAL_SNOR_FSPI_HOST /**< Choose SNOR Host: FSPI */ +//#define HAL_SNOR_SPI_HOST /**< Choose SNOR Host: SPI */ +//#define HAL_SNOR_SFC_HOST /**< Choose SNOR Host: SFC */ +#endif + +#ifdef HAL_WDT_MODULE_ENABLED +#define HAL_WDT_DYNFREQ_FEATURE_ENABLED +#endif + +#endif diff --git a/demos/rk3588/bsp/hal/hal_cru.c b/demos/rk3588/bsp/hal/hal_cru.c new file mode 100755 index 00000000..844d8b8b --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_cru.c @@ -0,0 +1,1528 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_How_To_Use How To Use + * @{ + + The CRU driver can be used as follows: + + - Invoke cru functions to set clk rate, enable or disable clk, reset clk in each device. + - The gate and soft reset id is include register offset and shift information: + + con_offset: id /16 + shift: id %16 + + - The mux and div id is include register offset, shift, mask information: + + [15:0]: con + [23:16]: shift + [31:24]: width + + - CRU driver is just responsible for passing simple command data, And + the usecount is the user's responsibility. Protection the usecount at the driver layer. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#if defined(SOC_RV1108) +#define PWRDOWN_SHIFT 0 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIFT +#define PLL_POSTDIV1_SHIFT 8 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 12 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 3 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#elif defined(SOC_RK3588) +#define PLLCON0_M_SHIFT 0 +#define PLLCON0_M_MASK 0x3ff << PLLCON0_M_SHIFT +#define PLLCON1_P_SHIFT 0 +#define PLLCON1_P_MASK 0x3f << PLLCON1_P_SHIFT +#define PLLCON1_S_SHIFT 6 +#define PLLCON1_S_MASK 0x7 << PLLCON1_S_SHIFT +#define PLLCON2_K_SHIFT 0 +#define PLLCON2_K_MASK 0xffff << PLLCON2_K_SHIFT +#define PLLCON1_PWRDOWN BIT(13) +#define PLLCON6_LOCK_STATUS BIT(15) + +#define BYPASS_SHIFT 15 +#define BYPASS_MASK (1 << BYPASS_SHIFT) + +#define PWRDOWN_SHIFT 13 +#define PWRDOWN_MASK (1 << PWRDOWN_SHIFT) + +#else +#define PWRDOWN_SHIFT 13 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIFT +#define PLL_POSTDIV1_SHIFT 12 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 6 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 12 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT +#endif + +#define MIN_FOUTVCO_FREQ (800 * MHZ) +#define MAX_FOUTVCO_FREQ (2000 * MHZ) +#define MIN_FOUT_FREQ (24 * MHZ) +#define MAX_FOUT_FREQ (1600 * MHZ) + +#define EXPONENT_OF_FRAC_PLL 24 +#define RK_PLL_MODE_SLOW 0 +#define RK_PLL_MODE_NORMAL 1 +#define RK_PLL_MODE_DEEP 2 +#define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift) + +#define PLL_GET_FBDIV(x) (((uint32_t)(x) & (PLL_FBDIV_MASK)) >> PLL_FBDIV_SHIFT) +#define PLL_GET_REFDIV(x) \ + (((uint32_t)(x) & (PLL_REFDIV_MASK)) >> PLL_REFDIV_SHIFT) +#define PLL_GET_POSTDIV1(x) \ + (((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT) +#define PLL_GET_POSTDIV2(x) \ + (((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT) +#define PLL_GET_DSMPD(x) (((uint32_t)(x) & (PLL_DSMPD_MASK)) >> PLL_DSMPD_SHIFT) +#define PLL_GET_FRAC(x) (((uint32_t)(x) & (PLL_FRAC_MASK)) >> PLL_FRAC_SHIFT) + +#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ) + +#define CRU_READ(r) (*(volatile uint32_t *)(r)) +#define CRU_WRITE(r, b, w, v) (*(volatile uint32_t *)(r) = ((w) << (16) | (v) << (b))) + +/********************* Private Structure Definition **************************/ +static struct PLL_CONFIG g_rockchipAutoTable; +__WEAK const struct HAL_CRU_DEV g_cruDev; + +/********************* Private Variable Definition ***************************/ +/********************* Private Function Definition ***************************/ + +/** Calculate the greatest common divisor */ +static uint32_t CRU_Gcd(uint32_t m, uint32_t n) +{ + int t; + + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } + m -= n; + } + + return n; +} + +static int isBetterFreq(uint32_t now, uint32_t new, uint32_t best) +{ + return (new <= now && new > best); +} + +int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3) +{ + uint32_t best = 0; + + if (isBetterFreq(freq, freq0, best)) { + best = freq0; + } + + if (isBetterFreq(freq, freq1, best)) { + best = freq1; + } + + if (isBetterFreq(freq, freq2, best)) { + best = freq2; + } + + if (isBetterFreq(freq, freq3, best)) { + best = freq3; + } + + if (best == freq0) { + return 0; + } else if (best == freq1) { + return 1; + } else if (best == freq2) { + return 2; + } else if (best == freq3) { + return 3; + } + + return HAL_INVAL; +} + +int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1, uint32_t freq2) +{ + return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq2, freq2); +} + +int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1) +{ + return HAL_CRU_FreqGetMux4(freq, freq0, freq1, freq1, freq1); +} + +uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3) +{ + switch (HAL_CRU_ClkGetMux(muxName)) { + case 0: + + return freq0; + case 1: + + return freq1; + case 2: + + return freq2; + case 3: + + return freq3; + } + + return HAL_INVAL; +} + +uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, + uint32_t freq1, uint32_t freq2) +{ + return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq2, freq2); +} + +uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1) +{ + return HAL_CRU_MuxGetFreq4(muxName, freq0, freq1, freq1, freq1); +} + +int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, + uint32_t pFreq1, uint32_t pFreq2, + uint32_t pFreq3, uint32_t *pFreqOut) +{ + uint32_t mux; + + if (pFreq3 && (pFreq3 % freq == 0)) { + *pFreqOut = pFreq3; + mux = 3; + } else if (pFreq2 && (pFreq2 % freq == 0)) { + *pFreqOut = pFreq2; + mux = 2; + } else if (pFreq1 % freq == 0) { + *pFreqOut = pFreq1; + mux = 1; + } else { + *pFreqOut = pFreq0; + mux = 0; + } + + return mux; +} + +int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, + uint32_t pFreq1, uint32_t pFreq2, uint32_t *pFreqOut) +{ + return HAL_CRU_RoundFreqGetMux4(freq, pFreq0, pFreq1, pFreq2, 0, pFreqOut); +} + +int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, uint32_t *pFreqOut) +{ + return HAL_CRU_RoundFreqGetMux4(freq, pFreq0, pFreq1, 0, 0, pFreqOut); +} + +#if defined(SOC_RK3588) +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * FFVCO = ((m + k / 65536) * FFIN) / p + * FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s) + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint64_t fvcoMin = 2250ULL * MHZ, fvcoMax = 4500ULL * MHZ; + uint64_t foutMin = 37ULL * MHZ, foutMax = 4500ULL * MHZ; + uint64_t fvco, fref, fout, ffrac; + uint32_t p, m, s; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + if (foutHz > foutMax || foutHz < foutMin) { + return NULL; + } + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 2; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if (fvco == m * finHz / p) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + rateTable->k = 0; + + return rateTable; + } + } + } + } + } else { + for (s = 0; s <= 6; s++) { + fvco = (uint64_t)foutHz << s; + if (fvco < fvcoMin || fvco > fvcoMax) { + continue; + } + + for (p = 1; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if ((fvco >= m * finHz / p) && (fvco < (m + 1) * finHz / p)) { + rateTable->p = p; + rateTable->m = m; + rateTable->s = s; + fref = finHz / p; + ffrac = fvco - (m * fref); + fout = ffrac * 65536; + rateTable->k = fout / fref; + + return rateTable; + } + } + } + } + } + + return NULL; +} + +#else +/** + * @brief Rockchip pll clk set postdiv. + * @param foutHz: output freq + * @param *postDiv1: pll postDiv1 + * @param *postDiv2: pll postDiv2 + * @param *foutVco: pll vco + * @return HAL_Status. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + */ +static HAL_Status CRU_PllSetPostDiv(uint32_t foutHz, uint32_t *postDiv1, + uint32_t *postDiv2, uint32_t *foutVco) +{ + uint32_t freq; + + if (foutHz < MIN_FOUTVCO_FREQ) { + for (*postDiv1 = 1; *postDiv1 <= 7; (*postDiv1)++) { + for (*postDiv2 = 1; *postDiv2 <= 7; (*postDiv2)++) { + freq = foutHz * (*postDiv1) * (*postDiv2); + if (freq >= MIN_FOUTVCO_FREQ && freq <= MAX_FOUTVCO_FREQ) { + *foutVco = freq; + + return HAL_OK; + } + } + } + + return HAL_ERROR; + } else { + *postDiv1 = 1; + *postDiv2 = 1; + + return HAL_OK; + } +} + +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + * FREF = fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, + uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint32_t foutVco = foutHz; + uint64_t fin64, frac64; + uint32_t postDiv1, postDiv2; + uint32_t clkGcd = 0; + HAL_Status error; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + error = CRU_PllSetPostDiv(foutHz, &postDiv1, &postDiv2, &foutVco); + if (error) { + return NULL; + } + rateTable->postDiv1 = postDiv1; + rateTable->postDiv2 = postDiv2; + rateTable->dsmpd = 1; + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + finHz /= MHZ; + foutVco /= MHZ; + clkGcd = CRU_Gcd(finHz, foutVco); + rateTable->refDiv = finHz / clkGcd; + rateTable->fbDiv = foutVco / clkGcd; + + rateTable->frac = 0; + } else if (finHz / MHZ * MHZ != finHz) { + clkGcd = foutHz / finHz; + rateTable->fbDiv = clkGcd; + rateTable->refDiv = 1; + rateTable->postDiv1 = 1; + rateTable->postDiv2 = 1; + + fin64 = foutHz * rateTable->refDiv; + fin64 = HAL_DivU64(fin64 << EXPONENT_OF_FRAC_PLL, finHz); + frac64 = rateTable->fbDiv; + frac64 = rateTable->fbDiv << EXPONENT_OF_FRAC_PLL; + frac64 = fin64 - frac64; + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } else { + clkGcd = CRU_Gcd(finHz / MHZ, foutVco / MHZ); + rateTable->refDiv = finHz / MHZ / clkGcd; + rateTable->fbDiv = foutVco / MHZ / clkGcd; + rateTable->frac = 0; + + frac64 = (foutVco % MHZ); + fin64 = finHz; + frac64 = frac64 * rateTable->refDiv; + frac64 = HAL_DivU64(frac64 << EXPONENT_OF_FRAC_PLL, fin64); + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } + + return rateTable; +} +#endif + +/** + * @brief Get pll parameter by rateTable. + * @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters + * @param rate: pll target rate. + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Look up the rateTable to get the PLL config parameter + */ +static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup, + uint32_t rate) +{ + const struct PLL_CONFIG *rateTable = pSetup->rateTable; + + if (rateTable == NULL) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } + + while (rateTable->rate) { + if (rateTable->rate == rate) { + break; + } + rateTable++; + } + if (rateTable->rate != rate) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } else { + return rateTable; + } +} +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer. + * @{ + */ + +#if defined(SOC_RV1108) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset1))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset3))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset2)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset3), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#elif defined(SOC_RK3588) +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If K = 0 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / P * M + * FOUT = FOUTVCO / 2^S + * If K > 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / P) * (M + K / 65536) + * FOUT = FOUTVCO / 2^S + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t m, p, s, k; + uint64_t rate = PLL_INPUT_OSC_RATE; + uint32_t mode = 0; + + if (pSetup->modeMask) { + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + } else { + mode = RK_PLL_MODE_NORMAL; + } + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + + case RK_PLL_MODE_NORMAL: + m = (READ_REG(*(pSetup->conOffset0)) & PLLCON0_M_MASK) >> PLLCON0_M_SHIFT; + p = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_P_MASK) >> PLLCON1_P_SHIFT; + s = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_S_MASK) >> PLLCON1_S_SHIFT; + k = (READ_REG(*(pSetup->conOffset2)) & PLLCON2_K_MASK) >> PLLCON2_K_SHIFT; + + rate *= m; + rate = rate / p; + if (k) { + /* fractional mode */ + uint64_t frac = PLL_INPUT_OSC_RATE / p; + + frac *= k; + frac = frac / 65536; + rate += frac; + } + rate = rate >> s; + break; + + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config M, P, S, K + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 24000000; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + } + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLLCON0_M_MASK, pConfig->m << PLLCON0_M_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_P_MASK, pConfig->p << PLLCON1_P_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_S_MASK, pConfig->s << PLLCON1_S_SHIFT); + if (pConfig->k) { + WRITE_REG_MASK_WE(*(pSetup->conOffset2), PLLCON2_K_MASK, pConfig->k << PLLCON2_K_SHIFT); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + if (pSetup->modeMask) { + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + } + + /* + * PLL operates normally. + * + * ATF system suspend requires memory repair operation which would + * bypass the pll, let's ensure it's on normal mode. + */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), BYPASS_MASK, 0 << BYPASS_SHIFT); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} + +#else +/* + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0))); + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/* + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIFT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIFT); + + return HAL_OK; +} +#endif + +#ifdef CRU_CLK_USE_CON_BANK +static const struct HAL_CRU_DEV *CRU_GetInfo(void) +{ + return &g_cruDev; +} + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + HAL_Check ret; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + ret = (HAL_Check)(!((CRU_READ(reg) & (1 << shift)) >> shift)); + + return ret; +} + +HAL_Status HAL_CRU_ClkEnable(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 0U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisable(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].gateOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 1U); + + return HAL_OK; +} + +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + HAL_Check ret; + + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + ret = (HAL_Check)((CRU_READ(reg) & (1 << shift)) >> shift); + + return ret; +} + +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + HAL_ASSERT(shift < 16); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 1U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + uint32_t bank = CLK_GATE_GET_REG_BANK(clk); + uint32_t reg; + + HAL_ASSERT(shift < 16); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].softOffset + index * 4; + CRU_WRITE(reg, shift, 1U << shift, 0U); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index; + uint32_t reg, bank; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + if (divValue > mask) { + divValue = mask; + } + + bank = CLK_DIV_GET_BANK(divName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, shift, mask, (divValue - 1U)); + + return HAL_OK; +} + +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index, divValue; + uint32_t reg, bank; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + bank = CLK_DIV_GET_BANK(divName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + divValue = ((CRU_READ(reg) & mask) >> shift) + 1; + + return divValue; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index; + uint32_t reg, bank; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + bank = CLK_MUX_GET_BANK(muxName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, shift, mask, muxValue); + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t shift, mask, index, muxValue; + uint32_t reg, bank; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + bank = CLK_MUX_GET_BANK(muxName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + muxValue = ((CRU_READ(reg) & mask) >> shift); + + return muxValue; +} + +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t reg, bank; + uint32_t index; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); + bank = CLK_DIV_GET_BANK(fracDivName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + CRU_WRITE(reg, 0, 0, ((numerator << 16) | denominator)); + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator) +{ + const struct HAL_CRU_DEV *ctrl = CRU_GetInfo(); + uint32_t reg, bank; + uint32_t index; + uint32_t val; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); + bank = CLK_DIV_GET_BANK(fracDivName); + reg = ctrl->banks[bank].cruBase + ctrl->banks[bank].selOffset + index * 4; + val = CRU_READ(reg); + + *numerator = (val & 0xffff0000) >> 16; + *denominator = (val & 0x0000ffff); + + return HAL_OK; +} +#else /* CRU_CLK_USE_CON_BANK */ + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); + } else { +#ifdef PMUCRU_BASE + ret = (HAL_Check)(!((PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#else + ret = (HAL_Check)(!((CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] & (1 << shift)) >> shift)); +#endif + } +#else + ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); +#endif + + return ret; +} + +HAL_Status HAL_CRU_ClkEnable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkDisable(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + +#ifdef CRU_GATE_CON_CNT + if (index < CRU_GATE_CON_CNT) { + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#else + CRU->PMU_CLKGATE_CON[index - CRU_GATE_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + } +#else + CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk) +{ + uint32_t index = CLK_GATE_GET_REG_OFFSET(clk); + uint32_t shift = CLK_GATE_GET_BITS_SHIFT(clk); + HAL_Check ret; + +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); + } else { + ret = (HAL_Check)((PMUCRU->CRU_CLKGATE_CON[index - CRU_SRST_CON_CNT] & (1 << shift)) >> shift); + } +#else + ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); +#endif + + return ret; +} + +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 1U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk) +{ + uint32_t index = CLK_RESET_GET_REG_OFFSET(clk); + uint32_t shift = CLK_RESET_GET_BITS_SHIFT(clk); + + HAL_ASSERT(shift < 16); +#ifdef CRU_SRST_CON_CNT + if (index < CRU_SRST_CON_CNT) { + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); + } else { + PMUCRU->CRU_SOFTRST_CON[index - CRU_SRST_CON_CNT] = VAL_MASK_WE(1U << shift, 0U << shift); + } +#else + CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue) +{ + uint32_t shift, mask, index; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + if (divValue > mask) { + divValue = mask; + } + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); +#endif + + return HAL_OK; +} + +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName) +{ + uint32_t shift, mask, index, divValue; + + index = CLK_DIV_GET_REG_OFFSET(divName); + shift = CLK_DIV_GET_BITS_SHIFT(divName); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(divName); + +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); + } else { +#ifdef PMUCRU_BASE + divValue = ((((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#else + divValue = ((((CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]) & mask) >> shift) + 1); +#endif + } +#else + divValue = ((((CRU->CRU_CLKSEL_CON[index]) & mask) >> shift) + 1); +#endif + + return divValue; +} + +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue) +{ + uint32_t shift, mask, index; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] = VAL_MASK_WE(mask, muxValue << shift); +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); +#endif + + return HAL_OK; +} + +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName) +{ + uint32_t shift, mask, index, muxValue; + + index = CLK_MUX_GET_REG_OFFSET(muxName); + shift = CLK_MUX_GET_BITS_SHIFT(muxName); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(muxName); + +#ifdef CRU_CLK_SEL_CON_CNT + if (index < CRU_CLK_SEL_CON_CNT) { + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); + } else { +#ifdef PMUCRU_BASE + muxValue = ((PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#else + muxValue = ((CRU->PMU_CLKSEL_CON[index - CRU_CLK_SEL_CON_CNT] & mask) >> shift); +#endif + } +#else + muxValue = ((CRU->CRU_CLKSEL_CON[index] & mask) >> shift); +#endif + + return muxValue; +} + +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator) +{ + uint32_t index; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + CRU->CRU_CLKSEL_CON[index] = (numerator << 16) | denominator; + } else { +#ifdef PMUCRU_BASE + PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = (numerator << 16) | denominator; +#else + CRU->PMU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT] = (numerator << 16) | denominator; +#endif + } +#else + CRU->CRU_CLKSEL_CON[index] = (numerator << 16) | denominator; +#endif + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t index; + uint32_t val; + + index = CLK_DIV_GET_REG_OFFSET(fracDivName); +#ifdef CRU_CLK_DIV_CON_CNT + if (index < CRU_CLK_DIV_CON_CNT) { + val = CRU->CRU_CLKSEL_CON[index]; + } else { +#ifdef PMUCRU_BASE + val = PMUCRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]; +#else + val = CRU->CRU_CLKSEL_CON[index - CRU_CLK_DIV_CON_CNT]; +#endif + } +#else + val = CRU->CRU_CLKSEL_CON[index]; +#endif + + *numerator = (val & 0xffff0000) >> 16; + *denominator = (val & 0x0000ffff); + + return HAL_OK; +} +#endif /* CRU_CLK_USE_CON_BANK */ + +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t gcdVal; + + gcdVal = CRU_Gcd(rate, rateOut); + if (!gcdVal) { + return HAL_ERROR; + } + + *numerator = rateOut / gcdVal; + *denominator = rate / gcdVal; + + if (*numerator < 4) { + *numerator *= 4; + *denominator *= 4; + } + if (*numerator > 0xffff || *denominator > 0xffff) { + return HAL_INVAL; + } + + return HAL_OK; +} + +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv) +{ + uint32_t div = CLK_GET_DIV(clockName); + uint32_t maxDiv = CLK_DIV_GET_MASK(div); + uint32_t i; + + for (i = 0; i < maxDiv; i++) { + if (((pRate * 2) == (rate * (i * 2 + 3)))) { + *bestdiv = i; + + return HAL_OK; + } + } + + return HAL_ERROR; +} + +__WEAK HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +{ + HAL_CRU_ClkEnable(gateId); + + return HAL_OK; +} + +__WEAK HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +{ + HAL_CRU_ClkDisable(gateId); + + return HAL_OK; +} + +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type) +{ +#ifdef CRU_GLB_SRST_FST_VALUE_OFFSET + if (type == GLB_SRST_FST) { + CRU->GLB_SRST_FST_VALUE = GLB_SRST_FST; + } +#endif +#ifdef CRU_GLB_SRST_SND_VALUE_OFFSET + if (type == GLB_SRST_SND) { + CRU->GLB_SRST_SND_VALUE = GLB_SRST_SND; + } +#endif + + return HAL_INVAL; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_cru.h b/demos/rk3588/bsp/hal/hal_cru.h new file mode 100755 index 00000000..b6a5d6f4 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_cru.h @@ -0,0 +1,452 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_CRU_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +#ifndef _HAL_CRU_H_ +#define _HAL_CRU_H_ + +#include "hal_def.h" + +/*************************** MACRO Definition ****************************/ +/** @defgroup CRU_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifdef HAL_CRU_DBG_ON +#define HAL_CRU_DBG(fmt, arg...) HAL_SYSLOG("[HAL CRU] " fmt, ##arg) +#else +#define HAL_CRU_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL CRU] " fmt, ##arg); } while (0) +#endif + +#define MHZ 1000000 +#define KHZ 1000 + +#ifndef PLL_INPUT_OSC_RATE +#define PLL_INPUT_OSC_RATE (24 * MHZ) +#endif + +#define GENVAL_D16(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) / 16)) +#define GENVAL_D16_REM(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) % 16)) +#define WIDTH_TO_MASK(w) ((1 << (w)) - 1) + +/* + * RESET/GATE fields: + * [31:16]: reserved + * [15:12]: bank + * [11:0]: id + */ +#define CLK_RESET_GET_REG_OFFSET(x) GENVAL_D16(x, 11, 0) +#define CLK_RESET_GET_BITS_SHIFT(x) GENVAL_D16_REM(x, 11, 0) +#define CLK_RESET_GET_REG_BANK(x) HAL_GENVAL(x, 15, 12) + +#define CLK_GATE_GET_REG_OFFSET(x) CLK_RESET_GET_REG_OFFSET(x) +#define CLK_GATE_GET_BITS_SHIFT(x) CLK_RESET_GET_BITS_SHIFT(x) +#define CLK_GATE_GET_REG_BANK(x) CLK_RESET_GET_REG_BANK(x) + +/* + * MUX/DIV fields: + * [31:24]: width + * [23:16]: shift + * [15:12]: reserved + * [11:8]: bank + * [7:0]: reg + */ +#define CLK_MUX_GET_REG_OFFSET(x) HAL_GENVAL(x, 7, 0) +#define CLK_MUX_GET_BANK(x) HAL_GENVAL(x, 11, 8) +#define CLK_MUX_GET_BITS_SHIFT(x) HAL_GENVAL(x, 23, 16) +#define CLK_MUX_GET_WIDTH(x) HAL_GENVAL(x, 31, 24) +#define CLK_MUX_GET_MASK(x) (WIDTH_TO_MASK(CLK_MUX_GET_WIDTH(x)) << CLK_MUX_GET_BITS_SHIFT(x)) + +#define CLK_DIV_GET_REG_OFFSET(x) CLK_MUX_GET_REG_OFFSET(x) +#define CLK_DIV_GET_BANK(x) CLK_MUX_GET_BANK(x) +#define CLK_DIV_GET_BITS_SHIFT(x) CLK_MUX_GET_BITS_SHIFT(x) +#define CLK_DIV_GET_WIDTH(x) CLK_MUX_GET_WIDTH(x) +#define CLK_DIV_GET_MASK(x) CLK_MUX_GET_MASK(x) +#define CLK_DIV_GET_MAXDIV(x) ((1 << CLK_DIV_GET_WIDTH(x)) - 1) + +/* + * v64 mux = v32 | bank(in bit[35:32]) + * v64 div = v32 | bank(in bit[39:36]) + */ +#ifdef CRU_CLK_USE_CON_BANK +#define CLK_GET_MUX(v64) ((uint32_t)(((v64) & 0xFFFFFFFF00000000) >> 32)) +#define CLK_GET_DIV(v64) ((uint32_t)((v64) & 0x00000000FFFFFFFF)) +#else +#define CLK_GET_MUX(v32) ((uint32_t)((v32) & 0x0F0F00FFU)) +#define CLK_GET_DIV(v32) ((uint32_t)((((v32) & 0x0000FF00U) >> 8) | \ + (((v32) & 0xF0F00000U) >> 4))) +#endif + +#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \ + _frac) \ + { \ + .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \ + .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \ + .frac = _frac, \ + } + +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ + { \ + .rate = _rate##U, .p = _p, .m = _m, \ + .s = _s, .k = _k, \ + } + +#define CRU_BANK_CFG_FLAGS(reg, sel, gate, soft) \ + { \ + .cruBase = reg, \ + .selOffset = sel, \ + .gateOffset = gate, \ + .softOffset = soft, \ + } + +struct PLL_CONFIG { + uint32_t rate; + + union { + struct { + uint32_t fbDiv; + uint32_t postDiv1; + uint32_t refDiv; + uint32_t postDiv2; + uint32_t dsmpd; + uint32_t frac; + }; + struct { + uint32_t m; + uint32_t p; + uint32_t s; + uint32_t k; + }; + }; +}; + +struct PLL_SETUP { + __IO uint32_t *conOffset0; + __IO uint32_t *conOffset1; + __IO uint32_t *conOffset2; + __IO uint32_t *conOffset3; + __IO uint32_t *conOffset6; + __IO uint32_t *modeOffset; + __I uint32_t *stat0; + uint32_t modeShift; + uint32_t lockShift; + uint32_t modeMask; + const struct PLL_CONFIG *rateTable; +}; + +typedef enum { + GLB_SRST_FST = 0xfdb9, + GLB_SRST_SND = 0xeca8, +} eCRU_GlbSrstType; + +typedef enum { + GLB_RST_FST_WDT0 = 0U, + GLB_RST_SND_WDT0, + GLB_RST_FST_WDT1, + GLB_RST_SND_WDT1, + GLB_RST_FST_WDT2, + GLB_RST_SND_WDT2, +} eCRU_WdtRstType; + +struct CRU_BANK_INFO { + uint32_t cruBase; + uint32_t selOffset; + uint32_t gateOffset; + uint32_t softOffset; +}; + +struct HAL_CRU_DEV { + const struct CRU_BANK_INFO *banks; + uint8_t banksNum; +}; + +extern const struct HAL_CRU_DEV g_cruDev; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup CRU_Private_Function_Declare Private Function Declare + * @{ + */ + +#define _MHZ(n) ((n) * 1000000) +#define DIV_NO_REM(pFreq, freq, maxDiv) \ + ((!((pFreq) % (freq))) && ((pFreq) / (freq) <= (maxDiv))) + +int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3); +int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1, + uint32_t freq2); +int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1); + +uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2, uint32_t freq3); +uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1, + uint32_t freq2); +uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1); + +int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut); +int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t pFreq2, uint32_t *pFreqOut); +int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1, + uint32_t *pFreqOut); + +/** @} */ + +/** @defgroup CRU_Public_Function_Declare Public Function Declare + * @{ + */ + +/** + * @brief Get pll freq. + * @param pSetup: Contains PLL register parameters + * @return pll rate. + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup); + +/** + * @brief Set pll freq. + * @param pSetup: Contains PLL register parameters + * @param rate: pll set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate); + +/** + * @brief Set pll power up. + * @param pSetup: Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup); + +/** + * @brief Set pll power down. + * @param pSetup: Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup); + +/** + * @brief Check if clk is enabled + * @param clk: clock to check + * @return HAL_Check. + */ +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk); + +/** + * @brief Enable clk + * @param clk: clock to set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkEnable(uint32_t clk); + +/** + * @brief Disable clk + * @param clk: clock to set + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkDisable(uint32_t clk); + +/** + * @brief Check if clk is reset + * @param clk: clock to check + * @return HAL_Check. + */ +HAL_Check HAL_CRU_ClkIsReset(uint32_t clk); + +/** + * @brief Assert the reset to the clk + * @param clk: clock to assert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk); + +/** + * @brief Deassert the reset to the clk + * @param clk: clock to deassert + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk); + +/** + * @brief Set frac div + * @param fracDivName: frac div id(Contains div offset, shift, mask information) + * @param numerator: the numerator to set. + * @param denominator: the denominator to set. + * @return HAL_Status + */ +HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName, + uint32_t numerator, + uint32_t denominator); + +/** + * @brief Get frac div + * @param fracDivName: frac div id(Contains div offset, shift, mask information) + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status + */ +HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName, + uint32_t *numerator, + uint32_t *denominator); + +/** + * @brief Set integer div + * @param divName: div id(Contains div offset, shift, mask information) + * @param divValue: div value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue); + +/** + * @brief Get integer div + * @param divName: div id (Contains div offset, shift, mask information) + * @return div value + */ +uint32_t HAL_CRU_ClkGetDiv(uint32_t divName); + +/** + * @brief Set mux + * @param muxName: mux id (Contains mux offset, shift, mask information) + * @param muxValue: mux value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue); + +/** + * @brief Get mux + * @param muxName: mux id (Contains mux offset, shift, mask information) + * @return mux value + */ +uint32_t HAL_CRU_ClkGetMux(uint32_t muxName); + +/** + * @brief Get frac div config. + * @param rateOut: clk out rate. + * @param rate: clk src rate. + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator); +/** + * @brief Get clk freq. + * @param clockName: CLOCK_Name id. + * @return rate. + * @attention these APIs allow direct use in the HAL layer. + */ +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName); + +/** + * @brief Set clk freq. + * @param clockName: CLOCK_Name id. + * @param rate: clk rate. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate); + +/** + * @brief vop dclk enable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId); + +/** + * @brief vop dclk disable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId); + +/** + * @brief Get Np5 best div. + * @param clockName: clk id. + * @param rate: clk rate. + * @param pRate: clk parent rate + * @param bestdiv: the returned bestdiv. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv); + +/** + * @brief assert CRU global software reset. + * @param type: global software reset type. + * @return HAL_INVAL if the SoC does not support. + */ +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type); + +/** + * @brief wdt glbrst enable. + * @param wdtType: wdt reset type. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType); + +/** + * @brief pll output freq Compensation. + * @param clockName: CLOCK_Name id. + * @param ppm: Efforts to compensate. + * @return HAL_OK. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm); + +/** + * @brief CRU suspend. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_Suspend(void); + +/** + * @brief CRU resume. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status HAL_CRU_Resume(void); + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +/** + * @brief it is for AS init. + */ +void HAL_CRU_AsInit(void); + +/** + * @brief it is for AS enable. + * @param ch: channel + * @param en: 1 is enable, 0 is disable. + */ +void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); +#endif + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_CRU_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_cru_rk3588.c b/demos/rk3588/bsp/hal/hal_cru_rk3588.c new file mode 100755 index 00000000..faf23593 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_cru_rk3588.c @@ -0,0 +1,1422 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ +#include "hal_base.h" + +#if defined(SOC_RK3588) && defined(HAL_CRU_MODULE_ENABLED) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ + +static struct PLL_CONFIG PLL_TABLE[] = +{ + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1500000000, 2, 250, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + { /* sentinel */ }, +}; + +static struct PLL_SETUP LPLL = +{ + .conOffset0 = &(DSUCRU->LPLL_CON[0]), + .conOffset1 = &(DSUCRU->LPLL_CON[1]), + .conOffset2 = &(DSUCRU->LPLL_CON[2]), + .conOffset3 = &(DSUCRU->LPLL_CON[3]), + .conOffset6 = &(DSUCRU->LPLL_CON[6]), + .modeOffset = &(DSUCRU->MODE_CON[0]), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP B0PLL = +{ + .conOffset0 = &(BIGCORE0CRU->B0PLL_CON[0]), + .conOffset1 = &(BIGCORE0CRU->B0PLL_CON[1]), + .conOffset2 = &(BIGCORE0CRU->B0PLL_CON[2]), + .conOffset3 = &(BIGCORE0CRU->B0PLL_CON[3]), + .conOffset6 = &(BIGCORE0CRU->B0PLL_CON[6]), + .modeOffset = &(BIGCORE0CRU->MODE_CON[0]), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP B1PLL = +{ + .conOffset0 = &(BIGCORE1CRU->B1PLL_CON[0]), + .conOffset1 = &(BIGCORE1CRU->B1PLL_CON[1]), + .conOffset2 = &(BIGCORE1CRU->B1PLL_CON[2]), + .conOffset3 = &(BIGCORE1CRU->B1PLL_CON[3]), + .conOffset6 = &(BIGCORE1CRU->B1PLL_CON[6]), + .modeOffset = &(BIGCORE1CRU->MODE_CON[0]), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP CPLL = +{ + .conOffset0 = &(CRU->CPLL_CON[0]), + .conOffset1 = &(CRU->CPLL_CON[1]), + .conOffset2 = &(CRU->CPLL_CON[2]), + .conOffset3 = &(CRU->CPLL_CON[3]), + .conOffset6 = &(CRU->CPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON[0]), + .modeShift = 8, + .lockShift = 15, + .modeMask = 0x3 << 8, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP GPLL = +{ + .conOffset0 = &(CRU->GPLL_CON[0]), + .conOffset1 = &(CRU->GPLL_CON[1]), + .conOffset2 = &(CRU->GPLL_CON[2]), + .conOffset3 = &(CRU->GPLL_CON[3]), + .conOffset6 = &(CRU->GPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON[0]), + .modeShift = 2, + .lockShift = 15, + .modeMask = 0x3 << 2, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP NPLL = +{ + .conOffset0 = &(CRU->NPLL_CON[0]), + .conOffset1 = &(CRU->NPLL_CON[1]), + .conOffset2 = &(CRU->NPLL_CON[2]), + .conOffset3 = &(CRU->NPLL_CON[3]), + .conOffset6 = &(CRU->NPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON[0]), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3 << 0, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP V0PLL = +{ + .conOffset0 = &(CRU->V0PLL_CON[0]), + .conOffset1 = &(CRU->V0PLL_CON[1]), + .conOffset2 = &(CRU->V0PLL_CON[2]), + .conOffset3 = &(CRU->V0PLL_CON[3]), + .conOffset6 = &(CRU->V0PLL_CON[6]), + .modeOffset = &(CRU->MODE_CON[0]), + .modeShift = 4, + .lockShift = 15, + .modeMask = 0x3 << 4, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP AUPLL = +{ + .conOffset0 = &(CRU->AUPLL_CON[0]), + .conOffset1 = &(CRU->AUPLL_CON[1]), + .conOffset2 = &(CRU->AUPLL_CON[2]), + .conOffset3 = &(CRU->AUPLL_CON[3]), + .conOffset6 = &(CRU->AUPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON[0]), + .modeShift = 6, + .lockShift = 15, + .modeMask = 0x3 << 6, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP PPLL = +{ + .conOffset0 = &(PHPTOPCRU->PPLL_CON[0]), + .conOffset1 = &(PHPTOPCRU->PPLL_CON[1]), + .conOffset2 = &(PHPTOPCRU->PPLL_CON[2]), + .conOffset3 = &(PHPTOPCRU->PPLL_CON[3]), + .conOffset6 = &(PHPTOPCRU->PPLL_CON[6]), + .lockShift = 15, + .rateTable = PLL_TABLE, +}; + +/********************* Private Variable Definition ***************************/ + +static uint32_t s_lpllFreq; +static uint32_t s_cpllFreq; +static uint32_t s_gpllFreq; +static uint32_t s_npllFreq; +static uint32_t s_v0pllFreq; +static uint32_t s_ppllFreq; +static uint32_t s_aupllFreq; + +static uint32_t cru_suspend; + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ +static uint32_t HAL_CRU_ClkGetUartFreq(eCLOCK_Name clockName) +{ + uint32_t mux = CLK_GET_MUX(clockName); + uint32_t pRate = 0, rate, n, m; + uint32_t divSrc, divFrac; + uint32_t muxSrc; + + switch (clockName) { + case CLK_UART0: + muxSrc = CLK_GET_MUX(CLK_UART0_SRC); + divSrc = CLK_GET_DIV(CLK_UART0_SRC); + divFrac = CLK_GET_DIV(CLK_UART0_FRAC); + pRate = s_cpllFreq / HAL_CRU_ClkGetDiv(divSrc); + break; + + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + break; + + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + break; + + case CLK_UART3: + muxSrc = CLK_GET_MUX(CLK_UART3_SRC); + divSrc = CLK_GET_DIV(CLK_UART3_SRC); + divFrac = CLK_GET_DIV(CLK_UART3_FRAC); + break; + + case CLK_UART4: + muxSrc = CLK_GET_MUX(CLK_UART4_SRC); + divSrc = CLK_GET_DIV(CLK_UART4_SRC); + divFrac = CLK_GET_DIV(CLK_UART4_FRAC); + break; + + case CLK_UART5: + muxSrc = CLK_GET_MUX(CLK_UART5_SRC); + divSrc = CLK_GET_DIV(CLK_UART5_SRC); + divFrac = CLK_GET_DIV(CLK_UART5_FRAC); + break; + + case CLK_UART6: + muxSrc = CLK_GET_MUX(CLK_UART6_SRC); + divSrc = CLK_GET_DIV(CLK_UART6_SRC); + divFrac = CLK_GET_DIV(CLK_UART6_FRAC); + break; + + case CLK_UART7: + muxSrc = CLK_GET_MUX(CLK_UART7_SRC); + divSrc = CLK_GET_DIV(CLK_UART7_SRC); + divFrac = CLK_GET_DIV(CLK_UART7_FRAC); + break; + + case CLK_UART8: + muxSrc = CLK_GET_MUX(CLK_UART8_SRC); + divSrc = CLK_GET_DIV(CLK_UART8_SRC); + divFrac = CLK_GET_DIV(CLK_UART8_FRAC); + break; + + case CLK_UART9: + muxSrc = CLK_GET_MUX(CLK_UART9_SRC); + divSrc = CLK_GET_DIV(CLK_UART9_SRC); + divFrac = CLK_GET_DIV(CLK_UART9_FRAC); + break; + + default: + + return HAL_INVAL; + } + + /* attention: UART0 src is fixed at CPLL, 'pRate' is initialized */ + if (pRate == 0) { + pRate = HAL_CRU_MuxGetFreq2(muxSrc, + s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc), + s_cpllFreq / HAL_CRU_ClkGetDiv(divSrc)); + } + + HAL_CRU_ClkGetFracDiv(divFrac, &n, &m); + + rate = HAL_CRU_MuxGetFreq3(mux, pRate, (pRate / m) * n, PLL_INPUT_OSC_RATE); + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): rate=%ld, mux=%ld, " + "prate0=%ld, prate1=%ld, prate2=%d\n", + __func__, muxSrc, divSrc, mux, rate, HAL_CRU_ClkGetMux(mux), + pRate, pRate / m * n, PLL_INPUT_OSC_RATE); + + return rate; +} + +static HAL_Status HAL_CRU_ClkSetUartFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t muxSrc, mux = CLK_GET_MUX(clockName); + uint32_t divSrc, divFrac; + uint32_t gateId, fracGateId; + uint32_t n = 0, m = 0, maxDiv; + + switch (clockName) { + case CLK_UART0: + muxSrc = 0; + divSrc = CLK_GET_DIV(CLK_UART0_SRC); + divFrac = CLK_GET_DIV(CLK_UART0_FRAC); + gateId = CLK_UART0_GATE; + fracGateId = CLK_UART0_FRAC_GATE; + break; + + case CLK_UART1: + muxSrc = CLK_GET_MUX(CLK_UART1_SRC); + divSrc = CLK_GET_DIV(CLK_UART1_SRC); + divFrac = CLK_GET_DIV(CLK_UART1_FRAC); + gateId = CLK_UART1_GATE; + fracGateId = CLK_UART1_FRAC_GATE; + break; + + case CLK_UART2: + muxSrc = CLK_GET_MUX(CLK_UART2_SRC); + divSrc = CLK_GET_DIV(CLK_UART2_SRC); + divFrac = CLK_GET_DIV(CLK_UART2_FRAC); + gateId = CLK_UART2_GATE; + fracGateId = CLK_UART2_FRAC_GATE; + break; + + case CLK_UART3: + muxSrc = CLK_GET_MUX(CLK_UART3_SRC); + divSrc = CLK_GET_DIV(CLK_UART3_SRC); + divFrac = CLK_GET_DIV(CLK_UART3_FRAC); + gateId = CLK_UART3_GATE; + fracGateId = CLK_UART3_FRAC_GATE; + break; + + case CLK_UART4: + muxSrc = CLK_GET_MUX(CLK_UART4_SRC); + divSrc = CLK_GET_DIV(CLK_UART4_SRC); + divFrac = CLK_GET_DIV(CLK_UART4_FRAC); + gateId = CLK_UART4_GATE; + fracGateId = CLK_UART4_FRAC_GATE; + break; + + case CLK_UART5: + muxSrc = CLK_GET_MUX(CLK_UART5_SRC); + divSrc = CLK_GET_DIV(CLK_UART5_SRC); + divFrac = CLK_GET_DIV(CLK_UART5_FRAC); + gateId = CLK_UART5_GATE; + fracGateId = CLK_UART5_FRAC_GATE; + break; + + case CLK_UART6: + muxSrc = CLK_GET_MUX(CLK_UART6_SRC); + divSrc = CLK_GET_DIV(CLK_UART6_SRC); + divFrac = CLK_GET_DIV(CLK_UART6_FRAC); + gateId = CLK_UART6_GATE; + fracGateId = CLK_UART6_FRAC_GATE; + break; + + case CLK_UART7: + muxSrc = CLK_GET_MUX(CLK_UART7_SRC); + divSrc = CLK_GET_DIV(CLK_UART7_SRC); + divFrac = CLK_GET_DIV(CLK_UART7_FRAC); + gateId = CLK_UART7_GATE; + fracGateId = CLK_UART7_FRAC_GATE; + break; + + case CLK_UART8: + muxSrc = CLK_GET_MUX(CLK_UART8_SRC); + divSrc = CLK_GET_DIV(CLK_UART8_SRC); + divFrac = CLK_GET_DIV(CLK_UART8_FRAC); + gateId = CLK_UART8_GATE; + fracGateId = CLK_UART8_FRAC_GATE; + break; + + case CLK_UART9: + muxSrc = CLK_GET_MUX(CLK_UART9_SRC); + divSrc = CLK_GET_DIV(CLK_UART9_SRC); + divFrac = CLK_GET_DIV(CLK_UART9_FRAC); + gateId = CLK_UART9_GATE; + fracGateId = CLK_UART9_FRAC_GATE; + break; + default: + + return HAL_INVAL; + } + + maxDiv = CLK_DIV_GET_MAXDIV(divSrc); + + HAL_CRU_ClkEnable(gateId); + HAL_CRU_ClkEnable(fracGateId); + + if (PLL_INPUT_OSC_RATE == rate) { + HAL_CRU_ClkSetMux(mux, 2); + HAL_CRU_ClkDisable(fracGateId); + /* attention: UART0 is fixed at CPLL, 'muxSrc' is set as 0 */ + } else if (DIV_NO_REM(s_cpllFreq, rate, maxDiv) || !muxSrc) { + HAL_CRU_ClkSetDiv(divSrc, HAL_DIV_ROUND_UP(s_cpllFreq, rate)); + if (muxSrc) { + HAL_CRU_ClkSetMux(muxSrc, 1); + } + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else if (DIV_NO_REM(s_gpllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else { + HAL_CRU_FracdivGetConfig(rate, s_gpllFreq, &n, &m); + HAL_CRU_ClkSetDiv(divSrc, 1); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetFracDiv(divFrac, n, m); + HAL_CRU_ClkSetMux(mux, 1); + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): " + "rate=%ld, pRate=%ld, muxSrc=%ld, divSrc=%ld, mux=%ld, " + "maxdiv=%ld, n/m=%ld/%ld\n", + __func__, muxSrc, divSrc, mux, + rate, m ? (rate * m / n) : (rate * HAL_CRU_ClkGetDiv(divSrc)), + HAL_CRU_ClkGetMux(muxSrc), HAL_CRU_ClkGetDiv(divSrc), + HAL_CRU_ClkGetMux(mux), maxDiv, n, m); + + return HAL_OK; +} + +static uint32_t HAL_CRU_ClkGetAudioFreq(eCLOCK_Name clockName) +{ + uint32_t mux = CLK_GET_MUX(clockName); + uint32_t divSrc, divFrac; + uint32_t pRate, rate, n, m; + uint32_t muxSrc; + + switch (clockName) { + case CLK_I2S0_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S0_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S0_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S0_8CH_TX_FRAC); + break; + + case CLK_I2S0_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S0_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S0_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S0_8CH_RX_FRAC); + break; + + case CLK_I2S1_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_TX_FRAC); + break; + + case CLK_I2S1_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_RX_FRAC); + break; + + case CLK_I2S2_2CH: + muxSrc = CLK_GET_MUX(CLK_I2S2_2CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S2_2CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S2_2CH_FRAC); + break; + + case CLK_I2S3_2CH: + muxSrc = CLK_GET_MUX(CLK_I2S3_2CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S3_2CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S3_2CH_FRAC); + break; + + case CLK_I2S4_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S4_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S4_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S4_8CH_TX_FRAC); + break; + + case CLK_I2S5_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S5_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S5_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S5_8CH_TX_FRAC); + break; + + case CLK_I2S6_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S6_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S6_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S6_8CH_TX_FRAC); + break; + + case CLK_I2S6_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S6_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S6_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S6_8CH_RX_FRAC); + break; + + case CLK_I2S7_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S7_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S7_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S7_8CH_RX_FRAC); + break; + + case CLK_I2S8_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S8_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S8_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S8_8CH_TX_FRAC); + break; + + case CLK_I2S9_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S9_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S9_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S9_8CH_RX_FRAC); + break; + + case CLK_I2S10_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S10_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S10_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S10_8CH_RX_FRAC); + break; + + case CLK_SPDIF0: + muxSrc = CLK_GET_MUX(CLK_SPDIF0_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF0_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF0_FRAC); + break; + + case CLK_SPDIF1: + muxSrc = CLK_GET_MUX(CLK_SPDIF1_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF1_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF1_FRAC); + break; + + case CLK_SPDIF2_DP0: + muxSrc = CLK_GET_MUX(CLK_SPDIF2_DP0_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF2_DP0_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF2_DP0_FRAC); + break; + + case CLK_SPDIF3: + muxSrc = CLK_GET_MUX(CLK_SPDIF3_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF3_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF3_FRAC); + break; + + case CLK_SPDIF4: + muxSrc = CLK_GET_MUX(CLK_SPDIF4_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF4_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF4_FRAC); + break; + + case CLK_SPDIF5_DP1: + muxSrc = CLK_GET_MUX(CLK_SPDIF5_DP1_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF5_DP1_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF5_DP1_FRAC); + break; + default: + + return HAL_INVAL; + } + + pRate = HAL_CRU_MuxGetFreq2(muxSrc, + s_gpllFreq / HAL_CRU_ClkGetDiv(divSrc), + s_aupllFreq / HAL_CRU_ClkGetDiv(divSrc)); + HAL_CRU_ClkGetFracDiv(divFrac, &n, &m); + rate = HAL_CRU_MuxGetFreq4(mux, pRate, pRate / m * n, + HAL_INVAL, PLL_INPUT_OSC_RATE / 2); + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): rate=%ld, mux=%ld, " + "prate0=%ld, prate1=%ld, prate2=%d, prate3=%d\n", + __func__, muxSrc, divSrc, mux, rate, HAL_CRU_ClkGetMux(mux), + pRate, pRate / m * n, HAL_INVAL, PLL_INPUT_OSC_RATE / 2); + + return rate; +} + +static HAL_Status HAL_CRU_ClkSetAudioFreq(eCLOCK_Name clockName, uint32_t rate) +{ + uint32_t muxSrc, mux = CLK_GET_MUX(clockName); + uint32_t divSrc, divFrac; + uint32_t gateId, fracGateId; + uint32_t n = 0, m = 0, maxDiv; + + switch (clockName) { + case CLK_I2S0_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S0_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S0_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S0_8CH_TX_FRAC); + gateId = CLK_I2S0_8CH_TX_GATE; + fracGateId = CLK_I2S0_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S0_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S0_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S0_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S0_8CH_RX_FRAC); + gateId = CLK_I2S0_8CH_RX_GATE; + fracGateId = CLK_I2S0_8CH_FRAC_RX_GATE; + break; + + case CLK_I2S1_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_TX_FRAC); + gateId = CLK_I2S1_8CH_TX_GATE; + fracGateId = CLK_I2S1_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S1_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S1_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S1_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S1_8CH_RX_FRAC); + gateId = CLK_I2S1_8CH_RX_GATE; + fracGateId = CLK_I2S1_8CH_FRAC_RX_GATE; + break; + + case CLK_I2S2_2CH: + muxSrc = CLK_GET_MUX(CLK_I2S2_2CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S2_2CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S2_2CH_FRAC); + gateId = CLK_I2S2_2CH_GATE; + fracGateId = CLK_I2S2_2CH_FRAC_GATE; + break; + + case CLK_I2S3_2CH: + muxSrc = CLK_GET_MUX(CLK_I2S3_2CH_SRC); + divSrc = CLK_GET_DIV(CLK_I2S3_2CH_SRC); + divFrac = CLK_GET_DIV(CLK_I2S3_2CH_FRAC); + gateId = CLK_I2S3_2CH_GATE; + fracGateId = CLK_I2S3_2CH_FRAC_GATE; + break; + + case CLK_I2S4_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S4_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S4_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S4_8CH_TX_FRAC); + gateId = CLK_I2S4_8CH_TX_GATE; + fracGateId = CLK_I2S4_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S5_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S5_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S5_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S5_8CH_TX_FRAC); + gateId = CLK_I2S5_8CH_TX_GATE; + fracGateId = CLK_I2S5_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S6_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S6_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S6_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S6_8CH_TX_FRAC); + gateId = CLK_I2S6_8CH_TX_GATE; + fracGateId = CLK_I2S6_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S6_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S6_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S6_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S6_8CH_RX_FRAC); + gateId = CLK_I2S6_8CH_RX_GATE; + fracGateId = CLK_I2S6_8CH_FRAC_RX_GATE; + break; + + case CLK_I2S7_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S7_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S7_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S7_8CH_RX_FRAC); + gateId = CLK_I2S7_8CH_RX_GATE; + fracGateId = CLK_I2S7_8CH_FRAC_RX_GATE; + break; + + case CLK_I2S8_8CH_TX: + muxSrc = CLK_GET_MUX(CLK_I2S8_8CH_TX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S8_8CH_TX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S8_8CH_TX_FRAC); + gateId = CLK_I2S8_8CH_TX_GATE; + fracGateId = CLK_I2S8_8CH_FRAC_TX_GATE; + break; + + case CLK_I2S9_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S9_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S9_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S9_8CH_RX_FRAC); + gateId = CLK_I2S9_8CH_RX_GATE; + fracGateId = CLK_I2S9_8CH_FRAC_RX_GATE; + break; + + case CLK_I2S10_8CH_RX: + muxSrc = CLK_GET_MUX(CLK_I2S10_8CH_RX_SRC); + divSrc = CLK_GET_DIV(CLK_I2S10_8CH_RX_SRC); + divFrac = CLK_GET_DIV(CLK_I2S10_8CH_RX_FRAC); + gateId = CLK_I2S10_8CH_RX_GATE; + fracGateId = CLK_I2S10_8CH_FRAC_RX_GATE; + break; + + case CLK_SPDIF0: + muxSrc = CLK_GET_MUX(CLK_SPDIF0_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF0_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF0_FRAC); + gateId = CLK_SPDIF0_GATE; + fracGateId = CLK_SPDIF0_FRAC_GATE; + break; + + case CLK_SPDIF1: + muxSrc = CLK_GET_MUX(CLK_SPDIF1_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF1_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF1_FRAC); + gateId = CLK_SPDIF1_GATE; + fracGateId = CLK_SPDIF1_FRAC_GATE; + break; + + case CLK_SPDIF2_DP0: + muxSrc = CLK_GET_MUX(CLK_SPDIF2_DP0_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF2_DP0_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF2_DP0_FRAC); + gateId = CLK_SPDIF2_DP0_GATE; + fracGateId = CLK_SPDIF2_DP0_FRAC_GATE; + break; + + case CLK_SPDIF3: + muxSrc = CLK_GET_MUX(CLK_SPDIF3_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF3_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF3_FRAC); + gateId = CLK_SPDIF3_GATE; + fracGateId = CLK_SPDIF3_FRAC_GATE; + break; + + case CLK_SPDIF4: + muxSrc = CLK_GET_MUX(CLK_SPDIF4_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF4_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF4_FRAC); + gateId = CLK_SPDIF4_GATE; + fracGateId = CLK_SPDIF4_FRAC_GATE; + break; + + case CLK_SPDIF5_DP1: + muxSrc = CLK_GET_MUX(CLK_SPDIF5_DP1_SRC); + divSrc = CLK_GET_DIV(CLK_SPDIF5_DP1_SRC); + divFrac = CLK_GET_DIV(CLK_SPDIF5_DP1_FRAC); + gateId = CLK_SPDIF5_DP1_GATE; + fracGateId = CLK_SPDIF5_DP1_FRAC_GATE; + break; + + default: + + return HAL_INVAL; + } + + maxDiv = CLK_DIV_GET_MAXDIV(divSrc); + + HAL_CRU_ClkEnable(gateId); + HAL_CRU_ClkEnable(fracGateId); + + if (PLL_INPUT_OSC_RATE / 2 == rate) { + HAL_CRU_ClkSetMux(mux, 3); + HAL_CRU_ClkDisable(fracGateId); + /* + * AUPLL is designed for audio, we will pre-calculate + * a common rate and set it for the most audio requirement. + * So AUPLL will not be changed like vop to change v0pll. + */ + } else if (DIV_NO_REM(s_aupllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_aupllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 1); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else if (DIV_NO_REM(s_gpllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetMux(mux, 0); + HAL_CRU_ClkDisable(fracGateId); + } else { + HAL_CRU_FracdivGetConfig(rate, s_gpllFreq, &n, &m); + HAL_CRU_ClkSetDiv(divSrc, 1); + HAL_CRU_ClkSetMux(muxSrc, 0); + HAL_CRU_ClkSetFracDiv(divFrac, n, m); + HAL_CRU_ClkSetMux(mux, 1); + HAL_CRU_ClkGetFracDiv(divFrac, &n, &m); + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): " + "rate=%ld, pRate=%ld, muxSrc=%ld, divSrc=%ld, mux=%ld, " + "maxdiv=%ld, n/m=%ld/%ld\n", + __func__, muxSrc, divSrc, mux, rate, + m ? (rate * m / n) : (rate * HAL_CRU_ClkGetDiv(divSrc)), + HAL_CRU_ClkGetMux(muxSrc), + HAL_CRU_ClkGetDiv(divSrc), HAL_CRU_ClkGetMux(mux), maxDiv, n, m); + + return HAL_OK; +} + +static uint32_t HAL_CRU_ClkGetVopFreq(eCLOCK_Name clockName) +{ + uint32_t mux = CLK_GET_MUX(clockName); + uint32_t muxSrc, divSrc; + uint32_t freq = HAL_INVAL; + uint32_t muxVal; + + switch (clockName) { + case DCLK_VOP0: + muxSrc = CLK_GET_MUX(DCLK_VOP0_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP0_SRC); + muxVal = HAL_CRU_ClkGetMux(mux); + break; + + case DCLK_VOP1: + muxSrc = CLK_GET_MUX(DCLK_VOP1_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP1_SRC); + muxVal = HAL_CRU_ClkGetMux(mux); + break; + + case DCLK_VOP2: + muxSrc = CLK_GET_MUX(DCLK_VOP2_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP2_SRC); + muxVal = HAL_CRU_ClkGetMux(mux); + break; + + case DCLK_VOP3: + muxSrc = CLK_GET_MUX(DCLK_VOP3); + divSrc = CLK_GET_DIV(DCLK_VOP3); + muxVal = 0; + break; + + default: + + return HAL_INVAL; + } + + if (muxVal == 0 && muxSrc && divSrc) { + freq = HAL_CRU_MuxGetFreq4(muxSrc, s_gpllFreq, s_cpllFreq, s_v0pllFreq, s_aupllFreq); + freq /= HAL_CRU_ClkGetDiv(divSrc); + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): srcMux=%ld, mux=%ld, " + "rate=%ld, div=%ld, prate0=%ld, prate1=%ld, prate2=%ld, prate3=%ld\n", + __func__, muxSrc, divSrc, muxVal, HAL_CRU_ClkGetMux(muxSrc), + HAL_CRU_ClkGetMux(mux), freq, HAL_CRU_ClkGetDiv(divSrc), + s_gpllFreq, s_cpllFreq, s_v0pllFreq, s_aupllFreq); + + return freq; +} + +static uint32_t HAL_CRU_ClkSetVopFreq(eCLOCK_Name clockName, uint32_t rate) +{ + /* vop2Pll[3] can be set as PLL_AUPLL, if the product doesn't use audio */ + uint32_t vop2Pll[] = { 0, 0, PLL_V0PLL, 0, }; + uint32_t mux = CLK_GET_MUX(clockName); + uint32_t muxSrc, divSrc; + uint32_t maxDiv, pllFreq; + uint32_t *pllTable = NULL; + uint32_t pllTableCnt = 0; + uint32_t curPll, i; + int best = -1; + + switch (clockName) { + case DCLK_VOP0: + muxSrc = CLK_GET_MUX(DCLK_VOP0_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP0_SRC); + break; + + case DCLK_VOP1: + muxSrc = CLK_GET_MUX(DCLK_VOP1_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP1_SRC); + break; + + case DCLK_VOP2: + muxSrc = CLK_GET_MUX(DCLK_VOP2_SRC); + divSrc = CLK_GET_DIV(DCLK_VOP2_SRC); + pllTable = vop2Pll; + pllTableCnt = HAL_ARRAY_SIZE(vop2Pll); + break; + + case DCLK_VOP3: + muxSrc = CLK_GET_MUX(DCLK_VOP3); + divSrc = CLK_GET_DIV(DCLK_VOP3); + break; + + default: + + return HAL_INVAL; + } + + maxDiv = CLK_DIV_GET_MAXDIV(divSrc); + + if (DIV_NO_REM(s_v0pllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_v0pllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 2); + if (muxSrc != mux) { + HAL_CRU_ClkSetMux(mux, 0); + } + } else if (DIV_NO_REM(s_gpllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_gpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 0); + if (muxSrc != mux) { + HAL_CRU_ClkSetMux(mux, 0); + } + } else if (DIV_NO_REM(s_cpllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_cpllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 1); + if (muxSrc != mux) { + HAL_CRU_ClkSetMux(mux, 0); + } + } else if (DIV_NO_REM(s_aupllFreq, rate, maxDiv)) { + HAL_CRU_ClkSetDiv(divSrc, s_aupllFreq / rate); + HAL_CRU_ClkSetMux(muxSrc, 3); + if (muxSrc != mux) { + HAL_CRU_ClkSetMux(mux, 0); + } + } else { + curPll = HAL_CRU_ClkGetMux(muxSrc); + for (i = 0; i < pllTableCnt; i++) { + if (pllTable[i]) { + best = i; + if (pllTable[i] == curPll) { + break; + } + } + } + + /* No PLL reserved for vop ? */ + if (best < 0) { + best = 0; + pllFreq = s_gpllFreq; + } else { + HAL_CRU_ClkSetFreq(pllTable[best], rate); + pllFreq = HAL_CRU_ClkGetFreq(pllTable[best]); + } + + HAL_CRU_ClkSetDiv(divSrc, HAL_DIV_ROUND_UP(pllFreq, rate)); + HAL_CRU_ClkSetMux(muxSrc, best); + if (muxSrc != mux) { + HAL_CRU_ClkSetMux(mux, 0); + } + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX) => (0x%08lX|0U): best=%d, " + "rate=%ld, pRate=%ld, muxSrc=%ld, divSrc=%ld, mux=%ld, maxdiv=%ld\n", + __func__, muxSrc, divSrc, mux, best, rate, + rate * HAL_CRU_ClkGetDiv(divSrc), HAL_CRU_ClkGetMux(muxSrc), + HAL_CRU_ClkGetDiv(divSrc), HAL_CRU_ClkGetMux(mux), maxDiv); + + return HAL_OK; +} + +static uint32_t HAL_CRU_ClkGetOtherFreq(eCLOCK_Name clockName) +{ + switch (clockName) { + case CLK_I2S0_8CH_TX: + case CLK_I2S0_8CH_RX: + case CLK_I2S1_8CH_TX: + case CLK_I2S1_8CH_RX: + case CLK_I2S2_2CH: + case CLK_I2S3_2CH: + case CLK_I2S4_8CH_TX: + case CLK_I2S5_8CH_TX: + case CLK_I2S6_8CH_TX: + case CLK_I2S6_8CH_RX: + case CLK_I2S7_8CH_RX: + case CLK_I2S8_8CH_TX: + case CLK_I2S9_8CH_RX: + case CLK_I2S10_8CH_RX: + case CLK_SPDIF0: + case CLK_SPDIF1: + case CLK_SPDIF2_DP0: + case CLK_SPDIF3: + case CLK_SPDIF4: + case CLK_SPDIF5_DP1: + + return HAL_CRU_ClkGetAudioFreq(clockName); + + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + case CLK_UART4: + case CLK_UART5: + case CLK_UART6: + case CLK_UART7: + case CLK_UART8: + case CLK_UART9: + + return HAL_CRU_ClkGetUartFreq(clockName); + + case DCLK_VOP0: + case DCLK_VOP1: + case DCLK_VOP2: + case DCLK_VOP3: + + return HAL_CRU_ClkGetVopFreq(clockName); + + default: + break; + } + + return HAL_INVAL; +} + +static HAL_Status HAL_CRU_ClkSetOtherFreq(eCLOCK_Name clockName, uint32_t rate) +{ + switch (clockName) { + case CLK_I2S0_8CH_TX: + case CLK_I2S0_8CH_RX: + case CLK_I2S1_8CH_TX: + case CLK_I2S1_8CH_RX: + case CLK_I2S2_2CH: + case CLK_I2S3_2CH: + case CLK_I2S4_8CH_TX: + case CLK_I2S5_8CH_TX: + case CLK_I2S6_8CH_TX: + case CLK_I2S6_8CH_RX: + case CLK_I2S7_8CH_RX: + case CLK_I2S8_8CH_TX: + case CLK_I2S9_8CH_RX: + case CLK_I2S10_8CH_RX: + case CLK_SPDIF0: + case CLK_SPDIF1: + case CLK_SPDIF2_DP0: + case CLK_SPDIF3: + case CLK_SPDIF4: + case CLK_SPDIF5_DP1: + + return HAL_CRU_ClkSetAudioFreq(clockName, rate); + + case CLK_UART0: + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + case CLK_UART4: + case CLK_UART5: + case CLK_UART6: + case CLK_UART7: + case CLK_UART8: + case CLK_UART9: + + return HAL_CRU_ClkSetUartFreq(clockName, rate); + + case DCLK_VOP0: + case DCLK_VOP1: + case DCLK_VOP2: + case DCLK_VOP3: + + return HAL_CRU_ClkSetVopFreq(clockName, rate); + + default: + break; + } + + return HAL_INVAL; +} + +static void CRU_InitPlls(void) +{ + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); + s_v0pllFreq = HAL_CRU_GetPllFreq(&V0PLL); + s_aupllFreq = HAL_CRU_GetPllFreq(&AUPLL); + s_ppllFreq = HAL_CRU_GetPllFreq(&PPLL); + s_lpllFreq = HAL_CRU_GetPllFreq(&LPLL); + s_npllFreq = HAL_CRU_GetPllFreq(&NPLL); + + HAL_CRU_DBG("%s: cpll=%ld, gpll=%ld, v0pll=%ld, aupll=%ld, ppll=%ld, lpll=%ld, npll=%ld\n", + __func__, s_cpllFreq, s_gpllFreq, s_v0pllFreq, s_aupllFreq, s_ppllFreq, s_lpllFreq, s_npllFreq); +} + +uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName) +{ + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t freq = 0; + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX)\n", __func__, clkMux, clkDiv); + HAL_CRU_DBG("%s: cpll=%ld, gpll=%ld, v0pll=%ld, aupll=%ld, ppll=%ld\n", + __func__, s_cpllFreq, s_gpllFreq, s_v0pllFreq, s_aupllFreq, s_ppllFreq); + + if (cru_suspend) { + return PLL_INPUT_OSC_RATE; + } + + if (!s_cpllFreq) { + CRU_InitPlls(); + } + + switch (clockName) { + case PLL_LPLL: + freq = HAL_CRU_GetPllFreq(&LPLL); + s_lpllFreq = freq; + + return freq; + + case PLL_B0PLL: + freq = HAL_CRU_GetPllFreq(&B0PLL); + + return freq; + + case PLL_B1PLL: + freq = HAL_CRU_GetPllFreq(&B1PLL); + + return freq; + + case PLL_CPLL: + freq = HAL_CRU_GetPllFreq(&CPLL); + s_cpllFreq = freq; + + return freq; + + case PLL_NPLL: + freq = HAL_CRU_GetPllFreq(&NPLL); + s_npllFreq = freq; + + return freq; + + case PLL_V0PLL: + freq = HAL_CRU_GetPllFreq(&V0PLL); + s_v0pllFreq = freq; + + return freq; + + case PLL_AUPLL: + freq = HAL_CRU_GetPllFreq(&AUPLL); + s_aupllFreq = freq; + + return freq; + + case PLL_PPLL: + freq = HAL_CRU_GetPllFreq(&PPLL); + s_ppllFreq = freq; + + return freq; + + case PLL_GPLL: + freq = HAL_CRU_GetPllFreq(&GPLL); + s_gpllFreq = freq; + + return freq; + + case CCLK_EMMC: + case SCLK_SFC: + case CCLK_SRC_SDIO: + freq = HAL_CRU_MuxGetFreq3(clkMux, s_gpllFreq, + s_cpllFreq, PLL_INPUT_OSC_RATE); + break; + + case BCLK_EMMC: + freq = HAL_CRU_MuxGetFreq2(clkMux, s_gpllFreq, s_cpllFreq); + break; + + case CLK_REF_PIPE_PHY0: + case CLK_REF_PIPE_PHY1: + case CLK_REF_PIPE_PHY2: + freq = HAL_CRU_MuxGetFreq2(clkMux, PLL_INPUT_OSC_RATE, s_ppllFreq); + if (freq == PLL_INPUT_OSC_RATE) { + clkDiv = 0; + } + break; + + case HCLK_VAD: + freq = HAL_CRU_MuxGetFreq4(clkMux, _MHZ(200), _MHZ(100), _MHZ(50), PLL_INPUT_OSC_RATE); + break; + + case MCLK_PDM0: + freq = HAL_CRU_MuxGetFreq2(clkMux, _MHZ(300), _MHZ(200)); + break; + + case HCLK_PMU_CM0: + freq = HAL_CRU_MuxGetFreq4(clkMux, _MHZ(400), _MHZ(200), _MHZ(100), PLL_INPUT_OSC_RATE); + break; + + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + case CLK_SPI4: + freq = HAL_CRU_MuxGetFreq3(clkMux, _MHZ(200), _MHZ(150), PLL_INPUT_OSC_RATE); + break; + + case CLK_PWM1: + case CLK_PWM2: + case CLK_PWM3: + freq = HAL_CRU_MuxGetFreq3(clkMux, _MHZ(100), _MHZ(50), PLL_INPUT_OSC_RATE); + break; + + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + case CLK_I2C8: + freq = HAL_CRU_MuxGetFreq2(clkMux, _MHZ(200), _MHZ(100)); + break; + + case CLK_GMAC_125M: + case CLK_GMAC_50M: + case REFCLKO25M_ETH0_OUT: + case REFCLKO25M_ETH1_OUT: + freq = HAL_CRU_MuxGetFreq2(clkMux, s_gpllFreq, s_cpllFreq); + break; + + default: + + return HAL_CRU_ClkGetOtherFreq(clockName); + } + + if (!clkMux && !clkDiv) { + return 0; + } + if (clkDiv) { + freq /= (HAL_CRU_ClkGetDiv(clkDiv)); + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX): freq: %ld=%ld/%ld\n", + __func__, clkMux, clkDiv, freq, freq * HAL_CRU_ClkGetDiv(clkDiv), + HAL_CRU_ClkGetDiv(clkDiv)); + + return freq; +} + +HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate) +{ + HAL_Status error = HAL_OK; + uint32_t clkMux = CLK_GET_MUX(clockName); + uint32_t clkDiv = CLK_GET_DIV(clockName); + uint32_t mux = 0, div = 1, pRate = 0; + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX): rate=%ld\n", __func__, clkMux, clkDiv, rate); + HAL_CRU_DBG("%s: cpll=%ld, gpll=%ld, v0pll=%ld, aupll=%ld, ppll=%ld\n", + __func__, s_cpllFreq, s_gpllFreq, s_v0pllFreq, s_aupllFreq, s_ppllFreq); + + if (cru_suspend) { + return HAL_OK; + } + + if (!s_cpllFreq) { + CRU_InitPlls(); + } + + switch (clockName) { + case PLL_LPLL: + error = HAL_CRU_SetPllFreq(&LPLL, rate); + s_lpllFreq = HAL_CRU_GetPllFreq(&LPLL); + + return error; + + case PLL_B0PLL: + error = HAL_CRU_SetPllFreq(&B0PLL, rate); + + return error; + + case PLL_B1PLL: + error = HAL_CRU_SetPllFreq(&B1PLL, rate); + + return error; + + case PLL_CPLL: + error = HAL_CRU_SetPllFreq(&CPLL, rate); + s_cpllFreq = HAL_CRU_GetPllFreq(&CPLL); + + return error; + + case PLL_PPLL: + error = HAL_CRU_SetPllFreq(&PPLL, rate); + s_ppllFreq = HAL_CRU_GetPllFreq(&PPLL); + + return error; + + case PLL_GPLL: + error = HAL_CRU_SetPllFreq(&GPLL, rate); + s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); + + return error; + + case PLL_NPLL: + error = HAL_CRU_SetPllFreq(&NPLL, rate); + s_npllFreq = HAL_CRU_GetPllFreq(&NPLL); + + return error; + + case PLL_AUPLL: + error = HAL_CRU_SetPllFreq(&AUPLL, rate); + s_aupllFreq = HAL_CRU_GetPllFreq(&AUPLL); + + return error; + + case PLL_V0PLL: + error = HAL_CRU_SetPllFreq(&V0PLL, rate); + s_v0pllFreq = HAL_CRU_GetPllFreq(&V0PLL); + + return error; + + case CLK_REF_PIPE_PHY0: + case CLK_REF_PIPE_PHY1: + case CLK_REF_PIPE_PHY2: + if (rate == PLL_INPUT_OSC_RATE) { + mux = 0; + pRate = PLL_INPUT_OSC_RATE; + } else { + mux = 1; + pRate = s_ppllFreq; + } + break; + + case HCLK_VAD: + mux = HAL_CRU_FreqGetMux4(rate, _MHZ(200), _MHZ(100), _MHZ(50), PLL_INPUT_OSC_RATE); + break; + + case MCLK_PDM0: + mux = HAL_CRU_FreqGetMux2(rate, _MHZ(300), _MHZ(200)); + break; + + case HCLK_PMU_CM0: + mux = HAL_CRU_FreqGetMux4(rate, _MHZ(400), _MHZ(200), _MHZ(100), PLL_INPUT_OSC_RATE); + break; + + case CCLK_EMMC: + case SCLK_SFC: + case CCLK_SRC_SDIO: + mux = HAL_CRU_RoundFreqGetMux3(rate, s_gpllFreq, s_cpllFreq, PLL_INPUT_OSC_RATE, &pRate); + break; + + case BCLK_EMMC: + mux = HAL_CRU_RoundFreqGetMux2(rate, s_gpllFreq, s_cpllFreq, &pRate); + break; + + case CLK_SPI0: + case CLK_SPI1: + case CLK_SPI2: + case CLK_SPI3: + case CLK_SPI4: + mux = HAL_CRU_FreqGetMux3(rate, _MHZ(200), _MHZ(150), PLL_INPUT_OSC_RATE); + break; + + case CLK_PWM1: + case CLK_PWM2: + case CLK_PWM3: + mux = HAL_CRU_FreqGetMux3(rate, _MHZ(100), _MHZ(50), PLL_INPUT_OSC_RATE); + break; + + case CLK_I2C0: + case CLK_I2C1: + case CLK_I2C2: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + case CLK_I2C6: + case CLK_I2C7: + case CLK_I2C8: + mux = HAL_CRU_FreqGetMux2(rate, _MHZ(200), _MHZ(100)); + break; + + case CLK_GMAC_125M: + case CLK_GMAC_50M: + case REFCLKO25M_ETH0_OUT: + case REFCLKO25M_ETH1_OUT: + mux = HAL_CRU_RoundFreqGetMux2(rate, s_gpllFreq, s_cpllFreq, &pRate); + break; + + default: + + return HAL_CRU_ClkSetOtherFreq(clockName, rate); + } + + if (!clkMux && !clkDiv) { + return HAL_INVAL; + } + + if (pRate) { + div = HAL_DIV_ROUND_UP(pRate, rate); + } + if (clkDiv) { + div = (div > CLK_DIV_GET_MAXDIV(clkDiv) ? + CLK_DIV_GET_MAXDIV(clkDiv) : (div)); + HAL_CRU_ClkSetDiv(clkDiv, div); + } + if (clkMux) { + HAL_CRU_ClkSetMux(clkMux, mux); + } + + HAL_CRU_DBG("%s: (0x%08lX|0x%08lX): mux=%ld, rate=%ld, pRate=%ld, div=%ld, maxdiv=%d\n", + __func__, clkMux, clkDiv, mux, rate, pRate, div, CLK_DIV_GET_MAXDIV(clkDiv)); + + return HAL_OK; +} + +static uint32_t clk_matrix_300m_src_div; +static uint32_t clk_matrix_pmu1_300m_src_div; +static uint32_t clk_matrix_400m_src_div; +static uint32_t clk_matrix_pmu1_400m_src_div; +static uint32_t clk_matrix_pmu1_200m_src_div; +static uint32_t hclk_pmu1_root_i_sel; + +HAL_Status HAL_CRU_Suspend(void) +{ + /* + * After ATF system suspend, the system clock rate is 24M. + * Set divider 1:1 to be 24M rate for some modules. + */ + clk_matrix_300m_src_div = HAL_CRU_ClkGetDiv(CLK_MATRIX_300M_SRC_DIV); + clk_matrix_pmu1_300m_src_div = HAL_CRU_ClkGetDiv(CLK_MATRIX_PMU1_300M_SRC_DIV); + clk_matrix_400m_src_div = HAL_CRU_ClkGetDiv(CLK_MATRIX_400M_SRC_DIV); + clk_matrix_pmu1_400m_src_div = HAL_CRU_ClkGetDiv(CLK_MATRIX_PMU1_400M_SRC_DIV); + clk_matrix_pmu1_200m_src_div = HAL_CRU_ClkGetDiv(CLK_MATRIX_PMU1_200M_SRC_DIV); + hclk_pmu1_root_i_sel = HAL_CRU_ClkGetMux(HCLK_PMU1_ROOT_I_SEL); + + /* clk_mclk_pdm0 div 1:1 */ + HAL_CRU_ClkSetDiv(CLK_MATRIX_300M_SRC_DIV, 1); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_300M_SRC_DIV, 1); + HAL_CRU_ClkSetDiv(CLK_MATRIX_400M_SRC_DIV, 1); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_400M_SRC_DIV, 1); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_200M_SRC_DIV, 1); + /* hclk_vad div 1:1 */ + HAL_CRU_ClkSetMux(HCLK_PMU1_ROOT_I_SEL, 3); + + cru_suspend = 1; + + return HAL_OK; +} + +HAL_Status HAL_CRU_Resume(void) +{ + /* clk_mclk_pdm0 */ + HAL_CRU_ClkSetDiv(CLK_MATRIX_300M_SRC_DIV, clk_matrix_300m_src_div); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_300M_SRC_DIV, clk_matrix_pmu1_300m_src_div); + HAL_CRU_ClkSetDiv(CLK_MATRIX_400M_SRC_DIV, clk_matrix_400m_src_div); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_400M_SRC_DIV, clk_matrix_pmu1_400m_src_div); + HAL_CRU_ClkSetDiv(CLK_MATRIX_PMU1_200M_SRC_DIV, clk_matrix_pmu1_200m_src_div); + /* hclk_vad */ + HAL_CRU_ClkSetMux(HCLK_PMU1_ROOT_I_SEL, hclk_pmu1_root_i_sel); + + cru_suspend = 0; + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* SOC_RK3588 && HAL_CRU_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_debug.h b/demos/rk3588/bsp/hal/hal_debug.h new file mode 100755 index 00000000..1a95c01f --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_debug.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DEBUG_H_ +#define _HAL_DEBUG_H_ +#include "prt_typedef.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup DEBUG + * @{ + */ + +/***************************** MACRO Definition ******************************/ + +/* Run only for debugging, please refer to how-to-use for the definition of the specification. */ + +/** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef HAL_SYSLOG +// #define HAL_SYSLOG HAL_DBG_Printf +#define HAL_SYSLOG PRT_Printf +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_INFO_ON) +#define HAL_DBG(fmt, arg...) HAL_SYSLOG("[HAL INFO] " fmt, ##arg) +#else +#define HAL_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL INFO] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_WRN_ON) +#define HAL_DBG_WRN(fmt, arg...) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg) +#else +#define HAL_DBG_WRN(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_DBG_ERR_ON) +#define HAL_DBG_ERR(fmt, arg...) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg) +#else +#define HAL_DBG_ERR(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg); } while (0) +#endif + +#if defined(HAL_DBG_ON) && defined(HAL_ASSERT_ON) +#define HAL_ASSERT(expr) \ + do { \ + if (!(expr)) \ + HAL_AssertFailed((const char *)__FILE__, __LINE__); \ + } while (0) +#else +#define HAL_ASSERT(expr) +#endif + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup DEBUG_Public_Function_Declare Public Function Declare + * @{ + */ + +void HAL_AssertFailed(const char *file, uint32_t line); +HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len); +#ifdef __GNUC__ +__attribute__((__format__(printf, 1, 2))) +#endif +int32_t HAL_DBG_Printf(const char *format, ...); +U32 PRT_Printf(const char *format, ...); +/** @} */ + +#endif + +/** @} */ + +/** @} */ + diff --git a/demos/rk3588/bsp/hal/hal_def.h b/demos/rk3588/bsp/hal/hal_def.h new file mode 100755 index 00000000..6bdfc271 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_def.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_DEF + * @{ + */ + +#ifndef _HAL_DEF_H_ +#define _HAL_DEF_H_ + +#include +#include +#include +#include +#include +#include + +#include "cmsis_compiler.h" +#include "soc.h" +#include "hal_list.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) /**< Set 1 to the register specific bit field */ +#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specific bits filed from the register */ +#define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value of a specific bits field from the register */ +#define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) /**< Write 0 to the register */ +#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) /**< Write the register */ +#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) /**< Read the register */ +#define MODIFY_REG(REG, CLEARMASK, SETMASK) \ + WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) /**< Clear and set the value of a specific bits field from the register */ +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#if defined(__GNUC__) || defined(__CC_ARM) +#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16)) +#else +#define MASK_TO_WE(msk) ((msk) << 16) +#endif +#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) +#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) + +/* Misc OPS Marco */ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define RESET 0 +#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check if the the specific bits filed from the register is valid */ +#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check if the the specific bits filed from the register is isvalid */ + +#define HAL_BIT(nr) (1UL << (nr)) +#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) +#define HAL_MAX(x, y) ((x) > (y) ? (x) : (y)) +#define HAL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) + +#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) +#ifdef CACHE_LINE_SIZE +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE) +#else +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4) +#endif + +/* Compiller Macro */ +#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__) +#define HAL_UNUSED __attribute__((__unused__)) +#else +#define HAL_UNUSED +#endif + +#ifdef CACHE_LINE_SIZE +#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE) +#else +#define HAL_CACHELINE_ALIGNED +#endif + +#ifdef HAL_SRAM_SECTION_ENABLED +#define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code"))) +#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata"))) +#define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data"))) +#define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss"))) +#else +#define HAL_SECTION_SRAM_CODE +#define HAL_SECTION_SRAM_RODATA +#define HAL_SECTION_SRAM_DATA +#define HAL_SECTION_SRAM_BSS +#endif + +#ifdef HAL_PSRAM_SECTION_ENABLED +#define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code"))) +#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata"))) +#define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data"))) +#define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss"))) +#else +#define HAL_SECTION_PSRAM_CODE +#define HAL_SECTION_PSRAM_RODATA +#define HAL_SECTION_PSRAM_DATA +#define HAL_SECTION_PSRAM_BSS +#endif + +#ifdef HAL_XIP_SECTION_ENABLED +#define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code"))) +#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata"))) +#else +#define HAL_SECTION_XIP_CODE +#define HAL_SECTION_XIP_RODATA +#endif + +#define HAL_GENMASK(h, l) (((~0U) << (l)) & (~0U >> (32 - 1 - (h)))) +#define HAL_GENVAL(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) >> (l))) +#define HAL_GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) +#define HAL_GENVAL_ULL(x, h, l) ((uint64_t)(((x) & HAL_GENMASK_ULL(h, l)) >> (l))) + +/** MCU systick clock source */ +typedef enum { + HAL_SYSTICK_CLKSRC_CORE, + HAL_SYSTICK_CLKSRC_EXT +} eHAL_systickClkSource; + +/** Check if is MCU systick clock source */ +#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT)) + +/***************************** Structure Definition **************************/ +/** HAL boolean type definition */ +typedef enum { + HAL_FALSE = 0x00U, + HAL_TRUE = 0x01U +} HAL_Check; + +/** HAL error code definition */ +typedef enum { + HAL_OK = 0x00U, + HAL_ERROR = (-1), + HAL_BUSY = (-16), + HAL_NODEV = (-19), + HAL_INVAL = (-22), + HAL_NOSYS = (-38), + HAL_TIMEOUT = (-110) +} HAL_Status; + +/** HAL functional status definition */ +typedef enum { + HAL_DISABLE = 0x00U, + HAL_ENABLE = 0x01U +} HAL_FuncStatus; + +/** HAL lock structures definition */ +typedef enum { + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockStatus; + +/** RK GPIO bank definition */ +typedef enum { +#ifdef GPIO0 + GPIO_BANK0 = 0, +#endif +#ifdef GPIO1 + GPIO_BANK1 = 1, +#endif +#ifdef GPIO2 + GPIO_BANK2 = 2, +#endif +#ifdef GPIO3 + GPIO_BANK3 = 3, +#endif +#ifdef GPIO4 + GPIO_BANK4 = 4, +#endif +#ifdef GPIO0_EXP + GPIO_BANK0_EXP = 5, +#endif +#ifdef GPIO1_EXP + GPIO_BANK1_EXP = 6, +#endif +#ifdef GPIO2_EXP + GPIO_BANK2_EXP = 7, +#endif +#ifdef GPIO3_EXP + GPIO_BANK3_EXP = 8, +#endif +#ifdef GPIO4_EXP + GPIO_BANK4_EXP = 9, +#endif + GPIO_BANK_NUM +} eGPIO_bankId; + +/** HAL function type definition */ +typedef void (*pFunc)(void); + +/** @} */ +/***************************** Function Declare ******************************/ + +#endif + +/** @} */ + +/** @} */ diff --git a/demos/rk3588/bsp/hal/hal_driver.h b/demos/rk3588/bsp/hal/hal_driver.h new file mode 100755 index 00000000..78157fe1 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_driver.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DRIVER_H_ +#define _HAL_DRIVER_H_ + +// #include "hal_pm.h" + +#ifdef HAL_ACDCDIG_MODULE_ENABLED +#include "hal_acdcdig.h" +#endif + +#ifdef HAL_ACODEC_MODULE_ENABLED +#include "hal_acodec.h" +#endif + +#ifdef HAL_ARCHTIMER_MODULE_ENABLED +#include "hal_archtimer.h" +#endif + +#ifdef HAL_AUDIOPWM_MODULE_ENABLED +#include "hal_audiopwm.h" +#endif + +// #include "hal_cache.h" + +#ifdef HAL_BUFMGR_MODULE_ENABLED +#include "hal_bufmgr.h" +#endif + +#ifdef HAL_CANFD_MODULE_ENABLED +#include "hal_canfd.h" +#endif + +#ifdef HAL_CKCAL_MODULE_ENABLED +#include "hal_ckcal.h" +#endif + +#ifdef HAL_CACHE_ECC_MODULE_ENABLED +#include "hal_cache_ecc.h" +#endif + +#ifdef HAL_CPU_TOPOLOGY_MODULE_ENABLED +#include "hal_cpu_topology.h" +#endif + +#ifdef HAL_CRU_MODULE_ENABLED +#include "hal_cru.h" +#endif + +#ifdef HAL_CRYPTO_MODULE_ENABLED +#include "hal_crypto.h" +#endif + +#ifdef HAL_DSI_MODULE_ENABLED +#include "hal_display.h" +#include "hal_dsi.h" +#endif + +#ifdef HAL_DEMO_MODULE_ENABLED +#include "hal_demo.h" +#endif + +#ifdef HAL_DDR_ECC_MODULE_ENABLED +#include "hal_ddr_ecc.h" +#endif + +#ifdef HAL_DSP_MODULE_ENABLED +#include "hal_dsp.h" +#endif + +// #include "hal_dma.h" + +#ifdef HAL_DWDMA_MODULE_ENABLED +#include "hal_dwdma.h" +#endif + +#ifdef HAL_EFUSE_MODULE_ENABLED +#include "hal_efuse.h" +#endif + +#ifdef HAL_GMAC_MODULE_ENABLED +#include "hal_gmac.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "hal_gpio.h" +#endif + +#ifdef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED +#include "hal_gpio_irq_group.h" +#endif + +#ifdef HAL_PINCTRL_MODULE_ENABLED +#include "hal_pinctrl.h" +#endif + +#if defined(HAL_HCD_MODULE_ENABLED) || defined(HAL_PCD_MODULE_ENABLED) +#include "hal_usb_core.h" +#include "hal_usb_phy.h" +#endif + +#if defined(HAL_EHCI_MODULE_ENABLED) || defined(HAL_OHCI_MODULE_ENABLED) +#include "hal_usbh.h" +#endif + +#ifdef HAL_HCD_MODULE_ENABLED +#include "hal_hcd.h" +#endif + +#ifdef HAL_HWSPINLOCK_MODULE_ENABLED +#include "hal_hwspinlock.h" +#endif + +#ifdef HAL_HYPERPSRAM_MODULE_ENABLED +#include "hal_hyperpsram.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +#include "hal_i2c.h" +#endif + +#ifdef HAL_I2S_MODULE_ENABLED +#include "hal_i2s.h" +#endif + +#ifdef HAL_I2STDM_MODULE_ENABLED +#include "hal_i2stdm.h" +#endif + +#ifdef HAL_INTC_MODULE_ENABLED +#include "hal_intc.h" +#endif + +#ifdef HAL_IRQ_HANDLER_MODULE_ENABLED +#include "hal_irq_handler.h" +#endif + +#ifdef HAL_GIC_MODULE_ENABLED +#include "hal_gic.h" +#endif + +#ifdef HAL_MBOX_MODULE_ENABLED +#include "hal_mbox.h" +#endif + +#ifdef HAL_NVIC_MODULE_ENABLED +#include "hal_nvic.h" +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +#include "hal_pcd.h" +#endif + +#ifdef HAL_PCIE_MODULE_ENABLED +#include "hal_pcie_dma.h" +#include "hal_pcie.h" +#endif + +#ifdef HAL_PDM_MODULE_ENABLED +#include "hal_pdm.h" +#endif + +#ifdef HAL_PL330_MODULE_ENABLED +#include "hal_pl330.h" +#endif + +#ifdef HAL_PMU_MODULE_ENABLED +#include "hal_pd.h" +#endif + +#ifdef HAL_PVTM_MODULE_ENABLED +#include "hal_pvtm.h" +#endif + +#ifdef HAL_PWM_MODULE_ENABLED +#include "hal_pwm.h" +#endif + +// #include "hal_pwr.h" + +#ifdef HAL_RISCVIC_MODULE_ENABLED +#include "hal_riscvic.h" +#endif + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "hal_sdio.h" +#endif + +#ifdef HAL_SNOR_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_snor.h" +#endif + +#ifdef HAL_SFC_MODULE_ENABLED +#include "hal_sfc.h" +#endif + +#ifdef HAL_SPINAND_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_spinand.h" +#endif + +#ifdef HAL_SPINLOCK_MODULE_ENABLED +#include "hal_spinlock.h" +#endif + +#ifdef HAL_SYSTICK_MODULE_ENABLED +#include "hal_systick.h" +#endif + +#ifdef HAL_FSPI_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_fspi.h" +#endif + +#ifdef HAL_QPIPSRAM_MODULE_ENABLED +#include "hal_spi_mem.h" +#include "hal_qpipsram.h" +#endif + +#ifdef HAL_TOUCHKEY_MODULE_ENABLED +#include "hal_touchkey.h" +#endif + +#ifdef HAL_TSADC_MODULE_ENABLED +#include "hal_tsadc.h" +#endif + +#ifdef HAL_SARADC_MODULE_ENABLED +#include "hal_saradc.h" +#endif + +#ifdef HAL_SMCCC_MODULE_ENABLED +#include "hal_smccc.h" +#endif + +#ifdef HAL_KEYCTRL_MODULE_ENABLED +#include "hal_keyctrl.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +#include "hal_spi.h" +#endif + +#ifdef HAL_SPI2APB_MODULE_ENABLED +#include "hal_spi2apb.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED +#include "hal_timer.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED +#include "hal_uart.h" +#endif + +#ifdef HAL_VAD_MODULE_ENABLED +#include "hal_vad.h" +#endif + +#ifdef HAL_VICAP_MODULE_ENABLED +#include "hal_vicap.h" +#endif + +#ifdef HAL_VOP_MODULE_ENABLED +#include "hal_display.h" +#include "hal_vop.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED +#include "hal_wdt.h" +#endif + +#endif diff --git a/demos/rk3588/bsp/hal/hal_gpio.c b/demos/rk3588/bsp/hal/hal_gpio.c new file mode 100755 index 00000000..58385d10 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_gpio.c @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_GPIO_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_How_To_Use How To Use + * @{ + + The GPIO driver can be used as follows: + + APIs for GPIO io read write: + + 1. HAL_GPIO_GetPinLevel() to get EXT port level. + 2. HAL_GPIO_SetPinLevel() to set io level. + 3. HAL_GPIO_SetPinDirection() to set io direction. + + APIs for GPIO IRQ: + + 1. HAL_GPIO_EnableIRQ() to enable a GPIO IRQ. + 2. HAL_GPIO_DisableIRQ() to disable a GPIO IRQ. + 3. HAL_GPIO_IRQHandler() to handle GPIO IRQ isr. + 4. HAL_GPIO_IRQDispatch() to dispatch GPIO IRQ, should be implemented by User. + + Please open the macro definition HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED to support + + APIs for GPIO virtual model: + + 1. HAL_GPIO_EnableVirtualModel() to enable a GPIO virtual model. + 2. HAL_GPIO_DisableVirtualModel() to disable a GPIO virtual model. + 3. HAL_GPIO_SetVirtualModel() to configure GPIO pins virtual model. + + @} */ + +/** @defgroup GPIO_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Set the GPIO IRQ end of interrupt(EOI). + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->PORT_EOI_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; + pGPIO->PORT_EOI_L = pin | (pin << 16); + } +#else + { + pGPIO->PORTA_EOI = pin; + } +#endif +} + +/** + * @brief Get GPIO all pins irq type. + * @param pGPIO: the GPIO struct. + * @return uint32_t: type value. + */ +static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO) +{ + uint32_t type; + +#if (GPIO_VER_ID == 0x01000C2BU) + type = (pGPIO->INT_TYPE_L & 0xffff); + type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16); + type |= (pGPIO->INT_BOTHEDGE_L & 0xffff); + type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16); +#else + type = pGPIO->INTTYPE_LEVEL; + #ifdef GPIO_INT_BOTHEDGE_OFFSET + type |= pGPIO->INT_BOTHEDGE; + #endif +#endif + + return type; +} + +/** + * @brief Get GPIO all pins irq status. + * @param pGPIO: the GPIO struct. + * @return uint32_t: status value. + */ +static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO) +{ + return pGPIO->INT_STATUS; +} + +/** @} */ +/********************* Public Function Definition ***************************/ + +/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions + + This section provides functions allowing to get the status of the module: + + * @{ + */ + +/** + * @brief GPIO Configure IRQ trigger type. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param mode: The value defined in @ref eGPIO_intType. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode) +{ + uint32_t both = 0, type = 0, plar = 0; + + UNUSED(both); + + switch (mode) { + case GPIO_INT_TYPE_EDGE_RISING: + type = 1; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_FALLING: + type = 1; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_HIGH: + type = 0; + plar = 1; + both = 0; + break; + case GPIO_INT_TYPE_LEVEL_LOW: + type = 0; + plar = 0; + both = 0; + break; + case GPIO_INT_TYPE_EDGE_BOTH: + type = 0; + plar = 0; + both = 1; + break; + default: + + return HAL_INVAL; + } + +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin); + pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16); + pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16); + } +#else + { + pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin)); + pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin)); + #ifdef GPIO_INT_BOTHEDGE_OFFSET + pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin)); + #endif + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: direction value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16); + } +#else + if (direction == GPIO_OUT) { + pGPIO->SWPORTA_DDR |= pin; + } else { + pGPIO->SWPORTA_DDR &= ~pin; + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO direction. + * @param pGPIO: the GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param direction: value defined in @ref eGPIO_pinDirection. + * @return HAL_Status: HAL_OK if success. + */ +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Get GPIO Pin data direction value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinDirection: data direction value. + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinDirection direction; + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin); +#else + value = pGPIO->SWPORTA_DDR & pin; +#endif + + if (value != (uint32_t)GPIO_IN) { + direction = GPIO_OUT; + } else { + direction = GPIO_IN; + } + + return direction; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin); + } else { + pin &= 0x0000FFFF; + pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16); + } +#else + if (level == GPIO_HIGH) { + pGPIO->SWPORTA_DR |= pin; + } else { + pGPIO->SWPORTA_DR &= ~pin; + } +#endif + + return HAL_OK; +} + +/** + * @brief Set GPIO pin level. + * @param pGPIO: The pointer of GPIO struct. + * @param mPins: The pins defined in @ref ePINCTRL_GPIO_PINS. + * @param level: The level defined in @ref eGPIO_pinLevel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO)); + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Get GPIO Pin data value. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval eGPIO_pinLevel: data value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + eGPIO_pinLevel level; + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin); +#else + value = pGPIO->SWPORTA_DR & pin; +#endif + + if (value != (uint32_t)GPIO_LOW) { + level = GPIO_HIGH; + } else { + level = GPIO_LOW; + } + + return level; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @retval GPIO_PinState: ext bank value. + */ +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = (pGPIO->EXT_PORT & pin); +#else + value = (pGPIO->EXT_PORTA & pin); +#endif + + return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH; +} + +/** + * @brief Get GPIO Pin ext bank level. + * @param pGPIO: the GPIO struct. + * @retval uint32_t: ext bank value. + */ +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO) +{ + uint32_t value; + +#if (GPIO_VER_ID == 0x01000C2BU) + value = (pGPIO->EXT_PORT); +#else + value = (pGPIO->EXT_PORTA); +#endif + + return value; +} +/** @} */ + +/** @defgroup GPIO_Exported_Functions_Group3 Other Functions + * @{ + */ + +/** + * @brief Set GPIO irq enable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin; +#endif + pGPIO->INT_EN_H = pin | (pin >> 16); + } else { + pin &= 0x0000FFFF; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin << 16; +#endif + pGPIO->INT_EN_L = pin | (pin << 16); + } +#else + { + pGPIO->INTEN |= pin; + pGPIO->INTMASK &= ~pin; + } +#endif +} + +/** + * @brief Set GPIO irq disable. + * @param pGPIO: The pointer of GPIO struct. + * @param pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + */ +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + if (IS_GPIO_HIGH_PIN(pin)) { + pin &= 0xFFFF0000; + pGPIO->INT_EN_H = pin; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_H = pin | (pin >> 16); +#endif + } else { + pin &= 0x0000FFFF; + pGPIO->INT_EN_L = pin << 16; +#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED + pGPIO->INT_MASK_L = pin | (pin << 16); +#endif + } +#else + { + pGPIO->INTEN &= ~pin; + pGPIO->INTMASK |= pin; + } +#endif +} + +/** + * @brief GPIO IRQ callbacks. + * @param bank: The bank id. + * @param pin: The true pin index, 0~31. + * NOTE: This function Should not be modified, when the callback is needed, + * the HAL_GPIO_IRQDispatch could be implemented in the user file. + */ +__WEAK void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin) +{ + UNUSED(bank); + UNUSED(pin); +} + +/** + * @brief GPIO IRQ hanlder. + * @param pGPIO: The pointer of GPIO struct. + * @param bank: The bank id. + */ +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank) +{ + uint32_t stat, type, clear; + uint32_t i; + uint32_t pin; + + stat = GPIO_GetIntStatus(pGPIO); + type = GPIO_GetIntType(pGPIO); + + /* Then process each pending GPIO interrupt */ + for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) { + clear = 0x1U << i; + pin = HAL_BIT(i); + + if ((stat & clear) != 0x0U) { + /* If gpio is Edge-sensitive triggered, clear eoi */ + if (type & clear) { + GPIO_SetEOI(pGPIO, pin); + } + + /* Remove the pending interrupt bit from the clear */ + stat &= ~clear; + + /* And disptach the GPIO interrupt to the handler */ + HAL_GPIO_IRQDispatch(bank, i); + } + } +} + +#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED + +/** + * @brief GPIO virtual model enable. + * @param pGPIO: The pointer of GPIO struct. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + pGPIO->GPIO_VIRTUAL_EN = 0x10001; + + return HAL_OK; +#endif + + return HAL_ERROR; +} + +/** + * @brief GPIO virtual model disable. + * @param pGPIO: The pointer of GPIO struct. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + pGPIO->GPIO_VIRTUAL_EN = 0x10000; + + return HAL_OK; +#endif + + return HAL_ERROR; +} + +/** + * @brief GPIO Configure pins for virtual model. + * @param pGPIO: The pointer of GPIO struct. + * @param pins: The pin bit defined in @ref ePINCTRL_GPIO_PINS. + * @param vmode: The value defined in @ref eGPIO_VirtualModel. + * @return HAL_Status. + */ +HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel) +{ +#if (GPIO_VER_ID == 0x01000C2BU) + uint32_t low_pins, high_pins; + + low_pins = pin & 0x0000ffff; + high_pins = (pin & 0xffff0000) >> 16; + + /* Support OS_A and OS_B */ + if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) { + pGPIO->GPIO_REG_GROUP_L = low_pins << 16; + pGPIO->GPIO_REG_GROUP_H = high_pins << 16; + } else { + pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16); + pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16); + } + + return HAL_OK; +#endif + + return HAL_ERROR; +} + +#endif /* HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED */ + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_gpio.h b/demos/rk3588/bsp/hal/hal_gpio.h new file mode 100755 index 00000000..ec0a0a39 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_gpio.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +#include "hal_def.h" +#include "hal_pinctrl.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup GPIO_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#ifndef GPIO_VER_ID +#define GPIO_VER_ID (0U) +#endif + +#define PIN_NUMBER_PER_BANK (32) + +#define GPIO_PIN_SHIFT (0) /**< Bits 0-4: GPIO Pin number: 0 - 31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +#define GPIO_BANK_SHIFT (5) /**< Bits 5-7: GPIO Port number: 0 - 7 */ +#define GPIO_BANK_MASK (0x7 << GPIO_BANK_SHIFT) + +#define BANK_PIN(BANK, PIN) ((((BANK) << GPIO_BANK_SHIFT) & GPIO_BANK_MASK) + (((PIN) << GPIO_PIN_SHIFT) & GPIO_PIN_MASK)) + +/***************************** Structure Definition **************************/ +/** GPIO pin level definition */ +typedef enum { + GPIO_LOW, + GPIO_HIGH +} eGPIO_pinLevel; + +/** GPIO pin direction definition */ +typedef enum { + GPIO_IN, + GPIO_OUT +} eGPIO_pinDirection; + +/** GPIO pin debounce definition */ +typedef enum { + GPIO_DEBOUNCE_DIS, + GPIO_DEBOUNCE_EN +} eGPIO_pinDebounce; + +/** GPIO pin interrupt enable definition */ +typedef enum { + GPIO_INT_DISABLE, + GPIO_INT_ENABLE +} eGPIO_intEnable; + +/** GPIO pin interrupt type definition */ +typedef enum { + GPIO_INT_TYPE_NONE = 0x00000000, + GPIO_INT_TYPE_EDGE_RISING = 0x00000001, + GPIO_INT_TYPE_EDGE_FALLING = 0x00000002, + GPIO_INT_TYPE_EDGE_BOTH = (GPIO_INT_TYPE_EDGE_FALLING | GPIO_INT_TYPE_EDGE_RISING), + GPIO_INT_TYPE_LEVEL_HIGH = 0x00000004, + GPIO_INT_TYPE_LEVEL_LOW = 0x00000008, + GPIO_INT_TYPE_LEVEL_MASK = (GPIO_INT_TYPE_LEVEL_LOW | GPIO_INT_TYPE_LEVEL_HIGH), + GPIO_INT_TYPE_SENSE_MASK = 0x0000000f, + GPIO_INT_TYPE_DEFAULT = GPIO_INT_TYPE_SENSE_MASK, +} eGPIO_intType; + +/** GPIO pin interrupt mode definition */ +typedef enum { + GPIO_INT_MODE_EDGE_RISING, + GPIO_INT_MODE_EDGE_FALLING, + GPIO_INT_MODE_EDGE_RISING_FALLING, + GPIO_INT_MODE_LEVEL_HIGH, + GPIO_INT_MODE_LEVEL_LOW, + GPIO_INT_MODE_INVALID +} eGPIO_intMode; + +/** GPIO pin virtual model definition */ +typedef enum { + GPIO_VIRTUAL_MODEL_OS_A, + GPIO_VIRTUAL_MODEL_OS_B, + GPIO_VIRTUAL_MODEL_OS_C, + GPIO_VIRTUAL_MODEL_OS_D, +} eGPIO_VirtualModel; + +#define IS_GPIO_PIN_DIR(ACTION) (((ACTION) == GPIO_IN) || ((ACTION) == GPIO_OUT)) +#define IS_GPIO_PIN_LEVEL(ACTION) (((ACTION) == GPIO_LOW) || ((ACTION) == GPIO_HIGH)) + +#define IS_GPIO_PIN(PIN) ((PIN) != 0x00000000U) +#define IS_GPIO_HIGH_PIN(PIN) IS_GPIO_PIN(((PIN) & 0xFFFF0000U)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_A0) || \ + ((PIN) == GPIO_PIN_A1) || \ + ((PIN) == GPIO_PIN_A2) || \ + ((PIN) == GPIO_PIN_A3) || \ + ((PIN) == GPIO_PIN_A4) || \ + ((PIN) == GPIO_PIN_A5) || \ + ((PIN) == GPIO_PIN_A6) || \ + ((PIN) == GPIO_PIN_A7) || \ + ((PIN) == GPIO_PIN_B0) || \ + ((PIN) == GPIO_PIN_B1) || \ + ((PIN) == GPIO_PIN_B2) || \ + ((PIN) == GPIO_PIN_B3) || \ + ((PIN) == GPIO_PIN_B4) || \ + ((PIN) == GPIO_PIN_B5) || \ + ((PIN) == GPIO_PIN_B6) || \ + ((PIN) == GPIO_PIN_B7) || \ + ((PIN) == GPIO_PIN_C0) || \ + ((PIN) == GPIO_PIN_C1) || \ + ((PIN) == GPIO_PIN_C2) || \ + ((PIN) == GPIO_PIN_C3) || \ + ((PIN) == GPIO_PIN_C4) || \ + ((PIN) == GPIO_PIN_C5) || \ + ((PIN) == GPIO_PIN_C6) || \ + ((PIN) == GPIO_PIN_C7) || \ + ((PIN) == GPIO_PIN_D0) || \ + ((PIN) == GPIO_PIN_D1) || \ + ((PIN) == GPIO_PIN_D2) || \ + ((PIN) == GPIO_PIN_D3) || \ + ((PIN) == GPIO_PIN_D4) || \ + ((PIN) == GPIO_PIN_D5) || \ + ((PIN) == GPIO_PIN_D6) || \ + ((PIN) == GPIO_PIN_D7)) + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup GPIO_Exported_Definition_Group2 Public Functions Declare. + * @{ + */ +eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO); + +HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction); +HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode); + +HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level); +HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction); + +void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin); +void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank); + +#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED +HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO); +HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO); +HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel); +#endif + +/* The parameter pin for this function is special, it's 0~31. */ +void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin); + +/** @} */ + +#endif +/** @} */ + +/** @} */ diff --git a/demos/rk3588/bsp/hal/hal_i2c.c b/demos/rk3588/bsp/hal/hal_i2c.c new file mode 100755 index 00000000..d2cde736 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_i2c.c @@ -0,0 +1,926 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_I2C_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @brief I2C HAL module driver + * @{ + */ + +/** @defgroup I2C_How_To_Use How To Use + * @{ + + The I2C HAL driver can be used as follows: + + - Declare a I2C_HANDLE handle structure, for example: + ``` + I2C_HANDLE instance; + ``` + - Invoke HAL_I2C_Init() API to initialize base address and bourate: + - Base register address; + - DIV base on speed. + + - Invoke HAL_I2C_ConfigureMode() API and HAL_I2C_SetupMsg() to program mode: + - I2C mode; + - Device address and register address; + - Current message. + + - There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode by calling + HAL_I2C_Transfer() and HAL_I2C_IRQHandler() with I2C_POLL type; + - No-Blocking mode: The communication is performed using Interrupts.The + HAL_I2C_Transfer() with I2C_IT type, HAL_I2C_IRQHandler() is used for + interrupt mode. + + - Invoke HAL_I2C_Close() to finish this transfer. + + - Invoke HAL_I2C_DeInit() if necessary. + + @} */ + +/** @defgroup I2C_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +/* REG_CON bits */ +#define REG_CON_EN (0x1 << I2C_CON_I2C_EN_SHIFT) +#define REG_CON_MOD(mod) ((mod) << I2C_CON_I2C_MODE_SHIFT) +#define REG_CON_MOD_MASK (I2C_CON_I2C_MODE_MASK) +#define REG_CON_START (0x1 << I2C_CON_START_SHIFT) +#define REG_CON_STOP (0x1 << I2C_CON_STOP_SHIFT) +#define REG_CON_LASTACK (0x1 << I2C_CON_ACK_SHIFT) /* send NACK after last received byte */ +#define REG_CON_ACTACK (0x1 << I2C_CON_ACT2NAK_SHIFT) /* stop if NACK is received */ + +#define REG_CON_TUNING_MASK (0xff << I2C_CON_DATA_UPD_ST_SHIFT) +#define REG_CON_SDA_CFG(cfg) ((cfg) << I2C_CON_DATA_UPD_ST_SHIFT) +#define REG_CON_STA_CFG(cfg) ((cfg) << I2C_CON_START_SETUP_SHIFT) +#define REG_CON_STO_CFG(cfg) ((cfg) << I2C_CON_STOP_SETUP_SHIFT) + +/* REG_IEN/REG_IPD bits */ +#define REG_INT_BTF (0x1 << I2C_IEN_BTFIEN_SHIFT) /* a byte was transmitted */ +#define REG_INT_BRF (0x1 << I2C_IEN_BRFIEN_SHIFT) /* a byte was received */ +#define REG_INT_MBTF (0x1 << I2C_IEN_MBTFIEN_SHIFT) /* master data transmit finished */ +#define REG_INT_MBRF (0x1 << I2C_IEN_MBRFIEN_SHIFT) /* master data receive finished */ +#define REG_INT_START (0x1 << I2C_IEN_STARTIEN_SHIFT) /* START condition generated */ +#define REG_INT_STOP (0x1 << I2C_IEN_STOPIEN_SHIFT) /* STOP condition generated */ +#define REG_INT_NAKRCV (0x1 << I2C_IEN_NAKRCVIEN_SHIFT) /* NACK received */ +#define REG_INT_ALL (0xff) + +/* Disable i2c all irqs */ +#define IEN_ALL_DISABLE 0 + +/* TX data */ +#define MAX_TX_DATA_REGISTER_CNT 8 + +/********************* Private Structure Definition **************************/ + +struct I2C_SPEC_VALUES { + uint32_t minLowNS; + uint32_t minHighNS; + uint32_t maxRiseNS; + uint32_t maxFallNS; +}; + +/********************* Private Variable Definition ***************************/ + +static const struct I2C_SPEC_VALUES standardModeSpec = { + .minLowNS = 4700, + .minHighNS = 4000, + .maxRiseNS = 1000, + .maxFallNS = 300, +}; + +static const struct I2C_SPEC_VALUES fastModeSpec = { + .minLowNS = 1300, + .minHighNS = 600, + .maxRiseNS = 300, + .maxFallNS = 300, +}; + +static const struct I2C_SPEC_VALUES fastModePlusSpec = { + .minLowNS = 500, + .minHighNS = 260, + .maxRiseNS = 120, + .maxFallNS = 120, +}; + +/********************* Private Function Definition ***************************/ + +/** + * @brief Get the I2C timing specification. + * @param speed: desired I2C bus speed. + * @return matched i2c spec values + */ +static const struct I2C_SPEC_VALUES *I2C_GetSpec(eI2C_BusSpeed speed) +{ + if (speed == I2C_1000K) { + return &fastModePlusSpec; + } else if (speed == I2C_400K) { + return &fastModeSpec; + } else { + return &standardModeSpec; + } +} + +/** + * @brief Clean the I2C pending interrupt. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_CleanIPD(struct I2C_HANDLE *pI2C) +{ + WRITE_REG(pI2C->pReg->IPD, REG_INT_ALL); + + return HAL_OK; +} + +/** + * @brief Disable the I2C interrupt. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_DisableIRQ(struct I2C_HANDLE *pI2C) +{ + WRITE_REG(pI2C->pReg->IEN, IEN_ALL_DISABLE); + + return HAL_OK; +} + +/** + * @brief Disable the I2C controller. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_Disable(struct I2C_HANDLE *pI2C) +{ + uint32_t val = READ_REG(pI2C->pReg->CON) & REG_CON_TUNING_MASK; + + WRITE_REG(pI2C->pReg->CON, val); + + return HAL_OK; +} + +/** + * @brief Send I2C start signal. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_Start(struct I2C_HANDLE *pI2C) +{ + uint32_t val = READ_REG(pI2C->pReg->CON) & REG_CON_TUNING_MASK; + + I2C_CleanIPD(pI2C); + + pI2C->state = STATE_START; + if (pI2C->type == I2C_IT) { + WRITE_REG(pI2C->pReg->IEN, REG_INT_START); + } + + /* enable adapter with correct mode, send START condition */ + val |= REG_CON_EN | REG_CON_MOD(pI2C->mode) | REG_CON_START | pI2C->cfg; + + /* if we want to react to NACK, set ACTACK bit */ + if (!(pI2C->msg.flags & HAL_I2C_M_IGNORE_NAK)) { + val |= REG_CON_ACTACK; + } + + WRITE_REG(pI2C->pReg->CON, val); + + return HAL_OK; +} + +/** + * @brief Send I2C stop signal. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param error: report the error for the stop. + * @return HAL status + */ +static HAL_Status I2C_Stop(struct I2C_HANDLE *pI2C, HAL_Status error) +{ + uint32_t ctrl; + + pI2C->processed = 0; + pI2C->error = error; + + if (pI2C->isLastMSG || error) { + if (pI2C->type == I2C_IT) { + /* Enable stop interrupt */ + WRITE_REG(pI2C->pReg->IEN, REG_INT_STOP); + } + + pI2C->state = STATE_STOP; + + ctrl = READ_REG(pI2C->pReg->CON); + ctrl |= REG_CON_STOP; + WRITE_REG(pI2C->pReg->CON, ctrl); + + return HAL_BUSY; + } else { + /* To start the next message. */ + pI2C->state = STATE_IDLE; + + /* + * The HW is actually not capable of REPEATED START. But we can + * get the intended effect by resetting its internal state + * and issuing an ordinary START. + */ + ctrl = READ_REG(pI2C->pReg->CON) & REG_CON_TUNING_MASK; + WRITE_REG(pI2C->pReg->CON, ctrl); + + return HAL_OK; + } +} + +/** + * @brief Prepare for reading i2c data. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_PrepareRead(struct I2C_HANDLE *pI2C) +{ + uint32_t len = pI2C->msg.len - pI2C->processed; + uint32_t con; + + con = READ_REG(pI2C->pReg->CON); + + /* + * The hw can read up to 32 bytes at a time. If we need more than one + * chunk, send an ACK after the last byte of the current chunk. + */ + if (len > 32) { + len = 32; + con &= ~REG_CON_LASTACK; + } else { + con |= REG_CON_LASTACK; + } + + /* make sure we are in plain RX mode if we read a second chunk */ + if (pI2C->processed != 0) { + con &= ~REG_CON_MOD_MASK; + con |= REG_CON_MOD(REG_CON_MOD_RX); + } + + WRITE_REG(pI2C->pReg->CON, con); + WRITE_REG(pI2C->pReg->MRXCNT, len); + + return HAL_OK; +} + +/** + * @brief Fill transmit buffer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +static HAL_Status I2C_FillTransmitBuf(struct I2C_HANDLE *pI2C) +{ + uint32_t i, j; + uint32_t val, cnt = 0; + uint8_t byte; + + for (i = 0; i < MAX_TX_DATA_REGISTER_CNT; ++i) { + val = 0; + for (j = 0; j < 4; ++j) { + if ((pI2C->processed == pI2C->msg.len) && (cnt != 0)) { + break; + } + + if (pI2C->processed == 0 && cnt == 0) { + byte = (pI2C->msg.addr & 0x7f) << 1; + } else { + byte = pI2C->msg.buf[pI2C->processed++]; + } + + val |= byte << (j * 8); + cnt++; + } + + WRITE_REG(pI2C->pReg->TXDATA[i], val); + if (pI2C->processed == pI2C->msg.len) { + break; + } + } + + WRITE_REG(pI2C->pReg->MTXCNT, cnt); + + return HAL_OK; +} + +/** + * @brief Handle I2C start interrupt for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param ipd: interrupt pending status + * @return HAL status + */ +static HAL_Status I2C_HandleStart(struct I2C_HANDLE *pI2C, uint32_t ipd) +{ + if (!(ipd & REG_INT_START)) { + I2C_Stop(pI2C, HAL_ERROR); + HAL_DBG_ERR("unexpected irq in START: 0x%lx\n", ipd); + I2C_CleanIPD(pI2C); + + return HAL_BUSY; + } + + /* ack interrupt */ + WRITE_REG(pI2C->pReg->IPD, REG_INT_START); + + /* disable start bit */ + WRITE_REG(pI2C->pReg->CON, READ_REG(pI2C->pReg->CON) & ~REG_CON_START); + + /* enable appropriate interrupts and transition */ + if (pI2C->mode == REG_CON_MOD_TX) { + if (pI2C->type == I2C_IT) { + WRITE_REG(pI2C->pReg->IEN, REG_INT_MBTF | REG_INT_NAKRCV); + } + pI2C->state = STATE_WRITE; + I2C_FillTransmitBuf(pI2C); + } else { + /* in any other case, we are going to be reading. */ + if (pI2C->type == I2C_IT) { + WRITE_REG(pI2C->pReg->IEN, REG_INT_MBRF | REG_INT_NAKRCV); + } + pI2C->state = STATE_READ; + I2C_PrepareRead(pI2C); + } + + return HAL_BUSY; +} + +/** + * @brief Handle I2C write interrupt for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param ipd: interrupt pending status + * @return HAL status + */ +static HAL_Status I2C_HandleWrite(struct I2C_HANDLE *pI2C, uint32_t ipd) +{ + if (!(ipd & REG_INT_MBTF)) { + I2C_Stop(pI2C, HAL_ERROR); + HAL_DBG_ERR("unexpected irq in WRITE: 0x%lx\n", ipd); + I2C_CleanIPD(pI2C); + + return HAL_BUSY; + } + + /* ack interrupt */ + WRITE_REG(pI2C->pReg->IPD, REG_INT_MBTF); + + /* are we finished? */ + if (pI2C->processed == pI2C->msg.len) { + return I2C_Stop(pI2C, pI2C->error); + } else { + I2C_FillTransmitBuf(pI2C); + + return HAL_BUSY; + } +} + +/** + * @brief Handle I2C read interrupt for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param ipd: interrupt pending status + * @return HAL status + */ +static HAL_Status I2C_HandleRead(struct I2C_HANDLE *pI2C, uint32_t ipd) +{ + uint32_t len = pI2C->msg.len - pI2C->processed; + uint32_t i, val = 0; + uint8_t byte; + + /* we only care for MBRF here. */ + if (!(ipd & REG_INT_MBRF)) { + return HAL_BUSY; + } + + /* ack interrupt */ + WRITE_REG(pI2C->pReg->IPD, REG_INT_MBRF); + + /* Can only handle a maximum of 32 bytes at a time */ + if (len > 32) { + len = 32; + } + + /* read the data from receive buffer */ + for (i = 0; i < len; ++i) { + if (i % 4 == 0) { + val = READ_REG(pI2C->pReg->RXDATA[i / 4]); + } + + byte = (val >> ((i % 4) * 8)) & 0xff; + pI2C->msg.buf[pI2C->processed++] = byte; + } + + /* are we finished? */ + if (pI2C->processed == pI2C->msg.len) { + return I2C_Stop(pI2C, pI2C->error); + } else { + I2C_PrepareRead(pI2C); + + return HAL_BUSY; + } +} + +/** + * @brief Handle I2C stop interrupt for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param ipd: interrupt pending status + * @return HAL status + */ +static HAL_Status I2C_HandleStop(struct I2C_HANDLE *pI2C, uint32_t ipd) +{ + uint32_t con; + + if (!(ipd & REG_INT_STOP)) { + I2C_Stop(pI2C, HAL_ERROR); + HAL_DBG_ERR("unexpected irq in STOP: 0x%lx\n", ipd); + I2C_CleanIPD(pI2C); + + return HAL_BUSY; + } + + /* ack interrupt */ + WRITE_REG(pI2C->pReg->IPD, REG_INT_STOP); + + /* disable stop bit */ + con = READ_REG(pI2C->pReg->CON); + con &= ~REG_CON_STOP; + WRITE_REG(pI2C->pReg->CON, con); + + pI2C->state = STATE_IDLE; + + return pI2C->error ? pI2C->error : HAL_OK; +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup I2C_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Auto adapte the clock div base on input clock rate and desired speed. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param rate: I2C sclk rate, unit is HZ. + * @return HAL status + */ +HAL_Status HAL_I2C_AdaptDIV(struct I2C_HANDLE *pI2C, uint32_t rate) +{ + const struct I2C_SPEC_VALUES *spec; + uint32_t rateKHZ, speedKHZ; + uint32_t minTotalDIV, minLowDIV, minHighDIV, minHoldDIV; + uint32_t lowDIV, highDIV, extraDIV, extraLowDIV; + uint32_t minLowNS, minHighNS; + uint32_t startSetup = 0; + + switch (pI2C->speed) { + case I2C_1000K: + speedKHZ = 1000; + break; + case I2C_400K: + speedKHZ = 400; + break; + default: + /* default start setup time may not enough for 100K */ + startSetup = 1; + speedKHZ = 100; + break; + } + + rateKHZ = HAL_DIV_ROUND_UP(rate, 1000); + spec = I2C_GetSpec(pI2C->speed); + + minTotalDIV = HAL_DIV_ROUND_UP(rateKHZ, speedKHZ * 8); + + minHighNS = spec->maxRiseNS + spec->minHighNS; + minHighDIV = HAL_DIV_ROUND_UP(rateKHZ * minHighNS, 8 * 1000000); + + minLowNS = spec->maxFallNS + spec->minLowNS; + minLowDIV = HAL_DIV_ROUND_UP(rateKHZ * minLowNS, 8 * 1000000); + + minHighDIV = (minHighDIV < 1) ? 2 : minHighDIV; + minLowDIV = (minLowDIV < 1) ? 2 : minLowDIV; + + minHoldDIV = minHighDIV + minLowDIV; + + if (minHoldDIV >= minTotalDIV) { + highDIV = minHighDIV; + lowDIV = minLowDIV; + } else { + extraDIV = minTotalDIV - minHoldDIV; + extraLowDIV = HAL_DIV_ROUND_UP(minLowDIV * extraDIV, minHoldDIV); + + lowDIV = minLowDIV + extraLowDIV; + highDIV = minHighDIV + (extraDIV - extraLowDIV); + } + + highDIV--; + lowDIV--; + + if (highDIV > 0xffff || lowDIV > 0xffff) { + return HAL_INVAL; + } + + pI2C->cfg = REG_CON_SDA_CFG(1) | REG_CON_STA_CFG(startSetup); + WRITE_REG(pI2C->pReg->CLKDIV, (highDIV << I2C_CLKDIV_CLKDIVH_SHIFT) | lowDIV); + /* 1 for data hold/setup time is enough */ + WRITE_REG(pI2C->pReg->CON, REG_CON_SDA_CFG(1) | REG_CON_STA_CFG(startSetup)); + + return HAL_OK; +} + +/** + * @brief Handle I2C interrupt for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_IRQHandler(struct I2C_HANDLE *pI2C) +{ + uint32_t ipd = READ_REG(pI2C->pReg->IPD); + HAL_Status result = HAL_BUSY; + + if (pI2C->state == STATE_IDLE) { + HAL_DBG_WRN("irq in STATE_IDLE, ipd = 0x%lx\n", ipd); + I2C_CleanIPD(pI2C); + /* Terminate this transfer. */ + result = HAL_INVAL; + goto out; + } + + /* Clean interrupt bits we don't care about */ + ipd &= ~(REG_INT_BRF | REG_INT_BTF); + + if (ipd & REG_INT_NAKRCV) { + /* + * We got a NACK in the last operation. Depending on whether + * IGNORE_NAK is set, we have to stop the operation and report + * an error. + */ + WRITE_REG(pI2C->pReg->IPD, REG_INT_NAKRCV); + ipd &= ~REG_INT_NAKRCV; + + if (!(pI2C->msg.flags & HAL_I2C_M_IGNORE_NAK)) { + /* + * Still return busy status, and would finish transfer + * after the stop handled. + */ + if (pI2C->speed == I2C_100K) { + HAL_DelayUs(1); + } + + I2C_Stop(pI2C, HAL_NODEV); + goto out; + } + } + + /* is there anything left to handle? */ + if ((ipd & REG_INT_ALL) == 0) { + goto out; + } + + switch (pI2C->state) { + case STATE_START: + result = I2C_HandleStart(pI2C, ipd); + break; + case STATE_WRITE: + result = I2C_HandleWrite(pI2C, ipd); + break; + case STATE_READ: + result = I2C_HandleRead(pI2C, ipd); + break; + case STATE_STOP: + /* finish transfer */ + result = I2C_HandleStop(pI2C, ipd); + case STATE_IDLE: + break; + } + +out: + + return result; +} + +/** + * @brief Setup current message for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param addr: slave device address. + * @param buf: pointer to the buffer for I2C transfer. + * @param len: data length for I2C transfer. + * @param flags: flags for I2C transfer. + * @return HAL status + */ +HAL_Status HAL_I2C_SetupMsg(struct I2C_HANDLE *pI2C, uint16_t addr, uint8_t *buf, + uint16_t len, uint16_t flags) +{ + HAL_ASSERT(pI2C != NULL); + + pI2C->msg.addr = addr; + pI2C->msg.buf = buf; + pI2C->msg.len = len; + pI2C->msg.flags = flags; + + return HAL_OK; +} + +/** + * @brief Configure the I2C mode. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param mode: mode for I2C transfer. + * @param addr: slave device address with r/w bit and vaild bit. + * @param regAddr: register address with vaild bit. + * @return HAL status + */ +HAL_Status HAL_I2C_ConfigureMode(struct I2C_HANDLE *pI2C, eI2C_Mode mode, + uint32_t addr, uint32_t regAddr) +{ + HAL_ASSERT(pI2C != NULL); + + if (mode == REG_CON_MOD_REGISTER_TX) { + WRITE_REG(pI2C->pReg->MRXADDR, addr); + WRITE_REG(pI2C->pReg->MRXRADDR, regAddr); + } + + pI2C->mode = mode; + + return HAL_OK; +} + +/** + * @brief Start the I2C transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param type: using poll or interrupt. + * @param last: Last message or not for this transmit. + * @return HAL status + */ +HAL_Status HAL_I2C_Transfer(struct I2C_HANDLE *pI2C, eI2C_TransferType type, bool last) +{ + HAL_ASSERT(pI2C != NULL); + + pI2C->type = type; + pI2C->isLastMSG = last; + + /* Reset value */ + pI2C->processed = 0; + pI2C->error = HAL_OK; + pI2C->state = STATE_IDLE; + + I2C_Start(pI2C); + + return HAL_OK; +} + +/** + * @brief Force to stop the I2C transfer without interrupt. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_ForceStop(struct I2C_HANDLE *pI2C) +{ + HAL_ASSERT(pI2C != NULL); + + /* Force a STOP condition without interrupt */ + I2C_DisableIRQ(pI2C); + MODIFY_REG(pI2C->pReg->CON, ~REG_CON_TUNING_MASK, + REG_CON_EN | REG_CON_STOP); + + pI2C->state = STATE_IDLE; + + return HAL_OK; +} + +/** + * @brief Close the I2C transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_Close(struct I2C_HANDLE *pI2C) +{ + HAL_ASSERT(pI2C != NULL); + + I2C_DisableIRQ(pI2C); + I2C_Disable(pI2C); + + return HAL_OK; +} + +/** + * @brief Handle I2C write finish for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_WriteFinish(struct I2C_HANDLE *pI2C) +{ + if (READ_REG(pI2C->pReg->IPD) & REG_INT_MBTF) { + return HAL_OK; + } + + return HAL_BUSY; +} + +/** + * @brief Handle I2C write stop finish for transfer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_StopFinish(struct I2C_HANDLE *pI2C) +{ + if (REG_INT_STOP & READ_REG(pI2C->pReg->IPD)) { + return HAL_OK; + } + + return HAL_BUSY; +} + +/** + * @brief Send I2C start TX with u32 buffer. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param buf: data buffer include device addr and register addr. + * @param len32: buffer word length. + * @param len8: buffer byte length. + * @return HAL status + */ +HAL_Status HAL_I2C_StartTXU32(struct I2C_HANDLE *pI2C, uint32_t *buf, + uint16_t len32, uint16_t len8) +{ + int i; + + HAL_ASSERT(len32 <= MAX_TX_DATA_REGISTER_CNT); + + I2C_CleanIPD(pI2C); + + for (i = 0; i < len32; i++) { + WRITE_REG(pI2C->pReg->TXDATA[i], buf[i]); + } + + /* enable adapter with correct mode 0, send START condition */ + WRITE_REG(pI2C->pReg->CON, REG_CON_EN | REG_CON_START | pI2C->cfg); + WRITE_REG(pI2C->pReg->MTXCNT, len8); + + return HAL_OK; +} + +/** + * @brief Send I2C start TX. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param addr: device address + * @param buf: data buffer pointer + * @param len: data byte length + * @return HAL status + */ +HAL_Status HAL_I2C_StartTX(struct I2C_HANDLE *pI2C, uint16_t addr, + uint8_t *buf, uint16_t len) +{ + uint32_t i, j; + uint32_t val, cnt = 0; + uint8_t byte; + + pI2C->processed = 0; + I2C_CleanIPD(pI2C); + for (i = 0; i < MAX_TX_DATA_REGISTER_CNT; ++i) { + val = 0; + for (j = 0; j < 4; ++j) { + if ((pI2C->processed == len) && (cnt != 0)) { + break; + } + + if (pI2C->processed == 0 && cnt == 0) { + byte = (addr & 0x7f) << 1; + } else { + byte = buf[pI2C->processed++]; + } + + val |= byte << (j * 8); + cnt++; + } + + WRITE_REG(pI2C->pReg->TXDATA[i], val); + if (pI2C->processed == len) { + break; + } + } + + /* enable adapter with correct mode 0, send START condition */ + WRITE_REG(pI2C->pReg->CON, REG_CON_EN | REG_CON_START | pI2C->cfg); + WRITE_REG(pI2C->pReg->MTXCNT, cnt); + + return HAL_OK; +} + +/** + * @brief Send I2C stop TX. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_StopTX(struct I2C_HANDLE *pI2C) +{ + uint32_t ctrl; + + ctrl = READ_REG(pI2C->pReg->CON); + ctrl &= ~REG_CON_START; + ctrl |= REG_CON_STOP; + WRITE_REG(pI2C->pReg->CON, ctrl); + + return HAL_OK; +} + +/** + * @brief Send I2C close TX. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_CloseTX(struct I2C_HANDLE *pI2C) +{ + WRITE_REG(pI2C->pReg->MTXCNT, 0); + WRITE_REG(pI2C->pReg->CON, 0); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup I2C_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Initialize the I2C according to the specified parameters. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @param pReg: I2C controller register base address. + * @param rate: I2C bus input clock rate. + * @param speed: I2C bus output speed. + * @return HAL status + */ +HAL_Status HAL_I2C_Init(struct I2C_HANDLE *pI2C, struct I2C_REG *pReg, uint32_t rate, + eI2C_BusSpeed speed) +{ + /* Check the I2C handle allocation */ + HAL_ASSERT(pI2C != NULL); + + pI2C->pReg = pReg; + pI2C->speed = speed; + HAL_ASSERT(IS_I2C_INSTANCE(pI2C->pReg)); + + /* Init speed */ + return HAL_I2C_AdaptDIV(pI2C, rate); +} + +/** + * @brief De Initialize the I2C peripheral. + * @param pI2C: pointer to a I2C_HANDLE structure that contains + * the information for I2C module. + * @return HAL status + */ +HAL_Status HAL_I2C_DeInit(struct I2C_HANDLE *pI2C) +{ + /* TO-DO */ + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_I2C_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_i2c.h b/demos/rk3588/bsp/hal/hal_i2c.h new file mode 100755 index 00000000..d9d63fc2 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_i2c.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_I2C_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +#ifndef __HAL_I2C_H +#define __HAL_I2C_H + +#include "hal_def.h" +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup I2C_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** + * @brief Hal I2C message flags + */ +#define HAL_I2C_M_WR (0x0000) /**< write data, from master to slave */ +#define HAL_I2C_M_RD (0x1 << 0) /**< read data, from slave to master */ +#define HAL_I2C_M_TEN (0x1 << 1) /**< this is a ten bit chip address */ +#define HAL_I2C_M_IGNORE_NAK (0x1 << 2) /**< if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * @brief I2C MRXADDR valid bits + */ +#define HAL_I2C_REG_MRXADDR_VALID(x) (0x1 << (24 + (x))) /**< [x*8+7:x*8] of MRX[R]ADDR valid */ + +/***************************** Structure Definition **************************/ + +/** + * @brief I2C mode definition + */ +typedef enum { + REG_CON_MOD_TX = 0, /**< transmit data */ + REG_CON_MOD_REGISTER_TX, /**< select register and restart */ + REG_CON_MOD_RX, /**< receive data */ + REG_CON_MOD_REGISTER_RX /**< broken: transmits read addr AND writes*/ +} eI2C_Mode; + +/** + * @brief I2C transfer mode definition + */ +typedef enum { + I2C_100K = 0, + I2C_400K, + I2C_1000K +} eI2C_BusSpeed; + +/** + * @brief I2C transfer type definition + */ +typedef enum { + I2C_POLL = 0, + I2C_IT +} eI2C_TransferType; + +/** + * @brief I2C transfer state definition + */ +typedef enum { + STATE_IDLE = 0, + STATE_START, + STATE_READ, + STATE_WRITE, + STATE_STOP +} eI2C_State; + +/** + * @brief I2C HW information definition + */ +struct HAL_I2C_DEV { + struct I2C_REG *pReg; + eCLOCK_Name clkID; + uint32_t clkGateID; + uint32_t pclkGateID; + IRQn_Type irqNum; +}; + +/** + * @brief I2C message definition + */ +struct I2C_MSG { + uint16_t addr; /**< slave address */ + uint16_t flags; /**< flags */ + uint16_t len; /**< msg length */ + uint8_t *buf; /**< pointer to msg data */ +}; + +/** + * @brief I2C handle Structure definition + */ + +struct I2C_HANDLE { + struct I2C_REG *pReg; + eI2C_Mode mode; + eI2C_TransferType type; + eI2C_BusSpeed speed; + struct I2C_MSG msg; + eI2C_State state; + uint32_t cfg; + uint32_t processed; + HAL_Status error; + bool isLastMSG; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup I2C_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_I2C_AdaptDIV(struct I2C_HANDLE *pI2C, uint32_t rate); +HAL_Status HAL_I2C_IRQHandler(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_ConfigureMode(struct I2C_HANDLE *pI2C, eI2C_Mode mode, + uint32_t addr, uint32_t regAddr); +HAL_Status HAL_I2C_SetupMsg(struct I2C_HANDLE *pI2C, uint16_t addr, uint8_t *buf, + uint16_t len, uint16_t flags); +HAL_Status HAL_I2C_Transfer(struct I2C_HANDLE *pI2C, eI2C_TransferType type, bool last); +HAL_Status HAL_I2C_ForceStop(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_Close(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_WriteFinish(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_StopFinish(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_StartTX(struct I2C_HANDLE *pI2C, uint16_t addr, + uint8_t *buf, uint16_t len); +HAL_Status HAL_I2C_StartTXU32(struct I2C_HANDLE *pI2C, uint32_t *buf, + uint16_t len32, uint16_t len8); +HAL_Status HAL_I2C_StopTX(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_CloseTX(struct I2C_HANDLE *pI2C); +HAL_Status HAL_I2C_Init(struct I2C_HANDLE *pI2C, struct I2C_REG *pReg, uint32_t rate, + eI2C_BusSpeed speed); +HAL_Status HAL_I2C_DeInit(struct I2C_HANDLE *pI2C); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_I2C_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_list.h b/demos/rk3588/bsp/hal/hal_list.h new file mode 100755 index 00000000..4e3678ef --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_list.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_LIST_H_ +#define _HAL_LIST_H_ + +/***************************** Structure Definition **************************/ + +/** double list struct */ +struct HAL_LIST_NODE { + struct HAL_LIST_NODE *next; + struct HAL_LIST_NODE *prev; +}; + +typedef struct HAL_LIST_NODE HAL_LIST; + +/***************************** Function Declare ******************************/ +/** + * @brief cast a member of a structure out to the containing structure + * @param ptr: the pointer to the member. + * @param type: the type of the container struct this is embedded in. + * @param member: the name of the member within the struct. + */ +#define HAL_CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * @brief initialize a list object + * @param object: object itself. + */ +#define HAL_LIST_OBJECT_INIT(object) { &(object), &(object) } + +#define HAL_LIST_HEAD_INIT(name) { &(name), &(name) } + +/** + * @brief initialize a list head + * @param name: list name.. + */ +#define HAL_LIST_HEAD(name) \ + struct HAL_LIST_NODE name = HAL_LIST_HEAD_INIT(name) + +/** + * @brief initialize a list + * @param l: list to be initialized + */ +__STATIC_INLINE void HAL_LIST_Init(HAL_LIST *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * @param l: list to insert it + * @param n: new node to be inserted + */ +__STATIC_INLINE void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * @param n: new node to be inserted + * @param l: list to insert it + */ +__STATIC_INLINE void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n: the node to remove from the list. + */ +__STATIC_INLINE void HAL_LIST_Remove(HAL_LIST *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief tests whether a list is empty + * @param l: the list to test. + */ +__STATIC_INLINE int HAL_LIST_IsEmpty(const HAL_LIST *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l: the list to get. + */ +__STATIC_INLINE uint32_t HAL_LIST_Len(const HAL_LIST *l) +{ + uint32_t len = 0; + const HAL_LIST *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief get the struct for this entry + * @param node: the entry point + * @param type: the type of structure + * @param member: the name of list in structure + */ +#define HAL_LIST_ENTRY(node, type, member) \ + HAL_CONTAINER_OF(node, type, member) + +/** + * @brief iterate over a list + * @param pos: the rt_list_t * to use as a loop cursor. + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * @brief iterate over a list safe against removal of list entry + * @param pos: the rt_list_t * to use as a loop cursor. + * @param n: another rt_list_t * to use as temporary storage + * @param head: the head for your list. + */ +#define HAL_LIST_FOR_EACH_SAFE(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * @brief iterate over list of given type + * @param pos: the type * to use as a loop cursor. + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY(pos, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member)) + +/** + * @brief iterate over list of given type safe against removal of list entry + * @param pos: the type * to use as a loop cursor. + * @param n: another type * to use as temporary storage + * @param head: the head for your list. + * @param member: the name of the list_struct within the struct. + */ +#define HAL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member) \ + for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member), \ + n = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member); \ + &pos->member != (head); \ + pos = n, n = HAL_LIST_ENTRY(n->member.next, __typeof__(*n), member)) + +/** + * @brief get the first element from a list + * @param ptr: the list head to take the element from. + * @param type: the type of the struct this is embedded in. + * @param member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define HAL_LIST_FIRST_ENTRY(ptr, type, member) \ + HAL_LIST_ENTRY((ptr)->next, type, member) + +#endif diff --git a/demos/rk3588/bsp/hal/hal_pinctrl.c b/demos/rk3588/bsp/hal/hal_pinctrl.c new file mode 100755 index 00000000..4ef5c3c6 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_pinctrl.c @@ -0,0 +1,754 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#if defined(HAL_PINCTRL_MODULE_ENABLED) && defined(SOC_RK3588) + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +/** @defgroup PINCTRL_How_To_Use How To Use + * @{ + + The pinctrl setting registers actually is bus grf registers, which include + iomux, drive strength, pull mode, slew rate and schmitt trigger. + + The pinctrl driver provides APIs: + - HAL_PINCTRL_SetIOMUX() to set pin iomux + - HAL_PINCTRL_SetParam() to set pin iomux/pull/drive strength/schmitt trigger + + Example: + + HAL_PINCTRL_SetIOMUX(GPIO_BANK1, + GPIO_PIN_D2 | // UART4_TX_M0 + GPIO_PIN_D3, // UART4_RX_M0 + PIN_CONFIG_MUX_FUNC10); + + HAL_PINCTRL_SetParam(GPIO_BANK1, + GPIO_PIN_D2 | // UART4_TX_M0 + GPIO_PIN_D3, // UART4_RX_M0 + PIN_CONFIG_MUX_FUNC10 | + PIN_CONFIG_PUL_UP | + PIN_CONFIG_DRV_LEVEL2); + @} */ + +/** @defgroup PINCTRL_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define _TO_MASK(w) ((1U << (w)) - 1U) +#define _TO_OFFSET(gp, w) ((gp) * (w)) +#define RK_GEN_VAL(gp, v, w) ((_TO_MASK(w) << (_TO_OFFSET(gp, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(gp, w))) + +#define _PINCTRL_WRITE(REG, VAL) \ +{ \ + REG = VAL; \ +} + +#define IOMUX_4_BIT_PER_PIN (4) +#define IOMUX_4_PIN_PER_REG (4) +#define SET_IOMUX_0AL(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0A_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0AH(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0A_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0BL(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0B_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0BH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0B_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0CL(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0C_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0CH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0C_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0DL(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0D_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0DH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0D_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0BH_P(_GP, _V, _W) _PINCTRL_WRITE((BUS_IOC->GPIO0B_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0CL_P(_GP, _V, _W) _PINCTRL_WRITE((BUS_IOC->GPIO0C_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0CH_P(_GP, _V, _W) _PINCTRL_WRITE((BUS_IOC->GPIO0C_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0DL_P(_GP, _V, _W) _PINCTRL_WRITE((BUS_IOC->GPIO0D_IOMUX_SEL_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_0DH_P(_GP, _V, _W) _PINCTRL_WRITE((BUS_IOC->GPIO0D_IOMUX_SEL_H), RK_GEN_VAL(_GP, _V, _W)) +#define RK_SET_IOMUX_0AL(BP, V) SET_IOMUX_0AL(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0AH(BP, V) SET_IOMUX_0AH(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0BL(BP, V) SET_IOMUX_0BL(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0BH(BP, V) SET_IOMUX_0BH(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0CL(BP, V) SET_IOMUX_0CL(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0CH(BP, V) SET_IOMUX_0CH(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0DL(BP, V) SET_IOMUX_0DL(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0DH(BP, V) SET_IOMUX_0DH(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0BH_P(BP, V) SET_IOMUX_0BH_P(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0CL_P(BP, V) SET_IOMUX_0CL_P(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0CH_P(BP, V) SET_IOMUX_0CH_P(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0DL_P(BP, V) SET_IOMUX_0DL_P(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_0DH_P(BP, V) SET_IOMUX_0DH_P(BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define IOMUX_L(__B, __G) (BUS_IOC->GPIO##__B##__G##_IOMUX_SEL_L) +#define IOMUX_H(__B, __G) (BUS_IOC->GPIO##__B##__G##_IOMUX_SEL_H) +#define SET_IOMUX_L(_B, _G, _GP, _V, _W) _PINCTRL_WRITE(IOMUX_L(_B, _G), RK_GEN_VAL(_GP, _V, _W)) +#define SET_IOMUX_H(_B, _G, _GP, _V, _W) _PINCTRL_WRITE(IOMUX_H(_B, _G), RK_GEN_VAL(_GP, _V, _W)) +#define RK_SET_IOMUX_L(B, G, BP, V) SET_IOMUX_L(B, G, BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define RK_SET_IOMUX_H(B, G, BP, V) SET_IOMUX_H(B, G, BP % IOMUX_4_PIN_PER_REG, V, IOMUX_4_BIT_PER_PIN) +#define SET_IOMUX_4_BIT(BANK, GROUP, BANK_PIN, VAL) \ +{ \ + if ((BANK_PIN % 8) < 4) { \ + RK_SET_IOMUX_L(BANK, GROUP, BANK_PIN, VAL); \ + } else { \ + RK_SET_IOMUX_H(BANK, GROUP, BANK_PIN, VAL); \ + } \ +} + +#define PINCTRL_SET_IOMUX_4_BIT(bank, bank_pin, val) \ +{ \ + if (bank_pin < 8) { \ + SET_IOMUX_4_BIT(bank, A, bank_pin, val); \ + } else if (bank_pin < 16) { \ + SET_IOMUX_4_BIT(bank, B, bank_pin, val); \ + } else if (bank_pin < 24) { \ + SET_IOMUX_4_BIT(bank, C, bank_pin, val); \ + } else if (bank_pin < 32) { \ + SET_IOMUX_4_BIT(bank, D, bank_pin, val); \ + } \ +} + +#define PULL_2_BIT_PER_PIN (2) +#define PULL_8_PIN_PER_REG (8) +#define SET_PULL_0A(_GP, _V, _W) _PINCTRL_WRITE(PMU1_IOC->GPIO0A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_0B(_GP, _V, _W) _PINCTRL_WRITE(PMU1_IOC->GPIO0B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_0B_P(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_0C(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_0D(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0D_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_1A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_1B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_1C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_1D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1D_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_2A(_GP, _V, _W) _PINCTRL_WRITE(EMMC_IOC->GPIO2A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_2A_P(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_2B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_2C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_2D(_GP, _V, _W) _PINCTRL_WRITE(EMMC_IOC->GPIO2D_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_3A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_3B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_3C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_3D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3D_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_4A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4A_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_4B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4B_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_4C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_4C_P(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO4C_P, RK_GEN_VAL(_GP, _V, _W)) +#define SET_PULL_4D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO2_IOC->GPIO4D_P, RK_GEN_VAL(_GP, _V, _W)) +#define RK_SET_PULL_0A(BP, V) SET_PULL_0A(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_0B(BP, V) SET_PULL_0B(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_0B_P(BP, V) SET_PULL_0B_P(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_0C(BP, V) SET_PULL_0C(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_0D(BP, V) SET_PULL_0D(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_1A(BP, V) SET_PULL_1A(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_1B(BP, V) SET_PULL_1B(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_1C(BP, V) SET_PULL_1C(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_1D(BP, V) SET_PULL_1D(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_2A(BP, V) SET_PULL_2A(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_2A_P(BP, V) SET_PULL_2A_P(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_2B(BP, V) SET_PULL_2B(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_2C(BP, V) SET_PULL_2C(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_2D(BP, V) SET_PULL_2D(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_3A(BP, V) SET_PULL_3A(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_3B(BP, V) SET_PULL_3B(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_3C(BP, V) SET_PULL_3C(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_3D(BP, V) SET_PULL_3D(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_4A(BP, V) SET_PULL_4A(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_4B(BP, V) SET_PULL_4B(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_4C(BP, V) SET_PULL_4C(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_4C_P(BP, V) SET_PULL_4C_P(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) +#define RK_SET_PULL_4D(BP, V) SET_PULL_4D(BP % PULL_8_PIN_PER_REG, V, PULL_2_BIT_PER_PIN) + +#define DRV_4_BIT_PER_PIN (4) +#define DRV_4_PIN_PER_REG (4) +#define SET_DRV_0AL(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0A_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0AH(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0A_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0BL(_GP, _V, _W) _PINCTRL_WRITE((PMU1_IOC->GPIO0B_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0BH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0B_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0CL(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0C_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0CH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0C_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0DL(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0D_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_0DH(_GP, _V, _W) _PINCTRL_WRITE((PMU2_IOC->GPIO0D_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1AL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1A_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1AH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1A_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1BL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1B_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1BH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1B_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1CL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1C_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1CH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1C_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1DL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1D_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_1DH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO1_4_IOC->GPIO1D_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2AL(_GP, _V, _W) _PINCTRL_WRITE((EMMC_IOC->GPIO2A_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2AH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO2A_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2BL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO2B_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2BH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO2B_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2CL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO2C_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2CH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO2C_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2DL(_GP, _V, _W) _PINCTRL_WRITE((EMMC_IOC->GPIO2D_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_2DH(_GP, _V, _W) _PINCTRL_WRITE((EMMC_IOC->GPIO2D_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3AL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3A_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3AH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3A_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3BL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3B_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3BH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3B_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3CL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3C_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3CH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3C_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3DL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3D_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_3DH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO3_5_IOC->GPIO3D_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4AL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO6_IOC->GPIO4A_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4AH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO6_IOC->GPIO4A_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4BL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO6_IOC->GPIO4B_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4BH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO6_IOC->GPIO4B_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4CL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO6_IOC->GPIO4C_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4DL(_GP, _V, _W) _PINCTRL_WRITE((VCCIO2_IOC->GPIO4D_DS_L), RK_GEN_VAL(_GP, _V, _W)) +#define SET_DRV_4DH(_GP, _V, _W) _PINCTRL_WRITE((VCCIO2_IOC->GPIO4D_DS_H), RK_GEN_VAL(_GP, _V, _W)) +#define RK_SET_DRV_0AL(BP, V) SET_DRV_0AL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0AH(BP, V) SET_DRV_0AH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0BL(BP, V) SET_DRV_0BL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0BH(BP, V) SET_DRV_0BH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0CL(BP, V) SET_DRV_0CL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0CH(BP, V) SET_DRV_0CH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0DL(BP, V) SET_DRV_0DL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_0DH(BP, V) SET_DRV_0DH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1AL(BP, V) SET_DRV_1AL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1AH(BP, V) SET_DRV_1AH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1BL(BP, V) SET_DRV_1BL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1BH(BP, V) SET_DRV_1BH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1CL(BP, V) SET_DRV_1CL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1CH(BP, V) SET_DRV_1CH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1DL(BP, V) SET_DRV_1DL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_1DH(BP, V) SET_DRV_1DH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2AL(BP, V) SET_DRV_2AL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2AH(BP, V) SET_DRV_2AH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2BL(BP, V) SET_DRV_2BL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2BH(BP, V) SET_DRV_2BH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2CL(BP, V) SET_DRV_2CL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2CH(BP, V) SET_DRV_2CH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2DL(BP, V) SET_DRV_2DL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_2DH(BP, V) SET_DRV_2DH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3AL(BP, V) SET_DRV_3AL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3AH(BP, V) SET_DRV_3AH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3BL(BP, V) SET_DRV_3BL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3BH(BP, V) SET_DRV_3BH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3CL(BP, V) SET_DRV_3CL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3CH(BP, V) SET_DRV_3CH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3DL(BP, V) SET_DRV_3DL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_3DH(BP, V) SET_DRV_3DH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4AL(BP, V) SET_DRV_3AL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4AH(BP, V) SET_DRV_3AH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4BL(BP, V) SET_DRV_3BL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4BH(BP, V) SET_DRV_3BH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4CL(BP, V) SET_DRV_3CL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4CH(BP, V) SET_DRV_3CH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4DL(BP, V) SET_DRV_3DL(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) +#define RK_SET_DRV_4DH(BP, V) SET_DRV_3DH(BP % DRV_4_PIN_PER_REG, V, DRV_4_BIT_PER_PIN) + +#define SMT_1_BIT_PER_PIN (1) +#define SMT_8_PIN_PER_REG (8) +#define SET_SMT_0A(_GP, _V, _W) _PINCTRL_WRITE(PMU1_IOC->GPIO0A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_0B(_GP, _V, _W) _PINCTRL_WRITE(PMU1_IOC->GPIO0B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_0B_P(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_0C(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_0D(_GP, _V, _W) _PINCTRL_WRITE(PMU2_IOC->GPIO0D_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_1A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_1B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_1C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_1D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO1_4_IOC->GPIO1D_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_2A(_GP, _V, _W) _PINCTRL_WRITE(EMMC_IOC->GPIO2A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_2A_P(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_2B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_2C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO2C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_2D(_GP, _V, _W) _PINCTRL_WRITE(EMMC_IOC->GPIO2D_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_3A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_3B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_3C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_3D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO3D_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_4A(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4A_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_4B(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4B_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_4C(_GP, _V, _W) _PINCTRL_WRITE(VCCIO6_IOC->GPIO4C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_4C_P(_GP, _V, _W) _PINCTRL_WRITE(VCCIO3_5_IOC->GPIO4C_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define SET_SMT_4D(_GP, _V, _W) _PINCTRL_WRITE(VCCIO2_IOC->GPIO4D_SMT, RK_GEN_VAL(_GP, _V, _W)) +#define RK_SET_SMT_0A(BP, V) SET_SMT_0A(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_0B(BP, V) SET_SMT_0B(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_0B_P(BP, V) SET_SMT_0B_P(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_0C(BP, V) SET_SMT_0C(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_0D(BP, V) SET_SMT_0D(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_1A(BP, V) SET_SMT_1A(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_1B(BP, V) SET_SMT_1B(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_1C(BP, V) SET_SMT_1C(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_1D(BP, V) SET_SMT_1D(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_2A(BP, V) SET_SMT_2A(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_2A_P(BP, V) SET_SMT_2A_P(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_2B(BP, V) SET_SMT_2B(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_2C(BP, V) SET_SMT_2C(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_2D(BP, V) SET_SMT_2D(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_3A(BP, V) SET_SMT_3A(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_3B(BP, V) SET_SMT_3B(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_3C(BP, V) SET_SMT_3C(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_3D(BP, V) SET_SMT_3D(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_4A(BP, V) SET_SMT_4A(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_4B(BP, V) SET_SMT_4B(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_4C(BP, V) SET_SMT_4C(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_4C_P(BP, V) SET_SMT_4C_P(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) +#define RK_SET_SMT_4D(BP, V) SET_SMT_4D(BP % SMT_8_PIN_PER_REG, V, SMT_1_BIT_PER_PIN) + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** + * @brief Private function to set pin iomux. + * @param bank: pin bank. + * @param pin: bank pin number 0~31. + * @param val: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t val) +{ + switch (bank) { + case 0: + if (pin < 4) { + RK_SET_IOMUX_0AL(pin, val); + } else if (pin < 8) { + RK_SET_IOMUX_0AH(pin, val); + } else if (pin < 12) { + RK_SET_IOMUX_0BL(pin, val); + } else if (pin < 16) { + if (val < 8) { + RK_SET_IOMUX_0BH(pin, val); + } else { + RK_SET_IOMUX_0BH(pin, 8); + RK_SET_IOMUX_0BH_P(pin, val); + } + } else if (pin < 20) { + if (val < 8) { + RK_SET_IOMUX_0CL(pin, val); + } else { + RK_SET_IOMUX_0CL(pin, 8); + RK_SET_IOMUX_0CL_P(pin, val); + } + } else if (pin < 24) { + if (val < 8) { + RK_SET_IOMUX_0CH(pin, val); + } else { + RK_SET_IOMUX_0CH(pin, 8); + RK_SET_IOMUX_0CH_P(pin, val); + } + } else if (pin < 28) { + if (val < 8) { + RK_SET_IOMUX_0DL(pin, val); + } else { + RK_SET_IOMUX_0DL(pin, 8); + RK_SET_IOMUX_0DL_P(pin, val); + } + } else { + if (val < 8) { + RK_SET_IOMUX_0DH(pin, val); + } else { + RK_SET_IOMUX_0DH(pin, 8); + RK_SET_IOMUX_0DH_P(pin, val); + } + } + break; + case 1: + PINCTRL_SET_IOMUX_4_BIT(1, pin, val); + break; + case 2: + PINCTRL_SET_IOMUX_4_BIT(2, pin, val); + break; + case 3: + PINCTRL_SET_IOMUX_4_BIT(3, pin, val); + break; + case 4: + PINCTRL_SET_IOMUX_4_BIT(4, pin, val); + break; + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +} + +/** + * @brief Private function to set pin pull. + * @param bank: pin bank. + * @param pin: bank pin number 0~31. + * @param val: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPULL(eGPIO_bankId bank, uint8_t pin, uint32_t val) +{ + switch (bank) { + case 0: + if (pin < 8) { + RK_SET_PULL_0A(pin, val); + } else if (pin < 12) { + RK_SET_PULL_0B(pin, val); + } else if (pin < 16) { + RK_SET_PULL_0B_P(pin, val); + } else if (pin < 24) { + RK_SET_PULL_0C(pin, val); + } else { + RK_SET_PULL_0D(pin, val); + } + break; + case 1: + if (pin < 8) { + RK_SET_PULL_1A(pin, val); + } else if (pin < 16) { + RK_SET_PULL_1B(pin, val); + } else if (pin < 24) { + RK_SET_PULL_1C(pin, val); + } else { + RK_SET_PULL_1D(pin, val); + } + break; + case 2: + if (pin < 4) { + RK_SET_PULL_2A(pin, val); + } else if (pin < 8) { + RK_SET_PULL_2A_P(pin, val); + } else if (pin < 16) { + RK_SET_PULL_2B(pin, val); + } else if (pin < 24) { + RK_SET_PULL_2C(pin, val); + } else { + RK_SET_PULL_2D(pin, val); + } + break; + case 3: + if (pin < 8) { + RK_SET_PULL_3A(pin, val); + } else if (pin < 16) { + RK_SET_PULL_3B(pin, val); + } else if (pin < 24) { + RK_SET_PULL_3C(pin, val); + } else { + RK_SET_PULL_3D(pin, val); + } + break; + case 4: + if (pin < 8) { + RK_SET_PULL_4A(pin, val); + } else if (pin < 16) { + RK_SET_PULL_4B(pin, val); + } else if (pin < 18) { + RK_SET_PULL_4C(pin, val); + } else if (pin < 24) { + RK_SET_PULL_4C_P(pin, val); + } else { + RK_SET_PULL_4D(pin, val); + } + break; + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +} + +/** + * @brief Private function to set pin drive strength. + * @param bank: pin bank. + * @param pin: bank pin number 0~31. + * @param val: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetDRV(eGPIO_bankId bank, uint8_t pin, uint32_t val) +{ + switch (bank) { + case 0: + if (pin < 4) { + RK_SET_DRV_0AL(pin, val); + } else if (pin < 8) { + RK_SET_DRV_0AH(pin, val); + } else if (pin < 12) { + RK_SET_DRV_0BL(pin, val); + } else if (pin < 16) { + RK_SET_DRV_0BH(pin, val); + } else if (pin < 20) { + RK_SET_DRV_0CL(pin, val); + } else if (pin < 24) { + RK_SET_DRV_0CH(pin, val); + } else if (pin < 28) { + RK_SET_DRV_0DL(pin, val); + } else { + RK_SET_DRV_0DH(pin, val); + } + break; + case 1: + if (pin < 4) { + RK_SET_DRV_1AL(pin, val); + } else if (pin < 8) { + RK_SET_DRV_1AH(pin, val); + } else if (pin < 12) { + RK_SET_DRV_1BL(pin, val); + } else if (pin < 16) { + RK_SET_DRV_1BH(pin, val); + } else if (pin < 20) { + RK_SET_DRV_1CL(pin, val); + } else if (pin < 24) { + RK_SET_DRV_1CH(pin, val); + } else if (pin < 28) { + RK_SET_DRV_1DL(pin, val); + } else { + RK_SET_DRV_1DH(pin, val); + } + break; + case 2: + if (pin < 4) { + RK_SET_DRV_2AL(pin, val); + } else if (pin < 8) { + RK_SET_DRV_2AH(pin, val); + } else if (pin < 12) { + RK_SET_DRV_2BL(pin, val); + } else if (pin < 16) { + RK_SET_DRV_2BH(pin, val); + } else if (pin < 20) { + RK_SET_DRV_2CL(pin, val); + } else if (pin < 24) { + RK_SET_DRV_2CH(pin, val); + } else if (pin < 28) { + RK_SET_DRV_2DL(pin, val); + } else { + RK_SET_DRV_2DH(pin, val); + } + break; + case 3: + if (pin < 4) { + RK_SET_DRV_3AL(pin, val); + } else if (pin < 8) { + RK_SET_DRV_3AH(pin, val); + } else if (pin < 12) { + RK_SET_DRV_3BL(pin, val); + } else if (pin < 16) { + RK_SET_DRV_3BH(pin, val); + } else if (pin < 20) { + RK_SET_DRV_3CL(pin, val); + } else if (pin < 24) { + RK_SET_DRV_3CH(pin, val); + } else if (pin < 28) { + RK_SET_DRV_3DL(pin, val); + } else { + RK_SET_DRV_3DH(pin, val); + } + break; + case 4: + if (pin < 4) { + RK_SET_DRV_4AL(pin, val); + } else if (pin < 8) { + RK_SET_DRV_4AH(pin, val); + } else if (pin < 12) { + RK_SET_DRV_4BL(pin, val); + } else if (pin < 16) { + RK_SET_DRV_4BH(pin, val); + } else if (pin < 20) { + RK_SET_DRV_4CL(pin, val); + } else if (pin < 24) { + } else if (pin < 28) { + RK_SET_DRV_4DL(pin, val); + } else { + RK_SET_DRV_4DH(pin, val); + } + break; + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +} + +/** + * @brief Private function to set pin schmitt trigger. + * @param bank: pin bank. + * @param pin: bank pin number 0~31. + * @param val: value to write. + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetSMT(eGPIO_bankId bank, uint8_t pin, uint32_t val) +{ + switch (bank) { + case 0: + if (pin < 8) { + RK_SET_SMT_0A(pin, val); + } else if (pin < 12) { + RK_SET_SMT_0B(pin, val); + } else if (pin < 16) { + RK_SET_SMT_0B_P(pin, val); + } else if (pin < 24) { + RK_SET_SMT_0C(pin, val); + } else { + RK_SET_SMT_0D(pin, val); + } + break; + case 1: + if (pin < 8) { + RK_SET_SMT_1A(pin, val); + } else if (pin < 16) { + RK_SET_SMT_1B(pin, val); + } else if (pin < 24) { + RK_SET_SMT_1C(pin, val); + } else { + RK_SET_SMT_1D(pin, val); + } + break; + case 2: + if (pin < 4) { + RK_SET_SMT_2A(pin, val); + } else if (pin < 8) { + RK_SET_SMT_2A_P(pin, val); + } else if (pin < 16) { + RK_SET_SMT_2B(pin, val); + } else if (pin < 24) { + RK_SET_SMT_2C(pin, val); + } else { + RK_SET_SMT_2D(pin, val); + } + break; + case 3: + if (pin < 8) { + RK_SET_SMT_3A(pin, val); + } else if (pin < 16) { + RK_SET_SMT_3B(pin, val); + } else if (pin < 24) { + RK_SET_SMT_3C(pin, val); + } else { + RK_SET_SMT_3D(pin, val); + } + break; + case 4: + if (pin < 8) { + RK_SET_SMT_4A(pin, val); + } else if (pin < 16) { + RK_SET_SMT_4B(pin, val); + } else if (pin < 18) { + RK_SET_SMT_4C(pin, val); + } else if (pin < 24) { + RK_SET_SMT_4C_P(pin, val); + } else { + RK_SET_SMT_4D(pin, val); + } + break; + default: + HAL_DBG("unknown gpio%d\n", bank); + break; + } + + return HAL_OK; +} + +/** + * @brief Private function to set pin parameter. + * @param bank: pin bank. + * @param pin: bank pin number 0~31. + * @param param: multi parameters defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param) +{ + HAL_Status rc = HAL_OK; + + if (param & FLAG_MUX) { + rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX)); + } + + if (param & FLAG_PUL) { + rc |= PINCTRL_SetPULL(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL)); + } + + if (param & FLAG_DRV) { + rc |= PINCTRL_SetDRV(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV)); + } + + if (param & FLAG_SMT) { + rc |= PINCTRL_SetSMT(bank, pin, (uint8_t)((param & MASK_SMT) >> SHIFT_SMT)); + } + + return rc; +} +/** @} */ + +/********************* Public Function Definition ****************************/ + +/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ + +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ +HAL_Status HAL_PINCTRL_Init(void) +{ + return HAL_OK; +} + +HAL_Status HAL_PINCTRL_DeInit(void) +{ + return HAL_OK; +} +/** @} */ + +/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions + + * @{ + */ + +/** + * @brief Public function to set pin parameter for multi pins. + * @param bank: pin bank. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi parameters defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + uint8_t pin; + HAL_Status rc; + + HAL_ASSERT(bank < GPIO_BANK_NUM); + + if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SMT))) { + HAL_DBG("pinctrl: no parameter!\n"); + + return HAL_ERROR; + } + + for (pin = 0; pin < 32; pin++) { + if (mPins & (1 << pin)) { + rc = PINCTRL_SetPinParam(bank, pin, param); + if (rc) { + return rc; + } + } + } + + return HAL_OK; +} + +/** + * @brief Public function to set pin iomux for multi pins. + * @param bank: pin bank. + * @param mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS. + * @param param: multi parameters defined in @ref ePINCTRL_configParam, + * @return HAL_Status. + */ +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param) +{ + return HAL_PINCTRL_SetParam(bank, mPins, param); +} +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_PINCTRL_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_pinctrl.h b/demos/rk3588/bsp/hal/hal_pinctrl.h new file mode 100755 index 00000000..1f559857 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_pinctrl.h @@ -0,0 +1,733 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup PINCTRL + * @{ + */ + +#ifndef __HAL_PINCTRL_H__ +#define __HAL_PINCTRL_H__ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/** PINCTRL IOFUNC Select definition */ +typedef enum { + IOFUNC_SEL_M0, + IOFUNC_SEL_M1, + IOFUNC_SEL_M2, +} eIOFUNC_SEL; + +typedef enum { +#if defined(GPIO0) + GPIO0_A0 = 0, + GPIO0_A1, + GPIO0_A2, + GPIO0_A3, + GPIO0_A4, + GPIO0_A5, + GPIO0_A6, + GPIO0_A7, + GPIO0_B0 = 8, + GPIO0_B1, + GPIO0_B2, + GPIO0_B3, + GPIO0_B4, + GPIO0_B5, + GPIO0_B6, + GPIO0_B7, + GPIO0_C0 = 16, + GPIO0_C1, + GPIO0_C2, + GPIO0_C3, + GPIO0_C4, + GPIO0_C5, + GPIO0_C6, + GPIO0_C7, + GPIO0_D0 = 24, + GPIO0_D1, + GPIO0_D2, + GPIO0_D3, + GPIO0_D4, + GPIO0_D5, + GPIO0_D6, + GPIO0_D7, +#endif +#if defined(GPIO1) + GPIO1_A0 = 32, + GPIO1_A1, + GPIO1_A2, + GPIO1_A3, + GPIO1_A4, + GPIO1_A5, + GPIO1_A6, + GPIO1_A7, + GPIO1_B0 = 40, + GPIO1_B1, + GPIO1_B2, + GPIO1_B3, + GPIO1_B4, + GPIO1_B5, + GPIO1_B6, + GPIO1_B7, + GPIO1_C0 = 48, + GPIO1_C1, + GPIO1_C2, + GPIO1_C3, + GPIO1_C4, + GPIO1_C5, + GPIO1_C6, + GPIO1_C7, + GPIO1_D0 = 56, + GPIO1_D1, + GPIO1_D2, + GPIO1_D3, + GPIO1_D4, + GPIO1_D5, + GPIO1_D6, + GPIO1_D7, +#endif +#if defined(GPIO2) + GPIO2_A0 = 64, + GPIO2_A1, + GPIO2_A2, + GPIO2_A3, + GPIO2_A4, + GPIO2_A5, + GPIO2_A6, + GPIO2_A7, + GPIO2_B0 = 72, + GPIO2_B1, + GPIO2_B2, + GPIO2_B3, + GPIO2_B4, + GPIO2_B5, + GPIO2_B6, + GPIO2_B7, + GPIO2_C0 = 80, + GPIO2_C1, + GPIO2_C2, + GPIO2_C3, + GPIO2_C4, + GPIO2_C5, + GPIO2_C6, + GPIO2_C7, + GPIO2_D0 = 88, + GPIO2_D1, + GPIO2_D2, + GPIO2_D3, + GPIO2_D4, + GPIO2_D5, + GPIO2_D6, + GPIO2_D7, +#endif +#if defined(GPIO3) + GPIO3_A0 = 96, + GPIO3_A1, + GPIO3_A2, + GPIO3_A3, + GPIO3_A4, + GPIO3_A5, + GPIO3_A6, + GPIO3_A7, + GPIO3_B0 = 104, + GPIO3_B1, + GPIO3_B2, + GPIO3_B3, + GPIO3_B4, + GPIO3_B5, + GPIO3_B6, + GPIO3_B7, + GPIO3_C0 = 112, + GPIO3_C1, + GPIO3_C2, + GPIO3_C3, + GPIO3_C4, + GPIO3_C5, + GPIO3_C6, + GPIO3_C7, + GPIO3_D0 = 120, + GPIO3_D1, + GPIO3_D2, + GPIO3_D3, + GPIO3_D4, + GPIO3_D5, + GPIO3_D6, + GPIO3_D7, +#endif +#if defined(GPIO4) + GPIO4_A0 = 128, + GPIO4_A1, + GPIO4_A2, + GPIO4_A3, + GPIO4_A4, + GPIO4_A5, + GPIO4_A6, + GPIO4_A7, + GPIO4_B0 = 136, + GPIO4_B1, + GPIO4_B2, + GPIO4_B3, + GPIO4_B4, + GPIO4_B5, + GPIO4_B6, + GPIO4_B7, + GPIO4_C0 = 144, + GPIO4_C1, + GPIO4_C2, + GPIO4_C3, + GPIO4_C4, + GPIO4_C5, + GPIO4_C6, + GPIO4_C7, + GPIO4_D0 = 152, + GPIO4_D1, + GPIO4_D2, + GPIO4_D3, + GPIO4_D4, + GPIO4_D5, + GPIO4_D6, + GPIO4_D7, +#endif +#if defined(GPIO0_EXP) + GPIO0_EXP_A0 = 160, + GPIO0_EXP_A1, + GPIO0_EXP_A2, + GPIO0_EXP_A3, + GPIO0_EXP_A4, + GPIO0_EXP_A5, + GPIO0_EXP_A6, + GPIO0_EXP_A7, + GPIO0_EXP_B0 = 168, + GPIO0_EXP_B1, + GPIO0_EXP_B2, + GPIO0_EXP_B3, + GPIO0_EXP_B4, + GPIO0_EXP_B5, + GPIO0_EXP_B6, + GPIO0_EXP_B7, + GPIO0_EXP_C0 = 176, + GPIO0_EXP_C1, + GPIO0_EXP_C2, + GPIO0_EXP_C3, + GPIO0_EXP_C4, + GPIO0_EXP_C5, + GPIO0_EXP_C6, + GPIO0_EXP_C7, + GPIO0_EXP_D0 = 184, + GPIO0_EXP_D1, + GPIO0_EXP_D2, + GPIO0_EXP_D3, + GPIO0_EXP_D4, + GPIO0_EXP_D5, + GPIO0_EXP_D6, + GPIO0_EXP_D7, +#endif +#if defined(GPIO1_EXP) + GPIO1_EXP_A0 = 192, + GPIO1_EXP_A1, + GPIO1_EXP_A2, + GPIO1_EXP_A3, + GPIO1_EXP_A4, + GPIO1_EXP_A5, + GPIO1_EXP_A6, + GPIO1_EXP_A7, + GPIO1_EXP_B0 = 200, + GPIO1_EXP_B1, + GPIO1_EXP_B2, + GPIO1_EXP_B3, + GPIO1_EXP_B4, + GPIO1_EXP_B5, + GPIO1_EXP_B6, + GPIO1_EXP_B7, + GPIO1_EXP_C0 = 208, + GPIO1_EXP_C1, + GPIO1_EXP_C2, + GPIO1_EXP_C3, + GPIO1_EXP_C4, + GPIO1_EXP_C5, + GPIO1_EXP_C6, + GPIO1_EXP_C7, + GPIO1_EXP_D0 = 216, + GPIO1_EXP_D1, + GPIO1_EXP_D2, + GPIO1_EXP_D3, + GPIO1_EXP_D4, + GPIO1_EXP_D5, + GPIO1_EXP_D6, + GPIO1_EXP_D7, +#endif +#if defined(GPIO2_EXP) + GPIO2_EXP_A0 = 224, + GPIO2_EXP_A1, + GPIO2_EXP_A2, + GPIO2_EXP_A3, + GPIO2_EXP_A4, + GPIO2_EXP_A5, + GPIO2_EXP_A6, + GPIO2_EXP_A7, + GPIO2_EXP_B0 = 232, + GPIO2_EXP_B1, + GPIO2_EXP_B2, + GPIO2_EXP_B3, + GPIO2_EXP_B4, + GPIO2_EXP_B5, + GPIO2_EXP_B6, + GPIO2_EXP_B7, + GPIO2_EXP_C0 = 240, + GPIO2_EXP_C1, + GPIO2_EXP_C2, + GPIO2_EXP_C3, + GPIO2_EXP_C4, + GPIO2_EXP_C5, + GPIO2_EXP_C6, + GPIO2_EXP_C7, + GPIO2_EXP_D0 = 248, + GPIO2_EXP_D1, + GPIO2_EXP_D2, + GPIO2_EXP_D3, + GPIO2_EXP_D4, + GPIO2_EXP_D5, + GPIO2_EXP_D6, + GPIO2_EXP_D7, +#endif +#if defined(GPIO3_EXP) + GPIO3_EXP_A0 = 256, + GPIO3_EXP_A1, + GPIO3_EXP_A2, + GPIO3_EXP_A3, + GPIO3_EXP_A4, + GPIO3_EXP_A5, + GPIO3_EXP_A6, + GPIO3_EXP_A7, + GPIO3_EXP_B0 = 264, + GPIO3_EXP_B1, + GPIO3_EXP_B2, + GPIO3_EXP_B3, + GPIO3_EXP_B4, + GPIO3_EXP_B5, + GPIO3_EXP_B6, + GPIO3_EXP_B7, + GPIO3_EXP_C0 = 272, + GPIO3_EXP_C1, + GPIO3_EXP_C2, + GPIO3_EXP_C3, + GPIO3_EXP_C4, + GPIO3_EXP_C5, + GPIO3_EXP_C6, + GPIO3_EXP_C7, + GPIO3_EXP_D0 = 280, + GPIO3_EXP_D1, + GPIO3_EXP_D2, + GPIO3_EXP_D3, + GPIO3_EXP_D4, + GPIO3_EXP_D5, + GPIO3_EXP_D6, + GPIO3_EXP_D7, +#endif +#if defined(GPIO4_EXP) + GPIO4_EXP_A0 = 288, + GPIO4_EXP_A1, + GPIO4_EXP_A2, + GPIO4_EXP_A3, + GPIO4_EXP_A4, + GPIO4_EXP_A5, + GPIO4_EXP_A6, + GPIO4_EXP_A7, + GPIO4_EXP_B0 = 296, + GPIO4_EXP_B1, + GPIO4_EXP_B2, + GPIO4_EXP_B3, + GPIO4_EXP_B4, + GPIO4_EXP_B5, + GPIO4_EXP_B6, + GPIO4_EXP_B7, + GPIO4_EXP_C0 = 304, + GPIO4_EXP_C1, + GPIO4_EXP_C2, + GPIO4_EXP_C3, + GPIO4_EXP_C4, + GPIO4_EXP_C5, + GPIO4_EXP_C6, + GPIO4_EXP_C7, + GPIO4_EXP_D0 = 312, + GPIO4_EXP_D1, + GPIO4_EXP_D2, + GPIO4_EXP_D3, + GPIO4_EXP_D4, + GPIO4_EXP_D5, + GPIO4_EXP_D6, + GPIO4_EXP_D7, +#endif + GPIO_NUM_MAX +} ePINCTRL_PIN; + +/** PINCTRL IOMUX definition */ +typedef enum { + PINCTRL_IOMUX_FUNC0, + PINCTRL_IOMUX_FUNC1, + PINCTRL_IOMUX_FUNC2, + PINCTRL_IOMUX_FUNC3, + PINCTRL_IOMUX_FUNC4, + PINCTRL_IOMUX_FUNC5, + PINCTRL_IOMUX_FUNC6, + PINCTRL_IOMUX_FUNC7, + PINCTRL_IOMUX_FUNC8, + PINCTRL_IOMUX_FUNC9, + PINCTRL_IOMUX_FUNC10, + PINCTRL_IOMUX_FUNC11, + PINCTRL_IOMUX_FUNC12, + PINCTRL_IOMUX_FUNC13, + PINCTRL_IOMUX_FUNC14, + PINCTRL_IOMUX_FUNC15 +} ePINCTRL_iomuxFunc; + +/** PINCTRL PULL definition */ +typedef enum { + PINCTRL_PULL_OD, + PINCTRL_PULL_UP, + PINCTRL_PULL_DOWN, + PINCTRL_PULL_KEEP +} ePINCTRL_pullMode; + +/** PINCTRL Drive Strength definition */ +typedef enum { + PINCTRL_DRIVE_LEVEL0, + PINCTRL_DRIVE_LEVEL1, + PINCTRL_DRIVE_LEVEL2, + PINCTRL_DRIVE_LEVEL3, + PINCTRL_DRIVE_LEVEL4, + PINCTRL_DRIVE_LEVEL5, + PINCTRL_DRIVE_LEVEL6, + PINCTRL_DRIVE_LEVEL7 +} ePINCTRL_driveLevel; + +/** PINCTRL Slew Rate definition */ +typedef enum { + PINCTRL_SLEWRATE_SLOW, + PINCTRL_SLEWRATE_FAST +} ePINCTRL_slewRate; + +/** PINCTRL Schmitt enable definition */ +typedef enum { + PINCTRL_SCHMITT_DIS, + PINCTRL_SCHMITT_EN +} ePINCTRL_schmitt; + +#define FLAG_MUX HAL_BIT(31) +#define FLAG_PUL HAL_BIT(30) +#define FLAG_DRV HAL_BIT(29) +#define FLAG_SRT HAL_BIT(28) +#define FLAG_SMT HAL_BIT(27) +#define SHIFT_MUX (0) +#define SHIFT_PUL (4) +#define SHIFT_DRV (8) +#define SHIFT_SRT (16) +#define SHIFT_SMT (18) +#define MASK_MUX (0xFU << SHIFT_MUX) +#define MASK_PUL (0xFU << SHIFT_PUL) +#define MASK_DRV (0xFFU << SHIFT_DRV) +#define MASK_SRT (0x3U << SHIFT_SRT) +#define MASK_SMT (0x3U << SHIFT_SMT) + +/** @brief PIN Configuration Mode + * Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx + * - ggggg : Flag to set Mux/Pull/Drive/Slewrate/Schmitt + * - tt : Schmitt value + * - rr : Slewrate value + * - dddddddd : Drive value + * - pppp : Pull value + * - xxxx : Mux mode value + */ +typedef enum { + PIN_CONFIG_MUX_FUNC0 = (0x0 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC1 = (0x1 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC2 = (0x2 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC3 = (0x3 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC4 = (0x4 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC5 = (0x5 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC6 = (0x6 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC7 = (0x7 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC8 = (0x8 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC9 = (0x9 << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC10 = (0xa << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC11 = (0xb << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC12 = (0xc << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC13 = (0xd << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC14 = (0xe << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_FUNC15 = (0xf << SHIFT_MUX | FLAG_MUX), + PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0, + +#if defined(SOC_SWALLOW) + PIN_CONFIG_PUL_NORMAL = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_DOWN = PIN_CONFIG_PUL_DEFAULT, + PIN_CONFIG_PUL_KEEP = PIN_CONFIG_PUL_DEFAULT, +#elif defined(SOC_RK3588) + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#else + PIN_CONFIG_PUL_NORMAL = (0x0 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_UP = (0x1 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DOWN = (0x2 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_KEEP = (0x3 << SHIFT_PUL | FLAG_PUL), + PIN_CONFIG_PUL_DEFAULT = PIN_CONFIG_PUL_NORMAL, +#endif + +#if defined(SOC_RK3568) || defined(SOC_RV1106) + PIN_CONFIG_DRV_LEVEL0 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0xf << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x1f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x3f << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#elif defined(SOC_RK3588) + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#else + PIN_CONFIG_DRV_LEVEL0 = (0x0 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL1 = (0x1 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL2 = (0x2 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL3 = (0x3 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL4 = (0x4 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL5 = (0x5 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL6 = (0x6 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL7 = (0x7 << SHIFT_DRV | FLAG_DRV), + PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2, +#endif + +#if defined(SOC_RV1106) + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x3 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_FAST, +#else + PIN_CONFIG_SRT_SLOW = (0x0 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_FAST = (0x1 << SHIFT_SRT | FLAG_SRT), + PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW, +#endif + + PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_ENABLE = (0x1 << SHIFT_SMT | FLAG_SMT), + PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE, + + PIN_CONFIG_MAX = 0xFFFFFFFFU, +} ePINCTRL_configParam; + +typedef enum { + GRF_MUX_INFO = 0, + GRF_PUL_INFO, + GRF_DRV_INFO, + GRF_SRT_INFO, + GRF_SMT_INFO, + GRF_INFO_NUM +} ePIN_GRF_INFO_ID; + +#define PIN_BANK_CFG_FLAGS(chn, cnt, reg, \ + offset0, bpp0, ppr0, \ + offset1, bpp1, ppr1, \ + offset2, bpp2, ppr2, \ + offset3, bpp3, ppr3, \ + offset4, bpp4, ppr4) \ + { \ + .channel = chn, \ + .pinCount = cnt, \ + .grfBase = reg, \ + .GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \ + .GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \ + .GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \ + .GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \ + .GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \ + } + +/** @defgroup ePINCTRL_GPIO_PINS Pins Definition + * @{ + */ +typedef enum { + GPIO_PIN_A0 = 0x00000001U, /*!< Pin 0 selected */ + GPIO_PIN_A1 = 0x00000002U, /*!< Pin 1 selected */ + GPIO_PIN_A2 = 0x00000004U, /*!< Pin 2 selected */ + GPIO_PIN_A3 = 0x00000008U, /*!< Pin 3 selected */ + GPIO_PIN_A4 = 0x00000010U, /*!< Pin 4 selected */ + GPIO_PIN_A5 = 0x00000020U, /*!< Pin 5 selected */ + GPIO_PIN_A6 = 0x00000040U, /*!< Pin 6 selected */ + GPIO_PIN_A7 = 0x00000080U, /*!< Pin 7 selected */ + GPIO_PIN_B0 = 0x00000100U, /*!< Pin 8 selected */ + GPIO_PIN_B1 = 0x00000200U, /*!< Pin 9 selected */ + GPIO_PIN_B2 = 0x00000400U, /*!< Pin 10 selected */ + GPIO_PIN_B3 = 0x00000800U, /*!< Pin 11 selected */ + GPIO_PIN_B4 = 0x00001000U, /*!< Pin 12 selected */ + GPIO_PIN_B5 = 0x00002000U, /*!< Pin 13 selected */ + GPIO_PIN_B6 = 0x00004000U, /*!< Pin 14 selected */ + GPIO_PIN_B7 = 0x00008000U, /*!< Pin 15 selected */ + GPIO_PIN_C0 = 0x00010000U, /*!< Pin 16 selected */ + GPIO_PIN_C1 = 0x00020000U, /*!< Pin 17 selected */ + GPIO_PIN_C2 = 0x00040000U, /*!< Pin 18 selected */ + GPIO_PIN_C3 = 0x00080000U, /*!< Pin 19 selected */ + GPIO_PIN_C4 = 0x00100000U, /*!< Pin 20 selected */ + GPIO_PIN_C5 = 0x00200000U, /*!< Pin 21 selected */ + GPIO_PIN_C6 = 0x00400000U, /*!< Pin 22 selected */ + GPIO_PIN_C7 = 0x00800000U, /*!< Pin 23 selected */ + GPIO_PIN_D0 = 0x01000000U, /*!< Pin 24 selected */ + GPIO_PIN_D1 = 0x02000000U, /*!< Pin 25 selected */ + GPIO_PIN_D2 = 0x04000000U, /*!< Pin 26 selected */ + GPIO_PIN_D3 = 0x08000000U, /*!< Pin 27 selected */ + GPIO_PIN_D4 = 0x10000000U, /*!< Pin 28 selected */ + GPIO_PIN_D5 = 0x20000000U, /*!< Pin 29 selected */ + GPIO_PIN_D6 = 0x40000000U, /*!< Pin 30 selected */ + GPIO_PIN_D7 = 0x80000000U, /*!< Pin 31 selected */ +} ePINCTRL_GPIO_PINS; + +#define GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */ + +/** @} */ + +#define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16)) + +/***************************** Structure Definition **************************/ + +struct PINCTRL_GRF_INFO { + uint16_t offset; + uint8_t bitsPerPin; + uint8_t pinsPerReg; +}; + +struct PINCTRL_MUX_RECAL_DATA { + uint32_t reg; + uint8_t bank; + uint8_t pin; + uint8_t bit; + uint8_t mask; +}; + +struct PINCTRL_MUX_ROUTE_DATA { + uint32_t routeReg; + uint32_t routeVal; + uint32_t pin; + uint8_t bank; + uint8_t func; +}; + +struct PINCTRL_BANK_INFO { + struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM]; + uint32_t grfBase; + uint8_t pinCount; + uint8_t channel; +}; + +struct HAL_PINCTRL_DEV { + const struct PINCTRL_BANK_INFO *banks; + const struct PINCTRL_MUX_RECAL_DATA *muxRecalData; + const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData; + uint8_t banksNum; + uint8_t muxRecalDataNum; + uint8_t muxRouteDataNum; +}; + +/** @brief Rockchip pinctrl device struct define + * Define a struct for pinctrl, including banks info, bank number, + * and grf info about iomux offset, iomux bit info, drive/pull/ + * slewrate/schmitt offset and bit info. + */ +extern const struct HAL_PINCTRL_DEV g_pinDev; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup PINCTRL_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_PINCTRL_Suspend(void); +HAL_Status HAL_PINCTRL_Resume(void); + +HAL_Status HAL_PINCTRL_Init(void); +HAL_Status HAL_PINCTRL_DeInit(void); + +HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); +HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param); + +HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode); + +HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode); +HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode); + +/** @} */ + +#endif /* __HAL_PINCTRL_H__ */ + +/** @} */ + +/** @} */ diff --git a/demos/rk3588/bsp/hal/hal_spi.c b/demos/rk3588/bsp/hal/hal_spi.c new file mode 100755 index 00000000..4ce6daa4 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_spi.c @@ -0,0 +1,837 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_SPI_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +/** @defgroup How_To_Use How To Use + * @{ + + The SPI HAL driver can be used as follows: + + - Declare a SPI_Handle handle structure, for example: + ``` + SPI_Handle instance; + ``` + + - Invoke HAL_SPI_Init() API to configure default config: + - opMode: slave or master + - apbTransform + - endianMode + - ssd + - Clock rate + + - Invoke HAL_SPI_Configure() API to program other mode: + - Data size + - Clock polarity and phase + - FirstBit + - Clock div + - Number of data frames received at RX only mode + - IT FIFO Level and DMA FIFO Level + - Transfer Mode + + - There are two modes of transfer: + - Blocking mode: The communication is performed in polling mode by calling HAL_SPI_PioTransfer(). + - No-Blocking mode: The communication is performed using Interrupts or DMA. + - The HAL_SPI_ItTransfer(), HAL_SPI_IrqHandler() is used for Interrupt mode. + - The HAL_SPI_DmaTransfer() is used for DMA mode, and Hal driver dones not + - provide more DMA functions. + + - Invoke HAL_SPI_DeInit() if necessary. + + - More details refer to APIs' descriptions as below. + + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes. + + @} */ + +/** @defgroup Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ + +#define HAL_SPI_FIFO_LENGTH 64 +/* Bit fields in SR */ +#define HAL_SPI_SR_BUSY (0x1 << SPI_SR_BSF_SHIFT) +#ifdef SPI_SR_STB_SHIFT +#define HAL_SPI_SR_STB_BUSY (0x1 << SPI_SR_STB_SHIFT) +#else +#define HAL_SPI_SR_STB_BUSY (0x1 << SPI_SR_BSF_SHIFT) +#endif + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << SPI_IMR_TFEIM_SHIFT) +#define SPI_INT_TXOI (1 << SPI_IMR_TFOIM_SHIFT) +#define SPI_INT_RXUI (1 << SPI_IMR_RFUIM_SHIFT) +#define SPI_INT_RXOI (1 << SPI_IMR_RFOIM_SHIFT) +#define SPI_INT_RXFI (1 << SPI_IMR_RFFIM_SHIFT) +#define SPI_INT_TOI (1 << SPI_IMR_TOIM_SHIFT) +#define SPI_INT_SSPI (1 << SPI_IMR_SSPIM_SHIFT) +#ifdef SPI_IMR_TXFIM_SHIFT +#define SPI_INT_TXFIM (1 << SPI_IMR_TXFIM_SHIFT) +#else +#define SPI_INT_TXFIM (1 << SPI_IMR_RFFIM_SHIFT) +#endif + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << SPI_ICR_CCI_SHIFT) +#define SPI_CLEAR_INT_RXUI (1 << SPI_ICR_CRFUI_SHIFT) +#define SPI_CLEAR_INT_RXOI (1 << SPI_ICR_CRFOI_SHIFT) +#define SPI_CLEAR_INT_TXOI (1 << SPI_ICR_CTFOI_SHIFT) +#define SPI_CLEAR_INT_TOI (1 << SPI_ICR_CTOI_SHIFT) +#define SPI_ICR_SSPI_SHIFT (1 << SPI_ICR_CSSPI_SHIFT) +#ifdef SPI_ICR_CTXFI_SHIFT +#define SPI_CLEAR_INT_TXFI (1 << SPI_ICR_CTXFI_SHIFT) +#else +#define SPI_CLEAR_INT_TXFI (1 << SPI_ICR_CTFOI_SHIFT) +#endif + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << SPI_DMACR_TDE_SHIFT) +#define SPI_DMACR_RX_ENABLE (1 << SPI_DMACR_RDE_SHIFT) + +/* Bit fields in SPI TIMEOUT */ +#define SPI_TIMEOUT_ENABLE (1 << SPI_TIMEOUT_TOE_SHIFT) +#define SPI_TIMEOUT_DISABLE 0 + +#define IS_SPI_MODE(__MODE__) (((__MODE__) == CR0_OPM_SLAVE) || \ + ((__MODE__) == CR0_OPM_MASTER)) + +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == CR0_XFM_TR) || \ + ((__MODE__) == CR0_XFM_TO) || \ + ((__MODE__) == CR0_XFM_RO)) + +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == CR0_DATA_FRAME_SIZE_4BIT) || \ + ((__DATASIZE__) == CR0_DATA_FRAME_SIZE_8BIT) || \ + ((__DATASIZE__) == CR0_DATA_FRAME_SIZE_16BIT)) + +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == CR0_POLARITY_LOW) || \ + ((__CPOL__) == CR0_POLARITY_HIGH)) + +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == CR0_PHASE_1EDGE) || \ + ((__CPHA__) == CR0_PHASE_2EDGE)) + +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == CR0_FIRSTBIT_MSB) || \ + ((__BIT__) == CR0_FIRSTBIT_LSB)) + +#define IS_SPI_APBTRANSFORM(__MODE__) (((__MODE__) == CR0_BHT_16BIT) || \ + ((__MODE__) == CR0_BHT_8BIT)) + +#define IS_SPI_ENDIAN_MODE(__MODE__) (((__MODE__) == CR0_EM_BIG) || \ + ((__MODE__) == CR0_EM_LITTLE)) + +#define IS_SPI_SSD_BIT(__MODE__) (((__MODE__) == CR0_SSD_HALF) || \ + ((__MODE__) == CR0_SSD_ONE)) + +#define IS_SPI_CSM(__NCYCLES__) (((__NCYCLES__) == CR0_CSM_0CYCLE) || \ + ((__NCYCLES__) == CR0_CSM_1CYCLE) || \ + ((__NCYCLES__) == CR0_CSM_2CYCLES) || \ + ((__NCYCLES__) == CR0_CSM_3CYCLES)) + +/* + * About 200us cost for calling DMA function in each SPI DMA xfer in whtch it + * can transfer 10Kbps in 50MHz IO rate. Unless DMA large data, or it's CPU waste. + */ +#define HAL_SPI_DMA_SIZE_MIN 512 + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup SPI_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param base: SPI controller register base address. + * @param slave: working at slave or master. + * @return HAL status + */ +HAL_Status HAL_SPI_Init(struct SPI_HANDLE *pSPI, uint32_t base, bool slave) +{ + /* Check the SPI handle allocation */ + HAL_ASSERT(pSPI != NULL); + + pSPI->pReg = (struct SPI_REG *)base; + HAL_ASSERT(IS_SPI_INSTANCE(pSPI->pReg)); + + if (slave) { + pSPI->config.opMode = CR0_OPM_SLAVE; + } else { + pSPI->config.opMode = CR0_OPM_MASTER; + } + + /* Default config */ + pSPI->config.apbTransform = CR0_BHT_8BIT; + pSPI->config.endianMode = CR0_EM_BIG; + pSPI->config.ssd = CR0_SSD_ONE; + pSPI->config.csm = CR0_CSM_0CYCLE; + pSPI->dmaBurstSize = 1; + + return HAL_OK; +} + +/** + * @brief DeInitialize the SPI peripheral. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_DeInit(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + /* TO-DO */ + return HAL_OK; +} + +/** @} */ + +/** @defgroup SPI_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ + +/** + * @brief Start or stop the spi module. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param enable: start or stop the spi module. + * @return HAL status + */ +static inline HAL_Status HAL_SPI_EnableChip(struct SPI_HANDLE *pSPI, int enable) +{ + WRITE_REG(pSPI->pReg->ENR, (enable ? 1 : 0)); + + return HAL_OK; +} + +/** + * @brief Configure the spi clock division. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param div: clock division. + * @return HAL status + */ +static inline HAL_Status HAL_SPI_SetClock(struct SPI_HANDLE *pSPI, uint16_t div) +{ + WRITE_REG(pSPI->pReg->BAUDR, div); + + return HAL_OK; +} + +/** + * @brief Configure the cs signal. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param select: cs number select. + * @param enable: active or inactive the cs signal. + * @return HAL status + */ +HAL_Status HAL_SPI_SetCS(struct SPI_HANDLE *pSPI, char select, bool enable) +{ + uint32_t ser; + + HAL_ASSERT(pSPI != NULL); + + ser = READ_REG(pSPI->pReg->SER) & SPI_SER_SER_MASK; + + if (enable) { + ser |= 1 << select; + } else { + ser &= ~(1 << select); + } + + WRITE_REG(pSPI->pReg->SER, ser); + + return HAL_OK; +} + +/** + * @brief Wait for the transfer finished. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_FlushFifo(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + while (READ_REG(pSPI->pReg->RXFLR)) { + READ_REG(pSPI->pReg->RXDR); + } + + return HAL_OK; +} + +/** + * @brief Calculate the timeout for transfer finished. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Time + */ +uint32_t HAL_SPI_CalculateTimeout(struct SPI_HANDLE *pSPI) +{ + uint32_t timeout; + uint32_t div, speed; + + HAL_ASSERT(pSPI != NULL); + + div = HAL_DIV_ROUND_UP(pSPI->maxFreq, pSPI->config.speed); + div = (div + 1) & 0xfffe; + + speed = pSPI->maxFreq / div; + + timeout = pSPI->len * 8 * 1000 / speed; + timeout += timeout + 100; /* some tolerance */ + + return timeout; +} + +/** + * @brief Query the SPI bus state is idle or busy. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_QueryBusState(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + if (pSPI->config.opMode == CR0_OPM_SLAVE) { + if (!(READ_REG(pSPI->pReg->SR) & HAL_SPI_SR_STB_BUSY)) { + return HAL_OK; + } + } else { + if (!(READ_REG(pSPI->pReg->SR) & HAL_SPI_SR_BUSY)) { + return HAL_OK; + } + } + + return HAL_BUSY; +} + +/** + * @brief The max amount of data can be written in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Max bytes can xfer. + */ +static inline uint32_t HAL_SPI_TxMax(struct SPI_HANDLE *pSPI) +{ + uint32_t txLeft, txRoom; + + txLeft = (pSPI->pTxBufferEnd - pSPI->pTxBuffer) / pSPI->config.nBytes; + txRoom = HAL_SPI_FIFO_LENGTH - READ_REG(pSPI->pReg->TXFLR); + + return HAL_MIN(txLeft, txRoom); +} + +/** + * @brief Send an amount of data in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +static HAL_Status HAL_SPI_PioWrite(struct SPI_HANDLE *pSPI) +{ + uint32_t max = HAL_SPI_TxMax(pSPI); + uint32_t txw = 0; + + while (max--) { + if (pSPI->config.nBytes == 1) { + txw = *(const uint8_t *)(pSPI->pTxBuffer); + } else { + txw = *(const uint16_t *)(pSPI->pTxBuffer); + } + + WRITE_REG(pSPI->pReg->TXDR, txw); + pSPI->pTxBuffer += pSPI->config.nBytes; + } + + return HAL_OK; +} + +/** + * @brief Read an amount of data(byte) in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +static HAL_Status HAL_SPI_PioReadByte(struct SPI_HANDLE *pSPI) +{ + uint32_t rxLeft = pSPI->pRxBufferEnd - pSPI->pRxBuffer; + uint32_t rxRoom = READ_REG(pSPI->pReg->RXFLR); + uint32_t max = HAL_MIN(rxLeft, rxRoom); + + while (max > 7) { + *(pSPI->pRxBuffer + 0) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 1) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 2) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 3) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 4) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 5) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 6) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 7) = (uint8_t)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 8; + max -= 8; + } + + while (max--) { + *pSPI->pRxBuffer = (uint8_t)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer++; + } + + return HAL_OK; +} + +/** + * @brief Read an amount of data(short) in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +static HAL_Status HAL_SPI_PioReadShort(struct SPI_HANDLE *pSPI) +{ + uint32_t rxLeft = (pSPI->pRxBufferEnd - pSPI->pRxBuffer) >> 1; + uint32_t rxRoom = READ_REG(pSPI->pReg->RXFLR); + uint32_t max = HAL_MIN(rxLeft, rxRoom); + + while (max > 7) { + *((uint16_t *)pSPI->pRxBuffer + 0) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 1) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 2) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 3) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 4) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 5) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 6) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + *((uint16_t *)pSPI->pRxBuffer + 7) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 16; + max -= 8; + } + + while (max--) { + *((uint16_t *)pSPI->pRxBuffer) = (uint16_t)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 2; + } + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_PioTransfer(struct SPI_HANDLE *pSPI) +{ + uint32_t remain = 0; + + HAL_ASSERT(pSPI != NULL); + + pSPI->type = SPI_POLL; + HAL_SPI_EnableChip(pSPI, 1); + + do { + if (pSPI->pTxBuffer) { + remain = pSPI->pTxBufferEnd - pSPI->pTxBuffer; + HAL_SPI_PioWrite(pSPI); + } + + if (pSPI->pRxBuffer) { + remain = pSPI->pRxBufferEnd - pSPI->pRxBuffer; + if (pSPI->config.nBytes == 1) { + HAL_SPI_PioReadByte(pSPI); + } else { + HAL_SPI_PioReadShort(pSPI); + } + } + } while (remain); + + return HAL_OK; +} + +/** + * @brief Disable IRQ bits. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for the specified SPI module. + * mask: The bit will be mask. + * @return HAL status + */ +static inline HAL_Status HAL_SPI_MaskIntr(struct SPI_HANDLE *pSPI, uint32_t mask) +{ + uint32_t newMask; + + newMask = READ_REG(pSPI->pReg->IMR) & ~mask; + WRITE_REG(pSPI->pReg->IMR, newMask); + + return HAL_OK; +} + +/** + * @brief Enable IRQ bits. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for the specified SPI module. + * mask: The bit will be unmask. + * @return HAL status + */ +static inline HAL_Status HAL_SPI_UnmaskIntr(struct SPI_HANDLE *pSPI, uint32_t mask) +{ + uint32_t newMask; + + newMask = READ_REG(pSPI->pReg->IMR) | mask; + WRITE_REG(pSPI->pReg->IMR, newMask); + + return HAL_OK; +} + +/** + * @brief Handle SPI interrupt request. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for the specified SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_IrqHandler(struct SPI_HANDLE *pSPI) +{ + uint32_t irqStatus = READ_REG(pSPI->pReg->ISR); + uint32_t int_level = HAL_SPI_FIFO_LENGTH / 2; + uint32_t left; + HAL_Status result; + + HAL_ASSERT(pSPI != NULL); + + if (!irqStatus) { + result = HAL_NODEV; + goto out; + } + + if (!(pSPI->pTxBuffer || pSPI->pRxBuffer)) { + result = HAL_INVAL; + goto out; + } + + /* Error handling */ + if (irqStatus & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { + WRITE_REG(pSPI->pReg->ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI); + result = HAL_ERROR; + goto out; + } + + if (irqStatus & SPI_INT_RXFI) { + HAL_SPI_MaskIntr(pSPI, SPI_INT_RXFI); + if (pSPI->config.nBytes == 1) { + HAL_SPI_PioReadByte(pSPI); + } else { + HAL_SPI_PioReadShort(pSPI); + } + HAL_SPI_UnmaskIntr(pSPI, SPI_INT_RXFI); + + if (pSPI->pRxBufferEnd > pSPI->pRxBuffer) { + left = ((pSPI->pRxBufferEnd - pSPI->pRxBuffer) / pSPI->config.nBytes) - 1; + left = (left > int_level) ? int_level : left; + WRITE_REG(pSPI->pReg->RXFTLR, left); + + if (pSPI->config.xfmMode == CR0_XFM_TR) { + HAL_SPI_PioWrite(pSPI); + } + } else { + result = HAL_OK; + goto out; + } + } + + if ((irqStatus & SPI_INT_TXEI) && (pSPI->pTxBufferEnd > pSPI->pTxBuffer)) { + HAL_SPI_MaskIntr(pSPI, SPI_INT_TXEI); + HAL_SPI_PioWrite(pSPI); + HAL_SPI_UnmaskIntr(pSPI, SPI_INT_TXEI); + } + + if ((irqStatus & SPI_INT_TXFIM) && (pSPI->pTxBufferEnd == pSPI->pTxBuffer)) { + WRITE_REG(pSPI->pReg->ICR, SPI_CLEAR_INT_TXFI); + result = HAL_OK; + goto out; + } + + return HAL_BUSY; + +out: + WRITE_REG(pSPI->pReg->IMR, 0); + WRITE_REG(pSPI->pReg->ICR, SPI_CLEAR_INT_ALL); + + return result; +} + +/** + * @brief Transmit an amount of data with interrupt in noblocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL_status + */ +HAL_Status HAL_SPI_ItTransfer(struct SPI_HANDLE *pSPI) +{ + uint32_t txLevel, rxLevel, tempLevel; + uint32_t newMask; + + HAL_ASSERT(pSPI != NULL); + + pSPI->type = SPI_IT; + if (pSPI->config.xfmMode == CR0_XFM_RO || pSPI->config.xfmMode == CR0_XFM_TR) { + tempLevel = pSPI->len / pSPI->config.nBytes - 1; + rxLevel = HAL_SPI_FIFO_LENGTH / 2; + rxLevel = (tempLevel > rxLevel) ? rxLevel : tempLevel; + + if (rxLevel != READ_REG(pSPI->pReg->RXFTLR)) { + WRITE_REG(pSPI->pReg->RXFTLR, rxLevel); + } + + HAL_SPI_EnableChip(pSPI, 1); + + if (pSPI->config.xfmMode == CR0_XFM_TR) { + HAL_SPI_PioWrite(pSPI); + } + + newMask = SPI_INT_RXFI | SPI_INT_RXOI | SPI_INT_RXUI; + } else { + tempLevel = pSPI->len / (uint16_t)pSPI->config.nBytes; + txLevel = HAL_SPI_FIFO_LENGTH / 2; + txLevel = (tempLevel > txLevel) ? txLevel : tempLevel; + + if (txLevel != READ_REG(pSPI->pReg->TXFTLR)) { + WRITE_REG(pSPI->pReg->TXFTLR, txLevel); + } + + HAL_SPI_EnableChip(pSPI, 1); + HAL_SPI_PioWrite(pSPI); + newMask = SPI_INT_TXEI | SPI_INT_TXFIM | SPI_INT_TXOI; + } + + WRITE_REG(pSPI->pReg->IMR, newMask); + + return HAL_OK; +} + +/** + * @brief Is the SPI slave mode or not. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Bool + */ +bool HAL_SPI_IsSlave(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + return (pSPI->config.opMode == CR0_OPM_SLAVE); +} + +/** + * @brief Can the Transmit use dma in noblocking mode or not. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Bool + */ +bool HAL_SPI_IsDmaXfer(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + return (pSPI->type == SPI_DMA); +} + +/** + * @brief Can the Transmit use dma in noblocking mode or not. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Bool + */ +bool HAL_SPI_CanDma(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + +#ifdef HAL_DCACHE_MODULE_ENABLED + if (!HAL_IS_CACHELINE_ALIGNED(pSPI->pRxBuffer) || + !HAL_IS_CACHELINE_ALIGNED(pSPI->pTxBuffer) || + !HAL_IS_CACHELINE_ALIGNED(pSPI->len)) { + return false; + } +#endif + + return (pSPI->len > HAL_SPI_DMA_SIZE_MIN); +} + +/** + * @brief Transmit an amount of data with dma in noblocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_DmaTransfer(struct SPI_HANDLE *pSPI) +{ + uint32_t dmacr = 0; + + HAL_ASSERT(pSPI != NULL); + + pSPI->type = SPI_DMA; + if (HAL_SPI_CanDma(pSPI)) { + if (pSPI->pTxBuffer) { + dmacr |= SPI_DMACR_TX_ENABLE; + } + if (pSPI->pRxBuffer) { + dmacr |= SPI_DMACR_RX_ENABLE; + } + } + + WRITE_REG(pSPI->pReg->DMACR, dmacr); + + HAL_SPI_EnableChip(pSPI, 1); + + return HAL_OK; +} + +/** + * @brief Stop the transmit. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +HAL_Status HAL_SPI_Stop(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + + /* IRQ disabled moved to handler is better than here */ + if (pSPI->type == SPI_DMA) { + WRITE_REG(pSPI->pReg->DMACR, 0); + } + + HAL_SPI_EnableChip(pSPI, 0); + + return HAL_OK; +} + +/** + * @brief Configure the SPI transfer mode depend on the tx/rx buffer. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +static HAL_Status HAL_SPI_ConfigureTransferMode(struct SPI_HANDLE *pSPI) +{ + uint32_t cr0; + + if (pSPI->pTxBuffer && pSPI->pRxBuffer) { + pSPI->config.xfmMode = CR0_XFM_TR; + } else if (pSPI->pTxBuffer) { + pSPI->config.xfmMode = CR0_XFM_TO; + } else if (pSPI->pRxBuffer) { + pSPI->config.xfmMode = CR0_XFM_RO; + } + + cr0 = READ_REG(pSPI->pReg->CTRLR[0]); + cr0 &= ~SPI_CTRLR0_XFM_MASK; + cr0 |= pSPI->config.xfmMode; + + WRITE_REG(pSPI->pReg->DMARDLR, pSPI->dmaBurstSize - 1); + + WRITE_REG(pSPI->pReg->CTRLR[0], cr0); + + return HAL_OK; +} + +/** + * @brief Program the SPI config via this api. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to TX buffer. + * @param pRxData: pointer to RX buffer. + * @param size: amount of data to be sent. + * @return HAL status + */ +HAL_Status HAL_SPI_Configure(struct SPI_HANDLE *pSPI, const uint8_t *pTxData, uint8_t *pRxData, uint32_t size) +{ + uint32_t cr0 = 0; + uint32_t div = 0; + + HAL_ASSERT(pSPI != NULL); + HAL_ASSERT((pTxData != NULL) || (pRxData != NULL)); + HAL_ASSERT(IS_SPI_MODE(pSPI->config.opMode)); + HAL_ASSERT(IS_SPI_DIRECTION(pSPI->config.xfmMode)); + HAL_ASSERT(IS_SPI_DATASIZE(pSPI->config.nBytes)); + HAL_ASSERT(IS_SPI_CPOL(pSPI->config.clkPolarity)); + HAL_ASSERT(IS_SPI_CPHA(pSPI->config.clkPhase)); + HAL_ASSERT(IS_SPI_FIRST_BIT(pSPI->config.firstBit)); + HAL_ASSERT(IS_SPI_ENDIAN_MODE(pSPI->config.endianMode)); + HAL_ASSERT(IS_SPI_APBTRANSFORM(pSPI->config.apbTransform)); + HAL_ASSERT(IS_SPI_SSD_BIT(pSPI->config.ssd)); + HAL_ASSERT(IS_SPI_CSM(pSPI->config.csm)); + + cr0 |= pSPI->config.opMode; + + cr0 |= pSPI->config.apbTransform | pSPI->config.endianMode | pSPI->config.ssd; + /* Data width */ + cr0 |= pSPI->config.nBytes; + + /* Mode for polarity, phase, first bit and endian */ + cr0 |= pSPI->config.clkPolarity | pSPI->config.clkPhase | pSPI->config.firstBit; + + /* Config CSM cycles */ + cr0 |= pSPI->config.csm; + + /* div doesn't support odd number */ + div = HAL_DIV_ROUND_UP(pSPI->maxFreq, pSPI->config.speed); + div = (div + 1) & 0xfffe; + + WRITE_REG(pSPI->pReg->CTRLR[0], cr0); + + WRITE_REG(pSPI->pReg->TXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + WRITE_REG(pSPI->pReg->RXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + + WRITE_REG(pSPI->pReg->DMATDLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + WRITE_REG(pSPI->pReg->DMARDLR, 0); + + HAL_SPI_SetClock(pSPI, div); + + pSPI->pTxBuffer = pTxData; + pSPI->pTxBufferEnd = pTxData + size; + pSPI->pRxBuffer = pRxData; + pSPI->pRxBufferEnd = pRxData + size; + pSPI->len = size; + + HAL_SPI_ConfigureTransferMode(pSPI); + + if (pSPI->config.xfmMode == CR0_XFM_RO) { + if (pSPI->config.nBytes == 1) { + WRITE_REG(pSPI->pReg->CTRLR[1], pSPI->len - 1); + } else if (pSPI->config.nBytes == 2) { + WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len / 2) - 1); + } else { + WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len * 2) - 1); + } + } + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_SPI_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_spi.h b/demos/rk3588/bsp/hal/hal_spi.h new file mode 100755 index 00000000..1c8075f9 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_spi.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_SPI_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +#ifndef __HAL_SPI_H +#define __HAL_SPI_H + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup SPI_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define HAL_SPI_MASTER_MAX_SCLK_OUT 50000000 /**< Max io clock in master mode */ +#define HAL_SPI_SLAVE_MAX_SCLK_OUT 20000000 /**< Max io in clock in slave mode */ + +#define CR0_DATA_FRAME_SIZE_4BIT (0x00 << SPI_CTRLR0_DFS_SHIFT) +#define CR0_DATA_FRAME_SIZE_8BIT (0x01 << SPI_CTRLR0_DFS_SHIFT) +#define CR0_DATA_FRAME_SIZE_16BIT (0x02 << SPI_CTRLR0_DFS_SHIFT) + +/* serial clock toggles in middle of first data bit */ +#define CR0_PHASE_1EDGE (0x00 << SPI_CTRLR0_SCPH_SHIFT) +/* serial clock toggles at start of first data bit */ +#define CR0_PHASE_2EDGE (0x01 << SPI_CTRLR0_SCPH_SHIFT) + +#define CR0_POLARITY_LOW (0x00 << SPI_CTRLR0_SCPOL_SHIFT) +#define CR0_POLARITY_HIGH (0x01 << SPI_CTRLR0_SCPOL_SHIFT) + +/* + * The period between ss_n active and + * sclk_out active is half sclk_out cycles + */ +#define CR0_SSD_HALF (0x00 << SPI_CTRLR0_SSD_SHIFT) +/* + * The period between ss_n active and + * sclk_out active is one sclk_out cycle + */ +#define CR0_SSD_ONE (0x01 << SPI_CTRLR0_SSD_SHIFT) + +#define CR0_EM_LITTLE (0x0 << SPI_CTRLR0_EM_SHIFT) +#define CR0_EM_BIG (0x1 << SPI_CTRLR0_EM_SHIFT) + +#define CR0_FIRSTBIT_MSB (0x0 << SPI_CTRLR0_FBM_SHIFT) +#define CR0_FIRSTBIT_LSB (0x1 << SPI_CTRLR0_FBM_SHIFT) + +#define CR0_BHT_16BIT (0x0 << SPI_CTRLR0_BHT_SHIFT) +#define CR0_BHT_8BIT (0x1 << SPI_CTRLR0_BHT_SHIFT) + +#define CR0_XFM_TR (0x00 << SPI_CTRLR0_XFM_SHIFT) +#define CR0_XFM_TO (0x01 << SPI_CTRLR0_XFM_SHIFT) +#define CR0_XFM_RO (0x02 << SPI_CTRLR0_XFM_SHIFT) + +#define CR0_OPM_MASTER (0x00 << SPI_CTRLR0_OPM_SHIFT) +#define CR0_OPM_SLAVE (0x01 << SPI_CTRLR0_OPM_SHIFT) + +#define CR0_CSM(nCycles) (((nCycles) << SPI_CTRLR0_CSM_SHIFT) & SPI_CTRLR0_CSM_MASK) +#define CR0_CSM_0CYCLE CR0_CSM(0) +#define CR0_CSM_1CYCLE CR0_CSM(1) +#define CR0_CSM_2CYCLES CR0_CSM(2) +#define CR0_CSM_3CYCLES CR0_CSM(3) + +/***************************** Structure Definition **************************/ + +/** @brief SPI Type definition */ +typedef enum { + SSI_MOTO_SPI = 0, + SSI_TI_SSP, + SSI_NS_MICROWIRE +} eSPI_SSIType; + +/** @brief SPI Transfer type definition */ +typedef enum { + SPI_POLL = 0, + SPI_IT, + SPI_DMA +} eSPI_TransferType; + +/** @brief SPI Configuration Structure definition */ +struct SPI_CONFIG { + uint32_t opMode; /**< Specifies the SPI operating mode, master or slave. */ + uint32_t xfmMode; /**< Specifies the SPI bidirectional mode state, tx only, rx only or trx mode. */ + uint32_t nBytes; /**< Specifies the SPI data size. */ + uint32_t clkPolarity; /**< Specifies the serial clock steady state. */ + uint32_t clkPhase; /**< Specifies the clock active edge for the bit capture. */ + uint32_t firstBit; /**< Specifies whether data transfers start from MSB or LSB bit. */ + uint32_t endianMode; /**< Specifies whether data transfers start from little or big endian. */ + uint32_t apbTransform; /**< Specifies apb transform type. */ + uint32_t ssd; /**< Specifies period between ss_n active and sclk_out. */ + uint32_t speed; /**< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. */ + uint32_t ssiType; /**< Specifies if the TI mode is enabled or not.*/ + uint32_t csm; /**< Specifies Motorola SPI Master SS_N high cycles for each frame data is transfer. */ +}; + +/* We have 2 DMA channels per SPI, one for RX and one for TX */ +struct HAL_SPI_DMA_INFO { + uint8_t channel; + uint8_t direction; + uint32_t addr; +}; + +struct HAL_SPI_DEV { + const uint32_t base; + const eCLOCK_Name clkId; + const uint32_t clkGateID; + const uint32_t pclkGateID; + const uint8_t irqNum; + const uint8_t isSlave; + const struct HAL_SPI_DMA_INFO txDma; + const struct HAL_SPI_DMA_INFO rxDma; +}; + +/** @brief SPI handle Structure definition */ +struct SPI_HANDLE { + struct SPI_REG *pReg; /**< Specifies SPI registers base address. */ + uint32_t maxFreq; /**< Specifies SPI clock frequency. */ + struct SPI_CONFIG config; /**< Specifies SPI communication parameters. */ + const uint8_t *pTxBuffer; /**< Specifies pointer to SPI Tx transfer Buffer. */ + const uint8_t *pTxBufferEnd; /**< Specifies pointer to SPI Tx End transfer Buffer. */ + uint8_t *pRxBuffer; /**< Specifies pointer to SPI Rx transfer Buffer. */ + uint8_t *pRxBufferEnd; /**< Specifies pointer to SPI Rx End transfer Buffer. */ + uint32_t len; /**< Specifies the transfer length . */ + eSPI_TransferType type; /**< Specifies the transfer type: POLL/IT/DMA. */ + uint32_t dmaBurstSize; /**< Specifies Dma Burst size */ +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup SPI_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_SPI_Init(struct SPI_HANDLE *pSPI, uint32_t base, bool slave); +HAL_Status HAL_SPI_DeInit(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_FlushFifo(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_SetCS(struct SPI_HANDLE *pSPI, char select, bool enable); +HAL_Status HAL_SPI_QueryBusState(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_PioTransfer(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_IrqHandler(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_ItTransfer(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_DmaTransfer(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_Stop(struct SPI_HANDLE *pSPI); +HAL_Status HAL_SPI_Configure(struct SPI_HANDLE *pSPI, const uint8_t *pTxData, + uint8_t *pRxData, uint32_t Size); +uint32_t HAL_SPI_CalculateTimeout(struct SPI_HANDLE *pSPI); +bool HAL_SPI_CanDma(struct SPI_HANDLE *pSPI); +bool HAL_SPI_IsSlave(struct SPI_HANDLE *pSPI); +bool HAL_SPI_IsDmaXfer(struct SPI_HANDLE *pSPI); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_SPI_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_timer.c b/demos/rk3588/bsp/hal/hal_timer.c new file mode 100755 index 00000000..b706e6c6 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_timer.c @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_How_To_Use How To Use + * @{ + + The TIMER driver can be used as follows: + + - IT mode: Resgister TIMER handler. + - Initialize the TIMER by calling HAL_TIMER_Init(): + - Set TIMER count by calling HAL_TIMER_SetCount(). + - Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT(). + - Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT(). + + SYS_TIMER + + - SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init. + + @} */ + +/** @defgroup TIMER_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) +#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) + +#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit module as follows: + + * @{ + */ + +/** + * @brief Timer init. + * @param pReg: Choose TIMER. + * @param mode: Choose TIMER mode. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT); + + return HAL_OK; +} + +/** + * @brief Timer deinit. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + WRITE_REG(pReg->CONTROLREG, 0); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup TIMER_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Start TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK); + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Stop TIMER counter. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Start TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + */ +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK); + return HAL_OK; +} + +/** + * @brief Stop TIMER counter in interrupt mode. + * @param pReg: Choose TIMER. + * @return HAL_Status. + * Just disable TIMER, and keep TIMER configuration. + */ +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg) +{ + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK); + + return HAL_OK; +} + +/** + * @brief Set TIMER count number. + * @param pReg: Choose TIMER. + * @param timerCount: TIMER counter loading number. + * @return HAL_Status. + * Set timer count number. + */ +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount) +{ + uint64_t loadCount = 0; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); +#ifdef SYS_TIMER + if (pReg == SYS_TIMER) + { + return HAL_BUSY; + } +#endif + + loadCount = timerCount; + pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff); + pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff); + + return HAL_OK; +} + +/** + * @brief Get TIMER count number. + * @param pReg: Choose TIMER. + * @return uint64_t: Current conut number. + */ +HAL_SECTION_SRAM_CODE +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg) +{ + uint32_t high, low, temp; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + do + { + high = pReg->CURRENT_VALUE[1]; + low = pReg->CURRENT_VALUE[0]; + temp = pReg->CURRENT_VALUE[1]; + } while (high != temp); + + return ((uint64_t)high << 32) | low; +} + +/** + * @brief Clear TIMER interrupt status. + * @param pReg: Choose TIMER. + * @return HAL_Status: HAL_OK. + */ +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg) +{ + uint32_t timeOut = 1000; + + HAL_ASSERT(IS_TIMER_INSTANCE(pReg)); + + pReg->INTSTATUS = 0x1; + while (pReg->INTSTATUS && timeOut) + { + timeOut--; + } + + if (timeOut == 0) + { + return HAL_TIMEOUT; + } + else + { + return HAL_OK; + } +} + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_timer.h b/demos/rk3588/bsp/hal/hal_timer.h new file mode 100755 index 00000000..6035719a --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_timer.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +#ifndef _HAL_TIMER_H_ +#define _HAL_TIMER_H_ + +#include "hal_def.h" + +/***************************** MACRO Definition ******************************/ + +/** @defgroup TIMER_Exported_Definition_Group1 Basic Definition + * @{ + */ + +typedef enum { + TIMER_FREE_RUNNING = 0, + TIMER_USER_DEFINED, + TIMER_MODE_MAX +} eTIMER_MODE; + +/***************************** Structure Definition **************************/ + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup TIMER_Public_Function_Declare Public Function Declare + * @{ + */ + +HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick); +uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode); +HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg); +HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_TIMER_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_uart.c b/demos/rk3588/bsp/hal/hal_uart.c new file mode 100755 index 00000000..ba9693f1 --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_uart.c @@ -0,0 +1,501 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_base.h" + +#ifdef HAL_UART_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** @defgroup UART_How_To_Use How To Use + * @{ + + The UART driver can be used as follows: + + @} */ + +/** @defgroup UART_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ +static void UART_EnableDLAB(struct UART_REG *pReg) +{ + pReg->LCR |= UART_LCR_DLAB; +} + +static void UART_DisableDLAB(struct UART_REG *pReg) +{ + pReg->LCR &= ~(UART_LCR_DLAB); +} + +static int32_t UART_SetBaudRate(struct UART_REG *pReg, uint32_t clkRate, + uint32_t baudRate) +{ + uint32_t DivLatch; + + DivLatch = clkRate / MODE_X_DIV / baudRate; + + pReg->MCR |= UART_MCR_LOOP; + UART_EnableDLAB(pReg); + + pReg->DLL = DivLatch & 0xff; + pReg->DLH = (DivLatch >> 8) & 0xff; + + UART_DisableDLAB(pReg); + pReg->MCR &= ~(UART_MCR_LOOP); + + return (0); +} + +static int32_t UART_SetLcrReg(struct UART_REG *pReg, uint8_t byteSize, + uint8_t parity, uint8_t stopBits) +{ + uint32_t lcr = 0; + int32_t bRet = 0; + + switch (byteSize) { + case UART_DATA_5B: + lcr |= UART_LCR_WLEN5; + break; + case UART_DATA_6B: + lcr |= UART_LCR_WLEN6; + break; + case UART_DATA_7B: + lcr |= UART_LCR_WLEN7; + break; + case UART_DATA_8B: + lcr |= UART_LCR_WLEN8; + break; + default: + bRet = -1; + break; + } + + switch (parity) { + case UART_ODD_PARITY: + case UART_EVEN_PARITY: + lcr |= UART_LCR_PARITY; + lcr |= ((parity) << 4); + break; + case UART_PARITY_DISABLE: + lcr &= ~UART_LCR_PARITY; + break; + default: + bRet = -1; + break; + } + + if (stopBits == UART_ONE_AND_HALF_OR_TWO_STOPBIT) { + lcr |= UART_LCR_STOP; + } + + pReg->LCR = lcr; + + return (bRet); +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup UART_Exported_Functions_Group1 Suspend and Resume Functions + + This section provides functions allowing to suspend and resume the module: + + * @{ + */ +/** + * @brief suspend uart + * @param pReg: uart reg base + * @param pUartSave: save uart reg + * @return HAL_OK + */ +HAL_Status HAL_UART_Suspend(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + if (pUartSave && pReg) { + while (!(pReg->USR & UART_USR_TX_FIFO_EMPTY)) { + ; + } + pUartSave->LCR = pReg->LCR; + pUartSave->IER = pReg->IER; + pUartSave->MCR = pReg->MCR; + if (pReg->USR & UART_USR_BUSY) { + HAL_DelayMs(10); + } + if (pReg->USR & UART_USR_BUSY) { + pReg->SRR = UART_SRR_XFR | UART_SRR_RFR; + } + pReg->LCR = UART_LCR_DLAB; + pUartSave->DLL = pReg->DLL; + pUartSave->DLH = pReg->DLH; + pUartSave->SRT = pReg->SRT; + pUartSave->STET = pReg->STET; + pReg->LCR = pUartSave->LCR; + } + + return HAL_OK; +} + +/** + * @brief resume uart + * @param pReg: uart reg base + * @param pUartSave: save uart reg + * @return HAL_OK + */ +HAL_Status HAL_UART_Resume(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + if (pUartSave && pReg) { + pReg->MCR = UART_MCR_LOOP; + pReg->LCR = UART_LCR_DLAB; + pReg->DLL = pUartSave->DLL; + pReg->DLH = pUartSave->DLH; + pReg->LCR = pUartSave->LCR; + pReg->IER = pUartSave->IER; + pReg->FCR = UART_FCR_ENABLE_FIFO; + pReg->MCR = pUartSave->MCR; + pReg->SRT = pUartSave->SRT; + pReg->STET = pUartSave->STET; + } + + return HAL_OK; +} +/** @} */ + +/** @defgroup UART_Exported_Functions_Group2 State and Errors Functions + + This section provides functions allowing to get uart status: + + * @{ + */ + +/** + * @brief get uart sub interrupt number + * @param pReg: uart reg base + * @return irq number like UART_IIR_RDI + */ +uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return (pReg->IIR & UART_IIR_MASK); +} + +/** + * @brief get uart sub interrupt number + * @param pReg: uart reg base + * @return line status + */ +uint32_t HAL_UART_GetLsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->LSR; +} + +/** + * @brief get uart status + * @param pReg: uart reg base + * @return uart status + */ +uint32_t HAL_UART_GetUsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->USR; +} + +/** + * @brief get uart modem status + * @param pReg: uart reg base + * @return uart modem status + */ +uint32_t HAL_UART_GetMsr(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->MSR; +} + +/** + * @brief get uart receive fifo level + * @param pReg: uart reg base + * @return uart received fifo level + */ +uint32_t HAL_UART_GetRfl(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + return pReg->RFL; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group3 IO Functions + + This section provides functions allowing to IO controlling: + + * @{ + */ +/** + * @brief send one character + * @param pReg: uart reg base + * @param c: the character to be sent + */ +void HAL_UART_SerialOutChar(struct UART_REG *pReg, char c) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (!(pReg->USR & UART_USR_TX_FIFO_NOT_FULL)) { + ; + } + pReg->THR = (uint32_t)c; +} + +/** + * @brief send many characters + * @param pReg: uart reg base + * @param pdata: characters buffer + * @param cnt: the number of characters + * @return dwRealSize the number has been sent + */ +int HAL_UART_SerialOut(struct UART_REG *pReg, const uint8_t *pdata, uint32_t cnt) +{ + int dwRealSize = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (cnt--) { + while (!(pReg->USR & UART_USR_TX_FIFO_NOT_FULL)) { + ; + } + pReg->THR = *pdata++; + dwRealSize++; + } + + return dwRealSize; +} + +/** + * @brief receive many characters + * @param pReg: uart reg base + * @param pdata: characters buffer + * @param cnt: the number of characters + * @return dwRealSize the number has been received + */ +int HAL_UART_SerialIn(struct UART_REG *pReg, uint8_t *pdata, uint32_t cnt) +{ + int dwRealSize = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + while (cnt--) { + if (!(pReg->USR & UART_USR_RX_FIFO_NOT_EMPTY)) { + break; + } + + *pdata++ = (uint8_t)pReg->RBR; + dwRealSize++; + } + + return dwRealSize; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief reset uart + * @param pReg: uart reg base + */ +void HAL_UART_Reset(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->SRR = UART_SRR_UR | UART_SRR_RFR | UART_SRR_XFR; + pReg->IER = 0; + pReg->DMASA = 1; +} + +/** + * @brief configure uart baudrate,data bit,stop bit and so on + * @param dev: uart hal information + * @param config: uart baud rate,data bit + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_Init(const struct HAL_UART_DEV *dev, const struct HAL_UART_CONFIG *config) +{ + uint32_t newRate; + struct UART_REG *pReg; + + HAL_ASSERT(dev != NULL); + + pReg = dev->pReg; + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + +#if defined(HAL_CRU_MODULE_ENABLED) && !defined(IS_FPGA) + { + uint32_t rate; + + /* set sclk according to uart baud rate */ + if (config->baudRate <= 115200) { + rate = PLL_INPUT_OSC_RATE; + } else { + rate = config->baudRate * 16; + } + HAL_CRU_ClkSetFreq(dev->sclkID, rate); + newRate = HAL_CRU_ClkGetFreq(dev->sclkID); + HAL_ASSERT(rate == newRate); + } +#elif defined(PLL_INPUT_OSC_RATE) && !defined(IS_FPGA) + newRate = PLL_INPUT_OSC_RATE; +#else + newRate = 24000000; +#endif + + pReg->FCR = + UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | UART_FCR_T_TRIG_10; + UART_SetLcrReg(pReg, config->dataBit, config->parity, config->stopBit); + UART_SetBaudRate(pReg, newRate, config->baudRate); + + return HAL_OK; +} + +/** + * @brief disable uart by resetting it + * @param pReg: uart reg base + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_DeInit(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + HAL_UART_Reset(pReg); + + return HAL_OK; +} + +/** @} */ + +/** @defgroup UART_Exported_Functions_Group5 Other Functions + + This section provides functions allowing to control uart: + + * @{ + */ +/** + * @brief enable uart sub interrupt + * @param pReg: uart reg base + * @param uartIntNumb: uart irq num, such as UART_IER_RDI + */ +void HAL_UART_EnableIrq(struct UART_REG *pReg, uint32_t uartIntNumb) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->IER |= uartIntNumb; +} + +/** + * @brief disable uart sub interrupt + * @param pReg: uart reg base + * @param uartIntNumb: uart irq num, such as UART_IER_RDI + */ +void HAL_UART_DisableIrq(struct UART_REG *pReg, uint32_t uartIntNumb) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->IER &= ~uartIntNumb; +} + +/** + * @brief enable uart loop back mode + * @param pReg: uart reg base + */ +void HAL_UART_EnableLoopback(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR |= UART_MCR_LOOP; +} + +/** + * @brief disable uart loop back mode + * @param pReg: uart reg base + */ +void HAL_UART_DisableLoopback(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR &= ~(UART_MCR_LOOP); +} + +/** + * @brief enable uart hardware auto flow control + * @param pReg: uart reg base + */ +void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR = UART_MCR_AFE | 0X02; +} + +/** + * @brief disable uart hardware auto flow control + * @param pReg: uart reg base + */ +void HAL_UART_DisableAutoFlowControl(struct UART_REG *pReg) +{ + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + pReg->MCR &= ~UART_MCR_AFE; +} + +/** + * @brief low level irq handler, for msi, busy, rlsi + * @param pReg: uart reg base + * @return HAL_OK for reserve + */ +HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg) +{ + int iir = 0; + + HAL_ASSERT(IS_UART_INSTANCE(pReg)); + + iir = HAL_UART_GetIrqID(pReg); + + /* Handle the three sub interrupts, so the upper irq handler needn't handle those */ + switch (iir) { + case UART_IIR_MSI: + HAL_UART_GetMsr(pReg); /* clear MSI only */ + break; + case UART_IIR_BUSY: + HAL_UART_GetUsr(pReg); /* clear BUSY interrupt only */ + break; + case UART_IIR_RLSI: + HAL_UART_GetMsr(pReg); /* clear RLSI interrupt only */ + break; + case UART_IIR_NO_INT: + break; + } + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* HAL_UART_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/hal_uart.h b/demos/rk3588/bsp/hal/hal_uart.h new file mode 100755 index 00000000..295eb3eb --- /dev/null +++ b/demos/rk3588/bsp/hal/hal_uart.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "hal_conf.h" + +#ifdef HAL_UART_MODULE_ENABLED + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +#ifndef _HAL_UART_H_ +#define _HAL_UART_H_ + +#include "hal_def.h" +#include "hal_base.h" + +/***************************** MACRO Definition ******************************/ +/** @defgroup UART_Exported_Definition_Group1 Basic Definition + * @{ + */ + +/* Out: Interrupt Enable Register */ +#define UART_IER_PTIME 0x80 /**< Enable Programmable THRE Interrupt Mode */ +#define UART_IER_MSI 0x08 /**< Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /**< Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /**< Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /**< Enable receiver data interrupt */ + +/* In: Interrupt ID Register */ +#define UART_IIR_MASK 0x0f /**< Interrupt ID Mask */ +#define UART_IIR_NO_INT 0x01 /**< No interrupts pending */ +#define UART_IIR_ID 0x0e /**< Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /**< Modem status interrupt */ +#define UART_IIR_THRI 0x02 /**< Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /**< Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /**< Receiver line status interrupt */ +#define UART_IIR_BUSY 0x07 /**< DesignWare APB Busy Detect */ +#define UART_IIR_RX_TIMEOUT 0x0c /**< RX Timeout interrupt */ + +/* Out: FIFO Control Register */ +#define UART_FCR_ENABLE_FIFO 0x01 /**< Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /**< Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /**< Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /**< For DMA applications */ + +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0xc0 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 + +#define UART_FCR_TRIGGER_MASK 0xC0 /**< Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /**< Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /**< Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /**< Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /**< Mask for trigger set at 14 */ +/* 16650 definitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /**< Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /**< Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /**< Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /**< Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /**< Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /**< Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /**< Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /**< Mask for transmit trigger set at 30 */ +#define UART_FCR7_64BYTE 0x20 +/* Go into 64 byte mode (TI16C750 and some Freescale UARTs) */ + +#define UART_FCR_R_TRIG_SHIFT 6 +#define UART_FCR_R_TRIG_BITS(x) (((x)&UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT) +#define UART_FCR_R_TRIG_MAX_STATE 4 + +/* Out: Line Control Register */ +/* + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /**< Set break control */ +#define UART_LCR_SPAR 0x20 /**< Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /**< Even parity select */ +#define UART_LCR_PARITY 0x08 /**< Parity Enable */ +#define UART_LCR_STOP 0x04 /**< Stop bits: 0=1 bit, 1=2 bits */ +#define UART_LCR_WLEN5 0x00 /**< Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /**< Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /**< Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /**< Wordlength: 8 bits */ + +/* Out: Modem Control Register */ +#define UART_MCR_CLKSEL 0x80 /**< Divide clock by 4 (TI16C752, EFR[4]=1) */ +#define UART_MCR_TCRTLR 0x40 /**< Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_XONANY 0x20 /**< Enable Xon Any (TI16C752, EFR[4]=1) */ +#define UART_MCR_AFE 0x20 /**< Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /**< Out2 complement */ +#define UART_MCR_OUT1 0x04 /**< Out1 complement */ +#define UART_MCR_RTS 0x02 /**< RTS complement */ +#define UART_MCR_DTR 0x01 /**< DTR complement */ + +/* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /**< Fifo error */ +#define UART_LSR_TEMT 0x40 /**< Transmitter empty */ +#define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /**< Break interrupt indicator */ +#define UART_LSR_FE 0x08 /**< Frame error indicator */ +#define UART_LSR_PE 0x04 /**< Parity error indicator */ +#define UART_LSR_OE 0x02 /**< Overrun error indicator */ +#define UART_LSR_DR 0x01 /**< Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /**< BI, FE, PE, OE bits */ + +/* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /**< Data Carrier Detect */ +#define UART_MSR_RI 0x40 /**< Ring Indicator */ +#define UART_MSR_DSR 0x20 /**< Data Set Ready */ +#define UART_MSR_CTS 0x10 /**< Clear to Send */ +#define UART_MSR_DDCD 0x08 /**< Delta DCD */ +#define UART_MSR_TERI 0x04 /**< Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /**< Delta DSR */ +#define UART_MSR_DCTS 0x01 /**< Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /**< Any of the delta bits! */ + +#define UART_USR_RX_FIFO_FULL 0x10 /**< Receive FIFO full */ +#define UART_USR_RX_FIFO_NOT_EMPTY 0x08 /**< Receive FIFO not empty */ +#define UART_USR_TX_FIFO_EMPTY 0x04 /**< Transmit FIFO empty */ +#define UART_USR_TX_FIFO_NOT_FULL 0x02 /**< Transmit FIFO not full */ +#define UART_USR_BUSY 0x01 /**< UART busy indicator */ + +#define UART_SRR_UR 0x1 /**< UART Reset */ +#define UART_SRR_RFR 0X2 /**< RCVR FIFO Reset */ +#define UART_SRR_XFR 0x4 /**< XMIT FIFO Reset */ + +#define MODE_X_DIV 16 /**< baud = f / 16 / div */ + +/***************************** Structure Definition **************************/ + +/** + * @brief UART baud rate definition + */ +typedef enum { + UART_BR_110 = 110, + UART_BR_300 = 300, + UART_BR_600 = 600, + UART_BR_1200 = 1200, + UART_BR_2400 = 2400, + UART_BR_4800 = 4800, + UART_BR_9600 = 9600, + UART_BR_14400 = 14400, + UART_BR_19200 = 19200, + UART_BR_38400 = 38400, + UART_BR_57600 = 57600, + UART_BR_115200 = 115200, + UART_BR_230400 = 230400, + UART_BR_380400 = 380400, + UART_BR_460800 = 460800, + UART_BR_921600 = 921600, + UART_BR_1000000 = 1000000, + UART_BR_1500000 = 1500000, + UART_BR_2000000 = 2000000, + UART_BR_3000000 = 3000000, + UART_BR_4000000 = 4000000, +} eUART_baudRate; + +/** + * @brief UART data bit definition + */ +typedef enum { + UART_DATA_5B = 5, + UART_DATA_6B, + UART_DATA_7B, + UART_DATA_8B +} eUART_dataLen; + +/** + * @brief UART stop bit definition + */ +typedef enum { + UART_ONE_STOPBIT, + UART_ONE_AND_HALF_OR_TWO_STOPBIT +} eUART_stopBit; + +/** + * @brief UART parity definition + */ +typedef enum { + UART_ODD_PARITY, + UART_EVEN_PARITY, + UART_PARITY_DISABLE +} eUART_parityEn; + +/** + * @brief UART config definition + */ +struct HAL_UART_CONFIG { + eUART_baudRate baudRate; + eUART_dataLen dataBit; + eUART_stopBit stopBit; + eUART_parityEn parity; +}; + +/** + * @brief UART HW information definition on a soc + */ +struct HAL_UART_DEV { + struct UART_REG *pReg; /**< registers base address */ + + /* sclk is for uart logic, pclk is for register access */ + eCLOCK_Name sclkID; + uint32_t sclkGateID; + uint32_t pclkGateID; + + IRQn_Type irqNum; + bool isAutoFlow; + // ePM_RUNTIME_ID runtimeID; + // DMA_REQ_Type dmaTxReqNum; /**< peri dma tx request num */ + // DMA_REQ_Type dmaRxReqNum; /**< peri dma rx request num */ + // struct DMA_REG *dmac; /**< dmac reg base ptr */ +}; + +/** + * @brief Save UART regist + */ +struct UART_SAVE_CONFIG { + uint32_t DLL; + uint32_t DLH; + uint32_t IER; + uint32_t LCR; + uint32_t MCR; + uint32_t SRT; + uint32_t STET; +}; + +/** @} */ + +/***************************** Function Declare ******************************/ +/** @defgroup UART_Public_Function_Declare Public Function Declare + * @{ + */ +void HAL_UART_EnableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); +void HAL_UART_DisableIrq(struct UART_REG *pReg, uint32_t uartIntNumb); +void HAL_UART_EnableLoopback(struct UART_REG *pReg); +void HAL_UART_DisableLoopback(struct UART_REG *pReg); +void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg); +void HAL_UART_DisableAutoFlowControl(struct UART_REG *pReg); +uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg); +uint32_t HAL_UART_GetLsr(struct UART_REG *pReg); +uint32_t HAL_UART_GetUsr(struct UART_REG *pReg); +uint32_t HAL_UART_GetMsr(struct UART_REG *pReg); +uint32_t HAL_UART_GetRfl(struct UART_REG *pReg); +void HAL_UART_SerialOutChar(struct UART_REG *pReg, char c); +int HAL_UART_SerialOut(struct UART_REG *pReg, const uint8_t *pdata, uint32_t cnt); +int HAL_UART_SerialIn(struct UART_REG *pReg, uint8_t *pdata, uint32_t cnt); +HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg); +void HAL_UART_Reset(struct UART_REG *pReg); +HAL_Status HAL_UART_Init(const struct HAL_UART_DEV *dev, const struct HAL_UART_CONFIG *config); +HAL_Status HAL_UART_DeInit(struct UART_REG *pReg); +HAL_Status HAL_UART_Suspend(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); +HAL_Status HAL_UART_Resume(struct UART_REG *pReg, struct UART_SAVE_CONFIG *pUartSave); + +/** @} */ + +#endif + +/** @} */ + +/** @} */ + +#endif /* HAL_UART_MODULE_ENABLED */ diff --git a/demos/rk3588/bsp/hal/rk3588.h b/demos/rk3588/bsp/hal/rk3588.h new file mode 100755 index 00000000..712b8ce8 --- /dev/null +++ b/demos/rk3588/bsp/hal/rk3588.h @@ -0,0 +1,21736 @@ +#ifndef __RK3588_H +#define __RK3588_H +#ifdef __cplusplus + extern "C" { +#endif +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +#ifndef __ASSEMBLY__ +/* PMU1_IOC Register Structure Define */ +struct PMU1_IOC_REG { + __IO uint32_t GPIO0A_IOMUX_SEL_L; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0A_IOMUX_SEL_H; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0B_IOMUX_SEL_L; /* Address Offset: 0x0008 */ + uint32_t RESERVED000C; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0A_DS_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0A_DS_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0B_DS_L; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t GPIO0A_P; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO0A_IE; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO0B_IE; /* Address Offset: 0x002C */ + __IO uint32_t GPIO0A_SMT; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO0B_SMT; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO0A_PDIS; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO0B_PDIS; /* Address Offset: 0x003C */ + __IO uint32_t XIN_CON; /* Address Offset: 0x0040 */ +}; +/* PMU2_IOC Register Structure Define */ +struct PMU2_IOC_REG { + __IO uint32_t GPIO0B_IOMUX_SEL_H; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0C_IOMUX_SEL_L; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0C_IOMUX_SEL_H; /* Address Offset: 0x0008 */ + __IO uint32_t GPIO0D_IOMUX_SEL_L; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0D_IOMUX_SEL_H; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0B_DS_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0C_DS_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0C_DS_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO0D_DS_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO0D_DS_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO0C_P; /* Address Offset: 0x002C */ + __IO uint32_t GPIO0D_P; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO0B_IE; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO0C_IE; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO0D_IE; /* Address Offset: 0x003C */ + __IO uint32_t GPIO0B_SMT; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO0C_SMT; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO0D_SMT; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO0B_PDIS; /* Address Offset: 0x004C */ + __IO uint32_t GPIO0C_PDIS; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO0D_PDIS; /* Address Offset: 0x0054 */ +}; +/* BUS_IOC Register Structure Define */ +struct BUS_IOC_REG { + uint32_t RESERVED0000[3]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0B_IOMUX_SEL_H; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0C_IOMUX_SEL_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0C_IOMUX_SEL_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0D_IOMUX_SEL_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0D_IOMUX_SEL_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO1A_IOMUX_SEL_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO1A_IOMUX_SEL_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO1B_IOMUX_SEL_L; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO1B_IOMUX_SEL_H; /* Address Offset: 0x002C */ + __IO uint32_t GPIO1C_IOMUX_SEL_L; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO1C_IOMUX_SEL_H; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO1D_IOMUX_SEL_L; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO1D_IOMUX_SEL_H; /* Address Offset: 0x003C */ + __IO uint32_t GPIO2A_IOMUX_SEL_L; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO2A_IOMUX_SEL_H; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO2B_IOMUX_SEL_L; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO2B_IOMUX_SEL_H; /* Address Offset: 0x004C */ + __IO uint32_t GPIO2C_IOMUX_SEL_L; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO2C_IOMUX_SEL_H; /* Address Offset: 0x0054 */ + __IO uint32_t GPIO2D_IOMUX_SEL_L; /* Address Offset: 0x0058 */ + __IO uint32_t GPIO2D_IOMUX_SEL_H; /* Address Offset: 0x005C */ + __IO uint32_t GPIO3A_IOMUX_SEL_L; /* Address Offset: 0x0060 */ + __IO uint32_t GPIO3A_IOMUX_SEL_H; /* Address Offset: 0x0064 */ + __IO uint32_t GPIO3B_IOMUX_SEL_L; /* Address Offset: 0x0068 */ + __IO uint32_t GPIO3B_IOMUX_SEL_H; /* Address Offset: 0x006C */ + __IO uint32_t GPIO3C_IOMUX_SEL_L; /* Address Offset: 0x0070 */ + __IO uint32_t GPIO3C_IOMUX_SEL_H; /* Address Offset: 0x0074 */ + __IO uint32_t GPIO3D_IOMUX_SEL_L; /* Address Offset: 0x0078 */ + __IO uint32_t GPIO3D_IOMUX_SEL_H; /* Address Offset: 0x007C */ + __IO uint32_t GPIO4A_IOMUX_SEL_L; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO4A_IOMUX_SEL_H; /* Address Offset: 0x0084 */ + __IO uint32_t GPIO4B_IOMUX_SEL_L; /* Address Offset: 0x0088 */ + __IO uint32_t GPIO4B_IOMUX_SEL_H; /* Address Offset: 0x008C */ + __IO uint32_t GPIO4C_IOMUX_SEL_L; /* Address Offset: 0x0090 */ + __IO uint32_t GPIO4C_IOMUX_SEL_H; /* Address Offset: 0x0094 */ + __IO uint32_t GPIO4D_IOMUX_SEL_L; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO4D_IOMUX_SEL_H; /* Address Offset: 0x009C */ +}; +/* VCCIO1_4_IOC Register Structure Define */ +struct VCCIO1_4_IOC_REG { + uint32_t RESERVED0000[8]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO1A_DS_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO1A_DS_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO1B_DS_L; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO1B_DS_H; /* Address Offset: 0x002C */ + __IO uint32_t GPIO1C_DS_L; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO1C_DS_H; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO1D_DS_L; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO1D_DS_H; /* Address Offset: 0x003C */ + uint32_t RESERVED0040[52]; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO1A_P; /* Address Offset: 0x0110 */ + __IO uint32_t GPIO1B_P; /* Address Offset: 0x0114 */ + __IO uint32_t GPIO1C_P; /* Address Offset: 0x0118 */ + __IO uint32_t GPIO1D_P; /* Address Offset: 0x011C */ + uint32_t RESERVED0120[24]; /* Address Offset: 0x0120 */ + __IO uint32_t GPIO1A_IE; /* Address Offset: 0x0180 */ + __IO uint32_t GPIO1B_IE; /* Address Offset: 0x0184 */ + __IO uint32_t GPIO1C_IE; /* Address Offset: 0x0188 */ + __IO uint32_t GPIO1D_IE; /* Address Offset: 0x018C */ + uint32_t RESERVED0190[32]; /* Address Offset: 0x0190 */ + __IO uint32_t GPIO1A_SMT; /* Address Offset: 0x0210 */ + __IO uint32_t GPIO1B_SMT; /* Address Offset: 0x0214 */ + __IO uint32_t GPIO1C_SMT; /* Address Offset: 0x0218 */ + __IO uint32_t GPIO1D_SMT; /* Address Offset: 0x021C */ + uint32_t RESERVED0220[24]; /* Address Offset: 0x0220 */ + __IO uint32_t GPIO_PDIS; /* Address Offset: 0x0280 */ +}; +/* VCCIO3_5_IOC Register Structure Define */ +struct VCCIO3_5_IOC_REG { + uint32_t RESERVED0000[17]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO2A_DS_H; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO2B_DS_L; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO2B_DS_H; /* Address Offset: 0x004C */ + __IO uint32_t GPIO2C_DS_L; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO2C_DS_H; /* Address Offset: 0x0054 */ + uint32_t RESERVED0058[2]; /* Address Offset: 0x0058 */ + __IO uint32_t GPIO3A_DS_L; /* Address Offset: 0x0060 */ + __IO uint32_t GPIO3A_DS_H; /* Address Offset: 0x0064 */ + __IO uint32_t GPIO3B_DS_L; /* Address Offset: 0x0068 */ + __IO uint32_t GPIO3B_DS_H; /* Address Offset: 0x006C */ + __IO uint32_t GPIO3C_DS_L; /* Address Offset: 0x0070 */ + __IO uint32_t GPIO3C_DS_H; /* Address Offset: 0x0074 */ + __IO uint32_t GPIO3D_DS_L; /* Address Offset: 0x0078 */ + __IO uint32_t GPIO3D_DS_H; /* Address Offset: 0x007C */ + uint32_t RESERVED0080[4]; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO4C_DS_L; /* Address Offset: 0x0090 */ + __IO uint32_t GPIO4C_DS_H; /* Address Offset: 0x0094 */ + uint32_t RESERVED0098[34]; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO2A_P; /* Address Offset: 0x0120 */ + __IO uint32_t GPIO2B_P; /* Address Offset: 0x0124 */ + __IO uint32_t GPIO2C_P; /* Address Offset: 0x0128 */ + uint32_t RESERVED012C; /* Address Offset: 0x012C */ + __IO uint32_t GPIO3A_P; /* Address Offset: 0x0130 */ + __IO uint32_t GPIO3B_P; /* Address Offset: 0x0134 */ + __IO uint32_t GPIO3C_P; /* Address Offset: 0x0138 */ + __IO uint32_t GPIO3D_P; /* Address Offset: 0x013C */ + uint32_t RESERVED0140[2]; /* Address Offset: 0x0140 */ + __IO uint32_t GPIO4C_P; /* Address Offset: 0x0148 */ + uint32_t RESERVED014C[17]; /* Address Offset: 0x014C */ + __IO uint32_t GPIO2A_IE; /* Address Offset: 0x0190 */ + __IO uint32_t GPIO2B_IE; /* Address Offset: 0x0194 */ + __IO uint32_t GPIO2C_IE; /* Address Offset: 0x0198 */ + uint32_t RESERVED019C; /* Address Offset: 0x019C */ + __IO uint32_t GPIO3A_IE; /* Address Offset: 0x01A0 */ + __IO uint32_t GPIO3B_IE; /* Address Offset: 0x01A4 */ + __IO uint32_t GPIO3C_IE; /* Address Offset: 0x01A8 */ + __IO uint32_t GPIO3D_IE; /* Address Offset: 0x01AC */ + uint32_t RESERVED01B0[2]; /* Address Offset: 0x01B0 */ + __IO uint32_t GPIO4C_IE; /* Address Offset: 0x01B8 */ + uint32_t RESERVED01BC[25]; /* Address Offset: 0x01BC */ + __IO uint32_t GPIO2A_SMT; /* Address Offset: 0x0220 */ + __IO uint32_t GPIO2B_SMT; /* Address Offset: 0x0224 */ + __IO uint32_t GPIO2C_SMT; /* Address Offset: 0x0228 */ + uint32_t RESERVED022C; /* Address Offset: 0x022C */ + __IO uint32_t GPIO3A_SMT; /* Address Offset: 0x0230 */ + __IO uint32_t GPIO3B_SMT; /* Address Offset: 0x0234 */ + __IO uint32_t GPIO3C_SMT; /* Address Offset: 0x0238 */ + __IO uint32_t GPIO3D_SMT; /* Address Offset: 0x023C */ + uint32_t RESERVED0240[2]; /* Address Offset: 0x0240 */ + __IO uint32_t GPIO4C_SMT; /* Address Offset: 0x0248 */ + uint32_t RESERVED024C[15]; /* Address Offset: 0x024C */ + __IO uint32_t GPIO_PDIS; /* Address Offset: 0x0288 */ +}; +/* VCCIO2_IOC Register Structure Define */ +struct VCCIO2_IOC_REG { + uint32_t RESERVED0000[38]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO4D_DS_L; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO4D_DS_H; /* Address Offset: 0x009C */ + uint32_t RESERVED00A0[43]; /* Address Offset: 0x00A0 */ + __IO uint32_t GPIO4D_P; /* Address Offset: 0x014C */ + uint32_t RESERVED0150[27]; /* Address Offset: 0x0150 */ + __IO uint32_t GPIO4D_IE; /* Address Offset: 0x01BC */ + uint32_t RESERVED01C0[35]; /* Address Offset: 0x01C0 */ + __IO uint32_t GPIO4D_SMT; /* Address Offset: 0x024C */ + uint32_t RESERVED0250[13]; /* Address Offset: 0x0250 */ + __IO uint32_t GPIO_PDIS; /* Address Offset: 0x0284 */ +}; +/* VCCIO6_IOC Register Structure Define */ +struct VCCIO6_IOC_REG { + uint32_t RESERVED0000[32]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO4A_DS_L; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO4A_DS_H; /* Address Offset: 0x0084 */ + __IO uint32_t GPIO4B_DS_L; /* Address Offset: 0x0088 */ + __IO uint32_t GPIO4B_DS_H; /* Address Offset: 0x008C */ + __IO uint32_t GPIO4C_DS_L; /* Address Offset: 0x0090 */ + uint32_t RESERVED0094[43]; /* Address Offset: 0x0094 */ + __IO uint32_t GPIO4A_P; /* Address Offset: 0x0140 */ + __IO uint32_t GPIO4B_P; /* Address Offset: 0x0144 */ + __IO uint32_t GPIO4C_P; /* Address Offset: 0x0148 */ + uint32_t RESERVED014C[25]; /* Address Offset: 0x014C */ + __IO uint32_t GPIO4A_IE; /* Address Offset: 0x01B0 */ + __IO uint32_t GPIO4B_IE; /* Address Offset: 0x01B4 */ + __IO uint32_t GPIO4C_IE; /* Address Offset: 0x01B8 */ + uint32_t RESERVED01BC[33]; /* Address Offset: 0x01BC */ + __IO uint32_t GPIO4A_SMT; /* Address Offset: 0x0240 */ + __IO uint32_t GPIO4B_SMT; /* Address Offset: 0x0244 */ + __IO uint32_t GPIO4C_SMT; /* Address Offset: 0x0248 */ + uint32_t RESERVED024C[16]; /* Address Offset: 0x024C */ + __IO uint32_t GPIO_PDIS; /* Address Offset: 0x028C */ +}; +/* EMMC_IOC Register Structure Define */ +struct EMMC_IOC_REG { + uint32_t RESERVED0000[16]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO2A_DS_L; /* Address Offset: 0x0040 */ + uint32_t RESERVED0044[5]; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO2D_DS_L; /* Address Offset: 0x0058 */ + __IO uint32_t GPIO2D_DS_H; /* Address Offset: 0x005C */ + uint32_t RESERVED0060[48]; /* Address Offset: 0x0060 */ + __IO uint32_t GPIO2A_P; /* Address Offset: 0x0120 */ + uint32_t RESERVED0124[2]; /* Address Offset: 0x0124 */ + __IO uint32_t GPIO2D_P; /* Address Offset: 0x012C */ + uint32_t RESERVED0130[24]; /* Address Offset: 0x0130 */ + __IO uint32_t GPIO2A_IE; /* Address Offset: 0x0190 */ + uint32_t RESERVED0194[2]; /* Address Offset: 0x0194 */ + __IO uint32_t GPIO2D_IE; /* Address Offset: 0x019C */ + uint32_t RESERVED01A0[32]; /* Address Offset: 0x01A0 */ + __IO uint32_t GPIO2A_SMT; /* Address Offset: 0x0220 */ + uint32_t RESERVED0224[2]; /* Address Offset: 0x0224 */ + __IO uint32_t GPIO2D_SMT; /* Address Offset: 0x022C */ + uint32_t RESERVED0230[24]; /* Address Offset: 0x0230 */ + __IO uint32_t GPIO_PDIS; /* Address Offset: 0x0290 */ +}; +/* CRU Register Structure Define */ +struct CRU_REG { + uint32_t RESERVED0000[88]; /* Address Offset: 0x0000 */ + __IO uint32_t V0PLL_CON[7]; /* Address Offset: 0x0160 */ + uint32_t RESERVED017C; /* Address Offset: 0x017C */ + __IO uint32_t AUPLL_CON[7]; /* Address Offset: 0x0180 */ + uint32_t RESERVED019C; /* Address Offset: 0x019C */ + __IO uint32_t CPLL_CON[7]; /* Address Offset: 0x01A0 */ + uint32_t RESERVED01BC; /* Address Offset: 0x01BC */ + __IO uint32_t GPLL_CON[7]; /* Address Offset: 0x01C0 */ + uint32_t RESERVED01DC; /* Address Offset: 0x01DC */ + __IO uint32_t NPLL_CON[6]; /* Address Offset: 0x01E0 */ + uint32_t RESERVED01F8[34]; /* Address Offset: 0x01F8 */ + __IO uint32_t MODE_CON[1]; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[178]; /* Address Offset: 0x0300 */ + uint32_t RESERVED05C8[142]; /* Address Offset: 0x05C8 */ + __IO uint32_t GATE_CON[78]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0938[51]; /* Address Offset: 0x0938 */ + __IO uint32_t SOFTRST_CON[77]; /* Address Offset: 0x0A04 */ + uint32_t RESERVED0B38[50]; /* Address Offset: 0x0B38 */ + __IO uint32_t GLB_CNT_TH; /* Address Offset: 0x0C00 */ + __IO uint32_t GLBRST_ST; /* Address Offset: 0x0C04 */ + __IO uint32_t GLB_SRST_FST_VALUE; /* Address Offset: 0x0C08 */ + __IO uint32_t GLB_SRST_SND_VALUE; /* Address Offset: 0x0C0C */ + __IO uint32_t GLB_RST_CON; /* Address Offset: 0x0C10 */ + uint32_t RESERVED0C14[4]; /* Address Offset: 0x0C14 */ + __IO uint32_t SDIO_CON[2]; /* Address Offset: 0x0C24 */ + uint32_t RESERVED0C2C; /* Address Offset: 0x0C2C */ + __IO uint32_t SDMMC_CON[2]; /* Address Offset: 0x0C30 */ + __IO uint32_t PHYREF_ALT_GATE_CON; /* Address Offset: 0x0C38 */ + __IO uint32_t CM0_GATEMASK_CON; /* Address Offset: 0x0C3C */ + uint32_t RESERVED0C40[25]; /* Address Offset: 0x0C40 */ + __IO uint32_t QCHANNEL_CON[1]; /* Address Offset: 0x0CA4 */ + uint32_t RESERVED0CA8[6]; /* Address Offset: 0x0CA8 */ + __IO uint32_t SMOTH_DIVFREE_CON[5]; /* Address Offset: 0x0CC0 */ + uint32_t RESERVED0CD4[11]; /* Address Offset: 0x0CD4 */ + __IO uint32_t AUTOCS_ACLK_TOP_ROOT_CON[2]; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_ACLK_LOW_TOP_ROOT_CON[2]; /* Address Offset: 0x0D08 */ + __IO uint32_t AUTOCS_ACLK_TOP_M400_ROOT_CON[2]; /* Address Offset: 0x0D10 */ + __IO uint32_t AUTOCS_ACLK_TOP_S400_ROOT_CON[2]; /* Address Offset: 0x0D18 */ + __IO uint32_t AUTOCS_ACLK_BUS_ROOT_CON[2]; /* Address Offset: 0x0D20 */ + __IO uint32_t AUTOCS_ACLK_ISP1_ROOT_CON[2]; /* Address Offset: 0x0D28 */ + __IO uint32_t AUTOCS_CLK_RKNN_DSU0_CON[2]; /* Address Offset: 0x0D30 */ + __IO uint32_t AUTOCS_HCLK_RKNN_ROOT_CON[2]; /* Address Offset: 0x0D38 */ + __IO uint32_t AUTOCS_ACLK_NVM_ROOT_CON[2]; /* Address Offset: 0x0D40 */ + __IO uint32_t AUTOCS_ACLK_PHP_ROOT_CON[2]; /* Address Offset: 0x0D48 */ + __IO uint32_t AUTOCS_ACLK_RKVDEC0_ROOT_CON[2]; /* Address Offset: 0x0D50 */ + __IO uint32_t AUTOCS_ACLK_RKVDEC_CCU_CON[2]; /* Address Offset: 0x0D58 */ + __IO uint32_t AUTOCS_ACLK_RKVDEC1_ROOT_CON[2]; /* Address Offset: 0x0D60 */ + __IO uint32_t AUTOCS_ACLK_USB_ROOT_CON[2]; /* Address Offset: 0x0D68 */ + __IO uint32_t AUTOCS_ACLK_VDPU_ROOT_CON[2]; /* Address Offset: 0x0D70 */ + __IO uint32_t AUTOCS_ACLK_VDPU_LOW_ROOT_CON[2]; /* Address Offset: 0x0D78 */ + __IO uint32_t AUTOCS_ACLK_JPEG_DECODER_ROOT_CON[2]; /* Address Offset: 0x0D80 */ + __IO uint32_t AUTOCS_ACLK_RKVENC0_ROOT_CON[2]; /* Address Offset: 0x0D88 */ + __IO uint32_t AUTOCS_ACLK_RKVENC1_ROOT_CON[2]; /* Address Offset: 0x0D90 */ + __IO uint32_t AUTOCS_ACLK_VI_ROOT_CON[2]; /* Address Offset: 0x0D98 */ + __IO uint32_t AUTOCS_ACLK_VOP_ROOT_CON[2]; /* Address Offset: 0x0DA0 */ + __IO uint32_t AUTOCS_ACLK_VO0_ROOT_CON[2]; /* Address Offset: 0x0DA8 */ + __IO uint32_t AUTOCS_ACLK_HDCP1_ROOT_CON[2]; /* Address Offset: 0x0DB0 */ + __IO uint32_t AUTOCS_ACLK_HDMIRX_ROOT_CON[2]; /* Address Offset: 0x0DB8 */ + __IO uint32_t AUTOCS_CLK_GPU_COREGROUP_CON[2]; /* Address Offset: 0x0DC0 */ + uint32_t RESERVED0DC8[6]; /* Address Offset: 0x0DC8 */ + __IO uint32_t AUTOCS_ACLK_AV1_ROOT_CON[2]; /* Address Offset: 0x0DE0 */ + __IO uint32_t AUTOCS_ACLK_CENTER_ROOT_CON[2]; /* Address Offset: 0x0DE8 */ + __IO uint32_t AUTOCS_ACLK_CENTER_LOW_ROOT_CON[2]; /* Address Offset: 0x0DF0 */ + __IO uint32_t AUTOCS_ACLK_CENTER_S400_ROOT_CON[2]; /* Address Offset: 0x0DF8 */ + __IO uint32_t AUTOCS_ACLK_VO1USB_TOP_ROOT_CON[2]; /* Address Offset: 0x0E00 */ + __IO uint32_t AUTOCS_ACLK_RGA3_ROOT_CON[2]; /* Address Offset: 0x0E08 */ + __IO uint32_t AUTOCS_PCLK_AV1_ROOT_CON[2]; /* Address Offset: 0x0E10 */ + __IO uint32_t AUTOCS_HCLK_ISP1_ROOT_CON[2]; /* Address Offset: 0x0E18 */ + __IO uint32_t AUTOCS_PCLK_NPUTOP_ROOT_CON[2]; /* Address Offset: 0x0E20 */ + __IO uint32_t AUTOCS_HCLK_NPU_CM0_ROOT_CON[2]; /* Address Offset: 0x0E28 */ + __IO uint32_t AUTOCS_HCLK_NVM_ROOT_CON[2]; /* Address Offset: 0x0E30 */ + __IO uint32_t AUTOCS_PCLK_PHP_ROOT_CON[2]; /* Address Offset: 0x0E38 */ + __IO uint32_t AUTOCS_ACLK_PCIE_ROOT_CON[2]; /* Address Offset: 0x0E40 */ + __IO uint32_t AUTOCS_HCLK_RKVDEC0_ROOT_CON[2]; /* Address Offset: 0x0E48 */ + __IO uint32_t AUTOCS_HCLK_RKVDEC1_ROOT_CON[2]; /* Address Offset: 0x0E50 */ + __IO uint32_t AUTOCS_PCLK_TOP_ROOT_CON[2]; /* Address Offset: 0x0E58 */ + __IO uint32_t AUTOCS_ACLK_TOP_M500_ROOT_CON[2]; /* Address Offset: 0x0E60 */ + __IO uint32_t AUTOCS_ACLK_TOP_S200_ROOT_CON[2]; /* Address Offset: 0x0E68 */ + __IO uint32_t AUTOCS_HCLK_USB_ROOT_CON[2]; /* Address Offset: 0x0E70 */ + __IO uint32_t AUTOCS_HCLK_VDPU_ROOT_CON[2]; /* Address Offset: 0x0E78 */ + __IO uint32_t AUTOCS_HCLK_RKVENC0_ROOT_CON[2]; /* Address Offset: 0x0E80 */ + __IO uint32_t AUTOCS_HCLK_RKVENC1_ROOT_CON[2]; /* Address Offset: 0x0E88 */ + __IO uint32_t AUTOCS_HCLK_VI_ROOT_CON[2]; /* Address Offset: 0x0E90 */ + __IO uint32_t AUTOCS_PCLK_VI_ROOT_CON[2]; /* Address Offset: 0x0E98 */ + __IO uint32_t AUTOCS_ACLK_VOP_LOW_ROOT_CON[2]; /* Address Offset: 0x0EA0 */ + __IO uint32_t AUTOCS_HCLK_VOP_ROOT_CON[2]; /* Address Offset: 0x0EA8 */ + __IO uint32_t AUTOCS_PCLK_VOP_ROOT_CON[2]; /* Address Offset: 0x0EB0 */ + __IO uint32_t AUTOCS_HCLK_VO0_ROOT_CON[2]; /* Address Offset: 0x0EB8 */ + __IO uint32_t AUTOCS_HCLK_VO0_S_ROOT_CON[2]; /* Address Offset: 0x0EC0 */ + __IO uint32_t AUTOCS_PCLK_VO0_ROOT_CON[2]; /* Address Offset: 0x0EC8 */ + __IO uint32_t AUTOCS_PCLK_VO0_S_ROOT_CON[2]; /* Address Offset: 0x0ED0 */ + __IO uint32_t AUTOCS_HCLK_VO1_ROOT_CON[2]; /* Address Offset: 0x0ED8 */ + __IO uint32_t AUTOCS_HCLK_VO1_S_ROOT_CON[2]; /* Address Offset: 0x0EE0 */ + __IO uint32_t AUTOCS_PCLK_VO1_ROOT_CON[2]; /* Address Offset: 0x0EE8 */ + __IO uint32_t AUTOCS_PCLK_VO1_S_ROOT_CON[2]; /* Address Offset: 0x0EF0 */ + __IO uint32_t AUTOCS_PCLK_GPU_ROOT_CON[2]; /* Address Offset: 0x0EF8 */ + __IO uint32_t AUTOCS_HCLK_CENTER_ROOT_CON[2]; /* Address Offset: 0x0F00 */ + __IO uint32_t AUTOCS_PCLK_CENTER_ROOT_CON[2]; /* Address Offset: 0x0F08 */ + __IO uint32_t AUTOCS_ACLK_CENTER_S200_ROOT_CON[2]; /* Address Offset: 0x0F10 */ + __IO uint32_t AUTOCS_HCLK_SDIO_ROOT_CON[2]; /* Address Offset: 0x0F18 */ + __IO uint32_t AUTOCS_HCLK_RGA3_ROOT_CON[2]; /* Address Offset: 0x0F20 */ + __IO uint32_t AUTOCS_HCLK_VO1USB_TOP_ROOT_CON[2]; /* Address Offset: 0x0F28 */ + __IO uint32_t AUTOCS_ACLK_TOP_M300_ROOT_CON[2]; /* Address Offset: 0x0F30 */ + __IO uint32_t AUTOCS_CLK_RKNN_DSU0_SRC_T_CON[2]; /* Address Offset: 0x0F38 */ + __IO uint32_t AUTOCS_HCLK_AUDIO_ROOT_CON[2]; /* Address Offset: 0x0F40 */ + __IO uint32_t AUTOCS_PCLK_AUDIO_ROOT_CON[2]; /* Address Offset: 0x0F48 */ +}; +/* PHPTOPCRU Register Structure Define */ +struct PHPTOPCRU_REG { + uint32_t RESERVED0000[128]; /* Address Offset: 0x0000 */ + __IO uint32_t PPLL_CON[7]; /* Address Offset: 0x0200 */ + uint32_t RESERVED021C[377]; /* Address Offset: 0x021C */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* SECURECRU Register Structure Define */ +struct SECURECRU_REG { + uint32_t RESERVED0000[192]; /* Address Offset: 0x0000 */ + __IO uint32_t CLKSEL_CON[4]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0310[316]; /* Address Offset: 0x0310 */ + __IO uint32_t GATE_CON[4]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0810[124]; /* Address Offset: 0x0810 */ + __IO uint32_t SOFTRST_CON[4]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A10[188]; /* Address Offset: 0x0A10 */ + __IO uint32_t AUTOCS_ACLK_SECURE_NS_ROOT_CON[2]; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_HCLK_SECURE_NS_ROOT_CON[2]; /* Address Offset: 0x0D08 */ + __IO uint32_t AUTOCS_ACLK_SECURE_S_ROOT_CON[2]; /* Address Offset: 0x0D10 */ + __IO uint32_t AUTOCS_HCLK_SECURE_S_ROOT_CON[2]; /* Address Offset: 0x0D18 */ + __IO uint32_t AUTOCS_PCLK_SECURE_S_ROOT_CON[2]; /* Address Offset: 0x0D20 */ +}; +/* SBUSCRU Register Structure Define */ +struct SBUSCRU_REG { + uint32_t RESERVED0000[136]; /* Address Offset: 0x0000 */ + __IO uint32_t SPLL_CON[6]; /* Address Offset: 0x0220 */ + uint32_t RESERVED0238[18]; /* Address Offset: 0x0238 */ + __IO uint32_t MODE_CON[1]; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[1]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0304[319]; /* Address Offset: 0x0304 */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* PMU1SCRU Register Structure Define */ +struct PMU1SCRU_REG { + uint32_t RESERVED0000[192]; /* Address Offset: 0x0000 */ + __IO uint32_t CLKSEL_CON[3]; /* Address Offset: 0x0300 */ + uint32_t RESERVED030C[317]; /* Address Offset: 0x030C */ + __IO uint32_t GATE_CON[2]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0808[126]; /* Address Offset: 0x0808 */ + __IO uint32_t SOFTRST_CON[2]; /* Address Offset: 0x0A00 */ +}; +/* PMU1CRU Register Structure Define */ +struct PMU1CRU_REG { + uint32_t RESERVED0000[192]; /* Address Offset: 0x0000 */ + __IO uint32_t CLKSEL_CON[18]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0348[302]; /* Address Offset: 0x0348 */ + __IO uint32_t GATE_CON[6]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0818[122]; /* Address Offset: 0x0818 */ + __IO uint32_t SOFTRST_CON[6]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A18[186]; /* Address Offset: 0x0A18 */ + __IO uint32_t AUTOCS_HCLK_PMU_CM0_ROOT_I_CON[2]; /* Address Offset: 0x0D00 */ +}; +/* DDR0CRU Register Structure Define */ +struct DDR0CRU_REG { + __IO uint32_t D0APLL_CON[7]; /* Address Offset: 0x0000 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t D0BPLL_CON[7]; /* Address Offset: 0x0020 */ + uint32_t RESERVED003C[177]; /* Address Offset: 0x003C */ + __IO uint32_t CLKSEL_CON[1]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0304[319]; /* Address Offset: 0x0304 */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* DDR1CRU Register Structure Define */ +struct DDR1CRU_REG { + __IO uint32_t D1APLL_CON[7]; /* Address Offset: 0x0000 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t D1BPLL_CON[7]; /* Address Offset: 0x0020 */ + uint32_t RESERVED003C[177]; /* Address Offset: 0x003C */ + __IO uint32_t CLKSEL_CON[1]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0304[319]; /* Address Offset: 0x0304 */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* DDR2CRU Register Structure Define */ +struct DDR2CRU_REG { + __IO uint32_t D2APLL_CON[7]; /* Address Offset: 0x0000 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t D2BPLL_CON[7]; /* Address Offset: 0x0020 */ + uint32_t RESERVED003C[177]; /* Address Offset: 0x003C */ + __IO uint32_t CLKSEL_CON[1]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0304[319]; /* Address Offset: 0x0304 */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* DDR3CRU Register Structure Define */ +struct DDR3CRU_REG { + __IO uint32_t D3APLL_CON[7]; /* Address Offset: 0x0000 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t D3BPLL_CON[7]; /* Address Offset: 0x0020 */ + uint32_t RESERVED003C[177]; /* Address Offset: 0x003C */ + __IO uint32_t CLKSEL_CON[1]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0304[319]; /* Address Offset: 0x0304 */ + __IO uint32_t GATE_CON[1]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON[1]; /* Address Offset: 0x0A00 */ +}; +/* BIGCORE0CRU Register Structure Define */ +struct BIGCORE0CRU_REG { + __IO uint32_t B0PLL_CON[6]; /* Address Offset: 0x0000 */ + uint32_t RESERVED0018[154]; /* Address Offset: 0x0018 */ + __IO uint32_t MODE_CON[1]; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[3]; /* Address Offset: 0x0300 */ + uint32_t RESERVED030C[317]; /* Address Offset: 0x030C */ + __IO uint32_t GATE_CON[2]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0808[126]; /* Address Offset: 0x0808 */ + __IO uint32_t SOFTRST_CON[2]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A08[174]; /* Address Offset: 0x0A08 */ + __IO uint32_t SMOTH_DIVFREE_CON[2]; /* Address Offset: 0x0CC0 */ + uint32_t RESERVED0CC8[14]; /* Address Offset: 0x0CC8 */ + __IO uint32_t AUTOCS_CLK_CORE_B01_I_CON[2]; /* Address Offset: 0x0D00 */ +}; +/* BIGCORE1CRU Register Structure Define */ +struct BIGCORE1CRU_REG { + uint32_t RESERVED0000[8]; /* Address Offset: 0x0000 */ + __IO uint32_t B1PLL_CON[6]; /* Address Offset: 0x0020 */ + uint32_t RESERVED0038[146]; /* Address Offset: 0x0038 */ + __IO uint32_t MODE_CON[1]; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[3]; /* Address Offset: 0x0300 */ + uint32_t RESERVED030C[317]; /* Address Offset: 0x030C */ + __IO uint32_t GATE_CON[2]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0808[126]; /* Address Offset: 0x0808 */ + __IO uint32_t SOFTRST_CON[2]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A08[174]; /* Address Offset: 0x0A08 */ + __IO uint32_t SMOTH_DIVFREE_CON[2]; /* Address Offset: 0x0CC0 */ + uint32_t RESERVED0CC8[14]; /* Address Offset: 0x0CC8 */ + __IO uint32_t AUTOCS_CLK_CORE_B23_I_CON[2]; /* Address Offset: 0x0D00 */ +}; +/* DSUCRU Register Structure Define */ +struct DSUCRU_REG { + uint32_t RESERVED0000[16]; /* Address Offset: 0x0000 */ + __IO uint32_t LPLL_CON[6]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0058[138]; /* Address Offset: 0x0058 */ + __IO uint32_t MODE_CON[1]; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[8]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0320[312]; /* Address Offset: 0x0320 */ + __IO uint32_t GATE_CON[4]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0810[124]; /* Address Offset: 0x0810 */ + __IO uint32_t SOFTRST_CON[4]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A10[188]; /* Address Offset: 0x0A10 */ + __IO uint32_t AUTOCS_ACLK_M_DSU_BIU_CON[2]; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_ACLK_S_DSU_BIU_CON[2]; /* Address Offset: 0x0D08 */ + __IO uint32_t AUTOCS_ACLK_MP_DSU_BIU_CON[2]; /* Address Offset: 0x0D10 */ + __IO uint32_t AUTOCS_SCLK_DSU_SRC_CON[2]; /* Address Offset: 0x0D18 */ + __IO uint32_t AUTOCS_CLK_CORE_L_CON[2]; /* Address Offset: 0x0D20 */ + uint32_t RESERVED0D28[118]; /* Address Offset: 0x0D28 */ + __IO uint32_t QCHANNEL_CON[1]; /* Address Offset: 0x0F00 */ + uint32_t RESERVED0F04[3]; /* Address Offset: 0x0F04 */ + __IO uint32_t SMOTH_DIVFREE_CON[4]; /* Address Offset: 0x0F10 */ +}; +/* I2C Register Structure Define */ +struct I2C_REG { + __IO uint32_t CON; /* Address Offset: 0x0000 */ + __IO uint32_t CLKDIV; /* Address Offset: 0x0004 */ + __IO uint32_t MRXADDR; /* Address Offset: 0x0008 */ + __IO uint32_t MRXRADDR; /* Address Offset: 0x000C */ + __IO uint32_t MTXCNT; /* Address Offset: 0x0010 */ + __IO uint32_t MRXCNT; /* Address Offset: 0x0014 */ + __IO uint32_t IEN; /* Address Offset: 0x0018 */ + __IO uint32_t IPD; /* Address Offset: 0x001C */ + __I uint32_t FCNT; /* Address Offset: 0x0020 */ + __IO uint32_t SCL_OE_DB; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[54]; /* Address Offset: 0x0028 */ + __IO uint32_t TXDATA[8]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0120[56]; /* Address Offset: 0x0120 */ + __I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */ + __I uint32_t ST; /* Address Offset: 0x0220 */ + __IO uint32_t DBGCTRL; /* Address Offset: 0x0224 */ + __IO uint32_t CON1; /* Address Offset: 0x0228 */ +}; +/* UART Register Structure Define */ +struct UART_REG { + union { + __I uint32_t RBR; /* Address Offset: 0x0000 */ + __IO uint32_t DLL; /* Address Offset: 0x0000 */ + __O uint32_t THR; /* Address Offset: 0x0000 */ + }; + union { + __IO uint32_t DLH; /* Address Offset: 0x0004 */ + __IO uint32_t IER; /* Address Offset: 0x0004 */ + }; + union { + __O uint32_t FCR; /* Address Offset: 0x0008 */ + __I uint32_t IIR; /* Address Offset: 0x0008 */ + }; + __IO uint32_t LCR; /* Address Offset: 0x000C */ + __IO uint32_t MCR; /* Address Offset: 0x0010 */ + __I uint32_t LSR; /* Address Offset: 0x0014 */ + __I uint32_t MSR; /* Address Offset: 0x0018 */ + __IO uint32_t SCR; /* Address Offset: 0x001C */ + uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */ + union { + __I uint32_t SRBR; /* Address Offset: 0x0030 */ + __O uint32_t STHR; /* Address Offset: 0x0030 */ + }; + uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */ + __IO uint32_t FAR; /* Address Offset: 0x0070 */ + __I uint32_t TFR; /* Address Offset: 0x0074 */ + __O uint32_t RFW; /* Address Offset: 0x0078 */ + __I uint32_t USR; /* Address Offset: 0x007C */ + __I uint32_t TFL; /* Address Offset: 0x0080 */ + __I uint32_t RFL; /* Address Offset: 0x0084 */ + __O uint32_t SRR; /* Address Offset: 0x0088 */ + __IO uint32_t SRTS; /* Address Offset: 0x008C */ + __IO uint32_t SBCR; /* Address Offset: 0x0090 */ + __IO uint32_t SDMAM; /* Address Offset: 0x0094 */ + __IO uint32_t SFE; /* Address Offset: 0x0098 */ + __IO uint32_t SRT; /* Address Offset: 0x009C */ + __IO uint32_t STET; /* Address Offset: 0x00A0 */ + __IO uint32_t HTX; /* Address Offset: 0x00A4 */ + __O uint32_t DMASA; /* Address Offset: 0x00A8 */ + uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */ + __I uint32_t CPR; /* Address Offset: 0x00F4 */ + __I uint32_t UCV; /* Address Offset: 0x00F8 */ + __I uint32_t CTR; /* Address Offset: 0x00FC */ +}; +/* GPIO Register Structure Define */ +struct GPIO_REG { + __IO uint32_t SWPORT_DR_L; /* Address Offset: 0x0000 */ + __IO uint32_t SWPORT_DR_H; /* Address Offset: 0x0004 */ + __IO uint32_t SWPORT_DDR_L; /* Address Offset: 0x0008 */ + __IO uint32_t SWPORT_DDR_H; /* Address Offset: 0x000C */ + __IO uint32_t INT_EN_L; /* Address Offset: 0x0010 */ + __IO uint32_t INT_EN_H; /* Address Offset: 0x0014 */ + __IO uint32_t INT_MASK_L; /* Address Offset: 0x0018 */ + __IO uint32_t INT_MASK_H; /* Address Offset: 0x001C */ + __IO uint32_t INT_TYPE_L; /* Address Offset: 0x0020 */ + __IO uint32_t INT_TYPE_H; /* Address Offset: 0x0024 */ + __IO uint32_t INT_POLARITY_L; /* Address Offset: 0x0028 */ + __IO uint32_t INT_POLARITY_H; /* Address Offset: 0x002C */ + __IO uint32_t INT_BOTHEDGE_L; /* Address Offset: 0x0030 */ + __IO uint32_t INT_BOTHEDGE_H; /* Address Offset: 0x0034 */ + __IO uint32_t DEBOUNCE_L; /* Address Offset: 0x0038 */ + __IO uint32_t DEBOUNCE_H; /* Address Offset: 0x003C */ + __IO uint32_t DBCLK_DIV_EN_L; /* Address Offset: 0x0040 */ + __IO uint32_t DBCLK_DIV_EN_H; /* Address Offset: 0x0044 */ + __IO uint32_t DBCLK_DIV_CON; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __I uint32_t INT_STATUS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054; /* Address Offset: 0x0054 */ + __I uint32_t INT_RAWSTATUS; /* Address Offset: 0x0058 */ + uint32_t RESERVED005C; /* Address Offset: 0x005C */ + __IO uint32_t PORT_EOI_L; /* Address Offset: 0x0060 */ + __IO uint32_t PORT_EOI_H; /* Address Offset: 0x0064 */ + uint32_t RESERVED0068[2]; /* Address Offset: 0x0068 */ + __I uint32_t EXT_PORT; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074; /* Address Offset: 0x0074 */ + __I uint32_t VER_ID; /* Address Offset: 0x0078 */ + uint32_t RESERVED007C[33]; /* Address Offset: 0x007C */ + __IO uint32_t GPIO_REG_GROUP_L; /* Address Offset: 0x0100 */ + __IO uint32_t GPIO_REG_GROUP_H; /* Address Offset: 0x0104 */ + __IO uint32_t GPIO_VIRTUAL_EN; /* Address Offset: 0x0108 */ +}; +/* PMU Register Structure Define */ +struct PMU_REG { + __IO uint32_t PWR_CON0; /* Address Offset: 0x0000 */ + uint32_t RESERVED0004; /* Address Offset: 0x0004 */ + __IO uint32_t WAKEUP_INT_CON_P0; /* Address Offset: 0x0008 */ + __I uint32_t WAKEUP_INT_STS_P0; /* Address Offset: 0x000C */ + __IO uint32_t PMIC_STABLE_CNT_P0; /* Address Offset: 0x0010 */ + __IO uint32_t WAKEUP_RST_CLR_CNT_P0; /* Address Offset: 0x0014 */ + __IO uint32_t OSC_STABLE_CNT_P0; /* Address Offset: 0x0018 */ + __IO uint32_t PMU1_PWR_CHAIN_STABLE_CON; /* Address Offset: 0x001C */ + __IO uint32_t DDR_RET_CON0_P0; /* Address Offset: 0x0020 */ + __IO uint32_t DDR_RET_CON1_P0; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ + __IO uint32_t INFO_TX_CON; /* Address Offset: 0x0030 */ + uint32_t RESERVED0034[4083]; /* Address Offset: 0x0034 */ + __I uint32_t VERSION; /* Address Offset: 0x4000 */ + __IO uint32_t PWR_CON1; /* Address Offset: 0x4004 */ + __I uint32_t GLB_POWER_STS; /* Address Offset: 0x4008 */ + __IO uint32_t INT_MASK_CON; /* Address Offset: 0x400C */ + __IO uint32_t WAKEUP_INT_CON; /* Address Offset: 0x4010 */ + __I uint32_t WAKEUP_INT_STS; /* Address Offset: 0x4014 */ + uint32_t RESERVED4018[2]; /* Address Offset: 0x4018 */ + __IO uint32_t DDR_CH0_PWR_CON; /* Address Offset: 0x4020 */ + __IO uint32_t DDR_CH1_PWR_CON; /* Address Offset: 0x4024 */ + __IO uint32_t DDR_CH2_PWR_CON; /* Address Offset: 0x4028 */ + __IO uint32_t DDR_CH3_PWR_CON; /* Address Offset: 0x402C */ + __IO uint32_t DDR_CH0_PWR_SFTCON; /* Address Offset: 0x4030 */ + __IO uint32_t DDR_CH1_PWR_SFTCON; /* Address Offset: 0x4034 */ + __IO uint32_t DDR_CH2_PWR_SFTCON; /* Address Offset: 0x4038 */ + __IO uint32_t DDR_CH3_PWR_SFTCON; /* Address Offset: 0x403C */ + __I uint32_t DDR_POWER_STS; /* Address Offset: 0x4040 */ + __I uint32_t DDR_STS; /* Address Offset: 0x4044 */ + uint32_t RESERVED4048[2]; /* Address Offset: 0x4048 */ + __IO uint32_t CRU_PWR_CON; /* Address Offset: 0x4050 */ + __IO uint32_t CRU_PWR_SFTCON; /* Address Offset: 0x4054 */ + __I uint32_t CRU_POWER_STS; /* Address Offset: 0x4058 */ + uint32_t RESERVED405C; /* Address Offset: 0x405C */ + __IO uint32_t PLLPD_CON0; /* Address Offset: 0x4060 */ + __IO uint32_t PLLPD_CON1; /* Address Offset: 0x4064 */ + __IO uint32_t PLLPD_SFTCON0; /* Address Offset: 0x4068 */ + __IO uint32_t PLLPD_SFTCON1; /* Address Offset: 0x406C */ + uint32_t RESERVED4070[4]; /* Address Offset: 0x4070 */ + __IO uint32_t PMIC_STABLE_CNT; /* Address Offset: 0x4080 */ + __IO uint32_t OSC_STABLE_CNT; /* Address Offset: 0x4084 */ + __IO uint32_t WAKEUP_RST_CLR_CNT; /* Address Offset: 0x4088 */ + __IO uint32_t PLL_LOCK_CNT; /* Address Offset: 0x408C */ + uint32_t RESERVED4090; /* Address Offset: 0x4090 */ + __IO uint32_t WAKEUP_TIMEOUT_CNT; /* Address Offset: 0x4094 */ + __IO uint32_t PWM_SWITCH_CNT; /* Address Offset: 0x4098 */ + uint32_t RESERVED409C[25]; /* Address Offset: 0x409C */ + __IO uint32_t SYS_REG0; /* Address Offset: 0x4100 */ + __IO uint32_t SYS_REG1; /* Address Offset: 0x4104 */ + __IO uint32_t SYS_REG2; /* Address Offset: 0x4108 */ + __IO uint32_t SYS_REG3; /* Address Offset: 0x410C */ + __IO uint32_t SYS_REG4; /* Address Offset: 0x4110 */ + __IO uint32_t SYS_REG5; /* Address Offset: 0x4114 */ + __IO uint32_t SYS_REG6; /* Address Offset: 0x4118 */ + __IO uint32_t SYS_REG7; /* Address Offset: 0x411C */ + uint32_t RESERVED4120[4024]; /* Address Offset: 0x4120 */ + __IO uint32_t PWR_CON2; /* Address Offset: 0x8000 */ + __IO uint32_t DSU_PWR_CON; /* Address Offset: 0x8004 */ + __IO uint32_t DSU_PWR_SFTCON; /* Address Offset: 0x8008 */ + __IO uint32_t DSU_AUTO_PWR_CON; /* Address Offset: 0x800C */ + __IO uint32_t CPU0_AUTO_PWR_CON; /* Address Offset: 0x8010 */ + __IO uint32_t CPU1_AUTO_PWR_CON; /* Address Offset: 0x8014 */ + __IO uint32_t CPU2_AUTO_PWR_CON; /* Address Offset: 0x8018 */ + __IO uint32_t CPU3_AUTO_PWR_CON; /* Address Offset: 0x801C */ + __IO uint32_t CPU4_AUTO_PWR_CON; /* Address Offset: 0x8020 */ + __IO uint32_t CPU5_AUTO_PWR_CON; /* Address Offset: 0x8024 */ + __IO uint32_t CPU6_AUTO_PWR_CON; /* Address Offset: 0x8028 */ + __IO uint32_t CPU7_AUTO_PWR_CON; /* Address Offset: 0x802C */ + __IO uint32_t CPU0_PWR_SFTCON; /* Address Offset: 0x8030 */ + __IO uint32_t CPU1_PWR_SFTCON; /* Address Offset: 0x8034 */ + __IO uint32_t CPU2_PWR_SFTCON; /* Address Offset: 0x8038 */ + __IO uint32_t CPU3_PWR_SFTCON; /* Address Offset: 0x803C */ + __IO uint32_t CPU4_PWR_SFTCON; /* Address Offset: 0x8040 */ + __IO uint32_t CPU5_PWR_SFTCON; /* Address Offset: 0x8044 */ + __IO uint32_t CPU6_PWR_SFTCON; /* Address Offset: 0x8048 */ + __IO uint32_t CPU7_PWR_SFTCON; /* Address Offset: 0x804C */ + __IO uint32_t CORE0_PWR_CON; /* Address Offset: 0x8050 */ + __IO uint32_t CORE1_PWR_CON; /* Address Offset: 0x8054 */ + __IO uint32_t CORE0_PWR_SFTCON; /* Address Offset: 0x8058 */ + __IO uint32_t CORE1_PWR_SFTCON; /* Address Offset: 0x805C */ + __IO uint32_t CORE0_AUTO_PWR_CON; /* Address Offset: 0x8060 */ + __IO uint32_t CORE1_AUTO_PWR_CON; /* Address Offset: 0x8064 */ + __IO uint32_t CLUSTER_BIU_AUTO_CON; /* Address Offset: 0x8068 */ + uint32_t RESERVED806C; /* Address Offset: 0x806C */ + __IO uint32_t CLUSTER_BIU_IDLE_CON; /* Address Offset: 0x8070 */ + __IO uint32_t CLUSTER_BIU_IDLE_SFTCON; /* Address Offset: 0x8074 */ + __I uint32_t CLUSTER_BIU_IDLE_ACK_STS; /* Address Offset: 0x8078 */ + __I uint32_t CLUSTER_BIU_IDLE_STS; /* Address Offset: 0x807C */ + __I uint32_t CLUSTER_STS; /* Address Offset: 0x8080 */ + __I uint32_t CLUSTER_POWER_STS0; /* Address Offset: 0x8084 */ + __I uint32_t CLUSTER_POWER_STS1; /* Address Offset: 0x8088 */ + __I uint32_t CLUSTER_PCHANNEL_STS0; /* Address Offset: 0x808C */ + __I uint32_t CLUSTER_PCHANNEL_STS1; /* Address Offset: 0x8090 */ + __I uint32_t CLUSTER_PCHANNEL_STS2; /* Address Offset: 0x8094 */ + __IO uint32_t CPU_PWR_CHAIN_STABLE_CON; /* Address Offset: 0x8098 */ + __IO uint32_t DSU_MEM_PWR_CON; /* Address Offset: 0x809C */ + uint32_t RESERVED80A0[4]; /* Address Offset: 0x80A0 */ + __IO uint32_t DSU_STABLE_CNT; /* Address Offset: 0x80B0 */ + __IO uint32_t DSU_PWRUP_CNT; /* Address Offset: 0x80B4 */ + __IO uint32_t DSU_PWRDN_CNT; /* Address Offset: 0x80B8 */ + __IO uint32_t CORE0_STABLE_CNT; /* Address Offset: 0x80BC */ + __IO uint32_t CORE0_PWRUP_CNT; /* Address Offset: 0x80C0 */ + __IO uint32_t CORE0_PWRDN_CNT; /* Address Offset: 0x80C4 */ + __IO uint32_t CORE1_STABLE_CNT; /* Address Offset: 0x80C8 */ + __IO uint32_t CORE1_PWRUP_CNT; /* Address Offset: 0x80CC */ + __IO uint32_t CORE1_PWRDN_CNT; /* Address Offset: 0x80D0 */ + __IO uint32_t CPU0_DBG_RST_CNT; /* Address Offset: 0x80D4 */ + __IO uint32_t CPU1_DBG_RST_CNT; /* Address Offset: 0x80D8 */ + __IO uint32_t CPU2_DBG_RST_CNT; /* Address Offset: 0x80DC */ + __IO uint32_t CPU3_DBG_RST_CNT; /* Address Offset: 0x80E0 */ + __IO uint32_t CPU4_DBG_RST_CNT; /* Address Offset: 0x80E4 */ + __IO uint32_t CPU5_DBG_RST_CNT; /* Address Offset: 0x80E8 */ + __IO uint32_t CPU6_DBG_RST_CNT; /* Address Offset: 0x80EC */ + __IO uint32_t CPU7_DBG_RST_CNT; /* Address Offset: 0x80F0 */ + uint32_t RESERVED80F4[3]; /* Address Offset: 0x80F4 */ + __IO uint32_t BIU_IDLE_CON0; /* Address Offset: 0x8100 */ + __IO uint32_t BIU_IDLE_CON1; /* Address Offset: 0x8104 */ + __IO uint32_t BIU_IDLE_CON2; /* Address Offset: 0x8108 */ + __IO uint32_t BUS_IDLE_REQ[3]; /* Address Offset: 0x810C */ + __I uint32_t BUS_IDLE_ACK[2]; /* Address Offset: 0x8118 */ + __I uint32_t BUS_IDLE_ST[2]; /* Address Offset: 0x8120 */ + __IO uint32_t BIU_AUTO_CON0; /* Address Offset: 0x8128 */ + __IO uint32_t BIU_AUTO_CON1; /* Address Offset: 0x812C */ + __IO uint32_t BIU_AUTO_CON2; /* Address Offset: 0x8130 */ + uint32_t RESERVED8134[3]; /* Address Offset: 0x8134 */ + __IO uint32_t PWR_GATE_CON0; /* Address Offset: 0x8140 */ + __IO uint32_t PWR_GATE_CON1; /* Address Offset: 0x8144 */ + __IO uint32_t PWR_GATE_CON2; /* Address Offset: 0x8148 */ + __IO uint32_t PWRDN_CON[3]; /* Address Offset: 0x814C */ + __IO uint32_t VOL_GATE_CON0; /* Address Offset: 0x8158 */ + uint32_t RESERVED815C; /* Address Offset: 0x815C */ + __IO uint32_t VOL_GATE_CON1; /* Address Offset: 0x8160 */ + __IO uint32_t PWR_CHAIN_PWRUP_CON0; /* Address Offset: 0x8164 */ + __IO uint32_t PWR_CHAIN_PWRUP_CON1; /* Address Offset: 0x8168 */ + uint32_t RESERVED816C; /* Address Offset: 0x816C */ + __IO uint32_t PWR_CHAIN_PWRDN_CON0; /* Address Offset: 0x8170 */ + __IO uint32_t PWR_CHAIN_PWRDN_CON1; /* Address Offset: 0x8174 */ + uint32_t RESERVED8178; /* Address Offset: 0x8178 */ + __IO uint32_t PWR_STABLE_CNT; /* Address Offset: 0x817C */ + __I uint32_t PWRDN_ST[2]; /* Address Offset: 0x8180 */ + __I uint32_t PWR_GATE_POWER_STS; /* Address Offset: 0x8188 */ + __IO uint32_t VOL_GATE_FAST_CON; /* Address Offset: 0x818C */ + __IO uint32_t GPU_PWRUP_CNT; /* Address Offset: 0x8190 */ + __IO uint32_t GPU_PWRDN_CNT; /* Address Offset: 0x8194 */ + __IO uint32_t NPU_PWRUP_CNT; /* Address Offset: 0x8198 */ + __IO uint32_t NPU_PWRDN_CNT; /* Address Offset: 0x819C */ + __IO uint32_t PWR_MEM_CON[3]; /* Address Offset: 0x81A0 */ + uint32_t RESERVED81AC; /* Address Offset: 0x81AC */ + __IO uint32_t SUBMEM_PWR_GATE_SFTCON0; /* Address Offset: 0x81B0 */ + __IO uint32_t SUBMEM_PWR_GATE_SFTCON1; /* Address Offset: 0x81B4 */ + __IO uint32_t SUBMEM_PWR_GATE_SFTCON2; /* Address Offset: 0x81B8 */ + __I uint32_t SUBMEM_PWR_GATE_STS; /* Address Offset: 0x81BC */ + __IO uint32_t SUBMEM_PWR_ACK_BYPASS_CON0; /* Address Offset: 0x81C0 */ + __IO uint32_t SUBMEM_PWR_ACK_BYPASS_CON1; /* Address Offset: 0x81C4 */ + uint32_t RESERVED81C8[2]; /* Address Offset: 0x81C8 */ + __IO uint32_t QCHANNEL_PWR_CON; /* Address Offset: 0x81D0 */ + __IO uint32_t QCHANNEL_PWR_SFTCON; /* Address Offset: 0x81D4 */ + __I uint32_t QCHANNEL_PWR_STS; /* Address Offset: 0x81D8 */ + uint32_t RESERVED81DC; /* Address Offset: 0x81DC */ + __IO uint32_t DEBUG_INFO_CON; /* Address Offset: 0x81E0 */ + __I uint32_t VOP_SUBPD_PWR_CHAIN_STS; /* Address Offset: 0x81E4 */ + __I uint32_t PWR_CHAIN0_ST[2]; /* Address Offset: 0x81E8 */ + __I uint32_t PWR_CHAIN1_ST[2]; /* Address Offset: 0x81F0 */ + __I uint32_t PWR_MEM_ST[2]; /* Address Offset: 0x81F8 */ + __IO uint32_t BISR_CON0; /* Address Offset: 0x8200 */ + __IO uint32_t BISR_CON1; /* Address Offset: 0x8204 */ + __IO uint32_t BISR_CON2; /* Address Offset: 0x8208 */ + __IO uint32_t BISR_CON3; /* Address Offset: 0x820C */ + __IO uint32_t BISR_CON4; /* Address Offset: 0x8210 */ + __IO uint32_t BISR_CON5; /* Address Offset: 0x8214 */ + __IO uint32_t BISR_CON6; /* Address Offset: 0x8218 */ + __IO uint32_t BISR_CON7; /* Address Offset: 0x821C */ + __IO uint32_t BISR_CON8; /* Address Offset: 0x8220 */ + __IO uint32_t BISR_CON9; /* Address Offset: 0x8224 */ + __IO uint32_t BISR_CON10; /* Address Offset: 0x8228 */ + __IO uint32_t BISR_CON11; /* Address Offset: 0x822C */ + __IO uint32_t BISR_CON12; /* Address Offset: 0x8230 */ + __IO uint32_t BISR_CON13; /* Address Offset: 0x8234 */ + __IO uint32_t BISR_CON14; /* Address Offset: 0x8238 */ + uint32_t RESERVED823C[17]; /* Address Offset: 0x823C */ + __I uint32_t BISR_STS0; /* Address Offset: 0x8280 */ + __I uint32_t BISR_STS1; /* Address Offset: 0x8284 */ + __I uint32_t BISR_STS2; /* Address Offset: 0x8288 */ + __I uint32_t BISR_STS3; /* Address Offset: 0x828C */ + __I uint32_t PWR_REPAIR_ST[2]; /* Address Offset: 0x8290 */ +}; +/* CAN Register Structure Define */ +struct CAN_REG { + __IO uint32_t MODE; /* Address Offset: 0x0000 */ + __IO uint32_t CMD; /* Address Offset: 0x0004 */ + __I uint32_t STATE; /* Address Offset: 0x0008 */ + __IO uint32_t INT; /* Address Offset: 0x000C */ + __IO uint32_t INT_MASK0; /* Address Offset: 0x0010 */ + __IO uint32_t DMA_CTRL; /* Address Offset: 0x0014 */ + __IO uint32_t BITTIMING; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C[3]; /* Address Offset: 0x001C */ + __I uint32_t ARBITFAIL; /* Address Offset: 0x0028 */ + __IO uint32_t ERROR_CODE; /* Address Offset: 0x002C */ + uint32_t RESERVED0030; /* Address Offset: 0x0030 */ + __I uint32_t RXERRORCNT; /* Address Offset: 0x0034 */ + __I uint32_t TXERRORCNT; /* Address Offset: 0x0038 */ + __IO uint32_t IDCODE; /* Address Offset: 0x003C */ + __IO uint32_t IDMASK; /* Address Offset: 0x0040 */ + uint32_t RESERVED0044[3]; /* Address Offset: 0x0044 */ + __IO uint32_t TXFRAMEINFO; /* Address Offset: 0x0050 */ + __IO uint32_t TXID; /* Address Offset: 0x0054 */ + __IO uint32_t TXDATA0; /* Address Offset: 0x0058 */ + __IO uint32_t TXDATA1; /* Address Offset: 0x005C */ + __I uint32_t RXFRAMEINFO; /* Address Offset: 0x0060 */ + __I uint32_t RXID; /* Address Offset: 0x0064 */ + __I uint32_t RXDATA0; /* Address Offset: 0x0068 */ + __I uint32_t RXDATA1; /* Address Offset: 0x006C */ + __I uint32_t RTL_VERSION; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074[35]; /* Address Offset: 0x0074 */ + __IO uint32_t FD_NOMINAL_BITTIMING; /* Address Offset: 0x0100 */ + __IO uint32_t FD_DATA_BITTIMING; /* Address Offset: 0x0104 */ + __IO uint32_t TRANSMIT_DELAY_COMPENSATION; /* Address Offset: 0x0108 */ + __IO uint32_t TIMESTAMP_CTRL; /* Address Offset: 0x010C */ + __IO uint32_t TIMESTAMP; /* Address Offset: 0x0110 */ + __IO uint32_t TXEVENT_FIFO_CTRL; /* Address Offset: 0x0114 */ + __IO uint32_t RX_FIFO_CTRL; /* Address Offset: 0x0118 */ + __IO uint32_t AFR_CTRL; /* Address Offset: 0x011C */ + __IO uint32_t IDCODE0; /* Address Offset: 0x0120 */ + __IO uint32_t IDMASK0; /* Address Offset: 0x0124 */ + __IO uint32_t IDCODE1; /* Address Offset: 0x0128 */ + __IO uint32_t IDMASK1; /* Address Offset: 0x012C */ + __IO uint32_t IDCODE2; /* Address Offset: 0x0130 */ + __IO uint32_t IDMASK2; /* Address Offset: 0x0134 */ + __IO uint32_t IDCODE3; /* Address Offset: 0x0138 */ + __IO uint32_t IDMASK3; /* Address Offset: 0x013C */ + __IO uint32_t IDCODE4; /* Address Offset: 0x0140 */ + __IO uint32_t IDMASK4; /* Address Offset: 0x0144 */ + uint32_t RESERVED0148[46]; /* Address Offset: 0x0148 */ + __IO uint32_t FD_TXFRAMEINFO; /* Address Offset: 0x0200 */ + __IO uint32_t FD_TXID; /* Address Offset: 0x0204 */ + __IO uint32_t FD_TXDATA[16]; /* Address Offset: 0x0208 */ + uint32_t RESERVED0248[46]; /* Address Offset: 0x0248 */ + __IO uint32_t FD_RXFRAMEINFO; /* Address Offset: 0x0300 */ + __I uint32_t FD_RXID; /* Address Offset: 0x0304 */ + __I uint32_t FD_RXTIMESTAMP; /* Address Offset: 0x0308 */ + __I uint32_t FD_RXDATA[16]; /* Address Offset: 0x030C */ + uint32_t RESERVED034C[45]; /* Address Offset: 0x034C */ + __I uint32_t RX_FIFO_RDATA; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[63]; /* Address Offset: 0x0404 */ + __I uint32_t TXE_FIFO_RDATA; /* Address Offset: 0x0500 */ +}; +/* WDT Register Structure Define */ +struct WDT_REG { + __IO uint32_t CR; /* Address Offset: 0x0000 */ + __IO uint32_t TORR; /* Address Offset: 0x0004 */ + __I uint32_t CCVR; /* Address Offset: 0x0008 */ + __O uint32_t CRR; /* Address Offset: 0x000C */ + __I uint32_t STAT; /* Address Offset: 0x0010 */ + __I uint32_t EOI; /* Address Offset: 0x0014 */ +}; +/* SPI Register Structure Define */ +struct SPI_REG { + __IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */ + __IO uint32_t ENR; /* Address Offset: 0x0008 */ + __IO uint32_t SER; /* Address Offset: 0x000C */ + __IO uint32_t BAUDR; /* Address Offset: 0x0010 */ + __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ + __IO uint32_t RXFTLR; /* Address Offset: 0x0018 */ + __I uint32_t TXFLR; /* Address Offset: 0x001C */ + __I uint32_t RXFLR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __IO uint32_t IPR; /* Address Offset: 0x0028 */ + __IO uint32_t IMR; /* Address Offset: 0x002C */ + __IO uint32_t ISR; /* Address Offset: 0x0030 */ + __IO uint32_t RISR; /* Address Offset: 0x0034 */ + __O uint32_t ICR; /* Address Offset: 0x0038 */ + __IO uint32_t DMACR; /* Address Offset: 0x003C */ + __IO uint32_t DMATDLR; /* Address Offset: 0x0040 */ + __IO uint32_t DMARDLR; /* Address Offset: 0x0044 */ + __I uint32_t VERSION; /* Address Offset: 0x0048 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t BYPASS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */ + __O uint32_t TXDR; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */ + __I uint32_t RXDR; /* Address Offset: 0x0800 */ +}; +/* PDM Register Structure Define */ +struct PDM_REG { + __IO uint32_t SYSCONFIG; /* Address Offset: 0x0000 */ + __IO uint32_t CTRL[2]; /* Address Offset: 0x0004 */ + __IO uint32_t CLK_CTRL; /* Address Offset: 0x000C */ + __IO uint32_t HPF_CTRL; /* Address Offset: 0x0010 */ + __IO uint32_t FIFO_CTRL; /* Address Offset: 0x0014 */ + __IO uint32_t DMA_CTRL; /* Address Offset: 0x0018 */ + __IO uint32_t INT_EN; /* Address Offset: 0x001C */ + __IO uint32_t INT_CLR; /* Address Offset: 0x0020 */ + __I uint32_t INT_ST; /* Address Offset: 0x0024 */ + uint32_t RESERVED0028[2]; /* Address Offset: 0x0028 */ + __I uint32_t RXFIFO_DATA_REG; /* Address Offset: 0x0030 */ + __I uint32_t DATA0R_REG; /* Address Offset: 0x0034 */ + __I uint32_t DATA0L_REG; /* Address Offset: 0x0038 */ + __I uint32_t DATA1R_REG; /* Address Offset: 0x003C */ + __I uint32_t DATA1L_REG; /* Address Offset: 0x0040 */ + __I uint32_t DATA2R_REG; /* Address Offset: 0x0044 */ + __I uint32_t DATA2L_REG; /* Address Offset: 0x0048 */ + __I uint32_t DATA3R_REG; /* Address Offset: 0x004C */ + __I uint32_t DATA3L_REG; /* Address Offset: 0x0050 */ + __I uint32_t DATA_VALID; /* Address Offset: 0x0054 */ + __I uint32_t VERSION; /* Address Offset: 0x0058 */ + uint32_t RESERVED005C[233]; /* Address Offset: 0x005C */ + __I uint32_t INCR_RXDR; /* Address Offset: 0x0400 */ +}; +/* VAD Register Structure Define */ +struct VAD_REG { + __IO uint32_t CONTROL; /* Address Offset: 0x0000 */ + __IO uint32_t VS_ADDR; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[17]; /* Address Offset: 0x0008 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t RAM_START_ADDR; /* Address Offset: 0x0050 */ + __IO uint32_t RAM_END_ADDR; /* Address Offset: 0x0054 */ + __IO uint32_t RAM_CUR_ADDR; /* Address Offset: 0x0058 */ + __IO uint32_t DET_CON[6]; /* Address Offset: 0x005C */ + __IO uint32_t INT; /* Address Offset: 0x0074 */ + __IO uint32_t AUX_CON0; /* Address Offset: 0x0078 */ + __I uint32_t SAMPLE_CNT; /* Address Offset: 0x007C */ + __IO uint32_t RAM_START_ADDR_BUS; /* Address Offset: 0x0080 */ + __IO uint32_t RAM_END_ADDR_BUS; /* Address Offset: 0x0084 */ + __IO uint32_t RAM_CUR_ADDR_BUS; /* Address Offset: 0x0088 */ + __IO uint32_t AUX_CON1; /* Address Offset: 0x008C */ + uint32_t RESERVED0090[28]; /* Address Offset: 0x0090 */ + __IO uint32_t NOISE_FIRST_DATA; /* Address Offset: 0x0100 */ + uint32_t RESERVED0104[126]; /* Address Offset: 0x0104 */ + __IO uint32_t NOISE_LAST_DATA; /* Address Offset: 0x02FC */ +}; +/* DMA Register Structure Define */ +struct DMA_CHANNEL_STATUS { + __I uint32_t CSR; + __I uint32_t CPC; +}; +struct DMA_CHANNEL_CONFIG { + __I uint32_t SAR; + __I uint32_t DAR; + __I uint32_t CCR; + __I uint32_t LC0; + __I uint32_t LC1; + __I uint32_t PADDING[3]; +}; +struct DMA_REG { + __I uint32_t DSR; /* Address Offset: 0x0000 */ + __I uint32_t DPC; /* Address Offset: 0x0004 */ + uint32_t RESERVED0008[6]; /* Address Offset: 0x0008 */ + __IO uint32_t INTEN; /* Address Offset: 0x0020 */ + __I uint32_t EVENT_RIS; /* Address Offset: 0x0024 */ + __I uint32_t INTMIS; /* Address Offset: 0x0028 */ + __O uint32_t INTCLR; /* Address Offset: 0x002C */ + __I uint32_t FSRD; /* Address Offset: 0x0030 */ + __I uint32_t FSRC; /* Address Offset: 0x0034 */ + __IO uint32_t FTRD; /* Address Offset: 0x0038 */ + uint32_t RESERVED003C; /* Address Offset: 0x003C */ + __I uint32_t FTR[6]; /* Address Offset: 0x0040 */ + uint32_t RESERVED0058[42]; /* Address Offset: 0x0058 */ + struct DMA_CHANNEL_STATUS CHAN_STS[6]; /* Address Offset: 0x0100 */ + uint32_t RESERVED0130[180]; /* Address Offset: 0x0130 */ + struct DMA_CHANNEL_CONFIG CHAN_CFG[6]; /* Address Offset: 0x0400 */ + uint32_t RESERVED04C0[528]; /* Address Offset: 0x04C0 */ + __I uint32_t DBGSTATUS; /* Address Offset: 0x0D00 */ + __O uint32_t DBGCMD; /* Address Offset: 0x0D04 */ + __O uint32_t DBGINST[2]; /* Address Offset: 0x0D08 */ + uint32_t RESERVED0D10[60]; /* Address Offset: 0x0D10 */ + __I uint32_t CR[5]; /* Address Offset: 0x0E00 */ + __I uint32_t CRDn; /* Address Offset: 0x0E14 */ + uint32_t RESERVED0E18[26]; /* Address Offset: 0x0E18 */ + __IO uint32_t WD; /* Address Offset: 0x0E80 */ +}; +/* TIMER Register Structure Define */ +struct TIMER_REG { + __IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */ + __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */ + __IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */ + uint32_t RESERVED0014; /* Address Offset: 0x0014 */ + __IO uint32_t INTSTATUS; /* Address Offset: 0x0018 */ +}; +/* MBOX Register Structure Define */ +struct MBOX_CMD_DAT { + __IO uint32_t CMD; + __IO uint32_t DATA; +}; +struct MBOX_REG { + __IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */ + __IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */ + struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */ + __IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */ + __IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */ + struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */ + uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */ + __IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */ +}; +#endif /* __ASSEMBLY__ */ +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define DCACHE_BASE 0xF6F10000U /* DCACHE base address */ +#define ICACHE_BASE 0xF6F10000U /* ICACHE base address */ +#define PMU1_IOC_BASE 0xFD5F0000U /* PMU1_IOC base address */ +#define PMU2_IOC_BASE 0xFD5F4000U /* PMU2_IOC base address */ +#define BUS_IOC_BASE 0xFD5F8000U /* BUS_IOC base address */ +#define VCCIO1_4_IOC_BASE 0xFD5F9000U /* VCCIO1_4_IOC base address */ +#define VCCIO3_5_IOC_BASE 0xFD5FA000U /* VCCIO3_5_IOC base address */ +#define VCCIO2_IOC_BASE 0xFD5FB000U /* VCCIO2_IOC base address */ +#define VCCIO6_IOC_BASE 0xFD5FC000U /* VCCIO6_IOC base address */ +#define EMMC_IOC_BASE 0xFD5FD000U /* EMMC_IOC base address */ +#define CRU_BASE 0xFD7C0000U /* CRU base address */ +#define PHPTOPCRU_BASE 0xFD7C8000U /* PHPTOPCRU base address */ +#define SECURECRU_BASE 0xFD7D0000U /* SECURECRU base address */ +#define SBUSCRU_BASE 0xFD7D8000U /* SBUSCRU base address */ +#define PMU1SCRU_BASE 0xFD7E0000U /* PMU1SCRU base address */ +#define PMU1CRU_BASE 0xFD7F0000U /* PMU1CRU base address */ +#define DDR0CRU_BASE 0xFD800000U /* DDR0CRU base address */ +#define DDR1CRU_BASE 0xFD804000U /* DDR1CRU base address */ +#define DDR2CRU_BASE 0xFD808000U /* DDR2CRU base address */ +#define DDR3CRU_BASE 0xFD80C000U /* DDR3CRU base address */ +#define BIGCORE0CRU_BASE 0xFD810000U /* BIGCORE0CRU base address */ +#define BIGCORE1CRU_BASE 0xFD812000U /* BIGCORE1CRU base address */ +#define DSUCRU_BASE 0xFD818000U /* DSUCRU base address */ +#define I2C0_BASE 0xFD880000U /* I2C0 base address */ +#define UART0_BASE 0xFD890000U /* UART0 base address */ +#define GPIO0_BASE 0xFD8A0000U /* GPIO0 base address */ +#define GPIO0_EXP_BASE 0xFD8A1000U /* GPIO0_EXP OSB base address */ +#define PMU_BASE 0xFD8D0000U /* PMU base address */ +#define WDT_BASE 0xFD8E0000U /* WDT base address */ +#define PDM0_BASE 0xFE4B0000U /* PDM0 base address */ +#define PDM1_BASE 0xFE4C0000U /* PDM1 base address */ +#define VAD_BASE 0xFE4D0000U /* VAD base address */ +#define DMA0_BASE 0xFEA10000U /* DMA0 base address */ +#define DMA1_BASE 0xFEA30000U /* DMA1 base address */ +#define CAN0_BASE 0xFEA50000U /* CAN0 base address */ +#define CAN1_BASE 0xFEA60000U /* CAN1 base address */ +#define CAN2_BASE 0xFEA70000U /* CAN2 base address */ +#define I2C1_BASE 0xFEA90000U /* I2C1 base address */ +#define I2C2_BASE 0xFEAA0000U /* I2C2 base address */ +#define I2C3_BASE 0xFEAB0000U /* I2C3 base address */ +#define I2C4_BASE 0xFEAC0000U /* I2C4 base address */ +#define I2C5_BASE 0xFEAD0000U /* I2C5 base address */ +#define TIMER0_BASE 0xFEAE0000U /* TIMER0 base address */ +#define TIMER1_BASE 0xFEAE0020U /* TIMER1 base address */ +#define TIMER2_BASE 0xFEAE0040U /* TIMER2 base address */ +#define TIMER3_BASE 0xFEAE0060U /* TIMER3 base address */ +#define TIMER4_BASE 0xFEAE0080U /* TIMER4 base address */ +#define TIMER5_BASE 0xFEAE00A0U /* TIMER5 base address */ +#define TIMER6_BASE 0xFEAE8000U /* TIMER6 base address */ +#define TIMER7_BASE 0xFEAE8020U /* TIMER7 base address */ +#define TIMER8_BASE 0xFEAE8040U /* TIMER8 base address */ +#define TIMER9_BASE 0xFEAE8060U /* TIMER9 base address */ +#define TIMER10_BASE 0xFEAE8080U /* TIMER10 base address */ +#define TIMER11_BASE 0xFEAE80A0U /* TIMER11 base address */ +#define SPI0_BASE 0xFEB00000U /* SPI0 base address */ +#define SPI1_BASE 0xFEB10000U /* SPI1 base address */ +#define SPI2_BASE 0xFEB20000U /* SPI2 base address */ +#define SPI3_BASE 0xFEB30000U /* SPI3 base address */ +#define UART1_BASE 0xFEB40000U /* UART1 base address */ +#define UART2_BASE 0xFEB50000U /* UART2 base address */ +#define UART3_BASE 0xFEB60000U /* UART3 base address */ +#define UART4_BASE 0xFEB70000U /* UART4 base address */ +#define UART5_BASE 0xFEB80000U /* UART5 base address */ +#define UART6_BASE 0xFEB90000U /* UART6 base address */ +#define UART7_BASE 0xFEBA0000U /* UART7 base address */ +#define UART8_BASE 0xFEBB0000U /* UART8 base address */ +#define UART9_BASE 0xFEBC0000U /* UART9 base address */ +#define GPIO1_BASE 0xFEC20000U /* GPIO1 base address */ +#define GPIO1_EXP_BASE 0xFEC21000U /* GPIO1_EXP OSB base address */ +#define GPIO2_BASE 0xFEC30000U /* GPIO2 base address */ +#define GPIO2_EXP_BASE 0xFEC31000U /* GPIO2_EXP OSB base address */ +#define GPIO3_BASE 0xFEC40000U /* GPIO3 base address */ +#define GPIO3_EXP_BASE 0xFEC41000U /* GPIO3_EXP OSB base address */ +#define GPIO4_BASE 0xFEC50000U /* GPIO4 base address */ +#define GPIO4_EXP_BASE 0xFEC51000U /* GPIO4_EXP OSB base address */ +#define MBOX0_BASE 0xFEC60000U /* MBOX0 base address */ +#define I2C6_BASE 0xFEC80000U /* I2C6 base address */ +#define I2C7_BASE 0xFEC90000U /* I2C7 base address */ +#define I2C8_BASE 0xFECA0000U /* I2C8 base address */ + +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ + +#define DCACHE ((struct DCACHE_REG *) DCACHE_BASE) +#define ICACHE ((struct ICACHE_REG *) ICACHE_BASE) +#define PMU1_IOC ((struct PMU1_IOC_REG *) PMU1_IOC_BASE) +#define PMU2_IOC ((struct PMU2_IOC_REG *) PMU2_IOC_BASE) +#define BUS_IOC ((struct BUS_IOC_REG *) BUS_IOC_BASE) +#define VCCIO1_4_IOC ((struct VCCIO1_4_IOC_REG *) VCCIO1_4_IOC_BASE) +#define VCCIO3_5_IOC ((struct VCCIO3_5_IOC_REG *) VCCIO3_5_IOC_BASE) +#define VCCIO2_IOC ((struct VCCIO2_IOC_REG *) VCCIO2_IOC_BASE) +#define VCCIO6_IOC ((struct VCCIO6_IOC_REG *) VCCIO6_IOC_BASE) +#define EMMC_IOC ((struct EMMC_IOC_REG *) EMMC_IOC_BASE) +#define CRU ((struct CRU_REG *) CRU_BASE) +#define PHPTOPCRU ((struct PHPTOPCRU_REG *) PHPTOPCRU_BASE) +#define SECURECRU ((struct SECURECRU_REG *) SECURECRU_BASE) +#define SBUSCRU ((struct SBUSCRU_REG *) SBUSCRU_BASE) +#define PMU1SCRU ((struct PMU1SCRU_REG *) PMU1SCRU_BASE) +#define PMU1CRU ((struct PMU1CRU_REG *) PMU1CRU_BASE) +#define DDR0CRU ((struct DDR0CRU_REG *) DDR0CRU_BASE) +#define DDR1CRU ((struct DDR1CRU_REG *) DDR1CRU_BASE) +#define DDR2CRU ((struct DDR2CRU_REG *) DDR2CRU_BASE) +#define DDR3CRU ((struct DDR3CRU_REG *) DDR3CRU_BASE) +#define BIGCORE0CRU ((struct BIGCORE0CRU_REG *) BIGCORE0CRU_BASE) +#define BIGCORE1CRU ((struct BIGCORE1CRU_REG *) BIGCORE1CRU_BASE) +#define DSUCRU ((struct DSUCRU_REG *) DSUCRU_BASE) +#define I2C0 ((struct I2C_REG *) I2C0_BASE) +#define UART0 ((struct UART_REG *) UART0_BASE) +#define GPIO0 ((struct GPIO_REG *) GPIO0_BASE) +#define GPIO0_EXP ((struct GPIO_REG *) GPIO0_EXP_BASE) +#define PMU ((struct PMU_REG *) PMU_BASE) +#define WDT ((struct WDT_REG *) WDT_BASE) +#define PDM0 ((struct PDM_REG *) PDM0_BASE) +#define PDM1 ((struct PDM_REG *) PDM1_BASE) +#define VAD ((struct VAD_REG *) VAD_BASE) +#define DMA0 ((struct DMA_REG *) DMA0_BASE) +#define DMA1 ((struct DMA_REG *) DMA1_BASE) +#define CAN0 ((struct CAN_REG *) CAN0_BASE) +#define CAN1 ((struct CAN_REG *) CAN1_BASE) +#define CAN2 ((struct CAN_REG *) CAN2_BASE) +#define I2C1 ((struct I2C_REG *) I2C1_BASE) +#define I2C2 ((struct I2C_REG *) I2C2_BASE) +#define I2C3 ((struct I2C_REG *) I2C3_BASE) +#define I2C4 ((struct I2C_REG *) I2C4_BASE) +#define I2C5 ((struct I2C_REG *) I2C5_BASE) +#define TIMER0 ((struct TIMER_REG *) TIMER0_BASE) +#define TIMER1 ((struct TIMER_REG *) TIMER1_BASE) +#define TIMER2 ((struct TIMER_REG *) TIMER2_BASE) +#define TIMER3 ((struct TIMER_REG *) TIMER3_BASE) +#define TIMER4 ((struct TIMER_REG *) TIMER4_BASE) +#define TIMER5 ((struct TIMER_REG *) TIMER5_BASE) +#define TIMER6 ((struct TIMER_REG *) TIMER6_BASE) +#define TIMER7 ((struct TIMER_REG *) TIMER7_BASE) +#define TIMER8 ((struct TIMER_REG *) TIMER8_BASE) +#define TIMER9 ((struct TIMER_REG *) TIMER9_BASE) +#define TIMER10 ((struct TIMER_REG *) TIMER10_BASE) +#define TIMER11 ((struct TIMER_REG *) TIMER11_BASE) +#define SPI0 ((struct SPI_REG *) SPI0_BASE) +#define SPI1 ((struct SPI_REG *) SPI1_BASE) +#define SPI2 ((struct SPI_REG *) SPI2_BASE) +#define SPI3 ((struct SPI_REG *) SPI3_BASE) +#define UART1 ((struct UART_REG *) UART1_BASE) +#define UART2 ((struct UART_REG *) UART2_BASE) +#define UART3 ((struct UART_REG *) UART3_BASE) +#define UART4 ((struct UART_REG *) UART4_BASE) +#define UART5 ((struct UART_REG *) UART5_BASE) +#define UART6 ((struct UART_REG *) UART6_BASE) +#define UART7 ((struct UART_REG *) UART7_BASE) +#define UART8 ((struct UART_REG *) UART8_BASE) +#define UART9 ((struct UART_REG *) UART9_BASE) +#define GPIO1 ((struct GPIO_REG *) GPIO1_BASE) +#define GPIO1_EXP ((struct GPIO_REG *) GPIO1_EXP_BASE) +#define GPIO2 ((struct GPIO_REG *) GPIO2_BASE) +#define GPIO2_EXP ((struct GPIO_REG *) GPIO2_EXP_BASE) +#define GPIO3 ((struct GPIO_REG *) GPIO3_BASE) +#define GPIO3_EXP ((struct GPIO_REG *) GPIO3_EXP_BASE) +#define GPIO4 ((struct GPIO_REG *) GPIO4_BASE) +#define GPIO4_EXP ((struct GPIO_REG *) GPIO4_EXP_BASE) +#define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) +#define I2C6 ((struct I2C_REG *) I2C6_BASE) +#define I2C7 ((struct I2C_REG *) I2C7_BASE) +#define I2C8 ((struct I2C_REG *) I2C8_BASE) + +#define IS_DCACHE_INSTANCE(instance) ((instance) == DCACHE) +#define IS_ICACHE_INSTANCE(instance) ((instance) == ICACHE) +#define IS_PMU1_IOC_INSTANCE(instance) ((instance) == PMU1_IOC) +#define IS_PMU2_IOC_INSTANCE(instance) ((instance) == PMU2_IOC) +#define IS_BUS_IOC_INSTANCE(instance) ((instance) == BUS_IOC) +#define IS_VCCIO1_4_IOC_INSTANCE(instance) ((instance) == VCCIO1_4_IOC) +#define IS_VCCIO3_5_IOC_INSTANCE(instance) ((instance) == VCCIO3_5_IOC) +#define IS_VCCIO2_IOC_INSTANCE(instance) ((instance) == VCCIO2_IOC) +#define IS_VCCIO6_IOC_INSTANCE(instance) ((instance) == VCCIO6_IOC) +#define IS_EMMC_IOC_INSTANCE(instance) ((instance) == EMMC_IOC) +#define IS_CRU_INSTANCE(instance) ((instance) == CRU) +#define IS_PHPTOPCRU_INSTANCE(instance) ((instance) == PHPTOPCRU) +#define IS_SECURECRU_INSTANCE(instance) ((instance) == SECURECRU) +#define IS_SBUSCRU_INSTANCE(instance) ((instance) == SBUSCRU) +#define IS_PMU1SCRU_INSTANCE(instance) ((instance) == PMU1SCRU) +#define IS_PMU1CRU_INSTANCE(instance) ((instance) == PMU1CRU) +#define IS_DDR0CRU_INSTANCE(instance) ((instance) == DDR0CRU) +#define IS_DDR1CRU_INSTANCE(instance) ((instance) == DDR1CRU) +#define IS_DDR2CRU_INSTANCE(instance) ((instance) == DDR2CRU) +#define IS_DDR3CRU_INSTANCE(instance) ((instance) == DDR3CRU) +#define IS_BIGCORE0CRU_INSTANCE(instance) ((instance) == BIGCORE0CRU) +#define IS_BIGCORE1CRU_INSTANCE(instance) ((instance) == BIGCORE1CRU) +#define IS_DSUCRU_INSTANCE(instance) ((instance) == DSUCRU) +#define IS_PMU_INSTANCE(instance) ((instance) == PMU) +#define IS_WDT_INSTANCE(instance) ((instance) == WDT) +#define IS_VAD_INSTANCE(instance) ((instance) == VAD) +#define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2) || ((instance) == UART3) || ((instance) == UART4) || ((instance) == UART5) || ((instance) == UART6) || ((instance) == UART7) || ((instance) == UART8) || ((instance) == UART9)) +#define IS_GPIO_INSTANCE(instance) (((instance) == GPIO0) || ((instance) == GPIO1) || ((instance) == GPIO2) || ((instance) == GPIO3) || ((instance) == GPIO4) || ((instance) == GPIO0_EXP) || ((instance) == GPIO1_EXP) || ((instance) == GPIO2_EXP) || ((instance) == GPIO3_EXP) || ((instance) == GPIO4_EXP)) +#define IS_PDM_INSTANCE(instance) (((instance) == PDM0) || ((instance) == PDM1)) +#define IS_DMA_INSTANCE(instance) (((instance) == DMA0) || ((instance) == DMA1)) +#define IS_TIMER_INSTANCE(instance) (((instance) == TIMER0) || ((instance) == TIMER1) || ((instance) == TIMER2) || ((instance) == TIMER3) || ((instance) == TIMER4) || ((instance) == TIMER5) || ((instance) == TIMER6) || ((instance) == TIMER7) || ((instance) == TIMER8) || ((instance) == TIMER9) || ((instance) == TIMER10) || ((instance) == TIMER11)) +#define IS_MBOX_INSTANCE(instance) ((instance) == MBOX0) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/****************************************PMU1_IOC****************************************/ +/* GPIO0A_IOMUX_SEL_L */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_OFFSET (0x0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0A_IOMUX_SEL_H */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_OFFSET (0x4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0B_IOMUX_SEL_L */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_OFFSET (0x8U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0A_DS_L */ +#define PMU1_IOC_GPIO0A_DS_L_OFFSET (0x10U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_SHIFT) /* 0x00003000 */ +/* GPIO0A_DS_H */ +#define PMU1_IOC_GPIO0A_DS_H_OFFSET (0x14U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_SHIFT) /* 0x00003000 */ +/* GPIO0B_DS_L */ +#define PMU1_IOC_GPIO0B_DS_L_OFFSET (0x18U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_SHIFT) /* 0x00003000 */ +/* GPIO0A_P */ +#define PMU1_IOC_GPIO0A_P_OFFSET (0x20U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PE_SHIFT (0U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A0_PE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PS_SHIFT (1U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A0_PS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PE_SHIFT (2U) +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A1_PE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PS_SHIFT (3U) +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A1_PS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PE_SHIFT (4U) +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A2_PE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PS_SHIFT (5U) +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A2_PS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PE_SHIFT (6U) +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A3_PE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PS_SHIFT (7U) +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A3_PS_SHIFT) /* 0x00000080 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PE_SHIFT (8U) +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A4_PE_SHIFT) /* 0x00000100 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PS_SHIFT (9U) +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A4_PS_SHIFT) /* 0x00000200 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PE_SHIFT (10U) +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A5_PE_SHIFT) /* 0x00000400 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PS_SHIFT (11U) +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A5_PS_SHIFT) /* 0x00000800 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PE_SHIFT (12U) +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A6_PE_SHIFT) /* 0x00001000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PS_SHIFT (13U) +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A6_PS_SHIFT) /* 0x00002000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PE_SHIFT (14U) +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A7_PE_SHIFT) /* 0x00004000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PS_SHIFT (15U) +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0B_P */ +#define PMU1_IOC_GPIO0B_P_OFFSET (0x24U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PE_SHIFT (0U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B0_PE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PS_SHIFT (1U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B0_PS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PE_SHIFT (2U) +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B1_PE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PS_SHIFT (3U) +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B1_PS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PE_SHIFT (4U) +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B2_PE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PS_SHIFT (5U) +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B2_PS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PE_SHIFT (6U) +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B3_PE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PS_SHIFT (7U) +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B3_PS_SHIFT) /* 0x00000080 */ +/* GPIO0A_IE */ +#define PMU1_IOC_GPIO0A_IE_OFFSET (0x28U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_SHIFT (1U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_SHIFT (2U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_SHIFT (3U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_SHIFT (5U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_SHIFT (6U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_SHIFT (7U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0B_IE */ +#define PMU1_IOC_GPIO0B_IE_OFFSET (0x2CU) +#define PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_SHIFT (0U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_SHIFT (1U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_SHIFT (2U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_SHIFT (3U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_SHIFT) /* 0x00000008 */ +/* GPIO0A_SMT */ +#define PMU1_IOC_GPIO0A_SMT_OFFSET (0x30U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_SHIFT (0U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_SHIFT (1U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_SHIFT (2U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_SHIFT (3U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_SHIFT (4U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_SHIFT (5U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_SHIFT (6U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_SHIFT (7U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0B_SMT */ +#define PMU1_IOC_GPIO0B_SMT_OFFSET (0x34U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_SHIFT (0U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_SHIFT (1U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_SHIFT (2U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_SHIFT (3U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_SHIFT) /* 0x00000008 */ +/* GPIO0A_PDIS */ +#define PMU1_IOC_GPIO0A_PDIS_OFFSET (0x38U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_SHIFT (1U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_SHIFT (2U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_SHIFT (3U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_SHIFT (5U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_SHIFT (6U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_SHIFT (7U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0B_PDIS */ +#define PMU1_IOC_GPIO0B_PDIS_OFFSET (0x3CU) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_SHIFT (0U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_SHIFT (1U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_SHIFT (2U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_SHIFT (3U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_SHIFT) /* 0x00000008 */ +/* XIN_CON */ +#define PMU1_IOC_XIN_CON_OFFSET (0x40U) +#define PMU1_IOC_XIN_CON_XIN_OSC_EN_SHIFT (0U) +#define PMU1_IOC_XIN_CON_XIN_OSC_EN_MASK (0x1U << PMU1_IOC_XIN_CON_XIN_OSC_EN_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_XIN_CON_XIN_OSC_SF_SHIFT (2U) +#define PMU1_IOC_XIN_CON_XIN_OSC_SF_MASK (0x3U << PMU1_IOC_XIN_CON_XIN_OSC_SF_SHIFT) /* 0x0000000C */ +/****************************************PMU2_IOC****************************************/ +/* GPIO0B_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_OFFSET (0x0U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_L */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_OFFSET (0x4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_OFFSET (0x8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_L */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_OFFSET (0xCU) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_OFFSET (0x10U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_SHIFT) /* 0x00000F00 */ +/* GPIO0B_DS_H */ +#define PMU2_IOC_GPIO0B_DS_H_OFFSET (0x14U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_SHIFT) /* 0x00007000 */ +/* GPIO0C_DS_L */ +#define PMU2_IOC_GPIO0C_DS_L_OFFSET (0x18U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_SHIFT) /* 0x00007000 */ +/* GPIO0C_DS_H */ +#define PMU2_IOC_GPIO0C_DS_H_OFFSET (0x1CU) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_SHIFT) /* 0x00007000 */ +/* GPIO0D_DS_L */ +#define PMU2_IOC_GPIO0D_DS_L_OFFSET (0x20U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_SHIFT) /* 0x00007000 */ +/* GPIO0D_DS_H */ +#define PMU2_IOC_GPIO0D_DS_H_OFFSET (0x24U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_SHIFT) /* 0x00000700 */ +/* GPIO0B_P */ +#define PMU2_IOC_GPIO0B_P_OFFSET (0x28U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B6_PS_SHIFT) /* 0x00002000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PE_SHIFT (14U) +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B7_PE_SHIFT) /* 0x00004000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PS_SHIFT (15U) +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0C_P */ +#define PMU2_IOC_GPIO0C_P_OFFSET (0x2CU) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PE_SHIFT (0U) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C0_PE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PS_SHIFT (1U) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C0_PS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PE_SHIFT (2U) +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C1_PE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PS_SHIFT (3U) +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C1_PS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PE_SHIFT (4U) +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C2_PE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PS_SHIFT (5U) +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C2_PS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PE_SHIFT (6U) +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C3_PE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PS_SHIFT (7U) +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C3_PS_SHIFT) /* 0x00000080 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PE_SHIFT (8U) +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C4_PE_SHIFT) /* 0x00000100 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PS_SHIFT (9U) +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C4_PS_SHIFT) /* 0x00000200 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C6_PS_SHIFT) /* 0x00002000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PE_SHIFT (14U) +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C7_PE_SHIFT) /* 0x00004000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PS_SHIFT (15U) +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0D_P */ +#define PMU2_IOC_GPIO0D_P_OFFSET (0x30U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PE_SHIFT (0U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D0_PE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PS_SHIFT (1U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D0_PS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PE_SHIFT (2U) +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D1_PE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PS_SHIFT (3U) +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D1_PS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PE_SHIFT (4U) +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D2_PE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PS_SHIFT (5U) +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D2_PS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PE_SHIFT (6U) +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D3_PE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PS_SHIFT (7U) +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D3_PS_SHIFT) /* 0x00000080 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PE_SHIFT (8U) +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D4_PE_SHIFT) /* 0x00000100 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PS_SHIFT (9U) +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D4_PS_SHIFT) /* 0x00000200 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D6_PS_SHIFT) /* 0x00002000 */ +/* GPIO0B_IE */ +#define PMU2_IOC_GPIO0B_IE_OFFSET (0x34U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_SHIFT (7U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0C_IE */ +#define PMU2_IOC_GPIO0C_IE_OFFSET (0x38U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_SHIFT (1U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_SHIFT (2U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_SHIFT (3U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_SHIFT (7U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0D_IE */ +#define PMU2_IOC_GPIO0D_IE_OFFSET (0x3CU) +#define PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_SHIFT (1U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_SHIFT (2U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_SHIFT (3U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_SHIFT) /* 0x00000040 */ +/* GPIO0B_SMT */ +#define PMU2_IOC_GPIO0B_SMT_OFFSET (0x40U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_SHIFT (7U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0C_SMT */ +#define PMU2_IOC_GPIO0C_SMT_OFFSET (0x44U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_SHIFT (0U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_SHIFT (1U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_SHIFT (2U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_SHIFT (3U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_SHIFT (4U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_SHIFT (7U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0D_SMT */ +#define PMU2_IOC_GPIO0D_SMT_OFFSET (0x48U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_SHIFT (0U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_SHIFT (1U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_SHIFT (2U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_SHIFT (3U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_SHIFT (4U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_SHIFT) /* 0x00000040 */ +/* GPIO0B_PDIS */ +#define PMU2_IOC_GPIO0B_PDIS_OFFSET (0x4CU) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_SHIFT (7U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0C_PDIS */ +#define PMU2_IOC_GPIO0C_PDIS_OFFSET (0x50U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_SHIFT (1U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_SHIFT (2U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_SHIFT (3U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_SHIFT (7U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0D_PDIS */ +#define PMU2_IOC_GPIO0D_PDIS_OFFSET (0x54U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_SHIFT (1U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_SHIFT (2U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_SHIFT (3U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_SHIFT) /* 0x00000040 */ +/****************************************BUS_IOC*****************************************/ +/* GPIO0B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_OFFSET (0xCU) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_OFFSET (0x10U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT) /* 0x0000000F */ +/* GPIO0C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_OFFSET (0x14U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_OFFSET (0x18U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_OFFSET (0x1CU) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO1A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_OFFSET (0x20U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_OFFSET (0x24U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_OFFSET (0x28U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_OFFSET (0x2CU) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_OFFSET (0x30U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_OFFSET (0x34U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_OFFSET (0x38U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_OFFSET (0x3CU) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_OFFSET (0x40U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_OFFSET (0x44U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_OFFSET (0x48U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_OFFSET (0x4CU) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_OFFSET (0x50U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_OFFSET (0x54U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO2D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_OFFSET (0x58U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_OFFSET (0x5CU) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_OFFSET (0x60U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_OFFSET (0x64U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_OFFSET (0x68U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_OFFSET (0x6CU) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_OFFSET (0x70U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_OFFSET (0x74U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_OFFSET (0x78U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_OFFSET (0x7CU) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO4A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_OFFSET (0x80U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_OFFSET (0x84U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_OFFSET (0x88U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_OFFSET (0x8CU) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_OFFSET (0x90U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_OFFSET (0x94U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_SHIFT) /* 0x00000F00 */ +/* GPIO4D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_OFFSET (0x98U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_OFFSET (0x9CU) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_SHIFT) /* 0x000000F0 */ +/**************************************VCCIO1_4_IOC**************************************/ +/* GPIO1A_DS_L */ +#define VCCIO1_4_IOC_GPIO1A_DS_L_OFFSET (0x20U) +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A0_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A0_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A1_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A1_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A2_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A2_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A3_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A3_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_L_GPIO1A3_DS_SHIFT) /* 0x00007000 */ +/* GPIO1A_DS_H */ +#define VCCIO1_4_IOC_GPIO1A_DS_H_OFFSET (0x24U) +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A4_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A4_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A5_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A5_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A6_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A6_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A7_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A7_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1A_DS_H_GPIO1A7_DS_SHIFT) /* 0x00007000 */ +/* GPIO1B_DS_L */ +#define VCCIO1_4_IOC_GPIO1B_DS_L_OFFSET (0x28U) +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B0_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B0_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B1_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B1_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B2_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B2_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B3_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B3_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_L_GPIO1B3_DS_SHIFT) /* 0x00007000 */ +/* GPIO1B_DS_H */ +#define VCCIO1_4_IOC_GPIO1B_DS_H_OFFSET (0x2CU) +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B4_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B4_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B5_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B5_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B6_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B6_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B7_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B7_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1B_DS_H_GPIO1B7_DS_SHIFT) /* 0x00007000 */ +/* GPIO1C_DS_L */ +#define VCCIO1_4_IOC_GPIO1C_DS_L_OFFSET (0x30U) +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C0_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C0_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C0_DS_SHIFT) /* 0x00000003 */ +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C1_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C1_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C1_DS_SHIFT) /* 0x00000030 */ +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C2_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C2_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C2_DS_SHIFT) /* 0x00000300 */ +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C3_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C3_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_L_GPIO1C3_DS_SHIFT) /* 0x00003000 */ +/* GPIO1C_DS_H */ +#define VCCIO1_4_IOC_GPIO1C_DS_H_OFFSET (0x34U) +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C4_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C4_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C4_DS_SHIFT) /* 0x00000003 */ +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C5_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C5_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C5_DS_SHIFT) /* 0x00000030 */ +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C6_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C6_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C6_DS_SHIFT) /* 0x00000300 */ +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C7_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C7_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1C_DS_H_GPIO1C7_DS_SHIFT) /* 0x00003000 */ +/* GPIO1D_DS_L */ +#define VCCIO1_4_IOC_GPIO1D_DS_L_OFFSET (0x38U) +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D0_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D0_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D0_DS_SHIFT) /* 0x00000003 */ +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D1_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D1_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D1_DS_SHIFT) /* 0x00000030 */ +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D2_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D2_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D2_DS_SHIFT) /* 0x00000300 */ +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D3_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D3_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_L_GPIO1D3_DS_SHIFT) /* 0x00003000 */ +/* GPIO1D_DS_H */ +#define VCCIO1_4_IOC_GPIO1D_DS_H_OFFSET (0x3CU) +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D4_DS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D4_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D4_DS_SHIFT) /* 0x00000003 */ +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D5_DS_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D5_DS_MASK (0x3U << VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D5_DS_SHIFT) /* 0x00000030 */ +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D6_DS_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D6_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D7_DS_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D7_DS_MASK (0x7U << VCCIO1_4_IOC_GPIO1D_DS_H_GPIO1D7_DS_SHIFT) /* 0x00007000 */ +/* GPIO1A_P */ +#define VCCIO1_4_IOC_GPIO1A_P_OFFSET (0x110U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PS_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PS_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PS_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PS_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PE_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PS_SHIFT (9U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PE_SHIFT (10U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PS_SHIFT (11U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PE_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PS_SHIFT (13U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PE_SHIFT (14U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PS_SHIFT (15U) +#define VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_P_GPIO1A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO1B_P */ +#define VCCIO1_4_IOC_GPIO1B_P_OFFSET (0x114U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PS_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PS_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PS_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PS_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PE_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PS_SHIFT (9U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PE_SHIFT (10U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PS_SHIFT (11U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PE_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PS_SHIFT (13U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PE_SHIFT (14U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PS_SHIFT (15U) +#define VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_P_GPIO1B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO1C_P */ +#define VCCIO1_4_IOC_GPIO1C_P_OFFSET (0x118U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PS_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PS_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PS_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PS_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PE_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PS_SHIFT (9U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PE_SHIFT (10U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PS_SHIFT (11U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PE_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PS_SHIFT (13U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PE_SHIFT (14U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PS_SHIFT (15U) +#define VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_P_GPIO1C7_PS_SHIFT) /* 0x00008000 */ +/* GPIO1D_P */ +#define VCCIO1_4_IOC_GPIO1D_P_OFFSET (0x11CU) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PS_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PS_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PS_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PS_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PE_SHIFT (8U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PS_SHIFT (9U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PE_SHIFT (10U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PS_SHIFT (11U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PE_SHIFT (12U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PS_SHIFT (13U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PE_SHIFT (14U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PS_SHIFT (15U) +#define VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PS_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_P_GPIO1D7_PS_SHIFT) /* 0x00008000 */ +/* GPIO1A_IE */ +#define VCCIO1_4_IOC_GPIO1A_IE_OFFSET (0x180U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A0_IE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A0_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A1_IE_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A1_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A2_IE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A2_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A3_IE_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A3_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A4_IE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A4_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A5_IE_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A5_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A6_IE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A6_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A7_IE_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1A_IE_GPIO1A7_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_IE_GPIO1A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO1B_IE */ +#define VCCIO1_4_IOC_GPIO1B_IE_OFFSET (0x184U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B0_IE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B0_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B1_IE_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B1_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B2_IE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B2_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B3_IE_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B3_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B4_IE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B4_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B5_IE_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B5_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B6_IE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B6_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B7_IE_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1B_IE_GPIO1B7_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_IE_GPIO1B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO1C_IE */ +#define VCCIO1_4_IOC_GPIO1C_IE_OFFSET (0x188U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C0_IE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C0_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C1_IE_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C1_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C2_IE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C2_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C3_IE_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C3_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C4_IE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C4_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C5_IE_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C5_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C6_IE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C6_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C7_IE_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1C_IE_GPIO1C7_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_IE_GPIO1C7_IE_SHIFT) /* 0x00000080 */ +/* GPIO1D_IE */ +#define VCCIO1_4_IOC_GPIO1D_IE_OFFSET (0x18CU) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D0_IE_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D0_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D1_IE_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D1_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D2_IE_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D2_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D3_IE_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D3_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D4_IE_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D4_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D5_IE_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D5_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D6_IE_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D6_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D7_IE_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1D_IE_GPIO1D7_IE_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_IE_GPIO1D7_IE_SHIFT) /* 0x00000080 */ +/* GPIO1A_SMT */ +#define VCCIO1_4_IOC_GPIO1A_SMT_OFFSET (0x210U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A0_SMT_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A0_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A1_SMT_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A1_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A2_SMT_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A2_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A3_SMT_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A3_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A4_SMT_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A4_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A5_SMT_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A5_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A6_SMT_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A6_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A7_SMT_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A7_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1A_SMT_GPIO1A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO1B_SMT */ +#define VCCIO1_4_IOC_GPIO1B_SMT_OFFSET (0x214U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B0_SMT_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B0_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B1_SMT_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B1_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B2_SMT_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B2_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B3_SMT_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B3_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B4_SMT_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B4_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B5_SMT_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B5_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B6_SMT_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B6_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B7_SMT_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B7_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1B_SMT_GPIO1B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO1C_SMT */ +#define VCCIO1_4_IOC_GPIO1C_SMT_OFFSET (0x218U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C0_SMT_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C0_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C1_SMT_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C1_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C2_SMT_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C2_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C3_SMT_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C3_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C4_SMT_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C4_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C5_SMT_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C5_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C6_SMT_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C6_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C7_SMT_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C7_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1C_SMT_GPIO1C7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO1D_SMT */ +#define VCCIO1_4_IOC_GPIO1D_SMT_OFFSET (0x21CU) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D0_SMT_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D0_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D1_SMT_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D1_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D2_SMT_SHIFT (2U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D2_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D3_SMT_SHIFT (3U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D3_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D4_SMT_SHIFT (4U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D4_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D5_SMT_SHIFT (5U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D5_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D6_SMT_SHIFT (6U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D6_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D7_SMT_SHIFT (7U) +#define VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D7_SMT_MASK (0x1U << VCCIO1_4_IOC_GPIO1D_SMT_GPIO1D7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO_PDIS */ +#define VCCIO1_4_IOC_GPIO_PDIS_OFFSET (0x280U) +#define VCCIO1_4_IOC_GPIO_PDIS_VCCIO1_PULL_DIS_SHIFT (0U) +#define VCCIO1_4_IOC_GPIO_PDIS_VCCIO1_PULL_DIS_MASK (0x1U << VCCIO1_4_IOC_GPIO_PDIS_VCCIO1_PULL_DIS_SHIFT) /* 0x00000001 */ +#define VCCIO1_4_IOC_GPIO_PDIS_VCCIO4_PULL_DIS_SHIFT (1U) +#define VCCIO1_4_IOC_GPIO_PDIS_VCCIO4_PULL_DIS_MASK (0x1U << VCCIO1_4_IOC_GPIO_PDIS_VCCIO4_PULL_DIS_SHIFT) /* 0x00000002 */ +/**************************************VCCIO3_5_IOC**************************************/ +/* GPIO2A_DS_H */ +#define VCCIO3_5_IOC_GPIO2A_DS_H_OFFSET (0x44U) +#define VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A6_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A6_DS_SHIFT) /* 0x00000300 */ +#define VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A7_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A7_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2A_DS_H_GPIO2A7_DS_SHIFT) /* 0x00003000 */ +/* GPIO2B_DS_L */ +#define VCCIO3_5_IOC_GPIO2B_DS_L_OFFSET (0x48U) +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B0_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B0_DS_SHIFT) /* 0x00000003 */ +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B1_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B1_DS_SHIFT) /* 0x00000030 */ +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B2_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B2_DS_SHIFT) /* 0x00000300 */ +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B3_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_L_GPIO2B3_DS_SHIFT) /* 0x00003000 */ +/* GPIO2B_DS_H */ +#define VCCIO3_5_IOC_GPIO2B_DS_H_OFFSET (0x4CU) +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B4_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B4_DS_SHIFT) /* 0x00000003 */ +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B5_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B5_DS_SHIFT) /* 0x00000030 */ +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B6_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B6_DS_SHIFT) /* 0x00000300 */ +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B7_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B7_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2B_DS_H_GPIO2B7_DS_SHIFT) /* 0x00003000 */ +/* GPIO2C_DS_L */ +#define VCCIO3_5_IOC_GPIO2C_DS_L_OFFSET (0x50U) +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C0_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C0_DS_SHIFT) /* 0x00000003 */ +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C1_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C1_DS_SHIFT) /* 0x00000030 */ +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C2_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C2_DS_SHIFT) /* 0x00000300 */ +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C3_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_L_GPIO2C3_DS_SHIFT) /* 0x00003000 */ +/* GPIO2C_DS_H */ +#define VCCIO3_5_IOC_GPIO2C_DS_H_OFFSET (0x54U) +#define VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C4_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C4_DS_SHIFT) /* 0x00000003 */ +#define VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C5_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO2C_DS_H_GPIO2C5_DS_SHIFT) /* 0x00000030 */ +/* GPIO3A_DS_L */ +#define VCCIO3_5_IOC_GPIO3A_DS_L_OFFSET (0x60U) +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A0_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A1_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A2_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A3_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_L_GPIO3A3_DS_SHIFT) /* 0x00007000 */ +/* GPIO3A_DS_H */ +#define VCCIO3_5_IOC_GPIO3A_DS_H_OFFSET (0x64U) +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A4_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A5_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A6_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A7_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A7_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3A_DS_H_GPIO3A7_DS_SHIFT) /* 0x00007000 */ +/* GPIO3B_DS_L */ +#define VCCIO3_5_IOC_GPIO3B_DS_L_OFFSET (0x68U) +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B0_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B1_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B2_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B3_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_L_GPIO3B3_DS_SHIFT) /* 0x00007000 */ +/* GPIO3B_DS_H */ +#define VCCIO3_5_IOC_GPIO3B_DS_H_OFFSET (0x6CU) +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B4_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B5_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B6_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B7_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B7_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3B_DS_H_GPIO3B7_DS_SHIFT) /* 0x00007000 */ +/* GPIO3C_DS_L */ +#define VCCIO3_5_IOC_GPIO3C_DS_L_OFFSET (0x70U) +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C0_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C1_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C2_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C3_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_L_GPIO3C3_DS_SHIFT) /* 0x00007000 */ +/* GPIO3C_DS_H */ +#define VCCIO3_5_IOC_GPIO3C_DS_H_OFFSET (0x74U) +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C4_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C5_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C6_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C7_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C7_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3C_DS_H_GPIO3C7_DS_SHIFT) /* 0x00007000 */ +/* GPIO3D_DS_L */ +#define VCCIO3_5_IOC_GPIO3D_DS_L_OFFSET (0x78U) +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D0_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D0_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D1_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D1_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D2_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D3_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_L_GPIO3D3_DS_SHIFT) /* 0x00007000 */ +/* GPIO3D_DS_H */ +#define VCCIO3_5_IOC_GPIO3D_DS_H_OFFSET (0x7CU) +#define VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D4_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D5_DS_MASK (0x7U << VCCIO3_5_IOC_GPIO3D_DS_H_GPIO3D5_DS_SHIFT) /* 0x00000070 */ +/* GPIO4C_DS_L */ +#define VCCIO3_5_IOC_GPIO4C_DS_L_OFFSET (0x90U) +#define VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C2_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C2_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C2_DS_SHIFT) /* 0x00000300 */ +#define VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C3_DS_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C3_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO4C_DS_L_GPIO4C3_DS_SHIFT) /* 0x00003000 */ +/* GPIO4C_DS_H */ +#define VCCIO3_5_IOC_GPIO4C_DS_H_OFFSET (0x94U) +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C4_DS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C4_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C4_DS_SHIFT) /* 0x00000003 */ +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C5_DS_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C5_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C5_DS_SHIFT) /* 0x00000030 */ +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C6_DS_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C6_DS_MASK (0x3U << VCCIO3_5_IOC_GPIO4C_DS_H_GPIO4C6_DS_SHIFT) /* 0x00000300 */ +/* GPIO2A_P */ +#define VCCIO3_5_IOC_GPIO2A_P_OFFSET (0x120U) +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_P_GPIO2A6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PE_SHIFT (14U) +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PS_SHIFT (15U) +#define VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_P_GPIO2A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO2B_P */ +#define VCCIO3_5_IOC_GPIO2B_P_OFFSET (0x124U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PE_SHIFT (14U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PS_SHIFT (15U) +#define VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_P_GPIO2B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO2C_P */ +#define VCCIO3_5_IOC_GPIO2C_P_OFFSET (0x128U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_P_GPIO2C5_PS_SHIFT) /* 0x00000800 */ +/* GPIO3A_P */ +#define VCCIO3_5_IOC_GPIO3A_P_OFFSET (0x130U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PE_SHIFT (14U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PS_SHIFT (15U) +#define VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_P_GPIO3A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO3B_P */ +#define VCCIO3_5_IOC_GPIO3B_P_OFFSET (0x134U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PE_SHIFT (14U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PS_SHIFT (15U) +#define VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_P_GPIO3B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO3C_P */ +#define VCCIO3_5_IOC_GPIO3C_P_OFFSET (0x138U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PE_SHIFT (14U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PS_SHIFT (15U) +#define VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_P_GPIO3C7_PS_SHIFT) /* 0x00008000 */ +/* GPIO3D_P */ +#define VCCIO3_5_IOC_GPIO3D_P_OFFSET (0x13CU) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PS_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_P_GPIO3D5_PS_SHIFT) /* 0x00000800 */ +/* GPIO4C_P */ +#define VCCIO3_5_IOC_GPIO4C_P_OFFSET (0x148U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PS_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PS_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PE_SHIFT (8U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PS_SHIFT (9U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PE_SHIFT (10U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PS_SHIFT (11U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PE_SHIFT (12U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PS_SHIFT (13U) +#define VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PS_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_P_GPIO4C6_PS_SHIFT) /* 0x00002000 */ +/* GPIO2A_IE */ +#define VCCIO3_5_IOC_GPIO2A_IE_OFFSET (0x190U) +#define VCCIO3_5_IOC_GPIO2A_IE_GPIO2A6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2A_IE_GPIO2A6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_IE_GPIO2A6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2A_IE_GPIO2A7_IE_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2A_IE_GPIO2A7_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_IE_GPIO2A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO2B_IE */ +#define VCCIO3_5_IOC_GPIO2B_IE_OFFSET (0x194U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B7_IE_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2B_IE_GPIO2B7_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_IE_GPIO2B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO2C_IE */ +#define VCCIO3_5_IOC_GPIO2C_IE_OFFSET (0x198U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2C_IE_GPIO2C5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_IE_GPIO2C5_IE_SHIFT) /* 0x00000020 */ +/* GPIO3A_IE */ +#define VCCIO3_5_IOC_GPIO3A_IE_OFFSET (0x1A0U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A7_IE_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3A_IE_GPIO3A7_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_IE_GPIO3A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO3B_IE */ +#define VCCIO3_5_IOC_GPIO3B_IE_OFFSET (0x1A4U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B7_IE_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3B_IE_GPIO3B7_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_IE_GPIO3B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO3C_IE */ +#define VCCIO3_5_IOC_GPIO3C_IE_OFFSET (0x1A8U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C7_IE_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3C_IE_GPIO3C7_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_IE_GPIO3C7_IE_SHIFT) /* 0x00000080 */ +/* GPIO3D_IE */ +#define VCCIO3_5_IOC_GPIO3D_IE_OFFSET (0x1ACU) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D0_IE_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D0_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D1_IE_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D1_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3D_IE_GPIO3D5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_IE_GPIO3D5_IE_SHIFT) /* 0x00000020 */ +/* GPIO4C_IE */ +#define VCCIO3_5_IOC_GPIO4C_IE_OFFSET (0x1B8U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C2_IE_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C2_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_IE_GPIO4C2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C3_IE_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C3_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_IE_GPIO4C3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C4_IE_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C4_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_IE_GPIO4C4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C5_IE_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C5_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_IE_GPIO4C5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C6_IE_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO4C_IE_GPIO4C6_IE_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_IE_GPIO4C6_IE_SHIFT) /* 0x00000040 */ +/* GPIO2A_SMT */ +#define VCCIO3_5_IOC_GPIO2A_SMT_OFFSET (0x220U) +#define VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A7_SMT_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A7_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2A_SMT_GPIO2A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO2B_SMT */ +#define VCCIO3_5_IOC_GPIO2B_SMT_OFFSET (0x224U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B7_SMT_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B7_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2B_SMT_GPIO2B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO2C_SMT */ +#define VCCIO3_5_IOC_GPIO2C_SMT_OFFSET (0x228U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO2C_SMT_GPIO2C5_SMT_SHIFT) /* 0x00000020 */ +/* GPIO3A_SMT */ +#define VCCIO3_5_IOC_GPIO3A_SMT_OFFSET (0x230U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A7_SMT_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A7_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3A_SMT_GPIO3A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO3B_SMT */ +#define VCCIO3_5_IOC_GPIO3B_SMT_OFFSET (0x234U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B7_SMT_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B7_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3B_SMT_GPIO3B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO3C_SMT */ +#define VCCIO3_5_IOC_GPIO3C_SMT_OFFSET (0x238U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C7_SMT_SHIFT (7U) +#define VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C7_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3C_SMT_GPIO3C7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO3D_SMT */ +#define VCCIO3_5_IOC_GPIO3D_SMT_OFFSET (0x23CU) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D0_SMT_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D0_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D1_SMT_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D1_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO3D_SMT_GPIO3D5_SMT_SHIFT) /* 0x00000020 */ +/* GPIO4C_SMT */ +#define VCCIO3_5_IOC_GPIO4C_SMT_OFFSET (0x248U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C2_SMT_SHIFT (2U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C2_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C3_SMT_SHIFT (3U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C3_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C4_SMT_SHIFT (4U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C4_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C5_SMT_SHIFT (5U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C5_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C6_SMT_SHIFT (6U) +#define VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C6_SMT_MASK (0x1U << VCCIO3_5_IOC_GPIO4C_SMT_GPIO4C6_SMT_SHIFT) /* 0x00000040 */ +/* GPIO_PDIS */ +#define VCCIO3_5_IOC_GPIO_PDIS_OFFSET (0x288U) +#define VCCIO3_5_IOC_GPIO_PDIS_VCCIO3_PULL_DIS_SHIFT (0U) +#define VCCIO3_5_IOC_GPIO_PDIS_VCCIO3_PULL_DIS_MASK (0x1U << VCCIO3_5_IOC_GPIO_PDIS_VCCIO3_PULL_DIS_SHIFT) /* 0x00000001 */ +#define VCCIO3_5_IOC_GPIO_PDIS_VCCIO5_PULL_DIS_SHIFT (1U) +#define VCCIO3_5_IOC_GPIO_PDIS_VCCIO5_PULL_DIS_MASK (0x1U << VCCIO3_5_IOC_GPIO_PDIS_VCCIO5_PULL_DIS_SHIFT) /* 0x00000002 */ +/***************************************VCCIO2_IOC***************************************/ +/* GPIO4D_DS_L */ +#define VCCIO2_IOC_GPIO4D_DS_L_OFFSET (0x98U) +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D0_DS_SHIFT (0U) +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D0_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_L_GPIO4D0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D1_DS_SHIFT (4U) +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D1_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_L_GPIO4D1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D2_DS_SHIFT (8U) +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D2_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_L_GPIO4D2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D3_DS_SHIFT (12U) +#define VCCIO2_IOC_GPIO4D_DS_L_GPIO4D3_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_L_GPIO4D3_DS_SHIFT) /* 0x00007000 */ +/* GPIO4D_DS_H */ +#define VCCIO2_IOC_GPIO4D_DS_H_OFFSET (0x9CU) +#define VCCIO2_IOC_GPIO4D_DS_H_GPIO4D4_DS_SHIFT (0U) +#define VCCIO2_IOC_GPIO4D_DS_H_GPIO4D4_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_H_GPIO4D4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO2_IOC_GPIO4D_DS_H_GPIO4D5_DS_SHIFT (4U) +#define VCCIO2_IOC_GPIO4D_DS_H_GPIO4D5_DS_MASK (0x7U << VCCIO2_IOC_GPIO4D_DS_H_GPIO4D5_DS_SHIFT) /* 0x00000070 */ +/* GPIO4D_P */ +#define VCCIO2_IOC_GPIO4D_P_OFFSET (0x14CU) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D0_PE_SHIFT (0U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D0_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D0_PS_SHIFT (1U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D0_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D1_PE_SHIFT (2U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D1_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D1_PS_SHIFT (3U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D1_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D2_PE_SHIFT (4U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D2_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D2_PS_SHIFT (5U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D2_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D3_PE_SHIFT (6U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D3_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D3_PS_SHIFT (7U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D3_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D4_PE_SHIFT (8U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D4_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D4_PS_SHIFT (9U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D4_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D5_PE_SHIFT (10U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D5_PE_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO2_IOC_GPIO4D_P_GPIO4D5_PS_SHIFT (11U) +#define VCCIO2_IOC_GPIO4D_P_GPIO4D5_PS_MASK (0x1U << VCCIO2_IOC_GPIO4D_P_GPIO4D5_PS_SHIFT) /* 0x00000800 */ +/* GPIO4D_IE */ +#define VCCIO2_IOC_GPIO4D_IE_OFFSET (0x1BCU) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D0_IE_SHIFT (0U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D0_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D1_IE_SHIFT (1U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D1_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D2_IE_SHIFT (2U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D2_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D3_IE_SHIFT (3U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D3_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D4_IE_SHIFT (4U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D4_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D5_IE_SHIFT (5U) +#define VCCIO2_IOC_GPIO4D_IE_GPIO4D5_IE_MASK (0x1U << VCCIO2_IOC_GPIO4D_IE_GPIO4D5_IE_SHIFT) /* 0x00000020 */ +/* GPIO4D_SMT */ +#define VCCIO2_IOC_GPIO4D_SMT_OFFSET (0x24CU) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D0_SMT_SHIFT (0U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D0_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D1_SMT_SHIFT (1U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D1_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D2_SMT_SHIFT (2U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D2_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D3_SMT_SHIFT (3U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D3_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D4_SMT_SHIFT (4U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D4_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D5_SMT_SHIFT (5U) +#define VCCIO2_IOC_GPIO4D_SMT_GPIO4D5_SMT_MASK (0x1U << VCCIO2_IOC_GPIO4D_SMT_GPIO4D5_SMT_SHIFT) /* 0x00000020 */ +/* GPIO_PDIS */ +#define VCCIO2_IOC_GPIO_PDIS_OFFSET (0x284U) +#define VCCIO2_IOC_GPIO_PDIS_VCCIO2_PULL_DIS_SHIFT (0U) +#define VCCIO2_IOC_GPIO_PDIS_VCCIO2_PULL_DIS_MASK (0x1U << VCCIO2_IOC_GPIO_PDIS_VCCIO2_PULL_DIS_SHIFT) /* 0x00000001 */ +/***************************************VCCIO6_IOC***************************************/ +/* GPIO4A_DS_L */ +#define VCCIO6_IOC_GPIO4A_DS_L_OFFSET (0x80U) +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A0_DS_SHIFT (0U) +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A0_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_L_GPIO4A0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A1_DS_SHIFT (4U) +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A1_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_L_GPIO4A1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A2_DS_SHIFT (8U) +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A2_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_L_GPIO4A2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A3_DS_SHIFT (12U) +#define VCCIO6_IOC_GPIO4A_DS_L_GPIO4A3_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_L_GPIO4A3_DS_SHIFT) /* 0x00007000 */ +/* GPIO4A_DS_H */ +#define VCCIO6_IOC_GPIO4A_DS_H_OFFSET (0x84U) +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A4_DS_SHIFT (0U) +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A4_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_H_GPIO4A4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A5_DS_SHIFT (4U) +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A5_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_H_GPIO4A5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A6_DS_SHIFT (8U) +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A6_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_H_GPIO4A6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A7_DS_SHIFT (12U) +#define VCCIO6_IOC_GPIO4A_DS_H_GPIO4A7_DS_MASK (0x7U << VCCIO6_IOC_GPIO4A_DS_H_GPIO4A7_DS_SHIFT) /* 0x00007000 */ +/* GPIO4B_DS_L */ +#define VCCIO6_IOC_GPIO4B_DS_L_OFFSET (0x88U) +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B0_DS_SHIFT (0U) +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B0_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_L_GPIO4B0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B1_DS_SHIFT (4U) +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B1_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_L_GPIO4B1_DS_SHIFT) /* 0x00000070 */ +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B2_DS_SHIFT (8U) +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B2_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_L_GPIO4B2_DS_SHIFT) /* 0x00000700 */ +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B3_DS_SHIFT (12U) +#define VCCIO6_IOC_GPIO4B_DS_L_GPIO4B3_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_L_GPIO4B3_DS_SHIFT) /* 0x00007000 */ +/* GPIO4B_DS_H */ +#define VCCIO6_IOC_GPIO4B_DS_H_OFFSET (0x8CU) +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B4_DS_SHIFT (0U) +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B4_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_H_GPIO4B4_DS_SHIFT) /* 0x00000007 */ +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B5_DS_SHIFT (4U) +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B5_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_H_GPIO4B5_DS_SHIFT) /* 0x00000070 */ +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B6_DS_SHIFT (8U) +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B6_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_H_GPIO4B6_DS_SHIFT) /* 0x00000700 */ +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B7_DS_SHIFT (12U) +#define VCCIO6_IOC_GPIO4B_DS_H_GPIO4B7_DS_MASK (0x7U << VCCIO6_IOC_GPIO4B_DS_H_GPIO4B7_DS_SHIFT) /* 0x00007000 */ +/* GPIO4C_DS_L */ +#define VCCIO6_IOC_GPIO4C_DS_L_OFFSET (0x90U) +#define VCCIO6_IOC_GPIO4C_DS_L_GPIO4C0_DS_SHIFT (0U) +#define VCCIO6_IOC_GPIO4C_DS_L_GPIO4C0_DS_MASK (0x7U << VCCIO6_IOC_GPIO4C_DS_L_GPIO4C0_DS_SHIFT) /* 0x00000007 */ +#define VCCIO6_IOC_GPIO4C_DS_L_GPIO4C1_DS_SHIFT (4U) +#define VCCIO6_IOC_GPIO4C_DS_L_GPIO4C1_DS_MASK (0x7U << VCCIO6_IOC_GPIO4C_DS_L_GPIO4C1_DS_SHIFT) /* 0x00000070 */ +/* GPIO4A_P */ +#define VCCIO6_IOC_GPIO4A_P_OFFSET (0x140U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A0_PE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A0_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A0_PS_SHIFT (1U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A0_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A1_PE_SHIFT (2U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A1_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A1_PS_SHIFT (3U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A1_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A2_PE_SHIFT (4U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A2_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A2_PS_SHIFT (5U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A2_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A3_PE_SHIFT (6U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A3_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A3_PS_SHIFT (7U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A3_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A4_PE_SHIFT (8U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A4_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A4_PS_SHIFT (9U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A4_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A5_PE_SHIFT (10U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A5_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A5_PS_SHIFT (11U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A5_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A6_PE_SHIFT (12U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A6_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A6_PS_SHIFT (13U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A6_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A7_PE_SHIFT (14U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A7_PE_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO6_IOC_GPIO4A_P_GPIO4A7_PS_SHIFT (15U) +#define VCCIO6_IOC_GPIO4A_P_GPIO4A7_PS_MASK (0x1U << VCCIO6_IOC_GPIO4A_P_GPIO4A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO4B_P */ +#define VCCIO6_IOC_GPIO4B_P_OFFSET (0x144U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B0_PE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B0_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B0_PS_SHIFT (1U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B0_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B1_PE_SHIFT (2U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B1_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B1_PS_SHIFT (3U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B1_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B1_PS_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B2_PE_SHIFT (4U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B2_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B2_PE_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B2_PS_SHIFT (5U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B2_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B2_PS_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B3_PE_SHIFT (6U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B3_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B3_PE_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B3_PS_SHIFT (7U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B3_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B3_PS_SHIFT) /* 0x00000080 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B4_PE_SHIFT (8U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B4_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B4_PE_SHIFT) /* 0x00000100 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B4_PS_SHIFT (9U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B4_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B4_PS_SHIFT) /* 0x00000200 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B5_PE_SHIFT (10U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B5_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B5_PE_SHIFT) /* 0x00000400 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B5_PS_SHIFT (11U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B5_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B5_PS_SHIFT) /* 0x00000800 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B6_PE_SHIFT (12U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B6_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B6_PE_SHIFT) /* 0x00001000 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B6_PS_SHIFT (13U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B6_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B6_PS_SHIFT) /* 0x00002000 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B7_PE_SHIFT (14U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B7_PE_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B7_PE_SHIFT) /* 0x00004000 */ +#define VCCIO6_IOC_GPIO4B_P_GPIO4B7_PS_SHIFT (15U) +#define VCCIO6_IOC_GPIO4B_P_GPIO4B7_PS_MASK (0x1U << VCCIO6_IOC_GPIO4B_P_GPIO4B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO4C_P */ +#define VCCIO6_IOC_GPIO4C_P_OFFSET (0x148U) +#define VCCIO6_IOC_GPIO4C_P_GPIO4C0_PE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4C_P_GPIO4C0_PE_MASK (0x1U << VCCIO6_IOC_GPIO4C_P_GPIO4C0_PE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4C_P_GPIO4C0_PS_SHIFT (1U) +#define VCCIO6_IOC_GPIO4C_P_GPIO4C0_PS_MASK (0x1U << VCCIO6_IOC_GPIO4C_P_GPIO4C0_PS_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4C_P_GPIO4C1_PE_SHIFT (2U) +#define VCCIO6_IOC_GPIO4C_P_GPIO4C1_PE_MASK (0x1U << VCCIO6_IOC_GPIO4C_P_GPIO4C1_PE_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4C_P_GPIO4C1_PS_SHIFT (3U) +#define VCCIO6_IOC_GPIO4C_P_GPIO4C1_PS_MASK (0x1U << VCCIO6_IOC_GPIO4C_P_GPIO4C1_PS_SHIFT) /* 0x00000008 */ +/* GPIO4A_IE */ +#define VCCIO6_IOC_GPIO4A_IE_OFFSET (0x1B0U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A0_IE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A0_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A1_IE_SHIFT (1U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A1_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A2_IE_SHIFT (2U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A2_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A3_IE_SHIFT (3U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A3_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A4_IE_SHIFT (4U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A4_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A5_IE_SHIFT (5U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A5_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A6_IE_SHIFT (6U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A6_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A7_IE_SHIFT (7U) +#define VCCIO6_IOC_GPIO4A_IE_GPIO4A7_IE_MASK (0x1U << VCCIO6_IOC_GPIO4A_IE_GPIO4A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO4B_IE */ +#define VCCIO6_IOC_GPIO4B_IE_OFFSET (0x1B4U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B0_IE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B0_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B1_IE_SHIFT (1U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B1_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B1_IE_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B2_IE_SHIFT (2U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B2_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B2_IE_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B3_IE_SHIFT (3U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B3_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B3_IE_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B4_IE_SHIFT (4U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B4_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B4_IE_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B5_IE_SHIFT (5U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B5_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B5_IE_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B6_IE_SHIFT (6U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B6_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B6_IE_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B7_IE_SHIFT (7U) +#define VCCIO6_IOC_GPIO4B_IE_GPIO4B7_IE_MASK (0x1U << VCCIO6_IOC_GPIO4B_IE_GPIO4B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO4C_IE */ +#define VCCIO6_IOC_GPIO4C_IE_OFFSET (0x1B8U) +#define VCCIO6_IOC_GPIO4C_IE_GPIO4C0_IE_SHIFT (0U) +#define VCCIO6_IOC_GPIO4C_IE_GPIO4C0_IE_MASK (0x1U << VCCIO6_IOC_GPIO4C_IE_GPIO4C0_IE_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4C_IE_GPIO4C1_IE_SHIFT (1U) +#define VCCIO6_IOC_GPIO4C_IE_GPIO4C1_IE_MASK (0x1U << VCCIO6_IOC_GPIO4C_IE_GPIO4C1_IE_SHIFT) /* 0x00000002 */ +/* GPIO4A_SMT */ +#define VCCIO6_IOC_GPIO4A_SMT_OFFSET (0x240U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A0_SMT_SHIFT (0U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A0_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A1_SMT_SHIFT (1U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A1_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A2_SMT_SHIFT (2U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A2_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A3_SMT_SHIFT (3U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A3_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A4_SMT_SHIFT (4U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A4_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A5_SMT_SHIFT (5U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A5_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A6_SMT_SHIFT (6U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A6_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A7_SMT_SHIFT (7U) +#define VCCIO6_IOC_GPIO4A_SMT_GPIO4A7_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4A_SMT_GPIO4A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO4B_SMT */ +#define VCCIO6_IOC_GPIO4B_SMT_OFFSET (0x244U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B0_SMT_SHIFT (0U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B0_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B1_SMT_SHIFT (1U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B1_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B1_SMT_SHIFT) /* 0x00000002 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B2_SMT_SHIFT (2U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B2_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B2_SMT_SHIFT) /* 0x00000004 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B3_SMT_SHIFT (3U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B3_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B3_SMT_SHIFT) /* 0x00000008 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B4_SMT_SHIFT (4U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B4_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B4_SMT_SHIFT) /* 0x00000010 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B5_SMT_SHIFT (5U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B5_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B5_SMT_SHIFT) /* 0x00000020 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B6_SMT_SHIFT (6U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B6_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B6_SMT_SHIFT) /* 0x00000040 */ +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B7_SMT_SHIFT (7U) +#define VCCIO6_IOC_GPIO4B_SMT_GPIO4B7_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4B_SMT_GPIO4B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO4C_SMT */ +#define VCCIO6_IOC_GPIO4C_SMT_OFFSET (0x248U) +#define VCCIO6_IOC_GPIO4C_SMT_GPIO4C0_SMT_SHIFT (0U) +#define VCCIO6_IOC_GPIO4C_SMT_GPIO4C0_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4C_SMT_GPIO4C0_SMT_SHIFT) /* 0x00000001 */ +#define VCCIO6_IOC_GPIO4C_SMT_GPIO4C1_SMT_SHIFT (1U) +#define VCCIO6_IOC_GPIO4C_SMT_GPIO4C1_SMT_MASK (0x1U << VCCIO6_IOC_GPIO4C_SMT_GPIO4C1_SMT_SHIFT) /* 0x00000002 */ +/* GPIO_PDIS */ +#define VCCIO6_IOC_GPIO_PDIS_OFFSET (0x28CU) +#define VCCIO6_IOC_GPIO_PDIS_VCCIO6_PULL_DIS_SHIFT (0U) +#define VCCIO6_IOC_GPIO_PDIS_VCCIO6_PULL_DIS_MASK (0x1U << VCCIO6_IOC_GPIO_PDIS_VCCIO6_PULL_DIS_SHIFT) /* 0x00000001 */ +/****************************************EMMC_IOC****************************************/ +/* GPIO2A_DS_L */ +#define EMMC_IOC_GPIO2A_DS_L_OFFSET (0x40U) +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A0_DS_SHIFT (0U) +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A0_DS_MASK (0x7U << EMMC_IOC_GPIO2A_DS_L_GPIO2A0_DS_SHIFT) /* 0x00000007 */ +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A1_DS_SHIFT (4U) +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A1_DS_MASK (0x7U << EMMC_IOC_GPIO2A_DS_L_GPIO2A1_DS_SHIFT) /* 0x00000070 */ +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A2_DS_SHIFT (8U) +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A2_DS_MASK (0x7U << EMMC_IOC_GPIO2A_DS_L_GPIO2A2_DS_SHIFT) /* 0x00000700 */ +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A3_DS_SHIFT (12U) +#define EMMC_IOC_GPIO2A_DS_L_GPIO2A3_DS_MASK (0x7U << EMMC_IOC_GPIO2A_DS_L_GPIO2A3_DS_SHIFT) /* 0x00007000 */ +/* GPIO2D_DS_L */ +#define EMMC_IOC_GPIO2D_DS_L_OFFSET (0x58U) +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D0_DS_SHIFT (0U) +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D0_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_L_GPIO2D0_DS_SHIFT) /* 0x00000007 */ +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D1_DS_SHIFT (4U) +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D1_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_L_GPIO2D1_DS_SHIFT) /* 0x00000070 */ +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D2_DS_SHIFT (8U) +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D2_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_L_GPIO2D2_DS_SHIFT) /* 0x00000700 */ +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D3_DS_SHIFT (12U) +#define EMMC_IOC_GPIO2D_DS_L_GPIO2D3_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_L_GPIO2D3_DS_SHIFT) /* 0x00007000 */ +/* GPIO2D_DS_H */ +#define EMMC_IOC_GPIO2D_DS_H_OFFSET (0x5CU) +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D4_DS_SHIFT (0U) +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D4_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_H_GPIO2D4_DS_SHIFT) /* 0x00000007 */ +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D5_DS_SHIFT (4U) +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D5_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_H_GPIO2D5_DS_SHIFT) /* 0x00000070 */ +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D6_DS_SHIFT (8U) +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D6_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_H_GPIO2D6_DS_SHIFT) /* 0x00000700 */ +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D7_DS_SHIFT (12U) +#define EMMC_IOC_GPIO2D_DS_H_GPIO2D7_DS_MASK (0x7U << EMMC_IOC_GPIO2D_DS_H_GPIO2D7_DS_SHIFT) /* 0x00007000 */ +/* GPIO2A_P */ +#define EMMC_IOC_GPIO2A_P_OFFSET (0x120U) +#define EMMC_IOC_GPIO2A_P_GPIO2A0_PE_SHIFT (0U) +#define EMMC_IOC_GPIO2A_P_GPIO2A0_PE_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A0_PE_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A0_PS_SHIFT (1U) +#define EMMC_IOC_GPIO2A_P_GPIO2A0_PS_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A0_PS_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A1_PE_SHIFT (2U) +#define EMMC_IOC_GPIO2A_P_GPIO2A1_PE_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A1_PE_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A1_PS_SHIFT (3U) +#define EMMC_IOC_GPIO2A_P_GPIO2A1_PS_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A1_PS_SHIFT) /* 0x00000008 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A2_PE_SHIFT (4U) +#define EMMC_IOC_GPIO2A_P_GPIO2A2_PE_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A2_PE_SHIFT) /* 0x00000010 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A2_PS_SHIFT (5U) +#define EMMC_IOC_GPIO2A_P_GPIO2A2_PS_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A2_PS_SHIFT) /* 0x00000020 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A3_PE_SHIFT (6U) +#define EMMC_IOC_GPIO2A_P_GPIO2A3_PE_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A3_PE_SHIFT) /* 0x00000040 */ +#define EMMC_IOC_GPIO2A_P_GPIO2A3_PS_SHIFT (7U) +#define EMMC_IOC_GPIO2A_P_GPIO2A3_PS_MASK (0x1U << EMMC_IOC_GPIO2A_P_GPIO2A3_PS_SHIFT) /* 0x00000080 */ +/* GPIO2D_P */ +#define EMMC_IOC_GPIO2D_P_OFFSET (0x12CU) +#define EMMC_IOC_GPIO2D_P_GPIO2D0_PE_SHIFT (0U) +#define EMMC_IOC_GPIO2D_P_GPIO2D0_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D0_PE_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D0_PS_SHIFT (1U) +#define EMMC_IOC_GPIO2D_P_GPIO2D0_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D0_PS_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D1_PE_SHIFT (2U) +#define EMMC_IOC_GPIO2D_P_GPIO2D1_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D1_PE_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D1_PS_SHIFT (3U) +#define EMMC_IOC_GPIO2D_P_GPIO2D1_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D1_PS_SHIFT) /* 0x00000008 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D2_PE_SHIFT (4U) +#define EMMC_IOC_GPIO2D_P_GPIO2D2_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D2_PE_SHIFT) /* 0x00000010 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D2_PS_SHIFT (5U) +#define EMMC_IOC_GPIO2D_P_GPIO2D2_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D2_PS_SHIFT) /* 0x00000020 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D3_PE_SHIFT (6U) +#define EMMC_IOC_GPIO2D_P_GPIO2D3_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D3_PE_SHIFT) /* 0x00000040 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D3_PS_SHIFT (7U) +#define EMMC_IOC_GPIO2D_P_GPIO2D3_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D3_PS_SHIFT) /* 0x00000080 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D4_PE_SHIFT (8U) +#define EMMC_IOC_GPIO2D_P_GPIO2D4_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D4_PE_SHIFT) /* 0x00000100 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D4_PS_SHIFT (9U) +#define EMMC_IOC_GPIO2D_P_GPIO2D4_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D4_PS_SHIFT) /* 0x00000200 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D5_PE_SHIFT (10U) +#define EMMC_IOC_GPIO2D_P_GPIO2D5_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D5_PE_SHIFT) /* 0x00000400 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D5_PS_SHIFT (11U) +#define EMMC_IOC_GPIO2D_P_GPIO2D5_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D5_PS_SHIFT) /* 0x00000800 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D6_PE_SHIFT (12U) +#define EMMC_IOC_GPIO2D_P_GPIO2D6_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D6_PE_SHIFT) /* 0x00001000 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D6_PS_SHIFT (13U) +#define EMMC_IOC_GPIO2D_P_GPIO2D6_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D6_PS_SHIFT) /* 0x00002000 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D7_PE_SHIFT (14U) +#define EMMC_IOC_GPIO2D_P_GPIO2D7_PE_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D7_PE_SHIFT) /* 0x00004000 */ +#define EMMC_IOC_GPIO2D_P_GPIO2D7_PS_SHIFT (15U) +#define EMMC_IOC_GPIO2D_P_GPIO2D7_PS_MASK (0x1U << EMMC_IOC_GPIO2D_P_GPIO2D7_PS_SHIFT) /* 0x00008000 */ +/* GPIO2A_IE */ +#define EMMC_IOC_GPIO2A_IE_OFFSET (0x190U) +#define EMMC_IOC_GPIO2A_IE_GPIO2A0_IE_SHIFT (0U) +#define EMMC_IOC_GPIO2A_IE_GPIO2A0_IE_MASK (0x1U << EMMC_IOC_GPIO2A_IE_GPIO2A0_IE_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2A_IE_GPIO2A1_IE_SHIFT (1U) +#define EMMC_IOC_GPIO2A_IE_GPIO2A1_IE_MASK (0x1U << EMMC_IOC_GPIO2A_IE_GPIO2A1_IE_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2A_IE_GPIO2A2_IE_SHIFT (2U) +#define EMMC_IOC_GPIO2A_IE_GPIO2A2_IE_MASK (0x1U << EMMC_IOC_GPIO2A_IE_GPIO2A2_IE_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2A_IE_GPIO2A3_IE_SHIFT (3U) +#define EMMC_IOC_GPIO2A_IE_GPIO2A3_IE_MASK (0x1U << EMMC_IOC_GPIO2A_IE_GPIO2A3_IE_SHIFT) /* 0x00000008 */ +/* GPIO2D_IE */ +#define EMMC_IOC_GPIO2D_IE_OFFSET (0x19CU) +#define EMMC_IOC_GPIO2D_IE_GPIO2D0_IE_SHIFT (0U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D0_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D0_IE_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D1_IE_SHIFT (1U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D1_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D1_IE_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D2_IE_SHIFT (2U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D2_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D2_IE_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D3_IE_SHIFT (3U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D3_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D3_IE_SHIFT) /* 0x00000008 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D4_IE_SHIFT (4U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D4_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D4_IE_SHIFT) /* 0x00000010 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D5_IE_SHIFT (5U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D5_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D5_IE_SHIFT) /* 0x00000020 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D6_IE_SHIFT (6U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D6_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D6_IE_SHIFT) /* 0x00000040 */ +#define EMMC_IOC_GPIO2D_IE_GPIO2D7_IE_SHIFT (7U) +#define EMMC_IOC_GPIO2D_IE_GPIO2D7_IE_MASK (0x1U << EMMC_IOC_GPIO2D_IE_GPIO2D7_IE_SHIFT) /* 0x00000080 */ +/* GPIO2A_SMT */ +#define EMMC_IOC_GPIO2A_SMT_OFFSET (0x220U) +#define EMMC_IOC_GPIO2A_SMT_GPIO2A0_SMT_SHIFT (0U) +#define EMMC_IOC_GPIO2A_SMT_GPIO2A0_SMT_MASK (0x1U << EMMC_IOC_GPIO2A_SMT_GPIO2A0_SMT_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2A_SMT_GPIO2A1_SMT_SHIFT (1U) +#define EMMC_IOC_GPIO2A_SMT_GPIO2A1_SMT_MASK (0x1U << EMMC_IOC_GPIO2A_SMT_GPIO2A1_SMT_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2A_SMT_GPIO2A2_SMT_SHIFT (2U) +#define EMMC_IOC_GPIO2A_SMT_GPIO2A2_SMT_MASK (0x1U << EMMC_IOC_GPIO2A_SMT_GPIO2A2_SMT_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2A_SMT_GPIO2A3_SMT_SHIFT (3U) +#define EMMC_IOC_GPIO2A_SMT_GPIO2A3_SMT_MASK (0x1U << EMMC_IOC_GPIO2A_SMT_GPIO2A3_SMT_SHIFT) /* 0x00000008 */ +/* GPIO2D_SMT */ +#define EMMC_IOC_GPIO2D_SMT_OFFSET (0x22CU) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D0_SMT_SHIFT (0U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D0_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D0_SMT_SHIFT) /* 0x00000001 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D1_SMT_SHIFT (1U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D1_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D1_SMT_SHIFT) /* 0x00000002 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D2_SMT_SHIFT (2U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D2_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D2_SMT_SHIFT) /* 0x00000004 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D3_SMT_SHIFT (3U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D3_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D3_SMT_SHIFT) /* 0x00000008 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D4_SMT_SHIFT (4U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D4_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D4_SMT_SHIFT) /* 0x00000010 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D5_SMT_SHIFT (5U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D5_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D5_SMT_SHIFT) /* 0x00000020 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D6_SMT_SHIFT (6U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D6_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D6_SMT_SHIFT) /* 0x00000040 */ +#define EMMC_IOC_GPIO2D_SMT_GPIO2D7_SMT_SHIFT (7U) +#define EMMC_IOC_GPIO2D_SMT_GPIO2D7_SMT_MASK (0x1U << EMMC_IOC_GPIO2D_SMT_GPIO2D7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO_PDIS */ +#define EMMC_IOC_GPIO_PDIS_OFFSET (0x290U) +#define EMMC_IOC_GPIO_PDIS_EMMCIO_PULL_DIS_SHIFT (0U) +#define EMMC_IOC_GPIO_PDIS_EMMCIO_PULL_DIS_MASK (0x1U << EMMC_IOC_GPIO_PDIS_EMMCIO_PULL_DIS_SHIFT) /* 0x00000001 */ +/******************************************CRU*******************************************/ +/* V0PLL_CON0 */ +#define CRU_V0PLL_CON0_OFFSET (0x160U) +#define CRU_V0PLL_CON0_V0PLL_M_SHIFT (0U) +#define CRU_V0PLL_CON0_V0PLL_M_MASK (0x3FFU << CRU_V0PLL_CON0_V0PLL_M_SHIFT) /* 0x000003FF */ +#define CRU_V0PLL_CON0_V0PLL_BP_SHIFT (15U) +#define CRU_V0PLL_CON0_V0PLL_BP_MASK (0x1U << CRU_V0PLL_CON0_V0PLL_BP_SHIFT) /* 0x00008000 */ +/* V0PLL_CON1 */ +#define CRU_V0PLL_CON1_OFFSET (0x164U) +#define CRU_V0PLL_CON1_V0PLL_P_SHIFT (0U) +#define CRU_V0PLL_CON1_V0PLL_P_MASK (0x3FU << CRU_V0PLL_CON1_V0PLL_P_SHIFT) /* 0x0000003F */ +#define CRU_V0PLL_CON1_V0PLL_S_SHIFT (6U) +#define CRU_V0PLL_CON1_V0PLL_S_MASK (0x7U << CRU_V0PLL_CON1_V0PLL_S_SHIFT) /* 0x000001C0 */ +#define CRU_V0PLL_CON1_V0PLL_RESETB_SHIFT (13U) +#define CRU_V0PLL_CON1_V0PLL_RESETB_MASK (0x1U << CRU_V0PLL_CON1_V0PLL_RESETB_SHIFT) /* 0x00002000 */ +/* V0PLL_CON2 */ +#define CRU_V0PLL_CON2_OFFSET (0x168U) +#define CRU_V0PLL_CON2_V0PLL_K_SHIFT (0U) +#define CRU_V0PLL_CON2_V0PLL_K_MASK (0xFFFFU << CRU_V0PLL_CON2_V0PLL_K_SHIFT) /* 0x0000FFFF */ +/* V0PLL_CON3 */ +#define CRU_V0PLL_CON3_OFFSET (0x16CU) +#define CRU_V0PLL_CON3_V0PLL_MFR_SHIFT (0U) +#define CRU_V0PLL_CON3_V0PLL_MFR_MASK (0xFFU << CRU_V0PLL_CON3_V0PLL_MFR_SHIFT) /* 0x000000FF */ +#define CRU_V0PLL_CON3_V0PLL_MRR_SHIFT (8U) +#define CRU_V0PLL_CON3_V0PLL_MRR_MASK (0x3FU << CRU_V0PLL_CON3_V0PLL_MRR_SHIFT) /* 0x00003F00 */ +#define CRU_V0PLL_CON3_V0PLL_SEL_PF_SHIFT (14U) +#define CRU_V0PLL_CON3_V0PLL_SEL_PF_MASK (0x3U << CRU_V0PLL_CON3_V0PLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* V0PLL_CON4 */ +#define CRU_V0PLL_CON4_OFFSET (0x170U) +#define CRU_V0PLL_CON4_V0PLL_SSCG_EN_SHIFT (0U) +#define CRU_V0PLL_CON4_V0PLL_SSCG_EN_MASK (0x1U << CRU_V0PLL_CON4_V0PLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define CRU_V0PLL_CON4_V0PLL_AFC_ENB_SHIFT (3U) +#define CRU_V0PLL_CON4_V0PLL_AFC_ENB_MASK (0x1U << CRU_V0PLL_CON4_V0PLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define CRU_V0PLL_CON4_V0PLL_EXTAFC_SHIFT (4U) +#define CRU_V0PLL_CON4_V0PLL_EXTAFC_MASK (0x1FU << CRU_V0PLL_CON4_V0PLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define CRU_V0PLL_CON4_V0PLL_FEED_EN_SHIFT (14U) +#define CRU_V0PLL_CON4_V0PLL_FEED_EN_MASK (0x1U << CRU_V0PLL_CON4_V0PLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define CRU_V0PLL_CON4_V0PLL_FSEL_SHIFT (15U) +#define CRU_V0PLL_CON4_V0PLL_FSEL_MASK (0x1U << CRU_V0PLL_CON4_V0PLL_FSEL_SHIFT) /* 0x00008000 */ +/* V0PLL_CON5 */ +#define CRU_V0PLL_CON5_OFFSET (0x174U) +#define CRU_V0PLL_CON5_V0PLL_FOUT_MASK_SHIFT (0U) +#define CRU_V0PLL_CON5_V0PLL_FOUT_MASK_MASK (0x1U << CRU_V0PLL_CON5_V0PLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* V0PLL_CON6 */ +#define CRU_V0PLL_CON6_OFFSET (0x178U) +#define CRU_V0PLL_CON6_V0PLL_AFC_CODE_SHIFT (10U) +#define CRU_V0PLL_CON6_V0PLL_AFC_CODE_MASK (0x1FU << CRU_V0PLL_CON6_V0PLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define CRU_V0PLL_CON6_V0PLL_LOCK_SHIFT (15U) +#define CRU_V0PLL_CON6_V0PLL_LOCK_MASK (0x1U << CRU_V0PLL_CON6_V0PLL_LOCK_SHIFT) /* 0x00008000 */ +/* AUPLL_CON0 */ +#define CRU_AUPLL_CON0_OFFSET (0x180U) +#define CRU_AUPLL_CON0_AUPLL_M_SHIFT (0U) +#define CRU_AUPLL_CON0_AUPLL_M_MASK (0x3FFU << CRU_AUPLL_CON0_AUPLL_M_SHIFT) /* 0x000003FF */ +#define CRU_AUPLL_CON0_AUPLL_BP_SHIFT (15U) +#define CRU_AUPLL_CON0_AUPLL_BP_MASK (0x1U << CRU_AUPLL_CON0_AUPLL_BP_SHIFT) /* 0x00008000 */ +/* AUPLL_CON1 */ +#define CRU_AUPLL_CON1_OFFSET (0x184U) +#define CRU_AUPLL_CON1_AUPLL_P_SHIFT (0U) +#define CRU_AUPLL_CON1_AUPLL_P_MASK (0x3FU << CRU_AUPLL_CON1_AUPLL_P_SHIFT) /* 0x0000003F */ +#define CRU_AUPLL_CON1_AUPLL_S_SHIFT (6U) +#define CRU_AUPLL_CON1_AUPLL_S_MASK (0x7U << CRU_AUPLL_CON1_AUPLL_S_SHIFT) /* 0x000001C0 */ +#define CRU_AUPLL_CON1_AUPLL_RESETB_SHIFT (13U) +#define CRU_AUPLL_CON1_AUPLL_RESETB_MASK (0x1U << CRU_AUPLL_CON1_AUPLL_RESETB_SHIFT) /* 0x00002000 */ +/* AUPLL_CON2 */ +#define CRU_AUPLL_CON2_OFFSET (0x188U) +#define CRU_AUPLL_CON2_AUPLL_K_SHIFT (0U) +#define CRU_AUPLL_CON2_AUPLL_K_MASK (0xFFFFU << CRU_AUPLL_CON2_AUPLL_K_SHIFT) /* 0x0000FFFF */ +/* AUPLL_CON3 */ +#define CRU_AUPLL_CON3_OFFSET (0x18CU) +#define CRU_AUPLL_CON3_AUPLL_MFR_SHIFT (0U) +#define CRU_AUPLL_CON3_AUPLL_MFR_MASK (0xFFU << CRU_AUPLL_CON3_AUPLL_MFR_SHIFT) /* 0x000000FF */ +#define CRU_AUPLL_CON3_AUPLL_MRR_SHIFT (8U) +#define CRU_AUPLL_CON3_AUPLL_MRR_MASK (0x3FU << CRU_AUPLL_CON3_AUPLL_MRR_SHIFT) /* 0x00003F00 */ +#define CRU_AUPLL_CON3_AUPLL_SEL_PF_SHIFT (14U) +#define CRU_AUPLL_CON3_AUPLL_SEL_PF_MASK (0x3U << CRU_AUPLL_CON3_AUPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* AUPLL_CON4 */ +#define CRU_AUPLL_CON4_OFFSET (0x190U) +#define CRU_AUPLL_CON4_AUPLL_SSCG_EN_SHIFT (0U) +#define CRU_AUPLL_CON4_AUPLL_SSCG_EN_MASK (0x1U << CRU_AUPLL_CON4_AUPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define CRU_AUPLL_CON4_AUPLL_AFC_ENB_SHIFT (3U) +#define CRU_AUPLL_CON4_AUPLL_AFC_ENB_MASK (0x1U << CRU_AUPLL_CON4_AUPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define CRU_AUPLL_CON4_AUPLL_EXTAFC_SHIFT (4U) +#define CRU_AUPLL_CON4_AUPLL_EXTAFC_MASK (0x1FU << CRU_AUPLL_CON4_AUPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define CRU_AUPLL_CON4_AUPLL_FEED_EN_SHIFT (14U) +#define CRU_AUPLL_CON4_AUPLL_FEED_EN_MASK (0x1U << CRU_AUPLL_CON4_AUPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define CRU_AUPLL_CON4_AUPLL_FSEL_SHIFT (15U) +#define CRU_AUPLL_CON4_AUPLL_FSEL_MASK (0x1U << CRU_AUPLL_CON4_AUPLL_FSEL_SHIFT) /* 0x00008000 */ +/* AUPLL_CON5 */ +#define CRU_AUPLL_CON5_OFFSET (0x194U) +#define CRU_AUPLL_CON5_AUPLL_FOUT_MASK_SHIFT (0U) +#define CRU_AUPLL_CON5_AUPLL_FOUT_MASK_MASK (0x1U << CRU_AUPLL_CON5_AUPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* AUPLL_CON6 */ +#define CRU_AUPLL_CON6_OFFSET (0x198U) +#define CRU_AUPLL_CON6_AUPLL_AFC_CODE_SHIFT (10U) +#define CRU_AUPLL_CON6_AUPLL_AFC_CODE_MASK (0x1FU << CRU_AUPLL_CON6_AUPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define CRU_AUPLL_CON6_AUPLL_LOCK_SHIFT (15U) +#define CRU_AUPLL_CON6_AUPLL_LOCK_MASK (0x1U << CRU_AUPLL_CON6_AUPLL_LOCK_SHIFT) /* 0x00008000 */ +/* CPLL_CON0 */ +#define CRU_CPLL_CON0_OFFSET (0x1A0U) +#define CRU_CPLL_CON0_CPLL_M_SHIFT (0U) +#define CRU_CPLL_CON0_CPLL_M_MASK (0x3FFU << CRU_CPLL_CON0_CPLL_M_SHIFT) /* 0x000003FF */ +#define CRU_CPLL_CON0_CPLL_BP_SHIFT (15U) +#define CRU_CPLL_CON0_CPLL_BP_MASK (0x1U << CRU_CPLL_CON0_CPLL_BP_SHIFT) /* 0x00008000 */ +/* CPLL_CON1 */ +#define CRU_CPLL_CON1_OFFSET (0x1A4U) +#define CRU_CPLL_CON1_CPLL_P_SHIFT (0U) +#define CRU_CPLL_CON1_CPLL_P_MASK (0x3FU << CRU_CPLL_CON1_CPLL_P_SHIFT) /* 0x0000003F */ +#define CRU_CPLL_CON1_CPLL_S_SHIFT (6U) +#define CRU_CPLL_CON1_CPLL_S_MASK (0x7U << CRU_CPLL_CON1_CPLL_S_SHIFT) /* 0x000001C0 */ +#define CRU_CPLL_CON1_CPLL_RESETB_SHIFT (13U) +#define CRU_CPLL_CON1_CPLL_RESETB_MASK (0x1U << CRU_CPLL_CON1_CPLL_RESETB_SHIFT) /* 0x00002000 */ +/* CPLL_CON2 */ +#define CRU_CPLL_CON2_OFFSET (0x1A8U) +#define CRU_CPLL_CON2_CPLL_K_SHIFT (0U) +#define CRU_CPLL_CON2_CPLL_K_MASK (0xFFFFU << CRU_CPLL_CON2_CPLL_K_SHIFT) /* 0x0000FFFF */ +/* CPLL_CON3 */ +#define CRU_CPLL_CON3_OFFSET (0x1ACU) +#define CRU_CPLL_CON3_CPLL_MFR_SHIFT (0U) +#define CRU_CPLL_CON3_CPLL_MFR_MASK (0xFFU << CRU_CPLL_CON3_CPLL_MFR_SHIFT) /* 0x000000FF */ +#define CRU_CPLL_CON3_CPLL_MRR_SHIFT (8U) +#define CRU_CPLL_CON3_CPLL_MRR_MASK (0x3FU << CRU_CPLL_CON3_CPLL_MRR_SHIFT) /* 0x00003F00 */ +#define CRU_CPLL_CON3_CPLL_SEL_PF_SHIFT (14U) +#define CRU_CPLL_CON3_CPLL_SEL_PF_MASK (0x3U << CRU_CPLL_CON3_CPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* CPLL_CON4 */ +#define CRU_CPLL_CON4_OFFSET (0x1B0U) +#define CRU_CPLL_CON4_CPLL_SSCG_EN_SHIFT (0U) +#define CRU_CPLL_CON4_CPLL_SSCG_EN_MASK (0x1U << CRU_CPLL_CON4_CPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define CRU_CPLL_CON4_CPLL_AFC_ENB_SHIFT (3U) +#define CRU_CPLL_CON4_CPLL_AFC_ENB_MASK (0x1U << CRU_CPLL_CON4_CPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define CRU_CPLL_CON4_CPLL_EXTAFC_SHIFT (4U) +#define CRU_CPLL_CON4_CPLL_EXTAFC_MASK (0x1FU << CRU_CPLL_CON4_CPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define CRU_CPLL_CON4_CPLL_FEED_EN_SHIFT (14U) +#define CRU_CPLL_CON4_CPLL_FEED_EN_MASK (0x1U << CRU_CPLL_CON4_CPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define CRU_CPLL_CON4_CPLL_FSEL_SHIFT (15U) +#define CRU_CPLL_CON4_CPLL_FSEL_MASK (0x1U << CRU_CPLL_CON4_CPLL_FSEL_SHIFT) /* 0x00008000 */ +/* CPLL_CON5 */ +#define CRU_CPLL_CON5_OFFSET (0x1B4U) +#define CRU_CPLL_CON5_CPLL_FOUT_MASK_SHIFT (0U) +#define CRU_CPLL_CON5_CPLL_FOUT_MASK_MASK (0x1U << CRU_CPLL_CON5_CPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* CPLL_CON6 */ +#define CRU_CPLL_CON6_OFFSET (0x1B8U) +#define CRU_CPLL_CON6_CPLL_AFC_CODE_SHIFT (10U) +#define CRU_CPLL_CON6_CPLL_AFC_CODE_MASK (0x1FU << CRU_CPLL_CON6_CPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define CRU_CPLL_CON6_CPLL_LOCK_SHIFT (15U) +#define CRU_CPLL_CON6_CPLL_LOCK_MASK (0x1U << CRU_CPLL_CON6_CPLL_LOCK_SHIFT) /* 0x00008000 */ +/* GPLL_CON0 */ +#define CRU_GPLL_CON0_OFFSET (0x1C0U) +#define CRU_GPLL_CON0_GPLL_M_SHIFT (0U) +#define CRU_GPLL_CON0_GPLL_M_MASK (0x3FFU << CRU_GPLL_CON0_GPLL_M_SHIFT) /* 0x000003FF */ +#define CRU_GPLL_CON0_GPLL_BP_SHIFT (15U) +#define CRU_GPLL_CON0_GPLL_BP_MASK (0x1U << CRU_GPLL_CON0_GPLL_BP_SHIFT) /* 0x00008000 */ +/* GPLL_CON1 */ +#define CRU_GPLL_CON1_OFFSET (0x1C4U) +#define CRU_GPLL_CON1_GPLL_P_SHIFT (0U) +#define CRU_GPLL_CON1_GPLL_P_MASK (0x3FU << CRU_GPLL_CON1_GPLL_P_SHIFT) /* 0x0000003F */ +#define CRU_GPLL_CON1_GPLL_S_SHIFT (6U) +#define CRU_GPLL_CON1_GPLL_S_MASK (0x7U << CRU_GPLL_CON1_GPLL_S_SHIFT) /* 0x000001C0 */ +#define CRU_GPLL_CON1_GPLL_RESETB_SHIFT (13U) +#define CRU_GPLL_CON1_GPLL_RESETB_MASK (0x1U << CRU_GPLL_CON1_GPLL_RESETB_SHIFT) /* 0x00002000 */ +/* GPLL_CON2 */ +#define CRU_GPLL_CON2_OFFSET (0x1C8U) +#define CRU_GPLL_CON2_GPLL_K_SHIFT (0U) +#define CRU_GPLL_CON2_GPLL_K_MASK (0xFFFFU << CRU_GPLL_CON2_GPLL_K_SHIFT) /* 0x0000FFFF */ +/* GPLL_CON3 */ +#define CRU_GPLL_CON3_OFFSET (0x1CCU) +#define CRU_GPLL_CON3_GPLL_MFR_SHIFT (0U) +#define CRU_GPLL_CON3_GPLL_MFR_MASK (0xFFU << CRU_GPLL_CON3_GPLL_MFR_SHIFT) /* 0x000000FF */ +#define CRU_GPLL_CON3_GPLL_MRR_SHIFT (8U) +#define CRU_GPLL_CON3_GPLL_MRR_MASK (0x3FU << CRU_GPLL_CON3_GPLL_MRR_SHIFT) /* 0x00003F00 */ +#define CRU_GPLL_CON3_GPLL_SEL_PF_SHIFT (14U) +#define CRU_GPLL_CON3_GPLL_SEL_PF_MASK (0x3U << CRU_GPLL_CON3_GPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* GPLL_CON4 */ +#define CRU_GPLL_CON4_OFFSET (0x1D0U) +#define CRU_GPLL_CON4_GPLL_SSCG_EN_SHIFT (0U) +#define CRU_GPLL_CON4_GPLL_SSCG_EN_MASK (0x1U << CRU_GPLL_CON4_GPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define CRU_GPLL_CON4_GPLL_AFC_ENB_SHIFT (3U) +#define CRU_GPLL_CON4_GPLL_AFC_ENB_MASK (0x1U << CRU_GPLL_CON4_GPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define CRU_GPLL_CON4_GPLL_EXTAFC_SHIFT (4U) +#define CRU_GPLL_CON4_GPLL_EXTAFC_MASK (0x1FU << CRU_GPLL_CON4_GPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define CRU_GPLL_CON4_GPLL_FEED_EN_SHIFT (14U) +#define CRU_GPLL_CON4_GPLL_FEED_EN_MASK (0x1U << CRU_GPLL_CON4_GPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define CRU_GPLL_CON4_GPLL_FSEL_SHIFT (15U) +#define CRU_GPLL_CON4_GPLL_FSEL_MASK (0x1U << CRU_GPLL_CON4_GPLL_FSEL_SHIFT) /* 0x00008000 */ +/* GPLL_CON5 */ +#define CRU_GPLL_CON5_OFFSET (0x1D4U) +#define CRU_GPLL_CON5_GPLL_FOUT_MASK_SHIFT (0U) +#define CRU_GPLL_CON5_GPLL_FOUT_MASK_MASK (0x1U << CRU_GPLL_CON5_GPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* GPLL_CON6 */ +#define CRU_GPLL_CON6_OFFSET (0x1D8U) +#define CRU_GPLL_CON6_GPLL_AFC_CODE_SHIFT (10U) +#define CRU_GPLL_CON6_GPLL_AFC_CODE_MASK (0x1FU << CRU_GPLL_CON6_GPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define CRU_GPLL_CON6_GPLL_LOCK_SHIFT (15U) +#define CRU_GPLL_CON6_GPLL_LOCK_MASK (0x1U << CRU_GPLL_CON6_GPLL_LOCK_SHIFT) /* 0x00008000 */ +/* NPLL_CON0 */ +#define CRU_NPLL_CON0_OFFSET (0x1E0U) +#define CRU_NPLL_CON0_NPLL_M_SHIFT (0U) +#define CRU_NPLL_CON0_NPLL_M_MASK (0x3FFU << CRU_NPLL_CON0_NPLL_M_SHIFT) /* 0x000003FF */ +#define CRU_NPLL_CON0_NPLL_BP_SHIFT (15U) +#define CRU_NPLL_CON0_NPLL_BP_MASK (0x1U << CRU_NPLL_CON0_NPLL_BP_SHIFT) /* 0x00008000 */ +/* NPLL_CON1 */ +#define CRU_NPLL_CON1_OFFSET (0x1E4U) +#define CRU_NPLL_CON1_NPLL_P_SHIFT (0U) +#define CRU_NPLL_CON1_NPLL_P_MASK (0x3FU << CRU_NPLL_CON1_NPLL_P_SHIFT) /* 0x0000003F */ +#define CRU_NPLL_CON1_NPLL_S_SHIFT (6U) +#define CRU_NPLL_CON1_NPLL_S_MASK (0x7U << CRU_NPLL_CON1_NPLL_S_SHIFT) /* 0x000001C0 */ +#define CRU_NPLL_CON1_NPLL_RESETB_SHIFT (13U) +#define CRU_NPLL_CON1_NPLL_RESETB_MASK (0x1U << CRU_NPLL_CON1_NPLL_RESETB_SHIFT) /* 0x00002000 */ +/* NPLL_CON4 */ +#define CRU_NPLL_CON4_OFFSET (0x1E8U) +#define CRU_NPLL_CON4_NPLL_ICP_SHIFT (1U) +#define CRU_NPLL_CON4_NPLL_ICP_MASK (0x3U << CRU_NPLL_CON4_NPLL_ICP_SHIFT) /* 0x00000006 */ +#define CRU_NPLL_CON4_NPLL_AFC_ENB_SHIFT (3U) +#define CRU_NPLL_CON4_NPLL_AFC_ENB_MASK (0x1U << CRU_NPLL_CON4_NPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define CRU_NPLL_CON4_NPLL_EXTAFC_SHIFT (4U) +#define CRU_NPLL_CON4_NPLL_EXTAFC_MASK (0x1FU << CRU_NPLL_CON4_NPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define CRU_NPLL_CON4_NPLL_FEED_EN_SHIFT (14U) +#define CRU_NPLL_CON4_NPLL_FEED_EN_MASK (0x1U << CRU_NPLL_CON4_NPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define CRU_NPLL_CON4_NPLL_FSEL_SHIFT (15U) +#define CRU_NPLL_CON4_NPLL_FSEL_MASK (0x1U << CRU_NPLL_CON4_NPLL_FSEL_SHIFT) /* 0x00008000 */ +/* NPLL_CON5 */ +#define CRU_NPLL_CON5_OFFSET (0x1F0U) +#define CRU_NPLL_CON5_NPLL_FOUT_MASK_SHIFT (0U) +#define CRU_NPLL_CON5_NPLL_FOUT_MASK_MASK (0x1U << CRU_NPLL_CON5_NPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +#define CRU_NPLL_CON5_NPLL_LOCK_CON_IN_SHIFT (5U) +#define CRU_NPLL_CON5_NPLL_LOCK_CON_IN_MASK (0x3U << CRU_NPLL_CON5_NPLL_LOCK_CON_IN_SHIFT) /* 0x00000060 */ +#define CRU_NPLL_CON5_NPLL_LOCK_CON_OUT_SHIFT (7U) +#define CRU_NPLL_CON5_NPLL_LOCK_CON_OUT_MASK (0x3U << CRU_NPLL_CON5_NPLL_LOCK_CON_OUT_SHIFT) /* 0x00000180 */ +#define CRU_NPLL_CON5_NPLL_LOCK_CON_DLY_SHIFT (9U) +#define CRU_NPLL_CON5_NPLL_LOCK_CON_DLY_MASK (0x3U << CRU_NPLL_CON5_NPLL_LOCK_CON_DLY_SHIFT) /* 0x00000600 */ +/* NPLL_CON6 */ +#define CRU_NPLL_CON6_OFFSET (0x1F4U) +#define CRU_NPLL_CON6_NPLL_AFC_CODE_SHIFT (10U) +#define CRU_NPLL_CON6_NPLL_AFC_CODE_MASK (0x1FU << CRU_NPLL_CON6_NPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define CRU_NPLL_CON6_NPLL_LOCK_SHIFT (15U) +#define CRU_NPLL_CON6_NPLL_LOCK_MASK (0x1U << CRU_NPLL_CON6_NPLL_LOCK_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define CRU_MODE_CON00_OFFSET (0x280U) +#define CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT (0U) +#define CRU_MODE_CON00_CLK_NPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_NPLL_MODE_SHIFT) /* 0x00000003 */ +#define CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT (2U) +#define CRU_MODE_CON00_CLK_GPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_GPLL_MODE_SHIFT) /* 0x0000000C */ +#define CRU_MODE_CON00_CLK_V0PLL_MODE_SHIFT (4U) +#define CRU_MODE_CON00_CLK_V0PLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_V0PLL_MODE_SHIFT) /* 0x00000030 */ +#define CRU_MODE_CON00_CLK_AUPLL_MODE_SHIFT (6U) +#define CRU_MODE_CON00_CLK_AUPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_AUPLL_MODE_SHIFT) /* 0x000000C0 */ +#define CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT (8U) +#define CRU_MODE_CON00_CLK_CPLL_MODE_MASK (0x3U << CRU_MODE_CON00_CLK_CPLL_MODE_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON00 */ +#define CRU_CLKSEL_CON00_OFFSET (0x300U) +#define CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_MATRIX_50M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON00_CLK_MATRIX_100M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON01 */ +#define CRU_CLKSEL_CON01_OFFSET (0x304U) +#define CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON01_CLK_MATRIX_150M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON01_CLK_MATRIX_200M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON02 */ +#define CRU_CLKSEL_CON02_OFFSET (0x308U) +#define CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON02_CLK_MATRIX_250M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON02_CLK_MATRIX_300M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON03 */ +#define CRU_CLKSEL_CON03_OFFSET (0x30CU) +#define CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON03_CLK_MATRIX_350M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON03_CLK_MATRIX_400M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON04 */ +#define CRU_CLKSEL_CON04_OFFSET (0x310U) +#define CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON04_CLK_MATRIX_450M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON04_CLK_MATRIX_500M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON05 */ +#define CRU_CLKSEL_CON05_OFFSET (0x314U) +#define CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON05_CLK_MATRIX_600M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON05_CLK_MATRIX_650M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON06 */ +#define CRU_CLKSEL_CON06_OFFSET (0x318U) +#define CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON06_CLK_MATRIX_700M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON06_CLK_MATRIX_800M_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON07 */ +#define CRU_CLKSEL_CON07_OFFSET (0x31CU) +#define CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON07_CLK_MATRIX_1000M_SRC_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON07_CLK_MATRIX_1200M_SRC_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON08 */ +#define CRU_CLKSEL_CON08_OFFSET (0x320U) +#define CRU_CLKSEL_CON08_ACLK_TOP_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON08_ACLK_TOP_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON08_ACLK_TOP_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON08_ACLK_TOP_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON08_ACLK_TOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON08_ACLK_TOP_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON08_PCLK_TOP_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON08_PCLK_TOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON08_PCLK_TOP_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON08_ACLK_LOW_TOP_ROOT_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON09 */ +#define CRU_CLKSEL_CON09_OFFSET (0x324U) +#define CRU_CLKSEL_CON09_ACLK_TOP_M300_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON09_ACLK_TOP_M300_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON09_ACLK_TOP_M300_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON09_ACLK_TOP_M500_ROOT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON09_ACLK_TOP_M500_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON09_ACLK_TOP_M500_ROOT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON09_ACLK_TOP_M400_ROOT_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON09_ACLK_TOP_M400_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON09_ACLK_TOP_M400_ROOT_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON09_ACLK_TOP_S200_ROOT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON09_ACLK_TOP_S200_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON09_ACLK_TOP_S200_ROOT_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON09_ACLK_TOP_S400_ROOT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON09_ACLK_TOP_S400_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON09_ACLK_TOP_S400_ROOT_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON10 */ +#define CRU_CLKSEL_CON10_OFFSET (0x328U) +#define CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_DIV_MASK (0x3FU << CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_SEL_MASK (0x7U << CRU_CLKSEL_CON10_CLK_TESTOUT_TOP_SEL_SHIFT) /* 0x000001C0 */ +#define CRU_CLKSEL_CON10_CLK_TESTOUT_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON10_CLK_TESTOUT_SEL_MASK (0x7U << CRU_CLKSEL_CON10_CLK_TESTOUT_SEL_SHIFT) /* 0x00000E00 */ +#define CRU_CLKSEL_CON10_CLK_TESTOUT_GRP0_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON10_CLK_TESTOUT_GRP0_SEL_MASK (0x7U << CRU_CLKSEL_CON10_CLK_TESTOUT_GRP0_SEL_SHIFT) /* 0x00007000 */ +/* CLKSEL_CON15 */ +#define CRU_CLKSEL_CON15_OFFSET (0x33CU) +#define CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_DIV_MASK (0x7FU << CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_SEL_MASK (0x1U << CRU_CLKSEL_CON15_MCLK_GMAC0_OUT_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_DIV_MASK (0x7FU << CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_DIV_SHIFT) /* 0x00007F00 */ +#define CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_SEL_MASK (0x1U << CRU_CLKSEL_CON15_REFCLKO25M_ETH0_OUT_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON16 */ +#define CRU_CLKSEL_CON16_OFFSET (0x340U) +#define CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_DIV_MASK (0x7FU << CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_SEL_MASK (0x1U << CRU_CLKSEL_CON16_REFCLKO25M_ETH1_OUT_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON17 */ +#define CRU_CLKSEL_CON17_OFFSET (0x344U) +#define CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_DIV_MASK (0xFFU << CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_SEL_MASK (0x3U << CRU_CLKSEL_CON17_CLK_CIFOUT_OUT_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON18 */ +#define CRU_CLKSEL_CON18_OFFSET (0x348U) +#define CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_DIV_MASK (0xFFU << CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_SEL_MASK (0x3U << CRU_CLKSEL_CON18_CLK_MIPI_CAMARAOUT_M0_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON19 */ +#define CRU_CLKSEL_CON19_OFFSET (0x34CU) +#define CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_DIV_MASK (0xFFU << CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_SEL_MASK (0x3U << CRU_CLKSEL_CON19_CLK_MIPI_CAMARAOUT_M1_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON20 */ +#define CRU_CLKSEL_CON20_OFFSET (0x350U) +#define CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_DIV_MASK (0xFFU << CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_SEL_MASK (0x3U << CRU_CLKSEL_CON20_CLK_MIPI_CAMARAOUT_M2_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON21 */ +#define CRU_CLKSEL_CON21_OFFSET (0x354U) +#define CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_DIV_MASK (0xFFU << CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_SEL_MASK (0x3U << CRU_CLKSEL_CON21_CLK_MIPI_CAMARAOUT_M3_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON22 */ +#define CRU_CLKSEL_CON22_OFFSET (0x358U) +#define CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_DIV_MASK (0xFFU << CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_SEL_MASK (0x3U << CRU_CLKSEL_CON22_CLK_MIPI_CAMARAOUT_M4_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON24 */ +#define CRU_CLKSEL_CON24_OFFSET (0x360U) +#define CRU_CLKSEL_CON24_HCLK_AUDIO_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON24_HCLK_AUDIO_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON24_HCLK_AUDIO_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON24_PCLK_AUDIO_ROOT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON24_PCLK_AUDIO_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON24_PCLK_AUDIO_ROOT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_DIV_SHIFT) /* 0x000001F0 */ +#define CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON24_CLK_I2S0_8CH_TX_SRC_SEL_SHIFT) /* 0x00000200 */ +/* CLKSEL_CON25 */ +#define CRU_CLKSEL_CON25_OFFSET (0x364U) +#define CRU_CLKSEL_CON25_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON25_CLK_I2S0_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON25_CLK_I2S0_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON26 */ +#define CRU_CLKSEL_CON26_OFFSET (0x368U) +#define CRU_CLKSEL_CON26_MCLK_I2S0_8CH_TX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON26_MCLK_I2S0_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON26_MCLK_I2S0_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON26_CLK_I2S0_8CH_RX_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON27 */ +#define CRU_CLKSEL_CON27_OFFSET (0x36CU) +#define CRU_CLKSEL_CON27_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON27_CLK_I2S0_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON27_CLK_I2S0_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON28 */ +#define CRU_CLKSEL_CON28_OFFSET (0x370U) +#define CRU_CLKSEL_CON28_MCLK_I2S0_8CH_RX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON28_MCLK_I2S0_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON28_MCLK_I2S0_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON28_I2S0_8CH_MCLKOUT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON28_I2S0_8CH_MCLKOUT_SEL_MASK (0x3U << CRU_CLKSEL_CON28_I2S0_8CH_MCLKOUT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_DIV_SHIFT) /* 0x000001F0 */ +#define CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON28_CLK_I2S2_2CH_SRC_SEL_SHIFT) /* 0x00000200 */ +/* CLKSEL_CON29 */ +#define CRU_CLKSEL_CON29_OFFSET (0x374U) +#define CRU_CLKSEL_CON29_CLK_I2S2_2CH_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON29_CLK_I2S2_2CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON29_CLK_I2S2_2CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON30 */ +#define CRU_CLKSEL_CON30_OFFSET (0x378U) +#define CRU_CLKSEL_CON30_MCLK_I2S2_2CH_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON30_MCLK_I2S2_2CH_SEL_MASK (0x3U << CRU_CLKSEL_CON30_MCLK_I2S2_2CH_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON30_I2S2_2CH_MCLKOUT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON30_I2S2_2CH_MCLKOUT_SEL_MASK (0x1U << CRU_CLKSEL_CON30_I2S2_2CH_MCLKOUT_SEL_SHIFT) /* 0x00000004 */ +#define CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON30_CLK_I2S3_2CH_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON31 */ +#define CRU_CLKSEL_CON31_OFFSET (0x37CU) +#define CRU_CLKSEL_CON31_CLK_I2S3_2CH_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON31_CLK_I2S3_2CH_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON31_CLK_I2S3_2CH_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON32 */ +#define CRU_CLKSEL_CON32_OFFSET (0x380U) +#define CRU_CLKSEL_CON32_MCLK_I2S3_2CH_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON32_MCLK_I2S3_2CH_SEL_MASK (0x3U << CRU_CLKSEL_CON32_MCLK_I2S3_2CH_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON32_I2S3_2CH_MCLKOUT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON32_I2S3_2CH_MCLKOUT_SEL_MASK (0x1U << CRU_CLKSEL_CON32_I2S3_2CH_MCLKOUT_SEL_SHIFT) /* 0x00000004 */ +#define CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON32_CLK_SPDIF0_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON33 */ +#define CRU_CLKSEL_CON33_OFFSET (0x384U) +#define CRU_CLKSEL_CON33_CLK_SPDIF0_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON33_CLK_SPDIF0_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON33_CLK_SPDIF0_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON34 */ +#define CRU_CLKSEL_CON34_OFFSET (0x388U) +#define CRU_CLKSEL_CON34_MCLK_SPDIF0_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON34_MCLK_SPDIF0_SEL_MASK (0x3U << CRU_CLKSEL_CON34_MCLK_SPDIF0_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON34_CLK_SPDIF1_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON35 */ +#define CRU_CLKSEL_CON35_OFFSET (0x38CU) +#define CRU_CLKSEL_CON35_CLK_SPDIF1_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON35_CLK_SPDIF1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON35_CLK_SPDIF1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON36 */ +#define CRU_CLKSEL_CON36_OFFSET (0x390U) +#define CRU_CLKSEL_CON36_MCLK_SPDIF1_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON36_MCLK_SPDIF1_SEL_MASK (0x3U << CRU_CLKSEL_CON36_MCLK_SPDIF1_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON36_MCLK_PDM1_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON36_MCLK_PDM1_DIV_MASK (0x1FU << CRU_CLKSEL_CON36_MCLK_PDM1_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON36_MCLK_PDM1_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON36_MCLK_PDM1_SEL_MASK (0x3U << CRU_CLKSEL_CON36_MCLK_PDM1_SEL_SHIFT) /* 0x00000180 */ +/* CLKSEL_CON38 */ +#define CRU_CLKSEL_CON38_OFFSET (0x398U) +#define CRU_CLKSEL_CON38_ACLK_BUS_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON38_ACLK_BUS_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON38_ACLK_BUS_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON38_ACLK_BUS_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON38_ACLK_BUS_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON38_ACLK_BUS_ROOT_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON38_CLK_I2C1_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON38_CLK_I2C1_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C1_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CLKSEL_CON38_CLK_I2C2_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON38_CLK_I2C2_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C2_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON38_CLK_I2C3_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON38_CLK_I2C3_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C3_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CLKSEL_CON38_CLK_I2C4_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON38_CLK_I2C4_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C4_SEL_SHIFT) /* 0x00000200 */ +#define CRU_CLKSEL_CON38_CLK_I2C5_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON38_CLK_I2C5_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C5_SEL_SHIFT) /* 0x00000400 */ +#define CRU_CLKSEL_CON38_CLK_I2C6_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON38_CLK_I2C6_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C6_SEL_SHIFT) /* 0x00000800 */ +#define CRU_CLKSEL_CON38_CLK_I2C7_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON38_CLK_I2C7_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C7_SEL_SHIFT) /* 0x00001000 */ +#define CRU_CLKSEL_CON38_CLK_I2C8_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON38_CLK_I2C8_SEL_MASK (0x1U << CRU_CLKSEL_CON38_CLK_I2C8_SEL_SHIFT) /* 0x00002000 */ +/* CLKSEL_CON39 */ +#define CRU_CLKSEL_CON39_OFFSET (0x39CU) +#define CRU_CLKSEL_CON39_CLK_CAN0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON39_CLK_CAN0_DIV_MASK (0x1FU << CRU_CLKSEL_CON39_CLK_CAN0_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON39_CLK_CAN0_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON39_CLK_CAN0_SEL_MASK (0x1U << CRU_CLKSEL_CON39_CLK_CAN0_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON39_CLK_CAN1_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON39_CLK_CAN1_DIV_MASK (0x1FU << CRU_CLKSEL_CON39_CLK_CAN1_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON39_CLK_CAN1_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON39_CLK_CAN1_SEL_MASK (0x1U << CRU_CLKSEL_CON39_CLK_CAN1_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON40 */ +#define CRU_CLKSEL_CON40_OFFSET (0x3A0U) +#define CRU_CLKSEL_CON40_CLK_CAN2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON40_CLK_CAN2_DIV_MASK (0x1FU << CRU_CLKSEL_CON40_CLK_CAN2_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON40_CLK_CAN2_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON40_CLK_CAN2_SEL_MASK (0x1U << CRU_CLKSEL_CON40_CLK_CAN2_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON40_CLK_SARADC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON40_CLK_SARADC_DIV_MASK (0xFFU << CRU_CLKSEL_CON40_CLK_SARADC_DIV_SHIFT) /* 0x00003FC0 */ +#define CRU_CLKSEL_CON40_CLK_SARADC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON40_CLK_SARADC_SEL_MASK (0x1U << CRU_CLKSEL_CON40_CLK_SARADC_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON41 */ +#define CRU_CLKSEL_CON41_OFFSET (0x3A4U) +#define CRU_CLKSEL_CON41_CLK_TSADC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON41_CLK_TSADC_DIV_MASK (0xFFU << CRU_CLKSEL_CON41_CLK_TSADC_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON41_CLK_TSADC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON41_CLK_TSADC_SEL_MASK (0x1U << CRU_CLKSEL_CON41_CLK_TSADC_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CLKSEL_CON41_CLK_UART1_SRC_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON41_CLK_UART1_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON41_CLK_UART1_SRC_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON41_CLK_UART1_SRC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON41_CLK_UART1_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON41_CLK_UART1_SRC_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON42 */ +#define CRU_CLKSEL_CON42_OFFSET (0x3A8U) +#define CRU_CLKSEL_CON42_CLK_UART1_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON42_CLK_UART1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON42_CLK_UART1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON43 */ +#define CRU_CLKSEL_CON43_OFFSET (0x3ACU) +#define CRU_CLKSEL_CON43_SCLK_UART1_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON43_SCLK_UART1_SEL_MASK (0x3U << CRU_CLKSEL_CON43_SCLK_UART1_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON43_CLK_UART2_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON43_CLK_UART2_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON43_CLK_UART2_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON43_CLK_UART2_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON43_CLK_UART2_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON43_CLK_UART2_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON44 */ +#define CRU_CLKSEL_CON44_OFFSET (0x3B0U) +#define CRU_CLKSEL_CON44_CLK_UART2_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON44_CLK_UART2_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON44_CLK_UART2_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON45 */ +#define CRU_CLKSEL_CON45_OFFSET (0x3B4U) +#define CRU_CLKSEL_CON45_SCLK_UART2_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON45_SCLK_UART2_SEL_MASK (0x3U << CRU_CLKSEL_CON45_SCLK_UART2_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON45_CLK_UART3_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON45_CLK_UART3_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON45_CLK_UART3_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON45_CLK_UART3_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON45_CLK_UART3_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON45_CLK_UART3_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON46 */ +#define CRU_CLKSEL_CON46_OFFSET (0x3B8U) +#define CRU_CLKSEL_CON46_CLK_UART3_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON46_CLK_UART3_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON46_CLK_UART3_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON47 */ +#define CRU_CLKSEL_CON47_OFFSET (0x3BCU) +#define CRU_CLKSEL_CON47_SCLK_UART3_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON47_SCLK_UART3_SEL_MASK (0x3U << CRU_CLKSEL_CON47_SCLK_UART3_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON47_CLK_UART4_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON47_CLK_UART4_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON47_CLK_UART4_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON47_CLK_UART4_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON47_CLK_UART4_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON47_CLK_UART4_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON48 */ +#define CRU_CLKSEL_CON48_OFFSET (0x3C0U) +#define CRU_CLKSEL_CON48_CLK_UART4_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON48_CLK_UART4_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON48_CLK_UART4_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON49 */ +#define CRU_CLKSEL_CON49_OFFSET (0x3C4U) +#define CRU_CLKSEL_CON49_SCLK_UART4_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON49_SCLK_UART4_SEL_MASK (0x3U << CRU_CLKSEL_CON49_SCLK_UART4_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON49_CLK_UART5_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON49_CLK_UART5_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON49_CLK_UART5_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON49_CLK_UART5_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON49_CLK_UART5_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON49_CLK_UART5_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON50 */ +#define CRU_CLKSEL_CON50_OFFSET (0x3C8U) +#define CRU_CLKSEL_CON50_CLK_UART5_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON50_CLK_UART5_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON50_CLK_UART5_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON51 */ +#define CRU_CLKSEL_CON51_OFFSET (0x3CCU) +#define CRU_CLKSEL_CON51_SCLK_UART5_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON51_SCLK_UART5_SEL_MASK (0x3U << CRU_CLKSEL_CON51_SCLK_UART5_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON51_CLK_UART6_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON51_CLK_UART6_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON51_CLK_UART6_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON51_CLK_UART6_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON51_CLK_UART6_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON51_CLK_UART6_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON52 */ +#define CRU_CLKSEL_CON52_OFFSET (0x3D0U) +#define CRU_CLKSEL_CON52_CLK_UART6_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON52_CLK_UART6_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON52_CLK_UART6_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON53 */ +#define CRU_CLKSEL_CON53_OFFSET (0x3D4U) +#define CRU_CLKSEL_CON53_SCLK_UART6_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON53_SCLK_UART6_SEL_MASK (0x3U << CRU_CLKSEL_CON53_SCLK_UART6_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON53_CLK_UART7_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON53_CLK_UART7_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON53_CLK_UART7_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON53_CLK_UART7_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON53_CLK_UART7_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON53_CLK_UART7_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON54 */ +#define CRU_CLKSEL_CON54_OFFSET (0x3D8U) +#define CRU_CLKSEL_CON54_CLK_UART7_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON54_CLK_UART7_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON54_CLK_UART7_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON55 */ +#define CRU_CLKSEL_CON55_OFFSET (0x3DCU) +#define CRU_CLKSEL_CON55_SCLK_UART7_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON55_SCLK_UART7_SEL_MASK (0x3U << CRU_CLKSEL_CON55_SCLK_UART7_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON55_CLK_UART8_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON55_CLK_UART8_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON55_CLK_UART8_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON55_CLK_UART8_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON55_CLK_UART8_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON55_CLK_UART8_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON56 */ +#define CRU_CLKSEL_CON56_OFFSET (0x3E0U) +#define CRU_CLKSEL_CON56_CLK_UART8_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON56_CLK_UART8_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON56_CLK_UART8_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON57 */ +#define CRU_CLKSEL_CON57_OFFSET (0x3E4U) +#define CRU_CLKSEL_CON57_SCLK_UART8_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON57_SCLK_UART8_SEL_MASK (0x3U << CRU_CLKSEL_CON57_SCLK_UART8_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON57_CLK_UART9_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON57_CLK_UART9_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON57_CLK_UART9_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON57_CLK_UART9_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON57_CLK_UART9_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON57_CLK_UART9_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON58 */ +#define CRU_CLKSEL_CON58_OFFSET (0x3E8U) +#define CRU_CLKSEL_CON58_CLK_UART9_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON58_CLK_UART9_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON58_CLK_UART9_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON59 */ +#define CRU_CLKSEL_CON59_OFFSET (0x3ECU) +#define CRU_CLKSEL_CON59_SCLK_UART9_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON59_SCLK_UART9_SEL_MASK (0x3U << CRU_CLKSEL_CON59_SCLK_UART9_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON59_CLK_SPI0_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON59_CLK_SPI0_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_SPI0_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON59_CLK_SPI1_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON59_CLK_SPI1_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_SPI1_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON59_CLK_SPI2_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON59_CLK_SPI2_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_SPI2_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON59_CLK_SPI3_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON59_CLK_SPI3_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_SPI3_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON59_CLK_SPI4_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON59_CLK_SPI4_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_SPI4_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON59_CLK_PWM1_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON59_CLK_PWM1_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_PWM1_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON59_CLK_PWM2_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON59_CLK_PWM2_SEL_MASK (0x3U << CRU_CLKSEL_CON59_CLK_PWM2_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON60 */ +#define CRU_CLKSEL_CON60_OFFSET (0x3F0U) +#define CRU_CLKSEL_CON60_CLK_PWM3_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON60_CLK_PWM3_SEL_MASK (0x3U << CRU_CLKSEL_CON60_CLK_PWM3_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON60_CLK_BUS_TIMER_ROOT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON60_CLK_BUS_TIMER_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON60_CLK_BUS_TIMER_ROOT_SEL_SHIFT) /* 0x00000004 */ +#define CRU_CLKSEL_CON60_DBCLK_GPIO1_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON60_DBCLK_GPIO1_DIV_MASK (0x1FU << CRU_CLKSEL_CON60_DBCLK_GPIO1_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON60_DBCLK_GPIO1_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON60_DBCLK_GPIO1_SEL_MASK (0x1U << CRU_CLKSEL_CON60_DBCLK_GPIO1_SEL_SHIFT) /* 0x00000100 */ +#define CRU_CLKSEL_CON60_DBCLK_GPIO2_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON60_DBCLK_GPIO2_DIV_MASK (0x1FU << CRU_CLKSEL_CON60_DBCLK_GPIO2_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON60_DBCLK_GPIO2_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON60_DBCLK_GPIO2_SEL_MASK (0x1U << CRU_CLKSEL_CON60_DBCLK_GPIO2_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON61 */ +#define CRU_CLKSEL_CON61_OFFSET (0x3F4U) +#define CRU_CLKSEL_CON61_DBCLK_GPIO3_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON61_DBCLK_GPIO3_DIV_MASK (0x1FU << CRU_CLKSEL_CON61_DBCLK_GPIO3_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON61_DBCLK_GPIO3_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON61_DBCLK_GPIO3_SEL_MASK (0x1U << CRU_CLKSEL_CON61_DBCLK_GPIO3_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON61_DBCLK_GPIO4_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON61_DBCLK_GPIO4_DIV_MASK (0x1FU << CRU_CLKSEL_CON61_DBCLK_GPIO4_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON61_DBCLK_GPIO4_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON61_DBCLK_GPIO4_SEL_MASK (0x1U << CRU_CLKSEL_CON61_DBCLK_GPIO4_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON62 */ +#define CRU_CLKSEL_CON62_OFFSET (0x3F8U) +#define CRU_CLKSEL_CON62_DCLK_DECOM_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON62_DCLK_DECOM_DIV_MASK (0x1FU << CRU_CLKSEL_CON62_DCLK_DECOM_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON62_DCLK_DECOM_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON62_DCLK_DECOM_SEL_MASK (0x1U << CRU_CLKSEL_CON62_DCLK_DECOM_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON62_CLK_BISRINTF_PLLSRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON62_CLK_BISRINTF_PLLSRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON62_CLK_BISRINTF_PLLSRC_DIV_SHIFT) /* 0x000007C0 */ +/* CLKSEL_CON63 */ +#define CRU_CLKSEL_CON63_OFFSET (0x3FCU) +#define CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_DIV_MASK (0x3FU << CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_SEL_MASK (0x1U << CRU_CLKSEL_CON63_CLK_TESTOUT_DDR01_SEL_SHIFT) /* 0x00000040 */ +/* CLKSEL_CON65 */ +#define CRU_CLKSEL_CON65_OFFSET (0x404U) +#define CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_DIV_MASK (0x3FU << CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_SEL_MASK (0x1U << CRU_CLKSEL_CON65_CLK_TESTOUT_DDR23_SEL_SHIFT) /* 0x00000040 */ +/* CLKSEL_CON67 */ +#define CRU_CLKSEL_CON67_OFFSET (0x40CU) +#define CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON67_ACLK_ISP1_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON67_HCLK_ISP1_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON67_HCLK_ISP1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON67_HCLK_ISP1_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON67_CLK_ISP1_CORE_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON67_CLK_ISP1_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON67_CLK_ISP1_CORE_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON67_CLK_ISP1_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON67_CLK_ISP1_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON67_CLK_ISP1_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON73 */ +#define CRU_CLKSEL_CON73_OFFSET (0x424U) +#define CRU_CLKSEL_CON73_HCLK_RKNN_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON73_HCLK_RKNN_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON73_HCLK_RKNN_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_DIV_MASK (0x1FU << CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_SEL_MASK (0x7U << CRU_CLKSEL_CON73_CLK_RKNN_DSU0_SRC_T_SEL_SHIFT) /* 0x00000380 */ +#define CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_DIV_SHIFT (10U) +#define CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_DIV_MASK (0x1FU << CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_DIV_SHIFT) /* 0x00007C00 */ +#define CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_SEL_MASK (0x1U << CRU_CLKSEL_CON73_CLK_TESTOUT_NPU_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON74 */ +#define CRU_CLKSEL_CON74_OFFSET (0x428U) +#define CRU_CLKSEL_CON74_CLK_RKNN_DSU0_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON74_CLK_RKNN_DSU0_SEL_MASK (0x1U << CRU_CLKSEL_CON74_CLK_RKNN_DSU0_SEL_SHIFT) /* 0x00000001 */ +#define CRU_CLKSEL_CON74_PCLK_NPUTOP_ROOT_SEL_SHIFT (1U) +#define CRU_CLKSEL_CON74_PCLK_NPUTOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON74_PCLK_NPUTOP_ROOT_SEL_SHIFT) /* 0x00000006 */ +#define CRU_CLKSEL_CON74_CLK_NPUTIMER_ROOT_SEL_SHIFT (3U) +#define CRU_CLKSEL_CON74_CLK_NPUTIMER_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON74_CLK_NPUTIMER_ROOT_SEL_SHIFT) /* 0x00000008 */ +#define CRU_CLKSEL_CON74_CLK_NPU_PVTPLL_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON74_CLK_NPU_PVTPLL_SEL_MASK (0x1U << CRU_CLKSEL_CON74_CLK_NPU_PVTPLL_SEL_SHIFT) /* 0x00000010 */ +#define CRU_CLKSEL_CON74_HCLK_NPU_CM0_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON74_HCLK_NPU_CM0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON74_HCLK_NPU_CM0_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_DIV_MASK (0x1FU << CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_SEL_MASK (0x1U << CRU_CLKSEL_CON74_CLK_NPU_CM0_RTC_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON77 */ +#define CRU_CLKSEL_CON77_OFFSET (0x434U) +#define CRU_CLKSEL_CON77_HCLK_NVM_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON77_HCLK_NVM_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON77_HCLK_NVM_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON77_ACLK_NVM_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON77_ACLK_NVM_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON77_ACLK_NVM_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON77_ACLK_NVM_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON77_ACLK_NVM_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON77_ACLK_NVM_ROOT_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON77_CCLK_EMMC_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON77_CCLK_EMMC_DIV_MASK (0x3FU << CRU_CLKSEL_CON77_CCLK_EMMC_DIV_SHIFT) /* 0x00003F00 */ +#define CRU_CLKSEL_CON77_CCLK_EMMC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON77_CCLK_EMMC_SEL_MASK (0x3U << CRU_CLKSEL_CON77_CCLK_EMMC_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON78 */ +#define CRU_CLKSEL_CON78_OFFSET (0x438U) +#define CRU_CLKSEL_CON78_BCLK_EMMC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON78_BCLK_EMMC_DIV_MASK (0x1FU << CRU_CLKSEL_CON78_BCLK_EMMC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON78_BCLK_EMMC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON78_BCLK_EMMC_SEL_MASK (0x1U << CRU_CLKSEL_CON78_BCLK_EMMC_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON78_SCLK_SFC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON78_SCLK_SFC_DIV_MASK (0x3FU << CRU_CLKSEL_CON78_SCLK_SFC_DIV_SHIFT) /* 0x00000FC0 */ +#define CRU_CLKSEL_CON78_SCLK_SFC_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON78_SCLK_SFC_SEL_MASK (0x3U << CRU_CLKSEL_CON78_SCLK_SFC_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON80 */ +#define CRU_CLKSEL_CON80_OFFSET (0x440U) +#define CRU_CLKSEL_CON80_PCLK_PHP_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON80_PCLK_PHP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON80_PCLK_PHP_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON80_ACLK_PCIE_ROOT_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON80_ACLK_PHP_ROOT_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON80_ACLK_PHP_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON80_ACLK_PHP_ROOT_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON80_ACLK_PHP_ROOT_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON80_ACLK_PHP_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON80_ACLK_PHP_ROOT_SEL_SHIFT) /* 0x00002000 */ +/* CLKSEL_CON81 */ +#define CRU_CLKSEL_CON81_OFFSET (0x444U) +#define CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_DIV_MASK (0x3FU << CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_SEL_MASK (0x1U << CRU_CLKSEL_CON81_CLK_GMAC0_PTP_REF_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_DIV_MASK (0x3FU << CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_DIV_SHIFT) /* 0x00001F80 */ +#define CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_SEL_MASK (0x1U << CRU_CLKSEL_CON81_CLK_GMAC1_PTP_REF_SEL_SHIFT) /* 0x00002000 */ +/* CLKSEL_CON82 */ +#define CRU_CLKSEL_CON82_OFFSET (0x448U) +#define CRU_CLKSEL_CON82_CLK_RXOOB0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON82_CLK_RXOOB0_DIV_MASK (0x7FU << CRU_CLKSEL_CON82_CLK_RXOOB0_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON82_CLK_RXOOB0_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON82_CLK_RXOOB0_SEL_MASK (0x1U << CRU_CLKSEL_CON82_CLK_RXOOB0_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON82_CLK_RXOOB1_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON82_CLK_RXOOB1_DIV_MASK (0x7FU << CRU_CLKSEL_CON82_CLK_RXOOB1_DIV_SHIFT) /* 0x00007F00 */ +#define CRU_CLKSEL_CON82_CLK_RXOOB1_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON82_CLK_RXOOB1_SEL_MASK (0x1U << CRU_CLKSEL_CON82_CLK_RXOOB1_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON83 */ +#define CRU_CLKSEL_CON83_OFFSET (0x44CU) +#define CRU_CLKSEL_CON83_CLK_RXOOB2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON83_CLK_RXOOB2_DIV_MASK (0x7FU << CRU_CLKSEL_CON83_CLK_RXOOB2_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON83_CLK_RXOOB2_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON83_CLK_RXOOB2_SEL_MASK (0x1U << CRU_CLKSEL_CON83_CLK_RXOOB2_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_DIV_MASK (0x7FU << CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_DIV_SHIFT) /* 0x00007F00 */ +#define CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_SEL_SHIFT (15U) +#define CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_SEL_MASK (0x1U << CRU_CLKSEL_CON83_CLK_GMAC_125M_CRU_I_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON84 */ +#define CRU_CLKSEL_CON84_OFFSET (0x450U) +#define CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_DIV_MASK (0x7FU << CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_SEL_MASK (0x1U << CRU_CLKSEL_CON84_CLK_GMAC_50M_CRU_I_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON84_CLK_UTMI_OTG2_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON84_CLK_UTMI_OTG2_DIV_MASK (0xFU << CRU_CLKSEL_CON84_CLK_UTMI_OTG2_DIV_SHIFT) /* 0x00000F00 */ +#define CRU_CLKSEL_CON84_CLK_UTMI_OTG2_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON84_CLK_UTMI_OTG2_SEL_MASK (0x3U << CRU_CLKSEL_CON84_CLK_UTMI_OTG2_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON85 */ +#define CRU_CLKSEL_CON85_OFFSET (0x454U) +#define CRU_CLKSEL_CON85_CLK_GMAC0_TX_125M_O_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON85_CLK_GMAC0_TX_125M_O_DIV_MASK (0x3FU << CRU_CLKSEL_CON85_CLK_GMAC0_TX_125M_O_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON85_CLK_GMAC1_TX_125M_O_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON85_CLK_GMAC1_TX_125M_O_DIV_MASK (0x3FU << CRU_CLKSEL_CON85_CLK_GMAC1_TX_125M_O_DIV_SHIFT) /* 0x00000FC0 */ +/* CLKSEL_CON89 */ +#define CRU_CLKSEL_CON89_OFFSET (0x464U) +#define CRU_CLKSEL_CON89_HCLK_RKVDEC0_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON89_HCLK_RKVDEC0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON89_HCLK_RKVDEC0_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON89_ACLK_RKVDEC0_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_DIV_MASK (0x1FU << CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_SEL_MASK (0x3U << CRU_CLKSEL_CON89_ACLK_RKVDEC_CCU_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON90 */ +#define CRU_CLKSEL_CON90_OFFSET (0x468U) +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_SEL_MASK (0x1U << CRU_CLKSEL_CON90_CLK_RKVDEC0_CA_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON90_CLK_RKVDEC0_HEVC_CA_SEL_SHIFT) /* 0x00001800 */ +/* CLKSEL_CON91 */ +#define CRU_CLKSEL_CON91_OFFSET (0x46CU) +#define CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_SEL_MASK (0x1U << CRU_CLKSEL_CON91_CLK_RKVDEC0_CORE_SEL_SHIFT) /* 0x00000020 */ +/* CLKSEL_CON93 */ +#define CRU_CLKSEL_CON93_OFFSET (0x474U) +#define CRU_CLKSEL_CON93_HCLK_RKVDEC1_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON93_HCLK_RKVDEC1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON93_HCLK_RKVDEC1_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON93_ACLK_RKVDEC1_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_SEL_MASK (0x1U << CRU_CLKSEL_CON93_CLK_RKVDEC1_CA_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON94 */ +#define CRU_CLKSEL_CON94_OFFSET (0x478U) +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_DIV_MASK (0x1FU << CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_SEL_MASK (0x3U << CRU_CLKSEL_CON94_CLK_RKVDEC1_HEVC_CA_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_SEL_MASK (0x1U << CRU_CLKSEL_CON94_CLK_RKVDEC1_CORE_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON96 */ +#define CRU_CLKSEL_CON96_OFFSET (0x480U) +#define CRU_CLKSEL_CON96_ACLK_USB_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON96_ACLK_USB_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON96_ACLK_USB_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON96_ACLK_USB_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON96_ACLK_USB_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON96_ACLK_USB_ROOT_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON96_HCLK_USB_ROOT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON96_HCLK_USB_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON96_HCLK_USB_ROOT_SEL_SHIFT) /* 0x000000C0 */ +/* CLKSEL_CON98 */ +#define CRU_CLKSEL_CON98_OFFSET (0x488U) +#define CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON98_ACLK_VDPU_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON98_ACLK_VDPU_LOW_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON98_ACLK_VDPU_LOW_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON98_ACLK_VDPU_LOW_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON98_HCLK_VDPU_ROOT_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON98_HCLK_VDPU_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON98_HCLK_VDPU_ROOT_SEL_SHIFT) /* 0x00000600 */ +/* CLKSEL_CON99 */ +#define CRU_CLKSEL_CON99_OFFSET (0x48CU) +#define CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON99_ACLK_JPEG_DECODER_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_SEL_MASK (0x1U << CRU_CLKSEL_CON99_CLK_IEP2P0_CORE_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON100 */ +#define CRU_CLKSEL_CON100_OFFSET (0x490U) +#define CRU_CLKSEL_CON100_CLK_RGA2_CORE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON100_CLK_RGA2_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON100_CLK_RGA2_CORE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON100_CLK_RGA2_CORE_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON100_CLK_RGA2_CORE_SEL_MASK (0x7U << CRU_CLKSEL_CON100_CLK_RGA2_CORE_SEL_SHIFT) /* 0x000000E0 */ +#define CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_SEL_MASK (0x7U << CRU_CLKSEL_CON100_CLK_RGA3_0_CORE_SEL_SHIFT) /* 0x0000E000 */ +/* CLKSEL_CON102 */ +#define CRU_CLKSEL_CON102_OFFSET (0x498U) +#define CRU_CLKSEL_CON102_HCLK_RKVENC0_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON102_HCLK_RKVENC0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON102_HCLK_RKVENC0_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON102_ACLK_RKVENC0_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON102_CLK_RKVENC0_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON104 */ +#define CRU_CLKSEL_CON104_OFFSET (0x4A0U) +#define CRU_CLKSEL_CON104_HCLK_RKVENC1_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON104_HCLK_RKVENC1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON104_HCLK_RKVENC1_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON104_ACLK_RKVENC1_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON104_CLK_RKVENC1_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON106 */ +#define CRU_CLKSEL_CON106_OFFSET (0x4A8U) +#define CRU_CLKSEL_CON106_ACLK_VI_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON106_ACLK_VI_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON106_ACLK_VI_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON106_ACLK_VI_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON106_ACLK_VI_ROOT_SEL_MASK (0x7U << CRU_CLKSEL_CON106_ACLK_VI_ROOT_SEL_SHIFT) /* 0x000000E0 */ +#define CRU_CLKSEL_CON106_HCLK_VI_ROOT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON106_HCLK_VI_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON106_HCLK_VI_ROOT_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON106_PCLK_VI_ROOT_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON106_PCLK_VI_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON106_PCLK_VI_ROOT_SEL_SHIFT) /* 0x00000C00 */ +/* CLKSEL_CON107 */ +#define CRU_CLKSEL_CON107_OFFSET (0x4ACU) +#define CRU_CLKSEL_CON107_DCLK_VICAP_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON107_DCLK_VICAP_DIV_MASK (0x1FU << CRU_CLKSEL_CON107_DCLK_VICAP_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON107_DCLK_VICAP_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON107_DCLK_VICAP_SEL_MASK (0x1U << CRU_CLKSEL_CON107_DCLK_VICAP_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON107_CLK_ISP0_CORE_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON107_CLK_ISP0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON107_CLK_ISP0_CORE_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON107_CLK_ISP0_CORE_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON107_CLK_ISP0_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON107_CLK_ISP0_CORE_SEL_SHIFT) /* 0x00001800 */ +/* CLKSEL_CON108 */ +#define CRU_CLKSEL_CON108_OFFSET (0x4B0U) +#define CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON108_CLK_FISHEYE0_CORE_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON108_CLK_FISHEYE1_CORE_SEL_SHIFT) /* 0x00003000 */ +#define CRU_CLKSEL_CON108_ICLK_CSIHOST01_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON108_ICLK_CSIHOST01_SEL_MASK (0x3U << CRU_CLKSEL_CON108_ICLK_CSIHOST01_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON110 */ +#define CRU_CLKSEL_CON110_OFFSET (0x4B8U) +#define CRU_CLKSEL_CON110_ACLK_VOP_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON110_ACLK_VOP_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON110_ACLK_VOP_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON110_ACLK_VOP_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON110_ACLK_VOP_ROOT_SEL_MASK (0x7U << CRU_CLKSEL_CON110_ACLK_VOP_ROOT_SEL_SHIFT) /* 0x000000E0 */ +#define CRU_CLKSEL_CON110_ACLK_VOP_LOW_ROOT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON110_ACLK_VOP_LOW_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON110_ACLK_VOP_LOW_ROOT_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON110_HCLK_VOP_ROOT_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON110_HCLK_VOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON110_HCLK_VOP_ROOT_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON110_PCLK_VOP_ROOT_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON110_PCLK_VOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON110_PCLK_VOP_ROOT_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON111 */ +#define CRU_CLKSEL_CON111_OFFSET (0x4BCU) +#define CRU_CLKSEL_CON111_DCLK_VOP0_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON111_DCLK_VOP0_SRC_DIV_MASK (0x7FU << CRU_CLKSEL_CON111_DCLK_VOP0_SRC_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON111_DCLK_VOP0_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON111_DCLK_VOP0_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON111_DCLK_VOP0_SRC_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON111_DCLK_VOP1_SRC_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON111_DCLK_VOP1_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON111_DCLK_VOP1_SRC_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON111_DCLK_VOP1_SRC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON111_DCLK_VOP1_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON111_DCLK_VOP1_SRC_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON112 */ +#define CRU_CLKSEL_CON112_OFFSET (0x4C0U) +#define CRU_CLKSEL_CON112_DCLK_VOP2_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON112_DCLK_VOP2_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON112_DCLK_VOP2_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON112_DCLK_VOP2_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON112_DCLK_VOP2_SRC_SEL_MASK (0x3U << CRU_CLKSEL_CON112_DCLK_VOP2_SRC_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON112_DCLK_VOP0_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON112_DCLK_VOP0_SEL_MASK (0x3U << CRU_CLKSEL_CON112_DCLK_VOP0_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON112_DCLK_VOP1_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON112_DCLK_VOP1_SEL_MASK (0x3U << CRU_CLKSEL_CON112_DCLK_VOP1_SEL_SHIFT) /* 0x00000600 */ +#define CRU_CLKSEL_CON112_DCLK_VOP2_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON112_DCLK_VOP2_SEL_MASK (0x3U << CRU_CLKSEL_CON112_DCLK_VOP2_SEL_SHIFT) /* 0x00001800 */ +/* CLKSEL_CON113 */ +#define CRU_CLKSEL_CON113_OFFSET (0x4C4U) +#define CRU_CLKSEL_CON113_DCLK_VOP3_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON113_DCLK_VOP3_DIV_MASK (0x7FU << CRU_CLKSEL_CON113_DCLK_VOP3_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON113_DCLK_VOP3_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON113_DCLK_VOP3_SEL_MASK (0x3U << CRU_CLKSEL_CON113_DCLK_VOP3_SEL_SHIFT) /* 0x00000180 */ +/* CLKSEL_CON114 */ +#define CRU_CLKSEL_CON114_OFFSET (0x4C8U) +#define CRU_CLKSEL_CON114_CLK_DSIHOST0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON114_CLK_DSIHOST0_DIV_MASK (0x7FU << CRU_CLKSEL_CON114_CLK_DSIHOST0_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON114_CLK_DSIHOST0_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON114_CLK_DSIHOST0_SEL_MASK (0x3U << CRU_CLKSEL_CON114_CLK_DSIHOST0_SEL_SHIFT) /* 0x00000180 */ +/* CLKSEL_CON115 */ +#define CRU_CLKSEL_CON115_OFFSET (0x4CCU) +#define CRU_CLKSEL_CON115_CLK_DSIHOST1_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON115_CLK_DSIHOST1_DIV_MASK (0x7FU << CRU_CLKSEL_CON115_CLK_DSIHOST1_DIV_SHIFT) /* 0x0000007F */ +#define CRU_CLKSEL_CON115_CLK_DSIHOST1_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON115_CLK_DSIHOST1_SEL_MASK (0x3U << CRU_CLKSEL_CON115_CLK_DSIHOST1_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON115_ACLK_VOP_SUB_SRC_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON115_ACLK_VOP_SUB_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON115_ACLK_VOP_SUB_SRC_SEL_SHIFT) /* 0x00000200 */ +/* CLKSEL_CON116 */ +#define CRU_CLKSEL_CON116_OFFSET (0x4D0U) +#define CRU_CLKSEL_CON116_ACLK_VO0_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON116_ACLK_VO0_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON116_ACLK_VO0_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON116_ACLK_VO0_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON116_ACLK_VO0_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON116_ACLK_VO0_ROOT_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON116_HCLK_VO0_ROOT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON116_HCLK_VO0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON116_HCLK_VO0_ROOT_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON116_HCLK_VO0_S_ROOT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON116_HCLK_VO0_S_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON116_HCLK_VO0_S_ROOT_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON116_PCLK_VO0_ROOT_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON116_PCLK_VO0_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON116_PCLK_VO0_ROOT_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON116_PCLK_VO0_S_ROOT_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON116_PCLK_VO0_S_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON116_PCLK_VO0_S_ROOT_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON117 */ +#define CRU_CLKSEL_CON117_OFFSET (0x4D4U) +#define CRU_CLKSEL_CON117_CLK_AUX16MHZ_0_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON117_CLK_AUX16MHZ_0_DIV_MASK (0xFFU << CRU_CLKSEL_CON117_CLK_AUX16MHZ_0_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON117_CLK_AUX16MHZ_1_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON117_CLK_AUX16MHZ_1_DIV_MASK (0xFFU << CRU_CLKSEL_CON117_CLK_AUX16MHZ_1_DIV_SHIFT) /* 0x0000FF00 */ +/* CLKSEL_CON118 */ +#define CRU_CLKSEL_CON118_OFFSET (0x4D8U) +#define CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON118_CLK_I2S4_8CH_TX_SRC_SEL_SHIFT) /* 0x00000020 */ +/* CLKSEL_CON119 */ +#define CRU_CLKSEL_CON119_OFFSET (0x4DCU) +#define CRU_CLKSEL_CON119_CLK_I2S4_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON119_CLK_I2S4_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON119_CLK_I2S4_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON120 */ +#define CRU_CLKSEL_CON120_OFFSET (0x4E0U) +#define CRU_CLKSEL_CON120_MCLK_I2S4_8CH_TX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON120_MCLK_I2S4_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON120_MCLK_I2S4_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON120_CLK_I2S8_8CH_TX_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON121 */ +#define CRU_CLKSEL_CON121_OFFSET (0x4E4U) +#define CRU_CLKSEL_CON121_CLK_I2S8_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON121_CLK_I2S8_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON121_CLK_I2S8_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON122 */ +#define CRU_CLKSEL_CON122_OFFSET (0x4E8U) +#define CRU_CLKSEL_CON122_MCLK_I2S8_8CH_TX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON122_MCLK_I2S8_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON122_MCLK_I2S8_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON122_CLK_SPDIF2_DP0_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON123 */ +#define CRU_CLKSEL_CON123_OFFSET (0x4ECU) +#define CRU_CLKSEL_CON123_CLK_SPDIF2_DP0_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON123_CLK_SPDIF2_DP0_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON123_CLK_SPDIF2_DP0_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON124 */ +#define CRU_CLKSEL_CON124_OFFSET (0x4F0U) +#define CRU_CLKSEL_CON124_MCLK_4X_SPDIF2_DP0_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON124_MCLK_4X_SPDIF2_DP0_SEL_MASK (0x3U << CRU_CLKSEL_CON124_MCLK_4X_SPDIF2_DP0_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON124_CLK_SPDIF5_DP1_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON125 */ +#define CRU_CLKSEL_CON125_OFFSET (0x4F4U) +#define CRU_CLKSEL_CON125_CLK_SPDIF5_DP1_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON125_CLK_SPDIF5_DP1_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON125_CLK_SPDIF5_DP1_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON126 */ +#define CRU_CLKSEL_CON126_OFFSET (0x4F8U) +#define CRU_CLKSEL_CON126_MCLK_4X_SPDIF5_DP1_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON126_MCLK_4X_SPDIF5_DP1_SEL_MASK (0x3U << CRU_CLKSEL_CON126_MCLK_4X_SPDIF5_DP1_SEL_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON128 */ +#define CRU_CLKSEL_CON128_OFFSET (0x500U) +#define CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON128_ACLK_HDCP1_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON128_ACLK_HDMIRX_ROOT_SEL_SHIFT) /* 0x00001000 */ +#define CRU_CLKSEL_CON128_HCLK_VO1_ROOT_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON128_HCLK_VO1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON128_HCLK_VO1_ROOT_SEL_SHIFT) /* 0x00006000 */ +/* CLKSEL_CON129 */ +#define CRU_CLKSEL_CON129_OFFSET (0x504U) +#define CRU_CLKSEL_CON129_HCLK_VO1_S_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON129_HCLK_VO1_S_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON129_HCLK_VO1_S_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON129_PCLK_VO1_ROOT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON129_PCLK_VO1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON129_PCLK_VO1_ROOT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON129_PCLK_VO1_S_ROOT_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON129_PCLK_VO1_S_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON129_PCLK_VO1_S_ROOT_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_DIV_SHIFT) /* 0x000007C0 */ +#define CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_SEL_SHIFT (11U) +#define CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON129_CLK_I2S7_8CH_RX_SRC_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON130 */ +#define CRU_CLKSEL_CON130_OFFSET (0x508U) +#define CRU_CLKSEL_CON130_CLK_I2S7_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON130_CLK_I2S7_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON130_CLK_I2S7_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON131 */ +#define CRU_CLKSEL_CON131_OFFSET (0x50CU) +#define CRU_CLKSEL_CON131_MCLK_I2S7_8CH_RX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON131_MCLK_I2S7_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON131_MCLK_I2S7_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON133 */ +#define CRU_CLKSEL_CON133_OFFSET (0x514U) +#define CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_DIV_SHIFT (1U) +#define CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_DIV_MASK (0x1FU << CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_DIV_SHIFT) /* 0x0000003E */ +#define CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_SEL_MASK (0x1U << CRU_CLKSEL_CON133_CLK_HDMITX0_EARC_SEL_SHIFT) /* 0x00000040 */ +/* CLKSEL_CON136 */ +#define CRU_CLKSEL_CON136_OFFSET (0x520U) +#define CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_DIV_SHIFT (1U) +#define CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_DIV_MASK (0x1FU << CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_DIV_SHIFT) /* 0x0000003E */ +#define CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_SEL_MASK (0x1U << CRU_CLKSEL_CON136_CLK_HDMITX1_EARC_SEL_SHIFT) /* 0x00000040 */ +/* CLKSEL_CON138 */ +#define CRU_CLKSEL_CON138_OFFSET (0x528U) +#define CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_DIV_MASK (0xFFU << CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_DIV_SHIFT) /* 0x000000FF */ +#define CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON138_CLK_HDMIRX_AUD_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON139 */ +#define CRU_CLKSEL_CON139_OFFSET (0x52CU) +#define CRU_CLKSEL_CON139_CLK_HDMIRX_AUD_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON139_CLK_HDMIRX_AUD_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON139_CLK_HDMIRX_AUD_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON140 */ +#define CRU_CLKSEL_CON140_OFFSET (0x530U) +#define CRU_CLKSEL_CON140_CLK_HDMIRX_AUD_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON140_CLK_HDMIRX_AUD_SEL_MASK (0x1U << CRU_CLKSEL_CON140_CLK_HDMIRX_AUD_SEL_SHIFT) /* 0x00000001 */ +#define CRU_CLKSEL_CON140_CLK_EDP0_200M_SEL_SHIFT (1U) +#define CRU_CLKSEL_CON140_CLK_EDP0_200M_SEL_MASK (0x3U << CRU_CLKSEL_CON140_CLK_EDP0_200M_SEL_SHIFT) /* 0x00000006 */ +#define CRU_CLKSEL_CON140_CLK_EDP1_200M_SEL_SHIFT (3U) +#define CRU_CLKSEL_CON140_CLK_EDP1_200M_SEL_MASK (0x3U << CRU_CLKSEL_CON140_CLK_EDP1_200M_SEL_SHIFT) /* 0x00000018 */ +#define CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_DIV_SHIFT (5U) +#define CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_DIV_SHIFT) /* 0x000003E0 */ +#define CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON140_CLK_I2S5_8CH_TX_SRC_SEL_SHIFT) /* 0x00000400 */ +/* CLKSEL_CON141 */ +#define CRU_CLKSEL_CON141_OFFSET (0x534U) +#define CRU_CLKSEL_CON141_CLK_I2S5_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON141_CLK_I2S5_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON141_CLK_I2S5_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON142 */ +#define CRU_CLKSEL_CON142_OFFSET (0x538U) +#define CRU_CLKSEL_CON142_MCLK_I2S5_8CH_TX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON142_MCLK_I2S5_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON142_MCLK_I2S5_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON144 */ +#define CRU_CLKSEL_CON144_OFFSET (0x540U) +#define CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON144_CLK_I2S6_8CH_TX_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON145 */ +#define CRU_CLKSEL_CON145_OFFSET (0x544U) +#define CRU_CLKSEL_CON145_CLK_I2S6_8CH_TX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON145_CLK_I2S6_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON145_CLK_I2S6_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON146 */ +#define CRU_CLKSEL_CON146_OFFSET (0x548U) +#define CRU_CLKSEL_CON146_MCLK_I2S6_8CH_TX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON146_MCLK_I2S6_8CH_TX_SEL_MASK (0x3U << CRU_CLKSEL_CON146_MCLK_I2S6_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON146_CLK_I2S6_8CH_RX_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON147 */ +#define CRU_CLKSEL_CON147_OFFSET (0x54CU) +#define CRU_CLKSEL_CON147_CLK_I2S6_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON147_CLK_I2S6_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON147_CLK_I2S6_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON148 */ +#define CRU_CLKSEL_CON148_OFFSET (0x550U) +#define CRU_CLKSEL_CON148_MCLK_I2S6_8CH_RX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON148_MCLK_I2S6_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON148_MCLK_I2S6_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON148_I2S6_8CH_MCLKOUT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON148_I2S6_8CH_MCLKOUT_SEL_MASK (0x3U << CRU_CLKSEL_CON148_I2S6_8CH_MCLKOUT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_DIV_SHIFT (4U) +#define CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_DIV_SHIFT) /* 0x000001F0 */ +#define CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_SEL_SHIFT (9U) +#define CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON148_CLK_SPDIF3_SRC_SEL_SHIFT) /* 0x00000200 */ +/* CLKSEL_CON149 */ +#define CRU_CLKSEL_CON149_OFFSET (0x554U) +#define CRU_CLKSEL_CON149_CLK_SPDIF3_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON149_CLK_SPDIF3_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON149_CLK_SPDIF3_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON150 */ +#define CRU_CLKSEL_CON150_OFFSET (0x558U) +#define CRU_CLKSEL_CON150_MCLK_SPDIF3_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON150_MCLK_SPDIF3_SEL_MASK (0x3U << CRU_CLKSEL_CON150_MCLK_SPDIF3_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON150_CLK_SPDIF4_SRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON151 */ +#define CRU_CLKSEL_CON151_OFFSET (0x55CU) +#define CRU_CLKSEL_CON151_CLK_SPDIF4_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON151_CLK_SPDIF4_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON151_CLK_SPDIF4_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON152 */ +#define CRU_CLKSEL_CON152_OFFSET (0x560U) +#define CRU_CLKSEL_CON152_MCLK_SPDIF4_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON152_MCLK_SPDIF4_SEL_MASK (0x3U << CRU_CLKSEL_CON152_MCLK_SPDIF4_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX0_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX0_DIV_MASK (0x1FU << CRU_CLKSEL_CON152_MCLK_SPDIFRX0_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX0_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX0_SEL_MASK (0x3U << CRU_CLKSEL_CON152_MCLK_SPDIFRX0_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX1_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX1_DIV_MASK (0x1FU << CRU_CLKSEL_CON152_MCLK_SPDIFRX1_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX1_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON152_MCLK_SPDIFRX1_SEL_MASK (0x3U << CRU_CLKSEL_CON152_MCLK_SPDIFRX1_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON153 */ +#define CRU_CLKSEL_CON153_OFFSET (0x564U) +#define CRU_CLKSEL_CON153_MCLK_SPDIFRX2_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON153_MCLK_SPDIFRX2_DIV_MASK (0x1FU << CRU_CLKSEL_CON153_MCLK_SPDIFRX2_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON153_MCLK_SPDIFRX2_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON153_MCLK_SPDIFRX2_SEL_MASK (0x3U << CRU_CLKSEL_CON153_MCLK_SPDIFRX2_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_DIV_SHIFT (7U) +#define CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_DIV_SHIFT) /* 0x00000F80 */ +#define CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON153_CLK_I2S9_8CH_RX_SRC_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON154 */ +#define CRU_CLKSEL_CON154_OFFSET (0x568U) +#define CRU_CLKSEL_CON154_CLK_I2S9_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON154_CLK_I2S9_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON154_CLK_I2S9_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON155 */ +#define CRU_CLKSEL_CON155_OFFSET (0x56CU) +#define CRU_CLKSEL_CON155_MCLK_I2S9_8CH_RX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON155_MCLK_I2S9_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON155_MCLK_I2S9_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_DIV_SHIFT (3U) +#define CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_DIV_SHIFT) /* 0x000000F8 */ +#define CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON155_CLK_I2S10_8CH_RX_SRC_SEL_SHIFT) /* 0x00000100 */ +/* CLKSEL_CON156 */ +#define CRU_CLKSEL_CON156_OFFSET (0x570U) +#define CRU_CLKSEL_CON156_CLK_I2S10_8CH_RX_FRAC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON156_CLK_I2S10_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << CRU_CLKSEL_CON156_CLK_I2S10_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON157 */ +#define CRU_CLKSEL_CON157_OFFSET (0x574U) +#define CRU_CLKSEL_CON157_MCLK_I2S10_8CH_RX_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON157_MCLK_I2S10_8CH_RX_SEL_MASK (0x3U << CRU_CLKSEL_CON157_MCLK_I2S10_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_DIV_MASK (0x1FU << CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_DIV_SHIFT) /* 0x0000007C */ +#define CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_SEL_MASK (0x1U << CRU_CLKSEL_CON157_CLK_HDMITRX_REFSRC_SEL_SHIFT) /* 0x00000080 */ +/* CLKSEL_CON158 */ +#define CRU_CLKSEL_CON158_OFFSET (0x578U) +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_T_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_T_DIV_MASK (0x1FU << CRU_CLKSEL_CON158_CLK_GPU_SRC_T_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_T_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_T_SEL_MASK (0x7U << CRU_CLKSEL_CON158_CLK_GPU_SRC_T_SEL_SHIFT) /* 0x000000E0 */ +#define CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_DIV_SHIFT (8U) +#define CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_DIV_MASK (0x1FU << CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_DIV_SHIFT) /* 0x00001F00 */ +#define CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_SEL_SHIFT (13U) +#define CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_SEL_MASK (0x1U << CRU_CLKSEL_CON158_CLK_TESTOUT_GPU_SEL_SHIFT) /* 0x00002000 */ +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON158_CLK_GPU_SRC_SEL_MASK (0x1U << CRU_CLKSEL_CON158_CLK_GPU_SRC_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON159 */ +#define CRU_CLKSEL_CON159_OFFSET (0x57CU) +#define CRU_CLKSEL_CON159_CLK_GPU_STACKS_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON159_CLK_GPU_STACKS_DIV_MASK (0x1FU << CRU_CLKSEL_CON159_CLK_GPU_STACKS_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON159_ACLK_S_GPU_BIU_DIV_SHIFT (5U) +#define CRU_CLKSEL_CON159_ACLK_S_GPU_BIU_DIV_MASK (0x1FU << CRU_CLKSEL_CON159_ACLK_S_GPU_BIU_DIV_SHIFT) /* 0x000003E0 */ +#define CRU_CLKSEL_CON159_ACLK_M0_GPU_BIU_DIV_SHIFT (10U) +#define CRU_CLKSEL_CON159_ACLK_M0_GPU_BIU_DIV_MASK (0x1FU << CRU_CLKSEL_CON159_ACLK_M0_GPU_BIU_DIV_SHIFT) /* 0x00007C00 */ +/* CLKSEL_CON160 */ +#define CRU_CLKSEL_CON160_OFFSET (0x580U) +#define CRU_CLKSEL_CON160_ACLK_M1_GPU_BIU_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON160_ACLK_M1_GPU_BIU_DIV_MASK (0x1FU << CRU_CLKSEL_CON160_ACLK_M1_GPU_BIU_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON160_ACLK_M2_GPU_BIU_DIV_SHIFT (5U) +#define CRU_CLKSEL_CON160_ACLK_M2_GPU_BIU_DIV_MASK (0x1FU << CRU_CLKSEL_CON160_ACLK_M2_GPU_BIU_DIV_SHIFT) /* 0x000003E0 */ +#define CRU_CLKSEL_CON160_ACLK_M3_GPU_BIU_DIV_SHIFT (10U) +#define CRU_CLKSEL_CON160_ACLK_M3_GPU_BIU_DIV_MASK (0x1FU << CRU_CLKSEL_CON160_ACLK_M3_GPU_BIU_DIV_SHIFT) /* 0x00007C00 */ +/* CLKSEL_CON161 */ +#define CRU_CLKSEL_CON161_OFFSET (0x584U) +#define CRU_CLKSEL_CON161_PCLK_GPU_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON161_PCLK_GPU_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON161_PCLK_GPU_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON161_CLK_GPU_PVTPLL_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON161_CLK_GPU_PVTPLL_SEL_MASK (0x1U << CRU_CLKSEL_CON161_CLK_GPU_PVTPLL_SEL_SHIFT) /* 0x00000004 */ +/* CLKSEL_CON163 */ +#define CRU_CLKSEL_CON163_OFFSET (0x58CU) +#define CRU_CLKSEL_CON163_ACLK_AV1_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON163_ACLK_AV1_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON163_ACLK_AV1_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON163_ACLK_AV1_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON163_ACLK_AV1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON163_ACLK_AV1_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON163_PCLK_AV1_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON163_PCLK_AV1_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON163_PCLK_AV1_ROOT_SEL_SHIFT) /* 0x00000180 */ +/* CLKSEL_CON165 */ +#define CRU_CLKSEL_CON165_OFFSET (0x594U) +#define CRU_CLKSEL_CON165_ACLK_CENTER_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON165_ACLK_CENTER_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_ACLK_CENTER_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON165_ACLK_CENTER_LOW_ROOT_SEL_SHIFT (2U) +#define CRU_CLKSEL_CON165_ACLK_CENTER_LOW_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_ACLK_CENTER_LOW_ROOT_SEL_SHIFT) /* 0x0000000C */ +#define CRU_CLKSEL_CON165_HCLK_CENTER_ROOT_SEL_SHIFT (4U) +#define CRU_CLKSEL_CON165_HCLK_CENTER_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_HCLK_CENTER_ROOT_SEL_SHIFT) /* 0x00000030 */ +#define CRU_CLKSEL_CON165_PCLK_CENTER_ROOT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON165_PCLK_CENTER_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_PCLK_CENTER_ROOT_SEL_SHIFT) /* 0x000000C0 */ +#define CRU_CLKSEL_CON165_ACLK_CENTER_S200_ROOT_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON165_ACLK_CENTER_S200_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_ACLK_CENTER_S200_ROOT_SEL_SHIFT) /* 0x00000300 */ +#define CRU_CLKSEL_CON165_ACLK_CENTER_S400_ROOT_SEL_SHIFT (10U) +#define CRU_CLKSEL_CON165_ACLK_CENTER_S400_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON165_ACLK_CENTER_S400_ROOT_SEL_SHIFT) /* 0x00000C00 */ +#define CRU_CLKSEL_CON165_CLK_DDR_TIMER_ROOT_SEL_SHIFT (12U) +#define CRU_CLKSEL_CON165_CLK_DDR_TIMER_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON165_CLK_DDR_TIMER_ROOT_SEL_SHIFT) /* 0x00001000 */ +/* CLKSEL_CON166 */ +#define CRU_CLKSEL_CON166_OFFSET (0x598U) +#define CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_DIV_MASK (0x1FU << CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_SEL_MASK (0x1U << CRU_CLKSEL_CON166_CLK_DDR_CM0_RTC_SEL_SHIFT) /* 0x00000020 */ +/* CLKSEL_CON170 */ +#define CRU_CLKSEL_CON170_OFFSET (0x5A8U) +#define CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_SEL_MASK (0x1U << CRU_CLKSEL_CON170_ACLK_VO1USB_TOP_ROOT_SEL_SHIFT) /* 0x00000020 */ +#define CRU_CLKSEL_CON170_HCLK_VO1USB_TOP_ROOT_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON170_HCLK_VO1USB_TOP_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON170_HCLK_VO1USB_TOP_ROOT_SEL_SHIFT) /* 0x000000C0 */ +/* CLKSEL_CON172 */ +#define CRU_CLKSEL_CON172_OFFSET (0x5B0U) +#define CRU_CLKSEL_CON172_HCLK_SDIO_ROOT_SEL_SHIFT (0U) +#define CRU_CLKSEL_CON172_HCLK_SDIO_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON172_HCLK_SDIO_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define CRU_CLKSEL_CON172_CCLK_SRC_SDIO_DIV_SHIFT (2U) +#define CRU_CLKSEL_CON172_CCLK_SRC_SDIO_DIV_MASK (0x3FU << CRU_CLKSEL_CON172_CCLK_SRC_SDIO_DIV_SHIFT) /* 0x000000FC */ +#define CRU_CLKSEL_CON172_CCLK_SRC_SDIO_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON172_CCLK_SRC_SDIO_SEL_MASK (0x3U << CRU_CLKSEL_CON172_CCLK_SRC_SDIO_SEL_SHIFT) /* 0x00000300 */ +/* CLKSEL_CON174 */ +#define CRU_CLKSEL_CON174_OFFSET (0x5B8U) +#define CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_DIV_MASK (0x1FU << CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_SEL_SHIFT (5U) +#define CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON174_ACLK_RGA3_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define CRU_CLKSEL_CON174_HCLK_RGA3_ROOT_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON174_HCLK_RGA3_ROOT_SEL_MASK (0x3U << CRU_CLKSEL_CON174_HCLK_RGA3_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_DIV_SHIFT (9U) +#define CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_DIV_MASK (0x1FU << CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_DIV_SHIFT) /* 0x00003E00 */ +#define CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_SEL_SHIFT (14U) +#define CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_SEL_MASK (0x3U << CRU_CLKSEL_CON174_CLK_RGA3_1_CORE_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON176 */ +#define CRU_CLKSEL_CON176_OFFSET (0x5C0U) +#define CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY0_PLL_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY0_PLL_SRC_DIV_MASK (0x3FU << CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY0_PLL_SRC_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY1_PLL_SRC_DIV_SHIFT (6U) +#define CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY1_PLL_SRC_DIV_MASK (0x3FU << CRU_CLKSEL_CON176_CLK_REF_PIPE_PHY1_PLL_SRC_DIV_SHIFT) /* 0x00000FC0 */ +/* CLKSEL_CON177 */ +#define CRU_CLKSEL_CON177_OFFSET (0x5C4U) +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_PLL_SRC_DIV_SHIFT (0U) +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_PLL_SRC_DIV_MASK (0x3FU << CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_PLL_SRC_DIV_SHIFT) /* 0x0000003F */ +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY0_SEL_SHIFT (6U) +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY0_SEL_MASK (0x1U << CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY0_SEL_SHIFT) /* 0x00000040 */ +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY1_SEL_SHIFT (7U) +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY1_SEL_MASK (0x1U << CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY1_SEL_SHIFT) /* 0x00000080 */ +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_SEL_SHIFT (8U) +#define CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_SEL_MASK (0x1U << CRU_CLKSEL_CON177_CLK_REF_PIPE_PHY2_SEL_SHIFT) /* 0x00000100 */ +/* GATE_CON00 */ +#define CRU_GATE_CON00_OFFSET (0x800U) +#define CRU_GATE_CON00_CLK_MATRIX_50M_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON00_CLK_MATRIX_50M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_50M_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON00_CLK_MATRIX_100M_SRC_EN_SHIFT (1U) +#define CRU_GATE_CON00_CLK_MATRIX_100M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_100M_SRC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON00_CLK_MATRIX_150M_SRC_EN_SHIFT (2U) +#define CRU_GATE_CON00_CLK_MATRIX_150M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_150M_SRC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON00_CLK_MATRIX_200M_SRC_EN_SHIFT (3U) +#define CRU_GATE_CON00_CLK_MATRIX_200M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_200M_SRC_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON00_CLK_MATRIX_250M_SRC_EN_SHIFT (4U) +#define CRU_GATE_CON00_CLK_MATRIX_250M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_250M_SRC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON00_CLK_MATRIX_300M_SRC_EN_SHIFT (5U) +#define CRU_GATE_CON00_CLK_MATRIX_300M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_300M_SRC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON00_CLK_MATRIX_350M_SRC_EN_SHIFT (6U) +#define CRU_GATE_CON00_CLK_MATRIX_350M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_350M_SRC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON00_CLK_MATRIX_400M_SRC_EN_SHIFT (7U) +#define CRU_GATE_CON00_CLK_MATRIX_400M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_400M_SRC_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON00_CLK_MATRIX_450M_SRC_EN_SHIFT (8U) +#define CRU_GATE_CON00_CLK_MATRIX_450M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_450M_SRC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON00_CLK_MATRIX_500M_SRC_EN_SHIFT (9U) +#define CRU_GATE_CON00_CLK_MATRIX_500M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_500M_SRC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON00_CLK_MATRIX_600M_SRC_EN_SHIFT (10U) +#define CRU_GATE_CON00_CLK_MATRIX_600M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_600M_SRC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON00_CLK_MATRIX_650M_SRC_EN_SHIFT (11U) +#define CRU_GATE_CON00_CLK_MATRIX_650M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_650M_SRC_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON00_CLK_MATRIX_700M_SRC_EN_SHIFT (12U) +#define CRU_GATE_CON00_CLK_MATRIX_700M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_700M_SRC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON00_CLK_MATRIX_800M_SRC_EN_SHIFT (13U) +#define CRU_GATE_CON00_CLK_MATRIX_800M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_800M_SRC_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON00_CLK_MATRIX_1000M_SRC_EN_SHIFT (14U) +#define CRU_GATE_CON00_CLK_MATRIX_1000M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_1000M_SRC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON00_CLK_MATRIX_1200M_SRC_EN_SHIFT (15U) +#define CRU_GATE_CON00_CLK_MATRIX_1200M_SRC_EN_MASK (0x1U << CRU_GATE_CON00_CLK_MATRIX_1200M_SRC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define CRU_GATE_CON01_OFFSET (0x804U) +#define CRU_GATE_CON01_ACLK_TOP_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON01_ACLK_TOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON01_PCLK_TOP_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON01_PCLK_TOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_TOP_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON01_ACLK_LOW_TOP_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON01_ACLK_LOW_TOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_LOW_TOP_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON01_ACLK_TOP_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON01_ACLK_TOP_BIU_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON01_PCLK_TOP_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON01_PCLK_TOP_BIU_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_TOP_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON01_PCLK_CSIPHY0_EN_SHIFT (6U) +#define CRU_GATE_CON01_PCLK_CSIPHY0_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CSIPHY0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON01_PCLK_CSIPHY1_EN_SHIFT (8U) +#define CRU_GATE_CON01_PCLK_CSIPHY1_EN_MASK (0x1U << CRU_GATE_CON01_PCLK_CSIPHY1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON01_ACLK_TOP_M300_ROOT_EN_SHIFT (10U) +#define CRU_GATE_CON01_ACLK_TOP_M300_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_M300_ROOT_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON01_ACLK_TOP_M500_ROOT_EN_SHIFT (11U) +#define CRU_GATE_CON01_ACLK_TOP_M500_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_M500_ROOT_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON01_ACLK_TOP_M400_ROOT_EN_SHIFT (12U) +#define CRU_GATE_CON01_ACLK_TOP_M400_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_M400_ROOT_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON01_ACLK_TOP_S200_ROOT_EN_SHIFT (13U) +#define CRU_GATE_CON01_ACLK_TOP_S200_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_S200_ROOT_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON01_ACLK_TOP_S400_ROOT_EN_SHIFT (14U) +#define CRU_GATE_CON01_ACLK_TOP_S400_ROOT_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_S400_ROOT_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON01_ACLK_TOP_M500_BIU_EN_SHIFT (15U) +#define CRU_GATE_CON01_ACLK_TOP_M500_BIU_EN_MASK (0x1U << CRU_GATE_CON01_ACLK_TOP_M500_BIU_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON02 */ +#define CRU_GATE_CON02_OFFSET (0x808U) +#define CRU_GATE_CON02_ACLK_TOP_M400_BIU_EN_SHIFT (0U) +#define CRU_GATE_CON02_ACLK_TOP_M400_BIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_TOP_M400_BIU_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON02_ACLK_TOP_S200_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON02_ACLK_TOP_S200_BIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_TOP_S200_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON02_ACLK_TOP_S400_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON02_ACLK_TOP_S400_BIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_TOP_S400_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON02_ACLK_TOP_M300_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON02_ACLK_TOP_M300_BIU_EN_MASK (0x1U << CRU_GATE_CON02_ACLK_TOP_M300_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON02_CLK_TESTOUT_TOP_EN_SHIFT (4U) +#define CRU_GATE_CON02_CLK_TESTOUT_TOP_EN_MASK (0x1U << CRU_GATE_CON02_CLK_TESTOUT_TOP_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON02_CLK_TESTOUT_GRP0_EN_SHIFT (6U) +#define CRU_GATE_CON02_CLK_TESTOUT_GRP0_EN_MASK (0x1U << CRU_GATE_CON02_CLK_TESTOUT_GRP0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON02_CLK_USBDP_COMBO_PHY0_IMMORTAL_EN_SHIFT (8U) +#define CRU_GATE_CON02_CLK_USBDP_COMBO_PHY0_IMMORTAL_EN_MASK (0x1U << CRU_GATE_CON02_CLK_USBDP_COMBO_PHY0_IMMORTAL_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON02_CLK_USBDP_COMBO_PHY1_IMMORTAL_EN_SHIFT (15U) +#define CRU_GATE_CON02_CLK_USBDP_COMBO_PHY1_IMMORTAL_EN_MASK (0x1U << CRU_GATE_CON02_CLK_USBDP_COMBO_PHY1_IMMORTAL_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON03 */ +#define CRU_GATE_CON03_OFFSET (0x80CU) +#define CRU_GATE_CON03_PCLK_MIPI_DCPHY0_EN_SHIFT (14U) +#define CRU_GATE_CON03_PCLK_MIPI_DCPHY0_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_MIPI_DCPHY0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON03_PCLK_MIPI_DCPHY0_GRF_EN_SHIFT (15U) +#define CRU_GATE_CON03_PCLK_MIPI_DCPHY0_GRF_EN_MASK (0x1U << CRU_GATE_CON03_PCLK_MIPI_DCPHY0_GRF_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON04 */ +#define CRU_GATE_CON04_OFFSET (0x810U) +#define CRU_GATE_CON04_PCLK_MIPI_DCPHY1_EN_SHIFT (3U) +#define CRU_GATE_CON04_PCLK_MIPI_DCPHY1_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_MIPI_DCPHY1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON04_PCLK_MIPI_DCPHY1_GRF_EN_SHIFT (4U) +#define CRU_GATE_CON04_PCLK_MIPI_DCPHY1_GRF_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_MIPI_DCPHY1_GRF_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_CDPHY_EN_SHIFT (5U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_CDPHY_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_CDPHY_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_CSIPHY_EN_SHIFT (6U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_CSIPHY_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_CSIPHY_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO3_5_EN_SHIFT (7U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO3_5_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO3_5_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO6_EN_SHIFT (8U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO6_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_VCCIO6_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_EMMCIO_EN_SHIFT (9U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_EMMCIO_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_EMMCIO_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_TOP_EN_SHIFT (10U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_TOP_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_TOP_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_RIGHT_EN_SHIFT (11U) +#define CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_RIGHT_EN_MASK (0x1U << CRU_GATE_CON04_PCLK_APB2ASB_SLV_IOC_RIGHT_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON05 */ +#define CRU_GATE_CON05_OFFSET (0x814U) +#define CRU_GATE_CON05_PCLK_CRU_EN_SHIFT (0U) +#define CRU_GATE_CON05_PCLK_CRU_EN_MASK (0x1U << CRU_GATE_CON05_PCLK_CRU_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON05_MCLK_GMAC0_OUT_EN_SHIFT (3U) +#define CRU_GATE_CON05_MCLK_GMAC0_OUT_EN_MASK (0x1U << CRU_GATE_CON05_MCLK_GMAC0_OUT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON05_REFCLKO25M_ETH0_OUT_EN_SHIFT (4U) +#define CRU_GATE_CON05_REFCLKO25M_ETH0_OUT_EN_MASK (0x1U << CRU_GATE_CON05_REFCLKO25M_ETH0_OUT_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON05_REFCLKO25M_ETH1_OUT_EN_SHIFT (5U) +#define CRU_GATE_CON05_REFCLKO25M_ETH1_OUT_EN_MASK (0x1U << CRU_GATE_CON05_REFCLKO25M_ETH1_OUT_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON05_CLK_CIFOUT_OUT_EN_SHIFT (6U) +#define CRU_GATE_CON05_CLK_CIFOUT_OUT_EN_MASK (0x1U << CRU_GATE_CON05_CLK_CIFOUT_OUT_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON05_ACLK_CHANNEL_SECURE2VO1USB_EN_SHIFT (7U) +#define CRU_GATE_CON05_ACLK_CHANNEL_SECURE2VO1USB_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_CHANNEL_SECURE2VO1USB_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON05_ACLK_CHANNEL_SECURE2CENTER_EN_SHIFT (8U) +#define CRU_GATE_CON05_ACLK_CHANNEL_SECURE2CENTER_EN_MASK (0x1U << CRU_GATE_CON05_ACLK_CHANNEL_SECURE2CENTER_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M0_EN_SHIFT (9U) +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M0_EN_MASK (0x1U << CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M0_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M1_EN_SHIFT (10U) +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M1_EN_MASK (0x1U << CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M2_EN_SHIFT (11U) +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M2_EN_MASK (0x1U << CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M2_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M3_EN_SHIFT (12U) +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M3_EN_MASK (0x1U << CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M3_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M4_EN_SHIFT (13U) +#define CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M4_EN_MASK (0x1U << CRU_GATE_CON05_CLK_MIPI_CAMERAOUT_M4_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON05_HCLK_CHANNEL_SECURE2VO1USB_EN_SHIFT (14U) +#define CRU_GATE_CON05_HCLK_CHANNEL_SECURE2VO1USB_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_CHANNEL_SECURE2VO1USB_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON05_HCLK_CHANNEL_SECURE2CENTER_EN_SHIFT (15U) +#define CRU_GATE_CON05_HCLK_CHANNEL_SECURE2CENTER_EN_MASK (0x1U << CRU_GATE_CON05_HCLK_CHANNEL_SECURE2CENTER_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON06 */ +#define CRU_GATE_CON06_OFFSET (0x818U) +#define CRU_GATE_CON06_PCLK_CHANNEL_SECURE2VO1USB_EN_SHIFT (0U) +#define CRU_GATE_CON06_PCLK_CHANNEL_SECURE2VO1USB_EN_MASK (0x1U << CRU_GATE_CON06_PCLK_CHANNEL_SECURE2VO1USB_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON06_PCLK_CHANNEL_SECURE2CENTER_EN_SHIFT (1U) +#define CRU_GATE_CON06_PCLK_CHANNEL_SECURE2CENTER_EN_MASK (0x1U << CRU_GATE_CON06_PCLK_CHANNEL_SECURE2CENTER_EN_SHIFT) /* 0x00000002 */ +/* GATE_CON07 */ +#define CRU_GATE_CON07_OFFSET (0x81CU) +#define CRU_GATE_CON07_HCLK_AUDIO_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON07_HCLK_AUDIO_ROOT_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_AUDIO_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON07_PCLK_AUDIO_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON07_PCLK_AUDIO_ROOT_EN_MASK (0x1U << CRU_GATE_CON07_PCLK_AUDIO_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON07_HCLK_AUDIO_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON07_HCLK_AUDIO_BIU_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_AUDIO_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON07_PCLK_AUDIO_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON07_PCLK_AUDIO_BIU_EN_MASK (0x1U << CRU_GATE_CON07_PCLK_AUDIO_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON07_HCLK_I2S0_8CH_EN_SHIFT (4U) +#define CRU_GATE_CON07_HCLK_I2S0_8CH_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_I2S0_8CH_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON07_CLK_I2S0_8CH_TX_EN_SHIFT (5U) +#define CRU_GATE_CON07_CLK_I2S0_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S0_8CH_TX_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_TX_EN_SHIFT (6U) +#define CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_TX_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_TX_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON07_MCLK_I2S0_8CH_TX_EN_SHIFT (7U) +#define CRU_GATE_CON07_MCLK_I2S0_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S0_8CH_TX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON07_CLK_I2S0_8CH_RX_EN_SHIFT (8U) +#define CRU_GATE_CON07_CLK_I2S0_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S0_8CH_RX_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_RX_EN_SHIFT (9U) +#define CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_RX_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S0_8CH_FRAC_RX_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON07_MCLK_I2S0_8CH_RX_EN_SHIFT (10U) +#define CRU_GATE_CON07_MCLK_I2S0_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON07_MCLK_I2S0_8CH_RX_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON07_PCLK_ACDCDIG_EN_SHIFT (11U) +#define CRU_GATE_CON07_PCLK_ACDCDIG_EN_MASK (0x1U << CRU_GATE_CON07_PCLK_ACDCDIG_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON07_HCLK_I2S2_2CH_EN_SHIFT (12U) +#define CRU_GATE_CON07_HCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_I2S2_2CH_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON07_HCLK_I2S3_2CH_EN_SHIFT (13U) +#define CRU_GATE_CON07_HCLK_I2S3_2CH_EN_MASK (0x1U << CRU_GATE_CON07_HCLK_I2S3_2CH_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON07_CLK_I2S2_2CH_EN_SHIFT (14U) +#define CRU_GATE_CON07_CLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT (15U) +#define CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON07_CLK_I2S2_2CH_FRAC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON08 */ +#define CRU_GATE_CON08_OFFSET (0x820U) +#define CRU_GATE_CON08_MCLK_I2S2_2CH_EN_SHIFT (0U) +#define CRU_GATE_CON08_MCLK_I2S2_2CH_EN_MASK (0x1U << CRU_GATE_CON08_MCLK_I2S2_2CH_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON08_CLK_I2S3_2CH_EN_SHIFT (1U) +#define CRU_GATE_CON08_CLK_I2S3_2CH_EN_MASK (0x1U << CRU_GATE_CON08_CLK_I2S3_2CH_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON08_CLK_I2S3_2CH_FRAC_EN_SHIFT (2U) +#define CRU_GATE_CON08_CLK_I2S3_2CH_FRAC_EN_MASK (0x1U << CRU_GATE_CON08_CLK_I2S3_2CH_FRAC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON08_MCLK_I2S3_2CH_EN_SHIFT (3U) +#define CRU_GATE_CON08_MCLK_I2S3_2CH_EN_MASK (0x1U << CRU_GATE_CON08_MCLK_I2S3_2CH_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON08_CLK_DAC_ACDCDIG_EN_SHIFT (4U) +#define CRU_GATE_CON08_CLK_DAC_ACDCDIG_EN_MASK (0x1U << CRU_GATE_CON08_CLK_DAC_ACDCDIG_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON08_HCLK_SPDIF0_EN_SHIFT (14U) +#define CRU_GATE_CON08_HCLK_SPDIF0_EN_MASK (0x1U << CRU_GATE_CON08_HCLK_SPDIF0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON08_CLK_SPDIF0_EN_SHIFT (15U) +#define CRU_GATE_CON08_CLK_SPDIF0_EN_MASK (0x1U << CRU_GATE_CON08_CLK_SPDIF0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON09 */ +#define CRU_GATE_CON09_OFFSET (0x824U) +#define CRU_GATE_CON09_CLK_SPDIF0_FRAC_EN_SHIFT (0U) +#define CRU_GATE_CON09_CLK_SPDIF0_FRAC_EN_MASK (0x1U << CRU_GATE_CON09_CLK_SPDIF0_FRAC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON09_MCLK_SPDIF0_EN_SHIFT (1U) +#define CRU_GATE_CON09_MCLK_SPDIF0_EN_MASK (0x1U << CRU_GATE_CON09_MCLK_SPDIF0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON09_HCLK_SPDIF1_EN_SHIFT (2U) +#define CRU_GATE_CON09_HCLK_SPDIF1_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_SPDIF1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON09_CLK_SPDIF1_EN_SHIFT (3U) +#define CRU_GATE_CON09_CLK_SPDIF1_EN_MASK (0x1U << CRU_GATE_CON09_CLK_SPDIF1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON09_CLK_SPDIF1_FRAC_EN_SHIFT (4U) +#define CRU_GATE_CON09_CLK_SPDIF1_FRAC_EN_MASK (0x1U << CRU_GATE_CON09_CLK_SPDIF1_FRAC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON09_MCLK_SPDIF1_EN_SHIFT (5U) +#define CRU_GATE_CON09_MCLK_SPDIF1_EN_MASK (0x1U << CRU_GATE_CON09_MCLK_SPDIF1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON09_HCLK_PDM1_EN_SHIFT (6U) +#define CRU_GATE_CON09_HCLK_PDM1_EN_MASK (0x1U << CRU_GATE_CON09_HCLK_PDM1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON09_MCLK_PDM1_EN_SHIFT (7U) +#define CRU_GATE_CON09_MCLK_PDM1_EN_MASK (0x1U << CRU_GATE_CON09_MCLK_PDM1_EN_SHIFT) /* 0x00000080 */ +/* GATE_CON10 */ +#define CRU_GATE_CON10_OFFSET (0x828U) +#define CRU_GATE_CON10_ACLK_BUS_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON10_ACLK_BUS_ROOT_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_BUS_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON10_ACLK_BUS_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON10_ACLK_BUS_BIU_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_BUS_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON10_PCLK_BUS_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON10_PCLK_BUS_BIU_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_BUS_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON10_ACLK_GIC_EN_SHIFT (3U) +#define CRU_GATE_CON10_ACLK_GIC_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_GIC_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON10_ACLK_DMAC0_EN_SHIFT (5U) +#define CRU_GATE_CON10_ACLK_DMAC0_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_DMAC0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON10_ACLK_DMAC1_EN_SHIFT (6U) +#define CRU_GATE_CON10_ACLK_DMAC1_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_DMAC1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON10_ACLK_DMAC2_EN_SHIFT (7U) +#define CRU_GATE_CON10_ACLK_DMAC2_EN_MASK (0x1U << CRU_GATE_CON10_ACLK_DMAC2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON10_PCLK_I2C1_EN_SHIFT (8U) +#define CRU_GATE_CON10_PCLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON10_PCLK_I2C2_EN_SHIFT (9U) +#define CRU_GATE_CON10_PCLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C2_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON10_PCLK_I2C3_EN_SHIFT (10U) +#define CRU_GATE_CON10_PCLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C3_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON10_PCLK_I2C4_EN_SHIFT (11U) +#define CRU_GATE_CON10_PCLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C4_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON10_PCLK_I2C5_EN_SHIFT (12U) +#define CRU_GATE_CON10_PCLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C5_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON10_PCLK_I2C6_EN_SHIFT (13U) +#define CRU_GATE_CON10_PCLK_I2C6_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C6_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON10_PCLK_I2C7_EN_SHIFT (14U) +#define CRU_GATE_CON10_PCLK_I2C7_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C7_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON10_PCLK_I2C8_EN_SHIFT (15U) +#define CRU_GATE_CON10_PCLK_I2C8_EN_MASK (0x1U << CRU_GATE_CON10_PCLK_I2C8_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON11 */ +#define CRU_GATE_CON11_OFFSET (0x82CU) +#define CRU_GATE_CON11_CLK_I2C1_EN_SHIFT (0U) +#define CRU_GATE_CON11_CLK_I2C1_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON11_CLK_I2C2_EN_SHIFT (1U) +#define CRU_GATE_CON11_CLK_I2C2_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON11_CLK_I2C3_EN_SHIFT (2U) +#define CRU_GATE_CON11_CLK_I2C3_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON11_CLK_I2C4_EN_SHIFT (3U) +#define CRU_GATE_CON11_CLK_I2C4_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C4_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON11_CLK_I2C5_EN_SHIFT (4U) +#define CRU_GATE_CON11_CLK_I2C5_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C5_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON11_CLK_I2C6_EN_SHIFT (5U) +#define CRU_GATE_CON11_CLK_I2C6_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C6_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON11_CLK_I2C7_EN_SHIFT (6U) +#define CRU_GATE_CON11_CLK_I2C7_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C7_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON11_CLK_I2C8_EN_SHIFT (7U) +#define CRU_GATE_CON11_CLK_I2C8_EN_MASK (0x1U << CRU_GATE_CON11_CLK_I2C8_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON11_PCLK_CAN0_EN_SHIFT (8U) +#define CRU_GATE_CON11_PCLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON11_PCLK_CAN0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON11_CLK_CAN0_EN_SHIFT (9U) +#define CRU_GATE_CON11_CLK_CAN0_EN_MASK (0x1U << CRU_GATE_CON11_CLK_CAN0_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON11_PCLK_CAN1_EN_SHIFT (10U) +#define CRU_GATE_CON11_PCLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON11_PCLK_CAN1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON11_CLK_CAN1_EN_SHIFT (11U) +#define CRU_GATE_CON11_CLK_CAN1_EN_MASK (0x1U << CRU_GATE_CON11_CLK_CAN1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON11_PCLK_CAN2_EN_SHIFT (12U) +#define CRU_GATE_CON11_PCLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON11_PCLK_CAN2_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON11_CLK_CAN2_EN_SHIFT (13U) +#define CRU_GATE_CON11_CLK_CAN2_EN_MASK (0x1U << CRU_GATE_CON11_CLK_CAN2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON11_PCLK_SARADC_EN_SHIFT (14U) +#define CRU_GATE_CON11_PCLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON11_PCLK_SARADC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON11_CLK_SARADC_EN_SHIFT (15U) +#define CRU_GATE_CON11_CLK_SARADC_EN_MASK (0x1U << CRU_GATE_CON11_CLK_SARADC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON12 */ +#define CRU_GATE_CON12_OFFSET (0x830U) +#define CRU_GATE_CON12_PCLK_TSADC_EN_SHIFT (0U) +#define CRU_GATE_CON12_PCLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_TSADC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON12_CLK_TSADC_EN_SHIFT (1U) +#define CRU_GATE_CON12_CLK_TSADC_EN_MASK (0x1U << CRU_GATE_CON12_CLK_TSADC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON12_PCLK_UART1_EN_SHIFT (2U) +#define CRU_GATE_CON12_PCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON12_PCLK_UART2_EN_SHIFT (3U) +#define CRU_GATE_CON12_PCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON12_PCLK_UART3_EN_SHIFT (4U) +#define CRU_GATE_CON12_PCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON12_PCLK_UART4_EN_SHIFT (5U) +#define CRU_GATE_CON12_PCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART4_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON12_PCLK_UART5_EN_SHIFT (6U) +#define CRU_GATE_CON12_PCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART5_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON12_PCLK_UART6_EN_SHIFT (7U) +#define CRU_GATE_CON12_PCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART6_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON12_PCLK_UART7_EN_SHIFT (8U) +#define CRU_GATE_CON12_PCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART7_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON12_PCLK_UART8_EN_SHIFT (9U) +#define CRU_GATE_CON12_PCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART8_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON12_PCLK_UART9_EN_SHIFT (10U) +#define CRU_GATE_CON12_PCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON12_PCLK_UART9_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON12_CLK_UART1_EN_SHIFT (11U) +#define CRU_GATE_CON12_CLK_UART1_EN_MASK (0x1U << CRU_GATE_CON12_CLK_UART1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON12_CLK_UART1_FRAC_EN_SHIFT (12U) +#define CRU_GATE_CON12_CLK_UART1_FRAC_EN_MASK (0x1U << CRU_GATE_CON12_CLK_UART1_FRAC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON12_SCLK_UART1_EN_SHIFT (13U) +#define CRU_GATE_CON12_SCLK_UART1_EN_MASK (0x1U << CRU_GATE_CON12_SCLK_UART1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON12_CLK_UART2_EN_SHIFT (14U) +#define CRU_GATE_CON12_CLK_UART2_EN_MASK (0x1U << CRU_GATE_CON12_CLK_UART2_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON12_CLK_UART2_FRAC_EN_SHIFT (15U) +#define CRU_GATE_CON12_CLK_UART2_FRAC_EN_MASK (0x1U << CRU_GATE_CON12_CLK_UART2_FRAC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON13 */ +#define CRU_GATE_CON13_OFFSET (0x834U) +#define CRU_GATE_CON13_SCLK_UART2_EN_SHIFT (0U) +#define CRU_GATE_CON13_SCLK_UART2_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON13_CLK_UART3_EN_SHIFT (1U) +#define CRU_GATE_CON13_CLK_UART3_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART3_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON13_CLK_UART3_FRAC_EN_SHIFT (2U) +#define CRU_GATE_CON13_CLK_UART3_FRAC_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART3_FRAC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON13_SCLK_UART3_EN_SHIFT (3U) +#define CRU_GATE_CON13_SCLK_UART3_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART3_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON13_CLK_UART4_EN_SHIFT (4U) +#define CRU_GATE_CON13_CLK_UART4_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART4_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON13_CLK_UART4_FRAC_EN_SHIFT (5U) +#define CRU_GATE_CON13_CLK_UART4_FRAC_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART4_FRAC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON13_SCLK_UART4_EN_SHIFT (6U) +#define CRU_GATE_CON13_SCLK_UART4_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART4_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON13_CLK_UART5_EN_SHIFT (7U) +#define CRU_GATE_CON13_CLK_UART5_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART5_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON13_CLK_UART5_FRAC_EN_SHIFT (8U) +#define CRU_GATE_CON13_CLK_UART5_FRAC_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART5_FRAC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON13_SCLK_UART5_EN_SHIFT (9U) +#define CRU_GATE_CON13_SCLK_UART5_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART5_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON13_CLK_UART6_EN_SHIFT (10U) +#define CRU_GATE_CON13_CLK_UART6_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART6_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON13_CLK_UART6_FRAC_EN_SHIFT (11U) +#define CRU_GATE_CON13_CLK_UART6_FRAC_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART6_FRAC_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON13_SCLK_UART6_EN_SHIFT (12U) +#define CRU_GATE_CON13_SCLK_UART6_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART6_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON13_CLK_UART7_EN_SHIFT (13U) +#define CRU_GATE_CON13_CLK_UART7_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART7_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON13_CLK_UART7_FRAC_EN_SHIFT (14U) +#define CRU_GATE_CON13_CLK_UART7_FRAC_EN_MASK (0x1U << CRU_GATE_CON13_CLK_UART7_FRAC_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON13_SCLK_UART7_EN_SHIFT (15U) +#define CRU_GATE_CON13_SCLK_UART7_EN_MASK (0x1U << CRU_GATE_CON13_SCLK_UART7_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON14 */ +#define CRU_GATE_CON14_OFFSET (0x838U) +#define CRU_GATE_CON14_CLK_UART8_EN_SHIFT (0U) +#define CRU_GATE_CON14_CLK_UART8_EN_MASK (0x1U << CRU_GATE_CON14_CLK_UART8_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON14_CLK_UART8_FRAC_EN_SHIFT (1U) +#define CRU_GATE_CON14_CLK_UART8_FRAC_EN_MASK (0x1U << CRU_GATE_CON14_CLK_UART8_FRAC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON14_SCLK_UART8_EN_SHIFT (2U) +#define CRU_GATE_CON14_SCLK_UART8_EN_MASK (0x1U << CRU_GATE_CON14_SCLK_UART8_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON14_CLK_UART9_EN_SHIFT (3U) +#define CRU_GATE_CON14_CLK_UART9_EN_MASK (0x1U << CRU_GATE_CON14_CLK_UART9_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON14_CLK_UART9_FRAC_EN_SHIFT (4U) +#define CRU_GATE_CON14_CLK_UART9_FRAC_EN_MASK (0x1U << CRU_GATE_CON14_CLK_UART9_FRAC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON14_SCLK_UART9_EN_SHIFT (5U) +#define CRU_GATE_CON14_SCLK_UART9_EN_MASK (0x1U << CRU_GATE_CON14_SCLK_UART9_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON14_PCLK_SPI0_EN_SHIFT (6U) +#define CRU_GATE_CON14_PCLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_SPI0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON14_PCLK_SPI1_EN_SHIFT (7U) +#define CRU_GATE_CON14_PCLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_SPI1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON14_PCLK_SPI2_EN_SHIFT (8U) +#define CRU_GATE_CON14_PCLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_SPI2_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON14_PCLK_SPI3_EN_SHIFT (9U) +#define CRU_GATE_CON14_PCLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_SPI3_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON14_PCLK_SPI4_EN_SHIFT (10U) +#define CRU_GATE_CON14_PCLK_SPI4_EN_MASK (0x1U << CRU_GATE_CON14_PCLK_SPI4_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON14_CLK_SPI0_EN_SHIFT (11U) +#define CRU_GATE_CON14_CLK_SPI0_EN_MASK (0x1U << CRU_GATE_CON14_CLK_SPI0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON14_CLK_SPI1_EN_SHIFT (12U) +#define CRU_GATE_CON14_CLK_SPI1_EN_MASK (0x1U << CRU_GATE_CON14_CLK_SPI1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON14_CLK_SPI2_EN_SHIFT (13U) +#define CRU_GATE_CON14_CLK_SPI2_EN_MASK (0x1U << CRU_GATE_CON14_CLK_SPI2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON14_CLK_SPI3_EN_SHIFT (14U) +#define CRU_GATE_CON14_CLK_SPI3_EN_MASK (0x1U << CRU_GATE_CON14_CLK_SPI3_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON14_CLK_SPI4_EN_SHIFT (15U) +#define CRU_GATE_CON14_CLK_SPI4_EN_MASK (0x1U << CRU_GATE_CON14_CLK_SPI4_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON15 */ +#define CRU_GATE_CON15_OFFSET (0x83CU) +#define CRU_GATE_CON15_PCLK_WDT0_EN_SHIFT (0U) +#define CRU_GATE_CON15_PCLK_WDT0_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_WDT0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON15_TCLK_WDT0_EN_SHIFT (1U) +#define CRU_GATE_CON15_TCLK_WDT0_EN_MASK (0x1U << CRU_GATE_CON15_TCLK_WDT0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON15_PCLK_SYS_GRF_EN_SHIFT (2U) +#define CRU_GATE_CON15_PCLK_SYS_GRF_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_SYS_GRF_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON15_PCLK_PWM1_EN_SHIFT (3U) +#define CRU_GATE_CON15_PCLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_PWM1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON15_CLK_PWM1_EN_SHIFT (4U) +#define CRU_GATE_CON15_CLK_PWM1_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON15_CLK_PWM1_CAPTURE_EN_SHIFT (5U) +#define CRU_GATE_CON15_CLK_PWM1_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM1_CAPTURE_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON15_PCLK_PWM2_EN_SHIFT (6U) +#define CRU_GATE_CON15_PCLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_PWM2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON15_CLK_PWM2_EN_SHIFT (7U) +#define CRU_GATE_CON15_CLK_PWM2_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON15_CLK_PWM2_CAPTURE_EN_SHIFT (8U) +#define CRU_GATE_CON15_CLK_PWM2_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM2_CAPTURE_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON15_PCLK_PWM3_EN_SHIFT (9U) +#define CRU_GATE_CON15_PCLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_PWM3_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON15_CLK_PWM3_EN_SHIFT (10U) +#define CRU_GATE_CON15_CLK_PWM3_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM3_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON15_CLK_PWM3_CAPTURE_EN_SHIFT (11U) +#define CRU_GATE_CON15_CLK_PWM3_CAPTURE_EN_MASK (0x1U << CRU_GATE_CON15_CLK_PWM3_CAPTURE_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON15_PCLK_BUSTIMER0_EN_SHIFT (12U) +#define CRU_GATE_CON15_PCLK_BUSTIMER0_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_BUSTIMER0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON15_PCLK_BUSTIMER1_EN_SHIFT (13U) +#define CRU_GATE_CON15_PCLK_BUSTIMER1_EN_MASK (0x1U << CRU_GATE_CON15_PCLK_BUSTIMER1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON15_CLK_BUSTIMER_ROOT_EN_SHIFT (14U) +#define CRU_GATE_CON15_CLK_BUSTIMER_ROOT_EN_MASK (0x1U << CRU_GATE_CON15_CLK_BUSTIMER_ROOT_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON15_CLK_BUSTIMER0_EN_SHIFT (15U) +#define CRU_GATE_CON15_CLK_BUSTIMER0_EN_MASK (0x1U << CRU_GATE_CON15_CLK_BUSTIMER0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON16 */ +#define CRU_GATE_CON16_OFFSET (0x840U) +#define CRU_GATE_CON16_CLK_BUSTIMER1_EN_SHIFT (0U) +#define CRU_GATE_CON16_CLK_BUSTIMER1_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON16_CLK_BUSTIMER2_EN_SHIFT (1U) +#define CRU_GATE_CON16_CLK_BUSTIMER2_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON16_CLK_BUSTIMER3_EN_SHIFT (2U) +#define CRU_GATE_CON16_CLK_BUSTIMER3_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON16_CLK_BUSTIMER4_EN_SHIFT (3U) +#define CRU_GATE_CON16_CLK_BUSTIMER4_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER4_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON16_CLK_BUSTIMER5_EN_SHIFT (4U) +#define CRU_GATE_CON16_CLK_BUSTIMER5_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER5_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON16_CLK_BUSTIMER6_EN_SHIFT (5U) +#define CRU_GATE_CON16_CLK_BUSTIMER6_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER6_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON16_CLK_BUSTIMER7_EN_SHIFT (6U) +#define CRU_GATE_CON16_CLK_BUSTIMER7_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER7_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON16_CLK_BUSTIMER8_EN_SHIFT (7U) +#define CRU_GATE_CON16_CLK_BUSTIMER8_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER8_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON16_CLK_BUSTIMER9_EN_SHIFT (8U) +#define CRU_GATE_CON16_CLK_BUSTIMER9_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER9_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON16_CLK_BUSTIMER10_EN_SHIFT (9U) +#define CRU_GATE_CON16_CLK_BUSTIMER10_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER10_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON16_CLK_BUSTIMER11_EN_SHIFT (10U) +#define CRU_GATE_CON16_CLK_BUSTIMER11_EN_MASK (0x1U << CRU_GATE_CON16_CLK_BUSTIMER11_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON16_PCLK_MAILBOX0_EN_SHIFT (11U) +#define CRU_GATE_CON16_PCLK_MAILBOX0_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_MAILBOX0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON16_PCLK_MAILBOX1_EN_SHIFT (12U) +#define CRU_GATE_CON16_PCLK_MAILBOX1_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_MAILBOX1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON16_PCLK_MAILBOX2_EN_SHIFT (13U) +#define CRU_GATE_CON16_PCLK_MAILBOX2_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_MAILBOX2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON16_PCLK_GPIO1_EN_SHIFT (14U) +#define CRU_GATE_CON16_PCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON16_PCLK_GPIO1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON16_DBCLK_GPIO1_EN_SHIFT (15U) +#define CRU_GATE_CON16_DBCLK_GPIO1_EN_MASK (0x1U << CRU_GATE_CON16_DBCLK_GPIO1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON17 */ +#define CRU_GATE_CON17_OFFSET (0x844U) +#define CRU_GATE_CON17_PCLK_GPIO2_EN_SHIFT (0U) +#define CRU_GATE_CON17_PCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_GPIO2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON17_DBCLK_GPIO2_EN_SHIFT (1U) +#define CRU_GATE_CON17_DBCLK_GPIO2_EN_MASK (0x1U << CRU_GATE_CON17_DBCLK_GPIO2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON17_PCLK_GPIO3_EN_SHIFT (2U) +#define CRU_GATE_CON17_PCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_GPIO3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON17_DBCLK_GPIO3_EN_SHIFT (3U) +#define CRU_GATE_CON17_DBCLK_GPIO3_EN_MASK (0x1U << CRU_GATE_CON17_DBCLK_GPIO3_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON17_PCLK_GPIO4_EN_SHIFT (4U) +#define CRU_GATE_CON17_PCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_GPIO4_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON17_DBCLK_GPIO4_EN_SHIFT (5U) +#define CRU_GATE_CON17_DBCLK_GPIO4_EN_MASK (0x1U << CRU_GATE_CON17_DBCLK_GPIO4_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON17_ACLK_DECOM_EN_SHIFT (6U) +#define CRU_GATE_CON17_ACLK_DECOM_EN_MASK (0x1U << CRU_GATE_CON17_ACLK_DECOM_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON17_PCLK_DECOM_EN_SHIFT (7U) +#define CRU_GATE_CON17_PCLK_DECOM_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_DECOM_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON17_DCLK_DECOM_EN_SHIFT (8U) +#define CRU_GATE_CON17_DCLK_DECOM_EN_MASK (0x1U << CRU_GATE_CON17_DCLK_DECOM_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON17_PCLK_TOP_EN_SHIFT (9U) +#define CRU_GATE_CON17_PCLK_TOP_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_TOP_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON17_ACLK_GICADB_GIC2CORE_BUS_EN_SHIFT (11U) +#define CRU_GATE_CON17_ACLK_GICADB_GIC2CORE_BUS_EN_MASK (0x1U << CRU_GATE_CON17_ACLK_GICADB_GIC2CORE_BUS_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON17_PCLK_DFT2APB_EN_SHIFT (12U) +#define CRU_GATE_CON17_PCLK_DFT2APB_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_DFT2APB_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_TOP_EN_SHIFT (13U) +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_TOP_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_APB2ASB_MST_TOP_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_CDPHY_EN_SHIFT (14U) +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_CDPHY_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_APB2ASB_MST_CDPHY_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_BOT_RIGHT_EN_SHIFT (15U) +#define CRU_GATE_CON17_PCLK_APB2ASB_MST_BOT_RIGHT_EN_MASK (0x1U << CRU_GATE_CON17_PCLK_APB2ASB_MST_BOT_RIGHT_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON18 */ +#define CRU_GATE_CON18_OFFSET (0x848U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_TOP_EN_SHIFT (0U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_TOP_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_TOP_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_RIGHT_EN_SHIFT (1U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_RIGHT_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_IOC_RIGHT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_CSIPHY_EN_SHIFT (2U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_CSIPHY_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_CSIPHY_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO3_5_EN_SHIFT (3U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO3_5_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO3_5_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO6_EN_SHIFT (4U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO6_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_VCCIO6_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_EMMCIO_EN_SHIFT (5U) +#define CRU_GATE_CON18_PCLK_APB2ASB_MST_EMMCIO_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_APB2ASB_MST_EMMCIO_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON18_ACLK_SPINLOCK_EN_SHIFT (6U) +#define CRU_GATE_CON18_ACLK_SPINLOCK_EN_MASK (0x1U << CRU_GATE_CON18_ACLK_SPINLOCK_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON18_PCLK_OTPC_NS_EN_SHIFT (9U) +#define CRU_GATE_CON18_PCLK_OTPC_NS_EN_MASK (0x1U << CRU_GATE_CON18_PCLK_OTPC_NS_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON18_CLK_OTPC_NS_EN_SHIFT (10U) +#define CRU_GATE_CON18_CLK_OTPC_NS_EN_MASK (0x1U << CRU_GATE_CON18_CLK_OTPC_NS_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON18_CLK_OTPC_ARB_EN_SHIFT (11U) +#define CRU_GATE_CON18_CLK_OTPC_ARB_EN_MASK (0x1U << CRU_GATE_CON18_CLK_OTPC_ARB_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON18_CLK_OTPC_AUTO_RD_EN_SHIFT (12U) +#define CRU_GATE_CON18_CLK_OTPC_AUTO_RD_EN_MASK (0x1U << CRU_GATE_CON18_CLK_OTPC_AUTO_RD_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON18_CLK_OTP_PHY_EN_SHIFT (13U) +#define CRU_GATE_CON18_CLK_OTP_PHY_EN_MASK (0x1U << CRU_GATE_CON18_CLK_OTP_PHY_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON19 */ +#define CRU_GATE_CON19_OFFSET (0x84CU) +#define CRU_GATE_CON19_PCLK_BUSIOC_EN_SHIFT (0U) +#define CRU_GATE_CON19_PCLK_BUSIOC_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_BUSIOC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON19_CLK_BISRINTF_PLLSRC_EN_SHIFT (1U) +#define CRU_GATE_CON19_CLK_BISRINTF_PLLSRC_EN_MASK (0x1U << CRU_GATE_CON19_CLK_BISRINTF_PLLSRC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON19_CLK_BISRINTF_EN_SHIFT (2U) +#define CRU_GATE_CON19_CLK_BISRINTF_EN_MASK (0x1U << CRU_GATE_CON19_CLK_BISRINTF_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON19_PCLK_PMU2_EN_SHIFT (3U) +#define CRU_GATE_CON19_PCLK_PMU2_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_PMU2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON19_PCLK_PMUCM0_INTMUX_EN_SHIFT (4U) +#define CRU_GATE_CON19_PCLK_PMUCM0_INTMUX_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_PMUCM0_INTMUX_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON19_PCLK_DDRCM0_INTMUX_EN_SHIFT (5U) +#define CRU_GATE_CON19_PCLK_DDRCM0_INTMUX_EN_MASK (0x1U << CRU_GATE_CON19_PCLK_DDRCM0_INTMUX_EN_SHIFT) /* 0x00000020 */ +/* GATE_CON20 */ +#define CRU_GATE_CON20_OFFSET (0x850U) +#define CRU_GATE_CON20_PCLK_DDR_DFICTL_CH0_EN_SHIFT (0U) +#define CRU_GATE_CON20_PCLK_DDR_DFICTL_CH0_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_DFICTL_CH0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON20_PCLK_DDR_MON_CH0_EN_SHIFT (1U) +#define CRU_GATE_CON20_PCLK_DDR_MON_CH0_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_MON_CH0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON20_PCLK_DDR_STANDBY_CH0_EN_SHIFT (2U) +#define CRU_GATE_CON20_PCLK_DDR_STANDBY_CH0_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_STANDBY_CH0_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON20_PCLK_DDR_UPCTL_CH0_EN_SHIFT (3U) +#define CRU_GATE_CON20_PCLK_DDR_UPCTL_CH0_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_UPCTL_CH0_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON20_TMCLK_DDR_MON_CH0_EN_SHIFT (4U) +#define CRU_GATE_CON20_TMCLK_DDR_MON_CH0_EN_MASK (0x1U << CRU_GATE_CON20_TMCLK_DDR_MON_CH0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON20_PCLK_DDR_GRF_CH01_EN_SHIFT (5U) +#define CRU_GATE_CON20_PCLK_DDR_GRF_CH01_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_GRF_CH01_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON20_CLK_DFI_CH0_EN_SHIFT (6U) +#define CRU_GATE_CON20_CLK_DFI_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_DFI_CH0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON20_CLK_SBR_CH0_EN_SHIFT (7U) +#define CRU_GATE_CON20_CLK_SBR_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_SBR_CH0_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON20_CLK_DDR_UPCTL_CH0_EN_SHIFT (8U) +#define CRU_GATE_CON20_CLK_DDR_UPCTL_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_DDR_UPCTL_CH0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON20_CLK_DDR_DFICTL_CH0_EN_SHIFT (9U) +#define CRU_GATE_CON20_CLK_DDR_DFICTL_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_DDR_DFICTL_CH0_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON20_CLK_DDR_MON_CH0_EN_SHIFT (10U) +#define CRU_GATE_CON20_CLK_DDR_MON_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_DDR_MON_CH0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON20_CLK_DDR_STANDBY_CH0_EN_SHIFT (11U) +#define CRU_GATE_CON20_CLK_DDR_STANDBY_CH0_EN_MASK (0x1U << CRU_GATE_CON20_CLK_DDR_STANDBY_CH0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON20_ACLK_DDR_UPCTL_CH0_EN_SHIFT (12U) +#define CRU_GATE_CON20_ACLK_DDR_UPCTL_CH0_EN_MASK (0x1U << CRU_GATE_CON20_ACLK_DDR_UPCTL_CH0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON20_PCLK_DDR_DFICTL_CH1_EN_SHIFT (13U) +#define CRU_GATE_CON20_PCLK_DDR_DFICTL_CH1_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_DFICTL_CH1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON20_PCLK_DDR_MON_CH1_EN_SHIFT (14U) +#define CRU_GATE_CON20_PCLK_DDR_MON_CH1_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_MON_CH1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON20_PCLK_DDR_STANDBY_CH1_EN_SHIFT (15U) +#define CRU_GATE_CON20_PCLK_DDR_STANDBY_CH1_EN_MASK (0x1U << CRU_GATE_CON20_PCLK_DDR_STANDBY_CH1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON21 */ +#define CRU_GATE_CON21_OFFSET (0x854U) +#define CRU_GATE_CON21_PCLK_DDR_UPCTL_CH1_EN_SHIFT (0U) +#define CRU_GATE_CON21_PCLK_DDR_UPCTL_CH1_EN_MASK (0x1U << CRU_GATE_CON21_PCLK_DDR_UPCTL_CH1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON21_TMCLK_DDR_MON_CH1_EN_SHIFT (1U) +#define CRU_GATE_CON21_TMCLK_DDR_MON_CH1_EN_MASK (0x1U << CRU_GATE_CON21_TMCLK_DDR_MON_CH1_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON21_CLK_DFI_CH1_EN_SHIFT (2U) +#define CRU_GATE_CON21_CLK_DFI_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_DFI_CH1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON21_CLK_SBR_CH1_EN_SHIFT (3U) +#define CRU_GATE_CON21_CLK_SBR_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_SBR_CH1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON21_CLK_DDR_UPCTL_CH1_EN_SHIFT (4U) +#define CRU_GATE_CON21_CLK_DDR_UPCTL_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_DDR_UPCTL_CH1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON21_CLK_DDR_DFICTL_CH1_EN_SHIFT (5U) +#define CRU_GATE_CON21_CLK_DDR_DFICTL_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_DDR_DFICTL_CH1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON21_CLK_DDR_MON_CH1_EN_SHIFT (6U) +#define CRU_GATE_CON21_CLK_DDR_MON_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_DDR_MON_CH1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON21_CLK_DDR_STANDBY_CH1_EN_SHIFT (7U) +#define CRU_GATE_CON21_CLK_DDR_STANDBY_CH1_EN_MASK (0x1U << CRU_GATE_CON21_CLK_DDR_STANDBY_CH1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON21_ACLK_DDR_UPCTL_CH1_EN_SHIFT (8U) +#define CRU_GATE_CON21_ACLK_DDR_UPCTL_CH1_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_DDR_UPCTL_CH1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON21_ACLK_DDR_DDRSCH0_EN_SHIFT (13U) +#define CRU_GATE_CON21_ACLK_DDR_DDRSCH0_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_DDR_DDRSCH0_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON21_ACLK_DDR_RS_DDRSCH0_EN_SHIFT (14U) +#define CRU_GATE_CON21_ACLK_DDR_RS_DDRSCH0_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_DDR_RS_DDRSCH0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON21_ACLK_DDR_FRS_DDRSCH0_EN_SHIFT (15U) +#define CRU_GATE_CON21_ACLK_DDR_FRS_DDRSCH0_EN_MASK (0x1U << CRU_GATE_CON21_ACLK_DDR_FRS_DDRSCH0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON22 */ +#define CRU_GATE_CON22_OFFSET (0x858U) +#define CRU_GATE_CON22_ACLK_DDR_SCRAMBLE0_EN_SHIFT (0U) +#define CRU_GATE_CON22_ACLK_DDR_SCRAMBLE0_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_SCRAMBLE0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE0_EN_SHIFT (1U) +#define CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE0_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON22_ACLK_DDR_DDRSCH1_EN_SHIFT (2U) +#define CRU_GATE_CON22_ACLK_DDR_DDRSCH1_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_DDRSCH1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON22_ACLK_DDR_RS_DDRSCH1_EN_SHIFT (3U) +#define CRU_GATE_CON22_ACLK_DDR_RS_DDRSCH1_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_RS_DDRSCH1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON22_ACLK_DDR_FRS_DDRSCH1_EN_SHIFT (4U) +#define CRU_GATE_CON22_ACLK_DDR_FRS_DDRSCH1_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_FRS_DDRSCH1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON22_ACLK_DDR_SCRAMBLE1_EN_SHIFT (5U) +#define CRU_GATE_CON22_ACLK_DDR_SCRAMBLE1_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_SCRAMBLE1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE1_EN_SHIFT (6U) +#define CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE1_EN_MASK (0x1U << CRU_GATE_CON22_ACLK_DDR_FRS_SCRAMBLE1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON22_PCLK_DDR_DDRSCH0_EN_SHIFT (7U) +#define CRU_GATE_CON22_PCLK_DDR_DDRSCH0_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_DDR_DDRSCH0_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON22_PCLK_DDR_DDRSCH1_EN_SHIFT (8U) +#define CRU_GATE_CON22_PCLK_DDR_DDRSCH1_EN_MASK (0x1U << CRU_GATE_CON22_PCLK_DDR_DDRSCH1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON22_CLK_TESTOUT_DDR01_EN_SHIFT (9U) +#define CRU_GATE_CON22_CLK_TESTOUT_DDR01_EN_MASK (0x1U << CRU_GATE_CON22_CLK_TESTOUT_DDR01_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON23 */ +#define CRU_GATE_CON23_OFFSET (0x85CU) +#define CRU_GATE_CON23_PCLK_DDR_DFICTL_CH2_EN_SHIFT (0U) +#define CRU_GATE_CON23_PCLK_DDR_DFICTL_CH2_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_DFICTL_CH2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON23_PCLK_DDR_MON_CH2_EN_SHIFT (1U) +#define CRU_GATE_CON23_PCLK_DDR_MON_CH2_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_MON_CH2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON23_PCLK_DDR_STANDBY_CH2_EN_SHIFT (2U) +#define CRU_GATE_CON23_PCLK_DDR_STANDBY_CH2_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_STANDBY_CH2_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON23_PCLK_DDR_UPCTL_CH2_EN_SHIFT (3U) +#define CRU_GATE_CON23_PCLK_DDR_UPCTL_CH2_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_UPCTL_CH2_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON23_TMCLK_DDR_MON_CH2_EN_SHIFT (4U) +#define CRU_GATE_CON23_TMCLK_DDR_MON_CH2_EN_MASK (0x1U << CRU_GATE_CON23_TMCLK_DDR_MON_CH2_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON23_PCLK_DDR_GRF_CH23_EN_SHIFT (5U) +#define CRU_GATE_CON23_PCLK_DDR_GRF_CH23_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_GRF_CH23_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON23_CLK_DFI_CH2_EN_SHIFT (6U) +#define CRU_GATE_CON23_CLK_DFI_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_DFI_CH2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON23_CLK_SBR_CH2_EN_SHIFT (7U) +#define CRU_GATE_CON23_CLK_SBR_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_SBR_CH2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON23_CLK_DDR_UPCTL_CH2_EN_SHIFT (8U) +#define CRU_GATE_CON23_CLK_DDR_UPCTL_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_DDR_UPCTL_CH2_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON23_CLK_DDR_DFICTL_CH2_EN_SHIFT (9U) +#define CRU_GATE_CON23_CLK_DDR_DFICTL_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_DDR_DFICTL_CH2_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON23_CLK_DDR_MON_CH2_EN_SHIFT (10U) +#define CRU_GATE_CON23_CLK_DDR_MON_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_DDR_MON_CH2_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON23_CLK_DDR_STANDBY_CH2_EN_SHIFT (11U) +#define CRU_GATE_CON23_CLK_DDR_STANDBY_CH2_EN_MASK (0x1U << CRU_GATE_CON23_CLK_DDR_STANDBY_CH2_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON23_ACLK_DDR_UPCTL_CH2_EN_SHIFT (12U) +#define CRU_GATE_CON23_ACLK_DDR_UPCTL_CH2_EN_MASK (0x1U << CRU_GATE_CON23_ACLK_DDR_UPCTL_CH2_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON23_PCLK_DDR_DFICTL_CH3_EN_SHIFT (13U) +#define CRU_GATE_CON23_PCLK_DDR_DFICTL_CH3_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_DFICTL_CH3_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON23_PCLK_DDR_MON_CH3_EN_SHIFT (14U) +#define CRU_GATE_CON23_PCLK_DDR_MON_CH3_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_MON_CH3_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON23_PCLK_DDR_STANDBY_CH3_EN_SHIFT (15U) +#define CRU_GATE_CON23_PCLK_DDR_STANDBY_CH3_EN_MASK (0x1U << CRU_GATE_CON23_PCLK_DDR_STANDBY_CH3_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON24 */ +#define CRU_GATE_CON24_OFFSET (0x860U) +#define CRU_GATE_CON24_PCLK_DDR_UPCTL_CH3_EN_SHIFT (0U) +#define CRU_GATE_CON24_PCLK_DDR_UPCTL_CH3_EN_MASK (0x1U << CRU_GATE_CON24_PCLK_DDR_UPCTL_CH3_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON24_TMCLK_DDR_MON_CH3_EN_SHIFT (1U) +#define CRU_GATE_CON24_TMCLK_DDR_MON_CH3_EN_MASK (0x1U << CRU_GATE_CON24_TMCLK_DDR_MON_CH3_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON24_CLK_DFI_CH3_EN_SHIFT (2U) +#define CRU_GATE_CON24_CLK_DFI_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_DFI_CH3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON24_CLK_SBR_CH3_EN_SHIFT (3U) +#define CRU_GATE_CON24_CLK_SBR_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_SBR_CH3_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON24_CLK_DDR_UPCTL_CH3_EN_SHIFT (4U) +#define CRU_GATE_CON24_CLK_DDR_UPCTL_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_DDR_UPCTL_CH3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON24_CLK_DDR_DFICTL_CH3_EN_SHIFT (5U) +#define CRU_GATE_CON24_CLK_DDR_DFICTL_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_DDR_DFICTL_CH3_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON24_CLK_DDR_MON_CH3_EN_SHIFT (6U) +#define CRU_GATE_CON24_CLK_DDR_MON_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_DDR_MON_CH3_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON24_CLK_DDR_STANDBY_CH3_EN_SHIFT (7U) +#define CRU_GATE_CON24_CLK_DDR_STANDBY_CH3_EN_MASK (0x1U << CRU_GATE_CON24_CLK_DDR_STANDBY_CH3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON24_ACLK_DDR_UPCTL_CH3_EN_SHIFT (8U) +#define CRU_GATE_CON24_ACLK_DDR_UPCTL_CH3_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_DDR_UPCTL_CH3_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON24_ACLK_DDR_DDRSCH2_EN_SHIFT (13U) +#define CRU_GATE_CON24_ACLK_DDR_DDRSCH2_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_DDR_DDRSCH2_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON24_ACLK_DDR_RS_DDRSCH2_EN_SHIFT (14U) +#define CRU_GATE_CON24_ACLK_DDR_RS_DDRSCH2_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_DDR_RS_DDRSCH2_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON24_ACLK_DDR_FRS_DDRSCH2_EN_SHIFT (15U) +#define CRU_GATE_CON24_ACLK_DDR_FRS_DDRSCH2_EN_MASK (0x1U << CRU_GATE_CON24_ACLK_DDR_FRS_DDRSCH2_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON25 */ +#define CRU_GATE_CON25_OFFSET (0x864U) +#define CRU_GATE_CON25_ACLK_DDR_SCRAMBLE2_EN_SHIFT (0U) +#define CRU_GATE_CON25_ACLK_DDR_SCRAMBLE2_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_SCRAMBLE2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE2_EN_SHIFT (1U) +#define CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE2_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON25_ACLK_DDR_DDRSCH3_EN_SHIFT (2U) +#define CRU_GATE_CON25_ACLK_DDR_DDRSCH3_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_DDRSCH3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON25_ACLK_DDR_RS_DDRSCH3_EN_SHIFT (3U) +#define CRU_GATE_CON25_ACLK_DDR_RS_DDRSCH3_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_RS_DDRSCH3_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON25_ACLK_DDR_FRS_DDRSCH3_EN_SHIFT (4U) +#define CRU_GATE_CON25_ACLK_DDR_FRS_DDRSCH3_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_FRS_DDRSCH3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON25_ACLK_DDR_SCRAMBLE3_EN_SHIFT (5U) +#define CRU_GATE_CON25_ACLK_DDR_SCRAMBLE3_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_SCRAMBLE3_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE3_EN_SHIFT (6U) +#define CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE3_EN_MASK (0x1U << CRU_GATE_CON25_ACLK_DDR_FRS_SCRAMBLE3_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON25_PCLK_DDR_DDRSCH2_EN_SHIFT (7U) +#define CRU_GATE_CON25_PCLK_DDR_DDRSCH2_EN_MASK (0x1U << CRU_GATE_CON25_PCLK_DDR_DDRSCH2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON25_PCLK_DDR_DDRSCH3_EN_SHIFT (8U) +#define CRU_GATE_CON25_PCLK_DDR_DDRSCH3_EN_MASK (0x1U << CRU_GATE_CON25_PCLK_DDR_DDRSCH3_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON25_CLK_TESTOUT_DDR23_EN_SHIFT (9U) +#define CRU_GATE_CON25_CLK_TESTOUT_DDR23_EN_MASK (0x1U << CRU_GATE_CON25_CLK_TESTOUT_DDR23_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON26 */ +#define CRU_GATE_CON26_OFFSET (0x868U) +#define CRU_GATE_CON26_ACLK_ISP1_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON26_ACLK_ISP1_ROOT_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_ISP1_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON26_HCLK_ISP1_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON26_HCLK_ISP1_ROOT_EN_MASK (0x1U << CRU_GATE_CON26_HCLK_ISP1_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON26_CLK_ISP1_CORE_EN_SHIFT (2U) +#define CRU_GATE_CON26_CLK_ISP1_CORE_EN_MASK (0x1U << CRU_GATE_CON26_CLK_ISP1_CORE_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON26_CLK_ISP1_CORE_MARVIN_EN_SHIFT (3U) +#define CRU_GATE_CON26_CLK_ISP1_CORE_MARVIN_EN_MASK (0x1U << CRU_GATE_CON26_CLK_ISP1_CORE_MARVIN_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON26_CLK_ISP1_CORE_VICAP_EN_SHIFT (4U) +#define CRU_GATE_CON26_CLK_ISP1_CORE_VICAP_EN_MASK (0x1U << CRU_GATE_CON26_CLK_ISP1_CORE_VICAP_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON26_ACLK_ISP1_EN_SHIFT (5U) +#define CRU_GATE_CON26_ACLK_ISP1_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_ISP1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON26_ACLK_ISP1_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON26_ACLK_ISP1_BIU_EN_MASK (0x1U << CRU_GATE_CON26_ACLK_ISP1_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON26_HCLK_ISP1_EN_SHIFT (7U) +#define CRU_GATE_CON26_HCLK_ISP1_EN_MASK (0x1U << CRU_GATE_CON26_HCLK_ISP1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON26_HCLK_ISP1_BIU_EN_SHIFT (8U) +#define CRU_GATE_CON26_HCLK_ISP1_BIU_EN_MASK (0x1U << CRU_GATE_CON26_HCLK_ISP1_BIU_EN_SHIFT) /* 0x00000100 */ +/* GATE_CON27 */ +#define CRU_GATE_CON27_OFFSET (0x86CU) +#define CRU_GATE_CON27_ACLK_RKNN1_EN_SHIFT (0U) +#define CRU_GATE_CON27_ACLK_RKNN1_EN_MASK (0x1U << CRU_GATE_CON27_ACLK_RKNN1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON27_ACLK_RKNN1_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON27_ACLK_RKNN1_BIU_EN_MASK (0x1U << CRU_GATE_CON27_ACLK_RKNN1_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON27_HCLK_RKNN1_EN_SHIFT (2U) +#define CRU_GATE_CON27_HCLK_RKNN1_EN_MASK (0x1U << CRU_GATE_CON27_HCLK_RKNN1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON27_HCLK_RKNN1_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON27_HCLK_RKNN1_BIU_EN_MASK (0x1U << CRU_GATE_CON27_HCLK_RKNN1_BIU_EN_SHIFT) /* 0x00000008 */ +/* GATE_CON28 */ +#define CRU_GATE_CON28_OFFSET (0x870U) +#define CRU_GATE_CON28_ACLK_RKNN2_EN_SHIFT (0U) +#define CRU_GATE_CON28_ACLK_RKNN2_EN_MASK (0x1U << CRU_GATE_CON28_ACLK_RKNN2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON28_ACLK_RKNN2_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON28_ACLK_RKNN2_BIU_EN_MASK (0x1U << CRU_GATE_CON28_ACLK_RKNN2_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON28_HCLK_RKNN2_EN_SHIFT (2U) +#define CRU_GATE_CON28_HCLK_RKNN2_EN_MASK (0x1U << CRU_GATE_CON28_HCLK_RKNN2_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON28_HCLK_RKNN2_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON28_HCLK_RKNN2_BIU_EN_MASK (0x1U << CRU_GATE_CON28_HCLK_RKNN2_BIU_EN_SHIFT) /* 0x00000008 */ +/* GATE_CON29 */ +#define CRU_GATE_CON29_OFFSET (0x874U) +#define CRU_GATE_CON29_HCLK_RKNN_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON29_HCLK_RKNN_ROOT_EN_MASK (0x1U << CRU_GATE_CON29_HCLK_RKNN_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON29_CLK_RKNN_DSU0_DF_EN_SHIFT (1U) +#define CRU_GATE_CON29_CLK_RKNN_DSU0_DF_EN_MASK (0x1U << CRU_GATE_CON29_CLK_RKNN_DSU0_DF_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON29_CLK_TESTOUT_NPU_EN_SHIFT (2U) +#define CRU_GATE_CON29_CLK_TESTOUT_NPU_EN_MASK (0x1U << CRU_GATE_CON29_CLK_TESTOUT_NPU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON29_CLK_RKNN_DSU0_EN_SHIFT (3U) +#define CRU_GATE_CON29_CLK_RKNN_DSU0_EN_MASK (0x1U << CRU_GATE_CON29_CLK_RKNN_DSU0_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON29_PCLK_NPUTOP_ROOT_EN_SHIFT (4U) +#define CRU_GATE_CON29_PCLK_NPUTOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_NPUTOP_ROOT_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON29_PCLK_NPUTOP_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON29_PCLK_NPUTOP_BIU_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_NPUTOP_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON29_PCLK_NPU_TIMER_EN_SHIFT (6U) +#define CRU_GATE_CON29_PCLK_NPU_TIMER_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_NPU_TIMER_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON29_CLK_NPUTIMER_ROOT_EN_SHIFT (7U) +#define CRU_GATE_CON29_CLK_NPUTIMER_ROOT_EN_MASK (0x1U << CRU_GATE_CON29_CLK_NPUTIMER_ROOT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON29_CLK_NPUTIMER0_EN_SHIFT (8U) +#define CRU_GATE_CON29_CLK_NPUTIMER0_EN_MASK (0x1U << CRU_GATE_CON29_CLK_NPUTIMER0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON29_CLK_NPUTIMER1_EN_SHIFT (9U) +#define CRU_GATE_CON29_CLK_NPUTIMER1_EN_MASK (0x1U << CRU_GATE_CON29_CLK_NPUTIMER1_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON29_PCLK_NPU_WDT_EN_SHIFT (10U) +#define CRU_GATE_CON29_PCLK_NPU_WDT_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_NPU_WDT_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON29_TCLK_NPU_WDT_EN_SHIFT (11U) +#define CRU_GATE_CON29_TCLK_NPU_WDT_EN_MASK (0x1U << CRU_GATE_CON29_TCLK_NPU_WDT_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON29_PCLK_PVTM1_EN_SHIFT (12U) +#define CRU_GATE_CON29_PCLK_PVTM1_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_PVTM1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON29_PCLK_NPU_GRF_EN_SHIFT (13U) +#define CRU_GATE_CON29_PCLK_NPU_GRF_EN_MASK (0x1U << CRU_GATE_CON29_PCLK_NPU_GRF_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON29_CLK_PVTM1_EN_SHIFT (14U) +#define CRU_GATE_CON29_CLK_PVTM1_EN_MASK (0x1U << CRU_GATE_CON29_CLK_PVTM1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON29_CLK_NPU_PVTM_EN_SHIFT (15U) +#define CRU_GATE_CON29_CLK_NPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON29_CLK_NPU_PVTM_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON30 */ +#define CRU_GATE_CON30_OFFSET (0x878U) +#define CRU_GATE_CON30_CLK_NPU_PVTPLL_EN_SHIFT (0U) +#define CRU_GATE_CON30_CLK_NPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON30_CLK_NPU_PVTPLL_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON30_HCLK_NPU_CM0_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON30_HCLK_NPU_CM0_ROOT_EN_MASK (0x1U << CRU_GATE_CON30_HCLK_NPU_CM0_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON30_HCLK_NPU_CM0_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON30_HCLK_NPU_CM0_BIU_EN_MASK (0x1U << CRU_GATE_CON30_HCLK_NPU_CM0_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON30_FCLK_NPU_CM0_CORE_EN_SHIFT (3U) +#define CRU_GATE_CON30_FCLK_NPU_CM0_CORE_EN_MASK (0x1U << CRU_GATE_CON30_FCLK_NPU_CM0_CORE_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON30_CLK_NPU_CM0_RTC_EN_SHIFT (5U) +#define CRU_GATE_CON30_CLK_NPU_CM0_RTC_EN_MASK (0x1U << CRU_GATE_CON30_CLK_NPU_CM0_RTC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON30_ACLK_RKNN0_EN_SHIFT (6U) +#define CRU_GATE_CON30_ACLK_RKNN0_EN_MASK (0x1U << CRU_GATE_CON30_ACLK_RKNN0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON30_ACLK_RKNN0_BIU_EN_SHIFT (7U) +#define CRU_GATE_CON30_ACLK_RKNN0_BIU_EN_MASK (0x1U << CRU_GATE_CON30_ACLK_RKNN0_BIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON30_HCLK_RKNN0_EN_SHIFT (8U) +#define CRU_GATE_CON30_HCLK_RKNN0_EN_MASK (0x1U << CRU_GATE_CON30_HCLK_RKNN0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON30_HCLK_RKNN0_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON30_HCLK_RKNN0_BIU_EN_MASK (0x1U << CRU_GATE_CON30_HCLK_RKNN0_BIU_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON31 */ +#define CRU_GATE_CON31_OFFSET (0x87CU) +#define CRU_GATE_CON31_HCLK_NVM_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON31_HCLK_NVM_ROOT_EN_MASK (0x1U << CRU_GATE_CON31_HCLK_NVM_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON31_ACLK_NVM_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON31_ACLK_NVM_ROOT_EN_MASK (0x1U << CRU_GATE_CON31_ACLK_NVM_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON31_HCLK_NVM_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON31_HCLK_NVM_BIU_EN_MASK (0x1U << CRU_GATE_CON31_HCLK_NVM_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON31_ACLK_NVM_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON31_ACLK_NVM_BIU_EN_MASK (0x1U << CRU_GATE_CON31_ACLK_NVM_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON31_HCLK_EMMC_EN_SHIFT (4U) +#define CRU_GATE_CON31_HCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON31_HCLK_EMMC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON31_ACLK_EMMC_EN_SHIFT (5U) +#define CRU_GATE_CON31_ACLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON31_ACLK_EMMC_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON31_CCLK_EMMC_EN_SHIFT (6U) +#define CRU_GATE_CON31_CCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON31_CCLK_EMMC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON31_BCLK_EMMC_EN_SHIFT (7U) +#define CRU_GATE_CON31_BCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON31_BCLK_EMMC_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON31_TMCLK_EMMC_EN_SHIFT (8U) +#define CRU_GATE_CON31_TMCLK_EMMC_EN_MASK (0x1U << CRU_GATE_CON31_TMCLK_EMMC_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON31_SCLK_SFC_EN_SHIFT (9U) +#define CRU_GATE_CON31_SCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON31_SCLK_SFC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON31_HCLK_SFC_EN_SHIFT (10U) +#define CRU_GATE_CON31_HCLK_SFC_EN_MASK (0x1U << CRU_GATE_CON31_HCLK_SFC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON31_HCLK_SFC_XIP_EN_SHIFT (11U) +#define CRU_GATE_CON31_HCLK_SFC_XIP_EN_MASK (0x1U << CRU_GATE_CON31_HCLK_SFC_XIP_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON32 */ +#define CRU_GATE_CON32_OFFSET (0x880U) +#define CRU_GATE_CON32_PCLK_PHP_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON32_PCLK_PHP_ROOT_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_PHP_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON32_PCLK_GRF_EN_SHIFT (1U) +#define CRU_GATE_CON32_PCLK_GRF_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_GRF_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON32_PCLK_DEC_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON32_PCLK_DEC_BIU_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_DEC_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON32_PCLK_GMAC0_EN_SHIFT (3U) +#define CRU_GATE_CON32_PCLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_GMAC0_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON32_PCLK_GMAC1_EN_SHIFT (4U) +#define CRU_GATE_CON32_PCLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_GMAC1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON32_PCLK_PHP_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON32_PCLK_PHP_BIU_EN_MASK (0x1U << CRU_GATE_CON32_PCLK_PHP_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON32_ACLK_PCIE_ROOT_EN_SHIFT (6U) +#define CRU_GATE_CON32_ACLK_PCIE_ROOT_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_ROOT_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON32_ACLK_PHP_ROOT_EN_SHIFT (7U) +#define CRU_GATE_CON32_ACLK_PHP_ROOT_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PHP_ROOT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON32_ACLK_PCIE_BRIDGE_EN_SHIFT (8U) +#define CRU_GATE_CON32_ACLK_PCIE_BRIDGE_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_BRIDGE_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON32_ACLK_PHP_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON32_ACLK_PHP_BIU_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PHP_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON32_ACLK_GMAC0_EN_SHIFT (10U) +#define CRU_GATE_CON32_ACLK_GMAC0_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_GMAC0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON32_ACLK_GMAC1_EN_SHIFT (11U) +#define CRU_GATE_CON32_ACLK_GMAC1_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_GMAC1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON32_ACLK_PCIE_BIU_EN_SHIFT (12U) +#define CRU_GATE_CON32_ACLK_PCIE_BIU_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_BIU_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON32_ACLK_PCIE_4L_DBI_EN_SHIFT (13U) +#define CRU_GATE_CON32_ACLK_PCIE_4L_DBI_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_4L_DBI_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON32_ACLK_PCIE_2L_DBI_EN_SHIFT (14U) +#define CRU_GATE_CON32_ACLK_PCIE_2L_DBI_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_2L_DBI_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON32_ACLK_PCIE_1L0_DBI_EN_SHIFT (15U) +#define CRU_GATE_CON32_ACLK_PCIE_1L0_DBI_EN_MASK (0x1U << CRU_GATE_CON32_ACLK_PCIE_1L0_DBI_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON33 */ +#define CRU_GATE_CON33_OFFSET (0x884U) +#define CRU_GATE_CON33_ACLK_PCIE_1L1_DBI_EN_SHIFT (0U) +#define CRU_GATE_CON33_ACLK_PCIE_1L1_DBI_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L1_DBI_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L2_DBI_EN_SHIFT (1U) +#define CRU_GATE_CON33_ACLK_PCIE_1L2_DBI_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L2_DBI_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON33_ACLK_PCIE_4L_MSTR_EN_SHIFT (2U) +#define CRU_GATE_CON33_ACLK_PCIE_4L_MSTR_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_4L_MSTR_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON33_ACLK_PCIE_2L_MSTR_EN_SHIFT (3U) +#define CRU_GATE_CON33_ACLK_PCIE_2L_MSTR_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_2L_MSTR_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L0_MSTR_EN_SHIFT (4U) +#define CRU_GATE_CON33_ACLK_PCIE_1L0_MSTR_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L0_MSTR_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L1_MSTR_EN_SHIFT (5U) +#define CRU_GATE_CON33_ACLK_PCIE_1L1_MSTR_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L1_MSTR_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L2_MSTR_EN_SHIFT (6U) +#define CRU_GATE_CON33_ACLK_PCIE_1L2_MSTR_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L2_MSTR_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON33_ACLK_PCIE_4L_SLV_EN_SHIFT (7U) +#define CRU_GATE_CON33_ACLK_PCIE_4L_SLV_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_4L_SLV_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON33_ACLK_PCIE_2L_SLV_EN_SHIFT (8U) +#define CRU_GATE_CON33_ACLK_PCIE_2L_SLV_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_2L_SLV_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L0_SLV_EN_SHIFT (9U) +#define CRU_GATE_CON33_ACLK_PCIE_1L0_SLV_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L0_SLV_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L1_SLV_EN_SHIFT (10U) +#define CRU_GATE_CON33_ACLK_PCIE_1L1_SLV_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L1_SLV_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON33_ACLK_PCIE_1L2_SLV_EN_SHIFT (11U) +#define CRU_GATE_CON33_ACLK_PCIE_1L2_SLV_EN_MASK (0x1U << CRU_GATE_CON33_ACLK_PCIE_1L2_SLV_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON33_PCLK_PCIE_4L_EN_SHIFT (12U) +#define CRU_GATE_CON33_PCLK_PCIE_4L_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE_4L_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON33_PCLK_PCIE_2L_EN_SHIFT (13U) +#define CRU_GATE_CON33_PCLK_PCIE_2L_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE_2L_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON33_PCLK_PCIE_1L0_EN_SHIFT (14U) +#define CRU_GATE_CON33_PCLK_PCIE_1L0_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE_1L0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON33_PCLK_PCIE_1L1_EN_SHIFT (15U) +#define CRU_GATE_CON33_PCLK_PCIE_1L1_EN_MASK (0x1U << CRU_GATE_CON33_PCLK_PCIE_1L1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON34 */ +#define CRU_GATE_CON34_OFFSET (0x888U) +#define CRU_GATE_CON34_PCLK_PCIE_1L2_EN_SHIFT (0U) +#define CRU_GATE_CON34_PCLK_PCIE_1L2_EN_MASK (0x1U << CRU_GATE_CON34_PCLK_PCIE_1L2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON34_CLK_PCIE_4L_AUX_EN_SHIFT (1U) +#define CRU_GATE_CON34_CLK_PCIE_4L_AUX_EN_MASK (0x1U << CRU_GATE_CON34_CLK_PCIE_4L_AUX_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON34_CLK_PCIE_2L_AUX_EN_SHIFT (2U) +#define CRU_GATE_CON34_CLK_PCIE_2L_AUX_EN_MASK (0x1U << CRU_GATE_CON34_CLK_PCIE_2L_AUX_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON34_CLK_PCIE_1L0_AUX_EN_SHIFT (3U) +#define CRU_GATE_CON34_CLK_PCIE_1L0_AUX_EN_MASK (0x1U << CRU_GATE_CON34_CLK_PCIE_1L0_AUX_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON34_CLK_PCIE_1L1_AUX_EN_SHIFT (4U) +#define CRU_GATE_CON34_CLK_PCIE_1L1_AUX_EN_MASK (0x1U << CRU_GATE_CON34_CLK_PCIE_1L1_AUX_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON34_CLK_PCIE_1L2_AUX_EN_SHIFT (5U) +#define CRU_GATE_CON34_CLK_PCIE_1L2_AUX_EN_MASK (0x1U << CRU_GATE_CON34_CLK_PCIE_1L2_AUX_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON34_ACLK_PHP_GIC_ITS_EN_SHIFT (6U) +#define CRU_GATE_CON34_ACLK_PHP_GIC_ITS_EN_MASK (0x1U << CRU_GATE_CON34_ACLK_PHP_GIC_ITS_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON34_ACLK_MMU_PCIE_EN_SHIFT (7U) +#define CRU_GATE_CON34_ACLK_MMU_PCIE_EN_MASK (0x1U << CRU_GATE_CON34_ACLK_MMU_PCIE_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON34_ACLK_MMU_PHP_EN_SHIFT (8U) +#define CRU_GATE_CON34_ACLK_MMU_PHP_EN_MASK (0x1U << CRU_GATE_CON34_ACLK_MMU_PHP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON34_ACLK_MMU_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON34_ACLK_MMU_BIU_EN_MASK (0x1U << CRU_GATE_CON34_ACLK_MMU_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON34_CLK_GMAC0_PTP_REF_EN_SHIFT (10U) +#define CRU_GATE_CON34_CLK_GMAC0_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON34_CLK_GMAC0_PTP_REF_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON34_CLK_GMAC1_PTP_REF_EN_SHIFT (11U) +#define CRU_GATE_CON34_CLK_GMAC1_PTP_REF_EN_MASK (0x1U << CRU_GATE_CON34_CLK_GMAC1_PTP_REF_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON35 */ +#define CRU_GATE_CON35_OFFSET (0x88CU) +#define CRU_GATE_CON35_CLK_GMAC_125M_CRU_EN_SHIFT (5U) +#define CRU_GATE_CON35_CLK_GMAC_125M_CRU_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GMAC_125M_CRU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON35_CLK_GMAC_50M_CRU_EN_SHIFT (6U) +#define CRU_GATE_CON35_CLK_GMAC_50M_CRU_EN_MASK (0x1U << CRU_GATE_CON35_CLK_GMAC_50M_CRU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON35_ACLK_USB3OTG2_EN_SHIFT (7U) +#define CRU_GATE_CON35_ACLK_USB3OTG2_EN_MASK (0x1U << CRU_GATE_CON35_ACLK_USB3OTG2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON35_SUSPEND_CLK_USB3OTG2_EN_SHIFT (8U) +#define CRU_GATE_CON35_SUSPEND_CLK_USB3OTG2_EN_MASK (0x1U << CRU_GATE_CON35_SUSPEND_CLK_USB3OTG2_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON35_REF_CLK_USB3OTG2_EN_SHIFT (9U) +#define CRU_GATE_CON35_REF_CLK_USB3OTG2_EN_MASK (0x1U << CRU_GATE_CON35_REF_CLK_USB3OTG2_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON35_CLK_UTMI_OTG2_EN_SHIFT (10U) +#define CRU_GATE_CON35_CLK_UTMI_OTG2_EN_MASK (0x1U << CRU_GATE_CON35_CLK_UTMI_OTG2_EN_SHIFT) /* 0x00000400 */ +/* GATE_CON37 */ +#define CRU_GATE_CON37_OFFSET (0x894U) +#define CRU_GATE_CON37_CLK_PIPEPHY0_REF_EN_SHIFT (0U) +#define CRU_GATE_CON37_CLK_PIPEPHY0_REF_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PIPEPHY0_REF_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON37_CLK_PIPEPHY1_REF_EN_SHIFT (1U) +#define CRU_GATE_CON37_CLK_PIPEPHY1_REF_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PIPEPHY1_REF_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON37_CLK_PIPEPHY2_REF_EN_SHIFT (2U) +#define CRU_GATE_CON37_CLK_PIPEPHY2_REF_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PIPEPHY2_REF_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON37_CLK_PMALIVE0_EN_SHIFT (4U) +#define CRU_GATE_CON37_CLK_PMALIVE0_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PMALIVE0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON37_CLK_PMALIVE1_EN_SHIFT (5U) +#define CRU_GATE_CON37_CLK_PMALIVE1_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PMALIVE1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON37_CLK_PMALIVE2_EN_SHIFT (6U) +#define CRU_GATE_CON37_CLK_PMALIVE2_EN_MASK (0x1U << CRU_GATE_CON37_CLK_PMALIVE2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON37_ACLK_SATA0_EN_SHIFT (7U) +#define CRU_GATE_CON37_ACLK_SATA0_EN_MASK (0x1U << CRU_GATE_CON37_ACLK_SATA0_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON37_ACLK_SATA1_EN_SHIFT (8U) +#define CRU_GATE_CON37_ACLK_SATA1_EN_MASK (0x1U << CRU_GATE_CON37_ACLK_SATA1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON37_ACLK_SATA2_EN_SHIFT (9U) +#define CRU_GATE_CON37_ACLK_SATA2_EN_MASK (0x1U << CRU_GATE_CON37_ACLK_SATA2_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON37_CLK_RXOOB0_EN_SHIFT (10U) +#define CRU_GATE_CON37_CLK_RXOOB0_EN_MASK (0x1U << CRU_GATE_CON37_CLK_RXOOB0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON37_CLK_RXOOB1_EN_SHIFT (11U) +#define CRU_GATE_CON37_CLK_RXOOB1_EN_MASK (0x1U << CRU_GATE_CON37_CLK_RXOOB1_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON37_CLK_RXOOB2_EN_SHIFT (12U) +#define CRU_GATE_CON37_CLK_RXOOB2_EN_MASK (0x1U << CRU_GATE_CON37_CLK_RXOOB2_EN_SHIFT) /* 0x00001000 */ +/* GATE_CON38 */ +#define CRU_GATE_CON38_OFFSET (0x898U) +#define CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_G_EN_SHIFT (3U) +#define CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_G_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_G_EN_SHIFT (4U) +#define CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_G_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_G_EN_SHIFT (5U) +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_G_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_ASIC_G_EN_SHIFT (6U) +#define CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_ASIC_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY0_PIPE_ASIC_G_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_ASIC_G_EN_SHIFT (7U) +#define CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_ASIC_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY1_PIPE_ASIC_G_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_ASIC_G_EN_SHIFT (8U) +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_ASIC_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_ASIC_G_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_U3_G_EN_SHIFT (9U) +#define CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_U3_G_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PIPEPHY2_PIPE_U3_G_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON38_CLK_PCIE_1L2_PIPE_EN_SHIFT (13U) +#define CRU_GATE_CON38_CLK_PCIE_1L2_PIPE_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PCIE_1L2_PIPE_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON38_CLK_PCIE_1L0_PIPE_EN_SHIFT (14U) +#define CRU_GATE_CON38_CLK_PCIE_1L0_PIPE_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PCIE_1L0_PIPE_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON38_CLK_PCIE_1L1_PIPE_EN_SHIFT (15U) +#define CRU_GATE_CON38_CLK_PCIE_1L1_PIPE_EN_MASK (0x1U << CRU_GATE_CON38_CLK_PCIE_1L1_PIPE_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON39 */ +#define CRU_GATE_CON39_OFFSET (0x89CU) +#define CRU_GATE_CON39_CLK_PCIE_4L_PIPE_EN_SHIFT (0U) +#define CRU_GATE_CON39_CLK_PCIE_4L_PIPE_EN_MASK (0x1U << CRU_GATE_CON39_CLK_PCIE_4L_PIPE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON39_CLK_PCIE_2L_PIPE_EN_SHIFT (1U) +#define CRU_GATE_CON39_CLK_PCIE_2L_PIPE_EN_MASK (0x1U << CRU_GATE_CON39_CLK_PCIE_2L_PIPE_EN_SHIFT) /* 0x00000002 */ +/* GATE_CON40 */ +#define CRU_GATE_CON40_OFFSET (0x8A0U) +#define CRU_GATE_CON40_HCLK_RKVDEC0_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON40_HCLK_RKVDEC0_ROOT_EN_MASK (0x1U << CRU_GATE_CON40_HCLK_RKVDEC0_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON40_ACLK_RKVDEC0_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON40_ACLK_RKVDEC0_ROOT_EN_MASK (0x1U << CRU_GATE_CON40_ACLK_RKVDEC0_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON40_ACLK_RKVDEC_CCU_EN_SHIFT (2U) +#define CRU_GATE_CON40_ACLK_RKVDEC_CCU_EN_MASK (0x1U << CRU_GATE_CON40_ACLK_RKVDEC_CCU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON40_HCLK_RKVDEC0_EN_SHIFT (3U) +#define CRU_GATE_CON40_HCLK_RKVDEC0_EN_MASK (0x1U << CRU_GATE_CON40_HCLK_RKVDEC0_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON40_ACLK_RKVDEC0_EN_SHIFT (4U) +#define CRU_GATE_CON40_ACLK_RKVDEC0_EN_MASK (0x1U << CRU_GATE_CON40_ACLK_RKVDEC0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON40_HCLK_RKVDEC0_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON40_HCLK_RKVDEC0_BIU_EN_MASK (0x1U << CRU_GATE_CON40_HCLK_RKVDEC0_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON40_ACLK_RKVDEC0_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON40_ACLK_RKVDEC0_BIU_EN_MASK (0x1U << CRU_GATE_CON40_ACLK_RKVDEC0_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON40_CLK_RKVDEC0_CA_EN_SHIFT (7U) +#define CRU_GATE_CON40_CLK_RKVDEC0_CA_EN_MASK (0x1U << CRU_GATE_CON40_CLK_RKVDEC0_CA_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON40_CLK_RKVDEC0_HEVC_CA_EN_SHIFT (8U) +#define CRU_GATE_CON40_CLK_RKVDEC0_HEVC_CA_EN_MASK (0x1U << CRU_GATE_CON40_CLK_RKVDEC0_HEVC_CA_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON40_CLK_RKVDEC0_CORE_EN_SHIFT (9U) +#define CRU_GATE_CON40_CLK_RKVDEC0_CORE_EN_MASK (0x1U << CRU_GATE_CON40_CLK_RKVDEC0_CORE_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON41 */ +#define CRU_GATE_CON41_OFFSET (0x8A4U) +#define CRU_GATE_CON41_HCLK_RKVDEC1_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON41_HCLK_RKVDEC1_ROOT_EN_MASK (0x1U << CRU_GATE_CON41_HCLK_RKVDEC1_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON41_ACLK_RKVDEC1_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON41_ACLK_RKVDEC1_ROOT_EN_MASK (0x1U << CRU_GATE_CON41_ACLK_RKVDEC1_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON41_HCLK_RKVDEC1_EN_SHIFT (2U) +#define CRU_GATE_CON41_HCLK_RKVDEC1_EN_MASK (0x1U << CRU_GATE_CON41_HCLK_RKVDEC1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON41_ACLK_RKVDEC1_EN_SHIFT (3U) +#define CRU_GATE_CON41_ACLK_RKVDEC1_EN_MASK (0x1U << CRU_GATE_CON41_ACLK_RKVDEC1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON41_HCLK_RKVDEC1_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON41_HCLK_RKVDEC1_BIU_EN_MASK (0x1U << CRU_GATE_CON41_HCLK_RKVDEC1_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON41_ACLK_RKVDEC1_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON41_ACLK_RKVDEC1_BIU_EN_MASK (0x1U << CRU_GATE_CON41_ACLK_RKVDEC1_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON41_CLK_RKVDEC1_CA_EN_SHIFT (6U) +#define CRU_GATE_CON41_CLK_RKVDEC1_CA_EN_MASK (0x1U << CRU_GATE_CON41_CLK_RKVDEC1_CA_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON41_CLK_RKVDEC1_HEVC_CA_EN_SHIFT (7U) +#define CRU_GATE_CON41_CLK_RKVDEC1_HEVC_CA_EN_MASK (0x1U << CRU_GATE_CON41_CLK_RKVDEC1_HEVC_CA_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON41_CLK_RKVDEC1_CORE_EN_SHIFT (8U) +#define CRU_GATE_CON41_CLK_RKVDEC1_CORE_EN_MASK (0x1U << CRU_GATE_CON41_CLK_RKVDEC1_CORE_EN_SHIFT) /* 0x00000100 */ +/* GATE_CON42 */ +#define CRU_GATE_CON42_OFFSET (0x8A8U) +#define CRU_GATE_CON42_ACLK_USB_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON42_ACLK_USB_ROOT_EN_MASK (0x1U << CRU_GATE_CON42_ACLK_USB_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON42_HCLK_USB_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON42_HCLK_USB_ROOT_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_USB_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON42_ACLK_USB_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON42_ACLK_USB_BIU_EN_MASK (0x1U << CRU_GATE_CON42_ACLK_USB_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON42_HCLK_USB_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON42_HCLK_USB_BIU_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_USB_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON42_ACLK_USB3OTG0_EN_SHIFT (4U) +#define CRU_GATE_CON42_ACLK_USB3OTG0_EN_MASK (0x1U << CRU_GATE_CON42_ACLK_USB3OTG0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON42_SUSPEND_CLK_USB3OTG0_EN_SHIFT (5U) +#define CRU_GATE_CON42_SUSPEND_CLK_USB3OTG0_EN_MASK (0x1U << CRU_GATE_CON42_SUSPEND_CLK_USB3OTG0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON42_REF_CLK_USB3OTG0_EN_SHIFT (6U) +#define CRU_GATE_CON42_REF_CLK_USB3OTG0_EN_MASK (0x1U << CRU_GATE_CON42_REF_CLK_USB3OTG0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON42_ACLK_USB3OTG1_EN_SHIFT (7U) +#define CRU_GATE_CON42_ACLK_USB3OTG1_EN_MASK (0x1U << CRU_GATE_CON42_ACLK_USB3OTG1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON42_SUSPEND_CLK_USB3OTG1_EN_SHIFT (8U) +#define CRU_GATE_CON42_SUSPEND_CLK_USB3OTG1_EN_MASK (0x1U << CRU_GATE_CON42_SUSPEND_CLK_USB3OTG1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON42_REF_CLK_USB3OTG1_EN_SHIFT (9U) +#define CRU_GATE_CON42_REF_CLK_USB3OTG1_EN_MASK (0x1U << CRU_GATE_CON42_REF_CLK_USB3OTG1_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON42_HCLK_HOST0_EN_SHIFT (10U) +#define CRU_GATE_CON42_HCLK_HOST0_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_HOST0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON42_HCLK_HOST_ARB0_EN_SHIFT (11U) +#define CRU_GATE_CON42_HCLK_HOST_ARB0_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_HOST_ARB0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON42_HCLK_HOST1_EN_SHIFT (12U) +#define CRU_GATE_CON42_HCLK_HOST1_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_HOST1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON42_HCLK_HOST_ARB1_EN_SHIFT (13U) +#define CRU_GATE_CON42_HCLK_HOST_ARB1_EN_MASK (0x1U << CRU_GATE_CON42_HCLK_HOST_ARB1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON42_ACLK_USB_GRF_EN_SHIFT (14U) +#define CRU_GATE_CON42_ACLK_USB_GRF_EN_MASK (0x1U << CRU_GATE_CON42_ACLK_USB_GRF_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON42_UTMI_OHCI_CLK48_HOST0_EN_SHIFT (15U) +#define CRU_GATE_CON42_UTMI_OHCI_CLK48_HOST0_EN_MASK (0x1U << CRU_GATE_CON42_UTMI_OHCI_CLK48_HOST0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON43 */ +#define CRU_GATE_CON43_OFFSET (0x8ACU) +#define CRU_GATE_CON43_UTMI_OHCI_CLK48_HOST1_EN_SHIFT (0U) +#define CRU_GATE_CON43_UTMI_OHCI_CLK48_HOST1_EN_MASK (0x1U << CRU_GATE_CON43_UTMI_OHCI_CLK48_HOST1_EN_SHIFT) /* 0x00000001 */ +/* GATE_CON44 */ +#define CRU_GATE_CON44_OFFSET (0x8B0U) +#define CRU_GATE_CON44_ACLK_VDPU_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON44_ACLK_VDPU_ROOT_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_VDPU_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON44_ACLK_VDPU_LOW_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON44_ACLK_VDPU_LOW_ROOT_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_VDPU_LOW_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON44_HCLK_VDPU_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON44_HCLK_VDPU_ROOT_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_VDPU_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON44_ACLK_JPEG_DECODER_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON44_ACLK_JPEG_DECODER_ROOT_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_JPEG_DECODER_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON44_ACLK_VDPU_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON44_ACLK_VDPU_BIU_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_VDPU_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON44_ACLK_VDPU_LOW_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON44_ACLK_VDPU_LOW_BIU_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_VDPU_LOW_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON44_HCLK_VDPU_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON44_HCLK_VDPU_BIU_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_VDPU_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON44_ACLK_JPEG_DECODER_BIU_EN_SHIFT (7U) +#define CRU_GATE_CON44_ACLK_JPEG_DECODER_BIU_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_JPEG_DECODER_BIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON44_ACLK_VPU_EN_SHIFT (8U) +#define CRU_GATE_CON44_ACLK_VPU_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_VPU_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON44_HCLK_VPU_EN_SHIFT (9U) +#define CRU_GATE_CON44_HCLK_VPU_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_VPU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER0_EN_SHIFT (10U) +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER0_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_JPEG_ENCODER0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER0_EN_SHIFT (11U) +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER0_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_JPEG_ENCODER0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER1_EN_SHIFT (12U) +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER1_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_JPEG_ENCODER1_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER1_EN_SHIFT (13U) +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER1_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_JPEG_ENCODER1_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER2_EN_SHIFT (14U) +#define CRU_GATE_CON44_ACLK_JPEG_ENCODER2_EN_MASK (0x1U << CRU_GATE_CON44_ACLK_JPEG_ENCODER2_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER2_EN_SHIFT (15U) +#define CRU_GATE_CON44_HCLK_JPEG_ENCODER2_EN_MASK (0x1U << CRU_GATE_CON44_HCLK_JPEG_ENCODER2_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON45 */ +#define CRU_GATE_CON45_OFFSET (0x8B4U) +#define CRU_GATE_CON45_ACLK_JPEG_ENCODER3_EN_SHIFT (0U) +#define CRU_GATE_CON45_ACLK_JPEG_ENCODER3_EN_MASK (0x1U << CRU_GATE_CON45_ACLK_JPEG_ENCODER3_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON45_HCLK_JPEG_ENCODER3_EN_SHIFT (1U) +#define CRU_GATE_CON45_HCLK_JPEG_ENCODER3_EN_MASK (0x1U << CRU_GATE_CON45_HCLK_JPEG_ENCODER3_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON45_ACLK_JPEG_DECODER_EN_SHIFT (2U) +#define CRU_GATE_CON45_ACLK_JPEG_DECODER_EN_MASK (0x1U << CRU_GATE_CON45_ACLK_JPEG_DECODER_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON45_HCLK_JPEG_DECODER_EN_SHIFT (3U) +#define CRU_GATE_CON45_HCLK_JPEG_DECODER_EN_MASK (0x1U << CRU_GATE_CON45_HCLK_JPEG_DECODER_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON45_HCLK_IEP2P0_EN_SHIFT (4U) +#define CRU_GATE_CON45_HCLK_IEP2P0_EN_MASK (0x1U << CRU_GATE_CON45_HCLK_IEP2P0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON45_ACLK_IEP2P0_EN_SHIFT (5U) +#define CRU_GATE_CON45_ACLK_IEP2P0_EN_MASK (0x1U << CRU_GATE_CON45_ACLK_IEP2P0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON45_CLK_IEP2P0_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON45_CLK_IEP2P0_CORE_EN_MASK (0x1U << CRU_GATE_CON45_CLK_IEP2P0_CORE_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON45_HCLK_RGA2_EN_SHIFT (7U) +#define CRU_GATE_CON45_HCLK_RGA2_EN_MASK (0x1U << CRU_GATE_CON45_HCLK_RGA2_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON45_ACLK_RGA2_EN_SHIFT (8U) +#define CRU_GATE_CON45_ACLK_RGA2_EN_MASK (0x1U << CRU_GATE_CON45_ACLK_RGA2_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON45_CLK_RGA2_CORE_EN_SHIFT (9U) +#define CRU_GATE_CON45_CLK_RGA2_CORE_EN_MASK (0x1U << CRU_GATE_CON45_CLK_RGA2_CORE_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON45_HCLK_RGA3_0_EN_SHIFT (10U) +#define CRU_GATE_CON45_HCLK_RGA3_0_EN_MASK (0x1U << CRU_GATE_CON45_HCLK_RGA3_0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON45_ACLK_RGA3_0_EN_SHIFT (11U) +#define CRU_GATE_CON45_ACLK_RGA3_0_EN_MASK (0x1U << CRU_GATE_CON45_ACLK_RGA3_0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON45_CLK_RGA3_0_CORE_EN_SHIFT (12U) +#define CRU_GATE_CON45_CLK_RGA3_0_CORE_EN_MASK (0x1U << CRU_GATE_CON45_CLK_RGA3_0_CORE_EN_SHIFT) /* 0x00001000 */ +/* GATE_CON47 */ +#define CRU_GATE_CON47_OFFSET (0x8BCU) +#define CRU_GATE_CON47_HCLK_RKVENC0_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON47_HCLK_RKVENC0_ROOT_EN_MASK (0x1U << CRU_GATE_CON47_HCLK_RKVENC0_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON47_ACLK_RKVENC0_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON47_ACLK_RKVENC0_ROOT_EN_MASK (0x1U << CRU_GATE_CON47_ACLK_RKVENC0_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON47_HCLK_RKVENC0_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON47_HCLK_RKVENC0_BIU_EN_MASK (0x1U << CRU_GATE_CON47_HCLK_RKVENC0_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON47_ACLK_RKVENC0_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON47_ACLK_RKVENC0_BIU_EN_MASK (0x1U << CRU_GATE_CON47_ACLK_RKVENC0_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON47_HCLK_RKVENC0_EN_SHIFT (4U) +#define CRU_GATE_CON47_HCLK_RKVENC0_EN_MASK (0x1U << CRU_GATE_CON47_HCLK_RKVENC0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON47_ACLK_RKVENC0_EN_SHIFT (5U) +#define CRU_GATE_CON47_ACLK_RKVENC0_EN_MASK (0x1U << CRU_GATE_CON47_ACLK_RKVENC0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON47_CLK_RKVENC0_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON47_CLK_RKVENC0_CORE_EN_MASK (0x1U << CRU_GATE_CON47_CLK_RKVENC0_CORE_EN_SHIFT) /* 0x00000040 */ +/* GATE_CON48 */ +#define CRU_GATE_CON48_OFFSET (0x8C0U) +#define CRU_GATE_CON48_HCLK_RKVENC1_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON48_HCLK_RKVENC1_ROOT_EN_MASK (0x1U << CRU_GATE_CON48_HCLK_RKVENC1_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON48_ACLK_RKVENC1_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON48_ACLK_RKVENC1_ROOT_EN_MASK (0x1U << CRU_GATE_CON48_ACLK_RKVENC1_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON48_HCLK_RKVENC1_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON48_HCLK_RKVENC1_BIU_EN_MASK (0x1U << CRU_GATE_CON48_HCLK_RKVENC1_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON48_ACLK_RKVENC1_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON48_ACLK_RKVENC1_BIU_EN_MASK (0x1U << CRU_GATE_CON48_ACLK_RKVENC1_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON48_HCLK_RKVENC1_EN_SHIFT (4U) +#define CRU_GATE_CON48_HCLK_RKVENC1_EN_MASK (0x1U << CRU_GATE_CON48_HCLK_RKVENC1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON48_ACLK_RKVENC1_EN_SHIFT (5U) +#define CRU_GATE_CON48_ACLK_RKVENC1_EN_MASK (0x1U << CRU_GATE_CON48_ACLK_RKVENC1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON48_CLK_RKVENC1_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON48_CLK_RKVENC1_CORE_EN_MASK (0x1U << CRU_GATE_CON48_CLK_RKVENC1_CORE_EN_SHIFT) /* 0x00000040 */ +/* GATE_CON49 */ +#define CRU_GATE_CON49_OFFSET (0x8C4U) +#define CRU_GATE_CON49_ACLK_VI_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON49_ACLK_VI_ROOT_EN_MASK (0x1U << CRU_GATE_CON49_ACLK_VI_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON49_HCLK_VI_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON49_HCLK_VI_ROOT_EN_MASK (0x1U << CRU_GATE_CON49_HCLK_VI_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON49_PCLK_VI_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON49_PCLK_VI_ROOT_EN_MASK (0x1U << CRU_GATE_CON49_PCLK_VI_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON49_ACLK_VI_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON49_ACLK_VI_BIU_EN_MASK (0x1U << CRU_GATE_CON49_ACLK_VI_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON49_HCLK_VI_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON49_HCLK_VI_BIU_EN_MASK (0x1U << CRU_GATE_CON49_HCLK_VI_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON49_PCLK_VI_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON49_PCLK_VI_BIU_EN_MASK (0x1U << CRU_GATE_CON49_PCLK_VI_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON49_DCLK_VICAP_EN_SHIFT (6U) +#define CRU_GATE_CON49_DCLK_VICAP_EN_MASK (0x1U << CRU_GATE_CON49_DCLK_VICAP_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON49_ACLK_VICAP_EN_SHIFT (7U) +#define CRU_GATE_CON49_ACLK_VICAP_EN_MASK (0x1U << CRU_GATE_CON49_ACLK_VICAP_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON49_HCLK_VICAP_EN_SHIFT (8U) +#define CRU_GATE_CON49_HCLK_VICAP_EN_MASK (0x1U << CRU_GATE_CON49_HCLK_VICAP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON49_CLK_ISP0_CORE_EN_SHIFT (9U) +#define CRU_GATE_CON49_CLK_ISP0_CORE_EN_MASK (0x1U << CRU_GATE_CON49_CLK_ISP0_CORE_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON49_CLK_ISP0_CORE_MARVIN_EN_SHIFT (10U) +#define CRU_GATE_CON49_CLK_ISP0_CORE_MARVIN_EN_MASK (0x1U << CRU_GATE_CON49_CLK_ISP0_CORE_MARVIN_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON49_CLK_ISP0_CORE_VICAP_EN_SHIFT (11U) +#define CRU_GATE_CON49_CLK_ISP0_CORE_VICAP_EN_MASK (0x1U << CRU_GATE_CON49_CLK_ISP0_CORE_VICAP_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON49_ACLK_ISP0_EN_SHIFT (12U) +#define CRU_GATE_CON49_ACLK_ISP0_EN_MASK (0x1U << CRU_GATE_CON49_ACLK_ISP0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON49_HCLK_ISP0_EN_SHIFT (13U) +#define CRU_GATE_CON49_HCLK_ISP0_EN_MASK (0x1U << CRU_GATE_CON49_HCLK_ISP0_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON49_ACLK_FISHEYE0_EN_SHIFT (14U) +#define CRU_GATE_CON49_ACLK_FISHEYE0_EN_MASK (0x1U << CRU_GATE_CON49_ACLK_FISHEYE0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON49_HCLK_FISHEYE0_EN_SHIFT (15U) +#define CRU_GATE_CON49_HCLK_FISHEYE0_EN_MASK (0x1U << CRU_GATE_CON49_HCLK_FISHEYE0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON50 */ +#define CRU_GATE_CON50_OFFSET (0x8C8U) +#define CRU_GATE_CON50_CLK_FISHEYE0_CORE_EN_SHIFT (0U) +#define CRU_GATE_CON50_CLK_FISHEYE0_CORE_EN_MASK (0x1U << CRU_GATE_CON50_CLK_FISHEYE0_CORE_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON50_ACLK_FISHEYE1_EN_SHIFT (1U) +#define CRU_GATE_CON50_ACLK_FISHEYE1_EN_MASK (0x1U << CRU_GATE_CON50_ACLK_FISHEYE1_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON50_HCLK_FISHEYE1_EN_SHIFT (2U) +#define CRU_GATE_CON50_HCLK_FISHEYE1_EN_MASK (0x1U << CRU_GATE_CON50_HCLK_FISHEYE1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON50_CLK_FISHEYE1_CORE_EN_SHIFT (3U) +#define CRU_GATE_CON50_CLK_FISHEYE1_CORE_EN_MASK (0x1U << CRU_GATE_CON50_CLK_FISHEYE1_CORE_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_0_EN_SHIFT (4U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_0_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_1_EN_SHIFT (5U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_1_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_2_EN_SHIFT (6U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_2_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_3_EN_SHIFT (7U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_3_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_4_EN_SHIFT (8U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_4_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_4_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON50_PCLK_CSI_HOST_5_EN_SHIFT (9U) +#define CRU_GATE_CON50_PCLK_CSI_HOST_5_EN_MASK (0x1U << CRU_GATE_CON50_PCLK_CSI_HOST_5_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON51 */ +#define CRU_GATE_CON51_OFFSET (0x8CCU) +#define CRU_GATE_CON51_CLK_CSIHOST0_VICAP_EN_SHIFT (4U) +#define CRU_GATE_CON51_CLK_CSIHOST0_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST0_VICAP_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON51_CLK_CSIHOST1_VICAP_EN_SHIFT (5U) +#define CRU_GATE_CON51_CLK_CSIHOST1_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST1_VICAP_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON51_CLK_CSIHOST2_VICAP_EN_SHIFT (6U) +#define CRU_GATE_CON51_CLK_CSIHOST2_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST2_VICAP_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON51_CLK_CSIHOST3_VICAP_EN_SHIFT (7U) +#define CRU_GATE_CON51_CLK_CSIHOST3_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST3_VICAP_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON51_CLK_CSIHOST4_VICAP_EN_SHIFT (8U) +#define CRU_GATE_CON51_CLK_CSIHOST4_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST4_VICAP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON51_CLK_CSIHOST5_VICAP_EN_SHIFT (9U) +#define CRU_GATE_CON51_CLK_CSIHOST5_VICAP_EN_MASK (0x1U << CRU_GATE_CON51_CLK_CSIHOST5_VICAP_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON51_ICLK_CSIHOST01_EN_SHIFT (10U) +#define CRU_GATE_CON51_ICLK_CSIHOST01_EN_MASK (0x1U << CRU_GATE_CON51_ICLK_CSIHOST01_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON51_ICLK_CSIHOST0_EN_SHIFT (11U) +#define CRU_GATE_CON51_ICLK_CSIHOST0_EN_MASK (0x1U << CRU_GATE_CON51_ICLK_CSIHOST0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON51_ICLK_CSIHOST1_EN_SHIFT (12U) +#define CRU_GATE_CON51_ICLK_CSIHOST1_EN_MASK (0x1U << CRU_GATE_CON51_ICLK_CSIHOST1_EN_SHIFT) /* 0x00001000 */ +/* GATE_CON52 */ +#define CRU_GATE_CON52_OFFSET (0x8D0U) +#define CRU_GATE_CON52_ACLK_VOP_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON52_ACLK_VOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON52_ACLK_VOP_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON52_ACLK_VOP_LOW_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON52_ACLK_VOP_LOW_ROOT_EN_MASK (0x1U << CRU_GATE_CON52_ACLK_VOP_LOW_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON52_HCLK_VOP_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON52_HCLK_VOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON52_HCLK_VOP_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON52_PCLK_VOP_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON52_PCLK_VOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON52_PCLK_VOP_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON52_ACLK_VOP_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON52_ACLK_VOP_BIU_EN_MASK (0x1U << CRU_GATE_CON52_ACLK_VOP_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON52_ACLK_VOP_LOW_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON52_ACLK_VOP_LOW_BIU_EN_MASK (0x1U << CRU_GATE_CON52_ACLK_VOP_LOW_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON52_HCLK_VOP_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON52_HCLK_VOP_BIU_EN_MASK (0x1U << CRU_GATE_CON52_HCLK_VOP_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON52_PCLK_VOP_BIU_EN_SHIFT (7U) +#define CRU_GATE_CON52_PCLK_VOP_BIU_EN_MASK (0x1U << CRU_GATE_CON52_PCLK_VOP_BIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON52_HCLK_VOP_EN_SHIFT (8U) +#define CRU_GATE_CON52_HCLK_VOP_EN_MASK (0x1U << CRU_GATE_CON52_HCLK_VOP_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON52_ACLK_VOP_EN_SHIFT (9U) +#define CRU_GATE_CON52_ACLK_VOP_EN_MASK (0x1U << CRU_GATE_CON52_ACLK_VOP_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON52_DCLK_VOP0_SRC_EN_SHIFT (10U) +#define CRU_GATE_CON52_DCLK_VOP0_SRC_EN_MASK (0x1U << CRU_GATE_CON52_DCLK_VOP0_SRC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON52_DCLK_VOP1_SRC_EN_SHIFT (11U) +#define CRU_GATE_CON52_DCLK_VOP1_SRC_EN_MASK (0x1U << CRU_GATE_CON52_DCLK_VOP1_SRC_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON52_DCLK_VOP2_SRC_EN_SHIFT (12U) +#define CRU_GATE_CON52_DCLK_VOP2_SRC_EN_MASK (0x1U << CRU_GATE_CON52_DCLK_VOP2_SRC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON52_DCLK_VOP0_EN_SHIFT (13U) +#define CRU_GATE_CON52_DCLK_VOP0_EN_MASK (0x1U << CRU_GATE_CON52_DCLK_VOP0_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON53 */ +#define CRU_GATE_CON53_OFFSET (0x8D4U) +#define CRU_GATE_CON53_DCLK_VOP1_EN_SHIFT (0U) +#define CRU_GATE_CON53_DCLK_VOP1_EN_MASK (0x1U << CRU_GATE_CON53_DCLK_VOP1_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON53_DCLK_VOP2_EN_SHIFT (1U) +#define CRU_GATE_CON53_DCLK_VOP2_EN_MASK (0x1U << CRU_GATE_CON53_DCLK_VOP2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON53_DCLK_VOP3_EN_SHIFT (2U) +#define CRU_GATE_CON53_DCLK_VOP3_EN_MASK (0x1U << CRU_GATE_CON53_DCLK_VOP3_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON53_PCLK_VOPGRF_EN_SHIFT (3U) +#define CRU_GATE_CON53_PCLK_VOPGRF_EN_MASK (0x1U << CRU_GATE_CON53_PCLK_VOPGRF_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON53_PCLK_DSIHOST0_EN_SHIFT (4U) +#define CRU_GATE_CON53_PCLK_DSIHOST0_EN_MASK (0x1U << CRU_GATE_CON53_PCLK_DSIHOST0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON53_PCLK_DSIHOST1_EN_SHIFT (5U) +#define CRU_GATE_CON53_PCLK_DSIHOST1_EN_MASK (0x1U << CRU_GATE_CON53_PCLK_DSIHOST1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON53_CLK_DSIHOST0_EN_SHIFT (6U) +#define CRU_GATE_CON53_CLK_DSIHOST0_EN_MASK (0x1U << CRU_GATE_CON53_CLK_DSIHOST0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON53_CLK_DSIHOST1_EN_SHIFT (7U) +#define CRU_GATE_CON53_CLK_DSIHOST1_EN_MASK (0x1U << CRU_GATE_CON53_CLK_DSIHOST1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON53_CLK_VOP_PMU_EN_SHIFT (8U) +#define CRU_GATE_CON53_CLK_VOP_PMU_EN_MASK (0x1U << CRU_GATE_CON53_CLK_VOP_PMU_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON53_PCLK_VOP_CHANNEL_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON53_PCLK_VOP_CHANNEL_BIU_EN_MASK (0x1U << CRU_GATE_CON53_PCLK_VOP_CHANNEL_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON53_ACLK_VOP_DOBY_EN_SHIFT (10U) +#define CRU_GATE_CON53_ACLK_VOP_DOBY_EN_MASK (0x1U << CRU_GATE_CON53_ACLK_VOP_DOBY_EN_SHIFT) /* 0x00000400 */ +/* GATE_CON55 */ +#define CRU_GATE_CON55_OFFSET (0x8DCU) +#define CRU_GATE_CON55_ACLK_VO0_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON55_ACLK_VO0_ROOT_EN_MASK (0x1U << CRU_GATE_CON55_ACLK_VO0_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON55_HCLK_VO0_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON55_HCLK_VO0_ROOT_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_VO0_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON55_HCLK_VO0_S_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON55_HCLK_VO0_S_ROOT_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_VO0_S_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON55_PCLK_VO0_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON55_PCLK_VO0_ROOT_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_VO0_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON55_PCLK_VO0_S_ROOT_EN_SHIFT (4U) +#define CRU_GATE_CON55_PCLK_VO0_S_ROOT_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_VO0_S_ROOT_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON55_HCLK_VO0_BIU_EN_SHIFT (5U) +#define CRU_GATE_CON55_HCLK_VO0_BIU_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_VO0_BIU_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON55_HCLK_VO0_S_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON55_HCLK_VO0_S_BIU_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_VO0_S_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON55_PCLK_VO0_BIU_EN_SHIFT (7U) +#define CRU_GATE_CON55_PCLK_VO0_BIU_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_VO0_BIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON55_PCLK_VO0_S_BIU_EN_SHIFT (8U) +#define CRU_GATE_CON55_PCLK_VO0_S_BIU_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_VO0_S_BIU_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON55_ACLK_HDCP0_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON55_ACLK_HDCP0_BIU_EN_MASK (0x1U << CRU_GATE_CON55_ACLK_HDCP0_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON55_PCLK_VO0GRF_EN_SHIFT (10U) +#define CRU_GATE_CON55_PCLK_VO0GRF_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_VO0GRF_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON55_HCLK_HDCP_KEY0_EN_SHIFT (11U) +#define CRU_GATE_CON55_HCLK_HDCP_KEY0_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_HDCP_KEY0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON55_ACLK_HDCP0_EN_SHIFT (12U) +#define CRU_GATE_CON55_ACLK_HDCP0_EN_MASK (0x1U << CRU_GATE_CON55_ACLK_HDCP0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON55_HCLK_HDCP0_EN_SHIFT (13U) +#define CRU_GATE_CON55_HCLK_HDCP0_EN_MASK (0x1U << CRU_GATE_CON55_HCLK_HDCP0_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON55_PCLK_HDCP0_EN_SHIFT (14U) +#define CRU_GATE_CON55_PCLK_HDCP0_EN_MASK (0x1U << CRU_GATE_CON55_PCLK_HDCP0_EN_SHIFT) /* 0x00004000 */ +/* GATE_CON56 */ +#define CRU_GATE_CON56_OFFSET (0x8E0U) +#define CRU_GATE_CON56_ACLK_TRNG0_EN_SHIFT (0U) +#define CRU_GATE_CON56_ACLK_TRNG0_EN_MASK (0x1U << CRU_GATE_CON56_ACLK_TRNG0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON56_PCLK_TRNG0_EN_SHIFT (1U) +#define CRU_GATE_CON56_PCLK_TRNG0_EN_MASK (0x1U << CRU_GATE_CON56_PCLK_TRNG0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON56_CLK_AUX16MHZ_0_EN_SHIFT (2U) +#define CRU_GATE_CON56_CLK_AUX16MHZ_0_EN_MASK (0x1U << CRU_GATE_CON56_CLK_AUX16MHZ_0_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON56_CLK_AUX16MHZ_1_EN_SHIFT (3U) +#define CRU_GATE_CON56_CLK_AUX16MHZ_1_EN_MASK (0x1U << CRU_GATE_CON56_CLK_AUX16MHZ_1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON56_PCLK_DP0_EN_SHIFT (4U) +#define CRU_GATE_CON56_PCLK_DP0_EN_MASK (0x1U << CRU_GATE_CON56_PCLK_DP0_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON56_PCLK_DP1_EN_SHIFT (5U) +#define CRU_GATE_CON56_PCLK_DP1_EN_MASK (0x1U << CRU_GATE_CON56_PCLK_DP1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON56_PCLK_S_DP0_EN_SHIFT (6U) +#define CRU_GATE_CON56_PCLK_S_DP0_EN_MASK (0x1U << CRU_GATE_CON56_PCLK_S_DP0_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON56_PCLK_S_DP1_EN_SHIFT (7U) +#define CRU_GATE_CON56_PCLK_S_DP1_EN_MASK (0x1U << CRU_GATE_CON56_PCLK_S_DP1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON56_CLK_DP0_EN_SHIFT (8U) +#define CRU_GATE_CON56_CLK_DP0_EN_MASK (0x1U << CRU_GATE_CON56_CLK_DP0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON56_CLK_DP1_EN_SHIFT (9U) +#define CRU_GATE_CON56_CLK_DP1_EN_MASK (0x1U << CRU_GATE_CON56_CLK_DP1_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON56_HCLK_I2S4_8CH_EN_SHIFT (10U) +#define CRU_GATE_CON56_HCLK_I2S4_8CH_EN_MASK (0x1U << CRU_GATE_CON56_HCLK_I2S4_8CH_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON56_CLK_I2S4_8CH_TX_EN_SHIFT (11U) +#define CRU_GATE_CON56_CLK_I2S4_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON56_CLK_I2S4_8CH_TX_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON56_CLK_I2S4_8CH_FRAC_TX_EN_SHIFT (12U) +#define CRU_GATE_CON56_CLK_I2S4_8CH_FRAC_TX_EN_MASK (0x1U << CRU_GATE_CON56_CLK_I2S4_8CH_FRAC_TX_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON56_MCLK_I2S4_8CH_TX_EN_SHIFT (13U) +#define CRU_GATE_CON56_MCLK_I2S4_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON56_MCLK_I2S4_8CH_TX_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON56_HCLK_I2S8_8CH_EN_SHIFT (14U) +#define CRU_GATE_CON56_HCLK_I2S8_8CH_EN_MASK (0x1U << CRU_GATE_CON56_HCLK_I2S8_8CH_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON56_CLK_I2S8_8CH_TX_EN_SHIFT (15U) +#define CRU_GATE_CON56_CLK_I2S8_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON56_CLK_I2S8_8CH_TX_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON57 */ +#define CRU_GATE_CON57_OFFSET (0x8E4U) +#define CRU_GATE_CON57_CLK_I2S8_8CH_FRAC_TX_EN_SHIFT (0U) +#define CRU_GATE_CON57_CLK_I2S8_8CH_FRAC_TX_EN_MASK (0x1U << CRU_GATE_CON57_CLK_I2S8_8CH_FRAC_TX_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON57_MCLK_I2S8_8CH_TX_EN_SHIFT (1U) +#define CRU_GATE_CON57_MCLK_I2S8_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON57_MCLK_I2S8_8CH_TX_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON57_HCLK_SPDIF2_DP0_EN_SHIFT (2U) +#define CRU_GATE_CON57_HCLK_SPDIF2_DP0_EN_MASK (0x1U << CRU_GATE_CON57_HCLK_SPDIF2_DP0_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON57_CLK_SPDIF2_DP0_EN_SHIFT (3U) +#define CRU_GATE_CON57_CLK_SPDIF2_DP0_EN_MASK (0x1U << CRU_GATE_CON57_CLK_SPDIF2_DP0_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON57_CLK_SPDIF2_DP0_FRAC_EN_SHIFT (4U) +#define CRU_GATE_CON57_CLK_SPDIF2_DP0_FRAC_EN_MASK (0x1U << CRU_GATE_CON57_CLK_SPDIF2_DP0_FRAC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON57_MCLK_SPDIF2_DP0_EN_SHIFT (5U) +#define CRU_GATE_CON57_MCLK_SPDIF2_DP0_EN_MASK (0x1U << CRU_GATE_CON57_MCLK_SPDIF2_DP0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON57_MCLK_SPDIF2_EN_SHIFT (6U) +#define CRU_GATE_CON57_MCLK_SPDIF2_EN_MASK (0x1U << CRU_GATE_CON57_MCLK_SPDIF2_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON57_HCLK_SPDIF5_DP1_EN_SHIFT (7U) +#define CRU_GATE_CON57_HCLK_SPDIF5_DP1_EN_MASK (0x1U << CRU_GATE_CON57_HCLK_SPDIF5_DP1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON57_CLK_SPDIF5_DP1_EN_SHIFT (8U) +#define CRU_GATE_CON57_CLK_SPDIF5_DP1_EN_MASK (0x1U << CRU_GATE_CON57_CLK_SPDIF5_DP1_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON57_CLK_SPDIF5_DP1_FRAC_EN_SHIFT (9U) +#define CRU_GATE_CON57_CLK_SPDIF5_DP1_FRAC_EN_MASK (0x1U << CRU_GATE_CON57_CLK_SPDIF5_DP1_FRAC_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON57_MCLK_SPDIF5_DP1_EN_SHIFT (10U) +#define CRU_GATE_CON57_MCLK_SPDIF5_DP1_EN_MASK (0x1U << CRU_GATE_CON57_MCLK_SPDIF5_DP1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON57_MCLK_SPDIF5_EN_SHIFT (11U) +#define CRU_GATE_CON57_MCLK_SPDIF5_EN_MASK (0x1U << CRU_GATE_CON57_MCLK_SPDIF5_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON59 */ +#define CRU_GATE_CON59_OFFSET (0x8ECU) +#define CRU_GATE_CON59_ACLK_HDCP1_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON59_ACLK_HDCP1_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_ACLK_HDCP1_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON59_ACLK_HDMIRX_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON59_ACLK_HDMIRX_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_ACLK_HDMIRX_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON59_HCLK_VO1_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON59_HCLK_VO1_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_HCLK_VO1_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON59_HCLK_VO1_S_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON59_HCLK_VO1_S_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_HCLK_VO1_S_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON59_PCLK_VO1_ROOT_EN_SHIFT (4U) +#define CRU_GATE_CON59_PCLK_VO1_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_VO1_ROOT_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON59_PCLK_VO1_S_ROOT_EN_SHIFT (5U) +#define CRU_GATE_CON59_PCLK_VO1_S_ROOT_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_VO1_S_ROOT_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON59_ACLK_HDCP1_BIU_EN_SHIFT (6U) +#define CRU_GATE_CON59_ACLK_HDCP1_BIU_EN_MASK (0x1U << CRU_GATE_CON59_ACLK_HDCP1_BIU_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON59_ACLK_VO1_BIU_EN_SHIFT (8U) +#define CRU_GATE_CON59_ACLK_VO1_BIU_EN_MASK (0x1U << CRU_GATE_CON59_ACLK_VO1_BIU_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON59_HCLK_VO1_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON59_HCLK_VO1_BIU_EN_MASK (0x1U << CRU_GATE_CON59_HCLK_VO1_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON59_HCLK_VO1_S_BIU_EN_SHIFT (10U) +#define CRU_GATE_CON59_HCLK_VO1_S_BIU_EN_MASK (0x1U << CRU_GATE_CON59_HCLK_VO1_S_BIU_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON59_PCLK_VO1_BIU_EN_SHIFT (11U) +#define CRU_GATE_CON59_PCLK_VO1_BIU_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_VO1_BIU_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON59_PCLK_VO1GRF_EN_SHIFT (12U) +#define CRU_GATE_CON59_PCLK_VO1GRF_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_VO1GRF_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON59_PCLK_VO1_S_BIU_EN_SHIFT (13U) +#define CRU_GATE_CON59_PCLK_VO1_S_BIU_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_VO1_S_BIU_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON59_PCLK_S_EDP0_EN_SHIFT (14U) +#define CRU_GATE_CON59_PCLK_S_EDP0_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_S_EDP0_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON59_PCLK_S_EDP1_EN_SHIFT (15U) +#define CRU_GATE_CON59_PCLK_S_EDP1_EN_MASK (0x1U << CRU_GATE_CON59_PCLK_S_EDP1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON60 */ +#define CRU_GATE_CON60_OFFSET (0x8F0U) +#define CRU_GATE_CON60_HCLK_I2S7_8CH_EN_SHIFT (0U) +#define CRU_GATE_CON60_HCLK_I2S7_8CH_EN_MASK (0x1U << CRU_GATE_CON60_HCLK_I2S7_8CH_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON60_CLK_I2S7_8CH_RX_EN_SHIFT (1U) +#define CRU_GATE_CON60_CLK_I2S7_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON60_CLK_I2S7_8CH_RX_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON60_CLK_I2S7_8CH_FRAC_RX_EN_SHIFT (2U) +#define CRU_GATE_CON60_CLK_I2S7_8CH_FRAC_RX_EN_MASK (0x1U << CRU_GATE_CON60_CLK_I2S7_8CH_FRAC_RX_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON60_MCLK_I2S7_8CH_RX_EN_SHIFT (3U) +#define CRU_GATE_CON60_MCLK_I2S7_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON60_MCLK_I2S7_8CH_RX_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON60_HCLK_HDCP_KEY1_EN_SHIFT (4U) +#define CRU_GATE_CON60_HCLK_HDCP_KEY1_EN_MASK (0x1U << CRU_GATE_CON60_HCLK_HDCP_KEY1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON60_ACLK_HDCP1_EN_SHIFT (5U) +#define CRU_GATE_CON60_ACLK_HDCP1_EN_MASK (0x1U << CRU_GATE_CON60_ACLK_HDCP1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON60_HCLK_HDCP1_EN_SHIFT (6U) +#define CRU_GATE_CON60_HCLK_HDCP1_EN_MASK (0x1U << CRU_GATE_CON60_HCLK_HDCP1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON60_PCLK_HDCP1_EN_SHIFT (7U) +#define CRU_GATE_CON60_PCLK_HDCP1_EN_MASK (0x1U << CRU_GATE_CON60_PCLK_HDCP1_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON60_ACLK_TRNG1_EN_SHIFT (9U) +#define CRU_GATE_CON60_ACLK_TRNG1_EN_MASK (0x1U << CRU_GATE_CON60_ACLK_TRNG1_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON60_PCLK_TRNG1_EN_SHIFT (10U) +#define CRU_GATE_CON60_PCLK_TRNG1_EN_MASK (0x1U << CRU_GATE_CON60_PCLK_TRNG1_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON60_PCLK_HDMITX0_EN_SHIFT (11U) +#define CRU_GATE_CON60_PCLK_HDMITX0_EN_MASK (0x1U << CRU_GATE_CON60_PCLK_HDMITX0_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON60_CLK_HDMITX0_EARC_EN_SHIFT (15U) +#define CRU_GATE_CON60_CLK_HDMITX0_EARC_EN_MASK (0x1U << CRU_GATE_CON60_CLK_HDMITX0_EARC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON61 */ +#define CRU_GATE_CON61_OFFSET (0x8F4U) +#define CRU_GATE_CON61_CLK_HDMITX0_REF_EN_SHIFT (0U) +#define CRU_GATE_CON61_CLK_HDMITX0_REF_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMITX0_REF_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON61_PCLK_HDMITX1_EN_SHIFT (2U) +#define CRU_GATE_CON61_PCLK_HDMITX1_EN_MASK (0x1U << CRU_GATE_CON61_PCLK_HDMITX1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON61_CLK_HDMITX1_EARC_EN_SHIFT (6U) +#define CRU_GATE_CON61_CLK_HDMITX1_EARC_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMITX1_EARC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON61_CLK_HDMITX1_REF_EN_SHIFT (7U) +#define CRU_GATE_CON61_CLK_HDMITX1_REF_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMITX1_REF_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON61_ACLK_HDMIRX_EN_SHIFT (9U) +#define CRU_GATE_CON61_ACLK_HDMIRX_EN_MASK (0x1U << CRU_GATE_CON61_ACLK_HDMIRX_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON61_PCLK_HDMIRX_EN_SHIFT (10U) +#define CRU_GATE_CON61_PCLK_HDMIRX_EN_MASK (0x1U << CRU_GATE_CON61_PCLK_HDMIRX_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON61_CLK_HDMIRX_REF_EN_SHIFT (11U) +#define CRU_GATE_CON61_CLK_HDMIRX_REF_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMIRX_REF_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_SRC_EN_SHIFT (12U) +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_SRC_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMIRX_AUD_SRC_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_FRAC_EN_SHIFT (13U) +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_FRAC_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMIRX_AUD_FRAC_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_EN_SHIFT (14U) +#define CRU_GATE_CON61_CLK_HDMIRX_AUD_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMIRX_AUD_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON61_CLK_HDMIRX_TMDSQP_EN_SHIFT (15U) +#define CRU_GATE_CON61_CLK_HDMIRX_TMDSQP_EN_MASK (0x1U << CRU_GATE_CON61_CLK_HDMIRX_TMDSQP_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON62 */ +#define CRU_GATE_CON62_OFFSET (0x8F8U) +#define CRU_GATE_CON62_PCLK_EDP0_EN_SHIFT (0U) +#define CRU_GATE_CON62_PCLK_EDP0_EN_MASK (0x1U << CRU_GATE_CON62_PCLK_EDP0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON62_CLK_EDP0_24M_EN_SHIFT (1U) +#define CRU_GATE_CON62_CLK_EDP0_24M_EN_MASK (0x1U << CRU_GATE_CON62_CLK_EDP0_24M_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON62_CLK_EDP0_200M_EN_SHIFT (2U) +#define CRU_GATE_CON62_CLK_EDP0_200M_EN_MASK (0x1U << CRU_GATE_CON62_CLK_EDP0_200M_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON62_PCLK_EDP1_EN_SHIFT (3U) +#define CRU_GATE_CON62_PCLK_EDP1_EN_MASK (0x1U << CRU_GATE_CON62_PCLK_EDP1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON62_CLK_EDP1_24M_EN_SHIFT (4U) +#define CRU_GATE_CON62_CLK_EDP1_24M_EN_MASK (0x1U << CRU_GATE_CON62_CLK_EDP1_24M_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON62_CLK_EDP1_200M_EN_SHIFT (5U) +#define CRU_GATE_CON62_CLK_EDP1_200M_EN_MASK (0x1U << CRU_GATE_CON62_CLK_EDP1_200M_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON62_CLK_I2S5_8CH_TX_EN_SHIFT (6U) +#define CRU_GATE_CON62_CLK_I2S5_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON62_CLK_I2S5_8CH_TX_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON62_CLK_I2S5_8CH_FRAC_TX_EN_SHIFT (7U) +#define CRU_GATE_CON62_CLK_I2S5_8CH_FRAC_TX_EN_MASK (0x1U << CRU_GATE_CON62_CLK_I2S5_8CH_FRAC_TX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON62_MCLK_I2S5_8CH_TX_EN_SHIFT (8U) +#define CRU_GATE_CON62_MCLK_I2S5_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON62_MCLK_I2S5_8CH_TX_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON62_HCLK_I2S5_8CH_EN_SHIFT (12U) +#define CRU_GATE_CON62_HCLK_I2S5_8CH_EN_MASK (0x1U << CRU_GATE_CON62_HCLK_I2S5_8CH_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON62_CLK_I2S6_8CH_TX_EN_SHIFT (13U) +#define CRU_GATE_CON62_CLK_I2S6_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON62_CLK_I2S6_8CH_TX_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON62_CLK_I2S6_8CH_FRAC_TX_EN_SHIFT (14U) +#define CRU_GATE_CON62_CLK_I2S6_8CH_FRAC_TX_EN_MASK (0x1U << CRU_GATE_CON62_CLK_I2S6_8CH_FRAC_TX_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON62_MCLK_I2S6_8CH_TX_EN_SHIFT (15U) +#define CRU_GATE_CON62_MCLK_I2S6_8CH_TX_EN_MASK (0x1U << CRU_GATE_CON62_MCLK_I2S6_8CH_TX_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON63 */ +#define CRU_GATE_CON63_OFFSET (0x8FCU) +#define CRU_GATE_CON63_CLK_I2S6_8CH_RX_EN_SHIFT (0U) +#define CRU_GATE_CON63_CLK_I2S6_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON63_CLK_I2S6_8CH_RX_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON63_CLK_I2S6_8CH_FRAC_RX_EN_SHIFT (1U) +#define CRU_GATE_CON63_CLK_I2S6_8CH_FRAC_RX_EN_MASK (0x1U << CRU_GATE_CON63_CLK_I2S6_8CH_FRAC_RX_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON63_MCLK_I2S6_8CH_RX_EN_SHIFT (2U) +#define CRU_GATE_CON63_MCLK_I2S6_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON63_MCLK_I2S6_8CH_RX_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON63_HCLK_I2S6_8CH_EN_SHIFT (3U) +#define CRU_GATE_CON63_HCLK_I2S6_8CH_EN_MASK (0x1U << CRU_GATE_CON63_HCLK_I2S6_8CH_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON63_HCLK_SPDIF3_EN_SHIFT (4U) +#define CRU_GATE_CON63_HCLK_SPDIF3_EN_MASK (0x1U << CRU_GATE_CON63_HCLK_SPDIF3_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON63_CLK_SPDIF3_EN_SHIFT (5U) +#define CRU_GATE_CON63_CLK_SPDIF3_EN_MASK (0x1U << CRU_GATE_CON63_CLK_SPDIF3_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON63_CLK_SPDIF3_FRAC_EN_SHIFT (6U) +#define CRU_GATE_CON63_CLK_SPDIF3_FRAC_EN_MASK (0x1U << CRU_GATE_CON63_CLK_SPDIF3_FRAC_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON63_MCLK_SPDIF3_EN_SHIFT (7U) +#define CRU_GATE_CON63_MCLK_SPDIF3_EN_MASK (0x1U << CRU_GATE_CON63_MCLK_SPDIF3_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON63_HCLK_SPDIF4_EN_SHIFT (8U) +#define CRU_GATE_CON63_HCLK_SPDIF4_EN_MASK (0x1U << CRU_GATE_CON63_HCLK_SPDIF4_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON63_CLK_SPDIF4_EN_SHIFT (9U) +#define CRU_GATE_CON63_CLK_SPDIF4_EN_MASK (0x1U << CRU_GATE_CON63_CLK_SPDIF4_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON63_CLK_SPDIF4_FRAC_EN_SHIFT (10U) +#define CRU_GATE_CON63_CLK_SPDIF4_FRAC_EN_MASK (0x1U << CRU_GATE_CON63_CLK_SPDIF4_FRAC_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON63_MCLK_SPDIF4_EN_SHIFT (11U) +#define CRU_GATE_CON63_MCLK_SPDIF4_EN_MASK (0x1U << CRU_GATE_CON63_MCLK_SPDIF4_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON63_HCLK_SPDIFRX0_EN_SHIFT (12U) +#define CRU_GATE_CON63_HCLK_SPDIFRX0_EN_MASK (0x1U << CRU_GATE_CON63_HCLK_SPDIFRX0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON63_MCLK_SPDIFRX0_EN_SHIFT (13U) +#define CRU_GATE_CON63_MCLK_SPDIFRX0_EN_MASK (0x1U << CRU_GATE_CON63_MCLK_SPDIFRX0_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON63_HCLK_SPDIFRX1_EN_SHIFT (14U) +#define CRU_GATE_CON63_HCLK_SPDIFRX1_EN_MASK (0x1U << CRU_GATE_CON63_HCLK_SPDIFRX1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON63_MCLK_SPDIFRX1_EN_SHIFT (15U) +#define CRU_GATE_CON63_MCLK_SPDIFRX1_EN_MASK (0x1U << CRU_GATE_CON63_MCLK_SPDIFRX1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON64 */ +#define CRU_GATE_CON64_OFFSET (0x900U) +#define CRU_GATE_CON64_HCLK_SPDIFRX2_EN_SHIFT (0U) +#define CRU_GATE_CON64_HCLK_SPDIFRX2_EN_MASK (0x1U << CRU_GATE_CON64_HCLK_SPDIFRX2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON64_MCLK_SPDIFRX2_EN_SHIFT (1U) +#define CRU_GATE_CON64_MCLK_SPDIFRX2_EN_MASK (0x1U << CRU_GATE_CON64_MCLK_SPDIFRX2_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE0_VO1_EN_SHIFT (14U) +#define CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE0_VO1_EN_MASK (0x1U << CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE0_VO1_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE1_VO1_EN_SHIFT (15U) +#define CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE1_VO1_EN_MASK (0x1U << CRU_GATE_CON64_DCLK_VOP2HDMI_BRIDGE1_VO1_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON65 */ +#define CRU_GATE_CON65_OFFSET (0x904U) +#define CRU_GATE_CON65_HCLK_I2S9_8CH_EN_SHIFT (0U) +#define CRU_GATE_CON65_HCLK_I2S9_8CH_EN_MASK (0x1U << CRU_GATE_CON65_HCLK_I2S9_8CH_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON65_CLK_I2S9_8CH_RX_EN_SHIFT (1U) +#define CRU_GATE_CON65_CLK_I2S9_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON65_CLK_I2S9_8CH_RX_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON65_CLK_I2S9_8CH_FRAC_RX_EN_SHIFT (2U) +#define CRU_GATE_CON65_CLK_I2S9_8CH_FRAC_RX_EN_MASK (0x1U << CRU_GATE_CON65_CLK_I2S9_8CH_FRAC_RX_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON65_MCLK_I2S9_8CH_RX_EN_SHIFT (3U) +#define CRU_GATE_CON65_MCLK_I2S9_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON65_MCLK_I2S9_8CH_RX_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON65_HCLK_I2S10_8CH_EN_SHIFT (4U) +#define CRU_GATE_CON65_HCLK_I2S10_8CH_EN_MASK (0x1U << CRU_GATE_CON65_HCLK_I2S10_8CH_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON65_CLK_I2S10_8CH_RX_EN_SHIFT (5U) +#define CRU_GATE_CON65_CLK_I2S10_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON65_CLK_I2S10_8CH_RX_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON65_CLK_I2S10_8CH_FRAC_RX_EN_SHIFT (6U) +#define CRU_GATE_CON65_CLK_I2S10_8CH_FRAC_RX_EN_MASK (0x1U << CRU_GATE_CON65_CLK_I2S10_8CH_FRAC_RX_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON65_MCLK_I2S10_8CH_RX_EN_SHIFT (7U) +#define CRU_GATE_CON65_MCLK_I2S10_8CH_RX_EN_MASK (0x1U << CRU_GATE_CON65_MCLK_I2S10_8CH_RX_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON65_PCLK_S_HDMIRX_EN_SHIFT (8U) +#define CRU_GATE_CON65_PCLK_S_HDMIRX_EN_MASK (0x1U << CRU_GATE_CON65_PCLK_S_HDMIRX_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON65_CLK_HDMITRX_REFSRC_EN_SHIFT (9U) +#define CRU_GATE_CON65_CLK_HDMITRX_REFSRC_EN_MASK (0x1U << CRU_GATE_CON65_CLK_HDMITRX_REFSRC_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON66 */ +#define CRU_GATE_CON66_OFFSET (0x908U) +#define CRU_GATE_CON66_CLK_GPU_SRC_DF_EN_SHIFT (1U) +#define CRU_GATE_CON66_CLK_GPU_SRC_DF_EN_MASK (0x1U << CRU_GATE_CON66_CLK_GPU_SRC_DF_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON66_CLK_TESTOUT_GPU_EN_SHIFT (2U) +#define CRU_GATE_CON66_CLK_TESTOUT_GPU_EN_MASK (0x1U << CRU_GATE_CON66_CLK_TESTOUT_GPU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON66_CLK_GPU_SRC_EN_SHIFT (3U) +#define CRU_GATE_CON66_CLK_GPU_SRC_EN_MASK (0x1U << CRU_GATE_CON66_CLK_GPU_SRC_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON66_CLK_GPU_EN_SHIFT (4U) +#define CRU_GATE_CON66_CLK_GPU_EN_MASK (0x1U << CRU_GATE_CON66_CLK_GPU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON66_CLK_GPU_COREGROUP_EN_SHIFT (6U) +#define CRU_GATE_CON66_CLK_GPU_COREGROUP_EN_MASK (0x1U << CRU_GATE_CON66_CLK_GPU_COREGROUP_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON66_CLK_GPU_STACKS_EN_SHIFT (7U) +#define CRU_GATE_CON66_CLK_GPU_STACKS_EN_MASK (0x1U << CRU_GATE_CON66_CLK_GPU_STACKS_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON66_ACLK_S_GPU_BIU_EN_SHIFT (8U) +#define CRU_GATE_CON66_ACLK_S_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_ACLK_S_GPU_BIU_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON66_ACLK_M0_GPU_BIU_EN_SHIFT (9U) +#define CRU_GATE_CON66_ACLK_M0_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_ACLK_M0_GPU_BIU_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON66_ACLK_M1_GPU_BIU_EN_SHIFT (10U) +#define CRU_GATE_CON66_ACLK_M1_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_ACLK_M1_GPU_BIU_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON66_ACLK_M2_GPU_BIU_EN_SHIFT (11U) +#define CRU_GATE_CON66_ACLK_M2_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_ACLK_M2_GPU_BIU_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON66_ACLK_M3_GPU_BIU_EN_SHIFT (12U) +#define CRU_GATE_CON66_ACLK_M3_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_ACLK_M3_GPU_BIU_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON66_PCLK_GPU_ROOT_EN_SHIFT (13U) +#define CRU_GATE_CON66_PCLK_GPU_ROOT_EN_MASK (0x1U << CRU_GATE_CON66_PCLK_GPU_ROOT_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON66_PCLK_GPU_BIU_EN_SHIFT (14U) +#define CRU_GATE_CON66_PCLK_GPU_BIU_EN_MASK (0x1U << CRU_GATE_CON66_PCLK_GPU_BIU_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON66_PCLK_PVTM2_EN_SHIFT (15U) +#define CRU_GATE_CON66_PCLK_PVTM2_EN_MASK (0x1U << CRU_GATE_CON66_PCLK_PVTM2_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON67 */ +#define CRU_GATE_CON67_OFFSET (0x90CU) +#define CRU_GATE_CON67_CLK_PVTM2_EN_SHIFT (0U) +#define CRU_GATE_CON67_CLK_PVTM2_EN_MASK (0x1U << CRU_GATE_CON67_CLK_PVTM2_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON67_CLK_GPU_PVTM_EN_SHIFT (1U) +#define CRU_GATE_CON67_CLK_GPU_PVTM_EN_MASK (0x1U << CRU_GATE_CON67_CLK_GPU_PVTM_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON67_PCLK_GPU_GRF_EN_SHIFT (2U) +#define CRU_GATE_CON67_PCLK_GPU_GRF_EN_MASK (0x1U << CRU_GATE_CON67_PCLK_GPU_GRF_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON67_CLK_GPU_PVTPLL_EN_SHIFT (3U) +#define CRU_GATE_CON67_CLK_GPU_PVTPLL_EN_MASK (0x1U << CRU_GATE_CON67_CLK_GPU_PVTPLL_EN_SHIFT) /* 0x00000008 */ +/* GATE_CON68 */ +#define CRU_GATE_CON68_OFFSET (0x910U) +#define CRU_GATE_CON68_ACLK_AV1_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON68_ACLK_AV1_ROOT_EN_MASK (0x1U << CRU_GATE_CON68_ACLK_AV1_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON68_ACLK_AV1_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON68_ACLK_AV1_BIU_EN_MASK (0x1U << CRU_GATE_CON68_ACLK_AV1_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON68_ACLK_AV1_EN_SHIFT (2U) +#define CRU_GATE_CON68_ACLK_AV1_EN_MASK (0x1U << CRU_GATE_CON68_ACLK_AV1_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON68_PCLK_AV1_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON68_PCLK_AV1_ROOT_EN_MASK (0x1U << CRU_GATE_CON68_PCLK_AV1_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON68_PCLK_AV1_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON68_PCLK_AV1_BIU_EN_MASK (0x1U << CRU_GATE_CON68_PCLK_AV1_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON68_PCLK_AV1_EN_SHIFT (5U) +#define CRU_GATE_CON68_PCLK_AV1_EN_MASK (0x1U << CRU_GATE_CON68_PCLK_AV1_EN_SHIFT) /* 0x00000020 */ +/* GATE_CON69 */ +#define CRU_GATE_CON69_OFFSET (0x914U) +#define CRU_GATE_CON69_ACLK_CENTER_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON69_ACLK_CENTER_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON69_ACLK_CENTER_LOW_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON69_ACLK_CENTER_LOW_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_LOW_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON69_HCLK_CENTER_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON69_HCLK_CENTER_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_HCLK_CENTER_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON69_PCLK_CENTER_ROOT_EN_SHIFT (3U) +#define CRU_GATE_CON69_PCLK_CENTER_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_PCLK_CENTER_ROOT_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON69_ACLK_DDR_BIU_EN_SHIFT (4U) +#define CRU_GATE_CON69_ACLK_DDR_BIU_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_DDR_BIU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON69_ACLK_DMA2DDR_EN_SHIFT (5U) +#define CRU_GATE_CON69_ACLK_DMA2DDR_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_DMA2DDR_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON69_ACLK_DDR_SHAREMEM_EN_SHIFT (6U) +#define CRU_GATE_CON69_ACLK_DDR_SHAREMEM_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_DDR_SHAREMEM_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON69_ACLK_DDR_SHAREMEM_BIU_EN_SHIFT (7U) +#define CRU_GATE_CON69_ACLK_DDR_SHAREMEM_BIU_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_DDR_SHAREMEM_BIU_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON69_ACLK_CENTER_S200_ROOT_EN_SHIFT (8U) +#define CRU_GATE_CON69_ACLK_CENTER_S200_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_S200_ROOT_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON69_ACLK_CENTER_S400_ROOT_EN_SHIFT (9U) +#define CRU_GATE_CON69_ACLK_CENTER_S400_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_S400_ROOT_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON69_ACLK_CENTER_S200_BIU_EN_SHIFT (10U) +#define CRU_GATE_CON69_ACLK_CENTER_S200_BIU_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_S200_BIU_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON69_ACLK_CENTER_S400_BIU_EN_SHIFT (11U) +#define CRU_GATE_CON69_ACLK_CENTER_S400_BIU_EN_MASK (0x1U << CRU_GATE_CON69_ACLK_CENTER_S400_BIU_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON69_HCLK_AHB2APB_EN_SHIFT (12U) +#define CRU_GATE_CON69_HCLK_AHB2APB_EN_MASK (0x1U << CRU_GATE_CON69_HCLK_AHB2APB_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON69_HCLK_CENTER_BIU_EN_SHIFT (13U) +#define CRU_GATE_CON69_HCLK_CENTER_BIU_EN_MASK (0x1U << CRU_GATE_CON69_HCLK_CENTER_BIU_EN_SHIFT) /* 0x00002000 */ +#define CRU_GATE_CON69_FCLK_DDR_CM0_CORE_EN_SHIFT (14U) +#define CRU_GATE_CON69_FCLK_DDR_CM0_CORE_EN_MASK (0x1U << CRU_GATE_CON69_FCLK_DDR_CM0_CORE_EN_SHIFT) /* 0x00004000 */ +#define CRU_GATE_CON69_CLK_DDR_TIMER_ROOT_EN_SHIFT (15U) +#define CRU_GATE_CON69_CLK_DDR_TIMER_ROOT_EN_MASK (0x1U << CRU_GATE_CON69_CLK_DDR_TIMER_ROOT_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON70 */ +#define CRU_GATE_CON70_OFFSET (0x918U) +#define CRU_GATE_CON70_CLK_DDR_TIMER0_EN_SHIFT (0U) +#define CRU_GATE_CON70_CLK_DDR_TIMER0_EN_MASK (0x1U << CRU_GATE_CON70_CLK_DDR_TIMER0_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON70_CLK_DDR_TIMER1_EN_SHIFT (1U) +#define CRU_GATE_CON70_CLK_DDR_TIMER1_EN_MASK (0x1U << CRU_GATE_CON70_CLK_DDR_TIMER1_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON70_TCLK_WDT_DDR_EN_SHIFT (2U) +#define CRU_GATE_CON70_TCLK_WDT_DDR_EN_MASK (0x1U << CRU_GATE_CON70_TCLK_WDT_DDR_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON70_CLK_DDR_CM0_RTC_EN_SHIFT (4U) +#define CRU_GATE_CON70_CLK_DDR_CM0_RTC_EN_MASK (0x1U << CRU_GATE_CON70_CLK_DDR_CM0_RTC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON70_PCLK_CENTER_GRF_EN_SHIFT (5U) +#define CRU_GATE_CON70_PCLK_CENTER_GRF_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_CENTER_GRF_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON70_PCLK_AHB2APB_EN_SHIFT (6U) +#define CRU_GATE_CON70_PCLK_AHB2APB_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_AHB2APB_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON70_PCLK_WDT_EN_SHIFT (7U) +#define CRU_GATE_CON70_PCLK_WDT_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_WDT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON70_PCLK_TIMER_EN_SHIFT (8U) +#define CRU_GATE_CON70_PCLK_TIMER_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_TIMER_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON70_PCLK_DMA2DDR_EN_SHIFT (9U) +#define CRU_GATE_CON70_PCLK_DMA2DDR_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_DMA2DDR_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON70_PCLK_SHAREMEM_EN_SHIFT (10U) +#define CRU_GATE_CON70_PCLK_SHAREMEM_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_SHAREMEM_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON70_PCLK_CENTER_BIU_EN_SHIFT (11U) +#define CRU_GATE_CON70_PCLK_CENTER_BIU_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_CENTER_BIU_EN_SHIFT) /* 0x00000800 */ +#define CRU_GATE_CON70_PCLK_CENTER_CHANNEL_BIU_EN_SHIFT (12U) +#define CRU_GATE_CON70_PCLK_CENTER_CHANNEL_BIU_EN_MASK (0x1U << CRU_GATE_CON70_PCLK_CENTER_CHANNEL_BIU_EN_SHIFT) /* 0x00001000 */ +/* GATE_CON72 */ +#define CRU_GATE_CON72_OFFSET (0x920U) +#define CRU_GATE_CON72_PCLK_USBDPGRF0_EN_SHIFT (1U) +#define CRU_GATE_CON72_PCLK_USBDPGRF0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USBDPGRF0_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON72_PCLK_USBDPPHY0_EN_SHIFT (2U) +#define CRU_GATE_CON72_PCLK_USBDPPHY0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USBDPPHY0_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON72_PCLK_USBDPGRF1_EN_SHIFT (3U) +#define CRU_GATE_CON72_PCLK_USBDPGRF1_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USBDPGRF1_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON72_PCLK_USBDPPHY1_EN_SHIFT (4U) +#define CRU_GATE_CON72_PCLK_USBDPPHY1_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USBDPPHY1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON72_PCLK_HDPTX0_EN_SHIFT (5U) +#define CRU_GATE_CON72_PCLK_HDPTX0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_HDPTX0_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON72_PCLK_HDPTX1_EN_SHIFT (6U) +#define CRU_GATE_CON72_PCLK_HDPTX1_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_HDPTX1_EN_SHIFT) /* 0x00000040 */ +#define CRU_GATE_CON72_PCLK_APB2ASB_SLV_BOT_RIGHT_EN_SHIFT (7U) +#define CRU_GATE_CON72_PCLK_APB2ASB_SLV_BOT_RIGHT_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_APB2ASB_SLV_BOT_RIGHT_EN_SHIFT) /* 0x00000080 */ +#define CRU_GATE_CON72_PCLK_USB2PHY_U3_0_GRF0_EN_SHIFT (8U) +#define CRU_GATE_CON72_PCLK_USB2PHY_U3_0_GRF0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USB2PHY_U3_0_GRF0_EN_SHIFT) /* 0x00000100 */ +#define CRU_GATE_CON72_PCLK_USB2PHY_U3_1_GRF0_EN_SHIFT (9U) +#define CRU_GATE_CON72_PCLK_USB2PHY_U3_1_GRF0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USB2PHY_U3_1_GRF0_EN_SHIFT) /* 0x00000200 */ +#define CRU_GATE_CON72_PCLK_USB2PHY_U2_0_GRF0_EN_SHIFT (10U) +#define CRU_GATE_CON72_PCLK_USB2PHY_U2_0_GRF0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USB2PHY_U2_0_GRF0_EN_SHIFT) /* 0x00000400 */ +#define CRU_GATE_CON72_PCLK_USB2PHY_U2_1_GRF0_EN_SHIFT (11U) +#define CRU_GATE_CON72_PCLK_USB2PHY_U2_1_GRF0_EN_MASK (0x1U << CRU_GATE_CON72_PCLK_USB2PHY_U2_1_GRF0_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON73 */ +#define CRU_GATE_CON73_OFFSET (0x924U) +#define CRU_GATE_CON73_CLK_HDMIHDP0_EN_SHIFT (12U) +#define CRU_GATE_CON73_CLK_HDMIHDP0_EN_MASK (0x1U << CRU_GATE_CON73_CLK_HDMIHDP0_EN_SHIFT) /* 0x00001000 */ +#define CRU_GATE_CON73_CLK_HDMIHDP1_EN_SHIFT (13U) +#define CRU_GATE_CON73_CLK_HDMIHDP1_EN_MASK (0x1U << CRU_GATE_CON73_CLK_HDMIHDP1_EN_SHIFT) /* 0x00002000 */ +/* GATE_CON74 */ +#define CRU_GATE_CON74_OFFSET (0x928U) +#define CRU_GATE_CON74_ACLK_VO1USB_TOP_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON74_ACLK_VO1USB_TOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON74_ACLK_VO1USB_TOP_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON74_ACLK_VO1USB_TOP_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON74_ACLK_VO1USB_TOP_BIU_EN_MASK (0x1U << CRU_GATE_CON74_ACLK_VO1USB_TOP_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON74_HCLK_VO1USB_TOP_ROOT_EN_SHIFT (2U) +#define CRU_GATE_CON74_HCLK_VO1USB_TOP_ROOT_EN_MASK (0x1U << CRU_GATE_CON74_HCLK_VO1USB_TOP_ROOT_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON74_HCLK_VO1USB_TOP_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON74_HCLK_VO1USB_TOP_BIU_EN_MASK (0x1U << CRU_GATE_CON74_HCLK_VO1USB_TOP_BIU_EN_SHIFT) /* 0x00000008 */ +/* GATE_CON75 */ +#define CRU_GATE_CON75_OFFSET (0x92CU) +#define CRU_GATE_CON75_HCLK_SDIO_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON75_HCLK_SDIO_ROOT_EN_MASK (0x1U << CRU_GATE_CON75_HCLK_SDIO_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON75_HCLK_SDIO_BIU_EN_SHIFT (1U) +#define CRU_GATE_CON75_HCLK_SDIO_BIU_EN_MASK (0x1U << CRU_GATE_CON75_HCLK_SDIO_BIU_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON75_HCLK_SDIO_EN_SHIFT (2U) +#define CRU_GATE_CON75_HCLK_SDIO_EN_MASK (0x1U << CRU_GATE_CON75_HCLK_SDIO_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON75_CCLK_SRC_SDIO_EN_SHIFT (3U) +#define CRU_GATE_CON75_CCLK_SRC_SDIO_EN_MASK (0x1U << CRU_GATE_CON75_CCLK_SRC_SDIO_EN_SHIFT) /* 0x00000008 */ +/* GATE_CON76 */ +#define CRU_GATE_CON76_OFFSET (0x930U) +#define CRU_GATE_CON76_ACLK_RGA3_ROOT_EN_SHIFT (0U) +#define CRU_GATE_CON76_ACLK_RGA3_ROOT_EN_MASK (0x1U << CRU_GATE_CON76_ACLK_RGA3_ROOT_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON76_HCLK_RGA3_ROOT_EN_SHIFT (1U) +#define CRU_GATE_CON76_HCLK_RGA3_ROOT_EN_MASK (0x1U << CRU_GATE_CON76_HCLK_RGA3_ROOT_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON76_HCLK_RGA3_BIU_EN_SHIFT (2U) +#define CRU_GATE_CON76_HCLK_RGA3_BIU_EN_MASK (0x1U << CRU_GATE_CON76_HCLK_RGA3_BIU_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON76_ACLK_RGA3_BIU_EN_SHIFT (3U) +#define CRU_GATE_CON76_ACLK_RGA3_BIU_EN_MASK (0x1U << CRU_GATE_CON76_ACLK_RGA3_BIU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON76_HCLK_RGA3_1_EN_SHIFT (4U) +#define CRU_GATE_CON76_HCLK_RGA3_1_EN_MASK (0x1U << CRU_GATE_CON76_HCLK_RGA3_1_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON76_ACLK_RGA3_1_EN_SHIFT (5U) +#define CRU_GATE_CON76_ACLK_RGA3_1_EN_MASK (0x1U << CRU_GATE_CON76_ACLK_RGA3_1_EN_SHIFT) /* 0x00000020 */ +#define CRU_GATE_CON76_CLK_RGA3_1_CORE_EN_SHIFT (6U) +#define CRU_GATE_CON76_CLK_RGA3_1_CORE_EN_MASK (0x1U << CRU_GATE_CON76_CLK_RGA3_1_CORE_EN_SHIFT) /* 0x00000040 */ +/* GATE_CON77 */ +#define CRU_GATE_CON77_OFFSET (0x934U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY0_OSC_SRC_EN_SHIFT (0U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY0_OSC_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY0_OSC_SRC_EN_SHIFT) /* 0x00000001 */ +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY1_OSC_SRC_EN_SHIFT (1U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY1_OSC_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY1_OSC_SRC_EN_SHIFT) /* 0x00000002 */ +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY2_OSC_SRC_EN_SHIFT (2U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY2_OSC_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY2_OSC_SRC_EN_SHIFT) /* 0x00000004 */ +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY0_PLL_SRC_EN_SHIFT (3U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY0_PLL_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY0_PLL_SRC_EN_SHIFT) /* 0x00000008 */ +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY1_PLL_SRC_EN_SHIFT (4U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY1_PLL_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY1_PLL_SRC_EN_SHIFT) /* 0x00000010 */ +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY2_PLL_SRC_EN_SHIFT (5U) +#define CRU_GATE_CON77_CLK_REF_PIPE_PHY2_PLL_SRC_EN_MASK (0x1U << CRU_GATE_CON77_CLK_REF_PIPE_PHY2_PLL_SRC_EN_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON01 */ +#define CRU_SOFTRST_CON01_OFFSET (0xA04U) +#define CRU_SOFTRST_CON01_ARESETN_TOP_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON01_ARESETN_TOP_BIU_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_TOP_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON01_PRESETN_TOP_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON01_PRESETN_TOP_BIU_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_TOP_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON01_PRESETN_CSIPHY0_SHIFT (6U) +#define CRU_SOFTRST_CON01_PRESETN_CSIPHY0_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CSIPHY0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON01_PRESETN_CSIPHY1_SHIFT (8U) +#define CRU_SOFTRST_CON01_PRESETN_CSIPHY1_MASK (0x1U << CRU_SOFTRST_CON01_PRESETN_CSIPHY1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON01_ARESETN_TOP_M500_BIU_SHIFT (15U) +#define CRU_SOFTRST_CON01_ARESETN_TOP_M500_BIU_MASK (0x1U << CRU_SOFTRST_CON01_ARESETN_TOP_M500_BIU_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON02 */ +#define CRU_SOFTRST_CON02_OFFSET (0xA08U) +#define CRU_SOFTRST_CON02_ARESETN_TOP_M400_BIU_SHIFT (0U) +#define CRU_SOFTRST_CON02_ARESETN_TOP_M400_BIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_TOP_M400_BIU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON02_ARESETN_TOP_S200_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON02_ARESETN_TOP_S200_BIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_TOP_S200_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON02_ARESETN_TOP_S400_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON02_ARESETN_TOP_S400_BIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_TOP_S400_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON02_ARESETN_TOP_M300_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON02_ARESETN_TOP_M300_BIU_MASK (0x1U << CRU_SOFTRST_CON02_ARESETN_TOP_M300_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_INIT_SHIFT (8U) +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_INIT_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_INIT_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_CMN_SHIFT (9U) +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_CMN_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_CMN_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_LANE_SHIFT (10U) +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_LANE_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_LANE_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_PCS_SHIFT (11U) +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_PCS_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY0_PCS_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY1_INIT_SHIFT (15U) +#define CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY1_INIT_MASK (0x1U << CRU_SOFTRST_CON02_RESETN_USBDP_COMBO_PHY1_INIT_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON03 */ +#define CRU_SOFTRST_CON03_OFFSET (0xA0CU) +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_CMN_SHIFT (0U) +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_CMN_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_CMN_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_LANE_SHIFT (1U) +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_LANE_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_LANE_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_PCS_SHIFT (2U) +#define CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_PCS_MASK (0x1U << CRU_SOFTRST_CON03_RESETN_USBDP_COMBO_PHY1_PCS_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_SHIFT (14U) +#define CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_GRF_SHIFT (15U) +#define CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_GRF_MASK (0x1U << CRU_SOFTRST_CON03_PRESETN_MIPI_DCPHY0_GRF_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON04 */ +#define CRU_SOFTRST_CON04_OFFSET (0xA10U) +#define CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_SHIFT (3U) +#define CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_GRF_SHIFT (4U) +#define CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_GRF_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_MIPI_DCPHY1_GRF_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CDPHY_SHIFT (5U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CDPHY_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CDPHY_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CSIPHY_SHIFT (6U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CSIPHY_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_CSIPHY_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO3_5_SHIFT (7U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO3_5_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO3_5_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO6_SHIFT (8U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO6_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_VCCIO6_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_EMMCIO_SHIFT (9U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_EMMCIO_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_EMMCIO_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_TOP_SHIFT (10U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_TOP_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_TOP_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_RIGHT_SHIFT (11U) +#define CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_RIGHT_MASK (0x1U << CRU_SOFTRST_CON04_PRESETN_APB2ASB_SLV_IOC_RIGHT_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON05 */ +#define CRU_SOFTRST_CON05_OFFSET (0xA14U) +#define CRU_SOFTRST_CON05_PRESETN_CRU_SHIFT (0U) +#define CRU_SOFTRST_CON05_PRESETN_CRU_MASK (0x1U << CRU_SOFTRST_CON05_PRESETN_CRU_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2VO1USB_SHIFT (7U) +#define CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2VO1USB_MASK (0x1U << CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2VO1USB_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2CENTER_SHIFT (8U) +#define CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2CENTER_MASK (0x1U << CRU_SOFTRST_CON05_ARESETN_CHANNEL_SECURE2CENTER_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2VO1USB_SHIFT (14U) +#define CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2VO1USB_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2VO1USB_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2CENTER_SHIFT (15U) +#define CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2CENTER_MASK (0x1U << CRU_SOFTRST_CON05_HRESETN_CHANNEL_SECURE2CENTER_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON06 */ +#define CRU_SOFTRST_CON06_OFFSET (0xA18U) +#define CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2VO1USB_SHIFT (0U) +#define CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2VO1USB_MASK (0x1U << CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2VO1USB_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2CENTER_SHIFT (1U) +#define CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2CENTER_MASK (0x1U << CRU_SOFTRST_CON06_PRESETN_CHANNEL_SECURE2CENTER_SHIFT) /* 0x00000002 */ +/* SOFTRST_CON07 */ +#define CRU_SOFTRST_CON07_OFFSET (0xA1CU) +#define CRU_SOFTRST_CON07_HRESETN_AUDIO_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON07_HRESETN_AUDIO_BIU_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_AUDIO_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON07_PRESETN_AUDIO_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON07_PRESETN_AUDIO_BIU_MASK (0x1U << CRU_SOFTRST_CON07_PRESETN_AUDIO_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON07_HRESETN_I2S0_8CH_SHIFT (4U) +#define CRU_SOFTRST_CON07_HRESETN_I2S0_8CH_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_I2S0_8CH_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_TX_SHIFT (7U) +#define CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_TX_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_RX_SHIFT (10U) +#define CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON07_MRESETN_I2S0_8CH_RX_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON07_PRESETN_ACDCDIG_SHIFT (11U) +#define CRU_SOFTRST_CON07_PRESETN_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON07_PRESETN_ACDCDIG_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON07_HRESETN_I2S2_2CH_SHIFT (12U) +#define CRU_SOFTRST_CON07_HRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_I2S2_2CH_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON07_HRESETN_I2S3_2CH_SHIFT (13U) +#define CRU_SOFTRST_CON07_HRESETN_I2S3_2CH_MASK (0x1U << CRU_SOFTRST_CON07_HRESETN_I2S3_2CH_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON08 */ +#define CRU_SOFTRST_CON08_OFFSET (0xA20U) +#define CRU_SOFTRST_CON08_MRESETN_I2S2_2CH_SHIFT (0U) +#define CRU_SOFTRST_CON08_MRESETN_I2S2_2CH_MASK (0x1U << CRU_SOFTRST_CON08_MRESETN_I2S2_2CH_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON08_MRESETN_I2S3_2CH_SHIFT (3U) +#define CRU_SOFTRST_CON08_MRESETN_I2S3_2CH_MASK (0x1U << CRU_SOFTRST_CON08_MRESETN_I2S3_2CH_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON08_RESETN_DAC_ACDCDIG_SHIFT (4U) +#define CRU_SOFTRST_CON08_RESETN_DAC_ACDCDIG_MASK (0x1U << CRU_SOFTRST_CON08_RESETN_DAC_ACDCDIG_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON08_HRESETN_SPDIF0_SHIFT (14U) +#define CRU_SOFTRST_CON08_HRESETN_SPDIF0_MASK (0x1U << CRU_SOFTRST_CON08_HRESETN_SPDIF0_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON09 */ +#define CRU_SOFTRST_CON09_OFFSET (0xA24U) +#define CRU_SOFTRST_CON09_MRESETN_SPDIF0_SHIFT (1U) +#define CRU_SOFTRST_CON09_MRESETN_SPDIF0_MASK (0x1U << CRU_SOFTRST_CON09_MRESETN_SPDIF0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON09_HRESETN_SPDIF1_SHIFT (2U) +#define CRU_SOFTRST_CON09_HRESETN_SPDIF1_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_SPDIF1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON09_MRESETN_SPDIF1_SHIFT (5U) +#define CRU_SOFTRST_CON09_MRESETN_SPDIF1_MASK (0x1U << CRU_SOFTRST_CON09_MRESETN_SPDIF1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON09_HRESETN_PDM1_SHIFT (6U) +#define CRU_SOFTRST_CON09_HRESETN_PDM1_MASK (0x1U << CRU_SOFTRST_CON09_HRESETN_PDM1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON09_RESETN_PDM1_SHIFT (7U) +#define CRU_SOFTRST_CON09_RESETN_PDM1_MASK (0x1U << CRU_SOFTRST_CON09_RESETN_PDM1_SHIFT) /* 0x00000080 */ +/* SOFTRST_CON10 */ +#define CRU_SOFTRST_CON10_OFFSET (0xA28U) +#define CRU_SOFTRST_CON10_ARESETN_BUS_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON10_ARESETN_BUS_BIU_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_BUS_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON10_PRESETN_BUS_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON10_PRESETN_BUS_BIU_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_BUS_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON10_ARESETN_GIC_SHIFT (3U) +#define CRU_SOFTRST_CON10_ARESETN_GIC_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_GIC_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON10_ARESETN_GIC_DBG_SHIFT (4U) +#define CRU_SOFTRST_CON10_ARESETN_GIC_DBG_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_GIC_DBG_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON10_ARESETN_DMAC0_SHIFT (5U) +#define CRU_SOFTRST_CON10_ARESETN_DMAC0_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_DMAC0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON10_ARESETN_DMAC1_SHIFT (6U) +#define CRU_SOFTRST_CON10_ARESETN_DMAC1_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_DMAC1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON10_ARESETN_DMAC2_SHIFT (7U) +#define CRU_SOFTRST_CON10_ARESETN_DMAC2_MASK (0x1U << CRU_SOFTRST_CON10_ARESETN_DMAC2_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C1_SHIFT (8U) +#define CRU_SOFTRST_CON10_PRESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C2_SHIFT (9U) +#define CRU_SOFTRST_CON10_PRESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C2_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C3_SHIFT (10U) +#define CRU_SOFTRST_CON10_PRESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C3_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C4_SHIFT (11U) +#define CRU_SOFTRST_CON10_PRESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C4_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C5_SHIFT (12U) +#define CRU_SOFTRST_CON10_PRESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C5_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C6_SHIFT (13U) +#define CRU_SOFTRST_CON10_PRESETN_I2C6_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C6_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C7_SHIFT (14U) +#define CRU_SOFTRST_CON10_PRESETN_I2C7_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C7_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON10_PRESETN_I2C8_SHIFT (15U) +#define CRU_SOFTRST_CON10_PRESETN_I2C8_MASK (0x1U << CRU_SOFTRST_CON10_PRESETN_I2C8_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON11 */ +#define CRU_SOFTRST_CON11_OFFSET (0xA2CU) +#define CRU_SOFTRST_CON11_RESETN_I2C1_SHIFT (0U) +#define CRU_SOFTRST_CON11_RESETN_I2C1_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON11_RESETN_I2C2_SHIFT (1U) +#define CRU_SOFTRST_CON11_RESETN_I2C2_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON11_RESETN_I2C3_SHIFT (2U) +#define CRU_SOFTRST_CON11_RESETN_I2C3_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON11_RESETN_I2C4_SHIFT (3U) +#define CRU_SOFTRST_CON11_RESETN_I2C4_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C4_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON11_RESETN_I2C5_SHIFT (4U) +#define CRU_SOFTRST_CON11_RESETN_I2C5_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C5_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON11_RESETN_I2C6_SHIFT (5U) +#define CRU_SOFTRST_CON11_RESETN_I2C6_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C6_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON11_RESETN_I2C7_SHIFT (6U) +#define CRU_SOFTRST_CON11_RESETN_I2C7_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C7_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON11_RESETN_I2C8_SHIFT (7U) +#define CRU_SOFTRST_CON11_RESETN_I2C8_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_I2C8_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON11_PRESETN_CAN0_SHIFT (8U) +#define CRU_SOFTRST_CON11_PRESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_CAN0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON11_RESETN_CAN0_SHIFT (9U) +#define CRU_SOFTRST_CON11_RESETN_CAN0_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_CAN0_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON11_PRESETN_CAN1_SHIFT (10U) +#define CRU_SOFTRST_CON11_PRESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_CAN1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON11_RESETN_CAN1_SHIFT (11U) +#define CRU_SOFTRST_CON11_RESETN_CAN1_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_CAN1_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON11_PRESETN_CAN2_SHIFT (12U) +#define CRU_SOFTRST_CON11_PRESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_CAN2_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON11_RESETN_CAN2_SHIFT (13U) +#define CRU_SOFTRST_CON11_RESETN_CAN2_MASK (0x1U << CRU_SOFTRST_CON11_RESETN_CAN2_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON11_PRESETN_SARADC_SHIFT (14U) +#define CRU_SOFTRST_CON11_PRESETN_SARADC_MASK (0x1U << CRU_SOFTRST_CON11_PRESETN_SARADC_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON12 */ +#define CRU_SOFTRST_CON12_OFFSET (0xA30U) +#define CRU_SOFTRST_CON12_PRESETN_TSADC_SHIFT (0U) +#define CRU_SOFTRST_CON12_PRESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_TSADC_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON12_RESETN_TSADC_SHIFT (1U) +#define CRU_SOFTRST_CON12_RESETN_TSADC_MASK (0x1U << CRU_SOFTRST_CON12_RESETN_TSADC_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON12_PRESETN_UART1_SHIFT (2U) +#define CRU_SOFTRST_CON12_PRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON12_PRESETN_UART2_SHIFT (3U) +#define CRU_SOFTRST_CON12_PRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART2_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON12_PRESETN_UART3_SHIFT (4U) +#define CRU_SOFTRST_CON12_PRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART3_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON12_PRESETN_UART4_SHIFT (5U) +#define CRU_SOFTRST_CON12_PRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART4_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON12_PRESETN_UART5_SHIFT (6U) +#define CRU_SOFTRST_CON12_PRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART5_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON12_PRESETN_UART6_SHIFT (7U) +#define CRU_SOFTRST_CON12_PRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART6_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON12_PRESETN_UART7_SHIFT (8U) +#define CRU_SOFTRST_CON12_PRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART7_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON12_PRESETN_UART8_SHIFT (9U) +#define CRU_SOFTRST_CON12_PRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART8_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON12_PRESETN_UART9_SHIFT (10U) +#define CRU_SOFTRST_CON12_PRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON12_PRESETN_UART9_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON12_SRESETN_UART1_SHIFT (13U) +#define CRU_SOFTRST_CON12_SRESETN_UART1_MASK (0x1U << CRU_SOFTRST_CON12_SRESETN_UART1_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON13 */ +#define CRU_SOFTRST_CON13_OFFSET (0xA34U) +#define CRU_SOFTRST_CON13_SRESETN_UART2_SHIFT (0U) +#define CRU_SOFTRST_CON13_SRESETN_UART2_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON13_SRESETN_UART3_SHIFT (3U) +#define CRU_SOFTRST_CON13_SRESETN_UART3_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON13_SRESETN_UART4_SHIFT (6U) +#define CRU_SOFTRST_CON13_SRESETN_UART4_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART4_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON13_SRESETN_UART5_SHIFT (9U) +#define CRU_SOFTRST_CON13_SRESETN_UART5_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART5_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON13_SRESETN_UART6_SHIFT (12U) +#define CRU_SOFTRST_CON13_SRESETN_UART6_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART6_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON13_SRESETN_UART7_SHIFT (15U) +#define CRU_SOFTRST_CON13_SRESETN_UART7_MASK (0x1U << CRU_SOFTRST_CON13_SRESETN_UART7_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON14 */ +#define CRU_SOFTRST_CON14_OFFSET (0xA38U) +#define CRU_SOFTRST_CON14_SRESETN_UART8_SHIFT (2U) +#define CRU_SOFTRST_CON14_SRESETN_UART8_MASK (0x1U << CRU_SOFTRST_CON14_SRESETN_UART8_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON14_SRESETN_UART9_SHIFT (5U) +#define CRU_SOFTRST_CON14_SRESETN_UART9_MASK (0x1U << CRU_SOFTRST_CON14_SRESETN_UART9_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON14_PRESETN_SPI0_SHIFT (6U) +#define CRU_SOFTRST_CON14_PRESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_SPI0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON14_PRESETN_SPI1_SHIFT (7U) +#define CRU_SOFTRST_CON14_PRESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_SPI1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON14_PRESETN_SPI2_SHIFT (8U) +#define CRU_SOFTRST_CON14_PRESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_SPI2_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON14_PRESETN_SPI3_SHIFT (9U) +#define CRU_SOFTRST_CON14_PRESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_SPI3_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON14_PRESETN_SPI4_SHIFT (10U) +#define CRU_SOFTRST_CON14_PRESETN_SPI4_MASK (0x1U << CRU_SOFTRST_CON14_PRESETN_SPI4_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON14_RESETN_SPI0_SHIFT (11U) +#define CRU_SOFTRST_CON14_RESETN_SPI0_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SPI0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON14_RESETN_SPI1_SHIFT (12U) +#define CRU_SOFTRST_CON14_RESETN_SPI1_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SPI1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON14_RESETN_SPI2_SHIFT (13U) +#define CRU_SOFTRST_CON14_RESETN_SPI2_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SPI2_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON14_RESETN_SPI3_SHIFT (14U) +#define CRU_SOFTRST_CON14_RESETN_SPI3_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SPI3_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON14_RESETN_SPI4_SHIFT (15U) +#define CRU_SOFTRST_CON14_RESETN_SPI4_MASK (0x1U << CRU_SOFTRST_CON14_RESETN_SPI4_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON15 */ +#define CRU_SOFTRST_CON15_OFFSET (0xA3CU) +#define CRU_SOFTRST_CON15_PRESETN_WDT0_SHIFT (0U) +#define CRU_SOFTRST_CON15_PRESETN_WDT0_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_WDT0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON15_TRESETN_WDT0_SHIFT (1U) +#define CRU_SOFTRST_CON15_TRESETN_WDT0_MASK (0x1U << CRU_SOFTRST_CON15_TRESETN_WDT0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON15_PRESETN_SYS_GRF_SHIFT (2U) +#define CRU_SOFTRST_CON15_PRESETN_SYS_GRF_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_SYS_GRF_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON15_PRESETN_PWM1_SHIFT (3U) +#define CRU_SOFTRST_CON15_PRESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_PWM1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON15_RESETN_PWM1_SHIFT (4U) +#define CRU_SOFTRST_CON15_RESETN_PWM1_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_PWM1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON15_PRESETN_PWM2_SHIFT (6U) +#define CRU_SOFTRST_CON15_PRESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_PWM2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON15_RESETN_PWM2_SHIFT (7U) +#define CRU_SOFTRST_CON15_RESETN_PWM2_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_PWM2_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON15_PRESETN_PWM3_SHIFT (9U) +#define CRU_SOFTRST_CON15_PRESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_PWM3_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON15_RESETN_PWM3_SHIFT (10U) +#define CRU_SOFTRST_CON15_RESETN_PWM3_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_PWM3_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON15_PRESETN_BUSTIMER0_SHIFT (12U) +#define CRU_SOFTRST_CON15_PRESETN_BUSTIMER0_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_BUSTIMER0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON15_PRESETN_BUSTIMER1_SHIFT (13U) +#define CRU_SOFTRST_CON15_PRESETN_BUSTIMER1_MASK (0x1U << CRU_SOFTRST_CON15_PRESETN_BUSTIMER1_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON15_RESETN_BUSTIMER0_SHIFT (15U) +#define CRU_SOFTRST_CON15_RESETN_BUSTIMER0_MASK (0x1U << CRU_SOFTRST_CON15_RESETN_BUSTIMER0_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON16 */ +#define CRU_SOFTRST_CON16_OFFSET (0xA40U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER1_SHIFT (0U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER1_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER2_SHIFT (1U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER2_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER3_SHIFT (2U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER3_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER4_SHIFT (3U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER4_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER4_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER5_SHIFT (4U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER5_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER5_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER6_SHIFT (5U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER6_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER6_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER7_SHIFT (6U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER7_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER7_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER8_SHIFT (7U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER8_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER8_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER9_SHIFT (8U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER9_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER9_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER10_SHIFT (9U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER10_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER10_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER11_SHIFT (10U) +#define CRU_SOFTRST_CON16_RESETN_BUSTIMER11_MASK (0x1U << CRU_SOFTRST_CON16_RESETN_BUSTIMER11_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX0_SHIFT (11U) +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX0_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_MAILBOX0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX1_SHIFT (12U) +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX1_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_MAILBOX1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX2_SHIFT (13U) +#define CRU_SOFTRST_CON16_PRESETN_MAILBOX2_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_MAILBOX2_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON16_PRESETN_GPIO1_SHIFT (14U) +#define CRU_SOFTRST_CON16_PRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON16_PRESETN_GPIO1_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON16_DBRESETN_GPIO1_SHIFT (15U) +#define CRU_SOFTRST_CON16_DBRESETN_GPIO1_MASK (0x1U << CRU_SOFTRST_CON16_DBRESETN_GPIO1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON17 */ +#define CRU_SOFTRST_CON17_OFFSET (0xA44U) +#define CRU_SOFTRST_CON17_PRESETN_GPIO2_SHIFT (0U) +#define CRU_SOFTRST_CON17_PRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_GPIO2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON17_DBRESETN_GPIO2_SHIFT (1U) +#define CRU_SOFTRST_CON17_DBRESETN_GPIO2_MASK (0x1U << CRU_SOFTRST_CON17_DBRESETN_GPIO2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON17_PRESETN_GPIO3_SHIFT (2U) +#define CRU_SOFTRST_CON17_PRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_GPIO3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON17_DBRESETN_GPIO3_SHIFT (3U) +#define CRU_SOFTRST_CON17_DBRESETN_GPIO3_MASK (0x1U << CRU_SOFTRST_CON17_DBRESETN_GPIO3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON17_PRESETN_GPIO4_SHIFT (4U) +#define CRU_SOFTRST_CON17_PRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_GPIO4_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON17_DBRESETN_GPIO4_SHIFT (5U) +#define CRU_SOFTRST_CON17_DBRESETN_GPIO4_MASK (0x1U << CRU_SOFTRST_CON17_DBRESETN_GPIO4_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON17_ARESETN_DECOM_SHIFT (6U) +#define CRU_SOFTRST_CON17_ARESETN_DECOM_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_DECOM_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON17_PRESETN_DECOM_SHIFT (7U) +#define CRU_SOFTRST_CON17_PRESETN_DECOM_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DECOM_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON17_DRESETN_DECOM_SHIFT (8U) +#define CRU_SOFTRST_CON17_DRESETN_DECOM_MASK (0x1U << CRU_SOFTRST_CON17_DRESETN_DECOM_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON17_PRESETN_TOP_SHIFT (9U) +#define CRU_SOFTRST_CON17_PRESETN_TOP_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_TOP_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON17_ARESETN_GICADB_GIC2CORE_BUS_SHIFT (11U) +#define CRU_SOFTRST_CON17_ARESETN_GICADB_GIC2CORE_BUS_MASK (0x1U << CRU_SOFTRST_CON17_ARESETN_GICADB_GIC2CORE_BUS_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON17_PRESETN_DFT2APB_SHIFT (12U) +#define CRU_SOFTRST_CON17_PRESETN_DFT2APB_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_DFT2APB_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_TOP_SHIFT (13U) +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_TOP_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_TOP_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_CDPHY_SHIFT (14U) +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_CDPHY_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_CDPHY_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_BOT_RIGHT_SHIFT (15U) +#define CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_BOT_RIGHT_MASK (0x1U << CRU_SOFTRST_CON17_PRESETN_APB2ASB_MST_BOT_RIGHT_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON18 */ +#define CRU_SOFTRST_CON18_OFFSET (0xA48U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_TOP_SHIFT (0U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_TOP_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_TOP_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_RIGHT_SHIFT (1U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_RIGHT_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_IOC_RIGHT_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_CSIPHY_SHIFT (2U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_CSIPHY_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_CSIPHY_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO3_5_SHIFT (3U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO3_5_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO3_5_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO6_SHIFT (4U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO6_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_VCCIO6_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_EMMCIO_SHIFT (5U) +#define CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_EMMCIO_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_APB2ASB_MST_EMMCIO_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON18_ARESETN_SPINLOCK_SHIFT (6U) +#define CRU_SOFTRST_CON18_ARESETN_SPINLOCK_MASK (0x1U << CRU_SOFTRST_CON18_ARESETN_SPINLOCK_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON18_PRESETN_OTPC_NS_SHIFT (9U) +#define CRU_SOFTRST_CON18_PRESETN_OTPC_NS_MASK (0x1U << CRU_SOFTRST_CON18_PRESETN_OTPC_NS_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON18_RESETN_OTPC_NS_SHIFT (10U) +#define CRU_SOFTRST_CON18_RESETN_OTPC_NS_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_OTPC_NS_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON18_RESETN_OTPC_ARB_SHIFT (11U) +#define CRU_SOFTRST_CON18_RESETN_OTPC_ARB_MASK (0x1U << CRU_SOFTRST_CON18_RESETN_OTPC_ARB_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON19 */ +#define CRU_SOFTRST_CON19_OFFSET (0xA4CU) +#define CRU_SOFTRST_CON19_PRESETN_BUSIOC_SHIFT (0U) +#define CRU_SOFTRST_CON19_PRESETN_BUSIOC_MASK (0x1U << CRU_SOFTRST_CON19_PRESETN_BUSIOC_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON19_PRESETN_PMUCM0_INTMUX_SHIFT (4U) +#define CRU_SOFTRST_CON19_PRESETN_PMUCM0_INTMUX_MASK (0x1U << CRU_SOFTRST_CON19_PRESETN_PMUCM0_INTMUX_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON19_PRESETN_DDRCM0_INTMUX_SHIFT (5U) +#define CRU_SOFTRST_CON19_PRESETN_DDRCM0_INTMUX_MASK (0x1U << CRU_SOFTRST_CON19_PRESETN_DDRCM0_INTMUX_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON20 */ +#define CRU_SOFTRST_CON20_OFFSET (0xA50U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH0_SHIFT (0U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH0_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH0_SHIFT (1U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH0_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH0_SHIFT (2U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH0_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH0_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_UPCTL_CH0_SHIFT (3U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_UPCTL_CH0_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_UPCTL_CH0_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON20_TMRESETN_DDR_MON_CH0_SHIFT (4U) +#define CRU_SOFTRST_CON20_TMRESETN_DDR_MON_CH0_MASK (0x1U << CRU_SOFTRST_CON20_TMRESETN_DDR_MON_CH0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_GRF_CH01_SHIFT (5U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_GRF_CH01_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_GRF_CH01_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON20_RESETN_DFI_CH0_SHIFT (6U) +#define CRU_SOFTRST_CON20_RESETN_DFI_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_DFI_CH0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON20_RESETN_SBR_CH0_SHIFT (7U) +#define CRU_SOFTRST_CON20_RESETN_SBR_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_SBR_CH0_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON20_RESETN_DDR_UPCTL_CH0_SHIFT (8U) +#define CRU_SOFTRST_CON20_RESETN_DDR_UPCTL_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_DDR_UPCTL_CH0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON20_RESETN_DDR_DFICTL_CH0_SHIFT (9U) +#define CRU_SOFTRST_CON20_RESETN_DDR_DFICTL_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_DDR_DFICTL_CH0_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON20_RESETN_DDR_MON_CH0_SHIFT (10U) +#define CRU_SOFTRST_CON20_RESETN_DDR_MON_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_DDR_MON_CH0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON20_RESETN_DDR_STANDBY_CH0_SHIFT (11U) +#define CRU_SOFTRST_CON20_RESETN_DDR_STANDBY_CH0_MASK (0x1U << CRU_SOFTRST_CON20_RESETN_DDR_STANDBY_CH0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON20_ARESETN_DDR_UPCTL_CH0_SHIFT (12U) +#define CRU_SOFTRST_CON20_ARESETN_DDR_UPCTL_CH0_MASK (0x1U << CRU_SOFTRST_CON20_ARESETN_DDR_UPCTL_CH0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH1_SHIFT (13U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH1_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_DFICTL_CH1_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH1_SHIFT (14U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH1_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_MON_CH1_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH1_SHIFT (15U) +#define CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH1_MASK (0x1U << CRU_SOFTRST_CON20_PRESETN_DDR_STANDBY_CH1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON21 */ +#define CRU_SOFTRST_CON21_OFFSET (0xA54U) +#define CRU_SOFTRST_CON21_PRESETN_DDR_UPCTL_CH1_SHIFT (0U) +#define CRU_SOFTRST_CON21_PRESETN_DDR_UPCTL_CH1_MASK (0x1U << CRU_SOFTRST_CON21_PRESETN_DDR_UPCTL_CH1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON21_TMRESETN_DDR_MON_CH1_SHIFT (1U) +#define CRU_SOFTRST_CON21_TMRESETN_DDR_MON_CH1_MASK (0x1U << CRU_SOFTRST_CON21_TMRESETN_DDR_MON_CH1_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON21_RESETN_DFI_CH1_SHIFT (2U) +#define CRU_SOFTRST_CON21_RESETN_DFI_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_DFI_CH1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON21_RESETN_SBR_CH1_SHIFT (3U) +#define CRU_SOFTRST_CON21_RESETN_SBR_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_SBR_CH1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON21_RESETN_DDR_UPCTL_CH1_SHIFT (4U) +#define CRU_SOFTRST_CON21_RESETN_DDR_UPCTL_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_DDR_UPCTL_CH1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON21_RESETN_DDR_DFICTL_CH1_SHIFT (5U) +#define CRU_SOFTRST_CON21_RESETN_DDR_DFICTL_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_DDR_DFICTL_CH1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON21_RESETN_DDR_MON_CH1_SHIFT (6U) +#define CRU_SOFTRST_CON21_RESETN_DDR_MON_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_DDR_MON_CH1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON21_RESETN_DDR_STANDBY_CH1_SHIFT (7U) +#define CRU_SOFTRST_CON21_RESETN_DDR_STANDBY_CH1_MASK (0x1U << CRU_SOFTRST_CON21_RESETN_DDR_STANDBY_CH1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON21_ARESETN_DDR_UPCTL_CH1_SHIFT (8U) +#define CRU_SOFTRST_CON21_ARESETN_DDR_UPCTL_CH1_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_DDR_UPCTL_CH1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON21_ARESETN_DDR_DDRSCH0_SHIFT (13U) +#define CRU_SOFTRST_CON21_ARESETN_DDR_DDRSCH0_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_DDR_DDRSCH0_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON21_ARESETN_DDR_RS_DDRSCH0_SHIFT (14U) +#define CRU_SOFTRST_CON21_ARESETN_DDR_RS_DDRSCH0_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_DDR_RS_DDRSCH0_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON21_ARESETN_DDR_FRS_DDRSCH0_SHIFT (15U) +#define CRU_SOFTRST_CON21_ARESETN_DDR_FRS_DDRSCH0_MASK (0x1U << CRU_SOFTRST_CON21_ARESETN_DDR_FRS_DDRSCH0_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON22 */ +#define CRU_SOFTRST_CON22_OFFSET (0xA58U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE0_SHIFT (0U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE0_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE0_SHIFT (1U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE0_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_DDRSCH1_SHIFT (2U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_DDRSCH1_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_DDRSCH1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_RS_DDRSCH1_SHIFT (3U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_RS_DDRSCH1_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_RS_DDRSCH1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_DDRSCH1_SHIFT (4U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_DDRSCH1_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_FRS_DDRSCH1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE1_SHIFT (5U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE1_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_SCRAMBLE1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE1_SHIFT (6U) +#define CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE1_MASK (0x1U << CRU_SOFTRST_CON22_ARESETN_DDR_FRS_SCRAMBLE1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH0_SHIFT (7U) +#define CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH0_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH0_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH1_SHIFT (8U) +#define CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH1_MASK (0x1U << CRU_SOFTRST_CON22_PRESETN_DDR_DDRSCH1_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON23 */ +#define CRU_SOFTRST_CON23_OFFSET (0xA5CU) +#define CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH2_SHIFT (0U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH2_SHIFT (1U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH2_SHIFT (2U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH2_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_UPCTL_CH2_SHIFT (3U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_UPCTL_CH2_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_UPCTL_CH2_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON23_TMRESETN_DDR_MON_CH2_SHIFT (4U) +#define CRU_SOFTRST_CON23_TMRESETN_DDR_MON_CH2_MASK (0x1U << CRU_SOFTRST_CON23_TMRESETN_DDR_MON_CH2_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_GRF_CH23_SHIFT (5U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_GRF_CH23_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_GRF_CH23_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON23_RESETN_DFI_CH2_SHIFT (6U) +#define CRU_SOFTRST_CON23_RESETN_DFI_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_DFI_CH2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON23_RESETN_SBR_CH2_SHIFT (7U) +#define CRU_SOFTRST_CON23_RESETN_SBR_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_SBR_CH2_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON23_RESETN_DDR_UPCTL_CH2_SHIFT (8U) +#define CRU_SOFTRST_CON23_RESETN_DDR_UPCTL_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_DDR_UPCTL_CH2_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON23_RESETN_DDR_DFICTL_CH2_SHIFT (9U) +#define CRU_SOFTRST_CON23_RESETN_DDR_DFICTL_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_DDR_DFICTL_CH2_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON23_RESETN_DDR_MON_CH2_SHIFT (10U) +#define CRU_SOFTRST_CON23_RESETN_DDR_MON_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_DDR_MON_CH2_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON23_RESETN_DDR_STANDBY_CH2_SHIFT (11U) +#define CRU_SOFTRST_CON23_RESETN_DDR_STANDBY_CH2_MASK (0x1U << CRU_SOFTRST_CON23_RESETN_DDR_STANDBY_CH2_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON23_ARESETN_DDR_UPCTL_CH2_SHIFT (12U) +#define CRU_SOFTRST_CON23_ARESETN_DDR_UPCTL_CH2_MASK (0x1U << CRU_SOFTRST_CON23_ARESETN_DDR_UPCTL_CH2_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH3_SHIFT (13U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_DFICTL_CH3_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH3_SHIFT (14U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_MON_CH3_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH3_SHIFT (15U) +#define CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH3_MASK (0x1U << CRU_SOFTRST_CON23_PRESETN_DDR_STANDBY_CH3_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON24 */ +#define CRU_SOFTRST_CON24_OFFSET (0xA60U) +#define CRU_SOFTRST_CON24_PRESETN_DDR_UPCTL_CH3_SHIFT (0U) +#define CRU_SOFTRST_CON24_PRESETN_DDR_UPCTL_CH3_MASK (0x1U << CRU_SOFTRST_CON24_PRESETN_DDR_UPCTL_CH3_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON24_TMRESETN_DDR_MON_CH3_SHIFT (1U) +#define CRU_SOFTRST_CON24_TMRESETN_DDR_MON_CH3_MASK (0x1U << CRU_SOFTRST_CON24_TMRESETN_DDR_MON_CH3_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON24_RESETN_DFI_CH3_SHIFT (2U) +#define CRU_SOFTRST_CON24_RESETN_DFI_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_DFI_CH3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON24_RESETN_SBR_CH3_SHIFT (3U) +#define CRU_SOFTRST_CON24_RESETN_SBR_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_SBR_CH3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON24_RESETN_DDR_UPCTL_CH3_SHIFT (4U) +#define CRU_SOFTRST_CON24_RESETN_DDR_UPCTL_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_DDR_UPCTL_CH3_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON24_RESETN_DDR_DFICTL_CH3_SHIFT (5U) +#define CRU_SOFTRST_CON24_RESETN_DDR_DFICTL_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_DDR_DFICTL_CH3_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON24_RESETN_DDR_MON_CH3_SHIFT (6U) +#define CRU_SOFTRST_CON24_RESETN_DDR_MON_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_DDR_MON_CH3_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON24_RESETN_DDR_STANDBY_CH3_SHIFT (7U) +#define CRU_SOFTRST_CON24_RESETN_DDR_STANDBY_CH3_MASK (0x1U << CRU_SOFTRST_CON24_RESETN_DDR_STANDBY_CH3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON24_ARESETN_DDR_UPCTL_CH3_SHIFT (8U) +#define CRU_SOFTRST_CON24_ARESETN_DDR_UPCTL_CH3_MASK (0x1U << CRU_SOFTRST_CON24_ARESETN_DDR_UPCTL_CH3_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON24_ARESETN_DDR_DDRSCH2_SHIFT (13U) +#define CRU_SOFTRST_CON24_ARESETN_DDR_DDRSCH2_MASK (0x1U << CRU_SOFTRST_CON24_ARESETN_DDR_DDRSCH2_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON24_ARESETN_DDR_RS_DDRSCH2_SHIFT (14U) +#define CRU_SOFTRST_CON24_ARESETN_DDR_RS_DDRSCH2_MASK (0x1U << CRU_SOFTRST_CON24_ARESETN_DDR_RS_DDRSCH2_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON24_ARESETN_DDR_FRS_DDRSCH2_SHIFT (15U) +#define CRU_SOFTRST_CON24_ARESETN_DDR_FRS_DDRSCH2_MASK (0x1U << CRU_SOFTRST_CON24_ARESETN_DDR_FRS_DDRSCH2_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON25 */ +#define CRU_SOFTRST_CON25_OFFSET (0xA64U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE2_SHIFT (0U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE2_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE2_SHIFT (1U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE2_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_DDRSCH3_SHIFT (2U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_DDRSCH3_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_DDRSCH3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_RS_DDRSCH3_SHIFT (3U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_RS_DDRSCH3_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_RS_DDRSCH3_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_DDRSCH3_SHIFT (4U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_DDRSCH3_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_FRS_DDRSCH3_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE3_SHIFT (5U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE3_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_SCRAMBLE3_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE3_SHIFT (6U) +#define CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE3_MASK (0x1U << CRU_SOFTRST_CON25_ARESETN_DDR_FRS_SCRAMBLE3_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH2_SHIFT (7U) +#define CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH2_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH2_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH3_SHIFT (8U) +#define CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH3_MASK (0x1U << CRU_SOFTRST_CON25_PRESETN_DDR_DDRSCH3_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON26 */ +#define CRU_SOFTRST_CON26_OFFSET (0xA68U) +#define CRU_SOFTRST_CON26_RESETN_ISP1_SHIFT (3U) +#define CRU_SOFTRST_CON26_RESETN_ISP1_MASK (0x1U << CRU_SOFTRST_CON26_RESETN_ISP1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON26_RESETN_ISP1_VICAP_SHIFT (4U) +#define CRU_SOFTRST_CON26_RESETN_ISP1_VICAP_MASK (0x1U << CRU_SOFTRST_CON26_RESETN_ISP1_VICAP_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON26_ARESETN_ISP1_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON26_ARESETN_ISP1_BIU_MASK (0x1U << CRU_SOFTRST_CON26_ARESETN_ISP1_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON26_HRESETN_ISP1_BIU_SHIFT (8U) +#define CRU_SOFTRST_CON26_HRESETN_ISP1_BIU_MASK (0x1U << CRU_SOFTRST_CON26_HRESETN_ISP1_BIU_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON27 */ +#define CRU_SOFTRST_CON27_OFFSET (0xA6CU) +#define CRU_SOFTRST_CON27_ARESETN_RKNN1_SHIFT (0U) +#define CRU_SOFTRST_CON27_ARESETN_RKNN1_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_RKNN1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON27_ARESETN_RKNN1_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON27_ARESETN_RKNN1_BIU_MASK (0x1U << CRU_SOFTRST_CON27_ARESETN_RKNN1_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON27_HRESETN_RKNN1_SHIFT (2U) +#define CRU_SOFTRST_CON27_HRESETN_RKNN1_MASK (0x1U << CRU_SOFTRST_CON27_HRESETN_RKNN1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON27_HRESETN_RKNN1_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON27_HRESETN_RKNN1_BIU_MASK (0x1U << CRU_SOFTRST_CON27_HRESETN_RKNN1_BIU_SHIFT) /* 0x00000008 */ +/* SOFTRST_CON28 */ +#define CRU_SOFTRST_CON28_OFFSET (0xA70U) +#define CRU_SOFTRST_CON28_ARESETN_RKNN2_SHIFT (0U) +#define CRU_SOFTRST_CON28_ARESETN_RKNN2_MASK (0x1U << CRU_SOFTRST_CON28_ARESETN_RKNN2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON28_ARESETN_RKNN2_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON28_ARESETN_RKNN2_BIU_MASK (0x1U << CRU_SOFTRST_CON28_ARESETN_RKNN2_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON28_HRESETN_RKNN2_SHIFT (2U) +#define CRU_SOFTRST_CON28_HRESETN_RKNN2_MASK (0x1U << CRU_SOFTRST_CON28_HRESETN_RKNN2_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON28_HRESETN_RKNN2_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON28_HRESETN_RKNN2_BIU_MASK (0x1U << CRU_SOFTRST_CON28_HRESETN_RKNN2_BIU_SHIFT) /* 0x00000008 */ +/* SOFTRST_CON29 */ +#define CRU_SOFTRST_CON29_OFFSET (0xA74U) +#define CRU_SOFTRST_CON29_ARESETN_RKNN_DSU0_SHIFT (3U) +#define CRU_SOFTRST_CON29_ARESETN_RKNN_DSU0_MASK (0x1U << CRU_SOFTRST_CON29_ARESETN_RKNN_DSU0_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON29_PRESETN_NPUTOP_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON29_PRESETN_NPUTOP_BIU_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_NPUTOP_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON29_PRESETN_NPU_TIMER_SHIFT (6U) +#define CRU_SOFTRST_CON29_PRESETN_NPU_TIMER_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_NPU_TIMER_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON29_RESETN_NPUTIMER0_SHIFT (8U) +#define CRU_SOFTRST_CON29_RESETN_NPUTIMER0_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_NPUTIMER0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON29_RESETN_NPUTIMER1_SHIFT (9U) +#define CRU_SOFTRST_CON29_RESETN_NPUTIMER1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_NPUTIMER1_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON29_PRESETN_NPU_WDT_SHIFT (10U) +#define CRU_SOFTRST_CON29_PRESETN_NPU_WDT_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_NPU_WDT_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON29_TRESETN_NPU_WDT_SHIFT (11U) +#define CRU_SOFTRST_CON29_TRESETN_NPU_WDT_MASK (0x1U << CRU_SOFTRST_CON29_TRESETN_NPU_WDT_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON29_PRESETN_PVTM1_SHIFT (12U) +#define CRU_SOFTRST_CON29_PRESETN_PVTM1_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_PVTM1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON29_PRESETN_NPU_GRF_SHIFT (13U) +#define CRU_SOFTRST_CON29_PRESETN_NPU_GRF_MASK (0x1U << CRU_SOFTRST_CON29_PRESETN_NPU_GRF_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON29_RESETN_PVTM1_SHIFT (14U) +#define CRU_SOFTRST_CON29_RESETN_PVTM1_MASK (0x1U << CRU_SOFTRST_CON29_RESETN_PVTM1_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON30 */ +#define CRU_SOFTRST_CON30_OFFSET (0xA78U) +#define CRU_SOFTRST_CON30_RESETN_NPU_PVTPLL_SHIFT (0U) +#define CRU_SOFTRST_CON30_RESETN_NPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON30_RESETN_NPU_PVTPLL_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON30_HRESETN_NPU_CM0_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON30_HRESETN_NPU_CM0_BIU_MASK (0x1U << CRU_SOFTRST_CON30_HRESETN_NPU_CM0_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON30_FRESETN_NPU_CM0_CORE_SHIFT (3U) +#define CRU_SOFTRST_CON30_FRESETN_NPU_CM0_CORE_MASK (0x1U << CRU_SOFTRST_CON30_FRESETN_NPU_CM0_CORE_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON30_TRESETN_NPU_CM0_JTAG_SHIFT (4U) +#define CRU_SOFTRST_CON30_TRESETN_NPU_CM0_JTAG_MASK (0x1U << CRU_SOFTRST_CON30_TRESETN_NPU_CM0_JTAG_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON30_ARESETN_RKNN0_SHIFT (6U) +#define CRU_SOFTRST_CON30_ARESETN_RKNN0_MASK (0x1U << CRU_SOFTRST_CON30_ARESETN_RKNN0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON30_ARESETN_RKNN0_BIU_SHIFT (7U) +#define CRU_SOFTRST_CON30_ARESETN_RKNN0_BIU_MASK (0x1U << CRU_SOFTRST_CON30_ARESETN_RKNN0_BIU_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON30_HRESETN_RKNN0_SHIFT (8U) +#define CRU_SOFTRST_CON30_HRESETN_RKNN0_MASK (0x1U << CRU_SOFTRST_CON30_HRESETN_RKNN0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON30_HRESETN_RKNN0_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON30_HRESETN_RKNN0_BIU_MASK (0x1U << CRU_SOFTRST_CON30_HRESETN_RKNN0_BIU_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON31 */ +#define CRU_SOFTRST_CON31_OFFSET (0xA7CU) +#define CRU_SOFTRST_CON31_HRESETN_NVM_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON31_HRESETN_NVM_BIU_MASK (0x1U << CRU_SOFTRST_CON31_HRESETN_NVM_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON31_ARESETN_NVM_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON31_ARESETN_NVM_BIU_MASK (0x1U << CRU_SOFTRST_CON31_ARESETN_NVM_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON31_HRESETN_EMMC_SHIFT (4U) +#define CRU_SOFTRST_CON31_HRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON31_HRESETN_EMMC_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON31_ARESETN_EMMC_SHIFT (5U) +#define CRU_SOFTRST_CON31_ARESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON31_ARESETN_EMMC_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON31_CRESETN_EMMC_SHIFT (6U) +#define CRU_SOFTRST_CON31_CRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON31_CRESETN_EMMC_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON31_BRESETN_EMMC_SHIFT (7U) +#define CRU_SOFTRST_CON31_BRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON31_BRESETN_EMMC_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON31_TRESETN_EMMC_SHIFT (8U) +#define CRU_SOFTRST_CON31_TRESETN_EMMC_MASK (0x1U << CRU_SOFTRST_CON31_TRESETN_EMMC_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON31_SRESETN_SFC_SHIFT (9U) +#define CRU_SOFTRST_CON31_SRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON31_SRESETN_SFC_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON31_HRESETN_SFC_SHIFT (10U) +#define CRU_SOFTRST_CON31_HRESETN_SFC_MASK (0x1U << CRU_SOFTRST_CON31_HRESETN_SFC_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON31_HRESETN_SFC_XIP_SHIFT (11U) +#define CRU_SOFTRST_CON31_HRESETN_SFC_XIP_MASK (0x1U << CRU_SOFTRST_CON31_HRESETN_SFC_XIP_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON32 */ +#define CRU_SOFTRST_CON32_OFFSET (0xA80U) +#define CRU_SOFTRST_CON32_PRESETN_GRF_SHIFT (1U) +#define CRU_SOFTRST_CON32_PRESETN_GRF_MASK (0x1U << CRU_SOFTRST_CON32_PRESETN_GRF_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON32_PRESETN_DEC_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON32_PRESETN_DEC_BIU_MASK (0x1U << CRU_SOFTRST_CON32_PRESETN_DEC_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON32_PRESETN_PHP_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON32_PRESETN_PHP_BIU_MASK (0x1U << CRU_SOFTRST_CON32_PRESETN_PHP_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON32_ARESETN_PCIE_BRIDGE_SHIFT (8U) +#define CRU_SOFTRST_CON32_ARESETN_PCIE_BRIDGE_MASK (0x1U << CRU_SOFTRST_CON32_ARESETN_PCIE_BRIDGE_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON32_ARESETN_PHP_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON32_ARESETN_PHP_BIU_MASK (0x1U << CRU_SOFTRST_CON32_ARESETN_PHP_BIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON32_ARESETN_GMAC0_SHIFT (10U) +#define CRU_SOFTRST_CON32_ARESETN_GMAC0_MASK (0x1U << CRU_SOFTRST_CON32_ARESETN_GMAC0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON32_ARESETN_GMAC1_SHIFT (11U) +#define CRU_SOFTRST_CON32_ARESETN_GMAC1_MASK (0x1U << CRU_SOFTRST_CON32_ARESETN_GMAC1_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON32_ARESETN_PCIE_BIU_SHIFT (12U) +#define CRU_SOFTRST_CON32_ARESETN_PCIE_BIU_MASK (0x1U << CRU_SOFTRST_CON32_ARESETN_PCIE_BIU_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON32_RESETN_PCIE_4L_POWER_UP_SHIFT (13U) +#define CRU_SOFTRST_CON32_RESETN_PCIE_4L_POWER_UP_MASK (0x1U << CRU_SOFTRST_CON32_RESETN_PCIE_4L_POWER_UP_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON32_RESETN_PCIE_2L_POWER_UP_SHIFT (14U) +#define CRU_SOFTRST_CON32_RESETN_PCIE_2L_POWER_UP_MASK (0x1U << CRU_SOFTRST_CON32_RESETN_PCIE_2L_POWER_UP_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON32_RESETN_PCIE_1L0_POWER_UP_SHIFT (15U) +#define CRU_SOFTRST_CON32_RESETN_PCIE_1L0_POWER_UP_MASK (0x1U << CRU_SOFTRST_CON32_RESETN_PCIE_1L0_POWER_UP_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON33 */ +#define CRU_SOFTRST_CON33_OFFSET (0xA84U) +#define CRU_SOFTRST_CON33_RESETN_PCIE_1L1_POWER_UP_SHIFT (0U) +#define CRU_SOFTRST_CON33_RESETN_PCIE_1L1_POWER_UP_MASK (0x1U << CRU_SOFTRST_CON33_RESETN_PCIE_1L1_POWER_UP_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON33_RESETN_PCIE_1L2_POWER_UP_SHIFT (1U) +#define CRU_SOFTRST_CON33_RESETN_PCIE_1L2_POWER_UP_MASK (0x1U << CRU_SOFTRST_CON33_RESETN_PCIE_1L2_POWER_UP_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON33_PRESETN_PCIE_4L_SHIFT (12U) +#define CRU_SOFTRST_CON33_PRESETN_PCIE_4L_MASK (0x1U << CRU_SOFTRST_CON33_PRESETN_PCIE_4L_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON33_PRESETN_PCIE_2L_SHIFT (13U) +#define CRU_SOFTRST_CON33_PRESETN_PCIE_2L_MASK (0x1U << CRU_SOFTRST_CON33_PRESETN_PCIE_2L_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON33_PRESETN_PCIE_1L0_SHIFT (14U) +#define CRU_SOFTRST_CON33_PRESETN_PCIE_1L0_MASK (0x1U << CRU_SOFTRST_CON33_PRESETN_PCIE_1L0_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON33_PRESETN_PCIE_1L1_SHIFT (15U) +#define CRU_SOFTRST_CON33_PRESETN_PCIE_1L1_MASK (0x1U << CRU_SOFTRST_CON33_PRESETN_PCIE_1L1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON34 */ +#define CRU_SOFTRST_CON34_OFFSET (0xA88U) +#define CRU_SOFTRST_CON34_PRESETN_PCIE_1L2_SHIFT (0U) +#define CRU_SOFTRST_CON34_PRESETN_PCIE_1L2_MASK (0x1U << CRU_SOFTRST_CON34_PRESETN_PCIE_1L2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON34_ARESETN_PHP_GIC_ITS_SHIFT (6U) +#define CRU_SOFTRST_CON34_ARESETN_PHP_GIC_ITS_MASK (0x1U << CRU_SOFTRST_CON34_ARESETN_PHP_GIC_ITS_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON34_ARESETN_MMU_PCIE_SHIFT (7U) +#define CRU_SOFTRST_CON34_ARESETN_MMU_PCIE_MASK (0x1U << CRU_SOFTRST_CON34_ARESETN_MMU_PCIE_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON34_ARESETN_MMU_PHP_SHIFT (8U) +#define CRU_SOFTRST_CON34_ARESETN_MMU_PHP_MASK (0x1U << CRU_SOFTRST_CON34_ARESETN_MMU_PHP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON34_ARESETN_MMU_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON34_ARESETN_MMU_BIU_MASK (0x1U << CRU_SOFTRST_CON34_ARESETN_MMU_BIU_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON35 */ +#define CRU_SOFTRST_CON35_OFFSET (0xA8CU) +#define CRU_SOFTRST_CON35_ARESETN_USB3OTG2_SHIFT (7U) +#define CRU_SOFTRST_CON35_ARESETN_USB3OTG2_MASK (0x1U << CRU_SOFTRST_CON35_ARESETN_USB3OTG2_SHIFT) /* 0x00000080 */ +/* SOFTRST_CON37 */ +#define CRU_SOFTRST_CON37_OFFSET (0xA94U) +#define CRU_SOFTRST_CON37_RESETN_PMALIVE0_SHIFT (4U) +#define CRU_SOFTRST_CON37_RESETN_PMALIVE0_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_PMALIVE0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON37_RESETN_PMALIVE1_SHIFT (5U) +#define CRU_SOFTRST_CON37_RESETN_PMALIVE1_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_PMALIVE1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON37_RESETN_PMALIVE2_SHIFT (6U) +#define CRU_SOFTRST_CON37_RESETN_PMALIVE2_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_PMALIVE2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON37_ARESETN_SATA0_SHIFT (7U) +#define CRU_SOFTRST_CON37_ARESETN_SATA0_MASK (0x1U << CRU_SOFTRST_CON37_ARESETN_SATA0_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON37_ARESETN_SATA1_SHIFT (8U) +#define CRU_SOFTRST_CON37_ARESETN_SATA1_MASK (0x1U << CRU_SOFTRST_CON37_ARESETN_SATA1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON37_ARESETN_SATA2_SHIFT (9U) +#define CRU_SOFTRST_CON37_ARESETN_SATA2_MASK (0x1U << CRU_SOFTRST_CON37_ARESETN_SATA2_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON37_RESETN_RXOOB0_SHIFT (10U) +#define CRU_SOFTRST_CON37_RESETN_RXOOB0_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_RXOOB0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON37_RESETN_RXOOB1_SHIFT (11U) +#define CRU_SOFTRST_CON37_RESETN_RXOOB1_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_RXOOB1_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON37_RESETN_RXOOB2_SHIFT (12U) +#define CRU_SOFTRST_CON37_RESETN_RXOOB2_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_RXOOB2_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON37_RESETN_ASIC0_SHIFT (13U) +#define CRU_SOFTRST_CON37_RESETN_ASIC0_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_ASIC0_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON37_RESETN_ASIC1_SHIFT (14U) +#define CRU_SOFTRST_CON37_RESETN_ASIC1_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_ASIC1_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON37_RESETN_ASIC2_SHIFT (15U) +#define CRU_SOFTRST_CON37_RESETN_ASIC2_MASK (0x1U << CRU_SOFTRST_CON37_RESETN_ASIC2_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON40 */ +#define CRU_SOFTRST_CON40_OFFSET (0xAA0U) +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC_CCU_SHIFT (2U) +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC_CCU_MASK (0x1U << CRU_SOFTRST_CON40_ARESETN_RKVDEC_CCU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON40_HRESETN_RKVDEC0_SHIFT (3U) +#define CRU_SOFTRST_CON40_HRESETN_RKVDEC0_MASK (0x1U << CRU_SOFTRST_CON40_HRESETN_RKVDEC0_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC0_SHIFT (4U) +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC0_MASK (0x1U << CRU_SOFTRST_CON40_ARESETN_RKVDEC0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON40_HRESETN_RKVDEC0_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON40_HRESETN_RKVDEC0_BIU_MASK (0x1U << CRU_SOFTRST_CON40_HRESETN_RKVDEC0_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC0_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON40_ARESETN_RKVDEC0_BIU_MASK (0x1U << CRU_SOFTRST_CON40_ARESETN_RKVDEC0_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_CA_SHIFT (7U) +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_CA_MASK (0x1U << CRU_SOFTRST_CON40_RESETN_RKVDEC0_CA_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_HEVC_CA_SHIFT (8U) +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_HEVC_CA_MASK (0x1U << CRU_SOFTRST_CON40_RESETN_RKVDEC0_HEVC_CA_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_CORE_SHIFT (9U) +#define CRU_SOFTRST_CON40_RESETN_RKVDEC0_CORE_MASK (0x1U << CRU_SOFTRST_CON40_RESETN_RKVDEC0_CORE_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON41 */ +#define CRU_SOFTRST_CON41_OFFSET (0xAA4U) +#define CRU_SOFTRST_CON41_HRESETN_RKVDEC1_SHIFT (2U) +#define CRU_SOFTRST_CON41_HRESETN_RKVDEC1_MASK (0x1U << CRU_SOFTRST_CON41_HRESETN_RKVDEC1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON41_ARESETN_RKVDEC1_SHIFT (3U) +#define CRU_SOFTRST_CON41_ARESETN_RKVDEC1_MASK (0x1U << CRU_SOFTRST_CON41_ARESETN_RKVDEC1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON41_HRESETN_RKVDEC1_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON41_HRESETN_RKVDEC1_BIU_MASK (0x1U << CRU_SOFTRST_CON41_HRESETN_RKVDEC1_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON41_ARESETN_RKVDEC1_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON41_ARESETN_RKVDEC1_BIU_MASK (0x1U << CRU_SOFTRST_CON41_ARESETN_RKVDEC1_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_CA_SHIFT (6U) +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_CA_MASK (0x1U << CRU_SOFTRST_CON41_RESETN_RKVDEC1_CA_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_HEVC_CA_SHIFT (7U) +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_HEVC_CA_MASK (0x1U << CRU_SOFTRST_CON41_RESETN_RKVDEC1_HEVC_CA_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_CORE_SHIFT (8U) +#define CRU_SOFTRST_CON41_RESETN_RKVDEC1_CORE_MASK (0x1U << CRU_SOFTRST_CON41_RESETN_RKVDEC1_CORE_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON42 */ +#define CRU_SOFTRST_CON42_OFFSET (0xAA8U) +#define CRU_SOFTRST_CON42_ARESETN_USB_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON42_ARESETN_USB_BIU_MASK (0x1U << CRU_SOFTRST_CON42_ARESETN_USB_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON42_HRESETN_USB_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON42_HRESETN_USB_BIU_MASK (0x1U << CRU_SOFTRST_CON42_HRESETN_USB_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON42_ARESETN_USB3OTG0_SHIFT (4U) +#define CRU_SOFTRST_CON42_ARESETN_USB3OTG0_MASK (0x1U << CRU_SOFTRST_CON42_ARESETN_USB3OTG0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON42_ARESETN_USB3OTG1_SHIFT (7U) +#define CRU_SOFTRST_CON42_ARESETN_USB3OTG1_MASK (0x1U << CRU_SOFTRST_CON42_ARESETN_USB3OTG1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON42_HRESETN_HOST0_SHIFT (10U) +#define CRU_SOFTRST_CON42_HRESETN_HOST0_MASK (0x1U << CRU_SOFTRST_CON42_HRESETN_HOST0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON42_HRESETN_HOST_ARB0_SHIFT (11U) +#define CRU_SOFTRST_CON42_HRESETN_HOST_ARB0_MASK (0x1U << CRU_SOFTRST_CON42_HRESETN_HOST_ARB0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON42_HRESETN_HOST1_SHIFT (12U) +#define CRU_SOFTRST_CON42_HRESETN_HOST1_MASK (0x1U << CRU_SOFTRST_CON42_HRESETN_HOST1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON42_HRESETN_HOST_ARB1_SHIFT (13U) +#define CRU_SOFTRST_CON42_HRESETN_HOST_ARB1_MASK (0x1U << CRU_SOFTRST_CON42_HRESETN_HOST_ARB1_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON42_ARESETN_USB_GRF_SHIFT (14U) +#define CRU_SOFTRST_CON42_ARESETN_USB_GRF_MASK (0x1U << CRU_SOFTRST_CON42_ARESETN_USB_GRF_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON42_CRESETN_USB2P0_HOST0_SHIFT (15U) +#define CRU_SOFTRST_CON42_CRESETN_USB2P0_HOST0_MASK (0x1U << CRU_SOFTRST_CON42_CRESETN_USB2P0_HOST0_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON43 */ +#define CRU_SOFTRST_CON43_OFFSET (0xAACU) +#define CRU_SOFTRST_CON43_CRESETN_USB2P0_HOST1_SHIFT (0U) +#define CRU_SOFTRST_CON43_CRESETN_USB2P0_HOST1_MASK (0x1U << CRU_SOFTRST_CON43_CRESETN_USB2P0_HOST1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON43_RESETN_HOST_UTMI0_SHIFT (1U) +#define CRU_SOFTRST_CON43_RESETN_HOST_UTMI0_MASK (0x1U << CRU_SOFTRST_CON43_RESETN_HOST_UTMI0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON43_RESETN_HOST_UTMI1_SHIFT (2U) +#define CRU_SOFTRST_CON43_RESETN_HOST_UTMI1_MASK (0x1U << CRU_SOFTRST_CON43_RESETN_HOST_UTMI1_SHIFT) /* 0x00000004 */ +/* SOFTRST_CON44 */ +#define CRU_SOFTRST_CON44_OFFSET (0xAB0U) +#define CRU_SOFTRST_CON44_ARESETN_VDPU_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON44_ARESETN_VDPU_BIU_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_VDPU_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON44_ARESETN_VDPU_LOW_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON44_ARESETN_VDPU_LOW_BIU_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_VDPU_LOW_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON44_HRESETN_VDPU_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON44_HRESETN_VDPU_BIU_MASK (0x1U << CRU_SOFTRST_CON44_HRESETN_VDPU_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON44_ARESETN_JPEG_DECODER_BIU_SHIFT (7U) +#define CRU_SOFTRST_CON44_ARESETN_JPEG_DECODER_BIU_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_JPEG_DECODER_BIU_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON44_ARESETN_VPU_SHIFT (8U) +#define CRU_SOFTRST_CON44_ARESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_VPU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON44_HRESETN_VPU_SHIFT (9U) +#define CRU_SOFTRST_CON44_HRESETN_VPU_MASK (0x1U << CRU_SOFTRST_CON44_HRESETN_VPU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER0_SHIFT (10U) +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER0_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER0_SHIFT (11U) +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER0_MASK (0x1U << CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER1_SHIFT (12U) +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER1_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER1_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER1_SHIFT (13U) +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER1_MASK (0x1U << CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER1_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER2_SHIFT (14U) +#define CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER2_MASK (0x1U << CRU_SOFTRST_CON44_ARESETN_JPEG_ENCODER2_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER2_SHIFT (15U) +#define CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER2_MASK (0x1U << CRU_SOFTRST_CON44_HRESETN_JPEG_ENCODER2_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON45 */ +#define CRU_SOFTRST_CON45_OFFSET (0xAB4U) +#define CRU_SOFTRST_CON45_ARESETN_JPEG_ENCODER3_SHIFT (0U) +#define CRU_SOFTRST_CON45_ARESETN_JPEG_ENCODER3_MASK (0x1U << CRU_SOFTRST_CON45_ARESETN_JPEG_ENCODER3_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON45_HRESETN_JPEG_ENCODER3_SHIFT (1U) +#define CRU_SOFTRST_CON45_HRESETN_JPEG_ENCODER3_MASK (0x1U << CRU_SOFTRST_CON45_HRESETN_JPEG_ENCODER3_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON45_ARESETN_JPEG_DECODER_SHIFT (2U) +#define CRU_SOFTRST_CON45_ARESETN_JPEG_DECODER_MASK (0x1U << CRU_SOFTRST_CON45_ARESETN_JPEG_DECODER_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON45_HRESETN_JPEG_DECODER_SHIFT (3U) +#define CRU_SOFTRST_CON45_HRESETN_JPEG_DECODER_MASK (0x1U << CRU_SOFTRST_CON45_HRESETN_JPEG_DECODER_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON45_HRESETN_IEP2P0_SHIFT (4U) +#define CRU_SOFTRST_CON45_HRESETN_IEP2P0_MASK (0x1U << CRU_SOFTRST_CON45_HRESETN_IEP2P0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON45_ARESETN_IEP2P0_SHIFT (5U) +#define CRU_SOFTRST_CON45_ARESETN_IEP2P0_MASK (0x1U << CRU_SOFTRST_CON45_ARESETN_IEP2P0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON45_RESETN_IEP2P0_CORE_SHIFT (6U) +#define CRU_SOFTRST_CON45_RESETN_IEP2P0_CORE_MASK (0x1U << CRU_SOFTRST_CON45_RESETN_IEP2P0_CORE_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON45_HRESETN_RGA2_SHIFT (7U) +#define CRU_SOFTRST_CON45_HRESETN_RGA2_MASK (0x1U << CRU_SOFTRST_CON45_HRESETN_RGA2_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON45_ARESETN_RGA2_SHIFT (8U) +#define CRU_SOFTRST_CON45_ARESETN_RGA2_MASK (0x1U << CRU_SOFTRST_CON45_ARESETN_RGA2_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON45_RESETN_RGA2_CORE_SHIFT (9U) +#define CRU_SOFTRST_CON45_RESETN_RGA2_CORE_MASK (0x1U << CRU_SOFTRST_CON45_RESETN_RGA2_CORE_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON45_HRESETN_RGA3_0_SHIFT (10U) +#define CRU_SOFTRST_CON45_HRESETN_RGA3_0_MASK (0x1U << CRU_SOFTRST_CON45_HRESETN_RGA3_0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON45_ARESETN_RGA3_0_SHIFT (11U) +#define CRU_SOFTRST_CON45_ARESETN_RGA3_0_MASK (0x1U << CRU_SOFTRST_CON45_ARESETN_RGA3_0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON45_RESETN_RGA3_0_CORE_SHIFT (12U) +#define CRU_SOFTRST_CON45_RESETN_RGA3_0_CORE_MASK (0x1U << CRU_SOFTRST_CON45_RESETN_RGA3_0_CORE_SHIFT) /* 0x00001000 */ +/* SOFTRST_CON47 */ +#define CRU_SOFTRST_CON47_OFFSET (0xABCU) +#define CRU_SOFTRST_CON47_HRESETN_RKVENC0_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON47_HRESETN_RKVENC0_BIU_MASK (0x1U << CRU_SOFTRST_CON47_HRESETN_RKVENC0_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON47_ARESETN_RKVENC0_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON47_ARESETN_RKVENC0_BIU_MASK (0x1U << CRU_SOFTRST_CON47_ARESETN_RKVENC0_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON47_HRESETN_RKVENC0_SHIFT (4U) +#define CRU_SOFTRST_CON47_HRESETN_RKVENC0_MASK (0x1U << CRU_SOFTRST_CON47_HRESETN_RKVENC0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON47_ARESETN_RKVENC0_SHIFT (5U) +#define CRU_SOFTRST_CON47_ARESETN_RKVENC0_MASK (0x1U << CRU_SOFTRST_CON47_ARESETN_RKVENC0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON47_RESETN_RKVENC0_CORE_SHIFT (6U) +#define CRU_SOFTRST_CON47_RESETN_RKVENC0_CORE_MASK (0x1U << CRU_SOFTRST_CON47_RESETN_RKVENC0_CORE_SHIFT) /* 0x00000040 */ +/* SOFTRST_CON48 */ +#define CRU_SOFTRST_CON48_OFFSET (0xAC0U) +#define CRU_SOFTRST_CON48_HRESETN_RKVENC1_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON48_HRESETN_RKVENC1_BIU_MASK (0x1U << CRU_SOFTRST_CON48_HRESETN_RKVENC1_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON48_ARESETN_RKVENC1_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON48_ARESETN_RKVENC1_BIU_MASK (0x1U << CRU_SOFTRST_CON48_ARESETN_RKVENC1_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON48_HRESETN_RKVENC1_SHIFT (4U) +#define CRU_SOFTRST_CON48_HRESETN_RKVENC1_MASK (0x1U << CRU_SOFTRST_CON48_HRESETN_RKVENC1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON48_ARESETN_RKVENC1_SHIFT (5U) +#define CRU_SOFTRST_CON48_ARESETN_RKVENC1_MASK (0x1U << CRU_SOFTRST_CON48_ARESETN_RKVENC1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON48_RESETN_RKVENC1_CORE_SHIFT (6U) +#define CRU_SOFTRST_CON48_RESETN_RKVENC1_CORE_MASK (0x1U << CRU_SOFTRST_CON48_RESETN_RKVENC1_CORE_SHIFT) /* 0x00000040 */ +/* SOFTRST_CON49 */ +#define CRU_SOFTRST_CON49_OFFSET (0xAC4U) +#define CRU_SOFTRST_CON49_ARESETN_VI_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON49_ARESETN_VI_BIU_MASK (0x1U << CRU_SOFTRST_CON49_ARESETN_VI_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON49_HRESETN_VI_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON49_HRESETN_VI_BIU_MASK (0x1U << CRU_SOFTRST_CON49_HRESETN_VI_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON49_PRESETN_VI_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON49_PRESETN_VI_BIU_MASK (0x1U << CRU_SOFTRST_CON49_PRESETN_VI_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON49_DRESETN_VICAP_SHIFT (6U) +#define CRU_SOFTRST_CON49_DRESETN_VICAP_MASK (0x1U << CRU_SOFTRST_CON49_DRESETN_VICAP_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON49_ARESETN_VICAP_SHIFT (7U) +#define CRU_SOFTRST_CON49_ARESETN_VICAP_MASK (0x1U << CRU_SOFTRST_CON49_ARESETN_VICAP_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON49_HRESETN_VICAP_SHIFT (8U) +#define CRU_SOFTRST_CON49_HRESETN_VICAP_MASK (0x1U << CRU_SOFTRST_CON49_HRESETN_VICAP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON49_RESETN_ISP0_SHIFT (10U) +#define CRU_SOFTRST_CON49_RESETN_ISP0_MASK (0x1U << CRU_SOFTRST_CON49_RESETN_ISP0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON49_RESETN_ISP0_VICAP_SHIFT (11U) +#define CRU_SOFTRST_CON49_RESETN_ISP0_VICAP_MASK (0x1U << CRU_SOFTRST_CON49_RESETN_ISP0_VICAP_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON50 */ +#define CRU_SOFTRST_CON50_OFFSET (0xAC8U) +#define CRU_SOFTRST_CON50_RESETN_FISHEYE0_SHIFT (0U) +#define CRU_SOFTRST_CON50_RESETN_FISHEYE0_MASK (0x1U << CRU_SOFTRST_CON50_RESETN_FISHEYE0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON50_RESETN_FISHEYE1_SHIFT (3U) +#define CRU_SOFTRST_CON50_RESETN_FISHEYE1_MASK (0x1U << CRU_SOFTRST_CON50_RESETN_FISHEYE1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_0_SHIFT (4U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_0_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_1_SHIFT (5U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_1_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_2_SHIFT (6U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_2_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_2_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_3_SHIFT (7U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_3_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_4_SHIFT (8U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_4_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_4_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_5_SHIFT (9U) +#define CRU_SOFTRST_CON50_PRESETN_CSI_HOST_5_MASK (0x1U << CRU_SOFTRST_CON50_PRESETN_CSI_HOST_5_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON51 */ +#define CRU_SOFTRST_CON51_OFFSET (0xACCU) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST0_VICAP_SHIFT (4U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST0_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST0_VICAP_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON51_RESETN_CSIHOST1_VICAP_SHIFT (5U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST1_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST1_VICAP_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON51_RESETN_CSIHOST2_VICAP_SHIFT (6U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST2_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST2_VICAP_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON51_RESETN_CSIHOST3_VICAP_SHIFT (7U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST3_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST3_VICAP_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON51_RESETN_CSIHOST4_VICAP_SHIFT (8U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST4_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST4_VICAP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON51_RESETN_CSIHOST5_VICAP_SHIFT (9U) +#define CRU_SOFTRST_CON51_RESETN_CSIHOST5_VICAP_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CSIHOST5_VICAP_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON51_RESETN_CIFIN_SHIFT (13U) +#define CRU_SOFTRST_CON51_RESETN_CIFIN_MASK (0x1U << CRU_SOFTRST_CON51_RESETN_CIFIN_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON52 */ +#define CRU_SOFTRST_CON52_OFFSET (0xAD0U) +#define CRU_SOFTRST_CON52_ARESETN_VOP_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON52_ARESETN_VOP_BIU_MASK (0x1U << CRU_SOFTRST_CON52_ARESETN_VOP_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON52_ARESETN_VOP_LOW_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON52_ARESETN_VOP_LOW_BIU_MASK (0x1U << CRU_SOFTRST_CON52_ARESETN_VOP_LOW_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON52_HRESETN_VOP_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON52_HRESETN_VOP_BIU_MASK (0x1U << CRU_SOFTRST_CON52_HRESETN_VOP_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON52_PRESETN_VOP_BIU_SHIFT (7U) +#define CRU_SOFTRST_CON52_PRESETN_VOP_BIU_MASK (0x1U << CRU_SOFTRST_CON52_PRESETN_VOP_BIU_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON52_HRESETN_VOP_SHIFT (8U) +#define CRU_SOFTRST_CON52_HRESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON52_HRESETN_VOP_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON52_ARESETN_VOP_SHIFT (9U) +#define CRU_SOFTRST_CON52_ARESETN_VOP_MASK (0x1U << CRU_SOFTRST_CON52_ARESETN_VOP_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON52_DRESETN_VOP0_SHIFT (13U) +#define CRU_SOFTRST_CON52_DRESETN_VOP0_MASK (0x1U << CRU_SOFTRST_CON52_DRESETN_VOP0_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE0_SHIFT (14U) +#define CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE0_MASK (0x1U << CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE0_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE1_SHIFT (15U) +#define CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE1_MASK (0x1U << CRU_SOFTRST_CON52_DRESETN_VOP2HDMI_BRIDGE1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON53 */ +#define CRU_SOFTRST_CON53_OFFSET (0xAD4U) +#define CRU_SOFTRST_CON53_DRESETN_VOP1_SHIFT (0U) +#define CRU_SOFTRST_CON53_DRESETN_VOP1_MASK (0x1U << CRU_SOFTRST_CON53_DRESETN_VOP1_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON53_DRESETN_VOP2_SHIFT (1U) +#define CRU_SOFTRST_CON53_DRESETN_VOP2_MASK (0x1U << CRU_SOFTRST_CON53_DRESETN_VOP2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON53_DRESETN_VOP3_SHIFT (2U) +#define CRU_SOFTRST_CON53_DRESETN_VOP3_MASK (0x1U << CRU_SOFTRST_CON53_DRESETN_VOP3_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON53_PRESETN_VOPGRF_SHIFT (3U) +#define CRU_SOFTRST_CON53_PRESETN_VOPGRF_MASK (0x1U << CRU_SOFTRST_CON53_PRESETN_VOPGRF_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON53_PRESETN_DSIHOST0_SHIFT (4U) +#define CRU_SOFTRST_CON53_PRESETN_DSIHOST0_MASK (0x1U << CRU_SOFTRST_CON53_PRESETN_DSIHOST0_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON53_PRESETN_DSIHOST1_SHIFT (5U) +#define CRU_SOFTRST_CON53_PRESETN_DSIHOST1_MASK (0x1U << CRU_SOFTRST_CON53_PRESETN_DSIHOST1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON53_RESETN_DSIHOST0_SHIFT (6U) +#define CRU_SOFTRST_CON53_RESETN_DSIHOST0_MASK (0x1U << CRU_SOFTRST_CON53_RESETN_DSIHOST0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON53_RESETN_DSIHOST1_SHIFT (7U) +#define CRU_SOFTRST_CON53_RESETN_DSIHOST1_MASK (0x1U << CRU_SOFTRST_CON53_RESETN_DSIHOST1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON53_RESETN_VOP_PMU_SHIFT (8U) +#define CRU_SOFTRST_CON53_RESETN_VOP_PMU_MASK (0x1U << CRU_SOFTRST_CON53_RESETN_VOP_PMU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON53_PRESETN_VOP_CHANNEL_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON53_PRESETN_VOP_CHANNEL_BIU_MASK (0x1U << CRU_SOFTRST_CON53_PRESETN_VOP_CHANNEL_BIU_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON55 */ +#define CRU_SOFTRST_CON55_OFFSET (0xADCU) +#define CRU_SOFTRST_CON55_HRESETN_VO0_BIU_SHIFT (5U) +#define CRU_SOFTRST_CON55_HRESETN_VO0_BIU_MASK (0x1U << CRU_SOFTRST_CON55_HRESETN_VO0_BIU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON55_HRESETN_VO0_S_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON55_HRESETN_VO0_S_BIU_MASK (0x1U << CRU_SOFTRST_CON55_HRESETN_VO0_S_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON55_PRESETN_VO0_BIU_SHIFT (7U) +#define CRU_SOFTRST_CON55_PRESETN_VO0_BIU_MASK (0x1U << CRU_SOFTRST_CON55_PRESETN_VO0_BIU_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON55_PRESETN_VO0_S_BIU_SHIFT (8U) +#define CRU_SOFTRST_CON55_PRESETN_VO0_S_BIU_MASK (0x1U << CRU_SOFTRST_CON55_PRESETN_VO0_S_BIU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON55_ARESETN_HDCP0_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON55_ARESETN_HDCP0_BIU_MASK (0x1U << CRU_SOFTRST_CON55_ARESETN_HDCP0_BIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON55_PRESETN_VO0GRF_SHIFT (10U) +#define CRU_SOFTRST_CON55_PRESETN_VO0GRF_MASK (0x1U << CRU_SOFTRST_CON55_PRESETN_VO0GRF_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON55_HRESETN_HDCP_KEY0_SHIFT (11U) +#define CRU_SOFTRST_CON55_HRESETN_HDCP_KEY0_MASK (0x1U << CRU_SOFTRST_CON55_HRESETN_HDCP_KEY0_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON55_ARESETN_HDCP0_SHIFT (12U) +#define CRU_SOFTRST_CON55_ARESETN_HDCP0_MASK (0x1U << CRU_SOFTRST_CON55_ARESETN_HDCP0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON55_HRESETN_HDCP0_SHIFT (13U) +#define CRU_SOFTRST_CON55_HRESETN_HDCP0_MASK (0x1U << CRU_SOFTRST_CON55_HRESETN_HDCP0_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON55_RESETN_HDCP0_SHIFT (15U) +#define CRU_SOFTRST_CON55_RESETN_HDCP0_MASK (0x1U << CRU_SOFTRST_CON55_RESETN_HDCP0_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON56 */ +#define CRU_SOFTRST_CON56_OFFSET (0xAE0U) +#define CRU_SOFTRST_CON56_PRESETN_TRNG0_SHIFT (1U) +#define CRU_SOFTRST_CON56_PRESETN_TRNG0_MASK (0x1U << CRU_SOFTRST_CON56_PRESETN_TRNG0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON56_RESETN_DP0_SHIFT (8U) +#define CRU_SOFTRST_CON56_RESETN_DP0_MASK (0x1U << CRU_SOFTRST_CON56_RESETN_DP0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON56_RESETN_DP1_SHIFT (9U) +#define CRU_SOFTRST_CON56_RESETN_DP1_MASK (0x1U << CRU_SOFTRST_CON56_RESETN_DP1_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON56_HRESETN_I2S4_8CH_SHIFT (10U) +#define CRU_SOFTRST_CON56_HRESETN_I2S4_8CH_MASK (0x1U << CRU_SOFTRST_CON56_HRESETN_I2S4_8CH_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON56_MRESETN_I2S4_8CH_TX_SHIFT (13U) +#define CRU_SOFTRST_CON56_MRESETN_I2S4_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON56_MRESETN_I2S4_8CH_TX_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON56_HRESETN_I2S8_8CH_SHIFT (14U) +#define CRU_SOFTRST_CON56_HRESETN_I2S8_8CH_MASK (0x1U << CRU_SOFTRST_CON56_HRESETN_I2S8_8CH_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON57 */ +#define CRU_SOFTRST_CON57_OFFSET (0xAE4U) +#define CRU_SOFTRST_CON57_MRESETN_I2S8_8CH_TX_SHIFT (1U) +#define CRU_SOFTRST_CON57_MRESETN_I2S8_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON57_MRESETN_I2S8_8CH_TX_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON57_HRESETN_SPDIF2_DP0_SHIFT (2U) +#define CRU_SOFTRST_CON57_HRESETN_SPDIF2_DP0_MASK (0x1U << CRU_SOFTRST_CON57_HRESETN_SPDIF2_DP0_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON57_MRESETN_SPDIF2_DP0_SHIFT (6U) +#define CRU_SOFTRST_CON57_MRESETN_SPDIF2_DP0_MASK (0x1U << CRU_SOFTRST_CON57_MRESETN_SPDIF2_DP0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON57_HRESETN_SPDIF5_DP1_SHIFT (7U) +#define CRU_SOFTRST_CON57_HRESETN_SPDIF5_DP1_MASK (0x1U << CRU_SOFTRST_CON57_HRESETN_SPDIF5_DP1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON57_MRESETN_SPDIF5_DP1_SHIFT (11U) +#define CRU_SOFTRST_CON57_MRESETN_SPDIF5_DP1_MASK (0x1U << CRU_SOFTRST_CON57_MRESETN_SPDIF5_DP1_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON59 */ +#define CRU_SOFTRST_CON59_OFFSET (0xAECU) +#define CRU_SOFTRST_CON59_ARESETN_HDCP1_BIU_SHIFT (6U) +#define CRU_SOFTRST_CON59_ARESETN_HDCP1_BIU_MASK (0x1U << CRU_SOFTRST_CON59_ARESETN_HDCP1_BIU_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON59_ARESETN_VO1_BIU_SHIFT (8U) +#define CRU_SOFTRST_CON59_ARESETN_VO1_BIU_MASK (0x1U << CRU_SOFTRST_CON59_ARESETN_VO1_BIU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON59_HRESETN_VOP1_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON59_HRESETN_VOP1_BIU_MASK (0x1U << CRU_SOFTRST_CON59_HRESETN_VOP1_BIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON59_HRESETN_VOP1_S_BIU_SHIFT (10U) +#define CRU_SOFTRST_CON59_HRESETN_VOP1_S_BIU_MASK (0x1U << CRU_SOFTRST_CON59_HRESETN_VOP1_S_BIU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON59_PRESETN_VOP1_BIU_SHIFT (11U) +#define CRU_SOFTRST_CON59_PRESETN_VOP1_BIU_MASK (0x1U << CRU_SOFTRST_CON59_PRESETN_VOP1_BIU_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON59_PRESETN_VO1GRF_SHIFT (12U) +#define CRU_SOFTRST_CON59_PRESETN_VO1GRF_MASK (0x1U << CRU_SOFTRST_CON59_PRESETN_VO1GRF_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON59_PRESETN_VO1_S_BIU_SHIFT (13U) +#define CRU_SOFTRST_CON59_PRESETN_VO1_S_BIU_MASK (0x1U << CRU_SOFTRST_CON59_PRESETN_VO1_S_BIU_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON60 */ +#define CRU_SOFTRST_CON60_OFFSET (0xAF0U) +#define CRU_SOFTRST_CON60_HRESETN_I2S7_8CH_SHIFT (0U) +#define CRU_SOFTRST_CON60_HRESETN_I2S7_8CH_MASK (0x1U << CRU_SOFTRST_CON60_HRESETN_I2S7_8CH_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON60_MRESETN_I2S7_8CH_RX_SHIFT (3U) +#define CRU_SOFTRST_CON60_MRESETN_I2S7_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON60_MRESETN_I2S7_8CH_RX_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON60_HRESETN_HDCP_KEY1_SHIFT (4U) +#define CRU_SOFTRST_CON60_HRESETN_HDCP_KEY1_MASK (0x1U << CRU_SOFTRST_CON60_HRESETN_HDCP_KEY1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON60_ARESETN_HDCP1_SHIFT (5U) +#define CRU_SOFTRST_CON60_ARESETN_HDCP1_MASK (0x1U << CRU_SOFTRST_CON60_ARESETN_HDCP1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON60_HRESETN_HDCP1_SHIFT (6U) +#define CRU_SOFTRST_CON60_HRESETN_HDCP1_MASK (0x1U << CRU_SOFTRST_CON60_HRESETN_HDCP1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON60_RESETN_HDCP1_SHIFT (8U) +#define CRU_SOFTRST_CON60_RESETN_HDCP1_MASK (0x1U << CRU_SOFTRST_CON60_RESETN_HDCP1_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON60_PRESETN_TRNG1_SHIFT (10U) +#define CRU_SOFTRST_CON60_PRESETN_TRNG1_MASK (0x1U << CRU_SOFTRST_CON60_PRESETN_TRNG1_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON60_PRESETN_HDMITX0_SHIFT (11U) +#define CRU_SOFTRST_CON60_PRESETN_HDMITX0_MASK (0x1U << CRU_SOFTRST_CON60_PRESETN_HDMITX0_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON61 */ +#define CRU_SOFTRST_CON61_OFFSET (0xAF4U) +#define CRU_SOFTRST_CON61_RESETN_HDMITX0_REF_SHIFT (0U) +#define CRU_SOFTRST_CON61_RESETN_HDMITX0_REF_MASK (0x1U << CRU_SOFTRST_CON61_RESETN_HDMITX0_REF_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON61_PRESETN_HDMITX1_SHIFT (2U) +#define CRU_SOFTRST_CON61_PRESETN_HDMITX1_MASK (0x1U << CRU_SOFTRST_CON61_PRESETN_HDMITX1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON61_RESETN_HDMITX1_REF_SHIFT (7U) +#define CRU_SOFTRST_CON61_RESETN_HDMITX1_REF_MASK (0x1U << CRU_SOFTRST_CON61_RESETN_HDMITX1_REF_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON61_ARESETN_HDMIRX_SHIFT (9U) +#define CRU_SOFTRST_CON61_ARESETN_HDMIRX_MASK (0x1U << CRU_SOFTRST_CON61_ARESETN_HDMIRX_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON61_PRESETN_HDMIRX_SHIFT (10U) +#define CRU_SOFTRST_CON61_PRESETN_HDMIRX_MASK (0x1U << CRU_SOFTRST_CON61_PRESETN_HDMIRX_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON61_RESETN_HDMIRX_REF_SHIFT (11U) +#define CRU_SOFTRST_CON61_RESETN_HDMIRX_REF_MASK (0x1U << CRU_SOFTRST_CON61_RESETN_HDMIRX_REF_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON62 */ +#define CRU_SOFTRST_CON62_OFFSET (0xAF8U) +#define CRU_SOFTRST_CON62_PRESETN_EDP0_SHIFT (0U) +#define CRU_SOFTRST_CON62_PRESETN_EDP0_MASK (0x1U << CRU_SOFTRST_CON62_PRESETN_EDP0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON62_RESETN_EDP0_24M_SHIFT (1U) +#define CRU_SOFTRST_CON62_RESETN_EDP0_24M_MASK (0x1U << CRU_SOFTRST_CON62_RESETN_EDP0_24M_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON62_PRESETN_EDP1_SHIFT (3U) +#define CRU_SOFTRST_CON62_PRESETN_EDP1_MASK (0x1U << CRU_SOFTRST_CON62_PRESETN_EDP1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON62_RESETN_EDP1_24M_SHIFT (4U) +#define CRU_SOFTRST_CON62_RESETN_EDP1_24M_MASK (0x1U << CRU_SOFTRST_CON62_RESETN_EDP1_24M_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON62_MRESETN_I2S5_8CH_TX_SHIFT (8U) +#define CRU_SOFTRST_CON62_MRESETN_I2S5_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON62_MRESETN_I2S5_8CH_TX_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON62_HRESETN_I2S5_8CH_SHIFT (12U) +#define CRU_SOFTRST_CON62_HRESETN_I2S5_8CH_MASK (0x1U << CRU_SOFTRST_CON62_HRESETN_I2S5_8CH_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON62_MRESETN_I2S6_8CH_TX_SHIFT (15U) +#define CRU_SOFTRST_CON62_MRESETN_I2S6_8CH_TX_MASK (0x1U << CRU_SOFTRST_CON62_MRESETN_I2S6_8CH_TX_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON63 */ +#define CRU_SOFTRST_CON63_OFFSET (0xAFCU) +#define CRU_SOFTRST_CON63_MRESETN_I2S6_8CH_RX_SHIFT (2U) +#define CRU_SOFTRST_CON63_MRESETN_I2S6_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON63_MRESETN_I2S6_8CH_RX_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON63_HRESETN_I2S6_8CH_SHIFT (3U) +#define CRU_SOFTRST_CON63_HRESETN_I2S6_8CH_MASK (0x1U << CRU_SOFTRST_CON63_HRESETN_I2S6_8CH_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON63_HRESETN_SPDIF3_SHIFT (4U) +#define CRU_SOFTRST_CON63_HRESETN_SPDIF3_MASK (0x1U << CRU_SOFTRST_CON63_HRESETN_SPDIF3_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON63_MRESETN_SPDIF3_SHIFT (7U) +#define CRU_SOFTRST_CON63_MRESETN_SPDIF3_MASK (0x1U << CRU_SOFTRST_CON63_MRESETN_SPDIF3_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON63_HRESETN_SPDIF4_SHIFT (8U) +#define CRU_SOFTRST_CON63_HRESETN_SPDIF4_MASK (0x1U << CRU_SOFTRST_CON63_HRESETN_SPDIF4_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON63_MRESETN_SPDIF4_SHIFT (11U) +#define CRU_SOFTRST_CON63_MRESETN_SPDIF4_MASK (0x1U << CRU_SOFTRST_CON63_MRESETN_SPDIF4_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON63_HRESETN_SPDIFRX0_SHIFT (12U) +#define CRU_SOFTRST_CON63_HRESETN_SPDIFRX0_MASK (0x1U << CRU_SOFTRST_CON63_HRESETN_SPDIFRX0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON63_MRESETN_SPDIFRX0_SHIFT (13U) +#define CRU_SOFTRST_CON63_MRESETN_SPDIFRX0_MASK (0x1U << CRU_SOFTRST_CON63_MRESETN_SPDIFRX0_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON63_HRESETN_SPDIFRX1_SHIFT (14U) +#define CRU_SOFTRST_CON63_HRESETN_SPDIFRX1_MASK (0x1U << CRU_SOFTRST_CON63_HRESETN_SPDIFRX1_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON63_MRESETN_SPDIFRX1_SHIFT (15U) +#define CRU_SOFTRST_CON63_MRESETN_SPDIFRX1_MASK (0x1U << CRU_SOFTRST_CON63_MRESETN_SPDIFRX1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON64 */ +#define CRU_SOFTRST_CON64_OFFSET (0xB00U) +#define CRU_SOFTRST_CON64_HRESETN_SPDIFRX2_SHIFT (0U) +#define CRU_SOFTRST_CON64_HRESETN_SPDIFRX2_MASK (0x1U << CRU_SOFTRST_CON64_HRESETN_SPDIFRX2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON64_MRESETN_SPDIFRX2_SHIFT (1U) +#define CRU_SOFTRST_CON64_MRESETN_SPDIFRX2_MASK (0x1U << CRU_SOFTRST_CON64_MRESETN_SPDIFRX2_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY0_SHIFT (12U) +#define CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY0_MASK (0x1U << CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY1_SHIFT (13U) +#define CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY1_MASK (0x1U << CRU_SOFTRST_CON64_RESETN_LINKSYM_HDMITXPHY1_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE0_SHIFT (14U) +#define CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE0_MASK (0x1U << CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE0_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE1_SHIFT (15U) +#define CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE1_MASK (0x1U << CRU_SOFTRST_CON64_RESETN_VO1_BRIDGE1_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON65 */ +#define CRU_SOFTRST_CON65_OFFSET (0xB04U) +#define CRU_SOFTRST_CON65_HRESETN_I2S9_8CH_SHIFT (0U) +#define CRU_SOFTRST_CON65_HRESETN_I2S9_8CH_MASK (0x1U << CRU_SOFTRST_CON65_HRESETN_I2S9_8CH_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON65_MRESETN_I2S9_8CH_RX_SHIFT (3U) +#define CRU_SOFTRST_CON65_MRESETN_I2S9_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON65_MRESETN_I2S9_8CH_RX_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON65_HRESETN_I2S10_8CH_SHIFT (4U) +#define CRU_SOFTRST_CON65_HRESETN_I2S10_8CH_MASK (0x1U << CRU_SOFTRST_CON65_HRESETN_I2S10_8CH_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON65_MRESETN_I2S10_8CH_RX_SHIFT (7U) +#define CRU_SOFTRST_CON65_MRESETN_I2S10_8CH_RX_MASK (0x1U << CRU_SOFTRST_CON65_MRESETN_I2S10_8CH_RX_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON65_PRESETN_S_HDMIRX_SHIFT (8U) +#define CRU_SOFTRST_CON65_PRESETN_S_HDMIRX_MASK (0x1U << CRU_SOFTRST_CON65_PRESETN_S_HDMIRX_SHIFT) /* 0x00000100 */ +/* SOFTRST_CON66 */ +#define CRU_SOFTRST_CON66_OFFSET (0xB08U) +#define CRU_SOFTRST_CON66_RESETN_GPU_SHIFT (4U) +#define CRU_SOFTRST_CON66_RESETN_GPU_MASK (0x1U << CRU_SOFTRST_CON66_RESETN_GPU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON66_SYSRESETN_GPU_SHIFT (5U) +#define CRU_SOFTRST_CON66_SYSRESETN_GPU_MASK (0x1U << CRU_SOFTRST_CON66_SYSRESETN_GPU_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON66_ARESETN_S_GPU_BIU_SHIFT (8U) +#define CRU_SOFTRST_CON66_ARESETN_S_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_ARESETN_S_GPU_BIU_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON66_ARESETN_M0_GPU_BIU_SHIFT (9U) +#define CRU_SOFTRST_CON66_ARESETN_M0_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_ARESETN_M0_GPU_BIU_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON66_ARESETN_M1_GPU_BIU_SHIFT (10U) +#define CRU_SOFTRST_CON66_ARESETN_M1_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_ARESETN_M1_GPU_BIU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON66_ARESETN_M2_GPU_BIU_SHIFT (11U) +#define CRU_SOFTRST_CON66_ARESETN_M2_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_ARESETN_M2_GPU_BIU_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON66_ARESETN_M3_GPU_BIU_SHIFT (12U) +#define CRU_SOFTRST_CON66_ARESETN_M3_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_ARESETN_M3_GPU_BIU_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON66_PRESETN_GPU_BIU_SHIFT (14U) +#define CRU_SOFTRST_CON66_PRESETN_GPU_BIU_MASK (0x1U << CRU_SOFTRST_CON66_PRESETN_GPU_BIU_SHIFT) /* 0x00004000 */ +#define CRU_SOFTRST_CON66_PRESETN_PVTM2_SHIFT (15U) +#define CRU_SOFTRST_CON66_PRESETN_PVTM2_MASK (0x1U << CRU_SOFTRST_CON66_PRESETN_PVTM2_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON67 */ +#define CRU_SOFTRST_CON67_OFFSET (0xB0CU) +#define CRU_SOFTRST_CON67_RESETN_PVTM2_SHIFT (0U) +#define CRU_SOFTRST_CON67_RESETN_PVTM2_MASK (0x1U << CRU_SOFTRST_CON67_RESETN_PVTM2_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON67_PRESETN_GPU_GRF_SHIFT (2U) +#define CRU_SOFTRST_CON67_PRESETN_GPU_GRF_MASK (0x1U << CRU_SOFTRST_CON67_PRESETN_GPU_GRF_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON67_RESETN_GPU_PVTPLL_SHIFT (3U) +#define CRU_SOFTRST_CON67_RESETN_GPU_PVTPLL_MASK (0x1U << CRU_SOFTRST_CON67_RESETN_GPU_PVTPLL_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON67_PORESETN_GPU_JTAG_SHIFT (4U) +#define CRU_SOFTRST_CON67_PORESETN_GPU_JTAG_MASK (0x1U << CRU_SOFTRST_CON67_PORESETN_GPU_JTAG_SHIFT) /* 0x00000010 */ +/* SOFTRST_CON68 */ +#define CRU_SOFTRST_CON68_OFFSET (0xB10U) +#define CRU_SOFTRST_CON68_ARESETN_AV1_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON68_ARESETN_AV1_BIU_MASK (0x1U << CRU_SOFTRST_CON68_ARESETN_AV1_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON68_ARESETN_AV1_SHIFT (2U) +#define CRU_SOFTRST_CON68_ARESETN_AV1_MASK (0x1U << CRU_SOFTRST_CON68_ARESETN_AV1_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON68_PRESETN_AV1_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON68_PRESETN_AV1_BIU_MASK (0x1U << CRU_SOFTRST_CON68_PRESETN_AV1_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON68_PRESETN_AV1_SHIFT (5U) +#define CRU_SOFTRST_CON68_PRESETN_AV1_MASK (0x1U << CRU_SOFTRST_CON68_PRESETN_AV1_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON69 */ +#define CRU_SOFTRST_CON69_OFFSET (0xB14U) +#define CRU_SOFTRST_CON69_ARESETN_DDR_BIU_SHIFT (4U) +#define CRU_SOFTRST_CON69_ARESETN_DDR_BIU_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_DDR_BIU_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON69_ARESETN_DMA2DDR_SHIFT (5U) +#define CRU_SOFTRST_CON69_ARESETN_DMA2DDR_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_DMA2DDR_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_SHIFT (6U) +#define CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_BIU_SHIFT (7U) +#define CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_BIU_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_DDR_SHAREMEM_BIU_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON69_ARESETN_CENTER_S200_BIU_SHIFT (10U) +#define CRU_SOFTRST_CON69_ARESETN_CENTER_S200_BIU_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_CENTER_S200_BIU_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON69_ARESETN_CENTER_S400_BIU_SHIFT (11U) +#define CRU_SOFTRST_CON69_ARESETN_CENTER_S400_BIU_MASK (0x1U << CRU_SOFTRST_CON69_ARESETN_CENTER_S400_BIU_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON69_HRESETN_AHB2APB_SHIFT (12U) +#define CRU_SOFTRST_CON69_HRESETN_AHB2APB_MASK (0x1U << CRU_SOFTRST_CON69_HRESETN_AHB2APB_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON69_HRESETN_CENTER_BIU_SHIFT (13U) +#define CRU_SOFTRST_CON69_HRESETN_CENTER_BIU_MASK (0x1U << CRU_SOFTRST_CON69_HRESETN_CENTER_BIU_SHIFT) /* 0x00002000 */ +#define CRU_SOFTRST_CON69_FRESETN_DDR_CM0_CORE_SHIFT (14U) +#define CRU_SOFTRST_CON69_FRESETN_DDR_CM0_CORE_MASK (0x1U << CRU_SOFTRST_CON69_FRESETN_DDR_CM0_CORE_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON70 */ +#define CRU_SOFTRST_CON70_OFFSET (0xB18U) +#define CRU_SOFTRST_CON70_RESETN_DDR_TIMER0_SHIFT (0U) +#define CRU_SOFTRST_CON70_RESETN_DDR_TIMER0_MASK (0x1U << CRU_SOFTRST_CON70_RESETN_DDR_TIMER0_SHIFT) /* 0x00000001 */ +#define CRU_SOFTRST_CON70_RESETN_DDR_TIMER1_SHIFT (1U) +#define CRU_SOFTRST_CON70_RESETN_DDR_TIMER1_MASK (0x1U << CRU_SOFTRST_CON70_RESETN_DDR_TIMER1_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON70_TRESETN_WDT_DDR_SHIFT (2U) +#define CRU_SOFTRST_CON70_TRESETN_WDT_DDR_MASK (0x1U << CRU_SOFTRST_CON70_TRESETN_WDT_DDR_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON70_TRESETN_DDR_CM0_JTAG_SHIFT (3U) +#define CRU_SOFTRST_CON70_TRESETN_DDR_CM0_JTAG_MASK (0x1U << CRU_SOFTRST_CON70_TRESETN_DDR_CM0_JTAG_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON70_PRESETN_CENTER_GRF_SHIFT (5U) +#define CRU_SOFTRST_CON70_PRESETN_CENTER_GRF_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_CENTER_GRF_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON70_PRESETN_AHB2APB_SHIFT (6U) +#define CRU_SOFTRST_CON70_PRESETN_AHB2APB_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_AHB2APB_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON70_PRESETN_WDT_SHIFT (7U) +#define CRU_SOFTRST_CON70_PRESETN_WDT_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_WDT_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON70_PRESETN_TIMER_SHIFT (8U) +#define CRU_SOFTRST_CON70_PRESETN_TIMER_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_TIMER_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON70_PRESETN_DMA2DDR_SHIFT (9U) +#define CRU_SOFTRST_CON70_PRESETN_DMA2DDR_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_DMA2DDR_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON70_PRESETN_SHAREMEM_SHIFT (10U) +#define CRU_SOFTRST_CON70_PRESETN_SHAREMEM_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_SHAREMEM_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON70_PRESETN_CENTER_BIU_SHIFT (11U) +#define CRU_SOFTRST_CON70_PRESETN_CENTER_BIU_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_CENTER_BIU_SHIFT) /* 0x00000800 */ +#define CRU_SOFTRST_CON70_PRESETN_CENTER_CHANNEL_BIU_SHIFT (12U) +#define CRU_SOFTRST_CON70_PRESETN_CENTER_CHANNEL_BIU_MASK (0x1U << CRU_SOFTRST_CON70_PRESETN_CENTER_CHANNEL_BIU_SHIFT) /* 0x00001000 */ +/* SOFTRST_CON72 */ +#define CRU_SOFTRST_CON72_OFFSET (0xB20U) +#define CRU_SOFTRST_CON72_PRESETN_USBDPGRF0_SHIFT (1U) +#define CRU_SOFTRST_CON72_PRESETN_USBDPGRF0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USBDPGRF0_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON72_PRESETN_USBDPPHY0_SHIFT (2U) +#define CRU_SOFTRST_CON72_PRESETN_USBDPPHY0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USBDPPHY0_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON72_PRESETN_USBDPGRF1_SHIFT (3U) +#define CRU_SOFTRST_CON72_PRESETN_USBDPGRF1_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USBDPGRF1_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON72_PRESETN_USBDPPHY1_SHIFT (4U) +#define CRU_SOFTRST_CON72_PRESETN_USBDPPHY1_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USBDPPHY1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON72_PRESETN_HDPTX0_SHIFT (5U) +#define CRU_SOFTRST_CON72_PRESETN_HDPTX0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_HDPTX0_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON72_PRESETN_HDPTX1_SHIFT (6U) +#define CRU_SOFTRST_CON72_PRESETN_HDPTX1_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_HDPTX1_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON72_PRESETN_APB2ASB_SLV_BOT_RIGHT_SHIFT (7U) +#define CRU_SOFTRST_CON72_PRESETN_APB2ASB_SLV_BOT_RIGHT_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_APB2ASB_SLV_BOT_RIGHT_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_0_GRF0_SHIFT (8U) +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_0_GRF0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_0_GRF0_SHIFT) /* 0x00000100 */ +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_1_GRF0_SHIFT (9U) +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_1_GRF0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USB2PHY_U3_1_GRF0_SHIFT) /* 0x00000200 */ +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_0_GRF0_SHIFT (10U) +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_0_GRF0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_0_GRF0_SHIFT) /* 0x00000400 */ +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_1_GRF0_SHIFT (11U) +#define CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_1_GRF0_MASK (0x1U << CRU_SOFTRST_CON72_PRESETN_USB2PHY_U2_1_GRF0_SHIFT) /* 0x00000800 */ +/* SOFTRST_CON73 */ +#define CRU_SOFTRST_CON73_OFFSET (0xB24U) +#define CRU_SOFTRST_CON73_RESETN_HDMIHDP0_SHIFT (12U) +#define CRU_SOFTRST_CON73_RESETN_HDMIHDP0_MASK (0x1U << CRU_SOFTRST_CON73_RESETN_HDMIHDP0_SHIFT) /* 0x00001000 */ +#define CRU_SOFTRST_CON73_RESETN_HDMIHDP1_SHIFT (13U) +#define CRU_SOFTRST_CON73_RESETN_HDMIHDP1_MASK (0x1U << CRU_SOFTRST_CON73_RESETN_HDMIHDP1_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON74 */ +#define CRU_SOFTRST_CON74_OFFSET (0xB28U) +#define CRU_SOFTRST_CON74_ARESETN_VO1USB_TOP_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON74_ARESETN_VO1USB_TOP_BIU_MASK (0x1U << CRU_SOFTRST_CON74_ARESETN_VO1USB_TOP_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON74_HRESETN_VO1USB_TOP_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON74_HRESETN_VO1USB_TOP_BIU_MASK (0x1U << CRU_SOFTRST_CON74_HRESETN_VO1USB_TOP_BIU_SHIFT) /* 0x00000008 */ +/* SOFTRST_CON75 */ +#define CRU_SOFTRST_CON75_OFFSET (0xB2CU) +#define CRU_SOFTRST_CON75_HRESETN_SDIO_BIU_SHIFT (1U) +#define CRU_SOFTRST_CON75_HRESETN_SDIO_BIU_MASK (0x1U << CRU_SOFTRST_CON75_HRESETN_SDIO_BIU_SHIFT) /* 0x00000002 */ +#define CRU_SOFTRST_CON75_HRESETN_SDIO_SHIFT (2U) +#define CRU_SOFTRST_CON75_HRESETN_SDIO_MASK (0x1U << CRU_SOFTRST_CON75_HRESETN_SDIO_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON75_RESETN_SDIO_SHIFT (3U) +#define CRU_SOFTRST_CON75_RESETN_SDIO_MASK (0x1U << CRU_SOFTRST_CON75_RESETN_SDIO_SHIFT) /* 0x00000008 */ +/* SOFTRST_CON76 */ +#define CRU_SOFTRST_CON76_OFFSET (0xB30U) +#define CRU_SOFTRST_CON76_HRESETN_RGA3_BIU_SHIFT (2U) +#define CRU_SOFTRST_CON76_HRESETN_RGA3_BIU_MASK (0x1U << CRU_SOFTRST_CON76_HRESETN_RGA3_BIU_SHIFT) /* 0x00000004 */ +#define CRU_SOFTRST_CON76_ARESETN_RGA3_BIU_SHIFT (3U) +#define CRU_SOFTRST_CON76_ARESETN_RGA3_BIU_MASK (0x1U << CRU_SOFTRST_CON76_ARESETN_RGA3_BIU_SHIFT) /* 0x00000008 */ +#define CRU_SOFTRST_CON76_HRESETN_RGA3_1_SHIFT (4U) +#define CRU_SOFTRST_CON76_HRESETN_RGA3_1_MASK (0x1U << CRU_SOFTRST_CON76_HRESETN_RGA3_1_SHIFT) /* 0x00000010 */ +#define CRU_SOFTRST_CON76_ARESETN_RGA3_1_SHIFT (5U) +#define CRU_SOFTRST_CON76_ARESETN_RGA3_1_MASK (0x1U << CRU_SOFTRST_CON76_ARESETN_RGA3_1_SHIFT) /* 0x00000020 */ +#define CRU_SOFTRST_CON76_RESETN_RGA3_1_CORE_SHIFT (6U) +#define CRU_SOFTRST_CON76_RESETN_RGA3_1_CORE_MASK (0x1U << CRU_SOFTRST_CON76_RESETN_RGA3_1_CORE_SHIFT) /* 0x00000040 */ +/* SOFTRST_CON77 */ +#define CRU_SOFTRST_CON77_OFFSET (0xB34U) +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY0_SHIFT (6U) +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY0_MASK (0x1U << CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY0_SHIFT) /* 0x00000040 */ +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY1_SHIFT (7U) +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY1_MASK (0x1U << CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY1_SHIFT) /* 0x00000080 */ +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY2_SHIFT (8U) +#define CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY2_MASK (0x1U << CRU_SOFTRST_CON77_RESETN_REF_PIPE_PHY2_SHIFT) /* 0x00000100 */ +/* GLB_CNT_TH */ +#define CRU_GLB_CNT_TH_OFFSET (0xC00U) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT (0U) +#define CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_MASK (0x3FFU << CRU_GLB_CNT_TH_GLOBAL_RESET_COUNTER_THRESHOLD_SHIFT) /* 0x000003FF */ +/* GLBRST_ST */ +#define CRU_GLBRST_ST_OFFSET (0xC04U) +#define CRU_GLBRST_ST_FIRST_GLBRST_REGISTER_RST_SHIFT (0U) +#define CRU_GLBRST_ST_FIRST_GLBRST_REGISTER_RST_MASK (0x1U << CRU_GLBRST_ST_FIRST_GLBRST_REGISTER_RST_SHIFT) /* 0x00000001 */ +#define CRU_GLBRST_ST_SECOND_GLBRST_REGISTER_RST_SHIFT (1U) +#define CRU_GLBRST_ST_SECOND_GLBRST_REGISTER_RST_MASK (0x1U << CRU_GLBRST_ST_SECOND_GLBRST_REGISTER_RST_SHIFT) /* 0x00000002 */ +#define CRU_GLBRST_ST_FIRST_GLBRST_TSADC_RST_SHIFT (2U) +#define CRU_GLBRST_ST_FIRST_GLBRST_TSADC_RST_MASK (0x1U << CRU_GLBRST_ST_FIRST_GLBRST_TSADC_RST_SHIFT) /* 0x00000004 */ +#define CRU_GLBRST_ST_SECOND_GLBRST_TSADC_RST_SHIFT (3U) +#define CRU_GLBRST_ST_SECOND_GLBRST_TSADC_RST_MASK (0x1U << CRU_GLBRST_ST_SECOND_GLBRST_TSADC_RST_SHIFT) /* 0x00000008 */ +#define CRU_GLBRST_ST_FIRST_GLBRST_WDT_RST_SHIFT (4U) +#define CRU_GLBRST_ST_FIRST_GLBRST_WDT_RST_MASK (0x1U << CRU_GLBRST_ST_FIRST_GLBRST_WDT_RST_SHIFT) /* 0x00000010 */ +#define CRU_GLBRST_ST_SECOND_GLBRST_WDT_RST_SHIFT (5U) +#define CRU_GLBRST_ST_SECOND_GLBRST_WDT_RST_MASK (0x1U << CRU_GLBRST_ST_SECOND_GLBRST_WDT_RST_SHIFT) /* 0x00000020 */ +#define CRU_GLBRST_ST_GLBRST_WDT_RST_SHIFT (6U) +#define CRU_GLBRST_ST_GLBRST_WDT_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT_RST_SHIFT) /* 0x00000040 */ +#define CRU_GLBRST_ST_GLBRST_OSC_CHK_RST_SHIFT (7U) +#define CRU_GLBRST_ST_GLBRST_OSC_CHK_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_OSC_CHK_RST_SHIFT) /* 0x00000080 */ +#define CRU_GLBRST_ST_GLBRST_PMUSGRF_CRC_CHK_RST_SHIFT (8U) +#define CRU_GLBRST_ST_GLBRST_PMUSGRF_CRC_CHK_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_PMUSGRF_CRC_CHK_RST_SHIFT) /* 0x00000100 */ +#define CRU_GLBRST_ST_GLBRST_DSUSGRF_CRC_CHK_RST_SHIFT (9U) +#define CRU_GLBRST_ST_GLBRST_DSUSGRF_CRC_CHK_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_DSUSGRF_CRC_CHK_RST_SHIFT) /* 0x00000200 */ +#define CRU_GLBRST_ST_GLBRST_SGRF_CRC_CHK_RST_SHIFT (10U) +#define CRU_GLBRST_ST_GLBRST_SGRF_CRC_CHK_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_SGRF_CRC_CHK_RST_SHIFT) /* 0x00000400 */ +#define CRU_GLBRST_ST_GLBRST_WDT0_RST_SHIFT (11U) +#define CRU_GLBRST_ST_GLBRST_WDT0_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT0_RST_SHIFT) /* 0x00000800 */ +#define CRU_GLBRST_ST_GLBRST_WDT1_RST_SHIFT (12U) +#define CRU_GLBRST_ST_GLBRST_WDT1_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT1_RST_SHIFT) /* 0x00001000 */ +#define CRU_GLBRST_ST_GLBRST_WDT2_RST_SHIFT (13U) +#define CRU_GLBRST_ST_GLBRST_WDT2_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT2_RST_SHIFT) /* 0x00002000 */ +#define CRU_GLBRST_ST_GLBRST_WDT3_RST_SHIFT (14U) +#define CRU_GLBRST_ST_GLBRST_WDT3_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT3_RST_SHIFT) /* 0x00004000 */ +#define CRU_GLBRST_ST_GLBRST_WDT4_RST_SHIFT (15U) +#define CRU_GLBRST_ST_GLBRST_WDT4_RST_MASK (0x1U << CRU_GLBRST_ST_GLBRST_WDT4_RST_SHIFT) /* 0x00008000 */ +/* GLB_SRST_FST_VALUE */ +#define CRU_GLB_SRST_FST_VALUE_OFFSET (0xC08U) +#define CRU_GLB_SRST_FST_VALUE_GLB_SRSC_FIRST_VALUE_SHIFT (0U) +#define CRU_GLB_SRST_FST_VALUE_GLB_SRSC_FIRST_VALUE_MASK (0xFFFFU << CRU_GLB_SRST_FST_VALUE_GLB_SRSC_FIRST_VALUE_SHIFT) /* 0x0000FFFF */ +/* GLB_SRST_SND_VALUE */ +#define CRU_GLB_SRST_SND_VALUE_OFFSET (0xC0CU) +#define CRU_GLB_SRST_SND_VALUE_GLB_SRSC_SECOND_VALUE_SHIFT (0U) +#define CRU_GLB_SRST_SND_VALUE_GLB_SRSC_SECOND_VALUE_MASK (0xFFFFU << CRU_GLB_SRST_SND_VALUE_GLB_SRSC_SECOND_VALUE_SHIFT) /* 0x0000FFFF */ +/* GLB_RST_CON */ +#define CRU_GLB_RST_CON_OFFSET (0xC10U) +#define CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_SEL_SHIFT (0U) +#define CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_SEL_SHIFT) /* 0x00000001 */ +#define CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_EN_SHIFT (1U) +#define CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_TSADC_TRIG_GLBRST_EN_SHIFT) /* 0x00000002 */ +#define CRU_GLB_RST_CON_GLBRST_TRIG_PMU_SEL_SHIFT (2U) +#define CRU_GLB_RST_CON_GLBRST_TRIG_PMU_SEL_MASK (0x1U << CRU_GLB_RST_CON_GLBRST_TRIG_PMU_SEL_SHIFT) /* 0x00000004 */ +#define CRU_GLB_RST_CON_GLBRST_TRIG_PMU_EN_SHIFT (3U) +#define CRU_GLB_RST_CON_GLBRST_TRIG_PMU_EN_MASK (0x1U << CRU_GLB_RST_CON_GLBRST_TRIG_PMU_EN_SHIFT) /* 0x00000008 */ +#define CRU_GLB_RST_CON_WDT_TRIG_PMU_EN_SHIFT (4U) +#define CRU_GLB_RST_CON_WDT_TRIG_PMU_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_TRIG_PMU_EN_SHIFT) /* 0x00000010 */ +#define CRU_GLB_RST_CON_WDT_TRIG_GLBRST_EN_SHIFT (6U) +#define CRU_GLB_RST_CON_WDT_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_WDT_TRIG_GLBRST_EN_SHIFT) /* 0x00000040 */ +#define CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_EN_SHIFT (7U) +#define CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_EN_SHIFT) /* 0x00000080 */ +#define CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_EN_SHIFT (8U) +#define CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_EN_SHIFT) /* 0x00000100 */ +#define CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_EN_SHIFT (9U) +#define CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_EN_SHIFT) /* 0x00000200 */ +#define CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_EN_SHIFT (10U) +#define CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_EN_MASK (0x1U << CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_EN_SHIFT) /* 0x00000400 */ +#define CRU_GLB_RST_CON_WDT_TRIG_GLBRST_SEL_SHIFT (11U) +#define CRU_GLB_RST_CON_WDT_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_WDT_TRIG_GLBRST_SEL_SHIFT) /* 0x00000800 */ +#define CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_SEL_SHIFT (12U) +#define CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_OSC_CHK_TRIG_GLBRST_SEL_SHIFT) /* 0x00001000 */ +#define CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_SEL_SHIFT (13U) +#define CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_CRC_PMUSGRF_CHK_TRIG_GLBRST_SEL_SHIFT) /* 0x00002000 */ +#define CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_SEL_SHIFT (14U) +#define CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_CRC_DSUSGRF_CHK_TRIG_GLBRST_SEL_SHIFT) /* 0x00004000 */ +#define CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_SEL_SHIFT (15U) +#define CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_SEL_MASK (0x1U << CRU_GLB_RST_CON_CRC_SGRF_CHK_TRIG_GLBRST_SEL_SHIFT) /* 0x00008000 */ +/* SDIO_CON0 */ +#define CRU_SDIO_CON0_OFFSET (0xC24U) +#define CRU_SDIO_CON0_SDIO_CON0_SHIFT (0U) +#define CRU_SDIO_CON0_SDIO_CON0_MASK (0xFFFFU << CRU_SDIO_CON0_SDIO_CON0_SHIFT) /* 0x0000FFFF */ +/* SDIO_CON1 */ +#define CRU_SDIO_CON1_OFFSET (0xC28U) +#define CRU_SDIO_CON1_SDIO_CON1_SHIFT (0U) +#define CRU_SDIO_CON1_SDIO_CON1_MASK (0xFFFFU << CRU_SDIO_CON1_SDIO_CON1_SHIFT) /* 0x0000FFFF */ +/* SDMMC_CON0 */ +#define CRU_SDMMC_CON0_OFFSET (0xC30U) +#define CRU_SDMMC_CON0_SDMMC_CON0_SHIFT (0U) +#define CRU_SDMMC_CON0_SDMMC_CON0_MASK (0xFFFFU << CRU_SDMMC_CON0_SDMMC_CON0_SHIFT) /* 0x0000FFFF */ +/* SDMMC_CON1 */ +#define CRU_SDMMC_CON1_OFFSET (0xC34U) +#define CRU_SDMMC_CON1_SDMMC_CON1_SHIFT (0U) +#define CRU_SDMMC_CON1_SDMMC_CON1_MASK (0xFFFFU << CRU_SDMMC_CON1_SDMMC_CON1_SHIFT) /* 0x0000FFFF */ +/* PHYREF_ALT_GATE_CON */ +#define CRU_PHYREF_ALT_GATE_CON_OFFSET (0xC38U) +#define CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_P_EN_SHIFT (0U) +#define CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_P_EN_MASK (0x1U << CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_P_EN_SHIFT) /* 0x00000001 */ +#define CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_M_EN_SHIFT (1U) +#define CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_M_EN_MASK (0x1U << CRU_PHYREF_ALT_GATE_CON_PHY0_REF_ALT_CLK_M_EN_SHIFT) /* 0x00000002 */ +#define CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_P_EN_SHIFT (2U) +#define CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_P_EN_MASK (0x1U << CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_P_EN_SHIFT) /* 0x00000004 */ +#define CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_M_EN_SHIFT (3U) +#define CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_M_EN_MASK (0x1U << CRU_PHYREF_ALT_GATE_CON_PHY1_REF_ALT_CLK_M_EN_SHIFT) /* 0x00000008 */ +/* CM0_GATEMASK_CON */ +#define CRU_CM0_GATEMASK_CON_OFFSET (0xC3CU) +#define CRU_CM0_GATEMASK_CON_NPUCM0_DCLK_CM0S_EN_SHIFT (0U) +#define CRU_CM0_GATEMASK_CON_NPUCM0_DCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_NPUCM0_DCLK_CM0S_EN_SHIFT) /* 0x00000001 */ +#define CRU_CM0_GATEMASK_CON_NPUCM0_HCLK_CM0S_EN_SHIFT (1U) +#define CRU_CM0_GATEMASK_CON_NPUCM0_HCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_NPUCM0_HCLK_CM0S_EN_SHIFT) /* 0x00000002 */ +#define CRU_CM0_GATEMASK_CON_NPUCM0_SCLK_CM0S_EN_SHIFT (2U) +#define CRU_CM0_GATEMASK_CON_NPUCM0_SCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_NPUCM0_SCLK_CM0S_EN_SHIFT) /* 0x00000004 */ +#define CRU_CM0_GATEMASK_CON_DDRCM0_DCLK_CM0S_EN_SHIFT (3U) +#define CRU_CM0_GATEMASK_CON_DDRCM0_DCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_DDRCM0_DCLK_CM0S_EN_SHIFT) /* 0x00000008 */ +#define CRU_CM0_GATEMASK_CON_DDRCM0_HCLK_CM0S_EN_SHIFT (4U) +#define CRU_CM0_GATEMASK_CON_DDRCM0_HCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_DDRCM0_HCLK_CM0S_EN_SHIFT) /* 0x00000010 */ +#define CRU_CM0_GATEMASK_CON_DDRCM0_SCLK_CM0S_EN_SHIFT (5U) +#define CRU_CM0_GATEMASK_CON_DDRCM0_SCLK_CM0S_EN_MASK (0x1U << CRU_CM0_GATEMASK_CON_DDRCM0_SCLK_CM0S_EN_SHIFT) /* 0x00000020 */ +/* QCHANNEL_CON01 */ +#define CRU_QCHANNEL_CON01_OFFSET (0xCA4U) +#define CRU_QCHANNEL_CON01_ACLK_GIC_QC_EN_SHIFT (0U) +#define CRU_QCHANNEL_CON01_ACLK_GIC_QC_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_GIC_QC_EN_SHIFT) /* 0x00000001 */ +#define CRU_QCHANNEL_CON01_ACLK_GIC_QC_GATE_EN_SHIFT (1U) +#define CRU_QCHANNEL_CON01_ACLK_GIC_QC_GATE_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_GIC_QC_GATE_EN_SHIFT) /* 0x00000002 */ +#define CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_EN_SHIFT (2U) +#define CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_EN_SHIFT) /* 0x00000004 */ +#define CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_GATE_EN_SHIFT (3U) +#define CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_GATE_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_GICADB_GIC2CORE_BUS_QC_GATE_EN_SHIFT) /* 0x00000008 */ +#define CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_EN_SHIFT (4U) +#define CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_EN_SHIFT) /* 0x00000010 */ +#define CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_GATE_EN_SHIFT (5U) +#define CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_GATE_EN_MASK (0x1U << CRU_QCHANNEL_CON01_ACLK_PHP_GIC_ITS_QC_GATE_EN_SHIFT) /* 0x00000020 */ +#define CRU_QCHANNEL_CON01_CLK_GPU_QC_EN_SHIFT (6U) +#define CRU_QCHANNEL_CON01_CLK_GPU_QC_EN_MASK (0x1U << CRU_QCHANNEL_CON01_CLK_GPU_QC_EN_SHIFT) /* 0x00000040 */ +#define CRU_QCHANNEL_CON01_CLK_GPU_QC_GATE_EN_SHIFT (7U) +#define CRU_QCHANNEL_CON01_CLK_GPU_QC_GATE_EN_MASK (0x1U << CRU_QCHANNEL_CON01_CLK_GPU_QC_GATE_EN_SHIFT) /* 0x00000080 */ +/* SMOTH_DIVFREE_CON08 */ +#define CRU_SMOTH_DIVFREE_CON08_OFFSET (0xCC0U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_STEP_SHIFT (0U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_STEP_MASK (0x1FU << CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_STEP_SHIFT) /* 0x0000001F */ +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_SMDIV_CLK_OFF_SHIFT (13U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_SMDIV_CLK_OFF_MASK (0x1U << CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_GATE_SMTH_EN_SHIFT (14U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_GATE_SMTH_EN_MASK (0x1U << CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_BYPASS_SHIFT (15U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_BYPASS_MASK (0x1U << CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_BYPASS_SHIFT) /* 0x00008000 */ +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_FREQ_KEEP_SHIFT (16U) +#define CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_FREQ_KEEP_MASK (0xFFFFU << CRU_SMOTH_DIVFREE_CON08_ACLK_M0_GPU_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON09 */ +#define CRU_SMOTH_DIVFREE_CON09_OFFSET (0xCC4U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_STEP_SHIFT (0U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_STEP_MASK (0x1FU << CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_STEP_SHIFT) /* 0x0000001F */ +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_SMDIV_CLK_OFF_SHIFT (13U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_SMDIV_CLK_OFF_MASK (0x1U << CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_GATE_SMTH_EN_SHIFT (14U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_GATE_SMTH_EN_MASK (0x1U << CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_BYPASS_SHIFT (15U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_BYPASS_MASK (0x1U << CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_BYPASS_SHIFT) /* 0x00008000 */ +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_FREQ_KEEP_SHIFT (16U) +#define CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_FREQ_KEEP_MASK (0xFFFFU << CRU_SMOTH_DIVFREE_CON09_ACLK_M1_GPU_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON10 */ +#define CRU_SMOTH_DIVFREE_CON10_OFFSET (0xCC8U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_STEP_SHIFT (0U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_STEP_MASK (0x1FU << CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_STEP_SHIFT) /* 0x0000001F */ +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_SMDIV_CLK_OFF_SHIFT (13U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_SMDIV_CLK_OFF_MASK (0x1U << CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_GATE_SMTH_EN_SHIFT (14U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_GATE_SMTH_EN_MASK (0x1U << CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_BYPASS_SHIFT (15U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_BYPASS_MASK (0x1U << CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_BYPASS_SHIFT) /* 0x00008000 */ +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_FREQ_KEEP_SHIFT (16U) +#define CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_FREQ_KEEP_MASK (0xFFFFU << CRU_SMOTH_DIVFREE_CON10_ACLK_M2_GPU_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON11 */ +#define CRU_SMOTH_DIVFREE_CON11_OFFSET (0xCCCU) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_STEP_SHIFT (0U) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_STEP_MASK (0x1FU << CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_STEP_SHIFT) /* 0x0000001F */ +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_SMDIV_CLK_OFF_SHIFT (13U) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_SMDIV_CLK_OFF_MASK (0x1U << CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_GATE_SMTH_EN_SHIFT (14U) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_GATE_SMTH_EN_MASK (0x1U << CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_BYPASS_SHIFT (15U) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_BYPASS_MASK (0x1U << CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_BYPASS_SHIFT) /* 0x00008000 */ +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_FREQ_KEEP_SHIFT (16U) +#define CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_FREQ_KEEP_MASK (0xFFFFU << CRU_SMOTH_DIVFREE_CON11_ACLK_M3_GPU_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON12 */ +#define CRU_SMOTH_DIVFREE_CON12_OFFSET (0xCD0U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_STEP_SHIFT (0U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_STEP_MASK (0x1FU << CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_STEP_SHIFT) /* 0x0000001F */ +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_SMDIV_CLK_OFF_SHIFT (13U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_SMDIV_CLK_OFF_MASK (0x1U << CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_GATE_SMTH_EN_SHIFT (14U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_GATE_SMTH_EN_MASK (0x1U << CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_BYPASS_SHIFT (15U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_BYPASS_MASK (0x1U << CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_BYPASS_SHIFT) /* 0x00008000 */ +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_FREQ_KEEP_SHIFT (16U) +#define CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_FREQ_KEEP_MASK (0xFFFFU << CRU_SMOTH_DIVFREE_CON12_CLK_RKNN_DSU0_SRC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON0_OFFSET (0xD00U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_ROOT_CON0_ACLK_TOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_OFFSET (0xD04U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_ROOT_CON1_ACLK_TOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_LOW_TOP_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_OFFSET (0xD08U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON0_ACLK_LOW_TOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_LOW_TOP_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_OFFSET (0xD0CU) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_LOW_TOP_ROOT_CON1_ACLK_LOW_TOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_TOP_M400_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_OFFSET (0xD10U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON0_ACLK_TOP_M400_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_M400_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_OFFSET (0xD14U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_M400_ROOT_CON1_ACLK_TOP_M400_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_TOP_S400_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_OFFSET (0xD18U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON0_ACLK_TOP_S400_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_S400_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_OFFSET (0xD1CU) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_S400_ROOT_CON1_ACLK_TOP_S400_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_BUS_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON0_OFFSET (0xD20U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_BUS_ROOT_CON0_ACLK_BUS_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_BUS_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_OFFSET (0xD24U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_BUS_ROOT_CON1_ACLK_BUS_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_ISP1_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_OFFSET (0xD28U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_ISP1_ROOT_CON0_ACLK_ISP1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_ISP1_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_OFFSET (0xD2CU) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_ISP1_ROOT_CON1_ACLK_ISP1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_CLK_RKNN_DSU0_CON0 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON0_OFFSET (0xD30U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_CON0_CLK_RKNN_DSU0_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_RKNN_DSU0_CON1 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_OFFSET (0xD34U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_CLK_RKNN_DSU0_CON1_CLK_RKNN_DSU0_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RKNN_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_OFFSET (0xD38U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKNN_ROOT_CON0_HCLK_RKNN_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RKNN_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_OFFSET (0xD3CU) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RKNN_ROOT_CON1_HCLK_RKNN_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_NVM_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON0_OFFSET (0xD40U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_NVM_ROOT_CON0_ACLK_NVM_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_NVM_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_OFFSET (0xD44U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_NVM_ROOT_CON1_ACLK_NVM_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_PHP_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON0_OFFSET (0xD48U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_PHP_ROOT_CON0_ACLK_PHP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_PHP_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_OFFSET (0xD4CU) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_PHP_ROOT_CON1_ACLK_PHP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RKVDEC0_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_OFFSET (0xD50U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON0_ACLK_RKVDEC0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RKVDEC0_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_OFFSET (0xD54U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RKVDEC0_ROOT_CON1_ACLK_RKVDEC0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RKVDEC_CCU_CON0 */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_OFFSET (0xD58U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON0_ACLK_RKVDEC_CCU_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RKVDEC_CCU_CON1 */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_OFFSET (0xD5CU) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RKVDEC_CCU_CON1_ACLK_RKVDEC_CCU_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RKVDEC1_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_OFFSET (0xD60U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON0_ACLK_RKVDEC1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RKVDEC1_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_OFFSET (0xD64U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RKVDEC1_ROOT_CON1_ACLK_RKVDEC1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_USB_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON0_OFFSET (0xD68U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_USB_ROOT_CON0_ACLK_USB_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_USB_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_OFFSET (0xD6CU) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_USB_ROOT_CON1_ACLK_USB_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VDPU_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_OFFSET (0xD70U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VDPU_ROOT_CON0_ACLK_VDPU_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VDPU_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_OFFSET (0xD74U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VDPU_ROOT_CON1_ACLK_VDPU_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VDPU_LOW_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_OFFSET (0xD78U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON0_ACLK_VDPU_LOW_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VDPU_LOW_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_OFFSET (0xD7CU) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VDPU_LOW_ROOT_CON1_ACLK_VDPU_LOW_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_OFFSET (0xD80U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON0_ACLK_JPEG_DECODER_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_OFFSET (0xD84U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_JPEG_DECODER_ROOT_CON1_ACLK_JPEG_DECODER_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RKVENC0_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_OFFSET (0xD88U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON0_ACLK_RKVENC0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RKVENC0_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_OFFSET (0xD8CU) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RKVENC0_ROOT_CON1_ACLK_RKVENC0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RKVENC1_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_OFFSET (0xD90U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON0_ACLK_RKVENC1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RKVENC1_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_OFFSET (0xD94U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RKVENC1_ROOT_CON1_ACLK_RKVENC1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VI_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON0_OFFSET (0xD98U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VI_ROOT_CON0_ACLK_VI_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VI_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_OFFSET (0xD9CU) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VI_ROOT_CON1_ACLK_VI_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VOP_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON0_OFFSET (0xDA0U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VOP_ROOT_CON0_ACLK_VOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VOP_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_OFFSET (0xDA4U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VOP_ROOT_CON1_ACLK_VOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VO0_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON0_OFFSET (0xDA8U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VO0_ROOT_CON0_ACLK_VO0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VO0_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_OFFSET (0xDACU) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VO0_ROOT_CON1_ACLK_VO0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_HDCP1_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_OFFSET (0xDB0U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON0_ACLK_HDCP1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_HDCP1_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_OFFSET (0xDB4U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_HDCP1_ROOT_CON1_ACLK_HDCP1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_HDMIRX_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_OFFSET (0xDB8U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON0_ACLK_HDMIRX_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_HDMIRX_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_OFFSET (0xDBCU) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_HDMIRX_ROOT_CON1_ACLK_HDMIRX_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_CLK_GPU_COREGROUP_CON0 */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_OFFSET (0xDC0U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_GPU_COREGROUP_CON0_CLK_GPU_COREGROUP_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_GPU_COREGROUP_CON1 */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_OFFSET (0xDC4U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_CLK_GPU_COREGROUP_CON1_CLK_GPU_COREGROUP_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_AV1_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON0_OFFSET (0xDE0U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_AV1_ROOT_CON0_ACLK_AV1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_AV1_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_OFFSET (0xDE4U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_AV1_ROOT_CON1_ACLK_AV1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_CENTER_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_OFFSET (0xDE8U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_ROOT_CON0_ACLK_CENTER_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_CENTER_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_OFFSET (0xDECU) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_CENTER_ROOT_CON1_ACLK_CENTER_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_CENTER_LOW_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_OFFSET (0xDF0U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON0_ACLK_CENTER_LOW_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_CENTER_LOW_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_OFFSET (0xDF4U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_CENTER_LOW_ROOT_CON1_ACLK_CENTER_LOW_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_CENTER_S400_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_OFFSET (0xDF8U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON0_ACLK_CENTER_S400_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_CENTER_S400_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_OFFSET (0xDFCU) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_CENTER_S400_ROOT_CON1_ACLK_CENTER_S400_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_OFFSET (0xE00U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON0_ACLK_VO1USB_TOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_OFFSET (0xE04U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VO1USB_TOP_ROOT_CON1_ACLK_VO1USB_TOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_RGA3_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_OFFSET (0xE08U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_RGA3_ROOT_CON0_ACLK_RGA3_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_RGA3_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_OFFSET (0xE0CU) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_RGA3_ROOT_CON1_ACLK_RGA3_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_AV1_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON0_OFFSET (0xE10U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_AV1_ROOT_CON0_PCLK_AV1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_AV1_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_OFFSET (0xE14U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_AV1_ROOT_CON1_PCLK_AV1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_ISP1_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_OFFSET (0xE18U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_ISP1_ROOT_CON0_HCLK_ISP1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_ISP1_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_OFFSET (0xE1CU) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_ISP1_ROOT_CON1_HCLK_ISP1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_NPUTOP_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_OFFSET (0xE20U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON0_PCLK_NPUTOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_NPUTOP_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_OFFSET (0xE24U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_NPUTOP_ROOT_CON1_PCLK_NPUTOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_NPU_CM0_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_OFFSET (0xE28U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON0_HCLK_NPU_CM0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_NPU_CM0_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_OFFSET (0xE2CU) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_NPU_CM0_ROOT_CON1_HCLK_NPU_CM0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_NVM_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON0_OFFSET (0xE30U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_NVM_ROOT_CON0_HCLK_NVM_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_NVM_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_OFFSET (0xE34U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_NVM_ROOT_CON1_HCLK_NVM_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_PHP_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON0_OFFSET (0xE38U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_PHP_ROOT_CON0_PCLK_PHP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_PHP_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_OFFSET (0xE3CU) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_PHP_ROOT_CON1_PCLK_PHP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_PCIE_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_OFFSET (0xE40U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_PCIE_ROOT_CON0_ACLK_PCIE_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_PCIE_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_OFFSET (0xE44U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_PCIE_ROOT_CON1_ACLK_PCIE_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RKVDEC0_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_OFFSET (0xE48U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON0_HCLK_RKVDEC0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RKVDEC0_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_OFFSET (0xE4CU) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RKVDEC0_ROOT_CON1_HCLK_RKVDEC0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RKVDEC1_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_OFFSET (0xE50U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON0_HCLK_RKVDEC1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RKVDEC1_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_OFFSET (0xE54U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RKVDEC1_ROOT_CON1_HCLK_RKVDEC1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_TOP_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON0_OFFSET (0xE58U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_TOP_ROOT_CON0_PCLK_TOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_TOP_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_OFFSET (0xE5CU) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_TOP_ROOT_CON1_PCLK_TOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_TOP_M500_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_OFFSET (0xE60U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON0_ACLK_TOP_M500_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_M500_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_OFFSET (0xE64U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_M500_ROOT_CON1_ACLK_TOP_M500_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_TOP_S200_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_OFFSET (0xE68U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON0_ACLK_TOP_S200_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_S200_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_OFFSET (0xE6CU) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_S200_ROOT_CON1_ACLK_TOP_S200_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_USB_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON0_OFFSET (0xE70U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_USB_ROOT_CON0_HCLK_USB_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_USB_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_OFFSET (0xE74U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_USB_ROOT_CON1_HCLK_USB_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VDPU_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_OFFSET (0xE78U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VDPU_ROOT_CON0_HCLK_VDPU_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VDPU_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_OFFSET (0xE7CU) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VDPU_ROOT_CON1_HCLK_VDPU_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RKVENC0_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_OFFSET (0xE80U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON0_HCLK_RKVENC0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RKVENC0_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_OFFSET (0xE84U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RKVENC0_ROOT_CON1_HCLK_RKVENC0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RKVENC1_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_OFFSET (0xE88U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON0_HCLK_RKVENC1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RKVENC1_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_OFFSET (0xE8CU) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RKVENC1_ROOT_CON1_HCLK_RKVENC1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VI_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON0_OFFSET (0xE90U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VI_ROOT_CON0_HCLK_VI_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VI_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_OFFSET (0xE94U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VI_ROOT_CON1_HCLK_VI_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VI_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON0_OFFSET (0xE98U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VI_ROOT_CON0_PCLK_VI_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VI_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_OFFSET (0xE9CU) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VI_ROOT_CON1_PCLK_VI_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_VOP_LOW_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_OFFSET (0xEA0U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON0_ACLK_VOP_LOW_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_VOP_LOW_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_OFFSET (0xEA4U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_VOP_LOW_ROOT_CON1_ACLK_VOP_LOW_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VOP_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON0_OFFSET (0xEA8U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VOP_ROOT_CON0_HCLK_VOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VOP_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_OFFSET (0xEACU) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VOP_ROOT_CON1_HCLK_VOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VOP_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON0_OFFSET (0xEB0U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VOP_ROOT_CON0_PCLK_VOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VOP_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_OFFSET (0xEB4U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VOP_ROOT_CON1_PCLK_VOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VO0_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON0_OFFSET (0xEB8U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO0_ROOT_CON0_HCLK_VO0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VO0_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_OFFSET (0xEBCU) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VO0_ROOT_CON1_HCLK_VO0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VO0_S_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_OFFSET (0xEC0U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON0_HCLK_VO0_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VO0_S_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_OFFSET (0xEC4U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VO0_S_ROOT_CON1_HCLK_VO0_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VO0_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON0_OFFSET (0xEC8U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO0_ROOT_CON0_PCLK_VO0_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VO0_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_OFFSET (0xECCU) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VO0_ROOT_CON1_PCLK_VO0_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VO0_S_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_OFFSET (0xED0U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON0_PCLK_VO0_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VO0_S_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_OFFSET (0xED4U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VO0_S_ROOT_CON1_PCLK_VO0_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VO1_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON0_OFFSET (0xED8U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1_ROOT_CON0_HCLK_VO1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VO1_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_OFFSET (0xEDCU) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VO1_ROOT_CON1_HCLK_VO1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VO1_S_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_OFFSET (0xEE0U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON0_HCLK_VO1_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VO1_S_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_OFFSET (0xEE4U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VO1_S_ROOT_CON1_HCLK_VO1_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VO1_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON0_OFFSET (0xEE8U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO1_ROOT_CON0_PCLK_VO1_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VO1_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_OFFSET (0xEECU) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VO1_ROOT_CON1_PCLK_VO1_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_VO1_S_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_OFFSET (0xEF0U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON0_PCLK_VO1_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_VO1_S_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_OFFSET (0xEF4U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_VO1_S_ROOT_CON1_PCLK_VO1_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_GPU_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON0_OFFSET (0xEF8U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_GPU_ROOT_CON0_PCLK_GPU_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_GPU_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_OFFSET (0xEFCU) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_GPU_ROOT_CON1_PCLK_GPU_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_CENTER_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_OFFSET (0xF00U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_CENTER_ROOT_CON0_HCLK_CENTER_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_CENTER_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_OFFSET (0xF04U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_CENTER_ROOT_CON1_HCLK_CENTER_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_CENTER_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_OFFSET (0xF08U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_CENTER_ROOT_CON0_PCLK_CENTER_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_CENTER_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_OFFSET (0xF0CU) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_CENTER_ROOT_CON1_PCLK_CENTER_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_CENTER_S200_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_OFFSET (0xF10U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON0_ACLK_CENTER_S200_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_CENTER_S200_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_OFFSET (0xF14U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_CENTER_S200_ROOT_CON1_ACLK_CENTER_S200_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_SDIO_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_OFFSET (0xF18U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_SDIO_ROOT_CON0_HCLK_SDIO_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_SDIO_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_OFFSET (0xF1CU) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_SDIO_ROOT_CON1_HCLK_SDIO_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_RGA3_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_OFFSET (0xF20U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_RGA3_ROOT_CON0_HCLK_RGA3_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_RGA3_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_OFFSET (0xF24U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_RGA3_ROOT_CON1_HCLK_RGA3_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_OFFSET (0xF28U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON0_HCLK_VO1USB_TOP_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_OFFSET (0xF2CU) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_VO1USB_TOP_ROOT_CON1_HCLK_VO1USB_TOP_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_TOP_M300_ROOT_CON0 */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_OFFSET (0xF30U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON0_ACLK_TOP_M300_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_TOP_M300_ROOT_CON1 */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_OFFSET (0xF34U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_ACLK_TOP_M300_ROOT_CON1_ACLK_TOP_M300_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_OFFSET (0xF38U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON0_CLK_RKNN_DSU0_SRC_T_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_OFFSET (0xF3CU) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_CLK_RKNN_DSU0_SRC_T_CON1_CLK_RKNN_DSU0_SRC_T_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_AUDIO_ROOT_CON0 */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_OFFSET (0xF40U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON0_HCLK_AUDIO_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_AUDIO_ROOT_CON1 */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_OFFSET (0xF44U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_HCLK_AUDIO_ROOT_CON1_HCLK_AUDIO_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_AUDIO_ROOT_CON0 */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_OFFSET (0xF48U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_IDLE_TH_SHIFT (0U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_IDLE_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_WAIT_TH_SHIFT (16U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_WAIT_TH_MASK (0xFFFFU << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON0_PCLK_AUDIO_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_AUDIO_ROOT_CON1 */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_OFFSET (0xF4CU) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_CTRL_MASK (0xFFFU << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_EN_SHIFT (12U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_EN_MASK (0x1U << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_SWITCH_EN_SHIFT (13U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_SWITCH_EN_MASK (0x1U << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_CLKSEL_CFG_SHIFT (14U) +#define CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_CLKSEL_CFG_MASK (0x3U << CRU_AUTOCS_PCLK_AUDIO_ROOT_CON1_PCLK_AUDIO_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/***************************************PHPTOPCRU****************************************/ +/* PPLL_CON0 */ +#define PHPTOPCRU_PPLL_CON0_OFFSET (0x200U) +#define PHPTOPCRU_PPLL_CON0_PPLL_M_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON0_PPLL_M_MASK (0x3FFU << PHPTOPCRU_PPLL_CON0_PPLL_M_SHIFT) /* 0x000003FF */ +#define PHPTOPCRU_PPLL_CON0_PPLL_BP_SHIFT (15U) +#define PHPTOPCRU_PPLL_CON0_PPLL_BP_MASK (0x1U << PHPTOPCRU_PPLL_CON0_PPLL_BP_SHIFT) /* 0x00008000 */ +/* PPLL_CON1 */ +#define PHPTOPCRU_PPLL_CON1_OFFSET (0x204U) +#define PHPTOPCRU_PPLL_CON1_PPLL_P_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON1_PPLL_P_MASK (0x3FU << PHPTOPCRU_PPLL_CON1_PPLL_P_SHIFT) /* 0x0000003F */ +#define PHPTOPCRU_PPLL_CON1_PPLL_S_SHIFT (6U) +#define PHPTOPCRU_PPLL_CON1_PPLL_S_MASK (0x7U << PHPTOPCRU_PPLL_CON1_PPLL_S_SHIFT) /* 0x000001C0 */ +#define PHPTOPCRU_PPLL_CON1_PPLL_RESETB_SHIFT (13U) +#define PHPTOPCRU_PPLL_CON1_PPLL_RESETB_MASK (0x1U << PHPTOPCRU_PPLL_CON1_PPLL_RESETB_SHIFT) /* 0x00002000 */ +/* PPLL_CON2 */ +#define PHPTOPCRU_PPLL_CON2_OFFSET (0x208U) +#define PHPTOPCRU_PPLL_CON2_PPLL_K_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON2_PPLL_K_MASK (0xFFFFU << PHPTOPCRU_PPLL_CON2_PPLL_K_SHIFT) /* 0x0000FFFF */ +/* PPLL_CON3 */ +#define PHPTOPCRU_PPLL_CON3_OFFSET (0x20CU) +#define PHPTOPCRU_PPLL_CON3_PPLL_MFR_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON3_PPLL_MFR_MASK (0xFFU << PHPTOPCRU_PPLL_CON3_PPLL_MFR_SHIFT) /* 0x000000FF */ +#define PHPTOPCRU_PPLL_CON3_PPLL_MRR_SHIFT (8U) +#define PHPTOPCRU_PPLL_CON3_PPLL_MRR_MASK (0x3FU << PHPTOPCRU_PPLL_CON3_PPLL_MRR_SHIFT) /* 0x00003F00 */ +#define PHPTOPCRU_PPLL_CON3_PPLL_SEL_PF_SHIFT (14U) +#define PHPTOPCRU_PPLL_CON3_PPLL_SEL_PF_MASK (0x3U << PHPTOPCRU_PPLL_CON3_PPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* PPLL_CON4 */ +#define PHPTOPCRU_PPLL_CON4_OFFSET (0x210U) +#define PHPTOPCRU_PPLL_CON4_PPLL_SSCG_EN_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON4_PPLL_SSCG_EN_MASK (0x1U << PHPTOPCRU_PPLL_CON4_PPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define PHPTOPCRU_PPLL_CON4_PPLL_AFC_ENB_SHIFT (3U) +#define PHPTOPCRU_PPLL_CON4_PPLL_AFC_ENB_MASK (0x1U << PHPTOPCRU_PPLL_CON4_PPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define PHPTOPCRU_PPLL_CON4_PPLL_EXTAFC_SHIFT (4U) +#define PHPTOPCRU_PPLL_CON4_PPLL_EXTAFC_MASK (0x1FU << PHPTOPCRU_PPLL_CON4_PPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define PHPTOPCRU_PPLL_CON4_PPLL_FEED_EN_SHIFT (14U) +#define PHPTOPCRU_PPLL_CON4_PPLL_FEED_EN_MASK (0x1U << PHPTOPCRU_PPLL_CON4_PPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define PHPTOPCRU_PPLL_CON4_PPLL_FSEL_SHIFT (15U) +#define PHPTOPCRU_PPLL_CON4_PPLL_FSEL_MASK (0x1U << PHPTOPCRU_PPLL_CON4_PPLL_FSEL_SHIFT) /* 0x00008000 */ +/* PPLL_CON5 */ +#define PHPTOPCRU_PPLL_CON5_OFFSET (0x214U) +#define PHPTOPCRU_PPLL_CON5_PPLL_FOUT_MASK_SHIFT (0U) +#define PHPTOPCRU_PPLL_CON5_PPLL_FOUT_MASK_MASK (0x1U << PHPTOPCRU_PPLL_CON5_PPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* PPLL_CON6 */ +#define PHPTOPCRU_PPLL_CON6_OFFSET (0x218U) +#define PHPTOPCRU_PPLL_CON6_PPLL_AFC_CODE_SHIFT (10U) +#define PHPTOPCRU_PPLL_CON6_PPLL_AFC_CODE_MASK (0x1FU << PHPTOPCRU_PPLL_CON6_PPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define PHPTOPCRU_PPLL_CON6_PPLL_LOCK_SHIFT (15U) +#define PHPTOPCRU_PPLL_CON6_PPLL_LOCK_MASK (0x1U << PHPTOPCRU_PPLL_CON6_PPLL_LOCK_SHIFT) /* 0x00008000 */ +/* GATE_CON00 */ +#define PHPTOPCRU_GATE_CON00_OFFSET (0x800U) +#define PHPTOPCRU_GATE_CON00_PCLK_PHPTOP_CRU_EN_SHIFT (1U) +#define PHPTOPCRU_GATE_CON00_PCLK_PHPTOP_CRU_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PHPTOP_CRU_EN_SHIFT) /* 0x00000002 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF0_EN_SHIFT (2U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF0_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF0_EN_SHIFT) /* 0x00000004 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF1_EN_SHIFT (3U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF1_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF1_EN_SHIFT) /* 0x00000008 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF2_EN_SHIFT (4U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF2_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_GRF2_EN_SHIFT) /* 0x00000010 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY0_EN_SHIFT (5U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY0_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY0_EN_SHIFT) /* 0x00000020 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY1_EN_SHIFT (6U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY1_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY1_EN_SHIFT) /* 0x00000040 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY2_EN_SHIFT (7U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY2_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE_COMBO_PIPE_PHY2_EN_SHIFT) /* 0x00000080 */ +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE3_PHY_EN_SHIFT (8U) +#define PHPTOPCRU_GATE_CON00_PCLK_PCIE3_PHY_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_PCIE3_PHY_EN_SHIFT) /* 0x00000100 */ +#define PHPTOPCRU_GATE_CON00_PCLK_APB2ASB_SLV_CHIP_TOP_EN_SHIFT (9U) +#define PHPTOPCRU_GATE_CON00_PCLK_APB2ASB_SLV_CHIP_TOP_EN_MASK (0x1U << PHPTOPCRU_GATE_CON00_PCLK_APB2ASB_SLV_CHIP_TOP_EN_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON00 */ +#define PHPTOPCRU_SOFTRST_CON00_OFFSET (0xA00U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PHPTOP_CRU_SHIFT (1U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PHPTOP_CRU_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PHPTOP_CRU_SHIFT) /* 0x00000002 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF0_SHIFT (2U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF0_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF0_SHIFT) /* 0x00000004 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF1_SHIFT (3U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF1_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF1_SHIFT) /* 0x00000008 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF2_SHIFT (4U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF2_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_GRF2_SHIFT) /* 0x00000010 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY0_SHIFT (5U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY0_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY0_SHIFT) /* 0x00000020 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY1_SHIFT (6U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY1_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY1_SHIFT) /* 0x00000040 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY2_SHIFT (7U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY2_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE_COMBO_PIPE_PHY2_SHIFT) /* 0x00000080 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE3_PHY_SHIFT (8U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE3_PHY_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_PCIE3_PHY_SHIFT) /* 0x00000100 */ +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_APB2ASB_SLV_CHIP_TOP_SHIFT (9U) +#define PHPTOPCRU_SOFTRST_CON00_PRESETN_APB2ASB_SLV_CHIP_TOP_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_PRESETN_APB2ASB_SLV_CHIP_TOP_SHIFT) /* 0x00000200 */ +#define PHPTOPCRU_SOFTRST_CON00_RESETN_PCIE3_PHY_SHIFT (10U) +#define PHPTOPCRU_SOFTRST_CON00_RESETN_PCIE3_PHY_MASK (0x1U << PHPTOPCRU_SOFTRST_CON00_RESETN_PCIE3_PHY_SHIFT) /* 0x00000400 */ +/***************************************SECURECRU****************************************/ +/* CLKSEL_CON00 */ +#define SECURECRU_CLKSEL_CON00_OFFSET (0x300U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_58M_SRC_DIV_SHIFT (0U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_58M_SRC_DIV_MASK (0x7U << SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_58M_SRC_DIV_SHIFT) /* 0x00000007 */ +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_116M_SRC_DIV_SHIFT (3U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_116M_SRC_DIV_MASK (0x7U << SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_116M_SRC_DIV_SHIFT) /* 0x00000038 */ +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_175M_SRC_DIV_SHIFT (6U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_175M_SRC_DIV_MASK (0x7U << SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_175M_SRC_DIV_SHIFT) /* 0x000001C0 */ +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_233M_SRC_DIV_SHIFT (9U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_233M_SRC_DIV_MASK (0x7U << SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_233M_SRC_DIV_SHIFT) /* 0x00000E00 */ +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_350M_SRC_DIV_SHIFT (12U) +#define SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_350M_SRC_DIV_MASK (0x7U << SECURECRU_CLKSEL_CON00_CLK_MATRIX_SEC_350M_SRC_DIV_SHIFT) /* 0x00007000 */ +/* CLKSEL_CON01 */ +#define SECURECRU_CLKSEL_CON01_OFFSET (0x304U) +#define SECURECRU_CLKSEL_CON01_ACLK_SECURE_NS_ROOT_SEL_SHIFT (0U) +#define SECURECRU_CLKSEL_CON01_ACLK_SECURE_NS_ROOT_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_ACLK_SECURE_NS_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define SECURECRU_CLKSEL_CON01_HCLK_SECURE_NS_ROOT_SEL_SHIFT (2U) +#define SECURECRU_CLKSEL_CON01_HCLK_SECURE_NS_ROOT_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_HCLK_SECURE_NS_ROOT_SEL_SHIFT) /* 0x0000000C */ +#define SECURECRU_CLKSEL_CON01_ACLK_SECURE_S_ROOT_SEL_SHIFT (4U) +#define SECURECRU_CLKSEL_CON01_ACLK_SECURE_S_ROOT_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_ACLK_SECURE_S_ROOT_SEL_SHIFT) /* 0x00000030 */ +#define SECURECRU_CLKSEL_CON01_HCLK_SECURE_S_ROOT_SEL_SHIFT (6U) +#define SECURECRU_CLKSEL_CON01_HCLK_SECURE_S_ROOT_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_HCLK_SECURE_S_ROOT_SEL_SHIFT) /* 0x000000C0 */ +#define SECURECRU_CLKSEL_CON01_PCLK_SECURE_S_ROOT_SEL_SHIFT (8U) +#define SECURECRU_CLKSEL_CON01_PCLK_SECURE_S_ROOT_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_PCLK_SECURE_S_ROOT_SEL_SHIFT) /* 0x00000300 */ +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_CORE_SEL_SHIFT (10U) +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_CORE_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_CLK_CRYPTO_CORE_SEL_SHIFT) /* 0x00000C00 */ +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_PKA_SEL_SHIFT (12U) +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_PKA_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_CLK_CRYPTO_PKA_SEL_SHIFT) /* 0x00003000 */ +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_RNG_SEL_SHIFT (14U) +#define SECURECRU_CLKSEL_CON01_CLK_CRYPTO_RNG_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON01_CLK_CRYPTO_RNG_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON02 */ +#define SECURECRU_CLKSEL_CON02_OFFSET (0x308U) +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_CORE_SEL_SHIFT (0U) +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_CORE_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_CORE_SEL_SHIFT) /* 0x00000003 */ +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_PKA_SEL_SHIFT (2U) +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_PKA_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_PKA_SEL_SHIFT) /* 0x0000000C */ +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_RNG_SEL_SHIFT (4U) +#define SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_RNG_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON02_CLK_SCRYPTO_RNG_SEL_SHIFT) /* 0x00000030 */ +#define SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_CORE_SEL_SHIFT (6U) +#define SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_CORE_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_CORE_SEL_SHIFT) /* 0x000000C0 */ +#define SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_RNG_SEL_SHIFT (8U) +#define SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_RNG_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON02_CLK_KEYLADDER_RNG_SEL_SHIFT) /* 0x00000300 */ +#define SECURECRU_CLKSEL_CON02_CLK_STIMER_ROOT_SEL_SHIFT (10U) +#define SECURECRU_CLKSEL_CON02_CLK_STIMER_ROOT_SEL_MASK (0x1U << SECURECRU_CLKSEL_CON02_CLK_STIMER_ROOT_SEL_SHIFT) /* 0x00000400 */ +/* CLKSEL_CON03 */ +#define SECURECRU_CLKSEL_CON03_OFFSET (0x30CU) +#define SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_DIV_SHIFT (0U) +#define SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_DIV_MASK (0x1FU << SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_DIV_SHIFT) /* 0x0000001F */ +#define SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_SEL_SHIFT (5U) +#define SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_SEL_MASK (0x1U << SECURECRU_CLKSEL_CON03_DCLK_SDMMC_BUFFER_SEL_SHIFT) /* 0x00000020 */ +#define SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_DIV_SHIFT (6U) +#define SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_DIV_MASK (0x3FU << SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_DIV_SHIFT) /* 0x00000FC0 */ +#define SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_SEL_SHIFT (12U) +#define SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_SEL_MASK (0x3U << SECURECRU_CLKSEL_CON03_CCLK_SRC_SDMMC_SEL_SHIFT) /* 0x00003000 */ +/* GATE_CON00 */ +#define SECURECRU_GATE_CON00_OFFSET (0x800U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_50M_SRC_EN_SHIFT (0U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_50M_SRC_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_MATRIX_SEC_50M_SRC_EN_SHIFT) /* 0x00000001 */ +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_100M_SRC_EN_SHIFT (1U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_100M_SRC_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_MATRIX_SEC_100M_SRC_EN_SHIFT) /* 0x00000002 */ +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_175M_SRC_EN_SHIFT (2U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_175M_SRC_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_MATRIX_SEC_175M_SRC_EN_SHIFT) /* 0x00000004 */ +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_200M_SRC_EN_SHIFT (3U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_200M_SRC_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_MATRIX_SEC_200M_SRC_EN_SHIFT) /* 0x00000008 */ +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_333M_SRC_EN_SHIFT (4U) +#define SECURECRU_GATE_CON00_CLK_MATRIX_SEC_333M_SRC_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_MATRIX_SEC_333M_SRC_EN_SHIFT) /* 0x00000010 */ +#define SECURECRU_GATE_CON00_ACLK_SECURE_NS_ROOT_EN_SHIFT (5U) +#define SECURECRU_GATE_CON00_ACLK_SECURE_NS_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON00_ACLK_SECURE_NS_ROOT_EN_SHIFT) /* 0x00000020 */ +#define SECURECRU_GATE_CON00_HCLK_SECURE_NS_ROOT_EN_SHIFT (6U) +#define SECURECRU_GATE_CON00_HCLK_SECURE_NS_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON00_HCLK_SECURE_NS_ROOT_EN_SHIFT) /* 0x00000040 */ +#define SECURECRU_GATE_CON00_ACLK_SECURE_S_ROOT_EN_SHIFT (7U) +#define SECURECRU_GATE_CON00_ACLK_SECURE_S_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON00_ACLK_SECURE_S_ROOT_EN_SHIFT) /* 0x00000080 */ +#define SECURECRU_GATE_CON00_HCLK_SECURE_S_ROOT_EN_SHIFT (8U) +#define SECURECRU_GATE_CON00_HCLK_SECURE_S_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON00_HCLK_SECURE_S_ROOT_EN_SHIFT) /* 0x00000100 */ +#define SECURECRU_GATE_CON00_PCLK_SECURE_S_ROOT_EN_SHIFT (9U) +#define SECURECRU_GATE_CON00_PCLK_SECURE_S_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON00_PCLK_SECURE_S_ROOT_EN_SHIFT) /* 0x00000200 */ +#define SECURECRU_GATE_CON00_ACLK_SECURE_NS_BIU_EN_SHIFT (10U) +#define SECURECRU_GATE_CON00_ACLK_SECURE_NS_BIU_EN_MASK (0x1U << SECURECRU_GATE_CON00_ACLK_SECURE_NS_BIU_EN_SHIFT) /* 0x00000400 */ +#define SECURECRU_GATE_CON00_HCLK_SECURE_NS_BIU_EN_SHIFT (11U) +#define SECURECRU_GATE_CON00_HCLK_SECURE_NS_BIU_EN_MASK (0x1U << SECURECRU_GATE_CON00_HCLK_SECURE_NS_BIU_EN_SHIFT) /* 0x00000800 */ +#define SECURECRU_GATE_CON00_ACLK_SECURE_S_BIU_EN_SHIFT (12U) +#define SECURECRU_GATE_CON00_ACLK_SECURE_S_BIU_EN_MASK (0x1U << SECURECRU_GATE_CON00_ACLK_SECURE_S_BIU_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_GATE_CON00_HCLK_SECURE_S_BIU_EN_SHIFT (13U) +#define SECURECRU_GATE_CON00_HCLK_SECURE_S_BIU_EN_MASK (0x1U << SECURECRU_GATE_CON00_HCLK_SECURE_S_BIU_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_GATE_CON00_PCLK_SECURE_S_BIU_EN_SHIFT (14U) +#define SECURECRU_GATE_CON00_PCLK_SECURE_S_BIU_EN_MASK (0x1U << SECURECRU_GATE_CON00_PCLK_SECURE_S_BIU_EN_SHIFT) /* 0x00004000 */ +#define SECURECRU_GATE_CON00_CLK_CRYPTO_CORE_EN_SHIFT (15U) +#define SECURECRU_GATE_CON00_CLK_CRYPTO_CORE_EN_MASK (0x1U << SECURECRU_GATE_CON00_CLK_CRYPTO_CORE_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define SECURECRU_GATE_CON01_OFFSET (0x804U) +#define SECURECRU_GATE_CON01_CLK_CRYPTO_PKA_EN_SHIFT (0U) +#define SECURECRU_GATE_CON01_CLK_CRYPTO_PKA_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_CRYPTO_PKA_EN_SHIFT) /* 0x00000001 */ +#define SECURECRU_GATE_CON01_CLK_CRYPTO_RNG_EN_SHIFT (1U) +#define SECURECRU_GATE_CON01_CLK_CRYPTO_RNG_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_CRYPTO_RNG_EN_SHIFT) /* 0x00000002 */ +#define SECURECRU_GATE_CON01_ACLK_CRYPTO_EN_SHIFT (2U) +#define SECURECRU_GATE_CON01_ACLK_CRYPTO_EN_MASK (0x1U << SECURECRU_GATE_CON01_ACLK_CRYPTO_EN_SHIFT) /* 0x00000004 */ +#define SECURECRU_GATE_CON01_HCLK_CRYPTO_EN_SHIFT (3U) +#define SECURECRU_GATE_CON01_HCLK_CRYPTO_EN_MASK (0x1U << SECURECRU_GATE_CON01_HCLK_CRYPTO_EN_SHIFT) /* 0x00000008 */ +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_CORE_EN_SHIFT (4U) +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_CORE_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_SCRYPTO_CORE_EN_SHIFT) /* 0x00000010 */ +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_PKA_EN_SHIFT (5U) +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_PKA_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_SCRYPTO_PKA_EN_SHIFT) /* 0x00000020 */ +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_RNG_EN_SHIFT (6U) +#define SECURECRU_GATE_CON01_CLK_SCRYPTO_RNG_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_SCRYPTO_RNG_EN_SHIFT) /* 0x00000040 */ +#define SECURECRU_GATE_CON01_ACLK_SCRYPTO_EN_SHIFT (7U) +#define SECURECRU_GATE_CON01_ACLK_SCRYPTO_EN_MASK (0x1U << SECURECRU_GATE_CON01_ACLK_SCRYPTO_EN_SHIFT) /* 0x00000080 */ +#define SECURECRU_GATE_CON01_HCLK_SCRYPTO_EN_SHIFT (8U) +#define SECURECRU_GATE_CON01_HCLK_SCRYPTO_EN_MASK (0x1U << SECURECRU_GATE_CON01_HCLK_SCRYPTO_EN_SHIFT) /* 0x00000100 */ +#define SECURECRU_GATE_CON01_CLK_KEYLADDER_CORE_EN_SHIFT (9U) +#define SECURECRU_GATE_CON01_CLK_KEYLADDER_CORE_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_KEYLADDER_CORE_EN_SHIFT) /* 0x00000200 */ +#define SECURECRU_GATE_CON01_CLK_KEYLADDER_RNG_EN_SHIFT (10U) +#define SECURECRU_GATE_CON01_CLK_KEYLADDER_RNG_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_KEYLADDER_RNG_EN_SHIFT) /* 0x00000400 */ +#define SECURECRU_GATE_CON01_ACLK_KEYLADDER_EN_SHIFT (11U) +#define SECURECRU_GATE_CON01_ACLK_KEYLADDER_EN_MASK (0x1U << SECURECRU_GATE_CON01_ACLK_KEYLADDER_EN_SHIFT) /* 0x00000800 */ +#define SECURECRU_GATE_CON01_HCLK_KEYLADDER_EN_SHIFT (12U) +#define SECURECRU_GATE_CON01_HCLK_KEYLADDER_EN_MASK (0x1U << SECURECRU_GATE_CON01_HCLK_KEYLADDER_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_GATE_CON01_PCLK_OTPC_S_EN_SHIFT (13U) +#define SECURECRU_GATE_CON01_PCLK_OTPC_S_EN_MASK (0x1U << SECURECRU_GATE_CON01_PCLK_OTPC_S_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_GATE_CON01_CLK_OTPC_S_EN_SHIFT (14U) +#define SECURECRU_GATE_CON01_CLK_OTPC_S_EN_MASK (0x1U << SECURECRU_GATE_CON01_CLK_OTPC_S_EN_SHIFT) /* 0x00004000 */ +#define SECURECRU_GATE_CON01_PCLK_WDT_S_EN_SHIFT (15U) +#define SECURECRU_GATE_CON01_PCLK_WDT_S_EN_MASK (0x1U << SECURECRU_GATE_CON01_PCLK_WDT_S_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON02 */ +#define SECURECRU_GATE_CON02_OFFSET (0x808U) +#define SECURECRU_GATE_CON02_TCLK_WDT_S_EN_SHIFT (0U) +#define SECURECRU_GATE_CON02_TCLK_WDT_S_EN_MASK (0x1U << SECURECRU_GATE_CON02_TCLK_WDT_S_EN_SHIFT) /* 0x00000001 */ +#define SECURECRU_GATE_CON02_HCLK_BOOTROM_EN_SHIFT (1U) +#define SECURECRU_GATE_CON02_HCLK_BOOTROM_EN_MASK (0x1U << SECURECRU_GATE_CON02_HCLK_BOOTROM_EN_SHIFT) /* 0x00000002 */ +#define SECURECRU_GATE_CON02_ACLK_DCF_EN_SHIFT (2U) +#define SECURECRU_GATE_CON02_ACLK_DCF_EN_MASK (0x1U << SECURECRU_GATE_CON02_ACLK_DCF_EN_SHIFT) /* 0x00000004 */ +#define SECURECRU_GATE_CON02_PCLK_DCF_EN_SHIFT (3U) +#define SECURECRU_GATE_CON02_PCLK_DCF_EN_MASK (0x1U << SECURECRU_GATE_CON02_PCLK_DCF_EN_SHIFT) /* 0x00000008 */ +#define SECURECRU_GATE_CON02_PCLK_STIMER0_EN_SHIFT (4U) +#define SECURECRU_GATE_CON02_PCLK_STIMER0_EN_MASK (0x1U << SECURECRU_GATE_CON02_PCLK_STIMER0_EN_SHIFT) /* 0x00000010 */ +#define SECURECRU_GATE_CON02_HCLK_BOOTROM_NS_EN_SHIFT (5U) +#define SECURECRU_GATE_CON02_HCLK_BOOTROM_NS_EN_MASK (0x1U << SECURECRU_GATE_CON02_HCLK_BOOTROM_NS_EN_SHIFT) /* 0x00000020 */ +#define SECURECRU_GATE_CON02_CLK_STIMER_ROOT_EN_SHIFT (6U) +#define SECURECRU_GATE_CON02_CLK_STIMER_ROOT_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER_ROOT_EN_SHIFT) /* 0x00000040 */ +#define SECURECRU_GATE_CON02_CLK_STIMER0_EN_SHIFT (7U) +#define SECURECRU_GATE_CON02_CLK_STIMER0_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER0_EN_SHIFT) /* 0x00000080 */ +#define SECURECRU_GATE_CON02_CLK_STIMER1_EN_SHIFT (8U) +#define SECURECRU_GATE_CON02_CLK_STIMER1_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER1_EN_SHIFT) /* 0x00000100 */ +#define SECURECRU_GATE_CON02_CLK_STIMER2_EN_SHIFT (9U) +#define SECURECRU_GATE_CON02_CLK_STIMER2_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER2_EN_SHIFT) /* 0x00000200 */ +#define SECURECRU_GATE_CON02_CLK_STIMER3_EN_SHIFT (10U) +#define SECURECRU_GATE_CON02_CLK_STIMER3_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER3_EN_SHIFT) /* 0x00000400 */ +#define SECURECRU_GATE_CON02_CLK_STIMER4_EN_SHIFT (11U) +#define SECURECRU_GATE_CON02_CLK_STIMER4_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER4_EN_SHIFT) /* 0x00000800 */ +#define SECURECRU_GATE_CON02_CLK_STIMER5_EN_SHIFT (12U) +#define SECURECRU_GATE_CON02_CLK_STIMER5_EN_MASK (0x1U << SECURECRU_GATE_CON02_CLK_STIMER5_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_GATE_CON02_PCLK_SCRYPTO_EN_SHIFT (13U) +#define SECURECRU_GATE_CON02_PCLK_SCRYPTO_EN_MASK (0x1U << SECURECRU_GATE_CON02_PCLK_SCRYPTO_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_GATE_CON02_PCLK_KEYLAD_EN_SHIFT (14U) +#define SECURECRU_GATE_CON02_PCLK_KEYLAD_EN_MASK (0x1U << SECURECRU_GATE_CON02_PCLK_KEYLAD_EN_SHIFT) /* 0x00004000 */ +#define SECURECRU_GATE_CON02_HCLK_TRNG_S_EN_SHIFT (15U) +#define SECURECRU_GATE_CON02_HCLK_TRNG_S_EN_MASK (0x1U << SECURECRU_GATE_CON02_HCLK_TRNG_S_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON03 */ +#define SECURECRU_GATE_CON03_OFFSET (0x80CU) +#define SECURECRU_GATE_CON03_HCLK_TRNG_NS_EN_SHIFT (0U) +#define SECURECRU_GATE_CON03_HCLK_TRNG_NS_EN_MASK (0x1U << SECURECRU_GATE_CON03_HCLK_TRNG_NS_EN_SHIFT) /* 0x00000001 */ +#define SECURECRU_GATE_CON03_DCLK_SDMMC_BUFFER_EN_SHIFT (1U) +#define SECURECRU_GATE_CON03_DCLK_SDMMC_BUFFER_EN_MASK (0x1U << SECURECRU_GATE_CON03_DCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000002 */ +#define SECURECRU_GATE_CON03_HCLK_SDMMC_EN_SHIFT (2U) +#define SECURECRU_GATE_CON03_HCLK_SDMMC_EN_MASK (0x1U << SECURECRU_GATE_CON03_HCLK_SDMMC_EN_SHIFT) /* 0x00000004 */ +#define SECURECRU_GATE_CON03_HCLK_SDMMC_BUFFER_EN_SHIFT (3U) +#define SECURECRU_GATE_CON03_HCLK_SDMMC_BUFFER_EN_MASK (0x1U << SECURECRU_GATE_CON03_HCLK_SDMMC_BUFFER_EN_SHIFT) /* 0x00000008 */ +#define SECURECRU_GATE_CON03_CCLK_SRC_SDMMC_EN_SHIFT (4U) +#define SECURECRU_GATE_CON03_CCLK_SRC_SDMMC_EN_MASK (0x1U << SECURECRU_GATE_CON03_CCLK_SRC_SDMMC_EN_SHIFT) /* 0x00000010 */ +#define SECURECRU_GATE_CON03_PCLK_TRNG_CHK_EN_SHIFT (5U) +#define SECURECRU_GATE_CON03_PCLK_TRNG_CHK_EN_MASK (0x1U << SECURECRU_GATE_CON03_PCLK_TRNG_CHK_EN_SHIFT) /* 0x00000020 */ +#define SECURECRU_GATE_CON03_CLK_TRNG_S_EN_SHIFT (6U) +#define SECURECRU_GATE_CON03_CLK_TRNG_S_EN_MASK (0x1U << SECURECRU_GATE_CON03_CLK_TRNG_S_EN_SHIFT) /* 0x00000040 */ +#define SECURECRU_GATE_CON03_PCLK_SECURE_CRU_EN_SHIFT (7U) +#define SECURECRU_GATE_CON03_PCLK_SECURE_CRU_EN_MASK (0x1U << SECURECRU_GATE_CON03_PCLK_SECURE_CRU_EN_SHIFT) /* 0x00000080 */ +/* SOFTRST_CON00 */ +#define SECURECRU_SOFTRST_CON00_OFFSET (0xA00U) +#define SECURECRU_SOFTRST_CON00_ARESETN_SECURE_NS_BIU_SHIFT (10U) +#define SECURECRU_SOFTRST_CON00_ARESETN_SECURE_NS_BIU_MASK (0x1U << SECURECRU_SOFTRST_CON00_ARESETN_SECURE_NS_BIU_SHIFT) /* 0x00000400 */ +#define SECURECRU_SOFTRST_CON00_HRESETN_SECURE_NS_BIU_SHIFT (11U) +#define SECURECRU_SOFTRST_CON00_HRESETN_SECURE_NS_BIU_MASK (0x1U << SECURECRU_SOFTRST_CON00_HRESETN_SECURE_NS_BIU_SHIFT) /* 0x00000800 */ +#define SECURECRU_SOFTRST_CON00_ARESETN_SECURE_S_BIU_SHIFT (12U) +#define SECURECRU_SOFTRST_CON00_ARESETN_SECURE_S_BIU_MASK (0x1U << SECURECRU_SOFTRST_CON00_ARESETN_SECURE_S_BIU_SHIFT) /* 0x00001000 */ +#define SECURECRU_SOFTRST_CON00_HRESETN_SECURE_S_BIU_SHIFT (13U) +#define SECURECRU_SOFTRST_CON00_HRESETN_SECURE_S_BIU_MASK (0x1U << SECURECRU_SOFTRST_CON00_HRESETN_SECURE_S_BIU_SHIFT) /* 0x00002000 */ +#define SECURECRU_SOFTRST_CON00_PRESETN_SECURE_S_BIU_SHIFT (14U) +#define SECURECRU_SOFTRST_CON00_PRESETN_SECURE_S_BIU_MASK (0x1U << SECURECRU_SOFTRST_CON00_PRESETN_SECURE_S_BIU_SHIFT) /* 0x00004000 */ +#define SECURECRU_SOFTRST_CON00_RESETN_CRYPTO_CORE_SHIFT (15U) +#define SECURECRU_SOFTRST_CON00_RESETN_CRYPTO_CORE_MASK (0x1U << SECURECRU_SOFTRST_CON00_RESETN_CRYPTO_CORE_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON01 */ +#define SECURECRU_SOFTRST_CON01_OFFSET (0xA04U) +#define SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_PKA_SHIFT (0U) +#define SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_PKA_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_PKA_SHIFT) /* 0x00000001 */ +#define SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_RNG_SHIFT (1U) +#define SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_RNG_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_CRYPTO_RNG_SHIFT) /* 0x00000002 */ +#define SECURECRU_SOFTRST_CON01_ARESETN_CRYPTO_SHIFT (2U) +#define SECURECRU_SOFTRST_CON01_ARESETN_CRYPTO_MASK (0x1U << SECURECRU_SOFTRST_CON01_ARESETN_CRYPTO_SHIFT) /* 0x00000004 */ +#define SECURECRU_SOFTRST_CON01_HRESETN_CRYPTO_SHIFT (3U) +#define SECURECRU_SOFTRST_CON01_HRESETN_CRYPTO_MASK (0x1U << SECURECRU_SOFTRST_CON01_HRESETN_CRYPTO_SHIFT) /* 0x00000008 */ +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_CORE_SHIFT (4U) +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_CORE_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_CORE_SHIFT) /* 0x00000010 */ +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_PKA_SHIFT (5U) +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_PKA_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_PKA_SHIFT) /* 0x00000020 */ +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_RNG_SHIFT (6U) +#define SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_RNG_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_SCRYPTO_RNG_SHIFT) /* 0x00000040 */ +#define SECURECRU_SOFTRST_CON01_ARESETN_SCRYPTO_SHIFT (7U) +#define SECURECRU_SOFTRST_CON01_ARESETN_SCRYPTO_MASK (0x1U << SECURECRU_SOFTRST_CON01_ARESETN_SCRYPTO_SHIFT) /* 0x00000080 */ +#define SECURECRU_SOFTRST_CON01_HRESETN_SCRYPTO_SHIFT (8U) +#define SECURECRU_SOFTRST_CON01_HRESETN_SCRYPTO_MASK (0x1U << SECURECRU_SOFTRST_CON01_HRESETN_SCRYPTO_SHIFT) /* 0x00000100 */ +#define SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_CORE_SHIFT (9U) +#define SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_CORE_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_CORE_SHIFT) /* 0x00000200 */ +#define SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_RNG_SHIFT (10U) +#define SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_RNG_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_KEYLADDER_RNG_SHIFT) /* 0x00000400 */ +#define SECURECRU_SOFTRST_CON01_ARESETN_KEYLADDER_SHIFT (11U) +#define SECURECRU_SOFTRST_CON01_ARESETN_KEYLADDER_MASK (0x1U << SECURECRU_SOFTRST_CON01_ARESETN_KEYLADDER_SHIFT) /* 0x00000800 */ +#define SECURECRU_SOFTRST_CON01_HRESETN_KEYLADDER_SHIFT (12U) +#define SECURECRU_SOFTRST_CON01_HRESETN_KEYLADDER_MASK (0x1U << SECURECRU_SOFTRST_CON01_HRESETN_KEYLADDER_SHIFT) /* 0x00001000 */ +#define SECURECRU_SOFTRST_CON01_PRESETN_OTPC_S_SHIFT (13U) +#define SECURECRU_SOFTRST_CON01_PRESETN_OTPC_S_MASK (0x1U << SECURECRU_SOFTRST_CON01_PRESETN_OTPC_S_SHIFT) /* 0x00002000 */ +#define SECURECRU_SOFTRST_CON01_RESETN_OTPC_S_SHIFT (14U) +#define SECURECRU_SOFTRST_CON01_RESETN_OTPC_S_MASK (0x1U << SECURECRU_SOFTRST_CON01_RESETN_OTPC_S_SHIFT) /* 0x00004000 */ +#define SECURECRU_SOFTRST_CON01_PRESETN_WDT_S_SHIFT (15U) +#define SECURECRU_SOFTRST_CON01_PRESETN_WDT_S_MASK (0x1U << SECURECRU_SOFTRST_CON01_PRESETN_WDT_S_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON02 */ +#define SECURECRU_SOFTRST_CON02_OFFSET (0xA08U) +#define SECURECRU_SOFTRST_CON02_TRESETN_WDT_S_SHIFT (0U) +#define SECURECRU_SOFTRST_CON02_TRESETN_WDT_S_MASK (0x1U << SECURECRU_SOFTRST_CON02_TRESETN_WDT_S_SHIFT) /* 0x00000001 */ +#define SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_SHIFT (1U) +#define SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_MASK (0x1U << SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_SHIFT) /* 0x00000002 */ +#define SECURECRU_SOFTRST_CON02_ARESETN_DCF_SHIFT (2U) +#define SECURECRU_SOFTRST_CON02_ARESETN_DCF_MASK (0x1U << SECURECRU_SOFTRST_CON02_ARESETN_DCF_SHIFT) /* 0x00000004 */ +#define SECURECRU_SOFTRST_CON02_PRESETN_DCF_SHIFT (3U) +#define SECURECRU_SOFTRST_CON02_PRESETN_DCF_MASK (0x1U << SECURECRU_SOFTRST_CON02_PRESETN_DCF_SHIFT) /* 0x00000008 */ +#define SECURECRU_SOFTRST_CON02_PRESETN_STIMER0_SHIFT (4U) +#define SECURECRU_SOFTRST_CON02_PRESETN_STIMER0_MASK (0x1U << SECURECRU_SOFTRST_CON02_PRESETN_STIMER0_SHIFT) /* 0x00000010 */ +#define SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_NS_SHIFT (5U) +#define SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_NS_MASK (0x1U << SECURECRU_SOFTRST_CON02_HRESETN_BOOTROM_NS_SHIFT) /* 0x00000020 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER0_SHIFT (7U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER0_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER0_SHIFT) /* 0x00000080 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER1_SHIFT (8U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER1_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER1_SHIFT) /* 0x00000100 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER2_SHIFT (9U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER2_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER2_SHIFT) /* 0x00000200 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER3_SHIFT (10U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER3_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER3_SHIFT) /* 0x00000400 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER4_SHIFT (11U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER4_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER4_SHIFT) /* 0x00000800 */ +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER5_SHIFT (12U) +#define SECURECRU_SOFTRST_CON02_RESETN_STIMER5_MASK (0x1U << SECURECRU_SOFTRST_CON02_RESETN_STIMER5_SHIFT) /* 0x00001000 */ +#define SECURECRU_SOFTRST_CON02_PRESETN_SCRYPTO_SHIFT (13U) +#define SECURECRU_SOFTRST_CON02_PRESETN_SCRYPTO_MASK (0x1U << SECURECRU_SOFTRST_CON02_PRESETN_SCRYPTO_SHIFT) /* 0x00002000 */ +#define SECURECRU_SOFTRST_CON02_PRESETN_KEYLAD_SHIFT (14U) +#define SECURECRU_SOFTRST_CON02_PRESETN_KEYLAD_MASK (0x1U << SECURECRU_SOFTRST_CON02_PRESETN_KEYLAD_SHIFT) /* 0x00004000 */ +#define SECURECRU_SOFTRST_CON02_HRESETN_TRNG_S_SHIFT (15U) +#define SECURECRU_SOFTRST_CON02_HRESETN_TRNG_S_MASK (0x1U << SECURECRU_SOFTRST_CON02_HRESETN_TRNG_S_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON03 */ +#define SECURECRU_SOFTRST_CON03_OFFSET (0xA0CU) +#define SECURECRU_SOFTRST_CON03_HRESETN_TRNG_NS_SHIFT (0U) +#define SECURECRU_SOFTRST_CON03_HRESETN_TRNG_NS_MASK (0x1U << SECURECRU_SOFTRST_CON03_HRESETN_TRNG_NS_SHIFT) /* 0x00000001 */ +#define SECURECRU_SOFTRST_CON03_DRESETN_SDMMC_BUFFER_SHIFT (1U) +#define SECURECRU_SOFTRST_CON03_DRESETN_SDMMC_BUFFER_MASK (0x1U << SECURECRU_SOFTRST_CON03_DRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000002 */ +#define SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_SHIFT (2U) +#define SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_MASK (0x1U << SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_SHIFT) /* 0x00000004 */ +#define SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_BUFFER_SHIFT (3U) +#define SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_BUFFER_MASK (0x1U << SECURECRU_SOFTRST_CON03_HRESETN_SDMMC_BUFFER_SHIFT) /* 0x00000008 */ +#define SECURECRU_SOFTRST_CON03_RESETN_SDMMC_SHIFT (4U) +#define SECURECRU_SOFTRST_CON03_RESETN_SDMMC_MASK (0x1U << SECURECRU_SOFTRST_CON03_RESETN_SDMMC_SHIFT) /* 0x00000010 */ +#define SECURECRU_SOFTRST_CON03_PRESETN_TRNG_CHK_SHIFT (5U) +#define SECURECRU_SOFTRST_CON03_PRESETN_TRNG_CHK_MASK (0x1U << SECURECRU_SOFTRST_CON03_PRESETN_TRNG_CHK_SHIFT) /* 0x00000020 */ +#define SECURECRU_SOFTRST_CON03_RESETN_TRNG_S_SHIFT (6U) +#define SECURECRU_SOFTRST_CON03_RESETN_TRNG_S_MASK (0x1U << SECURECRU_SOFTRST_CON03_RESETN_TRNG_S_SHIFT) /* 0x00000040 */ +#define SECURECRU_SOFTRST_CON03_PRESETN_SECURE_CRU_SHIFT (7U) +#define SECURECRU_SOFTRST_CON03_PRESETN_SECURE_CRU_MASK (0x1U << SECURECRU_SOFTRST_CON03_PRESETN_SECURE_CRU_SHIFT) /* 0x00000080 */ +/* AUTOCS_ACLK_SECURE_NS_ROOT_CON0 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_OFFSET (0xD00U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_IDLE_TH_SHIFT (0U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_IDLE_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_WAIT_TH_SHIFT (16U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_WAIT_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON0_ACLK_SECURE_NS_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_SECURE_NS_ROOT_CON1 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_OFFSET (0xD04U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_CTRL_MASK (0xFFFU << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_EN_SHIFT (12U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_EN_MASK (0x1U << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_SWITCH_EN_SHIFT (13U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_SWITCH_EN_MASK (0x1U << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_CLKSEL_CFG_SHIFT (14U) +#define SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_CLKSEL_CFG_MASK (0x3U << SECURECRU_AUTOCS_ACLK_SECURE_NS_ROOT_CON1_ACLK_SECURE_NS_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_SECURE_NS_ROOT_CON0 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_OFFSET (0xD08U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_IDLE_TH_SHIFT (0U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_IDLE_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_WAIT_TH_SHIFT (16U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_WAIT_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON0_HCLK_SECURE_NS_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_SECURE_NS_ROOT_CON1 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_OFFSET (0xD0CU) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_CTRL_MASK (0xFFFU << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_EN_SHIFT (12U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_EN_MASK (0x1U << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_SWITCH_EN_SHIFT (13U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_SWITCH_EN_MASK (0x1U << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_CLKSEL_CFG_SHIFT (14U) +#define SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_CLKSEL_CFG_MASK (0x3U << SECURECRU_AUTOCS_HCLK_SECURE_NS_ROOT_CON1_HCLK_SECURE_NS_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_SECURE_S_ROOT_CON0 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_OFFSET (0xD10U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_IDLE_TH_SHIFT (0U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_IDLE_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_WAIT_TH_SHIFT (16U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_WAIT_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON0_ACLK_SECURE_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_SECURE_S_ROOT_CON1 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_OFFSET (0xD14U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_EN_MASK (0x1U << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_SWITCH_EN_SHIFT (13U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_SWITCH_EN_MASK (0x1U << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_CLKSEL_CFG_MASK (0x3U << SECURECRU_AUTOCS_ACLK_SECURE_S_ROOT_CON1_ACLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_HCLK_SECURE_S_ROOT_CON0 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_OFFSET (0xD18U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_IDLE_TH_SHIFT (0U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_IDLE_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_WAIT_TH_SHIFT (16U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_WAIT_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON0_HCLK_SECURE_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_SECURE_S_ROOT_CON1 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_OFFSET (0xD1CU) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_EN_MASK (0x1U << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_SWITCH_EN_SHIFT (13U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_SWITCH_EN_MASK (0x1U << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_CLKSEL_CFG_MASK (0x3U << SECURECRU_AUTOCS_HCLK_SECURE_S_ROOT_CON1_HCLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_PCLK_SECURE_S_ROOT_CON0 */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_OFFSET (0xD20U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_IDLE_TH_SHIFT (0U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_IDLE_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_WAIT_TH_SHIFT (16U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_WAIT_TH_MASK (0xFFFFU << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON0_PCLK_SECURE_S_ROOT_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_PCLK_SECURE_S_ROOT_CON1 */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_OFFSET (0xD24U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT (0U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_CTRL_MASK (0xFFFU << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT (12U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_EN_MASK (0x1U << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_SWITCH_EN_SHIFT (13U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_SWITCH_EN_MASK (0x1U << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT (14U) +#define SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_CLKSEL_CFG_MASK (0x3U << SECURECRU_AUTOCS_PCLK_SECURE_S_ROOT_CON1_PCLK_SECURE_S_ROOT_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/****************************************SBUSCRU*****************************************/ +/* SPLL_CON0 */ +#define SBUSCRU_SPLL_CON0_OFFSET (0x220U) +#define SBUSCRU_SPLL_CON0_SPLL_M_SHIFT (0U) +#define SBUSCRU_SPLL_CON0_SPLL_M_MASK (0x3FFU << SBUSCRU_SPLL_CON0_SPLL_M_SHIFT) /* 0x000003FF */ +#define SBUSCRU_SPLL_CON0_SPLL_BP_SHIFT (15U) +#define SBUSCRU_SPLL_CON0_SPLL_BP_MASK (0x1U << SBUSCRU_SPLL_CON0_SPLL_BP_SHIFT) /* 0x00008000 */ +/* SPLL_CON1 */ +#define SBUSCRU_SPLL_CON1_OFFSET (0x224U) +#define SBUSCRU_SPLL_CON1_SPLL_P_SHIFT (0U) +#define SBUSCRU_SPLL_CON1_SPLL_P_MASK (0x3FU << SBUSCRU_SPLL_CON1_SPLL_P_SHIFT) /* 0x0000003F */ +#define SBUSCRU_SPLL_CON1_SPLL_S_SHIFT (6U) +#define SBUSCRU_SPLL_CON1_SPLL_S_MASK (0x7U << SBUSCRU_SPLL_CON1_SPLL_S_SHIFT) /* 0x000001C0 */ +#define SBUSCRU_SPLL_CON1_SPLL_RESETB_SHIFT (13U) +#define SBUSCRU_SPLL_CON1_SPLL_RESETB_MASK (0x1U << SBUSCRU_SPLL_CON1_SPLL_RESETB_SHIFT) /* 0x00002000 */ +/* SPLL_CON4 */ +#define SBUSCRU_SPLL_CON4_OFFSET (0x228U) +#define SBUSCRU_SPLL_CON4_SPLL_ICP_SHIFT (1U) +#define SBUSCRU_SPLL_CON4_SPLL_ICP_MASK (0x3U << SBUSCRU_SPLL_CON4_SPLL_ICP_SHIFT) /* 0x00000006 */ +#define SBUSCRU_SPLL_CON4_SPLL_AFC_ENB_SHIFT (3U) +#define SBUSCRU_SPLL_CON4_SPLL_AFC_ENB_MASK (0x1U << SBUSCRU_SPLL_CON4_SPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define SBUSCRU_SPLL_CON4_SPLL_EXTAFC_SHIFT (4U) +#define SBUSCRU_SPLL_CON4_SPLL_EXTAFC_MASK (0x1FU << SBUSCRU_SPLL_CON4_SPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define SBUSCRU_SPLL_CON4_SPLL_FEED_EN_SHIFT (14U) +#define SBUSCRU_SPLL_CON4_SPLL_FEED_EN_MASK (0x1U << SBUSCRU_SPLL_CON4_SPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define SBUSCRU_SPLL_CON4_SPLL_FSEL_SHIFT (15U) +#define SBUSCRU_SPLL_CON4_SPLL_FSEL_MASK (0x1U << SBUSCRU_SPLL_CON4_SPLL_FSEL_SHIFT) /* 0x00008000 */ +/* SPLL_CON5 */ +#define SBUSCRU_SPLL_CON5_OFFSET (0x230U) +#define SBUSCRU_SPLL_CON5_SPLL_FOUT_MASK_SHIFT (0U) +#define SBUSCRU_SPLL_CON5_SPLL_FOUT_MASK_MASK (0x1U << SBUSCRU_SPLL_CON5_SPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_IN_SHIFT (5U) +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_IN_MASK (0x3U << SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_IN_SHIFT) /* 0x00000060 */ +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_OUT_SHIFT (7U) +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_OUT_MASK (0x3U << SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_OUT_SHIFT) /* 0x00000180 */ +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_DLY_SHIFT (9U) +#define SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_DLY_MASK (0x3U << SBUSCRU_SPLL_CON5_SPLL_LOCK_CON_DLY_SHIFT) /* 0x00000600 */ +/* SPLL_CON6 */ +#define SBUSCRU_SPLL_CON6_OFFSET (0x234U) +#define SBUSCRU_SPLL_CON6_SPLL_AFC_CODE_SHIFT (10U) +#define SBUSCRU_SPLL_CON6_SPLL_AFC_CODE_MASK (0x1FU << SBUSCRU_SPLL_CON6_SPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define SBUSCRU_SPLL_CON6_SPLL_LOCK_SHIFT (15U) +#define SBUSCRU_SPLL_CON6_SPLL_LOCK_MASK (0x1U << SBUSCRU_SPLL_CON6_SPLL_LOCK_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define SBUSCRU_MODE_CON00_OFFSET (0x280U) +#define SBUSCRU_MODE_CON00_CLK_SPLL_MODE_SHIFT (0U) +#define SBUSCRU_MODE_CON00_CLK_SPLL_MODE_MASK (0x3U << SBUSCRU_MODE_CON00_CLK_SPLL_MODE_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON00 */ +#define SBUSCRU_CLKSEL_CON00_OFFSET (0x300U) +#define SBUSCRU_CLKSEL_CON00_PCLK_SBUS_ROOT_DIV_SHIFT (0U) +#define SBUSCRU_CLKSEL_CON00_PCLK_SBUS_ROOT_DIV_MASK (0x1FU << SBUSCRU_CLKSEL_CON00_PCLK_SBUS_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_DIV_SHIFT (5U) +#define SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_DIV_MASK (0x1FU << SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_DIV_SHIFT) /* 0x000003E0 */ +#define SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_SEL_SHIFT (10U) +#define SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_SEL_MASK (0x1U << SBUSCRU_CLKSEL_CON00_CLK_MATRIX_SBUS_100M_SRC_SEL_SHIFT) /* 0x00000400 */ +#define SBUSCRU_CLKSEL_CON00_CLK_SBUS_TIMER_ROOT_SEL_SHIFT (11U) +#define SBUSCRU_CLKSEL_CON00_CLK_SBUS_TIMER_ROOT_SEL_MASK (0x1U << SBUSCRU_CLKSEL_CON00_CLK_SBUS_TIMER_ROOT_SEL_SHIFT) /* 0x00000800 */ +/* GATE_CON00 */ +#define SBUSCRU_GATE_CON00_OFFSET (0x800U) +#define SBUSCRU_GATE_CON00_PCLK_SBUS_ROOT_EN_SHIFT (0U) +#define SBUSCRU_GATE_CON00_PCLK_SBUS_ROOT_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_SBUS_ROOT_EN_SHIFT) /* 0x00000001 */ +#define SBUSCRU_GATE_CON00_PCLK_SBUS_BIU_EN_SHIFT (1U) +#define SBUSCRU_GATE_CON00_PCLK_SBUS_BIU_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_SBUS_BIU_EN_SHIFT) /* 0x00000002 */ +#define SBUSCRU_GATE_CON00_PCLK_SBUS_CRU_EN_SHIFT (2U) +#define SBUSCRU_GATE_CON00_PCLK_SBUS_CRU_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_SBUS_CRU_EN_SHIFT) /* 0x00000004 */ +#define SBUSCRU_GATE_CON00_PCLK_SBUS_SGRF_EN_SHIFT (3U) +#define SBUSCRU_GATE_CON00_PCLK_SBUS_SGRF_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_SBUS_SGRF_EN_SHIFT) /* 0x00000008 */ +#define SBUSCRU_GATE_CON00_PCLK_JDBCK_DAP_EN_SHIFT (4U) +#define SBUSCRU_GATE_CON00_PCLK_JDBCK_DAP_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_JDBCK_DAP_EN_SHIFT) /* 0x00000010 */ +#define SBUSCRU_GATE_CON00_CLK_JDBCK_DAP_EN_SHIFT (5U) +#define SBUSCRU_GATE_CON00_CLK_JDBCK_DAP_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_JDBCK_DAP_EN_SHIFT) /* 0x00000020 */ +#define SBUSCRU_GATE_CON00_CLK_MATRIX_SBUS_100M_SRC_EN_SHIFT (6U) +#define SBUSCRU_GATE_CON00_CLK_MATRIX_SBUS_100M_SRC_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_MATRIX_SBUS_100M_SRC_EN_SHIFT) /* 0x00000040 */ +#define SBUSCRU_GATE_CON00_PCLK_STIMER1_EN_SHIFT (7U) +#define SBUSCRU_GATE_CON00_PCLK_STIMER1_EN_MASK (0x1U << SBUSCRU_GATE_CON00_PCLK_STIMER1_EN_SHIFT) /* 0x00000080 */ +#define SBUSCRU_GATE_CON00_CLK_SBUS_TIMER_EN_SHIFT (8U) +#define SBUSCRU_GATE_CON00_CLK_SBUS_TIMER_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_SBUS_TIMER_EN_SHIFT) /* 0x00000100 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER6_EN_SHIFT (9U) +#define SBUSCRU_GATE_CON00_CLK_STIMER6_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER6_EN_SHIFT) /* 0x00000200 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER7_EN_SHIFT (10U) +#define SBUSCRU_GATE_CON00_CLK_STIMER7_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER7_EN_SHIFT) /* 0x00000400 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER8_EN_SHIFT (11U) +#define SBUSCRU_GATE_CON00_CLK_STIMER8_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER8_EN_SHIFT) /* 0x00000800 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER9_EN_SHIFT (12U) +#define SBUSCRU_GATE_CON00_CLK_STIMER9_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER9_EN_SHIFT) /* 0x00001000 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER10_EN_SHIFT (13U) +#define SBUSCRU_GATE_CON00_CLK_STIMER10_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER10_EN_SHIFT) /* 0x00002000 */ +#define SBUSCRU_GATE_CON00_CLK_STIMER11_EN_SHIFT (14U) +#define SBUSCRU_GATE_CON00_CLK_STIMER11_EN_MASK (0x1U << SBUSCRU_GATE_CON00_CLK_STIMER11_EN_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON00 */ +#define SBUSCRU_SOFTRST_CON00_OFFSET (0xA00U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_BIU_SHIFT (1U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_BIU_MASK (0x1U << SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_BIU_SHIFT) /* 0x00000002 */ +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_CRU_SHIFT (2U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_CRU_MASK (0x1U << SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_CRU_SHIFT) /* 0x00000004 */ +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_SGRF_SHIFT (3U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_SGRF_MASK (0x1U << SBUSCRU_SOFTRST_CON00_PRESETN_SBUS_SGRF_SHIFT) /* 0x00000008 */ +#define SBUSCRU_SOFTRST_CON00_PRESETN_JDBCK_DAP_SHIFT (4U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_JDBCK_DAP_MASK (0x1U << SBUSCRU_SOFTRST_CON00_PRESETN_JDBCK_DAP_SHIFT) /* 0x00000010 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_JDBCK_DAP_SHIFT (5U) +#define SBUSCRU_SOFTRST_CON00_RESETN_JDBCK_DAP_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_JDBCK_DAP_SHIFT) /* 0x00000020 */ +#define SBUSCRU_SOFTRST_CON00_PRESETN_STIMER1_SHIFT (7U) +#define SBUSCRU_SOFTRST_CON00_PRESETN_STIMER1_MASK (0x1U << SBUSCRU_SOFTRST_CON00_PRESETN_STIMER1_SHIFT) /* 0x00000080 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER6_SHIFT (9U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER6_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER6_SHIFT) /* 0x00000200 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER7_SHIFT (10U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER7_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER7_SHIFT) /* 0x00000400 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER8_SHIFT (11U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER8_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER8_SHIFT) /* 0x00000800 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER9_SHIFT (12U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER9_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER9_SHIFT) /* 0x00001000 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER10_SHIFT (13U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER10_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER10_SHIFT) /* 0x00002000 */ +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER11_SHIFT (14U) +#define SBUSCRU_SOFTRST_CON00_RESETN_STIMER11_MASK (0x1U << SBUSCRU_SOFTRST_CON00_RESETN_STIMER11_SHIFT) /* 0x00004000 */ +/****************************************PMU1SCRU****************************************/ +/* CLKSEL_CON00 */ +#define PMU1SCRU_CLKSEL_CON00_OFFSET (0x300U) +#define PMU1SCRU_CLKSEL_CON00_HCLK_PMU1_S_ROOT_I_SEL_SHIFT (0U) +#define PMU1SCRU_CLKSEL_CON00_HCLK_PMU1_S_ROOT_I_SEL_MASK (0x3U << PMU1SCRU_CLKSEL_CON00_HCLK_PMU1_S_ROOT_I_SEL_SHIFT) /* 0x00000003 */ +#define PMU1SCRU_CLKSEL_CON00_PCLK_PMU1_S_ROOT_I_SEL_SHIFT (2U) +#define PMU1SCRU_CLKSEL_CON00_PCLK_PMU1_S_ROOT_I_SEL_MASK (0x3U << PMU1SCRU_CLKSEL_CON00_PCLK_PMU1_S_ROOT_I_SEL_SHIFT) /* 0x0000000C */ +/* CLKSEL_CON02 */ +#define PMU1SCRU_CLKSEL_CON02_OFFSET (0x308U) +#define PMU1SCRU_CLKSEL_CON02_XIN_OSC0_DIV_DIV_SHIFT (0U) +#define PMU1SCRU_CLKSEL_CON02_XIN_OSC0_DIV_DIV_MASK (0xFFFFFFFFU << PMU1SCRU_CLKSEL_CON02_XIN_OSC0_DIV_DIV_SHIFT) /* 0xFFFFFFFF */ +/* GATE_CON00 */ +#define PMU1SCRU_GATE_CON00_OFFSET (0x800U) +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_I_EN_SHIFT (1U) +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_I_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_I_EN_SHIFT) /* 0x00000002 */ +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_EN_SHIFT (2U) +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_HCLK_PMU1_S_ROOT_EN_SHIFT) /* 0x00000004 */ +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_S_ROOT_EN_SHIFT (3U) +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_S_ROOT_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_PCLK_PMU1_S_ROOT_EN_SHIFT) /* 0x00000008 */ +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_BIU_EN_SHIFT (4U) +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_S_BIU_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_HCLK_PMU1_S_BIU_EN_SHIFT) /* 0x00000010 */ +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_S_BIU_EN_SHIFT (5U) +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_S_BIU_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_PCLK_PMU1_S_BIU_EN_SHIFT) /* 0x00000020 */ +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_OSC_CHK_EN_SHIFT (6U) +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_OSC_CHK_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_PCLK_PMU1_OSC_CHK_EN_SHIFT) /* 0x00000040 */ +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_MEM_EN_SHIFT (7U) +#define PMU1SCRU_GATE_CON00_HCLK_PMU1_MEM_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_HCLK_PMU1_MEM_EN_SHIFT) /* 0x00000080 */ +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_SGRF_EN_SHIFT (8U) +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_SGRF_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_PCLK_PMU1_SGRF_EN_SHIFT) /* 0x00000100 */ +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_CRU_S_EN_SHIFT (9U) +#define PMU1SCRU_GATE_CON00_PCLK_PMU1_CRU_S_EN_MASK (0x1U << PMU1SCRU_GATE_CON00_PCLK_PMU1_CRU_S_EN_SHIFT) /* 0x00000200 */ +/* GATE_CON01 */ +#define PMU1SCRU_GATE_CON01_OFFSET (0x804U) +#define PMU1SCRU_GATE_CON01_XIN_OSC0_DIV_EN_SHIFT (0U) +#define PMU1SCRU_GATE_CON01_XIN_OSC0_DIV_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_XIN_OSC0_DIV_EN_SHIFT) /* 0x00000001 */ +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_S_ROOT_EN_SHIFT (1U) +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_S_ROOT_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_PCLK_PMU0_S_ROOT_EN_SHIFT) /* 0x00000002 */ +#define PMU1SCRU_GATE_CON01_CLK_PMU0PVTM_EN_SHIFT (2U) +#define PMU1SCRU_GATE_CON01_CLK_PMU0PVTM_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_CLK_PMU0PVTM_EN_SHIFT) /* 0x00000004 */ +#define PMU1SCRU_GATE_CON01_PCLK_PMU0PVTM_EN_SHIFT (3U) +#define PMU1SCRU_GATE_CON01_PCLK_PMU0PVTM_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_PCLK_PMU0PVTM_EN_SHIFT) /* 0x00000008 */ +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_SGRF_EN_SHIFT (4U) +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_SGRF_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_PCLK_PMU0_SGRF_EN_SHIFT) /* 0x00000010 */ +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_SCRKEYGEN_EN_SHIFT (6U) +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_SCRKEYGEN_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_PCLK_PMU0_SCRKEYGEN_EN_SHIFT) /* 0x00000040 */ +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_HP_TIMER_EN_SHIFT (7U) +#define PMU1SCRU_GATE_CON01_PCLK_PMU0_HP_TIMER_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_PCLK_PMU0_HP_TIMER_EN_SHIFT) /* 0x00000080 */ +#define PMU1SCRU_GATE_CON01_CLK_PMU0_HP_TIMER_EN_SHIFT (8U) +#define PMU1SCRU_GATE_CON01_CLK_PMU0_HP_TIMER_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_CLK_PMU0_HP_TIMER_EN_SHIFT) /* 0x00000100 */ +#define PMU1SCRU_GATE_CON01_CLK_PMU0_32K_HP_TIMER_EN_SHIFT (9U) +#define PMU1SCRU_GATE_CON01_CLK_PMU0_32K_HP_TIMER_EN_MASK (0x1U << PMU1SCRU_GATE_CON01_CLK_PMU0_32K_HP_TIMER_EN_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON00 */ +#define PMU1SCRU_SOFTRST_CON00_OFFSET (0xA00U) +#define PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_S_BIU_SHIFT (4U) +#define PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_S_BIU_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_S_BIU_SHIFT) /* 0x00000010 */ +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_S_BIU_SHIFT (5U) +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_S_BIU_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_S_BIU_SHIFT) /* 0x00000020 */ +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_OSC_CHK_SHIFT (6U) +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_OSC_CHK_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_OSC_CHK_SHIFT) /* 0x00000040 */ +#define PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_MEM_SHIFT (7U) +#define PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_MEM_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_HRESETN_PMU1_MEM_SHIFT) /* 0x00000080 */ +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_SGRF_SHIFT (8U) +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_SGRF_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_SGRF_SHIFT) /* 0x00000100 */ +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_CRU_S_SHIFT (9U) +#define PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_CRU_S_MASK (0x1U << PMU1SCRU_SOFTRST_CON00_PRESETN_PMU1_CRU_S_SHIFT) /* 0x00000200 */ +/* SOFTRST_CON01 */ +#define PMU1SCRU_SOFTRST_CON01_OFFSET (0xA04U) +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0PVTM_SHIFT (2U) +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0PVTM_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_RESETN_PMU0PVTM_SHIFT) /* 0x00000004 */ +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0PVTM_SHIFT (3U) +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0PVTM_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0PVTM_SHIFT) /* 0x00000008 */ +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_SHIFT (4U) +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_SHIFT) /* 0x00000010 */ +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_REMAP_SHIFT (5U) +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_REMAP_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_SGRF_REMAP_SHIFT) /* 0x00000020 */ +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_HP_TIMER_SHIFT (7U) +#define PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_HP_TIMER_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_PRESETN_PMU0_HP_TIMER_SHIFT) /* 0x00000080 */ +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_HP_TIMER_SHIFT (8U) +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_HP_TIMER_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_HP_TIMER_SHIFT) /* 0x00000100 */ +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_32K_HP_TIMER_SHIFT (9U) +#define PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_32K_HP_TIMER_MASK (0x1U << PMU1SCRU_SOFTRST_CON01_RESETN_PMU0_32K_HP_TIMER_SHIFT) /* 0x00000200 */ +/****************************************PMU1CRU*****************************************/ +/* CLKSEL_CON00 */ +#define PMU1CRU_CLKSEL_CON00_OFFSET (0x300U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_50M_SRC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_50M_SRC_DIV_MASK (0xFU << PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_50M_SRC_DIV_SHIFT) /* 0x0000000F */ +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_100M_SRC_DIV_SHIFT (4U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_100M_SRC_DIV_MASK (0x7U << PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_100M_SRC_DIV_SHIFT) /* 0x00000070 */ +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_200M_SRC_DIV_SHIFT (7U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_200M_SRC_DIV_MASK (0x7U << PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_200M_SRC_DIV_SHIFT) /* 0x00000380 */ +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_DIV_SHIFT (10U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_DIV_SHIFT) /* 0x00007C00 */ +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_SEL_SHIFT (15U) +#define PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON00_CLK_MATRIX_PMU1_300M_SRC_SEL_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON01 */ +#define PMU1CRU_CLKSEL_CON01_OFFSET (0x304U) +#define PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_DIV_SHIFT) /* 0x0000001F */ +#define PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_SEL_SHIFT (5U) +#define PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON01_CLK_MATRIX_PMU1_400M_SRC_SEL_SHIFT) /* 0x00000020 */ +#define PMU1CRU_CLKSEL_CON01_HCLK_PMU1_ROOT_I_SEL_SHIFT (6U) +#define PMU1CRU_CLKSEL_CON01_HCLK_PMU1_ROOT_I_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON01_HCLK_PMU1_ROOT_I_SEL_SHIFT) /* 0x000000C0 */ +#define PMU1CRU_CLKSEL_CON01_PCLK_PMU1_ROOT_I_SEL_SHIFT (8U) +#define PMU1CRU_CLKSEL_CON01_PCLK_PMU1_ROOT_I_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON01_PCLK_PMU1_ROOT_I_SEL_SHIFT) /* 0x00000300 */ +#define PMU1CRU_CLKSEL_CON01_HCLK_PMU_CM0_ROOT_I_SEL_SHIFT (10U) +#define PMU1CRU_CLKSEL_CON01_HCLK_PMU_CM0_ROOT_I_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON01_HCLK_PMU_CM0_ROOT_I_SEL_SHIFT) /* 0x00000C00 */ +/* CLKSEL_CON02 */ +#define PMU1CRU_CLKSEL_CON02_OFFSET (0x308U) +#define PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_DIV_SHIFT) /* 0x0000001F */ +#define PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_SEL_SHIFT (5U) +#define PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON02_CLK_PMU_CM0_RTC_SEL_SHIFT) /* 0x00000020 */ +#define PMU1CRU_CLKSEL_CON02_TCLK_PMU1WDT_SEL_SHIFT (6U) +#define PMU1CRU_CLKSEL_CON02_TCLK_PMU1WDT_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON02_TCLK_PMU1WDT_SEL_SHIFT) /* 0x00000040 */ +#define PMU1CRU_CLKSEL_CON02_CLK_PMU1TIMER_ROOT_SEL_SHIFT (7U) +#define PMU1CRU_CLKSEL_CON02_CLK_PMU1TIMER_ROOT_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON02_CLK_PMU1TIMER_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define PMU1CRU_CLKSEL_CON02_CLK_PMU1PWM_SEL_SHIFT (9U) +#define PMU1CRU_CLKSEL_CON02_CLK_PMU1PWM_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON02_CLK_PMU1PWM_SEL_SHIFT) /* 0x00000600 */ +/* CLKSEL_CON03 */ +#define PMU1CRU_CLKSEL_CON03_OFFSET (0x30CU) +#define PMU1CRU_CLKSEL_CON03_CLK_I2C0_SEL_SHIFT (6U) +#define PMU1CRU_CLKSEL_CON03_CLK_I2C0_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON03_CLK_I2C0_SEL_SHIFT) /* 0x00000040 */ +#define PMU1CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_SHIFT (7U) +#define PMU1CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON03_CLK_UART0_SRC_DIV_SHIFT) /* 0x00000F80 */ +/* CLKSEL_CON04 */ +#define PMU1CRU_CLKSEL_CON04_OFFSET (0x310U) +#define PMU1CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_MASK (0xFFFFFFFFU << PMU1CRU_CLKSEL_CON04_CLK_UART0_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON05 */ +#define PMU1CRU_CLKSEL_CON05_OFFSET (0x314U) +#define PMU1CRU_CLKSEL_CON05_SCLK_UART0_SEL_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON05_SCLK_UART0_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON05_SCLK_UART0_SEL_SHIFT) /* 0x00000003 */ +#define PMU1CRU_CLKSEL_CON05_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT (2U) +#define PMU1CRU_CLKSEL_CON05_CLK_I2S1_8CH_TX_SRC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON05_CLK_I2S1_8CH_TX_SRC_DIV_SHIFT) /* 0x0000007C */ +/* CLKSEL_CON06 */ +#define PMU1CRU_CLKSEL_CON06_OFFSET (0x318U) +#define PMU1CRU_CLKSEL_CON06_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON06_CLK_I2S1_8CH_TX_FRAC_DIV_MASK (0xFFFFFFFFU << PMU1CRU_CLKSEL_CON06_CLK_I2S1_8CH_TX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON07 */ +#define PMU1CRU_CLKSEL_CON07_OFFSET (0x31CU) +#define PMU1CRU_CLKSEL_CON07_MCLK_I2S1_8CH_TX_SEL_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON07_MCLK_I2S1_8CH_TX_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON07_MCLK_I2S1_8CH_TX_SEL_SHIFT) /* 0x00000003 */ +#define PMU1CRU_CLKSEL_CON07_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT (2U) +#define PMU1CRU_CLKSEL_CON07_CLK_I2S1_8CH_RX_SRC_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON07_CLK_I2S1_8CH_RX_SRC_DIV_SHIFT) /* 0x0000007C */ +/* CLKSEL_CON08 */ +#define PMU1CRU_CLKSEL_CON08_OFFSET (0x320U) +#define PMU1CRU_CLKSEL_CON08_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON08_CLK_I2S1_8CH_RX_FRAC_DIV_MASK (0xFFFFFFFFU << PMU1CRU_CLKSEL_CON08_CLK_I2S1_8CH_RX_FRAC_DIV_SHIFT) /* 0xFFFFFFFF */ +/* CLKSEL_CON09 */ +#define PMU1CRU_CLKSEL_CON09_OFFSET (0x324U) +#define PMU1CRU_CLKSEL_CON09_MCLK_I2S1_8CH_RX_SEL_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON09_MCLK_I2S1_8CH_RX_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON09_MCLK_I2S1_8CH_RX_SEL_SHIFT) /* 0x00000003 */ +#define PMU1CRU_CLKSEL_CON09_I2S1_8CH_MCLKOUT_SEL_SHIFT (2U) +#define PMU1CRU_CLKSEL_CON09_I2S1_8CH_MCLKOUT_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON09_I2S1_8CH_MCLKOUT_SEL_SHIFT) /* 0x0000000C */ +#define PMU1CRU_CLKSEL_CON09_MCLK_PDM0_SEL_SHIFT (4U) +#define PMU1CRU_CLKSEL_CON09_MCLK_PDM0_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON09_MCLK_PDM0_SEL_SHIFT) /* 0x00000010 */ +#define PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_DIV_SHIFT (5U) +#define PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_DIV_SHIFT) /* 0x000003E0 */ +#define PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_SHIFT (10U) +#define PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON09_CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_SHIFT) /* 0x00000400 */ +/* CLKSEL_CON12 */ +#define PMU1CRU_CLKSEL_CON12_OFFSET (0x330U) +#define PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_DIV_SHIFT (6U) +#define PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_DIV_SHIFT) /* 0x000007C0 */ +#define PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_SEL_SHIFT (11U) +#define PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON12_CLK_HDPTX0_REF_XTAL_SEL_SHIFT) /* 0x00000800 */ +/* CLKSEL_CON14 */ +#define PMU1CRU_CLKSEL_CON14_OFFSET (0x338U) +#define PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_DIV_MASK (0x7FU << PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_DIV_SHIFT) /* 0x0000007F */ +#define PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_SEL_SHIFT (7U) +#define PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON14_CLK_REF_MIPI_DCPHY0_SEL_SHIFT) /* 0x00000180 */ +#define PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_DIV_SHIFT (9U) +#define PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_DIV_SHIFT) /* 0x00003E00 */ +#define PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_SEL_SHIFT (14U) +#define PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON14_CLK_OTGPHY_U3_0_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON15 */ +#define PMU1CRU_CLKSEL_CON15_OFFSET (0x33CU) +#define PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_DIV_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_DIV_MASK (0x1FU << PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_DIV_SHIFT) /* 0x0000001F */ +#define PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_SEL_SHIFT (5U) +#define PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_SEL_MASK (0x3U << PMU1CRU_CLKSEL_CON15_CLK_CR_PARA_SEL_SHIFT) /* 0x00000060 */ +/* CLKSEL_CON17 */ +#define PMU1CRU_CLKSEL_CON17_OFFSET (0x344U) +#define PMU1CRU_CLKSEL_CON17_DBCLK_GPIO0_SEL_SHIFT (0U) +#define PMU1CRU_CLKSEL_CON17_DBCLK_GPIO0_SEL_MASK (0x1U << PMU1CRU_CLKSEL_CON17_DBCLK_GPIO0_SEL_SHIFT) /* 0x00000001 */ +/* GATE_CON00 */ +#define PMU1CRU_GATE_CON00_OFFSET (0x800U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_50M_SRC_EN_SHIFT (0U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_50M_SRC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_50M_SRC_EN_SHIFT) /* 0x00000001 */ +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_100M_SRC_EN_SHIFT (1U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_100M_SRC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_100M_SRC_EN_SHIFT) /* 0x00000002 */ +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_200M_SRC_EN_SHIFT (2U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_200M_SRC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_200M_SRC_EN_SHIFT) /* 0x00000004 */ +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_300M_SRC_EN_SHIFT (3U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_300M_SRC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_300M_SRC_EN_SHIFT) /* 0x00000008 */ +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_400M_SRC_EN_SHIFT (4U) +#define PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_400M_SRC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_MATRIX_PMU1_400M_SRC_EN_SHIFT) /* 0x00000010 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_I_EN_SHIFT (5U) +#define PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_I_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_I_EN_SHIFT) /* 0x00000020 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_EN_SHIFT (6U) +#define PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU1_ROOT_EN_SHIFT) /* 0x00000040 */ +#define PMU1CRU_GATE_CON00_PCLK_PMU1_ROOT_I_EN_SHIFT (7U) +#define PMU1CRU_GATE_CON00_PCLK_PMU1_ROOT_I_EN_MASK (0x1U << PMU1CRU_GATE_CON00_PCLK_PMU1_ROOT_I_EN_SHIFT) /* 0x00000080 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_I_EN_SHIFT (8U) +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_I_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_I_EN_SHIFT) /* 0x00000100 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_EN_SHIFT (9U) +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU_CM0_ROOT_EN_SHIFT) /* 0x00000200 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU1_BIU_EN_SHIFT (10U) +#define PMU1CRU_GATE_CON00_HCLK_PMU1_BIU_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU1_BIU_EN_SHIFT) /* 0x00000400 */ +#define PMU1CRU_GATE_CON00_PCLK_PMU1_BIU_EN_SHIFT (11U) +#define PMU1CRU_GATE_CON00_PCLK_PMU1_BIU_EN_MASK (0x1U << PMU1CRU_GATE_CON00_PCLK_PMU1_BIU_EN_SHIFT) /* 0x00000800 */ +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_BIU_EN_SHIFT (12U) +#define PMU1CRU_GATE_CON00_HCLK_PMU_CM0_BIU_EN_MASK (0x1U << PMU1CRU_GATE_CON00_HCLK_PMU_CM0_BIU_EN_SHIFT) /* 0x00001000 */ +#define PMU1CRU_GATE_CON00_FCLK_PMU_CM0_CORE_EN_SHIFT (13U) +#define PMU1CRU_GATE_CON00_FCLK_PMU_CM0_CORE_EN_MASK (0x1U << PMU1CRU_GATE_CON00_FCLK_PMU_CM0_CORE_EN_SHIFT) /* 0x00002000 */ +#define PMU1CRU_GATE_CON00_CLK_PMU_CM0_RTC_EN_SHIFT (15U) +#define PMU1CRU_GATE_CON00_CLK_PMU_CM0_RTC_EN_MASK (0x1U << PMU1CRU_GATE_CON00_CLK_PMU_CM0_RTC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define PMU1CRU_GATE_CON01_OFFSET (0x804U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1_EN_SHIFT (0U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1_EN_SHIFT) /* 0x00000001 */ +#define PMU1CRU_GATE_CON01_CLK_DDR_FAIL_SAFE_EN_SHIFT (1U) +#define PMU1CRU_GATE_CON01_CLK_DDR_FAIL_SAFE_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_DDR_FAIL_SAFE_EN_SHIFT) /* 0x00000002 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1_CRU_EN_SHIFT (2U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1_CRU_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1_CRU_EN_SHIFT) /* 0x00000004 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1_EN_SHIFT (3U) +#define PMU1CRU_GATE_CON01_CLK_PMU1_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1_EN_SHIFT) /* 0x00000008 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1_GRF_EN_SHIFT (4U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1_GRF_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1_GRF_EN_SHIFT) /* 0x00000010 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1_IOC_EN_SHIFT (5U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1_IOC_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1_IOC_EN_SHIFT) /* 0x00000020 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1WDT_EN_SHIFT (6U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1WDT_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1WDT_EN_SHIFT) /* 0x00000040 */ +#define PMU1CRU_GATE_CON01_TCLK_PMU1WDT_EN_SHIFT (7U) +#define PMU1CRU_GATE_CON01_TCLK_PMU1WDT_EN_MASK (0x1U << PMU1CRU_GATE_CON01_TCLK_PMU1WDT_EN_SHIFT) /* 0x00000080 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1TIMER_EN_SHIFT (8U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1TIMER_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1TIMER_EN_SHIFT) /* 0x00000100 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER_ROOT_EN_SHIFT (9U) +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER_ROOT_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1TIMER_ROOT_EN_SHIFT) /* 0x00000200 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER0_EN_SHIFT (10U) +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER0_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1TIMER0_EN_SHIFT) /* 0x00000400 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER1_EN_SHIFT (11U) +#define PMU1CRU_GATE_CON01_CLK_PMU1TIMER1_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1TIMER1_EN_SHIFT) /* 0x00000800 */ +#define PMU1CRU_GATE_CON01_PCLK_PMU1PWM_EN_SHIFT (12U) +#define PMU1CRU_GATE_CON01_PCLK_PMU1PWM_EN_MASK (0x1U << PMU1CRU_GATE_CON01_PCLK_PMU1PWM_EN_SHIFT) /* 0x00001000 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1PWM_EN_SHIFT (13U) +#define PMU1CRU_GATE_CON01_CLK_PMU1PWM_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1PWM_EN_SHIFT) /* 0x00002000 */ +#define PMU1CRU_GATE_CON01_CLK_PMU1PWM_CAPTURE_EN_SHIFT (14U) +#define PMU1CRU_GATE_CON01_CLK_PMU1PWM_CAPTURE_EN_MASK (0x1U << PMU1CRU_GATE_CON01_CLK_PMU1PWM_CAPTURE_EN_SHIFT) /* 0x00004000 */ +/* GATE_CON02 */ +#define PMU1CRU_GATE_CON02_OFFSET (0x808U) +#define PMU1CRU_GATE_CON02_PCLK_I2C0_EN_SHIFT (1U) +#define PMU1CRU_GATE_CON02_PCLK_I2C0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_PCLK_I2C0_EN_SHIFT) /* 0x00000002 */ +#define PMU1CRU_GATE_CON02_CLK_I2C0_EN_SHIFT (2U) +#define PMU1CRU_GATE_CON02_CLK_I2C0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_I2C0_EN_SHIFT) /* 0x00000004 */ +#define PMU1CRU_GATE_CON02_CLK_UART0_EN_SHIFT (3U) +#define PMU1CRU_GATE_CON02_CLK_UART0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_UART0_EN_SHIFT) /* 0x00000008 */ +#define PMU1CRU_GATE_CON02_CLK_UART0_FRAC_EN_SHIFT (4U) +#define PMU1CRU_GATE_CON02_CLK_UART0_FRAC_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_UART0_FRAC_EN_SHIFT) /* 0x00000010 */ +#define PMU1CRU_GATE_CON02_SCLK_UART0_EN_SHIFT (5U) +#define PMU1CRU_GATE_CON02_SCLK_UART0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_SCLK_UART0_EN_SHIFT) /* 0x00000020 */ +#define PMU1CRU_GATE_CON02_PCLK_UART0_EN_SHIFT (6U) +#define PMU1CRU_GATE_CON02_PCLK_UART0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_PCLK_UART0_EN_SHIFT) /* 0x00000040 */ +#define PMU1CRU_GATE_CON02_HCLK_I2S1_8CH_EN_SHIFT (7U) +#define PMU1CRU_GATE_CON02_HCLK_I2S1_8CH_EN_MASK (0x1U << PMU1CRU_GATE_CON02_HCLK_I2S1_8CH_EN_SHIFT) /* 0x00000080 */ +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_TX_EN_SHIFT (8U) +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_TX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_I2S1_8CH_TX_EN_SHIFT) /* 0x00000100 */ +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_TX_EN_SHIFT (9U) +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_TX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_TX_EN_SHIFT) /* 0x00000200 */ +#define PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_TX_EN_SHIFT (10U) +#define PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_TX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_TX_EN_SHIFT) /* 0x00000400 */ +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_RX_EN_SHIFT (11U) +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_RX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_I2S1_8CH_RX_EN_SHIFT) /* 0x00000800 */ +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_RX_EN_SHIFT (12U) +#define PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_RX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_CLK_I2S1_8CH_FRAC_RX_EN_SHIFT) /* 0x00001000 */ +#define PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_RX_EN_SHIFT (13U) +#define PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_RX_EN_MASK (0x1U << PMU1CRU_GATE_CON02_MCLK_I2S1_8CH_RX_EN_SHIFT) /* 0x00002000 */ +#define PMU1CRU_GATE_CON02_HCLK_PDM0_EN_SHIFT (14U) +#define PMU1CRU_GATE_CON02_HCLK_PDM0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_HCLK_PDM0_EN_SHIFT) /* 0x00004000 */ +#define PMU1CRU_GATE_CON02_MCLK_PDM0_EN_SHIFT (15U) +#define PMU1CRU_GATE_CON02_MCLK_PDM0_EN_MASK (0x1U << PMU1CRU_GATE_CON02_MCLK_PDM0_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON03 */ +#define PMU1CRU_GATE_CON03_OFFSET (0x80CU) +#define PMU1CRU_GATE_CON03_HCLK_VAD_EN_SHIFT (0U) +#define PMU1CRU_GATE_CON03_HCLK_VAD_EN_MASK (0x1U << PMU1CRU_GATE_CON03_HCLK_VAD_EN_SHIFT) /* 0x00000001 */ +#define PMU1CRU_GATE_CON03_CLK_USBDP_COMBO_PHY0_REF_XTAL_EN_SHIFT (5U) +#define PMU1CRU_GATE_CON03_CLK_USBDP_COMBO_PHY0_REF_XTAL_EN_MASK (0x1U << PMU1CRU_GATE_CON03_CLK_USBDP_COMBO_PHY0_REF_XTAL_EN_SHIFT) /* 0x00000020 */ +#define PMU1CRU_GATE_CON03_CLK_HDPTX0_REF_XTAL_EN_SHIFT (11U) +#define PMU1CRU_GATE_CON03_CLK_HDPTX0_REF_XTAL_EN_MASK (0x1U << PMU1CRU_GATE_CON03_CLK_HDPTX0_REF_XTAL_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON04 */ +#define PMU1CRU_GATE_CON04_OFFSET (0x810U) +#define PMU1CRU_GATE_CON04_CLK_REF_MIPI_DCPHY0_EN_SHIFT (3U) +#define PMU1CRU_GATE_CON04_CLK_REF_MIPI_DCPHY0_EN_MASK (0x1U << PMU1CRU_GATE_CON04_CLK_REF_MIPI_DCPHY0_EN_SHIFT) /* 0x00000008 */ +#define PMU1CRU_GATE_CON04_CLK_OTGPHY_U3_0_EN_SHIFT (7U) +#define PMU1CRU_GATE_CON04_CLK_OTGPHY_U3_0_EN_MASK (0x1U << PMU1CRU_GATE_CON04_CLK_OTGPHY_U3_0_EN_SHIFT) /* 0x00000080 */ +#define PMU1CRU_GATE_CON04_CLK_CR_PARA_EN_SHIFT (11U) +#define PMU1CRU_GATE_CON04_CLK_CR_PARA_EN_MASK (0x1U << PMU1CRU_GATE_CON04_CLK_CR_PARA_EN_SHIFT) /* 0x00000800 */ +/* GATE_CON05 */ +#define PMU1CRU_GATE_CON05_OFFSET (0x814U) +#define PMU1CRU_GATE_CON05_PCLK_PMU0_ROOT_EN_SHIFT (0U) +#define PMU1CRU_GATE_CON05_PCLK_PMU0_ROOT_EN_MASK (0x1U << PMU1CRU_GATE_CON05_PCLK_PMU0_ROOT_EN_SHIFT) /* 0x00000001 */ +#define PMU1CRU_GATE_CON05_CLK_PMU0_EN_SHIFT (1U) +#define PMU1CRU_GATE_CON05_CLK_PMU0_EN_MASK (0x1U << PMU1CRU_GATE_CON05_CLK_PMU0_EN_SHIFT) /* 0x00000002 */ +#define PMU1CRU_GATE_CON05_PCLK_PMU0_EN_SHIFT (2U) +#define PMU1CRU_GATE_CON05_PCLK_PMU0_EN_MASK (0x1U << PMU1CRU_GATE_CON05_PCLK_PMU0_EN_SHIFT) /* 0x00000004 */ +#define PMU1CRU_GATE_CON05_PCLK_PMU0GRF_EN_SHIFT (3U) +#define PMU1CRU_GATE_CON05_PCLK_PMU0GRF_EN_MASK (0x1U << PMU1CRU_GATE_CON05_PCLK_PMU0GRF_EN_SHIFT) /* 0x00000008 */ +#define PMU1CRU_GATE_CON05_PCLK_PMU0IOC_EN_SHIFT (4U) +#define PMU1CRU_GATE_CON05_PCLK_PMU0IOC_EN_MASK (0x1U << PMU1CRU_GATE_CON05_PCLK_PMU0IOC_EN_SHIFT) /* 0x00000010 */ +#define PMU1CRU_GATE_CON05_PCLK_GPIO0_EN_SHIFT (5U) +#define PMU1CRU_GATE_CON05_PCLK_GPIO0_EN_MASK (0x1U << PMU1CRU_GATE_CON05_PCLK_GPIO0_EN_SHIFT) /* 0x00000020 */ +#define PMU1CRU_GATE_CON05_DBCLK_GPIO0_EN_SHIFT (6U) +#define PMU1CRU_GATE_CON05_DBCLK_GPIO0_EN_MASK (0x1U << PMU1CRU_GATE_CON05_DBCLK_GPIO0_EN_SHIFT) /* 0x00000040 */ +/* SOFTRST_CON00 */ +#define PMU1CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define PMU1CRU_SOFTRST_CON00_HRESETN_PMU1_BIU_SHIFT (10U) +#define PMU1CRU_SOFTRST_CON00_HRESETN_PMU1_BIU_MASK (0x1U << PMU1CRU_SOFTRST_CON00_HRESETN_PMU1_BIU_SHIFT) /* 0x00000400 */ +#define PMU1CRU_SOFTRST_CON00_PRESETN_PMU1_BIU_SHIFT (11U) +#define PMU1CRU_SOFTRST_CON00_PRESETN_PMU1_BIU_MASK (0x1U << PMU1CRU_SOFTRST_CON00_PRESETN_PMU1_BIU_SHIFT) /* 0x00000800 */ +#define PMU1CRU_SOFTRST_CON00_HRESETN_PMU_CM0_BIU_SHIFT (12U) +#define PMU1CRU_SOFTRST_CON00_HRESETN_PMU_CM0_BIU_MASK (0x1U << PMU1CRU_SOFTRST_CON00_HRESETN_PMU_CM0_BIU_SHIFT) /* 0x00001000 */ +#define PMU1CRU_SOFTRST_CON00_FRESETN_PMU_CM0_CORE_SHIFT (13U) +#define PMU1CRU_SOFTRST_CON00_FRESETN_PMU_CM0_CORE_MASK (0x1U << PMU1CRU_SOFTRST_CON00_FRESETN_PMU_CM0_CORE_SHIFT) /* 0x00002000 */ +#define PMU1CRU_SOFTRST_CON00_TRESETN_PMU1_CM0_JTAG_SHIFT (14U) +#define PMU1CRU_SOFTRST_CON00_TRESETN_PMU1_CM0_JTAG_MASK (0x1U << PMU1CRU_SOFTRST_CON00_TRESETN_PMU1_CM0_JTAG_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON01 */ +#define PMU1CRU_SOFTRST_CON01_OFFSET (0xA04U) +#define PMU1CRU_SOFTRST_CON01_RESETN_DDR_FAIL_SAFE_SHIFT (1U) +#define PMU1CRU_SOFTRST_CON01_RESETN_DDR_FAIL_SAFE_MASK (0x1U << PMU1CRU_SOFTRST_CON01_RESETN_DDR_FAIL_SAFE_SHIFT) /* 0x00000002 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_CRU_PMU1_SHIFT (2U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_CRU_PMU1_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_CRU_PMU1_SHIFT) /* 0x00000004 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_GRF_SHIFT (4U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_GRF_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_GRF_SHIFT) /* 0x00000010 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_IOC_SHIFT (5U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_IOC_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_PMU1_IOC_SHIFT) /* 0x00000020 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1WDT_SHIFT (6U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1WDT_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_PMU1WDT_SHIFT) /* 0x00000040 */ +#define PMU1CRU_SOFTRST_CON01_TRESETN_PMU1WDT_SHIFT (7U) +#define PMU1CRU_SOFTRST_CON01_TRESETN_PMU1WDT_MASK (0x1U << PMU1CRU_SOFTRST_CON01_TRESETN_PMU1WDT_SHIFT) /* 0x00000080 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1TIMER_SHIFT (8U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1TIMER_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_PMU1TIMER_SHIFT) /* 0x00000100 */ +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER0_SHIFT (10U) +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER0_MASK (0x1U << PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER0_SHIFT) /* 0x00000400 */ +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER1_SHIFT (11U) +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER1_MASK (0x1U << PMU1CRU_SOFTRST_CON01_RESETN_PMU1TIMER1_SHIFT) /* 0x00000800 */ +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1PWM_SHIFT (12U) +#define PMU1CRU_SOFTRST_CON01_PRESETN_PMU1PWM_MASK (0x1U << PMU1CRU_SOFTRST_CON01_PRESETN_PMU1PWM_SHIFT) /* 0x00001000 */ +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1PWM_SHIFT (13U) +#define PMU1CRU_SOFTRST_CON01_RESETN_PMU1PWM_MASK (0x1U << PMU1CRU_SOFTRST_CON01_RESETN_PMU1PWM_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON02 */ +#define PMU1CRU_SOFTRST_CON02_OFFSET (0xA08U) +#define PMU1CRU_SOFTRST_CON02_PRESETN_I2C0_SHIFT (1U) +#define PMU1CRU_SOFTRST_CON02_PRESETN_I2C0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_PRESETN_I2C0_SHIFT) /* 0x00000002 */ +#define PMU1CRU_SOFTRST_CON02_RESETN_I2C0_SHIFT (2U) +#define PMU1CRU_SOFTRST_CON02_RESETN_I2C0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_RESETN_I2C0_SHIFT) /* 0x00000004 */ +#define PMU1CRU_SOFTRST_CON02_SRESETN_UART0_SHIFT (5U) +#define PMU1CRU_SOFTRST_CON02_SRESETN_UART0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_SRESETN_UART0_SHIFT) /* 0x00000020 */ +#define PMU1CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT (6U) +#define PMU1CRU_SOFTRST_CON02_PRESETN_UART0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_PRESETN_UART0_SHIFT) /* 0x00000040 */ +#define PMU1CRU_SOFTRST_CON02_HRESETN_I2S1_8CH_SHIFT (7U) +#define PMU1CRU_SOFTRST_CON02_HRESETN_I2S1_8CH_MASK (0x1U << PMU1CRU_SOFTRST_CON02_HRESETN_I2S1_8CH_SHIFT) /* 0x00000080 */ +#define PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_TX_SHIFT (10U) +#define PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_TX_MASK (0x1U << PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_TX_SHIFT) /* 0x00000400 */ +#define PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_RX_SHIFT (13U) +#define PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_RX_MASK (0x1U << PMU1CRU_SOFTRST_CON02_MRESETN_I2S1_8CH_RX_SHIFT) /* 0x00002000 */ +#define PMU1CRU_SOFTRST_CON02_HRESETN_PDM0_SHIFT (14U) +#define PMU1CRU_SOFTRST_CON02_HRESETN_PDM0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_HRESETN_PDM0_SHIFT) /* 0x00004000 */ +#define PMU1CRU_SOFTRST_CON02_RESETN_PDM0_SHIFT (15U) +#define PMU1CRU_SOFTRST_CON02_RESETN_PDM0_MASK (0x1U << PMU1CRU_SOFTRST_CON02_RESETN_PDM0_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON03 */ +#define PMU1CRU_SOFTRST_CON03_OFFSET (0xA0CU) +#define PMU1CRU_SOFTRST_CON03_HRESETN_VAD_SHIFT (0U) +#define PMU1CRU_SOFTRST_CON03_HRESETN_VAD_MASK (0x1U << PMU1CRU_SOFTRST_CON03_HRESETN_VAD_SHIFT) /* 0x00000001 */ +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_INIT_SHIFT (11U) +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_INIT_MASK (0x1U << PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_INIT_SHIFT) /* 0x00000800 */ +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_CMN_SHIFT (12U) +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_CMN_MASK (0x1U << PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_CMN_SHIFT) /* 0x00001000 */ +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_LANE_SHIFT (13U) +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_LANE_MASK (0x1U << PMU1CRU_SOFTRST_CON03_RESETN_HDPTX0_LANE_SHIFT) /* 0x00002000 */ +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX1_INIT_SHIFT (15U) +#define PMU1CRU_SOFTRST_CON03_RESETN_HDPTX1_INIT_MASK (0x1U << PMU1CRU_SOFTRST_CON03_RESETN_HDPTX1_INIT_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON04 */ +#define PMU1CRU_SOFTRST_CON04_OFFSET (0xA10U) +#define PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_CMN_SHIFT (0U) +#define PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_CMN_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_CMN_SHIFT) /* 0x00000001 */ +#define PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_LANE_SHIFT (1U) +#define PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_LANE_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_HDPTX1_LANE_SHIFT) /* 0x00000002 */ +#define PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY0_SHIFT (3U) +#define PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY0_MASK (0x1U << PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY0_SHIFT) /* 0x00000008 */ +#define PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY0_SHIFT (4U) +#define PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY0_MASK (0x1U << PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY0_SHIFT) /* 0x00000010 */ +#define PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY1_SHIFT (5U) +#define PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY1_MASK (0x1U << PMU1CRU_SOFTRST_CON04_MRESETN_MIPI_DCPHY1_SHIFT) /* 0x00000020 */ +#define PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY1_SHIFT (6U) +#define PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY1_MASK (0x1U << PMU1CRU_SOFTRST_CON04_SRESETN_MIPI_DCPHY1_SHIFT) /* 0x00000040 */ +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_0_SHIFT (7U) +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_0_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_0_SHIFT) /* 0x00000080 */ +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_1_SHIFT (8U) +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_1_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U3_1_SHIFT) /* 0x00000100 */ +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_0_SHIFT (9U) +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_0_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_0_SHIFT) /* 0x00000200 */ +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_1_SHIFT (10U) +#define PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_1_MASK (0x1U << PMU1CRU_SOFTRST_CON04_RESETN_OTGPHY_U2_1_SHIFT) /* 0x00000400 */ +/* SOFTRST_CON05 */ +#define PMU1CRU_SOFTRST_CON05_OFFSET (0xA14U) +#define PMU1CRU_SOFTRST_CON05_PRESETN_PMU0GRF_SHIFT (3U) +#define PMU1CRU_SOFTRST_CON05_PRESETN_PMU0GRF_MASK (0x1U << PMU1CRU_SOFTRST_CON05_PRESETN_PMU0GRF_SHIFT) /* 0x00000008 */ +#define PMU1CRU_SOFTRST_CON05_PRESETN_PMU0IOC_SHIFT (4U) +#define PMU1CRU_SOFTRST_CON05_PRESETN_PMU0IOC_MASK (0x1U << PMU1CRU_SOFTRST_CON05_PRESETN_PMU0IOC_SHIFT) /* 0x00000010 */ +#define PMU1CRU_SOFTRST_CON05_PRESETN_GPIO0_SHIFT (5U) +#define PMU1CRU_SOFTRST_CON05_PRESETN_GPIO0_MASK (0x1U << PMU1CRU_SOFTRST_CON05_PRESETN_GPIO0_SHIFT) /* 0x00000020 */ +#define PMU1CRU_SOFTRST_CON05_DBRESETN_GPIO0_SHIFT (6U) +#define PMU1CRU_SOFTRST_CON05_DBRESETN_GPIO0_MASK (0x1U << PMU1CRU_SOFTRST_CON05_DBRESETN_GPIO0_SHIFT) /* 0x00000040 */ +/* AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0 */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_OFFSET (0xD00U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_IDLE_TH_SHIFT (0U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_IDLE_TH_MASK (0xFFFFU << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_WAIT_TH_SHIFT (16U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_WAIT_TH_MASK (0xFFFFU << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0_HCLK_PMU_CM0_ROOT_I_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1 */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_OFFSET (0xD04U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_CTRL_SHIFT (0U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_CTRL_MASK (0xFFFU << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_EN_SHIFT (12U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_EN_MASK (0x1U << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_SWITCH_EN_SHIFT (13U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_SWITCH_EN_MASK (0x1U << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_CLKSEL_CFG_SHIFT (14U) +#define PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_CLKSEL_CFG_MASK (0x3U << PMU1CRU_AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1_HCLK_PMU_CM0_ROOT_I_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/****************************************DDR0CRU*****************************************/ +/* D0APLL_CON0 */ +#define DDR0CRU_D0APLL_CON0_OFFSET (0x0U) +#define DDR0CRU_D0APLL_CON0_D0APLL_M_SHIFT (0U) +#define DDR0CRU_D0APLL_CON0_D0APLL_M_MASK (0x3FFU << DDR0CRU_D0APLL_CON0_D0APLL_M_SHIFT) /* 0x000003FF */ +#define DDR0CRU_D0APLL_CON0_D0APLL_BP_SHIFT (15U) +#define DDR0CRU_D0APLL_CON0_D0APLL_BP_MASK (0x1U << DDR0CRU_D0APLL_CON0_D0APLL_BP_SHIFT) /* 0x00008000 */ +/* D0APLL_CON1 */ +#define DDR0CRU_D0APLL_CON1_OFFSET (0x4U) +#define DDR0CRU_D0APLL_CON1_D0APLL_P_SHIFT (0U) +#define DDR0CRU_D0APLL_CON1_D0APLL_P_MASK (0x3FU << DDR0CRU_D0APLL_CON1_D0APLL_P_SHIFT) /* 0x0000003F */ +#define DDR0CRU_D0APLL_CON1_D0APLL_S_SHIFT (6U) +#define DDR0CRU_D0APLL_CON1_D0APLL_S_MASK (0x7U << DDR0CRU_D0APLL_CON1_D0APLL_S_SHIFT) /* 0x000001C0 */ +#define DDR0CRU_D0APLL_CON1_D0APLL_RESETB_SHIFT (13U) +#define DDR0CRU_D0APLL_CON1_D0APLL_RESETB_MASK (0x1U << DDR0CRU_D0APLL_CON1_D0APLL_RESETB_SHIFT) /* 0x00002000 */ +/* D0APLL_CON2 */ +#define DDR0CRU_D0APLL_CON2_OFFSET (0x8U) +#define DDR0CRU_D0APLL_CON2_D0APLL_K_SHIFT (0U) +#define DDR0CRU_D0APLL_CON2_D0APLL_K_MASK (0xFFFFU << DDR0CRU_D0APLL_CON2_D0APLL_K_SHIFT) /* 0x0000FFFF */ +/* D0APLL_CON3 */ +#define DDR0CRU_D0APLL_CON3_OFFSET (0xCU) +#define DDR0CRU_D0APLL_CON3_D0APLL_MFR_SHIFT (0U) +#define DDR0CRU_D0APLL_CON3_D0APLL_MFR_MASK (0xFFU << DDR0CRU_D0APLL_CON3_D0APLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR0CRU_D0APLL_CON3_D0APLL_MRR_SHIFT (8U) +#define DDR0CRU_D0APLL_CON3_D0APLL_MRR_MASK (0x3FU << DDR0CRU_D0APLL_CON3_D0APLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR0CRU_D0APLL_CON3_D0APLL_SEL_PF_SHIFT (14U) +#define DDR0CRU_D0APLL_CON3_D0APLL_SEL_PF_MASK (0x3U << DDR0CRU_D0APLL_CON3_D0APLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D0APLL_CON4 */ +#define DDR0CRU_D0APLL_CON4_OFFSET (0x10U) +#define DDR0CRU_D0APLL_CON4_D0APLL_SSCG_EN_SHIFT (0U) +#define DDR0CRU_D0APLL_CON4_D0APLL_SSCG_EN_MASK (0x1U << DDR0CRU_D0APLL_CON4_D0APLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR0CRU_D0APLL_CON4_D0APLL_AFC_ENB_SHIFT (3U) +#define DDR0CRU_D0APLL_CON4_D0APLL_AFC_ENB_MASK (0x1U << DDR0CRU_D0APLL_CON4_D0APLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR0CRU_D0APLL_CON4_D0APLL_EXTAFC_SHIFT (4U) +#define DDR0CRU_D0APLL_CON4_D0APLL_EXTAFC_MASK (0x1FU << DDR0CRU_D0APLL_CON4_D0APLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR0CRU_D0APLL_CON4_D0APLL_FEED_EN_SHIFT (14U) +#define DDR0CRU_D0APLL_CON4_D0APLL_FEED_EN_MASK (0x1U << DDR0CRU_D0APLL_CON4_D0APLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR0CRU_D0APLL_CON4_D0APLL_FSEL_SHIFT (15U) +#define DDR0CRU_D0APLL_CON4_D0APLL_FSEL_MASK (0x1U << DDR0CRU_D0APLL_CON4_D0APLL_FSEL_SHIFT) /* 0x00008000 */ +/* D0APLL_CON5 */ +#define DDR0CRU_D0APLL_CON5_OFFSET (0x14U) +#define DDR0CRU_D0APLL_CON5_D0APLL_FOUT_MASK_SHIFT (0U) +#define DDR0CRU_D0APLL_CON5_D0APLL_FOUT_MASK_MASK (0x1U << DDR0CRU_D0APLL_CON5_D0APLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D0APLL_CON6 */ +#define DDR0CRU_D0APLL_CON6_OFFSET (0x18U) +#define DDR0CRU_D0APLL_CON6_D0APLL_AFC_CODE_SHIFT (10U) +#define DDR0CRU_D0APLL_CON6_D0APLL_AFC_CODE_MASK (0x1FU << DDR0CRU_D0APLL_CON6_D0APLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR0CRU_D0APLL_CON6_D0APLL_LOCK_SHIFT (15U) +#define DDR0CRU_D0APLL_CON6_D0APLL_LOCK_MASK (0x1U << DDR0CRU_D0APLL_CON6_D0APLL_LOCK_SHIFT) /* 0x00008000 */ +/* D0BPLL_CON0 */ +#define DDR0CRU_D0BPLL_CON0_OFFSET (0x20U) +#define DDR0CRU_D0BPLL_CON0_D0BPLL_M_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON0_D0BPLL_M_MASK (0x3FFU << DDR0CRU_D0BPLL_CON0_D0BPLL_M_SHIFT) /* 0x000003FF */ +#define DDR0CRU_D0BPLL_CON0_D0BPLL_BP_SHIFT (15U) +#define DDR0CRU_D0BPLL_CON0_D0BPLL_BP_MASK (0x1U << DDR0CRU_D0BPLL_CON0_D0BPLL_BP_SHIFT) /* 0x00008000 */ +/* D0BPLL_CON1 */ +#define DDR0CRU_D0BPLL_CON1_OFFSET (0x24U) +#define DDR0CRU_D0BPLL_CON1_D0BPLL_P_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON1_D0BPLL_P_MASK (0x3FU << DDR0CRU_D0BPLL_CON1_D0BPLL_P_SHIFT) /* 0x0000003F */ +#define DDR0CRU_D0BPLL_CON1_D0BPLL_S_SHIFT (6U) +#define DDR0CRU_D0BPLL_CON1_D0BPLL_S_MASK (0x7U << DDR0CRU_D0BPLL_CON1_D0BPLL_S_SHIFT) /* 0x000001C0 */ +#define DDR0CRU_D0BPLL_CON1_D0BPLL_RESETB_SHIFT (13U) +#define DDR0CRU_D0BPLL_CON1_D0BPLL_RESETB_MASK (0x1U << DDR0CRU_D0BPLL_CON1_D0BPLL_RESETB_SHIFT) /* 0x00002000 */ +/* D0BPLL_CON2 */ +#define DDR0CRU_D0BPLL_CON2_OFFSET (0x28U) +#define DDR0CRU_D0BPLL_CON2_D0BPLL_K_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON2_D0BPLL_K_MASK (0xFFFFU << DDR0CRU_D0BPLL_CON2_D0BPLL_K_SHIFT) /* 0x0000FFFF */ +/* D0BPLL_CON3 */ +#define DDR0CRU_D0BPLL_CON3_OFFSET (0x2CU) +#define DDR0CRU_D0BPLL_CON3_D0BPLL_MFR_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON3_D0BPLL_MFR_MASK (0xFFU << DDR0CRU_D0BPLL_CON3_D0BPLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR0CRU_D0BPLL_CON3_D0BPLL_MRR_SHIFT (8U) +#define DDR0CRU_D0BPLL_CON3_D0BPLL_MRR_MASK (0x3FU << DDR0CRU_D0BPLL_CON3_D0BPLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR0CRU_D0BPLL_CON3_D0BPLL_SEL_PF_SHIFT (14U) +#define DDR0CRU_D0BPLL_CON3_D0BPLL_SEL_PF_MASK (0x3U << DDR0CRU_D0BPLL_CON3_D0BPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D0BPLL_CON4 */ +#define DDR0CRU_D0BPLL_CON4_OFFSET (0x30U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_SSCG_EN_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_SSCG_EN_MASK (0x1U << DDR0CRU_D0BPLL_CON4_D0BPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR0CRU_D0BPLL_CON4_D0BPLL_AFC_ENB_SHIFT (3U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_AFC_ENB_MASK (0x1U << DDR0CRU_D0BPLL_CON4_D0BPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR0CRU_D0BPLL_CON4_D0BPLL_EXTAFC_SHIFT (4U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_EXTAFC_MASK (0x1FU << DDR0CRU_D0BPLL_CON4_D0BPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR0CRU_D0BPLL_CON4_D0BPLL_FEED_EN_SHIFT (14U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_FEED_EN_MASK (0x1U << DDR0CRU_D0BPLL_CON4_D0BPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR0CRU_D0BPLL_CON4_D0BPLL_FSEL_SHIFT (15U) +#define DDR0CRU_D0BPLL_CON4_D0BPLL_FSEL_MASK (0x1U << DDR0CRU_D0BPLL_CON4_D0BPLL_FSEL_SHIFT) /* 0x00008000 */ +/* D0BPLL_CON5 */ +#define DDR0CRU_D0BPLL_CON5_OFFSET (0x34U) +#define DDR0CRU_D0BPLL_CON5_D0BPLL_FOUT_MASK_SHIFT (0U) +#define DDR0CRU_D0BPLL_CON5_D0BPLL_FOUT_MASK_MASK (0x1U << DDR0CRU_D0BPLL_CON5_D0BPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D0BPLL_CON6 */ +#define DDR0CRU_D0BPLL_CON6_OFFSET (0x38U) +#define DDR0CRU_D0BPLL_CON6_D0BPLL_AFC_CODE_SHIFT (10U) +#define DDR0CRU_D0BPLL_CON6_D0BPLL_AFC_CODE_MASK (0x1FU << DDR0CRU_D0BPLL_CON6_D0BPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR0CRU_D0BPLL_CON6_D0BPLL_LOCK_SHIFT (15U) +#define DDR0CRU_D0BPLL_CON6_D0BPLL_LOCK_MASK (0x1U << DDR0CRU_D0BPLL_CON6_D0BPLL_LOCK_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON00 */ +#define DDR0CRU_CLKSEL_CON00_OFFSET (0x300U) +#define DDR0CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH0_SEL_SHIFT (0U) +#define DDR0CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH0_SEL_MASK (0x1U << DDR0CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH0_SEL_SHIFT) /* 0x00000001 */ +/* GATE_CON00 */ +#define DDR0CRU_GATE_CON00_OFFSET (0x800U) +#define DDR0CRU_GATE_CON00_PCLK_DDR_CRU_CH0_EN_SHIFT (3U) +#define DDR0CRU_GATE_CON00_PCLK_DDR_CRU_CH0_EN_MASK (0x1U << DDR0CRU_GATE_CON00_PCLK_DDR_CRU_CH0_EN_SHIFT) /* 0x00000008 */ +#define DDR0CRU_GATE_CON00_PCLK_DDRPHY_CH0_EN_SHIFT (4U) +#define DDR0CRU_GATE_CON00_PCLK_DDRPHY_CH0_EN_MASK (0x1U << DDR0CRU_GATE_CON00_PCLK_DDRPHY_CH0_EN_SHIFT) /* 0x00000010 */ +#define DDR0CRU_GATE_CON00_CLK_OSC_DDRPHY_CH0_EN_SHIFT (5U) +#define DDR0CRU_GATE_CON00_CLK_OSC_DDRPHY_CH0_EN_MASK (0x1U << DDR0CRU_GATE_CON00_CLK_OSC_DDRPHY_CH0_EN_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON00 */ +#define DDR0CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH0_SHIFT (1U) +#define DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH0_MASK (0x1U << DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH0_SHIFT) /* 0x00000002 */ +#define DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH0_SHIFT (2U) +#define DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH0_MASK (0x1U << DDR0CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH0_SHIFT) /* 0x00000004 */ +#define DDR0CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH0_SHIFT (3U) +#define DDR0CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH0_MASK (0x1U << DDR0CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH0_SHIFT) /* 0x00000008 */ +#define DDR0CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH0_SHIFT (4U) +#define DDR0CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH0_MASK (0x1U << DDR0CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH0_SHIFT) /* 0x00000010 */ +/****************************************DDR1CRU*****************************************/ +/* D1APLL_CON0 */ +#define DDR1CRU_D1APLL_CON0_OFFSET (0x0U) +#define DDR1CRU_D1APLL_CON0_D1APLL_M_SHIFT (0U) +#define DDR1CRU_D1APLL_CON0_D1APLL_M_MASK (0x3FFU << DDR1CRU_D1APLL_CON0_D1APLL_M_SHIFT) /* 0x000003FF */ +#define DDR1CRU_D1APLL_CON0_D1APLL_BP_SHIFT (15U) +#define DDR1CRU_D1APLL_CON0_D1APLL_BP_MASK (0x1U << DDR1CRU_D1APLL_CON0_D1APLL_BP_SHIFT) /* 0x00008000 */ +/* D1APLL_CON1 */ +#define DDR1CRU_D1APLL_CON1_OFFSET (0x4U) +#define DDR1CRU_D1APLL_CON1_D1APLL_P_SHIFT (0U) +#define DDR1CRU_D1APLL_CON1_D1APLL_P_MASK (0x3FU << DDR1CRU_D1APLL_CON1_D1APLL_P_SHIFT) /* 0x0000003F */ +#define DDR1CRU_D1APLL_CON1_D1APLL_S_SHIFT (6U) +#define DDR1CRU_D1APLL_CON1_D1APLL_S_MASK (0x7U << DDR1CRU_D1APLL_CON1_D1APLL_S_SHIFT) /* 0x000001C0 */ +#define DDR1CRU_D1APLL_CON1_D1APLL_RESETB_SHIFT (13U) +#define DDR1CRU_D1APLL_CON1_D1APLL_RESETB_MASK (0x1U << DDR1CRU_D1APLL_CON1_D1APLL_RESETB_SHIFT) /* 0x00002000 */ +/* D1APLL_CON2 */ +#define DDR1CRU_D1APLL_CON2_OFFSET (0x8U) +#define DDR1CRU_D1APLL_CON2_D1APLL_K_SHIFT (0U) +#define DDR1CRU_D1APLL_CON2_D1APLL_K_MASK (0xFFFFU << DDR1CRU_D1APLL_CON2_D1APLL_K_SHIFT) /* 0x0000FFFF */ +/* D1APLL_CON3 */ +#define DDR1CRU_D1APLL_CON3_OFFSET (0xCU) +#define DDR1CRU_D1APLL_CON3_D1APLL_MFR_SHIFT (0U) +#define DDR1CRU_D1APLL_CON3_D1APLL_MFR_MASK (0xFFU << DDR1CRU_D1APLL_CON3_D1APLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR1CRU_D1APLL_CON3_D1APLL_MRR_SHIFT (8U) +#define DDR1CRU_D1APLL_CON3_D1APLL_MRR_MASK (0x3FU << DDR1CRU_D1APLL_CON3_D1APLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR1CRU_D1APLL_CON3_D1APLL_SEL_PF_SHIFT (14U) +#define DDR1CRU_D1APLL_CON3_D1APLL_SEL_PF_MASK (0x3U << DDR1CRU_D1APLL_CON3_D1APLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D1APLL_CON4 */ +#define DDR1CRU_D1APLL_CON4_OFFSET (0x10U) +#define DDR1CRU_D1APLL_CON4_D1APLL_SSCG_EN_SHIFT (0U) +#define DDR1CRU_D1APLL_CON4_D1APLL_SSCG_EN_MASK (0x1U << DDR1CRU_D1APLL_CON4_D1APLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR1CRU_D1APLL_CON4_D1APLL_AFC_ENB_SHIFT (3U) +#define DDR1CRU_D1APLL_CON4_D1APLL_AFC_ENB_MASK (0x1U << DDR1CRU_D1APLL_CON4_D1APLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR1CRU_D1APLL_CON4_D1APLL_EXTAFC_SHIFT (4U) +#define DDR1CRU_D1APLL_CON4_D1APLL_EXTAFC_MASK (0x1FU << DDR1CRU_D1APLL_CON4_D1APLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR1CRU_D1APLL_CON4_D1APLL_FEED_EN_SHIFT (14U) +#define DDR1CRU_D1APLL_CON4_D1APLL_FEED_EN_MASK (0x1U << DDR1CRU_D1APLL_CON4_D1APLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR1CRU_D1APLL_CON4_D1APLL_FSEL_SHIFT (15U) +#define DDR1CRU_D1APLL_CON4_D1APLL_FSEL_MASK (0x1U << DDR1CRU_D1APLL_CON4_D1APLL_FSEL_SHIFT) /* 0x00008000 */ +/* D1APLL_CON5 */ +#define DDR1CRU_D1APLL_CON5_OFFSET (0x14U) +#define DDR1CRU_D1APLL_CON5_D1APLL_FOUT_MASK_SHIFT (0U) +#define DDR1CRU_D1APLL_CON5_D1APLL_FOUT_MASK_MASK (0x1U << DDR1CRU_D1APLL_CON5_D1APLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D1APLL_CON6 */ +#define DDR1CRU_D1APLL_CON6_OFFSET (0x18U) +#define DDR1CRU_D1APLL_CON6_D1APLL_AFC_CODE_SHIFT (10U) +#define DDR1CRU_D1APLL_CON6_D1APLL_AFC_CODE_MASK (0x1FU << DDR1CRU_D1APLL_CON6_D1APLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR1CRU_D1APLL_CON6_D1APLL_LOCK_SHIFT (15U) +#define DDR1CRU_D1APLL_CON6_D1APLL_LOCK_MASK (0x1U << DDR1CRU_D1APLL_CON6_D1APLL_LOCK_SHIFT) /* 0x00008000 */ +/* D1BPLL_CON0 */ +#define DDR1CRU_D1BPLL_CON0_OFFSET (0x20U) +#define DDR1CRU_D1BPLL_CON0_D1BPLL_M_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON0_D1BPLL_M_MASK (0x3FFU << DDR1CRU_D1BPLL_CON0_D1BPLL_M_SHIFT) /* 0x000003FF */ +#define DDR1CRU_D1BPLL_CON0_D1BPLL_BP_SHIFT (15U) +#define DDR1CRU_D1BPLL_CON0_D1BPLL_BP_MASK (0x1U << DDR1CRU_D1BPLL_CON0_D1BPLL_BP_SHIFT) /* 0x00008000 */ +/* D1BPLL_CON1 */ +#define DDR1CRU_D1BPLL_CON1_OFFSET (0x24U) +#define DDR1CRU_D1BPLL_CON1_D1BPLL_P_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON1_D1BPLL_P_MASK (0x3FU << DDR1CRU_D1BPLL_CON1_D1BPLL_P_SHIFT) /* 0x0000003F */ +#define DDR1CRU_D1BPLL_CON1_D1BPLL_S_SHIFT (6U) +#define DDR1CRU_D1BPLL_CON1_D1BPLL_S_MASK (0x7U << DDR1CRU_D1BPLL_CON1_D1BPLL_S_SHIFT) /* 0x000001C0 */ +#define DDR1CRU_D1BPLL_CON1_D1BPLL_RESETB_SHIFT (13U) +#define DDR1CRU_D1BPLL_CON1_D1BPLL_RESETB_MASK (0x1U << DDR1CRU_D1BPLL_CON1_D1BPLL_RESETB_SHIFT) /* 0x00002000 */ +/* D1BPLL_CON2 */ +#define DDR1CRU_D1BPLL_CON2_OFFSET (0x28U) +#define DDR1CRU_D1BPLL_CON2_D1BPLL_K_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON2_D1BPLL_K_MASK (0xFFFFU << DDR1CRU_D1BPLL_CON2_D1BPLL_K_SHIFT) /* 0x0000FFFF */ +/* D1BPLL_CON3 */ +#define DDR1CRU_D1BPLL_CON3_OFFSET (0x2CU) +#define DDR1CRU_D1BPLL_CON3_D1BPLL_MFR_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON3_D1BPLL_MFR_MASK (0xFFU << DDR1CRU_D1BPLL_CON3_D1BPLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR1CRU_D1BPLL_CON3_D1BPLL_MRR_SHIFT (8U) +#define DDR1CRU_D1BPLL_CON3_D1BPLL_MRR_MASK (0x3FU << DDR1CRU_D1BPLL_CON3_D1BPLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR1CRU_D1BPLL_CON3_D1BPLL_SEL_PF_SHIFT (14U) +#define DDR1CRU_D1BPLL_CON3_D1BPLL_SEL_PF_MASK (0x3U << DDR1CRU_D1BPLL_CON3_D1BPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D1BPLL_CON4 */ +#define DDR1CRU_D1BPLL_CON4_OFFSET (0x30U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_SSCG_EN_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_SSCG_EN_MASK (0x1U << DDR1CRU_D1BPLL_CON4_D1BPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR1CRU_D1BPLL_CON4_D1BPLL_AFC_ENB_SHIFT (3U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_AFC_ENB_MASK (0x1U << DDR1CRU_D1BPLL_CON4_D1BPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR1CRU_D1BPLL_CON4_D1BPLL_EXTAFC_SHIFT (4U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_EXTAFC_MASK (0x1FU << DDR1CRU_D1BPLL_CON4_D1BPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR1CRU_D1BPLL_CON4_D1BPLL_FEED_EN_SHIFT (14U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_FEED_EN_MASK (0x1U << DDR1CRU_D1BPLL_CON4_D1BPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR1CRU_D1BPLL_CON4_D1BPLL_FSEL_SHIFT (15U) +#define DDR1CRU_D1BPLL_CON4_D1BPLL_FSEL_MASK (0x1U << DDR1CRU_D1BPLL_CON4_D1BPLL_FSEL_SHIFT) /* 0x00008000 */ +/* D1BPLL_CON5 */ +#define DDR1CRU_D1BPLL_CON5_OFFSET (0x34U) +#define DDR1CRU_D1BPLL_CON5_D1BPLL_FOUT_MASK_SHIFT (0U) +#define DDR1CRU_D1BPLL_CON5_D1BPLL_FOUT_MASK_MASK (0x1U << DDR1CRU_D1BPLL_CON5_D1BPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D1BPLL_CON6 */ +#define DDR1CRU_D1BPLL_CON6_OFFSET (0x38U) +#define DDR1CRU_D1BPLL_CON6_D1BPLL_AFC_CODE_SHIFT (10U) +#define DDR1CRU_D1BPLL_CON6_D1BPLL_AFC_CODE_MASK (0x1FU << DDR1CRU_D1BPLL_CON6_D1BPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR1CRU_D1BPLL_CON6_D1BPLL_LOCK_SHIFT (15U) +#define DDR1CRU_D1BPLL_CON6_D1BPLL_LOCK_MASK (0x1U << DDR1CRU_D1BPLL_CON6_D1BPLL_LOCK_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON00 */ +#define DDR1CRU_CLKSEL_CON00_OFFSET (0x300U) +#define DDR1CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH1_SEL_SHIFT (0U) +#define DDR1CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH1_SEL_MASK (0x1U << DDR1CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH1_SEL_SHIFT) /* 0x00000001 */ +/* GATE_CON00 */ +#define DDR1CRU_GATE_CON00_OFFSET (0x800U) +#define DDR1CRU_GATE_CON00_PCLK_DDR_CRU_CH1_EN_SHIFT (3U) +#define DDR1CRU_GATE_CON00_PCLK_DDR_CRU_CH1_EN_MASK (0x1U << DDR1CRU_GATE_CON00_PCLK_DDR_CRU_CH1_EN_SHIFT) /* 0x00000008 */ +#define DDR1CRU_GATE_CON00_PCLK_DDRPHY_CH1_EN_SHIFT (4U) +#define DDR1CRU_GATE_CON00_PCLK_DDRPHY_CH1_EN_MASK (0x1U << DDR1CRU_GATE_CON00_PCLK_DDRPHY_CH1_EN_SHIFT) /* 0x00000010 */ +#define DDR1CRU_GATE_CON00_CLK_OSC_DDRPHY_CH1_EN_SHIFT (5U) +#define DDR1CRU_GATE_CON00_CLK_OSC_DDRPHY_CH1_EN_MASK (0x1U << DDR1CRU_GATE_CON00_CLK_OSC_DDRPHY_CH1_EN_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON00 */ +#define DDR1CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH1_SHIFT (1U) +#define DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH1_MASK (0x1U << DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH1_SHIFT) /* 0x00000002 */ +#define DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH1_SHIFT (2U) +#define DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH1_MASK (0x1U << DDR1CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH1_SHIFT) /* 0x00000004 */ +#define DDR1CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH1_SHIFT (3U) +#define DDR1CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH1_MASK (0x1U << DDR1CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH1_SHIFT) /* 0x00000008 */ +#define DDR1CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH1_SHIFT (4U) +#define DDR1CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH1_MASK (0x1U << DDR1CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH1_SHIFT) /* 0x00000010 */ +/****************************************DDR2CRU*****************************************/ +/* D2APLL_CON0 */ +#define DDR2CRU_D2APLL_CON0_OFFSET (0x0U) +#define DDR2CRU_D2APLL_CON0_D2APLL_M_SHIFT (0U) +#define DDR2CRU_D2APLL_CON0_D2APLL_M_MASK (0x3FFU << DDR2CRU_D2APLL_CON0_D2APLL_M_SHIFT) /* 0x000003FF */ +#define DDR2CRU_D2APLL_CON0_D2APLL_BP_SHIFT (15U) +#define DDR2CRU_D2APLL_CON0_D2APLL_BP_MASK (0x1U << DDR2CRU_D2APLL_CON0_D2APLL_BP_SHIFT) /* 0x00008000 */ +/* D2APLL_CON1 */ +#define DDR2CRU_D2APLL_CON1_OFFSET (0x4U) +#define DDR2CRU_D2APLL_CON1_D2APLL_P_SHIFT (0U) +#define DDR2CRU_D2APLL_CON1_D2APLL_P_MASK (0x3FU << DDR2CRU_D2APLL_CON1_D2APLL_P_SHIFT) /* 0x0000003F */ +#define DDR2CRU_D2APLL_CON1_D2APLL_S_SHIFT (6U) +#define DDR2CRU_D2APLL_CON1_D2APLL_S_MASK (0x7U << DDR2CRU_D2APLL_CON1_D2APLL_S_SHIFT) /* 0x000001C0 */ +#define DDR2CRU_D2APLL_CON1_D2APLL_RESETB_SHIFT (13U) +#define DDR2CRU_D2APLL_CON1_D2APLL_RESETB_MASK (0x1U << DDR2CRU_D2APLL_CON1_D2APLL_RESETB_SHIFT) /* 0x00002000 */ +/* D2APLL_CON2 */ +#define DDR2CRU_D2APLL_CON2_OFFSET (0x8U) +#define DDR2CRU_D2APLL_CON2_D2APLL_K_SHIFT (0U) +#define DDR2CRU_D2APLL_CON2_D2APLL_K_MASK (0xFFFFU << DDR2CRU_D2APLL_CON2_D2APLL_K_SHIFT) /* 0x0000FFFF */ +/* D2APLL_CON3 */ +#define DDR2CRU_D2APLL_CON3_OFFSET (0xCU) +#define DDR2CRU_D2APLL_CON3_D2APLL_MFR_SHIFT (0U) +#define DDR2CRU_D2APLL_CON3_D2APLL_MFR_MASK (0xFFU << DDR2CRU_D2APLL_CON3_D2APLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR2CRU_D2APLL_CON3_D2APLL_MRR_SHIFT (8U) +#define DDR2CRU_D2APLL_CON3_D2APLL_MRR_MASK (0x3FU << DDR2CRU_D2APLL_CON3_D2APLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR2CRU_D2APLL_CON3_D2APLL_SEL_PF_SHIFT (14U) +#define DDR2CRU_D2APLL_CON3_D2APLL_SEL_PF_MASK (0x3U << DDR2CRU_D2APLL_CON3_D2APLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D2APLL_CON4 */ +#define DDR2CRU_D2APLL_CON4_OFFSET (0x10U) +#define DDR2CRU_D2APLL_CON4_D2APLL_SSCG_EN_SHIFT (0U) +#define DDR2CRU_D2APLL_CON4_D2APLL_SSCG_EN_MASK (0x1U << DDR2CRU_D2APLL_CON4_D2APLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR2CRU_D2APLL_CON4_D2APLL_AFC_ENB_SHIFT (3U) +#define DDR2CRU_D2APLL_CON4_D2APLL_AFC_ENB_MASK (0x1U << DDR2CRU_D2APLL_CON4_D2APLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR2CRU_D2APLL_CON4_D2APLL_EXTAFC_SHIFT (4U) +#define DDR2CRU_D2APLL_CON4_D2APLL_EXTAFC_MASK (0x1FU << DDR2CRU_D2APLL_CON4_D2APLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR2CRU_D2APLL_CON4_D2APLL_FEED_EN_SHIFT (14U) +#define DDR2CRU_D2APLL_CON4_D2APLL_FEED_EN_MASK (0x1U << DDR2CRU_D2APLL_CON4_D2APLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR2CRU_D2APLL_CON4_D2APLL_FSEL_SHIFT (15U) +#define DDR2CRU_D2APLL_CON4_D2APLL_FSEL_MASK (0x1U << DDR2CRU_D2APLL_CON4_D2APLL_FSEL_SHIFT) /* 0x00008000 */ +/* D2APLL_CON5 */ +#define DDR2CRU_D2APLL_CON5_OFFSET (0x14U) +#define DDR2CRU_D2APLL_CON5_D2APLL_FOUT_MASK_SHIFT (0U) +#define DDR2CRU_D2APLL_CON5_D2APLL_FOUT_MASK_MASK (0x1U << DDR2CRU_D2APLL_CON5_D2APLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D2APLL_CON6 */ +#define DDR2CRU_D2APLL_CON6_OFFSET (0x18U) +#define DDR2CRU_D2APLL_CON6_D2APLL_AFC_CODE_SHIFT (10U) +#define DDR2CRU_D2APLL_CON6_D2APLL_AFC_CODE_MASK (0x1FU << DDR2CRU_D2APLL_CON6_D2APLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR2CRU_D2APLL_CON6_D2APLL_LOCK_SHIFT (15U) +#define DDR2CRU_D2APLL_CON6_D2APLL_LOCK_MASK (0x1U << DDR2CRU_D2APLL_CON6_D2APLL_LOCK_SHIFT) /* 0x00008000 */ +/* D2BPLL_CON0 */ +#define DDR2CRU_D2BPLL_CON0_OFFSET (0x20U) +#define DDR2CRU_D2BPLL_CON0_D2BPLL_M_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON0_D2BPLL_M_MASK (0x3FFU << DDR2CRU_D2BPLL_CON0_D2BPLL_M_SHIFT) /* 0x000003FF */ +#define DDR2CRU_D2BPLL_CON0_D2BPLL_BP_SHIFT (15U) +#define DDR2CRU_D2BPLL_CON0_D2BPLL_BP_MASK (0x1U << DDR2CRU_D2BPLL_CON0_D2BPLL_BP_SHIFT) /* 0x00008000 */ +/* D2BPLL_CON1 */ +#define DDR2CRU_D2BPLL_CON1_OFFSET (0x24U) +#define DDR2CRU_D2BPLL_CON1_D2BPLL_P_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON1_D2BPLL_P_MASK (0x3FU << DDR2CRU_D2BPLL_CON1_D2BPLL_P_SHIFT) /* 0x0000003F */ +#define DDR2CRU_D2BPLL_CON1_D2BPLL_S_SHIFT (6U) +#define DDR2CRU_D2BPLL_CON1_D2BPLL_S_MASK (0x7U << DDR2CRU_D2BPLL_CON1_D2BPLL_S_SHIFT) /* 0x000001C0 */ +#define DDR2CRU_D2BPLL_CON1_D2BPLL_RESETB_SHIFT (13U) +#define DDR2CRU_D2BPLL_CON1_D2BPLL_RESETB_MASK (0x1U << DDR2CRU_D2BPLL_CON1_D2BPLL_RESETB_SHIFT) /* 0x00002000 */ +/* D2BPLL_CON2 */ +#define DDR2CRU_D2BPLL_CON2_OFFSET (0x28U) +#define DDR2CRU_D2BPLL_CON2_D2BPLL_K_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON2_D2BPLL_K_MASK (0xFFFFU << DDR2CRU_D2BPLL_CON2_D2BPLL_K_SHIFT) /* 0x0000FFFF */ +/* D2BPLL_CON3 */ +#define DDR2CRU_D2BPLL_CON3_OFFSET (0x2CU) +#define DDR2CRU_D2BPLL_CON3_D2BPLL_MFR_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON3_D2BPLL_MFR_MASK (0xFFU << DDR2CRU_D2BPLL_CON3_D2BPLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR2CRU_D2BPLL_CON3_D2BPLL_MRR_SHIFT (8U) +#define DDR2CRU_D2BPLL_CON3_D2BPLL_MRR_MASK (0x3FU << DDR2CRU_D2BPLL_CON3_D2BPLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR2CRU_D2BPLL_CON3_D2BPLL_SEL_PF_SHIFT (14U) +#define DDR2CRU_D2BPLL_CON3_D2BPLL_SEL_PF_MASK (0x3U << DDR2CRU_D2BPLL_CON3_D2BPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D2BPLL_CON4 */ +#define DDR2CRU_D2BPLL_CON4_OFFSET (0x30U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_SSCG_EN_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_SSCG_EN_MASK (0x1U << DDR2CRU_D2BPLL_CON4_D2BPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR2CRU_D2BPLL_CON4_D2BPLL_AFC_ENB_SHIFT (3U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_AFC_ENB_MASK (0x1U << DDR2CRU_D2BPLL_CON4_D2BPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR2CRU_D2BPLL_CON4_D2BPLL_EXTAFC_SHIFT (4U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_EXTAFC_MASK (0x1FU << DDR2CRU_D2BPLL_CON4_D2BPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR2CRU_D2BPLL_CON4_D2BPLL_FEED_EN_SHIFT (14U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_FEED_EN_MASK (0x1U << DDR2CRU_D2BPLL_CON4_D2BPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR2CRU_D2BPLL_CON4_D2BPLL_FSEL_SHIFT (15U) +#define DDR2CRU_D2BPLL_CON4_D2BPLL_FSEL_MASK (0x1U << DDR2CRU_D2BPLL_CON4_D2BPLL_FSEL_SHIFT) /* 0x00008000 */ +/* D2BPLL_CON5 */ +#define DDR2CRU_D2BPLL_CON5_OFFSET (0x34U) +#define DDR2CRU_D2BPLL_CON5_D2BPLL_FOUT_MASK_SHIFT (0U) +#define DDR2CRU_D2BPLL_CON5_D2BPLL_FOUT_MASK_MASK (0x1U << DDR2CRU_D2BPLL_CON5_D2BPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D2BPLL_CON6 */ +#define DDR2CRU_D2BPLL_CON6_OFFSET (0x38U) +#define DDR2CRU_D2BPLL_CON6_D2BPLL_AFC_CODE_SHIFT (10U) +#define DDR2CRU_D2BPLL_CON6_D2BPLL_AFC_CODE_MASK (0x1FU << DDR2CRU_D2BPLL_CON6_D2BPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR2CRU_D2BPLL_CON6_D2BPLL_LOCK_SHIFT (15U) +#define DDR2CRU_D2BPLL_CON6_D2BPLL_LOCK_MASK (0x1U << DDR2CRU_D2BPLL_CON6_D2BPLL_LOCK_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON00 */ +#define DDR2CRU_CLKSEL_CON00_OFFSET (0x300U) +#define DDR2CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH2_SEL_SHIFT (0U) +#define DDR2CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH2_SEL_MASK (0x1U << DDR2CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH2_SEL_SHIFT) /* 0x00000001 */ +/* GATE_CON00 */ +#define DDR2CRU_GATE_CON00_OFFSET (0x800U) +#define DDR2CRU_GATE_CON00_PCLK_DDR_CRU_CH2_EN_SHIFT (3U) +#define DDR2CRU_GATE_CON00_PCLK_DDR_CRU_CH2_EN_MASK (0x1U << DDR2CRU_GATE_CON00_PCLK_DDR_CRU_CH2_EN_SHIFT) /* 0x00000008 */ +#define DDR2CRU_GATE_CON00_PCLK_DDRPHY_CH2_EN_SHIFT (4U) +#define DDR2CRU_GATE_CON00_PCLK_DDRPHY_CH2_EN_MASK (0x1U << DDR2CRU_GATE_CON00_PCLK_DDRPHY_CH2_EN_SHIFT) /* 0x00000010 */ +#define DDR2CRU_GATE_CON00_CLK_OSC_DDRPHY_CH2_EN_SHIFT (5U) +#define DDR2CRU_GATE_CON00_CLK_OSC_DDRPHY_CH2_EN_MASK (0x1U << DDR2CRU_GATE_CON00_CLK_OSC_DDRPHY_CH2_EN_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON00 */ +#define DDR2CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH2_SHIFT (1U) +#define DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH2_MASK (0x1U << DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH2_SHIFT) /* 0x00000002 */ +#define DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH2_SHIFT (2U) +#define DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH2_MASK (0x1U << DDR2CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH2_SHIFT) /* 0x00000004 */ +#define DDR2CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH2_SHIFT (3U) +#define DDR2CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH2_MASK (0x1U << DDR2CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH2_SHIFT) /* 0x00000008 */ +#define DDR2CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH2_SHIFT (4U) +#define DDR2CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH2_MASK (0x1U << DDR2CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH2_SHIFT) /* 0x00000010 */ +/****************************************DDR3CRU*****************************************/ +/* D3APLL_CON0 */ +#define DDR3CRU_D3APLL_CON0_OFFSET (0x0U) +#define DDR3CRU_D3APLL_CON0_D3APLL_M_SHIFT (0U) +#define DDR3CRU_D3APLL_CON0_D3APLL_M_MASK (0x3FFU << DDR3CRU_D3APLL_CON0_D3APLL_M_SHIFT) /* 0x000003FF */ +#define DDR3CRU_D3APLL_CON0_D3APLL_BP_SHIFT (15U) +#define DDR3CRU_D3APLL_CON0_D3APLL_BP_MASK (0x1U << DDR3CRU_D3APLL_CON0_D3APLL_BP_SHIFT) /* 0x00008000 */ +/* D3APLL_CON1 */ +#define DDR3CRU_D3APLL_CON1_OFFSET (0x4U) +#define DDR3CRU_D3APLL_CON1_D3APLL_P_SHIFT (0U) +#define DDR3CRU_D3APLL_CON1_D3APLL_P_MASK (0x3FU << DDR3CRU_D3APLL_CON1_D3APLL_P_SHIFT) /* 0x0000003F */ +#define DDR3CRU_D3APLL_CON1_D3APLL_S_SHIFT (6U) +#define DDR3CRU_D3APLL_CON1_D3APLL_S_MASK (0x7U << DDR3CRU_D3APLL_CON1_D3APLL_S_SHIFT) /* 0x000001C0 */ +#define DDR3CRU_D3APLL_CON1_D3APLL_RESETB_SHIFT (13U) +#define DDR3CRU_D3APLL_CON1_D3APLL_RESETB_MASK (0x1U << DDR3CRU_D3APLL_CON1_D3APLL_RESETB_SHIFT) /* 0x00002000 */ +/* D3APLL_CON2 */ +#define DDR3CRU_D3APLL_CON2_OFFSET (0x8U) +#define DDR3CRU_D3APLL_CON2_D3APLL_K_SHIFT (0U) +#define DDR3CRU_D3APLL_CON2_D3APLL_K_MASK (0xFFFFU << DDR3CRU_D3APLL_CON2_D3APLL_K_SHIFT) /* 0x0000FFFF */ +/* D3APLL_CON3 */ +#define DDR3CRU_D3APLL_CON3_OFFSET (0xCU) +#define DDR3CRU_D3APLL_CON3_D3APLL_MFR_SHIFT (0U) +#define DDR3CRU_D3APLL_CON3_D3APLL_MFR_MASK (0xFFU << DDR3CRU_D3APLL_CON3_D3APLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR3CRU_D3APLL_CON3_D3APLL_MRR_SHIFT (8U) +#define DDR3CRU_D3APLL_CON3_D3APLL_MRR_MASK (0x3FU << DDR3CRU_D3APLL_CON3_D3APLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR3CRU_D3APLL_CON3_D3APLL_SEL_PF_SHIFT (14U) +#define DDR3CRU_D3APLL_CON3_D3APLL_SEL_PF_MASK (0x3U << DDR3CRU_D3APLL_CON3_D3APLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D3APLL_CON4 */ +#define DDR3CRU_D3APLL_CON4_OFFSET (0x10U) +#define DDR3CRU_D3APLL_CON4_D3APLL_SSCG_EN_SHIFT (0U) +#define DDR3CRU_D3APLL_CON4_D3APLL_SSCG_EN_MASK (0x1U << DDR3CRU_D3APLL_CON4_D3APLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR3CRU_D3APLL_CON4_D3APLL_AFC_ENB_SHIFT (3U) +#define DDR3CRU_D3APLL_CON4_D3APLL_AFC_ENB_MASK (0x1U << DDR3CRU_D3APLL_CON4_D3APLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR3CRU_D3APLL_CON4_D3APLL_EXTAFC_SHIFT (4U) +#define DDR3CRU_D3APLL_CON4_D3APLL_EXTAFC_MASK (0x1FU << DDR3CRU_D3APLL_CON4_D3APLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR3CRU_D3APLL_CON4_D3APLL_FEED_EN_SHIFT (14U) +#define DDR3CRU_D3APLL_CON4_D3APLL_FEED_EN_MASK (0x1U << DDR3CRU_D3APLL_CON4_D3APLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR3CRU_D3APLL_CON4_D3APLL_FSEL_SHIFT (15U) +#define DDR3CRU_D3APLL_CON4_D3APLL_FSEL_MASK (0x1U << DDR3CRU_D3APLL_CON4_D3APLL_FSEL_SHIFT) /* 0x00008000 */ +/* D3APLL_CON5 */ +#define DDR3CRU_D3APLL_CON5_OFFSET (0x14U) +#define DDR3CRU_D3APLL_CON5_D3APLL_FOUT_MASK_SHIFT (0U) +#define DDR3CRU_D3APLL_CON5_D3APLL_FOUT_MASK_MASK (0x1U << DDR3CRU_D3APLL_CON5_D3APLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D3APLL_CON6 */ +#define DDR3CRU_D3APLL_CON6_OFFSET (0x18U) +#define DDR3CRU_D3APLL_CON6_D3APLL_AFC_CODE_SHIFT (10U) +#define DDR3CRU_D3APLL_CON6_D3APLL_AFC_CODE_MASK (0x1FU << DDR3CRU_D3APLL_CON6_D3APLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR3CRU_D3APLL_CON6_D3APLL_LOCK_SHIFT (15U) +#define DDR3CRU_D3APLL_CON6_D3APLL_LOCK_MASK (0x1U << DDR3CRU_D3APLL_CON6_D3APLL_LOCK_SHIFT) /* 0x00008000 */ +/* D3BPLL_CON0 */ +#define DDR3CRU_D3BPLL_CON0_OFFSET (0x20U) +#define DDR3CRU_D3BPLL_CON0_D3BPLL_M_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON0_D3BPLL_M_MASK (0x3FFU << DDR3CRU_D3BPLL_CON0_D3BPLL_M_SHIFT) /* 0x000003FF */ +#define DDR3CRU_D3BPLL_CON0_D3BPLL_BP_SHIFT (15U) +#define DDR3CRU_D3BPLL_CON0_D3BPLL_BP_MASK (0x1U << DDR3CRU_D3BPLL_CON0_D3BPLL_BP_SHIFT) /* 0x00008000 */ +/* D3BPLL_CON1 */ +#define DDR3CRU_D3BPLL_CON1_OFFSET (0x24U) +#define DDR3CRU_D3BPLL_CON1_D3BPLL_P_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON1_D3BPLL_P_MASK (0x3FU << DDR3CRU_D3BPLL_CON1_D3BPLL_P_SHIFT) /* 0x0000003F */ +#define DDR3CRU_D3BPLL_CON1_D3BPLL_S_SHIFT (6U) +#define DDR3CRU_D3BPLL_CON1_D3BPLL_S_MASK (0x7U << DDR3CRU_D3BPLL_CON1_D3BPLL_S_SHIFT) /* 0x000001C0 */ +#define DDR3CRU_D3BPLL_CON1_D3BPLL_RESETB_SHIFT (13U) +#define DDR3CRU_D3BPLL_CON1_D3BPLL_RESETB_MASK (0x1U << DDR3CRU_D3BPLL_CON1_D3BPLL_RESETB_SHIFT) /* 0x00002000 */ +/* D3BPLL_CON2 */ +#define DDR3CRU_D3BPLL_CON2_OFFSET (0x28U) +#define DDR3CRU_D3BPLL_CON2_D3BPLL_K_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON2_D3BPLL_K_MASK (0xFFFFU << DDR3CRU_D3BPLL_CON2_D3BPLL_K_SHIFT) /* 0x0000FFFF */ +/* D3BPLL_CON3 */ +#define DDR3CRU_D3BPLL_CON3_OFFSET (0x2CU) +#define DDR3CRU_D3BPLL_CON3_D3BPLL_MFR_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON3_D3BPLL_MFR_MASK (0xFFU << DDR3CRU_D3BPLL_CON3_D3BPLL_MFR_SHIFT) /* 0x000000FF */ +#define DDR3CRU_D3BPLL_CON3_D3BPLL_MRR_SHIFT (8U) +#define DDR3CRU_D3BPLL_CON3_D3BPLL_MRR_MASK (0x3FU << DDR3CRU_D3BPLL_CON3_D3BPLL_MRR_SHIFT) /* 0x00003F00 */ +#define DDR3CRU_D3BPLL_CON3_D3BPLL_SEL_PF_SHIFT (14U) +#define DDR3CRU_D3BPLL_CON3_D3BPLL_SEL_PF_MASK (0x3U << DDR3CRU_D3BPLL_CON3_D3BPLL_SEL_PF_SHIFT) /* 0x0000C000 */ +/* D3BPLL_CON4 */ +#define DDR3CRU_D3BPLL_CON4_OFFSET (0x30U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_SSCG_EN_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_SSCG_EN_MASK (0x1U << DDR3CRU_D3BPLL_CON4_D3BPLL_SSCG_EN_SHIFT) /* 0x00000001 */ +#define DDR3CRU_D3BPLL_CON4_D3BPLL_AFC_ENB_SHIFT (3U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_AFC_ENB_MASK (0x1U << DDR3CRU_D3BPLL_CON4_D3BPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DDR3CRU_D3BPLL_CON4_D3BPLL_EXTAFC_SHIFT (4U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_EXTAFC_MASK (0x1FU << DDR3CRU_D3BPLL_CON4_D3BPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DDR3CRU_D3BPLL_CON4_D3BPLL_FEED_EN_SHIFT (14U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_FEED_EN_MASK (0x1U << DDR3CRU_D3BPLL_CON4_D3BPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DDR3CRU_D3BPLL_CON4_D3BPLL_FSEL_SHIFT (15U) +#define DDR3CRU_D3BPLL_CON4_D3BPLL_FSEL_MASK (0x1U << DDR3CRU_D3BPLL_CON4_D3BPLL_FSEL_SHIFT) /* 0x00008000 */ +/* D3BPLL_CON5 */ +#define DDR3CRU_D3BPLL_CON5_OFFSET (0x34U) +#define DDR3CRU_D3BPLL_CON5_D3BPLL_FOUT_MASK_SHIFT (0U) +#define DDR3CRU_D3BPLL_CON5_D3BPLL_FOUT_MASK_MASK (0x1U << DDR3CRU_D3BPLL_CON5_D3BPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +/* D3BPLL_CON6 */ +#define DDR3CRU_D3BPLL_CON6_OFFSET (0x38U) +#define DDR3CRU_D3BPLL_CON6_D3BPLL_AFC_CODE_SHIFT (10U) +#define DDR3CRU_D3BPLL_CON6_D3BPLL_AFC_CODE_MASK (0x1FU << DDR3CRU_D3BPLL_CON6_D3BPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DDR3CRU_D3BPLL_CON6_D3BPLL_LOCK_SHIFT (15U) +#define DDR3CRU_D3BPLL_CON6_D3BPLL_LOCK_MASK (0x1U << DDR3CRU_D3BPLL_CON6_D3BPLL_LOCK_SHIFT) /* 0x00008000 */ +/* CLKSEL_CON00 */ +#define DDR3CRU_CLKSEL_CON00_OFFSET (0x300U) +#define DDR3CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH3_SEL_SHIFT (0U) +#define DDR3CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH3_SEL_MASK (0x1U << DDR3CRU_CLKSEL_CON00_CLK_DDRPHY2X_CH3_SEL_SHIFT) /* 0x00000001 */ +/* GATE_CON00 */ +#define DDR3CRU_GATE_CON00_OFFSET (0x800U) +#define DDR3CRU_GATE_CON00_PCLK_DDR_CRU_CH3_EN_SHIFT (3U) +#define DDR3CRU_GATE_CON00_PCLK_DDR_CRU_CH3_EN_MASK (0x1U << DDR3CRU_GATE_CON00_PCLK_DDR_CRU_CH3_EN_SHIFT) /* 0x00000008 */ +#define DDR3CRU_GATE_CON00_PCLK_DDRPHY_CH3_EN_SHIFT (4U) +#define DDR3CRU_GATE_CON00_PCLK_DDRPHY_CH3_EN_MASK (0x1U << DDR3CRU_GATE_CON00_PCLK_DDRPHY_CH3_EN_SHIFT) /* 0x00000010 */ +#define DDR3CRU_GATE_CON00_CLK_OSC_DDRPHY_CH3_EN_SHIFT (5U) +#define DDR3CRU_GATE_CON00_CLK_OSC_DDRPHY_CH3_EN_MASK (0x1U << DDR3CRU_GATE_CON00_CLK_OSC_DDRPHY_CH3_EN_SHIFT) /* 0x00000020 */ +/* SOFTRST_CON00 */ +#define DDR3CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH3_SHIFT (1U) +#define DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH3_MASK (0x1U << DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2XDIV_CH3_SHIFT) /* 0x00000002 */ +#define DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH3_SHIFT (2U) +#define DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH3_MASK (0x1U << DDR3CRU_SOFTRST_CON00_RESETN_DDRPHY2X_CH3_SHIFT) /* 0x00000004 */ +#define DDR3CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH3_SHIFT (3U) +#define DDR3CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH3_MASK (0x1U << DDR3CRU_SOFTRST_CON00_PRESETN_DDR_CRU_CH3_SHIFT) /* 0x00000008 */ +#define DDR3CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH3_SHIFT (4U) +#define DDR3CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH3_MASK (0x1U << DDR3CRU_SOFTRST_CON00_PRESETN_DDRPHY_CH3_SHIFT) /* 0x00000010 */ +/**************************************BIGCORE0CRU***************************************/ +/* B0PLL_CON0 */ +#define BIGCORE0CRU_B0PLL_CON0_OFFSET (0x0U) +#define BIGCORE0CRU_B0PLL_CON0_B0PLL_M_SHIFT (0U) +#define BIGCORE0CRU_B0PLL_CON0_B0PLL_M_MASK (0x3FFU << BIGCORE0CRU_B0PLL_CON0_B0PLL_M_SHIFT) /* 0x000003FF */ +#define BIGCORE0CRU_B0PLL_CON0_B0PLL_BP_SHIFT (15U) +#define BIGCORE0CRU_B0PLL_CON0_B0PLL_BP_MASK (0x1U << BIGCORE0CRU_B0PLL_CON0_B0PLL_BP_SHIFT) /* 0x00008000 */ +/* B0PLL_CON1 */ +#define BIGCORE0CRU_B0PLL_CON1_OFFSET (0x4U) +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_P_SHIFT (0U) +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_P_MASK (0x3FU << BIGCORE0CRU_B0PLL_CON1_B0PLL_P_SHIFT) /* 0x0000003F */ +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_S_SHIFT (6U) +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_S_MASK (0x7U << BIGCORE0CRU_B0PLL_CON1_B0PLL_S_SHIFT) /* 0x000001C0 */ +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_RESETB_SHIFT (13U) +#define BIGCORE0CRU_B0PLL_CON1_B0PLL_RESETB_MASK (0x1U << BIGCORE0CRU_B0PLL_CON1_B0PLL_RESETB_SHIFT) /* 0x00002000 */ +/* B0PLL_CON4 */ +#define BIGCORE0CRU_B0PLL_CON4_OFFSET (0x8U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_ICP_SHIFT (1U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_ICP_MASK (0x3U << BIGCORE0CRU_B0PLL_CON4_B0PLL_ICP_SHIFT) /* 0x00000006 */ +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_AFC_ENB_SHIFT (3U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_AFC_ENB_MASK (0x1U << BIGCORE0CRU_B0PLL_CON4_B0PLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_EXTAFC_SHIFT (4U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_EXTAFC_MASK (0x1FU << BIGCORE0CRU_B0PLL_CON4_B0PLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_FEED_EN_SHIFT (14U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_FEED_EN_MASK (0x1U << BIGCORE0CRU_B0PLL_CON4_B0PLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_FSEL_SHIFT (15U) +#define BIGCORE0CRU_B0PLL_CON4_B0PLL_FSEL_MASK (0x1U << BIGCORE0CRU_B0PLL_CON4_B0PLL_FSEL_SHIFT) /* 0x00008000 */ +/* B0PLL_CON5 */ +#define BIGCORE0CRU_B0PLL_CON5_OFFSET (0x10U) +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_FOUT_MASK_SHIFT (0U) +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_FOUT_MASK_MASK (0x1U << BIGCORE0CRU_B0PLL_CON5_B0PLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_IN_SHIFT (5U) +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_IN_MASK (0x3U << BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_IN_SHIFT) /* 0x00000060 */ +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_OUT_SHIFT (7U) +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_OUT_MASK (0x3U << BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_OUT_SHIFT) /* 0x00000180 */ +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_DLY_SHIFT (9U) +#define BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_DLY_MASK (0x3U << BIGCORE0CRU_B0PLL_CON5_B0PLL_LOCK_CON_DLY_SHIFT) /* 0x00000600 */ +/* B0PLL_CON6 */ +#define BIGCORE0CRU_B0PLL_CON6_OFFSET (0x14U) +#define BIGCORE0CRU_B0PLL_CON6_B0PLL_AFC_CODE_SHIFT (10U) +#define BIGCORE0CRU_B0PLL_CON6_B0PLL_AFC_CODE_MASK (0x1FU << BIGCORE0CRU_B0PLL_CON6_B0PLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define BIGCORE0CRU_B0PLL_CON6_B0PLL_LOCK_SHIFT (15U) +#define BIGCORE0CRU_B0PLL_CON6_B0PLL_LOCK_MASK (0x1U << BIGCORE0CRU_B0PLL_CON6_B0PLL_LOCK_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define BIGCORE0CRU_MODE_CON00_OFFSET (0x280U) +#define BIGCORE0CRU_MODE_CON00_CLK_B0PLL_MODE_SHIFT (0U) +#define BIGCORE0CRU_MODE_CON00_CLK_B0PLL_MODE_MASK (0x3U << BIGCORE0CRU_MODE_CON00_CLK_B0PLL_MODE_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON00 */ +#define BIGCORE0CRU_CLKSEL_CON00_OFFSET (0x300U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SLOW_SRC_SEL_SHIFT (0U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SLOW_SRC_SEL_MASK (0x1U << BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SLOW_SRC_SEL_SHIFT) /* 0x00000001 */ +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_GPLL_SRC_DIV_SHIFT (1U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_GPLL_SRC_DIV_MASK (0x1FU << BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_GPLL_SRC_DIV_SHIFT) /* 0x0000003E */ +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SRC_SEL_SHIFT (6U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SRC_SEL_MASK (0x3U << BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B01_SRC_SEL_SHIFT) /* 0x000000C0 */ +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_UC_DIV_SHIFT (8U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_UC_DIV_MASK (0x1FU << BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_UC_DIV_SHIFT) /* 0x00001F00 */ +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_SEL_SHIFT (13U) +#define BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_SEL_MASK (0x3U << BIGCORE0CRU_CLKSEL_CON00_CLK_CORE_B0_SEL_SHIFT) /* 0x00006000 */ +/* CLKSEL_CON01 */ +#define BIGCORE0CRU_CLKSEL_CON01_OFFSET (0x304U) +#define BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_UC_DIV_SHIFT (0U) +#define BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_UC_DIV_MASK (0x1FU << BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_UC_DIV_SHIFT) /* 0x0000001F */ +#define BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_SEL_SHIFT (5U) +#define BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_SEL_MASK (0x3U << BIGCORE0CRU_CLKSEL_CON01_CLK_CORE_B1_SEL_SHIFT) /* 0x00000060 */ +#define BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_DIV_SHIFT (7U) +#define BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_DIV_MASK (0x3FU << BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_DIV_SHIFT) /* 0x00001F80 */ +#define BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_SEL_SHIFT (13U) +#define BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_SEL_MASK (0x1U << BIGCORE0CRU_CLKSEL_CON01_CLK_TESTOUT_B0_SEL_SHIFT) /* 0x00002000 */ +#define BIGCORE0CRU_CLKSEL_CON01_REFCLK_BIGCORE0_PVTPLL_SEL_SHIFT (14U) +#define BIGCORE0CRU_CLKSEL_CON01_REFCLK_BIGCORE0_PVTPLL_SEL_MASK (0x1U << BIGCORE0CRU_CLKSEL_CON01_REFCLK_BIGCORE0_PVTPLL_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON02 */ +#define BIGCORE0CRU_CLKSEL_CON02_OFFSET (0x308U) +#define BIGCORE0CRU_CLKSEL_CON02_PCLK_BIGCORE0_ROOT_SEL_SHIFT (0U) +#define BIGCORE0CRU_CLKSEL_CON02_PCLK_BIGCORE0_ROOT_SEL_MASK (0x3U << BIGCORE0CRU_CLKSEL_CON02_PCLK_BIGCORE0_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define BIGCORE0CRU_CLKSEL_CON02_CLK_CORE_B01_PVTPLL_T_SEL_SHIFT (2U) +#define BIGCORE0CRU_CLKSEL_CON02_CLK_CORE_B01_PVTPLL_T_SEL_MASK (0x1U << BIGCORE0CRU_CLKSEL_CON02_CLK_CORE_B01_PVTPLL_T_SEL_SHIFT) /* 0x00000004 */ +/* GATE_CON00 */ +#define BIGCORE0CRU_GATE_CON00_OFFSET (0x800U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B01_I_EN_SHIFT (1U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B01_I_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_B01_I_EN_SHIFT) /* 0x00000002 */ +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_CLEAN_EN_SHIFT (2U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_CLEAN_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_CLEAN_EN_SHIFT) /* 0x00000004 */ +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_UC_EN_SHIFT (3U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_UC_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_B0_UC_EN_SHIFT) /* 0x00000008 */ +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_CLEAN_EN_SHIFT (6U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_CLEAN_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_CLEAN_EN_SHIFT) /* 0x00000040 */ +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_UC_EN_SHIFT (7U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_UC_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_B1_UC_EN_SHIFT) /* 0x00000080 */ +#define BIGCORE0CRU_GATE_CON00_CLK_TESTOUT_B0_EN_SHIFT (10U) +#define BIGCORE0CRU_GATE_CON00_CLK_TESTOUT_B0_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_TESTOUT_B0_EN_SHIFT) /* 0x00000400 */ +#define BIGCORE0CRU_GATE_CON00_REFCLK_BIGCORE0_PVTPLL_EN_SHIFT (11U) +#define BIGCORE0CRU_GATE_CON00_REFCLK_BIGCORE0_PVTPLL_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_REFCLK_BIGCORE0_PVTPLL_EN_SHIFT) /* 0x00000800 */ +#define BIGCORE0CRU_GATE_CON00_CLK_BIGCORE0_PVTM_EN_SHIFT (12U) +#define BIGCORE0CRU_GATE_CON00_CLK_BIGCORE0_PVTM_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_BIGCORE0_PVTM_EN_SHIFT) /* 0x00001000 */ +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_BIGCORE0_PVTM_EN_SHIFT (13U) +#define BIGCORE0CRU_GATE_CON00_CLK_CORE_BIGCORE0_PVTM_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_CLK_CORE_BIGCORE0_PVTM_EN_SHIFT) /* 0x00002000 */ +#define BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_ROOT_EN_SHIFT (14U) +#define BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_ROOT_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_ROOT_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_BIU_EN_SHIFT (15U) +#define BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_BIU_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON00_PCLK_BIGCORE0_BIU_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define BIGCORE0CRU_GATE_CON01_OFFSET (0x804U) +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_PVTM_EN_SHIFT (0U) +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_PVTM_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_PVTM_EN_SHIFT) /* 0x00000001 */ +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_GRF_EN_SHIFT (1U) +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_GRF_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_GRF_EN_SHIFT) /* 0x00000002 */ +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CRU_EN_SHIFT (2U) +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CRU_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CRU_EN_SHIFT) /* 0x00000004 */ +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CPUBOOST_EN_SHIFT (3U) +#define BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CPUBOOST_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON01_PCLK_BIGCORE0_CPUBOOST_EN_SHIFT) /* 0x00000008 */ +#define BIGCORE0CRU_GATE_CON01_CLK_24M_BIGCORE0_CPUBOOST_EN_SHIFT (4U) +#define BIGCORE0CRU_GATE_CON01_CLK_24M_BIGCORE0_CPUBOOST_EN_MASK (0x1U << BIGCORE0CRU_GATE_CON01_CLK_24M_BIGCORE0_CPUBOOST_EN_SHIFT) /* 0x00000010 */ +/* SOFTRST_CON00 */ +#define BIGCORE0CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B0_SHIFT (4U) +#define BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B0_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B0_SHIFT) /* 0x00000010 */ +#define BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B0_SHIFT (5U) +#define BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B0_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B0_SHIFT) /* 0x00000020 */ +#define BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B1_SHIFT (8U) +#define BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B1_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_NCPUPORESET_B1_SHIFT) /* 0x00000100 */ +#define BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B1_SHIFT (9U) +#define BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B1_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_NCORERESET_B1_SHIFT) /* 0x00000200 */ +#define BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTPLL_SHIFT (11U) +#define BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTPLL_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTPLL_SHIFT) /* 0x00000800 */ +#define BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTM_SHIFT (12U) +#define BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTM_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_RESETN_BIGCORE0_PVTM_SHIFT) /* 0x00001000 */ +#define BIGCORE0CRU_SOFTRST_CON00_PRESETN_BIGCORE0_BIU_SHIFT (15U) +#define BIGCORE0CRU_SOFTRST_CON00_PRESETN_BIGCORE0_BIU_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON00_PRESETN_BIGCORE0_BIU_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON01 */ +#define BIGCORE0CRU_SOFTRST_CON01_OFFSET (0xA04U) +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_PVTM_SHIFT (0U) +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_PVTM_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_PVTM_SHIFT) /* 0x00000001 */ +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_GRF_SHIFT (1U) +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_GRF_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_GRF_SHIFT) /* 0x00000002 */ +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CRU_SHIFT (2U) +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CRU_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CRU_SHIFT) /* 0x00000004 */ +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CPUBOOST_SHIFT (3U) +#define BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CPUBOOST_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON01_PRESETN_BIGCORE0_CPUBOOST_SHIFT) /* 0x00000008 */ +#define BIGCORE0CRU_SOFTRST_CON01_RESETN_24M_BIGCORE0_CPUBOOST_SHIFT (4U) +#define BIGCORE0CRU_SOFTRST_CON01_RESETN_24M_BIGCORE0_CPUBOOST_MASK (0x1U << BIGCORE0CRU_SOFTRST_CON01_RESETN_24M_BIGCORE0_CPUBOOST_SHIFT) /* 0x00000010 */ +/* SMOTH_DIVFREE_CON04 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_OFFSET (0xCC0U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_STEP_SHIFT (0U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_STEP_MASK (0x1FU << BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_STEP_SHIFT) /* 0x0000001F */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_SMDIV_CLK_OFF_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_GATE_SMTH_EN_SHIFT (14U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_GATE_SMTH_EN_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_BYPASS_SHIFT (15U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_BYPASS_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_FREQ_KEEP_SHIFT (16U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_FREQ_KEEP_MASK (0xFFFFU << BIGCORE0CRU_SMOTH_DIVFREE_CON04_CLK_CORE_B0_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON05 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_OFFSET (0xCC4U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_STEP_SHIFT (0U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_STEP_MASK (0x1FU << BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_STEP_SHIFT) /* 0x0000001F */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_SMDIV_CLK_OFF_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_GATE_SMTH_EN_SHIFT (14U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_GATE_SMTH_EN_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_BYPASS_SHIFT (15U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_BYPASS_MASK (0x1U << BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_FREQ_KEEP_SHIFT (16U) +#define BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_FREQ_KEEP_MASK (0xFFFFU << BIGCORE0CRU_SMOTH_DIVFREE_CON05_CLK_CORE_B1_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_CORE_B01_I_CON0 */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_OFFSET (0xD00U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_IDLE_TH_SHIFT (0U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_IDLE_TH_MASK (0xFFFFU << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_WAIT_TH_SHIFT (16U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_WAIT_TH_MASK (0xFFFFU << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON0_CLK_CORE_B01_I_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_CORE_B01_I_CON1 */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_OFFSET (0xD04U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_CTRL_SHIFT (0U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_CTRL_MASK (0xFFFU << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_EN_SHIFT (12U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_EN_MASK (0x1U << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_SWITCH_EN_SHIFT (13U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_SWITCH_EN_MASK (0x1U << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_CLKSEL_CFG_SHIFT (14U) +#define BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_CLKSEL_CFG_MASK (0x3U << BIGCORE0CRU_AUTOCS_CLK_CORE_B01_I_CON1_CLK_CORE_B01_I_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/**************************************BIGCORE1CRU***************************************/ +/* B1PLL_CON0 */ +#define BIGCORE1CRU_B1PLL_CON0_OFFSET (0x20U) +#define BIGCORE1CRU_B1PLL_CON0_B1PLL_M_SHIFT (0U) +#define BIGCORE1CRU_B1PLL_CON0_B1PLL_M_MASK (0x3FFU << BIGCORE1CRU_B1PLL_CON0_B1PLL_M_SHIFT) /* 0x000003FF */ +#define BIGCORE1CRU_B1PLL_CON0_B1PLL_BP_SHIFT (15U) +#define BIGCORE1CRU_B1PLL_CON0_B1PLL_BP_MASK (0x1U << BIGCORE1CRU_B1PLL_CON0_B1PLL_BP_SHIFT) /* 0x00008000 */ +/* B1PLL_CON1 */ +#define BIGCORE1CRU_B1PLL_CON1_OFFSET (0x24U) +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_P_SHIFT (0U) +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_P_MASK (0x3FU << BIGCORE1CRU_B1PLL_CON1_B1PLL_P_SHIFT) /* 0x0000003F */ +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_S_SHIFT (6U) +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_S_MASK (0x7U << BIGCORE1CRU_B1PLL_CON1_B1PLL_S_SHIFT) /* 0x000001C0 */ +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_RESETB_SHIFT (13U) +#define BIGCORE1CRU_B1PLL_CON1_B1PLL_RESETB_MASK (0x1U << BIGCORE1CRU_B1PLL_CON1_B1PLL_RESETB_SHIFT) /* 0x00002000 */ +/* B1PLL_CON4 */ +#define BIGCORE1CRU_B1PLL_CON4_OFFSET (0x28U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_ICP_SHIFT (1U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_ICP_MASK (0x3U << BIGCORE1CRU_B1PLL_CON4_B1PLL_ICP_SHIFT) /* 0x00000006 */ +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_AFC_ENB_SHIFT (3U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_AFC_ENB_MASK (0x1U << BIGCORE1CRU_B1PLL_CON4_B1PLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_EXTAFC_SHIFT (4U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_EXTAFC_MASK (0x1FU << BIGCORE1CRU_B1PLL_CON4_B1PLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_FEED_EN_SHIFT (14U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_FEED_EN_MASK (0x1U << BIGCORE1CRU_B1PLL_CON4_B1PLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_FSEL_SHIFT (15U) +#define BIGCORE1CRU_B1PLL_CON4_B1PLL_FSEL_MASK (0x1U << BIGCORE1CRU_B1PLL_CON4_B1PLL_FSEL_SHIFT) /* 0x00008000 */ +/* B1PLL_CON5 */ +#define BIGCORE1CRU_B1PLL_CON5_OFFSET (0x30U) +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_FOUT_MASK_SHIFT (0U) +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_FOUT_MASK_MASK (0x1U << BIGCORE1CRU_B1PLL_CON5_B1PLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_IN_SHIFT (5U) +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_IN_MASK (0x3U << BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_IN_SHIFT) /* 0x00000060 */ +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_OUT_SHIFT (7U) +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_OUT_MASK (0x3U << BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_OUT_SHIFT) /* 0x00000180 */ +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_DLY_SHIFT (9U) +#define BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_DLY_MASK (0x3U << BIGCORE1CRU_B1PLL_CON5_B1PLL_LOCK_CON_DLY_SHIFT) /* 0x00000600 */ +/* B1PLL_CON6 */ +#define BIGCORE1CRU_B1PLL_CON6_OFFSET (0x34U) +#define BIGCORE1CRU_B1PLL_CON6_B1PLL_AFC_CODE_SHIFT (10U) +#define BIGCORE1CRU_B1PLL_CON6_B1PLL_AFC_CODE_MASK (0x1FU << BIGCORE1CRU_B1PLL_CON6_B1PLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define BIGCORE1CRU_B1PLL_CON6_B1PLL_LOCK_SHIFT (15U) +#define BIGCORE1CRU_B1PLL_CON6_B1PLL_LOCK_MASK (0x1U << BIGCORE1CRU_B1PLL_CON6_B1PLL_LOCK_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define BIGCORE1CRU_MODE_CON00_OFFSET (0x280U) +#define BIGCORE1CRU_MODE_CON00_CLK_B1PLL_MODE_SHIFT (0U) +#define BIGCORE1CRU_MODE_CON00_CLK_B1PLL_MODE_MASK (0x3U << BIGCORE1CRU_MODE_CON00_CLK_B1PLL_MODE_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON00 */ +#define BIGCORE1CRU_CLKSEL_CON00_OFFSET (0x300U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SLOW_SRC_SEL_SHIFT (0U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SLOW_SRC_SEL_MASK (0x1U << BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SLOW_SRC_SEL_SHIFT) /* 0x00000001 */ +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_GPLL_SRC_DIV_SHIFT (1U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_GPLL_SRC_DIV_MASK (0x1FU << BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_GPLL_SRC_DIV_SHIFT) /* 0x0000003E */ +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SRC_SEL_SHIFT (6U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SRC_SEL_MASK (0x3U << BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B23_SRC_SEL_SHIFT) /* 0x000000C0 */ +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_UC_DIV_SHIFT (8U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_UC_DIV_MASK (0x1FU << BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_UC_DIV_SHIFT) /* 0x00001F00 */ +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_SEL_SHIFT (13U) +#define BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_SEL_MASK (0x3U << BIGCORE1CRU_CLKSEL_CON00_CLK_CORE_B2_SEL_SHIFT) /* 0x00006000 */ +/* CLKSEL_CON01 */ +#define BIGCORE1CRU_CLKSEL_CON01_OFFSET (0x304U) +#define BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_UC_DIV_SHIFT (0U) +#define BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_UC_DIV_MASK (0x1FU << BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_UC_DIV_SHIFT) /* 0x0000001F */ +#define BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_SEL_SHIFT (5U) +#define BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_SEL_MASK (0x3U << BIGCORE1CRU_CLKSEL_CON01_CLK_CORE_B3_SEL_SHIFT) /* 0x00000060 */ +#define BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_DIV_SHIFT (7U) +#define BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_DIV_MASK (0x3FU << BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_DIV_SHIFT) /* 0x00001F80 */ +#define BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_SEL_SHIFT (13U) +#define BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_SEL_MASK (0x1U << BIGCORE1CRU_CLKSEL_CON01_CLK_TESTOUT_B1_SEL_SHIFT) /* 0x00002000 */ +#define BIGCORE1CRU_CLKSEL_CON01_REFCLK_BIGCORE1_PVTPLL_SEL_SHIFT (14U) +#define BIGCORE1CRU_CLKSEL_CON01_REFCLK_BIGCORE1_PVTPLL_SEL_MASK (0x1U << BIGCORE1CRU_CLKSEL_CON01_REFCLK_BIGCORE1_PVTPLL_SEL_SHIFT) /* 0x00004000 */ +/* CLKSEL_CON02 */ +#define BIGCORE1CRU_CLKSEL_CON02_OFFSET (0x308U) +#define BIGCORE1CRU_CLKSEL_CON02_PCLK_BIGCORE1_ROOT_SEL_SHIFT (0U) +#define BIGCORE1CRU_CLKSEL_CON02_PCLK_BIGCORE1_ROOT_SEL_MASK (0x3U << BIGCORE1CRU_CLKSEL_CON02_PCLK_BIGCORE1_ROOT_SEL_SHIFT) /* 0x00000003 */ +#define BIGCORE1CRU_CLKSEL_CON02_CLK_CORE_B23PVTPLL_T_SEL_SHIFT (2U) +#define BIGCORE1CRU_CLKSEL_CON02_CLK_CORE_B23PVTPLL_T_SEL_MASK (0x1U << BIGCORE1CRU_CLKSEL_CON02_CLK_CORE_B23PVTPLL_T_SEL_SHIFT) /* 0x00000004 */ +/* GATE_CON00 */ +#define BIGCORE1CRU_GATE_CON00_OFFSET (0x800U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B23_I_EN_SHIFT (1U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B23_I_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_B23_I_EN_SHIFT) /* 0x00000002 */ +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_CLEAN_EN_SHIFT (2U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_CLEAN_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_CLEAN_EN_SHIFT) /* 0x00000004 */ +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_UC_EN_SHIFT (3U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_UC_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_B2_UC_EN_SHIFT) /* 0x00000008 */ +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_CLEAN_EN_SHIFT (6U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_CLEAN_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_CLEAN_EN_SHIFT) /* 0x00000040 */ +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_UC_EN_SHIFT (7U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_UC_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_B3_UC_EN_SHIFT) /* 0x00000080 */ +#define BIGCORE1CRU_GATE_CON00_CLK_TESTOUT_B1_EN_SHIFT (10U) +#define BIGCORE1CRU_GATE_CON00_CLK_TESTOUT_B1_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_TESTOUT_B1_EN_SHIFT) /* 0x00000400 */ +#define BIGCORE1CRU_GATE_CON00_REFCLK_BIGCORE1_PVTPLL_EN_SHIFT (11U) +#define BIGCORE1CRU_GATE_CON00_REFCLK_BIGCORE1_PVTPLL_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_REFCLK_BIGCORE1_PVTPLL_EN_SHIFT) /* 0x00000800 */ +#define BIGCORE1CRU_GATE_CON00_CLK_BIGCORE1_PVTM_EN_SHIFT (12U) +#define BIGCORE1CRU_GATE_CON00_CLK_BIGCORE1_PVTM_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_BIGCORE1_PVTM_EN_SHIFT) /* 0x00001000 */ +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_BIGCORE1_PVTM_EN_SHIFT (13U) +#define BIGCORE1CRU_GATE_CON00_CLK_CORE_BIGCORE1_PVTM_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_CLK_CORE_BIGCORE1_PVTM_EN_SHIFT) /* 0x00002000 */ +#define BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_ROOT_EN_SHIFT (14U) +#define BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_ROOT_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_ROOT_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_BIU_EN_SHIFT (15U) +#define BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_BIU_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON00_PCLK_BIGCORE1_BIU_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define BIGCORE1CRU_GATE_CON01_OFFSET (0x804U) +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_PVTM_EN_SHIFT (0U) +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_PVTM_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_PVTM_EN_SHIFT) /* 0x00000001 */ +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_GRF_EN_SHIFT (1U) +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_GRF_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_GRF_EN_SHIFT) /* 0x00000002 */ +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CRU_EN_SHIFT (2U) +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CRU_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CRU_EN_SHIFT) /* 0x00000004 */ +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CPUBOOST_EN_SHIFT (3U) +#define BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CPUBOOST_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON01_PCLK_BIGCORE1_CPUBOOST_EN_SHIFT) /* 0x00000008 */ +#define BIGCORE1CRU_GATE_CON01_CLK_24M_BIGCORE1_CPUBOOST_EN_SHIFT (4U) +#define BIGCORE1CRU_GATE_CON01_CLK_24M_BIGCORE1_CPUBOOST_EN_MASK (0x1U << BIGCORE1CRU_GATE_CON01_CLK_24M_BIGCORE1_CPUBOOST_EN_SHIFT) /* 0x00000010 */ +/* SOFTRST_CON00 */ +#define BIGCORE1CRU_SOFTRST_CON00_OFFSET (0xA00U) +#define BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B2_SHIFT (4U) +#define BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B2_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B2_SHIFT) /* 0x00000010 */ +#define BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B2_SHIFT (5U) +#define BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B2_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B2_SHIFT) /* 0x00000020 */ +#define BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B3_SHIFT (8U) +#define BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B3_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_NCPUPORESET_B3_SHIFT) /* 0x00000100 */ +#define BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B3_SHIFT (9U) +#define BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B3_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_NCORERESET_B3_SHIFT) /* 0x00000200 */ +#define BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTPLL_SHIFT (11U) +#define BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTPLL_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTPLL_SHIFT) /* 0x00000800 */ +#define BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTM_SHIFT (12U) +#define BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTM_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_RESETN_BIGCORE1_PVTM_SHIFT) /* 0x00001000 */ +#define BIGCORE1CRU_SOFTRST_CON00_PRESETN_BIGCORE1_BIU_SHIFT (15U) +#define BIGCORE1CRU_SOFTRST_CON00_PRESETN_BIGCORE1_BIU_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON00_PRESETN_BIGCORE1_BIU_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON01 */ +#define BIGCORE1CRU_SOFTRST_CON01_OFFSET (0xA04U) +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_PVTM_SHIFT (0U) +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_PVTM_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_PVTM_SHIFT) /* 0x00000001 */ +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_GRF_SHIFT (1U) +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_GRF_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_GRF_SHIFT) /* 0x00000002 */ +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CRU_SHIFT (2U) +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CRU_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CRU_SHIFT) /* 0x00000004 */ +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CPUBOOST_SHIFT (3U) +#define BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CPUBOOST_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON01_PRESETN_BIGCORE1_CPUBOOST_SHIFT) /* 0x00000008 */ +#define BIGCORE1CRU_SOFTRST_CON01_RESETN_24M_BIGCORE1_CPUBOOST_SHIFT (4U) +#define BIGCORE1CRU_SOFTRST_CON01_RESETN_24M_BIGCORE1_CPUBOOST_MASK (0x1U << BIGCORE1CRU_SOFTRST_CON01_RESETN_24M_BIGCORE1_CPUBOOST_SHIFT) /* 0x00000010 */ +/* SMOTH_DIVFREE_CON06 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_OFFSET (0xCC0U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_STEP_SHIFT (0U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_STEP_MASK (0x1FU << BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_STEP_SHIFT) /* 0x0000001F */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_SMDIV_CLK_OFF_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_GATE_SMTH_EN_SHIFT (14U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_GATE_SMTH_EN_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_BYPASS_SHIFT (15U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_BYPASS_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_FREQ_KEEP_SHIFT (16U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_FREQ_KEEP_MASK (0xFFFFU << BIGCORE1CRU_SMOTH_DIVFREE_CON06_CLK_CORE_B2_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON07 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_OFFSET (0xCC4U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_STEP_SHIFT (0U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_STEP_MASK (0x1FU << BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_STEP_SHIFT) /* 0x0000001F */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_SMDIV_CLK_OFF_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_GATE_SMTH_EN_SHIFT (14U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_GATE_SMTH_EN_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_BYPASS_SHIFT (15U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_BYPASS_MASK (0x1U << BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_FREQ_KEEP_SHIFT (16U) +#define BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_FREQ_KEEP_MASK (0xFFFFU << BIGCORE1CRU_SMOTH_DIVFREE_CON07_CLK_CORE_B3_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_CORE_B23_I_CON0 */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_OFFSET (0xD00U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_IDLE_TH_SHIFT (0U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_IDLE_TH_MASK (0xFFFFU << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_WAIT_TH_SHIFT (16U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_WAIT_TH_MASK (0xFFFFU << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON0_CLK_CORE_B23_I_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_CORE_B23_I_CON1 */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_OFFSET (0xD04U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_CTRL_SHIFT (0U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_CTRL_MASK (0xFFFU << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_EN_SHIFT (12U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_EN_MASK (0x1U << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_SWITCH_EN_SHIFT (13U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_SWITCH_EN_MASK (0x1U << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_CLKSEL_CFG_SHIFT (14U) +#define BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_CLKSEL_CFG_MASK (0x3U << BIGCORE1CRU_AUTOCS_CLK_CORE_B23_I_CON1_CLK_CORE_B23_I_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/*****************************************DSUCRU*****************************************/ +/* LPLL_CON0 */ +#define DSUCRU_LPLL_CON0_OFFSET (0x40U) +#define DSUCRU_LPLL_CON0_LPLL_M_SHIFT (0U) +#define DSUCRU_LPLL_CON0_LPLL_M_MASK (0x3FFU << DSUCRU_LPLL_CON0_LPLL_M_SHIFT) /* 0x000003FF */ +#define DSUCRU_LPLL_CON0_LPLL_BP_SHIFT (15U) +#define DSUCRU_LPLL_CON0_LPLL_BP_MASK (0x1U << DSUCRU_LPLL_CON0_LPLL_BP_SHIFT) /* 0x00008000 */ +/* LPLL_CON1 */ +#define DSUCRU_LPLL_CON1_OFFSET (0x44U) +#define DSUCRU_LPLL_CON1_LPLL_P_SHIFT (0U) +#define DSUCRU_LPLL_CON1_LPLL_P_MASK (0x3FU << DSUCRU_LPLL_CON1_LPLL_P_SHIFT) /* 0x0000003F */ +#define DSUCRU_LPLL_CON1_LPLL_S_SHIFT (6U) +#define DSUCRU_LPLL_CON1_LPLL_S_MASK (0x7U << DSUCRU_LPLL_CON1_LPLL_S_SHIFT) /* 0x000001C0 */ +#define DSUCRU_LPLL_CON1_LPLL_RESETB_SHIFT (13U) +#define DSUCRU_LPLL_CON1_LPLL_RESETB_MASK (0x1U << DSUCRU_LPLL_CON1_LPLL_RESETB_SHIFT) /* 0x00002000 */ +/* LPLL_CON4 */ +#define DSUCRU_LPLL_CON4_OFFSET (0x48U) +#define DSUCRU_LPLL_CON4_LPLL_ICP_SHIFT (1U) +#define DSUCRU_LPLL_CON4_LPLL_ICP_MASK (0x3U << DSUCRU_LPLL_CON4_LPLL_ICP_SHIFT) /* 0x00000006 */ +#define DSUCRU_LPLL_CON4_LPLL_AFC_ENB_SHIFT (3U) +#define DSUCRU_LPLL_CON4_LPLL_AFC_ENB_MASK (0x1U << DSUCRU_LPLL_CON4_LPLL_AFC_ENB_SHIFT) /* 0x00000008 */ +#define DSUCRU_LPLL_CON4_LPLL_EXTAFC_SHIFT (4U) +#define DSUCRU_LPLL_CON4_LPLL_EXTAFC_MASK (0x1FU << DSUCRU_LPLL_CON4_LPLL_EXTAFC_SHIFT) /* 0x000001F0 */ +#define DSUCRU_LPLL_CON4_LPLL_FEED_EN_SHIFT (14U) +#define DSUCRU_LPLL_CON4_LPLL_FEED_EN_MASK (0x1U << DSUCRU_LPLL_CON4_LPLL_FEED_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_LPLL_CON4_LPLL_FSEL_SHIFT (15U) +#define DSUCRU_LPLL_CON4_LPLL_FSEL_MASK (0x1U << DSUCRU_LPLL_CON4_LPLL_FSEL_SHIFT) /* 0x00008000 */ +/* LPLL_CON5 */ +#define DSUCRU_LPLL_CON5_OFFSET (0x50U) +#define DSUCRU_LPLL_CON5_LPLL_FOUT_MASK_SHIFT (0U) +#define DSUCRU_LPLL_CON5_LPLL_FOUT_MASK_MASK (0x1U << DSUCRU_LPLL_CON5_LPLL_FOUT_MASK_SHIFT) /* 0x00000001 */ +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_IN_SHIFT (5U) +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_IN_MASK (0x3U << DSUCRU_LPLL_CON5_LPLL_LOCK_CON_IN_SHIFT) /* 0x00000060 */ +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_OUT_SHIFT (7U) +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_OUT_MASK (0x3U << DSUCRU_LPLL_CON5_LPLL_LOCK_CON_OUT_SHIFT) /* 0x00000180 */ +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_DLY_SHIFT (9U) +#define DSUCRU_LPLL_CON5_LPLL_LOCK_CON_DLY_MASK (0x3U << DSUCRU_LPLL_CON5_LPLL_LOCK_CON_DLY_SHIFT) /* 0x00000600 */ +/* LPLL_CON6 */ +#define DSUCRU_LPLL_CON6_OFFSET (0x54U) +#define DSUCRU_LPLL_CON6_LPLL_AFC_CODE_SHIFT (10U) +#define DSUCRU_LPLL_CON6_LPLL_AFC_CODE_MASK (0x1FU << DSUCRU_LPLL_CON6_LPLL_AFC_CODE_SHIFT) /* 0x00007C00 */ +#define DSUCRU_LPLL_CON6_LPLL_LOCK_SHIFT (15U) +#define DSUCRU_LPLL_CON6_LPLL_LOCK_MASK (0x1U << DSUCRU_LPLL_CON6_LPLL_LOCK_SHIFT) /* 0x00008000 */ +/* MODE_CON00 */ +#define DSUCRU_MODE_CON00_OFFSET (0x280U) +#define DSUCRU_MODE_CON00_CLK_LPLL_MODE_SHIFT (0U) +#define DSUCRU_MODE_CON00_CLK_LPLL_MODE_MASK (0x3U << DSUCRU_MODE_CON00_CLK_LPLL_MODE_SHIFT) /* 0x00000003 */ +/* CLKSEL_CON00 */ +#define DSUCRU_CLKSEL_CON00_OFFSET (0x300U) +#define DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_DIV_SHIFT (7U) +#define DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_DIV_SHIFT) /* 0x00000F80 */ +#define DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_SEL_SHIFT (12U) +#define DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON00_SCLK_DSU_DF_SRC_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON01 */ +#define DSUCRU_CLKSEL_CON01_OFFSET (0x304U) +#define DSUCRU_CLKSEL_CON01_SCLK_DSU_SRC_T_SEL_SHIFT (0U) +#define DSUCRU_CLKSEL_CON01_SCLK_DSU_SRC_T_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON01_SCLK_DSU_SRC_T_SEL_SHIFT) /* 0x00000001 */ +#define DSUCRU_CLKSEL_CON01_ACLKM_DSU_DIV_SHIFT (1U) +#define DSUCRU_CLKSEL_CON01_ACLKM_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON01_ACLKM_DSU_DIV_SHIFT) /* 0x0000003E */ +#define DSUCRU_CLKSEL_CON01_ACLKS_DSU_DIV_SHIFT (6U) +#define DSUCRU_CLKSEL_CON01_ACLKS_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON01_ACLKS_DSU_DIV_SHIFT) /* 0x000007C0 */ +#define DSUCRU_CLKSEL_CON01_ACLK_MP_DSU_DIV_SHIFT (11U) +#define DSUCRU_CLKSEL_CON01_ACLK_MP_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON01_ACLK_MP_DSU_DIV_SHIFT) /* 0x0000F800 */ +/* CLKSEL_CON02 */ +#define DSUCRU_CLKSEL_CON02_OFFSET (0x308U) +#define DSUCRU_CLKSEL_CON02_PERIPHCLK_DSU_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON02_PERIPHCLK_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON02_PERIPHCLK_DSU_DIV_SHIFT) /* 0x0000001F */ +#define DSUCRU_CLKSEL_CON02_CNTCLK_DSU_DIV_SHIFT (5U) +#define DSUCRU_CLKSEL_CON02_CNTCLK_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON02_CNTCLK_DSU_DIV_SHIFT) /* 0x000003E0 */ +#define DSUCRU_CLKSEL_CON02_TSCLK_DSU_DIV_SHIFT (10U) +#define DSUCRU_CLKSEL_CON02_TSCLK_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON02_TSCLK_DSU_DIV_SHIFT) /* 0x00007C00 */ +/* CLKSEL_CON03 */ +#define DSUCRU_CLKSEL_CON03_OFFSET (0x30CU) +#define DSUCRU_CLKSEL_CON03_ATCLK_DSU_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON03_ATCLK_DSU_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON03_ATCLK_DSU_DIV_SHIFT) /* 0x0000001F */ +#define DSUCRU_CLKSEL_CON03_GICCLK_DSU_T_DIV_SHIFT (5U) +#define DSUCRU_CLKSEL_CON03_GICCLK_DSU_T_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON03_GICCLK_DSU_T_DIV_SHIFT) /* 0x000003E0 */ +/* CLKSEL_CON04 */ +#define DSUCRU_CLKSEL_CON04_OFFSET (0x310U) +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_DIV_SHIFT) /* 0x0000001F */ +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_SEL_SHIFT (5U) +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON04_PCLK_DSU_ROOT_SEL_SHIFT) /* 0x00000060 */ +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_NS_ROOT_SEL_SHIFT (7U) +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_NS_ROOT_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON04_PCLK_DSU_NS_ROOT_SEL_SHIFT) /* 0x00000180 */ +#define DSUCRU_CLKSEL_CON04_REFCLK_LITCORE_PVTPLL_SEL_SHIFT (9U) +#define DSUCRU_CLKSEL_CON04_REFCLK_LITCORE_PVTPLL_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON04_REFCLK_LITCORE_PVTPLL_SEL_SHIFT) /* 0x00000200 */ +#define DSUCRU_CLKSEL_CON04_REFCLK_DSU_PVTPLL_SEL_SHIFT (10U) +#define DSUCRU_CLKSEL_CON04_REFCLK_DSU_PVTPLL_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON04_REFCLK_DSU_PVTPLL_SEL_SHIFT) /* 0x00000400 */ +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_S_ROOT_SEL_SHIFT (11U) +#define DSUCRU_CLKSEL_CON04_PCLK_DSU_S_ROOT_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON04_PCLK_DSU_S_ROOT_SEL_SHIFT) /* 0x00001800 */ +/* CLKSEL_CON05 */ +#define DSUCRU_CLKSEL_CON05_OFFSET (0x314U) +#define DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_DIV_MASK (0x3FU << DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_DIV_SHIFT) /* 0x0000003F */ +#define DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_SEL_SHIFT (6U) +#define DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON05_CLK_TESTOUT_L_SEL_SHIFT) /* 0x000000C0 */ +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_SLOW_SRC_SEL_SHIFT (8U) +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_SLOW_SRC_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON05_CLK_CORE_L_SLOW_SRC_SEL_SHIFT) /* 0x00000100 */ +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_GPLL_SRC_DIV_SHIFT (9U) +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_GPLL_SRC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON05_CLK_CORE_L_GPLL_SRC_DIV_SHIFT) /* 0x00003E00 */ +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_SRC_SEL_SHIFT (14U) +#define DSUCRU_CLKSEL_CON05_CLK_CORE_L_SRC_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON05_CLK_CORE_L_SRC_SEL_SHIFT) /* 0x0000C000 */ +/* CLKSEL_CON06 */ +#define DSUCRU_CLKSEL_CON06_OFFSET (0x318U) +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L0_UC_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L0_UC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON06_CLK_CORE_L0_UC_DIV_SHIFT) /* 0x0000001F */ +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L0_SEL_SHIFT (5U) +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L0_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON06_CLK_CORE_L0_SEL_SHIFT) /* 0x00000060 */ +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L1_UC_DIV_SHIFT (7U) +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L1_UC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON06_CLK_CORE_L1_UC_DIV_SHIFT) /* 0x00000F80 */ +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L1_SEL_SHIFT (12U) +#define DSUCRU_CLKSEL_CON06_CLK_CORE_L1_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON06_CLK_CORE_L1_SEL_SHIFT) /* 0x00003000 */ +/* CLKSEL_CON07 */ +#define DSUCRU_CLKSEL_CON07_OFFSET (0x31CU) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L2_UC_DIV_SHIFT (0U) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L2_UC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON07_CLK_CORE_L2_UC_DIV_SHIFT) /* 0x0000001F */ +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L2_SEL_SHIFT (5U) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L2_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON07_CLK_CORE_L2_SEL_SHIFT) /* 0x00000060 */ +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L3_UC_DIV_SHIFT (7U) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L3_UC_DIV_MASK (0x1FU << DSUCRU_CLKSEL_CON07_CLK_CORE_L3_UC_DIV_SHIFT) /* 0x00000F80 */ +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L3_SEL_SHIFT (12U) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L3_SEL_MASK (0x3U << DSUCRU_CLKSEL_CON07_CLK_CORE_L3_SEL_SHIFT) /* 0x00003000 */ +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L_PVTPLL_T_SEL_SHIFT (14U) +#define DSUCRU_CLKSEL_CON07_CLK_CORE_L_PVTPLL_T_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON07_CLK_CORE_L_PVTPLL_T_SEL_SHIFT) /* 0x00004000 */ +#define DSUCRU_CLKSEL_CON07_CLK_DSU_PVTPLL_T_SEL_SHIFT (15U) +#define DSUCRU_CLKSEL_CON07_CLK_DSU_PVTPLL_T_SEL_MASK (0x1U << DSUCRU_CLKSEL_CON07_CLK_DSU_PVTPLL_T_SEL_SHIFT) /* 0x00008000 */ +/* GATE_CON00 */ +#define DSUCRU_GATE_CON00_OFFSET (0x800U) +#define DSUCRU_GATE_CON00_SCLK_DSU_DF_SRC_EN_SHIFT (0U) +#define DSUCRU_GATE_CON00_SCLK_DSU_DF_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_DF_SRC_EN_SHIFT) /* 0x00000001 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_DF_DIV2_SRC_EN_SHIFT (1U) +#define DSUCRU_GATE_CON00_SCLK_DSU_DF_DIV2_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_DF_DIV2_SRC_EN_SHIFT) /* 0x00000002 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_NP5_SRC_EN_SHIFT (2U) +#define DSUCRU_GATE_CON00_SCLK_DSU_NP5_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_NP5_SRC_EN_SHIFT) /* 0x00000004 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_NP5_DIV2_SRC_EN_SHIFT (3U) +#define DSUCRU_GATE_CON00_SCLK_DSU_NP5_DIV2_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_NP5_DIV2_SRC_EN_SHIFT) /* 0x00000008 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_SRC_EN_SHIFT (4U) +#define DSUCRU_GATE_CON00_SCLK_DSU_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_SRC_EN_SHIFT) /* 0x00000010 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_SRC_T_EN_SHIFT (5U) +#define DSUCRU_GATE_CON00_SCLK_DSU_SRC_T_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_SRC_T_EN_SHIFT) /* 0x00000020 */ +#define DSUCRU_GATE_CON00_SCLK_DSU_EN_SHIFT (6U) +#define DSUCRU_GATE_CON00_SCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_SCLK_DSU_EN_SHIFT) /* 0x00000040 */ +#define DSUCRU_GATE_CON00_ACLKM_DSU_EN_SHIFT (8U) +#define DSUCRU_GATE_CON00_ACLKM_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_ACLKM_DSU_EN_SHIFT) /* 0x00000100 */ +#define DSUCRU_GATE_CON00_ACLKS_DSU_EN_SHIFT (9U) +#define DSUCRU_GATE_CON00_ACLKS_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_ACLKS_DSU_EN_SHIFT) /* 0x00000200 */ +#define DSUCRU_GATE_CON00_ACLK_M_DSU_BIU_EN_SHIFT (10U) +#define DSUCRU_GATE_CON00_ACLK_M_DSU_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON00_ACLK_M_DSU_BIU_EN_SHIFT) /* 0x00000400 */ +#define DSUCRU_GATE_CON00_ACLK_S_DSU_BIU_EN_SHIFT (11U) +#define DSUCRU_GATE_CON00_ACLK_S_DSU_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON00_ACLK_S_DSU_BIU_EN_SHIFT) /* 0x00000800 */ +#define DSUCRU_GATE_CON00_ACLK_MP_DSU_EN_SHIFT (12U) +#define DSUCRU_GATE_CON00_ACLK_MP_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_ACLK_MP_DSU_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_GATE_CON00_PERIPHCLK_DSU_EN_SHIFT (13U) +#define DSUCRU_GATE_CON00_PERIPHCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_PERIPHCLK_DSU_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_GATE_CON00_CNTCLK_DSU_EN_SHIFT (14U) +#define DSUCRU_GATE_CON00_CNTCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_CNTCLK_DSU_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_GATE_CON00_TSCLK_DSU_EN_SHIFT (15U) +#define DSUCRU_GATE_CON00_TSCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON00_TSCLK_DSU_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON01 */ +#define DSUCRU_GATE_CON01_OFFSET (0x804U) +#define DSUCRU_GATE_CON01_ATCLK_DSU_EN_SHIFT (0U) +#define DSUCRU_GATE_CON01_ATCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON01_ATCLK_DSU_EN_SHIFT) /* 0x00000001 */ +#define DSUCRU_GATE_CON01_GICCLK_DSU_T_EN_SHIFT (1U) +#define DSUCRU_GATE_CON01_GICCLK_DSU_T_EN_MASK (0x1U << DSUCRU_GATE_CON01_GICCLK_DSU_T_EN_SHIFT) /* 0x00000002 */ +#define DSUCRU_GATE_CON01_ACLK_ADB_DSU_EN_SHIFT (2U) +#define DSUCRU_GATE_CON01_ACLK_ADB_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON01_ACLK_ADB_DSU_EN_SHIFT) /* 0x00000004 */ +#define DSUCRU_GATE_CON01_PCLK_DSU_ROOT_EN_SHIFT (3U) +#define DSUCRU_GATE_CON01_PCLK_DSU_ROOT_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DSU_ROOT_EN_SHIFT) /* 0x00000008 */ +#define DSUCRU_GATE_CON01_PCLK_DSU_NS_ROOT_EN_SHIFT (4U) +#define DSUCRU_GATE_CON01_PCLK_DSU_NS_ROOT_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DSU_NS_ROOT_EN_SHIFT) /* 0x00000010 */ +#define DSUCRU_GATE_CON01_PCLK_DSU_BIU_EN_SHIFT (5U) +#define DSUCRU_GATE_CON01_PCLK_DSU_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DSU_BIU_EN_SHIFT) /* 0x00000020 */ +#define DSUCRU_GATE_CON01_PCLK_DSU_EN_SHIFT (6U) +#define DSUCRU_GATE_CON01_PCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DSU_EN_SHIFT) /* 0x00000040 */ +#define DSUCRU_GATE_CON01_PCLK_DBG_EN_SHIFT (7U) +#define DSUCRU_GATE_CON01_PCLK_DBG_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DBG_EN_SHIFT) /* 0x00000080 */ +#define DSUCRU_GATE_CON01_PCLK_S_DAPLITE_EN_SHIFT (8U) +#define DSUCRU_GATE_CON01_PCLK_S_DAPLITE_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_S_DAPLITE_EN_SHIFT) /* 0x00000100 */ +#define DSUCRU_GATE_CON01_PCLK_M_DAPLITE_EN_SHIFT (9U) +#define DSUCRU_GATE_CON01_PCLK_M_DAPLITE_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_M_DAPLITE_EN_SHIFT) /* 0x00000200 */ +#define DSUCRU_GATE_CON01_PCLK_M_DAPLITE_BIU_EN_SHIFT (10U) +#define DSUCRU_GATE_CON01_PCLK_M_DAPLITE_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_M_DAPLITE_BIU_EN_SHIFT) /* 0x00000400 */ +#define DSUCRU_GATE_CON01_PCLK_DSU_GRF_EN_SHIFT (11U) +#define DSUCRU_GATE_CON01_PCLK_DSU_GRF_EN_MASK (0x1U << DSUCRU_GATE_CON01_PCLK_DSU_GRF_EN_SHIFT) /* 0x00000800 */ +#define DSUCRU_GATE_CON01_REFCLK_LITCORE_PVTPLL_EN_SHIFT (14U) +#define DSUCRU_GATE_CON01_REFCLK_LITCORE_PVTPLL_EN_MASK (0x1U << DSUCRU_GATE_CON01_REFCLK_LITCORE_PVTPLL_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_GATE_CON01_REFCLK_DSU_PVTPLL_EN_SHIFT (15U) +#define DSUCRU_GATE_CON01_REFCLK_DSU_PVTPLL_EN_MASK (0x1U << DSUCRU_GATE_CON01_REFCLK_DSU_PVTPLL_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON02 */ +#define DSUCRU_GATE_CON02_OFFSET (0x808U) +#define DSUCRU_GATE_CON02_CLK_LITCORE_PVTM_EN_SHIFT (0U) +#define DSUCRU_GATE_CON02_CLK_LITCORE_PVTM_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_LITCORE_PVTM_EN_SHIFT) /* 0x00000001 */ +#define DSUCRU_GATE_CON02_CLK_CORE_LITCORE_PVTM_EN_SHIFT (1U) +#define DSUCRU_GATE_CON02_CLK_CORE_LITCORE_PVTM_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_LITCORE_PVTM_EN_SHIFT) /* 0x00000002 */ +#define DSUCRU_GATE_CON02_PCLK_DSU_S_ROOT_EN_SHIFT (2U) +#define DSUCRU_GATE_CON02_PCLK_DSU_S_ROOT_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_DSU_S_ROOT_EN_SHIFT) /* 0x00000004 */ +#define DSUCRU_GATE_CON02_PCLK_DSU_S_BIU_EN_SHIFT (3U) +#define DSUCRU_GATE_CON02_PCLK_DSU_S_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_DSU_S_BIU_EN_SHIFT) /* 0x00000008 */ +#define DSUCRU_GATE_CON02_PCLK_DSU_SGRF_EN_SHIFT (4U) +#define DSUCRU_GATE_CON02_PCLK_DSU_SGRF_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_DSU_SGRF_EN_SHIFT) /* 0x00000010 */ +#define DSUCRU_GATE_CON02_CLK_TESTOUT_L_EN_SHIFT (5U) +#define DSUCRU_GATE_CON02_CLK_TESTOUT_L_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_TESTOUT_L_EN_SHIFT) /* 0x00000020 */ +#define DSUCRU_GATE_CON02_PCLK_LITCORE_PVTM_EN_SHIFT (6U) +#define DSUCRU_GATE_CON02_PCLK_LITCORE_PVTM_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_LITCORE_PVTM_EN_SHIFT) /* 0x00000040 */ +#define DSUCRU_GATE_CON02_PCLK_LITCORE_GRF_EN_SHIFT (7U) +#define DSUCRU_GATE_CON02_PCLK_LITCORE_GRF_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_LITCORE_GRF_EN_SHIFT) /* 0x00000080 */ +#define DSUCRU_GATE_CON02_PCLK_DSU_CRU_EN_SHIFT (8U) +#define DSUCRU_GATE_CON02_PCLK_DSU_CRU_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_DSU_CRU_EN_SHIFT) /* 0x00000100 */ +#define DSUCRU_GATE_CON02_PCLK_LITCORE_CPUBOOST_EN_SHIFT (9U) +#define DSUCRU_GATE_CON02_PCLK_LITCORE_CPUBOOST_EN_MASK (0x1U << DSUCRU_GATE_CON02_PCLK_LITCORE_CPUBOOST_EN_SHIFT) /* 0x00000200 */ +#define DSUCRU_GATE_CON02_CLK_24M_LITCORE_CPUBOOST_EN_SHIFT (10U) +#define DSUCRU_GATE_CON02_CLK_24M_LITCORE_CPUBOOST_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_24M_LITCORE_CPUBOOST_EN_SHIFT) /* 0x00000400 */ +#define DSUCRU_GATE_CON02_CLK_CORE_L0_CLEAN_EN_SHIFT (11U) +#define DSUCRU_GATE_CON02_CLK_CORE_L0_CLEAN_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_L0_CLEAN_EN_SHIFT) /* 0x00000800 */ +#define DSUCRU_GATE_CON02_CLK_CORE_L1_CLEAN_EN_SHIFT (12U) +#define DSUCRU_GATE_CON02_CLK_CORE_L1_CLEAN_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_L1_CLEAN_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_GATE_CON02_CLK_CORE_L2_CLEAN_EN_SHIFT (13U) +#define DSUCRU_GATE_CON02_CLK_CORE_L2_CLEAN_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_L2_CLEAN_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_GATE_CON02_CLK_CORE_L3_CLEAN_EN_SHIFT (14U) +#define DSUCRU_GATE_CON02_CLK_CORE_L3_CLEAN_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_L3_CLEAN_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_GATE_CON02_CLK_CORE_L_DIV2_SRC_EN_SHIFT (15U) +#define DSUCRU_GATE_CON02_CLK_CORE_L_DIV2_SRC_EN_MASK (0x1U << DSUCRU_GATE_CON02_CLK_CORE_L_DIV2_SRC_EN_SHIFT) /* 0x00008000 */ +/* GATE_CON03 */ +#define DSUCRU_GATE_CON03_OFFSET (0x80CU) +#define DSUCRU_GATE_CON03_CLK_CORE_L_EN_SHIFT (0U) +#define DSUCRU_GATE_CON03_CLK_CORE_L_EN_MASK (0x1U << DSUCRU_GATE_CON03_CLK_CORE_L_EN_SHIFT) /* 0x00000001 */ +#define DSUCRU_GATE_CON03_CLK_CORE_L0_UC_EN_SHIFT (1U) +#define DSUCRU_GATE_CON03_CLK_CORE_L0_UC_EN_MASK (0x1U << DSUCRU_GATE_CON03_CLK_CORE_L0_UC_EN_SHIFT) /* 0x00000002 */ +#define DSUCRU_GATE_CON03_CLK_CORE_L1_UC_EN_SHIFT (4U) +#define DSUCRU_GATE_CON03_CLK_CORE_L1_UC_EN_MASK (0x1U << DSUCRU_GATE_CON03_CLK_CORE_L1_UC_EN_SHIFT) /* 0x00000010 */ +#define DSUCRU_GATE_CON03_CLK_CORE_L2_UC_EN_SHIFT (7U) +#define DSUCRU_GATE_CON03_CLK_CORE_L2_UC_EN_MASK (0x1U << DSUCRU_GATE_CON03_CLK_CORE_L2_UC_EN_SHIFT) /* 0x00000080 */ +#define DSUCRU_GATE_CON03_CLK_CORE_L3_UC_EN_SHIFT (10U) +#define DSUCRU_GATE_CON03_CLK_CORE_L3_UC_EN_MASK (0x1U << DSUCRU_GATE_CON03_CLK_CORE_L3_UC_EN_SHIFT) /* 0x00000400 */ +#define DSUCRU_GATE_CON03_ACLK_MP_DSU_BIU_EN_SHIFT (13U) +#define DSUCRU_GATE_CON03_ACLK_MP_DSU_BIU_EN_MASK (0x1U << DSUCRU_GATE_CON03_ACLK_MP_DSU_BIU_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_GATE_CON03_GICCLK_DSU_EN_SHIFT (14U) +#define DSUCRU_GATE_CON03_GICCLK_DSU_EN_MASK (0x1U << DSUCRU_GATE_CON03_GICCLK_DSU_EN_SHIFT) /* 0x00004000 */ +/* SOFTRST_CON00 */ +#define DSUCRU_SOFTRST_CON00_OFFSET (0xA00U) +#define DSUCRU_SOFTRST_CON00_NSPORESET_DSU_SHIFT (6U) +#define DSUCRU_SOFTRST_CON00_NSPORESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON00_NSPORESET_DSU_SHIFT) /* 0x00000040 */ +#define DSUCRU_SOFTRST_CON00_NSRESET_DSU_SHIFT (7U) +#define DSUCRU_SOFTRST_CON00_NSRESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON00_NSRESET_DSU_SHIFT) /* 0x00000080 */ +#define DSUCRU_SOFTRST_CON00_ARESETN_M_DSU_BIU_SHIFT (10U) +#define DSUCRU_SOFTRST_CON00_ARESETN_M_DSU_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON00_ARESETN_M_DSU_BIU_SHIFT) /* 0x00000400 */ +#define DSUCRU_SOFTRST_CON00_ARESETN_S_DSU_BIU_SHIFT (11U) +#define DSUCRU_SOFTRST_CON00_ARESETN_S_DSU_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON00_ARESETN_S_DSU_BIU_SHIFT) /* 0x00000800 */ +#define DSUCRU_SOFTRST_CON00_NPERIPHRESET_DSU_SHIFT (13U) +#define DSUCRU_SOFTRST_CON00_NPERIPHRESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON00_NPERIPHRESET_DSU_SHIFT) /* 0x00002000 */ +/* SOFTRST_CON01 */ +#define DSUCRU_SOFTRST_CON01_OFFSET (0xA04U) +#define DSUCRU_SOFTRST_CON01_NATRESET_DSU_SHIFT (0U) +#define DSUCRU_SOFTRST_CON01_NATRESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON01_NATRESET_DSU_SHIFT) /* 0x00000001 */ +#define DSUCRU_SOFTRST_CON01_ARESETN_ADB_DSU_SHIFT (2U) +#define DSUCRU_SOFTRST_CON01_ARESETN_ADB_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON01_ARESETN_ADB_DSU_SHIFT) /* 0x00000004 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_DSU_BIU_SHIFT (5U) +#define DSUCRU_SOFTRST_CON01_PRESETN_DSU_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_DSU_BIU_SHIFT) /* 0x00000020 */ +#define DSUCRU_SOFTRST_CON01_NPRESET_DSU_SHIFT (6U) +#define DSUCRU_SOFTRST_CON01_NPRESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON01_NPRESET_DSU_SHIFT) /* 0x00000040 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_DBG_SHIFT (7U) +#define DSUCRU_SOFTRST_CON01_PRESETN_DBG_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_DBG_SHIFT) /* 0x00000080 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_S_DAPLITE_SHIFT (8U) +#define DSUCRU_SOFTRST_CON01_PRESETN_S_DAPLITE_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_S_DAPLITE_SHIFT) /* 0x00000100 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_SHIFT (9U) +#define DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_SHIFT) /* 0x00000200 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_BIU_SHIFT (10U) +#define DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_M_DAPLITE_BIU_SHIFT) /* 0x00000400 */ +#define DSUCRU_SOFTRST_CON01_PRESETN_DSU_GRF_SHIFT (11U) +#define DSUCRU_SOFTRST_CON01_PRESETN_DSU_GRF_MASK (0x1U << DSUCRU_SOFTRST_CON01_PRESETN_DSU_GRF_SHIFT) /* 0x00000800 */ +#define DSUCRU_SOFTRST_CON01_PORESETN_JTAG_SHIFT (12U) +#define DSUCRU_SOFTRST_CON01_PORESETN_JTAG_MASK (0x1U << DSUCRU_SOFTRST_CON01_PORESETN_JTAG_SHIFT) /* 0x00001000 */ +#define DSUCRU_SOFTRST_CON01_NTRESET_JTAG_SHIFT (13U) +#define DSUCRU_SOFTRST_CON01_NTRESET_JTAG_MASK (0x1U << DSUCRU_SOFTRST_CON01_NTRESET_JTAG_SHIFT) /* 0x00002000 */ +#define DSUCRU_SOFTRST_CON01_RESETN_LITCORE_PVTPLL_SHIFT (14U) +#define DSUCRU_SOFTRST_CON01_RESETN_LITCORE_PVTPLL_MASK (0x1U << DSUCRU_SOFTRST_CON01_RESETN_LITCORE_PVTPLL_SHIFT) /* 0x00004000 */ +#define DSUCRU_SOFTRST_CON01_RESETN_DSU_PVTPLL_SHIFT (15U) +#define DSUCRU_SOFTRST_CON01_RESETN_DSU_PVTPLL_MASK (0x1U << DSUCRU_SOFTRST_CON01_RESETN_DSU_PVTPLL_SHIFT) /* 0x00008000 */ +/* SOFTRST_CON02 */ +#define DSUCRU_SOFTRST_CON02_OFFSET (0xA08U) +#define DSUCRU_SOFTRST_CON02_RESETN_LITCORE_PVTM_SHIFT (0U) +#define DSUCRU_SOFTRST_CON02_RESETN_LITCORE_PVTM_MASK (0x1U << DSUCRU_SOFTRST_CON02_RESETN_LITCORE_PVTM_SHIFT) /* 0x00000001 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_S_BIU_SHIFT (3U) +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_S_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_DSU_S_BIU_SHIFT) /* 0x00000008 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_SGRF_SHIFT (4U) +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_SGRF_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_DSU_SGRF_SHIFT) /* 0x00000010 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_PVTM_SHIFT (6U) +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_PVTM_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_PVTM_SHIFT) /* 0x00000040 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_GRF_SHIFT (7U) +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_GRF_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_GRF_SHIFT) /* 0x00000080 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_CRU_SHIFT (8U) +#define DSUCRU_SOFTRST_CON02_PRESETN_DSU_CRU_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_DSU_CRU_SHIFT) /* 0x00000100 */ +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_CPUBOOST_SHIFT (9U) +#define DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_CPUBOOST_MASK (0x1U << DSUCRU_SOFTRST_CON02_PRESETN_LITCORE_CPUBOOST_SHIFT) /* 0x00000200 */ +#define DSUCRU_SOFTRST_CON02_RESETN_24M_LITCORE_CPUBOOST_SHIFT (10U) +#define DSUCRU_SOFTRST_CON02_RESETN_24M_LITCORE_CPUBOOST_MASK (0x1U << DSUCRU_SOFTRST_CON02_RESETN_24M_LITCORE_CPUBOOST_SHIFT) /* 0x00000400 */ +/* SOFTRST_CON03 */ +#define DSUCRU_SOFTRST_CON03_OFFSET (0xA0CU) +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L0_SHIFT (2U) +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L0_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCPUPORESET_L0_SHIFT) /* 0x00000004 */ +#define DSUCRU_SOFTRST_CON03_NCORERESET_L0_SHIFT (3U) +#define DSUCRU_SOFTRST_CON03_NCORERESET_L0_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCORERESET_L0_SHIFT) /* 0x00000008 */ +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L1_SHIFT (5U) +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L1_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCPUPORESET_L1_SHIFT) /* 0x00000020 */ +#define DSUCRU_SOFTRST_CON03_NCORERESET_L1_SHIFT (6U) +#define DSUCRU_SOFTRST_CON03_NCORERESET_L1_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCORERESET_L1_SHIFT) /* 0x00000040 */ +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L2_SHIFT (8U) +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L2_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCPUPORESET_L2_SHIFT) /* 0x00000100 */ +#define DSUCRU_SOFTRST_CON03_NCORERESET_L2_SHIFT (9U) +#define DSUCRU_SOFTRST_CON03_NCORERESET_L2_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCORERESET_L2_SHIFT) /* 0x00000200 */ +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L3_SHIFT (11U) +#define DSUCRU_SOFTRST_CON03_NCPUPORESET_L3_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCPUPORESET_L3_SHIFT) /* 0x00000800 */ +#define DSUCRU_SOFTRST_CON03_NCORERESET_L3_SHIFT (12U) +#define DSUCRU_SOFTRST_CON03_NCORERESET_L3_MASK (0x1U << DSUCRU_SOFTRST_CON03_NCORERESET_L3_SHIFT) /* 0x00001000 */ +#define DSUCRU_SOFTRST_CON03_ARESETN_MP_DSU_BIU_SHIFT (13U) +#define DSUCRU_SOFTRST_CON03_ARESETN_MP_DSU_BIU_MASK (0x1U << DSUCRU_SOFTRST_CON03_ARESETN_MP_DSU_BIU_SHIFT) /* 0x00002000 */ +#define DSUCRU_SOFTRST_CON03_NGICRESET_DSU_SHIFT (14U) +#define DSUCRU_SOFTRST_CON03_NGICRESET_DSU_MASK (0x1U << DSUCRU_SOFTRST_CON03_NGICRESET_DSU_SHIFT) /* 0x00004000 */ +/* AUTOCS_ACLK_M_DSU_BIU_CON0 */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_OFFSET (0xD00U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_IDLE_TH_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_IDLE_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_WAIT_TH_SHIFT (16U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_WAIT_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON0_ACLK_M_DSU_BIU_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_M_DSU_BIU_CON1 */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_OFFSET (0xD04U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_CTRL_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_CTRL_MASK (0xFFFU << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_EN_SHIFT (12U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_SWITCH_EN_SHIFT (13U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_SWITCH_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_CLKSEL_CFG_SHIFT (14U) +#define DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_CLKSEL_CFG_MASK (0x3U << DSUCRU_AUTOCS_ACLK_M_DSU_BIU_CON1_ACLK_M_DSU_BIU_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_S_DSU_BIU_CON0 */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_OFFSET (0xD08U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_IDLE_TH_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_IDLE_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_WAIT_TH_SHIFT (16U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_WAIT_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON0_ACLK_S_DSU_BIU_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_S_DSU_BIU_CON1 */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_OFFSET (0xD0CU) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_CTRL_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_CTRL_MASK (0xFFFU << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_EN_SHIFT (12U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_SWITCH_EN_SHIFT (13U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_SWITCH_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_CLKSEL_CFG_SHIFT (14U) +#define DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_CLKSEL_CFG_MASK (0x3U << DSUCRU_AUTOCS_ACLK_S_DSU_BIU_CON1_ACLK_S_DSU_BIU_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_ACLK_MP_DSU_BIU_CON0 */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_OFFSET (0xD10U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_IDLE_TH_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_IDLE_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_WAIT_TH_SHIFT (16U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_WAIT_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON0_ACLK_MP_DSU_BIU_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_ACLK_MP_DSU_BIU_CON1 */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_OFFSET (0xD14U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_CTRL_SHIFT (0U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_CTRL_MASK (0xFFFU << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_EN_SHIFT (12U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_SWITCH_EN_SHIFT (13U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_SWITCH_EN_MASK (0x1U << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_CLKSEL_CFG_SHIFT (14U) +#define DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_CLKSEL_CFG_MASK (0x3U << DSUCRU_AUTOCS_ACLK_MP_DSU_BIU_CON1_ACLK_MP_DSU_BIU_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_SCLK_DSU_SRC_CON0 */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_OFFSET (0xD18U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_IDLE_TH_SHIFT (0U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_IDLE_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_WAIT_TH_SHIFT (16U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_WAIT_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON0_SCLK_DSU_SRC_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_SCLK_DSU_SRC_CON1 */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_OFFSET (0xD1CU) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_CTRL_SHIFT (0U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_CTRL_MASK (0xFFFU << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_EN_SHIFT (12U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_EN_MASK (0x1U << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_SWITCH_EN_SHIFT (13U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_SWITCH_EN_MASK (0x1U << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_CLKSEL_CFG_SHIFT (14U) +#define DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_CLKSEL_CFG_MASK (0x3U << DSUCRU_AUTOCS_SCLK_DSU_SRC_CON1_SCLK_DSU_SRC_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* AUTOCS_CLK_CORE_L_CON0 */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON0_OFFSET (0xD20U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_IDLE_TH_SHIFT (0U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_IDLE_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_IDLE_TH_SHIFT) /* 0x0000FFFF */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_WAIT_TH_SHIFT (16U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_WAIT_TH_MASK (0xFFFFU << DSUCRU_AUTOCS_CLK_CORE_L_CON0_CLK_CORE_L_WAIT_TH_SHIFT) /* 0xFFFF0000 */ +/* AUTOCS_CLK_CORE_L_CON1 */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_OFFSET (0xD24U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_CTRL_SHIFT (0U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_CTRL_MASK (0xFFFU << DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_CTRL_SHIFT) /* 0x00000FFF */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_EN_SHIFT (12U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_EN_MASK (0x1U << DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_AUTOCS_EN_SHIFT) /* 0x00001000 */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_SWITCH_EN_SHIFT (13U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_SWITCH_EN_MASK (0x1U << DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_SWITCH_EN_SHIFT) /* 0x00002000 */ +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_CLKSEL_CFG_SHIFT (14U) +#define DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_CLKSEL_CFG_MASK (0x3U << DSUCRU_AUTOCS_CLK_CORE_L_CON1_CLK_CORE_L_CLKSEL_CFG_SHIFT) /* 0x0000C000 */ +/* QCHANNEL_CON00 */ +#define DSUCRU_QCHANNEL_CON00_OFFSET (0xF00U) +#define DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_EN_SHIFT (0U) +#define DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_EN_SHIFT) /* 0x00000001 */ +#define DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_GATE_EN_SHIFT (1U) +#define DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_SCLK_DSU_QC_GATE_EN_SHIFT) /* 0x00000002 */ +#define DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_EN_SHIFT (2U) +#define DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_EN_SHIFT) /* 0x00000004 */ +#define DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_GATE_EN_SHIFT (3U) +#define DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_ATCLK_DSU_QC_GATE_EN_SHIFT) /* 0x00000008 */ +#define DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_EN_SHIFT (4U) +#define DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_EN_SHIFT) /* 0x00000010 */ +#define DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_GATE_EN_SHIFT (5U) +#define DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_GICCLK_DSU_QC_GATE_EN_SHIFT) /* 0x00000020 */ +#define DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_EN_SHIFT (6U) +#define DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_EN_SHIFT) /* 0x00000040 */ +#define DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_GATE_EN_SHIFT (7U) +#define DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_ACLK_ADB_DSU_QC_GATE_EN_SHIFT) /* 0x00000080 */ +#define DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_EN_SHIFT (8U) +#define DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_EN_SHIFT) /* 0x00000100 */ +#define DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_GATE_EN_SHIFT (9U) +#define DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_PCLK_DSU_QC_GATE_EN_SHIFT) /* 0x00000200 */ +#define DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_EN_SHIFT (10U) +#define DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_EN_SHIFT) /* 0x00000400 */ +#define DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_GATE_EN_SHIFT (11U) +#define DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_GATE_EN_MASK (0x1U << DSUCRU_QCHANNEL_CON00_PCLK_DBG_QC_GATE_EN_SHIFT) /* 0x00000800 */ +/* SMOTH_DIVFREE_CON00 */ +#define DSUCRU_SMOTH_DIVFREE_CON00_OFFSET (0xF10U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_STEP_SHIFT (0U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_STEP_MASK (0x1FU << DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_STEP_SHIFT) /* 0x0000001F */ +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_SMDIV_CLK_OFF_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_GATE_SMTH_EN_SHIFT (14U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_GATE_SMTH_EN_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_BYPASS_SHIFT (15U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_BYPASS_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_FREQ_KEEP_SHIFT (16U) +#define DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_FREQ_KEEP_MASK (0xFFFFU << DSUCRU_SMOTH_DIVFREE_CON00_CLK_CORE_L0_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON01 */ +#define DSUCRU_SMOTH_DIVFREE_CON01_OFFSET (0xF14U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_STEP_SHIFT (0U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_STEP_MASK (0x1FU << DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_STEP_SHIFT) /* 0x0000001F */ +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_SMDIV_CLK_OFF_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_GATE_SMTH_EN_SHIFT (14U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_GATE_SMTH_EN_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_BYPASS_SHIFT (15U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_BYPASS_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_FREQ_KEEP_SHIFT (16U) +#define DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_FREQ_KEEP_MASK (0xFFFFU << DSUCRU_SMOTH_DIVFREE_CON01_CLK_CORE_L1_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON02 */ +#define DSUCRU_SMOTH_DIVFREE_CON02_OFFSET (0xF18U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_STEP_SHIFT (0U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_STEP_MASK (0x1FU << DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_STEP_SHIFT) /* 0x0000001F */ +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_SMDIV_CLK_OFF_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_GATE_SMTH_EN_SHIFT (14U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_GATE_SMTH_EN_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_BYPASS_SHIFT (15U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_BYPASS_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_FREQ_KEEP_SHIFT (16U) +#define DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_FREQ_KEEP_MASK (0xFFFFU << DSUCRU_SMOTH_DIVFREE_CON02_CLK_CORE_L2_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/* SMOTH_DIVFREE_CON03 */ +#define DSUCRU_SMOTH_DIVFREE_CON03_OFFSET (0xF1CU) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_STEP_SHIFT (0U) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_STEP_MASK (0x1FU << DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_STEP_SHIFT) /* 0x0000001F */ +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_SMDIV_CLK_OFF_SHIFT (13U) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_SMDIV_CLK_OFF_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_SMDIV_CLK_OFF_SHIFT) /* 0x00002000 */ +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_GATE_SMTH_EN_SHIFT (14U) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_GATE_SMTH_EN_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_GATE_SMTH_EN_SHIFT) /* 0x00004000 */ +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_BYPASS_SHIFT (15U) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_BYPASS_MASK (0x1U << DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_BYPASS_SHIFT) /* 0x00008000 */ +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_FREQ_KEEP_SHIFT (16U) +#define DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_FREQ_KEEP_MASK (0xFFFFU << DSUCRU_SMOTH_DIVFREE_CON03_CLK_CORE_L3_UC_FREQ_KEEP_SHIFT) /* 0xFFFF0000 */ +/******************************************I2C*******************************************/ +/* CON */ +#define I2C_CON_OFFSET (0x0U) +#define I2C_CON_I2C_EN_SHIFT (0U) +#define I2C_CON_I2C_EN_MASK (0x1U << I2C_CON_I2C_EN_SHIFT) /* 0x00000001 */ +#define I2C_CON_I2C_MODE_SHIFT (1U) +#define I2C_CON_I2C_MODE_MASK (0x3U << I2C_CON_I2C_MODE_SHIFT) /* 0x00000006 */ +#define I2C_CON_START_SHIFT (3U) +#define I2C_CON_START_MASK (0x1U << I2C_CON_START_SHIFT) /* 0x00000008 */ +#define I2C_CON_STOP_SHIFT (4U) +#define I2C_CON_STOP_MASK (0x1U << I2C_CON_STOP_SHIFT) /* 0x00000010 */ +#define I2C_CON_ACK_SHIFT (5U) +#define I2C_CON_ACK_MASK (0x1U << I2C_CON_ACK_SHIFT) /* 0x00000020 */ +#define I2C_CON_ACT2NAK_SHIFT (6U) +#define I2C_CON_ACT2NAK_MASK (0x1U << I2C_CON_ACT2NAK_SHIFT) /* 0x00000040 */ +#define I2C_CON_DATA_UPD_ST_SHIFT (8U) +#define I2C_CON_DATA_UPD_ST_MASK (0x7U << I2C_CON_DATA_UPD_ST_SHIFT) /* 0x00000700 */ +#define I2C_CON_START_SETUP_SHIFT (12U) +#define I2C_CON_START_SETUP_MASK (0x3U << I2C_CON_START_SETUP_SHIFT) /* 0x00003000 */ +#define I2C_CON_STOP_SETUP_SHIFT (14U) +#define I2C_CON_STOP_SETUP_MASK (0x3U << I2C_CON_STOP_SETUP_SHIFT) /* 0x0000C000 */ +#define I2C_CON_VERSION_SHIFT (16U) +#define I2C_CON_VERSION_MASK (0xFFFFU << I2C_CON_VERSION_SHIFT) /* 0xFFFF0000 */ +/* CLKDIV */ +#define I2C_CLKDIV_OFFSET (0x4U) +#define I2C_CLKDIV_CLKDIVL_SHIFT (0U) +#define I2C_CLKDIV_CLKDIVL_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVL_SHIFT) /* 0x0000FFFF */ +#define I2C_CLKDIV_CLKDIVH_SHIFT (16U) +#define I2C_CLKDIV_CLKDIVH_MASK (0xFFFFU << I2C_CLKDIV_CLKDIVH_SHIFT) /* 0xFFFF0000 */ +/* MRXADDR */ +#define I2C_MRXADDR_OFFSET (0x8U) +#define I2C_MRXADDR_SADDR_SHIFT (0U) +#define I2C_MRXADDR_SADDR_MASK (0xFFFFFFU << I2C_MRXADDR_SADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXADDR_ADDLVLD_SHIFT (24U) +#define I2C_MRXADDR_ADDLVLD_MASK (0x1U << I2C_MRXADDR_ADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXADDR_ADDMVLD_SHIFT (25U) +#define I2C_MRXADDR_ADDMVLD_MASK (0x1U << I2C_MRXADDR_ADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXADDR_ADDHVLD_SHIFT (26U) +#define I2C_MRXADDR_ADDHVLD_MASK (0x1U << I2C_MRXADDR_ADDHVLD_SHIFT) /* 0x04000000 */ +/* MRXRADDR */ +#define I2C_MRXRADDR_OFFSET (0xCU) +#define I2C_MRXRADDR_SRADDR_SHIFT (0U) +#define I2C_MRXRADDR_SRADDR_MASK (0xFFFFFFU << I2C_MRXRADDR_SRADDR_SHIFT) /* 0x00FFFFFF */ +#define I2C_MRXRADDR_SRADDLVLD_SHIFT (24U) +#define I2C_MRXRADDR_SRADDLVLD_MASK (0x1U << I2C_MRXRADDR_SRADDLVLD_SHIFT) /* 0x01000000 */ +#define I2C_MRXRADDR_SRADDMVLD_SHIFT (25U) +#define I2C_MRXRADDR_SRADDMVLD_MASK (0x1U << I2C_MRXRADDR_SRADDMVLD_SHIFT) /* 0x02000000 */ +#define I2C_MRXRADDR_SRADDHVLD_SHIFT (26U) +#define I2C_MRXRADDR_SRADDHVLD_MASK (0x1U << I2C_MRXRADDR_SRADDHVLD_SHIFT) /* 0x04000000 */ +/* MTXCNT */ +#define I2C_MTXCNT_OFFSET (0x10U) +#define I2C_MTXCNT_MTXCNT_SHIFT (0U) +#define I2C_MTXCNT_MTXCNT_MASK (0x3FU << I2C_MTXCNT_MTXCNT_SHIFT) /* 0x0000003F */ +/* MRXCNT */ +#define I2C_MRXCNT_OFFSET (0x14U) +#define I2C_MRXCNT_MRXCNT_SHIFT (0U) +#define I2C_MRXCNT_MRXCNT_MASK (0x3FU << I2C_MRXCNT_MRXCNT_SHIFT) /* 0x0000003F */ +/* IEN */ +#define I2C_IEN_OFFSET (0x18U) +#define I2C_IEN_BTFIEN_SHIFT (0U) +#define I2C_IEN_BTFIEN_MASK (0x1U << I2C_IEN_BTFIEN_SHIFT) /* 0x00000001 */ +#define I2C_IEN_BRFIEN_SHIFT (1U) +#define I2C_IEN_BRFIEN_MASK (0x1U << I2C_IEN_BRFIEN_SHIFT) /* 0x00000002 */ +#define I2C_IEN_MBTFIEN_SHIFT (2U) +#define I2C_IEN_MBTFIEN_MASK (0x1U << I2C_IEN_MBTFIEN_SHIFT) /* 0x00000004 */ +#define I2C_IEN_MBRFIEN_SHIFT (3U) +#define I2C_IEN_MBRFIEN_MASK (0x1U << I2C_IEN_MBRFIEN_SHIFT) /* 0x00000008 */ +#define I2C_IEN_STARTIEN_SHIFT (4U) +#define I2C_IEN_STARTIEN_MASK (0x1U << I2C_IEN_STARTIEN_SHIFT) /* 0x00000010 */ +#define I2C_IEN_STOPIEN_SHIFT (5U) +#define I2C_IEN_STOPIEN_MASK (0x1U << I2C_IEN_STOPIEN_SHIFT) /* 0x00000020 */ +#define I2C_IEN_NAKRCVIEN_SHIFT (6U) +#define I2C_IEN_NAKRCVIEN_MASK (0x1U << I2C_IEN_NAKRCVIEN_SHIFT) /* 0x00000040 */ +#define I2C_IEN_SLAVEHDSCLEN_SHIFT (7U) +#define I2C_IEN_SLAVEHDSCLEN_MASK (0x1U << I2C_IEN_SLAVEHDSCLEN_SHIFT) /* 0x00000080 */ +/* IPD */ +#define I2C_IPD_OFFSET (0x1CU) +#define I2C_IPD_BTFIPD_SHIFT (0U) +#define I2C_IPD_BTFIPD_MASK (0x1U << I2C_IPD_BTFIPD_SHIFT) /* 0x00000001 */ +#define I2C_IPD_BRFIPD_SHIFT (1U) +#define I2C_IPD_BRFIPD_MASK (0x1U << I2C_IPD_BRFIPD_SHIFT) /* 0x00000002 */ +#define I2C_IPD_MBTFIPD_SHIFT (2U) +#define I2C_IPD_MBTFIPD_MASK (0x1U << I2C_IPD_MBTFIPD_SHIFT) /* 0x00000004 */ +#define I2C_IPD_MBRFIPD_SHIFT (3U) +#define I2C_IPD_MBRFIPD_MASK (0x1U << I2C_IPD_MBRFIPD_SHIFT) /* 0x00000008 */ +#define I2C_IPD_STARTIPD_SHIFT (4U) +#define I2C_IPD_STARTIPD_MASK (0x1U << I2C_IPD_STARTIPD_SHIFT) /* 0x00000010 */ +#define I2C_IPD_STOPIPD_SHIFT (5U) +#define I2C_IPD_STOPIPD_MASK (0x1U << I2C_IPD_STOPIPD_SHIFT) /* 0x00000020 */ +#define I2C_IPD_NAKRCVIPD_SHIFT (6U) +#define I2C_IPD_NAKRCVIPD_MASK (0x1U << I2C_IPD_NAKRCVIPD_SHIFT) /* 0x00000040 */ +#define I2C_IPD_SLAVEHDSCLIPD_SHIFT (7U) +#define I2C_IPD_SLAVEHDSCLIPD_MASK (0x1U << I2C_IPD_SLAVEHDSCLIPD_SHIFT) /* 0x00000080 */ +/* FCNT */ +#define I2C_FCNT_OFFSET (0x20U) +#define I2C_FCNT (0x0U) +#define I2C_FCNT_FCNT_SHIFT (0U) +#define I2C_FCNT_FCNT_MASK (0x3FU << I2C_FCNT_FCNT_SHIFT) /* 0x0000003F */ +/* SCL_OE_DB */ +#define I2C_SCL_OE_DB_OFFSET (0x24U) +#define I2C_SCL_OE_DB_SCL_OE_DB_SHIFT (0U) +#define I2C_SCL_OE_DB_SCL_OE_DB_MASK (0xFFU << I2C_SCL_OE_DB_SCL_OE_DB_SHIFT) /* 0x000000FF */ +/* TXDATA0 */ +#define I2C_TXDATA0_OFFSET (0x100U) +#define I2C_TXDATA0_TXDATA0_SHIFT (0U) +#define I2C_TXDATA0_TXDATA0_MASK (0xFFFFFFFFU << I2C_TXDATA0_TXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA1 */ +#define I2C_TXDATA1_OFFSET (0x104U) +#define I2C_TXDATA1_TXDATA1_SHIFT (0U) +#define I2C_TXDATA1_TXDATA1_MASK (0xFFFFFFFFU << I2C_TXDATA1_TXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA2 */ +#define I2C_TXDATA2_OFFSET (0x108U) +#define I2C_TXDATA2_TXDATA2_SHIFT (0U) +#define I2C_TXDATA2_TXDATA2_MASK (0xFFFFFFFFU << I2C_TXDATA2_TXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA3 */ +#define I2C_TXDATA3_OFFSET (0x10CU) +#define I2C_TXDATA3_TXDATA3_SHIFT (0U) +#define I2C_TXDATA3_TXDATA3_MASK (0xFFFFFFFFU << I2C_TXDATA3_TXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA4 */ +#define I2C_TXDATA4_OFFSET (0x110U) +#define I2C_TXDATA4_TXDATA4_SHIFT (0U) +#define I2C_TXDATA4_TXDATA4_MASK (0xFFFFFFFFU << I2C_TXDATA4_TXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA5 */ +#define I2C_TXDATA5_OFFSET (0x114U) +#define I2C_TXDATA5_TXDATA5_SHIFT (0U) +#define I2C_TXDATA5_TXDATA5_MASK (0xFFFFFFFFU << I2C_TXDATA5_TXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA6 */ +#define I2C_TXDATA6_OFFSET (0x118U) +#define I2C_TXDATA6_TXDATA6_SHIFT (0U) +#define I2C_TXDATA6_TXDATA6_MASK (0xFFFFFFFFU << I2C_TXDATA6_TXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA7 */ +#define I2C_TXDATA7_OFFSET (0x11CU) +#define I2C_TXDATA7_TXDATA7_SHIFT (0U) +#define I2C_TXDATA7_TXDATA7_MASK (0xFFFFFFFFU << I2C_TXDATA7_TXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA0 */ +#define I2C_RXDATA0_OFFSET (0x200U) +#define I2C_RXDATA0 (0x0U) +#define I2C_RXDATA0_RXDATA0_SHIFT (0U) +#define I2C_RXDATA0_RXDATA0_MASK (0xFFFFFFFFU << I2C_RXDATA0_RXDATA0_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA1 */ +#define I2C_RXDATA1_OFFSET (0x204U) +#define I2C_RXDATA1 (0x0U) +#define I2C_RXDATA1_RXDATA1_SHIFT (0U) +#define I2C_RXDATA1_RXDATA1_MASK (0xFFFFFFFFU << I2C_RXDATA1_RXDATA1_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA2 */ +#define I2C_RXDATA2_OFFSET (0x208U) +#define I2C_RXDATA2 (0x0U) +#define I2C_RXDATA2_RXDATA2_SHIFT (0U) +#define I2C_RXDATA2_RXDATA2_MASK (0xFFFFFFFFU << I2C_RXDATA2_RXDATA2_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA3 */ +#define I2C_RXDATA3_OFFSET (0x20CU) +#define I2C_RXDATA3 (0x0U) +#define I2C_RXDATA3_RXDATA3_SHIFT (0U) +#define I2C_RXDATA3_RXDATA3_MASK (0xFFFFFFFFU << I2C_RXDATA3_RXDATA3_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA4 */ +#define I2C_RXDATA4_OFFSET (0x210U) +#define I2C_RXDATA4 (0x0U) +#define I2C_RXDATA4_RXDATA4_SHIFT (0U) +#define I2C_RXDATA4_RXDATA4_MASK (0xFFFFFFFFU << I2C_RXDATA4_RXDATA4_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA5 */ +#define I2C_RXDATA5_OFFSET (0x214U) +#define I2C_RXDATA5 (0x0U) +#define I2C_RXDATA5_RXDATA5_SHIFT (0U) +#define I2C_RXDATA5_RXDATA5_MASK (0xFFFFFFFFU << I2C_RXDATA5_RXDATA5_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA6 */ +#define I2C_RXDATA6_OFFSET (0x218U) +#define I2C_RXDATA6 (0x0U) +#define I2C_RXDATA6_RXDATA6_SHIFT (0U) +#define I2C_RXDATA6_RXDATA6_MASK (0xFFFFFFFFU << I2C_RXDATA6_RXDATA6_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA7 */ +#define I2C_RXDATA7_OFFSET (0x21CU) +#define I2C_RXDATA7 (0x0U) +#define I2C_RXDATA7_RXDATA7_SHIFT (0U) +#define I2C_RXDATA7_RXDATA7_MASK (0xFFFFFFFFU << I2C_RXDATA7_RXDATA7_SHIFT) /* 0xFFFFFFFF */ +/* ST */ +#define I2C_ST_OFFSET (0x220U) +#define I2C_ST (0x0U) +#define I2C_ST_SDA_ST_SHIFT (0U) +#define I2C_ST_SDA_ST_MASK (0x1U << I2C_ST_SDA_ST_SHIFT) /* 0x00000001 */ +#define I2C_ST_SCL_ST_SHIFT (1U) +#define I2C_ST_SCL_ST_MASK (0x1U << I2C_ST_SCL_ST_SHIFT) /* 0x00000002 */ +/* DBGCTRL */ +#define I2C_DBGCTRL_OFFSET (0x224U) +#define I2C_DBGCTRL_FLT_F_SHIFT (0U) +#define I2C_DBGCTRL_FLT_F_MASK (0xFU << I2C_DBGCTRL_FLT_F_SHIFT) /* 0x0000000F */ +#define I2C_DBGCTRL_FLT_R_SHIFT (4U) +#define I2C_DBGCTRL_FLT_R_MASK (0xFU << I2C_DBGCTRL_FLT_R_SHIFT) /* 0x000000F0 */ +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT (8U) +#define I2C_DBGCTRL_SLV_HOLD_SCL_TH_MASK (0xFU << I2C_DBGCTRL_SLV_HOLD_SCL_TH_SHIFT) /* 0x00000F00 */ +#define I2C_DBGCTRL_FLT_EN_SHIFT (12U) +#define I2C_DBGCTRL_FLT_EN_MASK (0x1U << I2C_DBGCTRL_FLT_EN_SHIFT) /* 0x00001000 */ +#define I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT (13U) +#define I2C_DBGCTRL_NAK_RELEASE_SCL_MASK (0x1U << I2C_DBGCTRL_NAK_RELEASE_SCL_SHIFT) /* 0x00002000 */ +#define I2C_DBGCTRL_H0_CHECK_SCL_SHIFT (14U) +#define I2C_DBGCTRL_H0_CHECK_SCL_MASK (0x1U << I2C_DBGCTRL_H0_CHECK_SCL_SHIFT) /* 0x00004000 */ +/* CON1 */ +#define I2C_CON1_OFFSET (0x228U) +#define I2C_CON1_AUTO_STOP_SHIFT (0U) +#define I2C_CON1_AUTO_STOP_MASK (0x1U << I2C_CON1_AUTO_STOP_SHIFT) /* 0x00000001 */ +#define I2C_CON1_AUTO_STOP_TX_END_SHIFT (1U) +#define I2C_CON1_AUTO_STOP_TX_END_MASK (0x1U << I2C_CON1_AUTO_STOP_TX_END_SHIFT) /* 0x00000002 */ +#define I2C_CON1_AUTO_STOP_NAK_SHIFT (2U) +#define I2C_CON1_AUTO_STOP_NAK_MASK (0x1U << I2C_CON1_AUTO_STOP_NAK_SHIFT) /* 0x00000004 */ +/******************************************UART******************************************/ +/* RBR */ +#define UART_RBR_OFFSET (0x0U) +#define UART_RBR (0x0U) +#define UART_RBR_DATA_INPUT_SHIFT (0U) +#define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) /* 0x000000FF */ +/* DLL */ +#define UART_DLL_OFFSET (0x0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) /* 0x000000FF */ +/* THR */ +#define UART_THR_OFFSET (0x0U) +#define UART_THR_DATA_OUTPUT_SHIFT (0U) +#define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) /* 0x000000FF */ +/* DLH */ +#define UART_DLH_OFFSET (0x4U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) /* 0x000000FF */ +/* IER */ +#define UART_IER_OFFSET (0x4U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) /* 0x00000001 */ +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U) +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) /* 0x00000002 */ +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U) +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) /* 0x00000004 */ +#define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U) +#define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) /* 0x00000008 */ +#define UART_IER_PROG_THRE_INT_EN_SHIFT (7U) +#define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) /* 0x00000080 */ +/* FCR */ +#define UART_FCR_OFFSET (0x8U) +#define UART_FCR_FIFO_EN_SHIFT (0U) +#define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) /* 0x00000001 */ +#define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +#define UART_FCR_DMA_MODE_SHIFT (3U) +#define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) /* 0x00000008 */ +#define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U) +#define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000030 */ +#define UART_FCR_RCVR_TRIGGER_SHIFT (6U) +#define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) /* 0x000000C0 */ +/* IIR */ +#define UART_IIR_OFFSET (0x8U) +#define UART_IIR (0x1U) +#define UART_IIR_INT_ID_SHIFT (0U) +#define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) /* 0x0000000F */ +#define UART_IIR_FIFOS_EN_SHIFT (6U) +#define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) /* 0x000000C0 */ +/* LCR */ +#define UART_LCR_OFFSET (0xCU) +#define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U) +#define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) /* 0x00000003 */ +#define UART_LCR_STOP_BITS_NUM_SHIFT (2U) +#define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) /* 0x00000004 */ +#define UART_LCR_PARITY_EN_SHIFT (3U) +#define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) /* 0x00000008 */ +#define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U) +#define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) /* 0x00000010 */ +#define UART_LCR_BREAK_CTRL_SHIFT (6U) +#define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) /* 0x00000040 */ +#define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U) +#define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) /* 0x00000080 */ +/* MCR */ +#define UART_MCR_OFFSET (0x10U) +#define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U) +#define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) /* 0x00000001 */ +#define UART_MCR_REQ_TO_SEND_SHIFT (1U) +#define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) /* 0x00000002 */ +#define UART_MCR_OUT1_SHIFT (2U) +#define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) /* 0x00000004 */ +#define UART_MCR_OUT2_SHIFT (3U) +#define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) /* 0x00000008 */ +#define UART_MCR_LOOPBACK_SHIFT (4U) +#define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) /* 0x00000010 */ +#define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U) +#define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) /* 0x00000020 */ +#define UART_MCR_SIR_MODE_EN_SHIFT (6U) +#define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) /* 0x00000040 */ +/* LSR */ +#define UART_LSR_OFFSET (0x14U) +#define UART_LSR (0x60U) +#define UART_LSR_DATA_READY_SHIFT (0U) +#define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) /* 0x00000001 */ +#define UART_LSR_OVERRUN_ERROR_SHIFT (1U) +#define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) /* 0x00000002 */ +#define UART_LSR_PARITY_EROR_SHIFT (2U) +#define UART_LSR_PARITY_EROR_MASK (0x1U << UART_LSR_PARITY_EROR_SHIFT) /* 0x00000004 */ +#define UART_LSR_FRAMING_ERROR_SHIFT (3U) +#define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) /* 0x00000008 */ +#define UART_LSR_BREAK_INT_SHIFT (4U) +#define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) /* 0x00000010 */ +#define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U) +#define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) /* 0x00000020 */ +#define UART_LSR_TRANS_EMPTY_SHIFT (6U) +#define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) /* 0x00000040 */ +#define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U) +#define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) /* 0x00000080 */ +/* MSR */ +#define UART_MSR_OFFSET (0x18U) +#define UART_MSR (0x0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) /* 0x00000001 */ +#define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U) +#define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) /* 0x00000002 */ +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U) +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) /* 0x00000004 */ +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U) +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) /* 0x00000008 */ +#define UART_MSR_CLEAR_TO_SEND_SHIFT (4U) +#define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) /* 0x00000010 */ +#define UART_MSR_DATA_SET_READY_SHIFT (5U) +#define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) /* 0x00000020 */ +#define UART_MSR_RING_INDICATOR_SHIFT (6U) +#define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) /* 0x00000040 */ +#define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U) +#define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) /* 0x00000080 */ +/* SCR */ +#define UART_SCR_OFFSET (0x1CU) +#define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U) +#define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) /* 0x000000FF */ +/* SRBR */ +#define UART_SRBR_OFFSET (0x30U) +#define UART_SRBR (0x0U) +#define UART_SRBR_SHADOW_RBR_SHIFT (0U) +#define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) /* 0x000000FF */ +/* STHR */ +#define UART_STHR_OFFSET (0x30U) +#define UART_STHR_SHADOW_THR_SHIFT (0U) +#define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) /* 0x000000FF */ +/* FAR */ +#define UART_FAR_OFFSET (0x70U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) /* 0x00000001 */ +/* TFR */ +#define UART_TFR_OFFSET (0x74U) +#define UART_TFR (0x0U) +#define UART_TFR_TRANS_FIFO_READ_SHIFT (0U) +#define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) /* 0x000000FF */ +/* RFW */ +#define UART_RFW_OFFSET (0x78U) +#define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U) +#define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) /* 0x000000FF */ +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U) +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) /* 0x00000100 */ +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U) +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) /* 0x00000200 */ +/* USR */ +#define UART_USR_OFFSET (0x7CU) +#define UART_USR (0x6U) +#define UART_USR_UART_BUSY_SHIFT (0U) +#define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) /* 0x00000001 */ +#define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U) +#define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) /* 0x00000002 */ +#define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U) +#define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U) +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) /* 0x00000008 */ +#define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U) +#define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) /* 0x00000010 */ +/* TFL */ +#define UART_TFL_OFFSET (0x80U) +#define UART_TFL (0x0U) +#define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U) +#define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x3FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* RFL */ +#define UART_RFL_OFFSET (0x84U) +#define UART_RFL (0x0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x3FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* SRR */ +#define UART_SRR_OFFSET (0x88U) +#define UART_SRR_UART_RESET_SHIFT (0U) +#define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) /* 0x00000001 */ +#define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +/* SRTS */ +#define UART_SRTS_OFFSET (0x8CU) +#define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U) +#define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) /* 0x00000001 */ +/* SBCR */ +#define UART_SBCR_OFFSET (0x90U) +#define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U) +#define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) /* 0x00000001 */ +/* SDMAM */ +#define UART_SDMAM_OFFSET (0x94U) +#define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U) +#define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) /* 0x00000001 */ +/* SFE */ +#define UART_SFE_OFFSET (0x98U) +#define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U) +#define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) /* 0x00000001 */ +/* SRT */ +#define UART_SRT_OFFSET (0x9CU) +#define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U) +#define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x3U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) /* 0x00000003 */ +/* STET */ +#define UART_STET_OFFSET (0xA0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x3U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000003 */ +/* HTX */ +#define UART_HTX_OFFSET (0xA4U) +#define UART_HTX_HALT_TX_EN_SHIFT (0U) +#define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) /* 0x00000001 */ +/* DMASA */ +#define UART_DMASA_OFFSET (0xA8U) +#define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U) +#define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) /* 0x00000001 */ +/* CPR */ +#define UART_CPR_OFFSET (0xF4U) +#define UART_CPR (0x0U) +#define UART_CPR_APB_DATA_WIDTH_SHIFT (0U) +#define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) /* 0x00000003 */ +#define UART_CPR_AFCE_MODE_SHIFT (4U) +#define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) /* 0x00000010 */ +#define UART_CPR_THRE_MODE_SHIFT (5U) +#define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) /* 0x00000020 */ +#define UART_CPR_SIR_MODE_SHIFT (6U) +#define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) /* 0x00000040 */ +#define UART_CPR_SIR_LP_MODE_SHIFT (7U) +#define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) /* 0x00000080 */ +#define UART_CPR_NEW_FEAT_SHIFT (8U) +#define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) /* 0x00000100 */ +#define UART_CPR_FIFO_ACCESS_SHIFT (9U) +#define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) /* 0x00000200 */ +#define UART_CPR_FIFO_STAT_SHIFT (10U) +#define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) /* 0x00000400 */ +#define UART_CPR_SHADOW_SHIFT (11U) +#define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) /* 0x00000800 */ +#define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U) +#define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) /* 0x00001000 */ +#define UART_CPR_DMA_EXTRA_SHIFT (13U) +#define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) /* 0x00002000 */ +#define UART_CPR_FIFO_MODE_SHIFT (16U) +#define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) /* 0x00FF0000 */ +/* UCV */ +#define UART_UCV_OFFSET (0xF8U) +#define UART_UCV (0x330372AU) +#define UART_UCV_VER_SHIFT (0U) +#define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) /* 0xFFFFFFFF */ +/* CTR */ +#define UART_CTR_OFFSET (0xFCU) +#define UART_CTR (0x44570110U) +#define UART_CTR_PERIPHERAL_ID_SHIFT (0U) +#define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************GPIO******************************************/ +/* SWPORT_DR_L */ +#define GPIO_SWPORT_DR_L_OFFSET (0x0U) +#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DR_L_SWPORT_DR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DR_L_SWPORT_DR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DR_H */ +#define GPIO_SWPORT_DR_H_OFFSET (0x4U) +#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DR_H_SWPORT_DR_HIGH_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_L */ +#define GPIO_SWPORT_DDR_L_OFFSET (0x8U) +#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT (0U) +#define GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_MASK (0xFFFFU << GPIO_SWPORT_DDR_L_SWPORT_DDR_LOW_SHIFT) /* 0x0000FFFF */ +/* SWPORT_DDR_H */ +#define GPIO_SWPORT_DDR_H_OFFSET (0xCU) +#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT (0U) +#define GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_MASK (0xFFFFU << GPIO_SWPORT_DDR_H_SWPORT_DDR_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_EN_L */ +#define GPIO_INT_EN_L_OFFSET (0x10U) +#define GPIO_INT_EN_L_INT_EN_LOW_SHIFT (0U) +#define GPIO_INT_EN_L_INT_EN_LOW_MASK (0xFFFFU << GPIO_INT_EN_L_INT_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_EN_H */ +#define GPIO_INT_EN_H_OFFSET (0x14U) +#define GPIO_INT_EN_H_INT_EN_HIGH_SHIFT (0U) +#define GPIO_INT_EN_H_INT_EN_HIGH_MASK (0xFFFFU << GPIO_INT_EN_H_INT_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_L */ +#define GPIO_INT_MASK_L_OFFSET (0x18U) +#define GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT (0U) +#define GPIO_INT_MASK_L_INT_MASK_LOW_MASK (0xFFFFU << GPIO_INT_MASK_L_INT_MASK_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_MASK_H */ +#define GPIO_INT_MASK_H_OFFSET (0x1CU) +#define GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT (0U) +#define GPIO_INT_MASK_H_INT_MASK_HIGH_MASK (0xFFFFU << GPIO_INT_MASK_H_INT_MASK_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_L */ +#define GPIO_INT_TYPE_L_OFFSET (0x20U) +#define GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT (0U) +#define GPIO_INT_TYPE_L_INT_TYPE_LOW_MASK (0xFFFFU << GPIO_INT_TYPE_L_INT_TYPE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_TYPE_H */ +#define GPIO_INT_TYPE_H_OFFSET (0x24U) +#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT (0U) +#define GPIO_INT_TYPE_H_INT_TYPE_HIGH_MASK (0xFFFFU << GPIO_INT_TYPE_H_INT_TYPE_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_L */ +#define GPIO_INT_POLARITY_L_OFFSET (0x28U) +#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT (0U) +#define GPIO_INT_POLARITY_L_INT_POLARITY_LOW_MASK (0xFFFFU << GPIO_INT_POLARITY_L_INT_POLARITY_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_POLARITY_H */ +#define GPIO_INT_POLARITY_H_OFFSET (0x2CU) +#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT (0U) +#define GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_MASK (0xFFFFU << GPIO_INT_POLARITY_H_INT_POLARITY_HIGH_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_L */ +#define GPIO_INT_BOTHEDGE_L_OFFSET (0x30U) +#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_L_INT_BOTHEDGE_LOW_SHIFT) /* 0x0000FFFF */ +/* INT_BOTHEDGE_H */ +#define GPIO_INT_BOTHEDGE_H_OFFSET (0x34U) +#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT (0U) +#define GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_MASK (0xFFFFU << GPIO_INT_BOTHEDGE_H_INT_BOTHEDGE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_L */ +#define GPIO_DEBOUNCE_L_OFFSET (0x38U) +#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT (0U) +#define GPIO_DEBOUNCE_L_DEBOUNCE_LOW_MASK (0xFFFFU << GPIO_DEBOUNCE_L_DEBOUNCE_LOW_SHIFT) /* 0x0000FFFF */ +/* DEBOUNCE_H */ +#define GPIO_DEBOUNCE_H_OFFSET (0x3CU) +#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT (0U) +#define GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_MASK (0xFFFFU << GPIO_DEBOUNCE_H_DEBOUNCE_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_L */ +#define GPIO_DBCLK_DIV_EN_L_OFFSET (0x40U) +#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_L_DBCLK_DIV_EN_LOW_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_EN_H */ +#define GPIO_DBCLK_DIV_EN_H_OFFSET (0x44U) +#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT (0U) +#define GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_MASK (0xFFFFU << GPIO_DBCLK_DIV_EN_H_DBCLK_DIV_EN_HIGH_SHIFT) /* 0x0000FFFF */ +/* DBCLK_DIV_CON */ +#define GPIO_DBCLK_DIV_CON_OFFSET (0x48U) +#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT (0U) +#define GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_MASK (0xFFFFFFU << GPIO_DBCLK_DIV_CON_DBCLK_DIV_CON_SHIFT) /* 0x00FFFFFF */ +/* INT_STATUS */ +#define GPIO_INT_STATUS_OFFSET (0x50U) +#define GPIO_INT_STATUS (0x0U) +#define GPIO_INT_STATUS_INT_STATUS_SHIFT (0U) +#define GPIO_INT_STATUS_INT_STATUS_MASK (0xFFFFFFFFU << GPIO_INT_STATUS_INT_STATUS_SHIFT) /* 0xFFFFFFFF */ +/* INT_RAWSTATUS */ +#define GPIO_INT_RAWSTATUS_OFFSET (0x58U) +#define GPIO_INT_RAWSTATUS (0x0U) +#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT (0U) +#define GPIO_INT_RAWSTATUS_INT_RAWSTATUS_MASK (0xFFFFFFFFU << GPIO_INT_RAWSTATUS_INT_RAWSTATUS_SHIFT) /* 0xFFFFFFFF */ +/* PORT_EOI_L */ +#define GPIO_PORT_EOI_L_OFFSET (0x60U) +#define GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT (0U) +#define GPIO_PORT_EOI_L_PORT_EOI_LOW_MASK (0xFFFFU << GPIO_PORT_EOI_L_PORT_EOI_LOW_SHIFT) /* 0x0000FFFF */ +/* PORT_EOI_H */ +#define GPIO_PORT_EOI_H_OFFSET (0x64U) +#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT (0U) +#define GPIO_PORT_EOI_H_PORT_EOI_HIGH_MASK (0xFFFFU << GPIO_PORT_EOI_H_PORT_EOI_HIGH_SHIFT) /* 0x0000FFFF */ +/* EXT_PORT */ +#define GPIO_EXT_PORT_OFFSET (0x70U) +#define GPIO_EXT_PORT (0x0U) +#define GPIO_EXT_PORT_EXT_PORT_SHIFT (0U) +#define GPIO_EXT_PORT_EXT_PORT_MASK (0xFFFFFFFFU << GPIO_EXT_PORT_EXT_PORT_SHIFT) /* 0xFFFFFFFF */ +/* VER_ID */ +#define GPIO_VER_ID_OFFSET (0x78U) +#define GPIO_VER_ID (0x101157CU) +#define GPIO_VER_ID_VER_ID_SHIFT (0U) +#define GPIO_VER_ID_VER_ID_MASK (0xFFFFFFFFU << GPIO_VER_ID_VER_ID_SHIFT) /* 0xFFFFFFFF */ +/* GPIO_REG_GROUP_L */ +#define GPIO_GPIO_REG_GROUP_L_OFFSET (0x100U) +#define GPIO_GPIO_REG_GROUP_L_GPIO_REG_GROUP_LOW_SHIFT (0U) +#define GPIO_GPIO_REG_GROUP_L_GPIO_REG_GROUP_LOW_MASK (0xFFFFU << GPIO_GPIO_REG_GROUP_L_GPIO_REG_GROUP_LOW_SHIFT) /* 0x0000FFFF */ +/* GPIO_REG_GROUP_H */ +#define GPIO_GPIO_REG_GROUP_H_OFFSET (0x104U) +#define GPIO_GPIO_REG_GROUP_H_GPIO_REG_GROUP_HIGH_SHIFT (0U) +#define GPIO_GPIO_REG_GROUP_H_GPIO_REG_GROUP_HIGH_MASK (0xFFFFU << GPIO_GPIO_REG_GROUP_H_GPIO_REG_GROUP_HIGH_SHIFT) /* 0x0000FFFF */ +/* GPIO_VIRTUAL_EN */ +#define GPIO_GPIO_VIRTUAL_EN_OFFSET (0x108U) +#define GPIO_GPIO_VIRTUAL_EN_GPIO_VIRTUAL_EN_SHIFT (0U) +#define GPIO_GPIO_VIRTUAL_EN_GPIO_VIRTUAL_EN_MASK (0x1U << GPIO_GPIO_VIRTUAL_EN_GPIO_VIRTUAL_EN_SHIFT) /* 0x00000001 */ +/******************************************PMU*******************************************/ +/* PWR_CON0 */ +#define PMU_PWR_CON0_OFFSET (0x0U) +#define PMU_PWR_CON0_POWERMODE0_EN_SHIFT (0U) +#define PMU_PWR_CON0_POWERMODE0_EN_MASK (0x1U << PMU_PWR_CON0_POWERMODE0_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CON0_PMU1_PWR_BYPASS_SHIFT (1U) +#define PMU_PWR_CON0_PMU1_PWR_BYPASS_MASK (0x1U << PMU_PWR_CON0_PMU1_PWR_BYPASS_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CON0_PMU1_BUS_BYPASS_SHIFT (2U) +#define PMU_PWR_CON0_PMU1_BUS_BYPASS_MASK (0x1U << PMU_PWR_CON0_PMU1_BUS_BYPASS_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CON0_WAKEUP_BYPASS_SHIFT (3U) +#define PMU_PWR_CON0_WAKEUP_BYPASS_MASK (0x1U << PMU_PWR_CON0_WAKEUP_BYPASS_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CON0_PMIC_BYPASS_SHIFT (4U) +#define PMU_PWR_CON0_PMIC_BYPASS_MASK (0x1U << PMU_PWR_CON0_PMIC_BYPASS_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CON0_RESET_BYPASS_SHIFT (5U) +#define PMU_PWR_CON0_RESET_BYPASS_MASK (0x1U << PMU_PWR_CON0_RESET_BYPASS_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CON0_FREQ_SWITCH_BYPASS_SHIFT (6U) +#define PMU_PWR_CON0_FREQ_SWITCH_BYPASS_MASK (0x1U << PMU_PWR_CON0_FREQ_SWITCH_BYPASS_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CON0_OSC_DIS_BYPASS_SHIFT (7U) +#define PMU_PWR_CON0_OSC_DIS_BYPASS_MASK (0x1U << PMU_PWR_CON0_OSC_DIS_BYPASS_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CON0_PMU1_PWR_GATE_ENA_SHIFT (8U) +#define PMU_PWR_CON0_PMU1_PWR_GATE_ENA_MASK (0x1U << PMU_PWR_CON0_PMU1_PWR_GATE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CON0_PMU1_PWR_GATE_SFTENA_SHIFT (9U) +#define PMU_PWR_CON0_PMU1_PWR_GATE_SFTENA_MASK (0x1U << PMU_PWR_CON0_PMU1_PWR_GATE_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_CON0_PMU1_MEMPWR_GATE_SFTENA_SHIFT (10U) +#define PMU_PWR_CON0_PMU1_MEMPWR_GATE_SFTENA_MASK (0x1U << PMU_PWR_CON0_PMU1_MEMPWR_GATE_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_CON0_PMU1_BUS_IDLE_ENA_SHIFT (11U) +#define PMU_PWR_CON0_PMU1_BUS_IDLE_ENA_MASK (0x1U << PMU_PWR_CON0_PMU1_BUS_IDLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CON0_PMU1_BUS_IDLE_SFTENA_SHIFT (12U) +#define PMU_PWR_CON0_PMU1_BUS_IDLE_SFTENA_MASK (0x1U << PMU_PWR_CON0_PMU1_BUS_IDLE_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CON0_BIU_AUTO_PMU1_SHIFT (13U) +#define PMU_PWR_CON0_BIU_AUTO_PMU1_MASK (0x1U << PMU_PWR_CON0_BIU_AUTO_PMU1_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CON0_POWER_OFF_IO_ENA_SHIFT (14U) +#define PMU_PWR_CON0_POWER_OFF_IO_ENA_MASK (0x1U << PMU_PWR_CON0_POWER_OFF_IO_ENA_SHIFT) /* 0x00004000 */ +/* WAKEUP_INT_CON_P0 */ +#define PMU_WAKEUP_INT_CON_P0_OFFSET (0x8U) +#define PMU_WAKEUP_INT_CON_P0_WAKEUP_INT_EN_SHIFT (0U) +#define PMU_WAKEUP_INT_CON_P0_WAKEUP_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_P0_WAKEUP_INT_EN_SHIFT) /* 0x00000001 */ +/* WAKEUP_INT_STS_P0 */ +#define PMU_WAKEUP_INT_STS_P0_OFFSET (0xCU) +#define PMU_WAKEUP_INT_STS_P0 (0x0U) +#define PMU_WAKEUP_INT_STS_P0_WAKEUP_INT_ST_SHIFT (0U) +#define PMU_WAKEUP_INT_STS_P0_WAKEUP_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_P0_WAKEUP_INT_ST_SHIFT) /* 0x00000001 */ +/* PMIC_STABLE_CNT_P0 */ +#define PMU_PMIC_STABLE_CNT_P0_OFFSET (0x10U) +#define PMU_PMIC_STABLE_CNT_P0_PMIC_STABLE_CNT_SHIFT (0U) +#define PMU_PMIC_STABLE_CNT_P0_PMIC_STABLE_CNT_MASK (0xFFFFFU << PMU_PMIC_STABLE_CNT_P0_PMIC_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* WAKEUP_RST_CLR_CNT_P0 */ +#define PMU_WAKEUP_RST_CLR_CNT_P0_OFFSET (0x14U) +#define PMU_WAKEUP_RST_CLR_CNT_P0_WAKEUP_RST_CLR_CNT_SHIFT (0U) +#define PMU_WAKEUP_RST_CLR_CNT_P0_WAKEUP_RST_CLR_CNT_MASK (0xFFFFFU << PMU_WAKEUP_RST_CLR_CNT_P0_WAKEUP_RST_CLR_CNT_SHIFT) /* 0x000FFFFF */ +/* OSC_STABLE_CNT_P0 */ +#define PMU_OSC_STABLE_CNT_P0_OFFSET (0x18U) +#define PMU_OSC_STABLE_CNT_P0_OSC_STABLE_CNT_SHIFT (0U) +#define PMU_OSC_STABLE_CNT_P0_OSC_STABLE_CNT_MASK (0xFFFFFU << PMU_OSC_STABLE_CNT_P0_OSC_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* PMU1_PWR_CHAIN_STABLE_CON */ +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_OFFSET (0x1CU) +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_EN_SHIFT (0U) +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_EN_MASK (0x1U << PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_EN_SHIFT) /* 0x00000001 */ +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_CNT_SHIFT (1U) +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_CNT_MASK (0x1FU << PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_UP_STABLE_CNT_SHIFT) /* 0x0000003E */ +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_EN_SHIFT (8U) +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_EN_MASK (0x1U << PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_EN_SHIFT) /* 0x00000100 */ +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_CNT_SHIFT (9U) +#define PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_CNT_MASK (0x1FU << PMU_PMU1_PWR_CHAIN_STABLE_CON_PMU1_PWR_DWN_STABLE_CNT_SHIFT) /* 0x00003E00 */ +/* DDR_RET_CON0_P0 */ +#define PMU_DDR_RET_CON0_P0_OFFSET (0x20U) +#define PMU_DDR_RET_CON0_P0_DDRIO_RETON_ENTER_ENA_SHIFT (0U) +#define PMU_DDR_RET_CON0_P0_DDRIO_RETON_ENTER_ENA_MASK (0xFU << PMU_DDR_RET_CON0_P0_DDRIO_RETON_ENTER_ENA_SHIFT) /* 0x0000000F */ +#define PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_ENTER_ENA_SHIFT (4U) +#define PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_ENTER_ENA_MASK (0xFU << PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_ENTER_ENA_SHIFT) /* 0x000000F0 */ +#define PMU_DDR_RET_CON0_P0_DDRIO_RETON_EXIT_ENA_SHIFT (8U) +#define PMU_DDR_RET_CON0_P0_DDRIO_RETON_EXIT_ENA_MASK (0xFU << PMU_DDR_RET_CON0_P0_DDRIO_RETON_EXIT_ENA_SHIFT) /* 0x00000F00 */ +#define PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_EXIT_ENA_SHIFT (12U) +#define PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_EXIT_ENA_MASK (0xFU << PMU_DDR_RET_CON0_P0_DDRIO_RSTIOV_EXIT_ENA_SHIFT) /* 0x0000F000 */ +/* DDR_RET_CON1_P0 */ +#define PMU_DDR_RET_CON1_P0_OFFSET (0x24U) +#define PMU_DDR_RET_CON1_P0_DDRIO_RETON_ENTER_SFTENA_SHIFT (0U) +#define PMU_DDR_RET_CON1_P0_DDRIO_RETON_ENTER_SFTENA_MASK (0xFU << PMU_DDR_RET_CON1_P0_DDRIO_RETON_ENTER_SFTENA_SHIFT) /* 0x0000000F */ +#define PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT (4U) +#define PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_ENTER_SFTENA_MASK (0xFU << PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT) /* 0x000000F0 */ +#define PMU_DDR_RET_CON1_P0_DDRIO_RETON_EXIT_SFTENA_SHIFT (8U) +#define PMU_DDR_RET_CON1_P0_DDRIO_RETON_EXIT_SFTENA_MASK (0xFU << PMU_DDR_RET_CON1_P0_DDRIO_RETON_EXIT_SFTENA_SHIFT) /* 0x00000F00 */ +#define PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT (12U) +#define PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_EXIT_SFTENA_MASK (0xFU << PMU_DDR_RET_CON1_P0_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT) /* 0x0000F000 */ +/* INFO_TX_CON */ +#define PMU_INFO_TX_CON_OFFSET (0x30U) +#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT (0U) +#define PMU_INFO_TX_CON_INFO_TX_INTV_TIME_MASK (0xFFU << PMU_INFO_TX_CON_INFO_TX_INTV_TIME_SHIFT) /* 0x000000FF */ +#define PMU_INFO_TX_CON_INFO_TX_EN_SHIFT (8U) +#define PMU_INFO_TX_CON_INFO_TX_EN_MASK (0x1U << PMU_INFO_TX_CON_INFO_TX_EN_SHIFT) /* 0x00000100 */ +/* VERSION */ +#define PMU_VERSION_OFFSET (0x4000U) +#define PMU_VERSION (0x3588U) +#define PMU_VERSION_VERSION_SHIFT (0U) +#define PMU_VERSION_VERSION_MASK (0xFFFFFFFFU << PMU_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* PWR_CON1 */ +#define PMU_PWR_CON1_OFFSET (0x4004U) +#define PMU_PWR_CON1_POWERMODE1_EN_SHIFT (0U) +#define PMU_PWR_CON1_POWERMODE1_EN_MASK (0x1U << PMU_PWR_CON1_POWERMODE1_EN_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CON1_DSU_BYPASS_SHIFT (1U) +#define PMU_PWR_CON1_DSU_BYPASS_MASK (0x1U << PMU_PWR_CON1_DSU_BYPASS_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CON1_BUS_BYPASS_SHIFT (4U) +#define PMU_PWR_CON1_BUS_BYPASS_MASK (0x1U << PMU_PWR_CON1_BUS_BYPASS_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CON1_DDR_BYPASS_SHIFT (5U) +#define PMU_PWR_CON1_DDR_BYPASS_MASK (0x1U << PMU_PWR_CON1_DDR_BYPASS_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CON1_PWRGATE_BYPASS_SHIFT (6U) +#define PMU_PWR_CON1_PWRGATE_BYPASS_MASK (0x1U << PMU_PWR_CON1_PWRGATE_BYPASS_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CON1_CRU_BYPASS_SHIFT (7U) +#define PMU_PWR_CON1_CRU_BYPASS_MASK (0x1U << PMU_PWR_CON1_CRU_BYPASS_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CON1_QCH_BYPASS_SHIFT (8U) +#define PMU_PWR_CON1_QCH_BYPASS_MASK (0x1U << PMU_PWR_CON1_QCH_BYPASS_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CON1_CORE_BYPASS_SHIFT (9U) +#define PMU_PWR_CON1_CORE_BYPASS_MASK (0x7U << PMU_PWR_CON1_CORE_BYPASS_SHIFT) /* 0x00000E00 */ +#define PMU_PWR_CON1_WFI_BYPASS_SHIFT (12U) +#define PMU_PWR_CON1_WFI_BYPASS_MASK (0x1U << PMU_PWR_CON1_WFI_BYPASS_SHIFT) /* 0x00001000 */ +/* GLB_POWER_STS */ +#define PMU_GLB_POWER_STS_OFFSET (0x4008U) +#define PMU_GLB_POWER_STS (0x0U) +#define PMU_GLB_POWER_STS_POWER_STATE_SHIFT (0U) +#define PMU_GLB_POWER_STS_POWER_STATE_MASK (0xFU << PMU_GLB_POWER_STS_POWER_STATE_SHIFT) /* 0x0000000F */ +/* INT_MASK_CON */ +#define PMU_INT_MASK_CON_OFFSET (0x400CU) +#define PMU_INT_MASK_CON_GLB_INT_MASK_SHIFT (0U) +#define PMU_INT_MASK_CON_GLB_INT_MASK_MASK (0x1U << PMU_INT_MASK_CON_GLB_INT_MASK_SHIFT) /* 0x00000001 */ +/* WAKEUP_INT_CON */ +#define PMU_WAKEUP_INT_CON_OFFSET (0x4010U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT (0U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU0_INT_EN_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT (1U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU1_INT_EN_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT (2U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU2_INT_EN_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT (3U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU3_INT_EN_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU4_INT_EN_SHIFT (4U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU4_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU4_INT_EN_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU5_INT_EN_SHIFT (5U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU5_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU5_INT_EN_SHIFT) /* 0x00000020 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU6_INT_EN_SHIFT (6U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU6_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU6_INT_EN_SHIFT) /* 0x00000040 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU7_INT_EN_SHIFT (7U) +#define PMU_WAKEUP_INT_CON_WAKEUP_CPU7_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_CPU7_INT_EN_SHIFT) /* 0x00000080 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT (8U) +#define PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_GPIO0_INT_EN_SHIFT) /* 0x00000100 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC_INT_EN_SHIFT (9U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SDMMC_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDMMC_INT_EN_SHIFT) /* 0x00000200 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SDIO_INT_EN_SHIFT (10U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SDIO_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SDIO_INT_EN_SHIFT) /* 0x00000400 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_USB_INT_EN_SHIFT (11U) +#define PMU_WAKEUP_INT_CON_WAKEUP_USB_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_USB_INT_EN_SHIFT) /* 0x00000800 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_INT_EN_SHIFT (12U) +#define PMU_WAKEUP_INT_CON_WAKEUP_UART0_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_UART0_INT_EN_SHIFT) /* 0x00001000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_INT_EN_SHIFT (13U) +#define PMU_WAKEUP_INT_CON_WAKEUP_VAD_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_VAD_INT_EN_SHIFT) /* 0x00002000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_INT_EN_SHIFT (14U) +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMER_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMER_INT_EN_SHIFT) /* 0x00004000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_SYS_INT_EN_SHIFT (15U) +#define PMU_WAKEUP_INT_CON_WAKEUP_SYS_INT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_SYS_INT_EN_SHIFT) /* 0x00008000 */ +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT (16U) +#define PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_MASK (0x1U << PMU_WAKEUP_INT_CON_WAKEUP_TIMEOUT_EN_SHIFT) /* 0x00010000 */ +/* WAKEUP_INT_STS */ +#define PMU_WAKEUP_INT_STS_OFFSET (0x4014U) +#define PMU_WAKEUP_INT_STS (0x0U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU0_INT_ST_SHIFT (0U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU0_INT_ST_SHIFT) /* 0x00000001 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU1_INT_ST_SHIFT (1U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU1_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU1_INT_ST_SHIFT) /* 0x00000002 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU2_INT_ST_SHIFT (2U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU2_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU2_INT_ST_SHIFT) /* 0x00000004 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU3_INT_ST_SHIFT (3U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU3_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU3_INT_ST_SHIFT) /* 0x00000008 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU4_INT_ST_SHIFT (4U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU4_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU4_INT_ST_SHIFT) /* 0x00000010 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU5_INT_ST_SHIFT (5U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU5_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU5_INT_ST_SHIFT) /* 0x00000020 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU6_INT_ST_SHIFT (6U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU6_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU6_INT_ST_SHIFT) /* 0x00000040 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU7_INT_ST_SHIFT (7U) +#define PMU_WAKEUP_INT_STS_WAKEUP_CPU7_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_CPU7_INT_ST_SHIFT) /* 0x00000080 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_GPIO0_INT_ST_SHIFT (8U) +#define PMU_WAKEUP_INT_STS_WAKEUP_GPIO0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_GPIO0_INT_ST_SHIFT) /* 0x00000100 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_SDMMC_INT_ST_SHIFT (9U) +#define PMU_WAKEUP_INT_STS_WAKEUP_SDMMC_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_SDMMC_INT_ST_SHIFT) /* 0x00000200 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_SDIO_INT_ST_SHIFT (10U) +#define PMU_WAKEUP_INT_STS_WAKEUP_SDIO_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_SDIO_INT_ST_SHIFT) /* 0x00000400 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_USB_INT_ST_SHIFT (11U) +#define PMU_WAKEUP_INT_STS_WAKEUP_USB_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_USB_INT_ST_SHIFT) /* 0x00000800 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_UART0_INT_ST_SHIFT (12U) +#define PMU_WAKEUP_INT_STS_WAKEUP_UART0_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_UART0_INT_ST_SHIFT) /* 0x00001000 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_VAD_INT_ST_SHIFT (13U) +#define PMU_WAKEUP_INT_STS_WAKEUP_VAD_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_VAD_INT_ST_SHIFT) /* 0x00002000 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_TIMER_INT_ST_SHIFT (14U) +#define PMU_WAKEUP_INT_STS_WAKEUP_TIMER_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_TIMER_INT_ST_SHIFT) /* 0x00004000 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_SYS_INT_ST_SHIFT (15U) +#define PMU_WAKEUP_INT_STS_WAKEUP_SYS_INT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_SYS_INT_ST_SHIFT) /* 0x00008000 */ +#define PMU_WAKEUP_INT_STS_WAKEUP_TIMEOUT_ST_SHIFT (16U) +#define PMU_WAKEUP_INT_STS_WAKEUP_TIMEOUT_ST_MASK (0x1U << PMU_WAKEUP_INT_STS_WAKEUP_TIMEOUT_ST_SHIFT) /* 0x00010000 */ +/* DDR_CH0_PWR_CON */ +#define PMU_DDR_CH0_PWR_CON_OFFSET (0x4020U) +#define PMU_DDR_CH0_PWR_CON_DDR_SREF_C_ENA_SHIFT (0U) +#define PMU_DDR_CH0_PWR_CON_DDR_SREF_C_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDR_SREF_C_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH0_PWR_CON_DDR_SREF_A_ENA_SHIFT (1U) +#define PMU_DDR_CH0_PWR_CON_DDR_SREF_A_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDR_SREF_A_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH0_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT (2U) +#define PMU_DDR_CH0_PWR_CON_DDRIO_RETON_ENTER_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH0_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT (5U) +#define PMU_DDR_CH0_PWR_CON_DDRIO_RETON_EXIT_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT (6U) +#define PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT (7U) +#define PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH0_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT (8U) +#define PMU_DDR_CH0_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH0_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT (9U) +#define PMU_DDR_CH0_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH0_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (10U) +#define PMU_DDR_CH0_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH0_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000400 */ +/* DDR_CH1_PWR_CON */ +#define PMU_DDR_CH1_PWR_CON_OFFSET (0x4024U) +#define PMU_DDR_CH1_PWR_CON_DDR_SREF_C_ENA_SHIFT (0U) +#define PMU_DDR_CH1_PWR_CON_DDR_SREF_C_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDR_SREF_C_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH1_PWR_CON_DDR_SREF_A_ENA_SHIFT (1U) +#define PMU_DDR_CH1_PWR_CON_DDR_SREF_A_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDR_SREF_A_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH1_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT (2U) +#define PMU_DDR_CH1_PWR_CON_DDRIO_RETON_ENTER_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH1_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT (5U) +#define PMU_DDR_CH1_PWR_CON_DDRIO_RETON_EXIT_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT (6U) +#define PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT (7U) +#define PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH1_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT (8U) +#define PMU_DDR_CH1_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH1_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT (9U) +#define PMU_DDR_CH1_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH1_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (10U) +#define PMU_DDR_CH1_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH1_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000400 */ +/* DDR_CH2_PWR_CON */ +#define PMU_DDR_CH2_PWR_CON_OFFSET (0x4028U) +#define PMU_DDR_CH2_PWR_CON_DDR_SREF_C_ENA_SHIFT (0U) +#define PMU_DDR_CH2_PWR_CON_DDR_SREF_C_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDR_SREF_C_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH2_PWR_CON_DDR_SREF_A_ENA_SHIFT (1U) +#define PMU_DDR_CH2_PWR_CON_DDR_SREF_A_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDR_SREF_A_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH2_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT (2U) +#define PMU_DDR_CH2_PWR_CON_DDRIO_RETON_ENTER_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH2_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT (5U) +#define PMU_DDR_CH2_PWR_CON_DDRIO_RETON_EXIT_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT (6U) +#define PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT (7U) +#define PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH2_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT (8U) +#define PMU_DDR_CH2_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH2_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT (9U) +#define PMU_DDR_CH2_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH2_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (10U) +#define PMU_DDR_CH2_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH2_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000400 */ +/* DDR_CH3_PWR_CON */ +#define PMU_DDR_CH3_PWR_CON_OFFSET (0x402CU) +#define PMU_DDR_CH3_PWR_CON_DDR_SREF_C_ENA_SHIFT (0U) +#define PMU_DDR_CH3_PWR_CON_DDR_SREF_C_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDR_SREF_C_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH3_PWR_CON_DDR_SREF_A_ENA_SHIFT (1U) +#define PMU_DDR_CH3_PWR_CON_DDR_SREF_A_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDR_SREF_A_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH3_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT (2U) +#define PMU_DDR_CH3_PWR_CON_DDRIO_RETON_ENTER_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRIO_RETON_ENTER_ENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH3_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT (5U) +#define PMU_DDR_CH3_PWR_CON_DDRIO_RETON_EXIT_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRIO_RETON_EXIT_ENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT (6U) +#define PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_ENTER_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT (7U) +#define PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRIO_RSTIOV_EXIT_ENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH3_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT (8U) +#define PMU_DDR_CH3_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRCTL_A_AUTO_GATING_ENA_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH3_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT (9U) +#define PMU_DDR_CH3_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRCTL_C_AUTO_GATING_ENA_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH3_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT (10U) +#define PMU_DDR_CH3_PWR_CON_DDRPHY_AUTO_GATING_ENA_MASK (0x1U << PMU_DDR_CH3_PWR_CON_DDRPHY_AUTO_GATING_ENA_SHIFT) /* 0x00000400 */ +/* DDR_CH0_PWR_SFTCON */ +#define PMU_DDR_CH0_PWR_SFTCON_OFFSET (0x4030U) +#define PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT (0U) +#define PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_C_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT (1U) +#define PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_A_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT (2U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT (5U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT (6U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT (7U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT (8U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT (9U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT (10U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000400 */ +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT (11U) +#define PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH0_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000800 */ +/* DDR_CH1_PWR_SFTCON */ +#define PMU_DDR_CH1_PWR_SFTCON_OFFSET (0x4034U) +#define PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT (0U) +#define PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_C_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT (1U) +#define PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_A_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT (2U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT (5U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT (6U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT (7U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT (8U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT (9U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT (10U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000400 */ +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT (11U) +#define PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH1_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000800 */ +/* DDR_CH2_PWR_SFTCON */ +#define PMU_DDR_CH2_PWR_SFTCON_OFFSET (0x4038U) +#define PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT (0U) +#define PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_C_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT (1U) +#define PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_A_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT (2U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT (5U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT (6U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT (7U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT (8U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT (9U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT (10U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000400 */ +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT (11U) +#define PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH2_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000800 */ +/* DDR_CH3_PWR_SFTCON */ +#define PMU_DDR_CH3_PWR_SFTCON_OFFSET (0x403CU) +#define PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT (0U) +#define PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_C_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_C_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT (1U) +#define PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_A_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDR_SREF_A_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT (2U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_ENTER_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT (5U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRIO_RETON_EXIT_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT (6U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_ENTER_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT (7U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRIO_RSTIOV_EXIT_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT (8U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000100 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT (9U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000200 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT (10U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRCTL_A_ACTIVE_WAIT_EXIT_SHIFT) /* 0x00000400 */ +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT (11U) +#define PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_MASK (0x1U << PMU_DDR_CH3_PWR_SFTCON_DDRCTL_C_ACTIVE_WAIT_ENTER_SHIFT) /* 0x00000800 */ +/* DDR_POWER_STS */ +#define PMU_DDR_POWER_STS_OFFSET (0x4040U) +#define PMU_DDR_POWER_STS (0x0U) +#define PMU_DDR_POWER_STS_DDR_POWER_STATE_SHIFT (0U) +#define PMU_DDR_POWER_STS_DDR_POWER_STATE_MASK (0xFU << PMU_DDR_POWER_STS_DDR_POWER_STATE_SHIFT) /* 0x0000000F */ +/* DDR_STS */ +#define PMU_DDR_STS_OFFSET (0x4044U) +#define PMU_DDR_STS (0x0U) +#define PMU_DDR_STS_DDRCTRL_CH0_C_SYSACK_SHIFT (0U) +#define PMU_DDR_STS_DDRCTRL_CH0_C_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH0_C_SYSACK_SHIFT) /* 0x00000001 */ +#define PMU_DDR_STS_DDRCTRL_CH0_C_SYSACTIVE_SHIFT (1U) +#define PMU_DDR_STS_DDRCTRL_CH0_C_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH0_C_SYSACTIVE_SHIFT) /* 0x00000002 */ +#define PMU_DDR_STS_DDR_CH0_IO_RETON_SHIFT (2U) +#define PMU_DDR_STS_DDR_CH0_IO_RETON_MASK (0x1U << PMU_DDR_STS_DDR_CH0_IO_RETON_SHIFT) /* 0x00000004 */ +#define PMU_DDR_STS_DDRCTRL_CH0_A_SYSACK_SHIFT (3U) +#define PMU_DDR_STS_DDRCTRL_CH0_A_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH0_A_SYSACK_SHIFT) /* 0x00000008 */ +#define PMU_DDR_STS_DDRCTRL_CH0_A_SYSACTIVE_SHIFT (4U) +#define PMU_DDR_STS_DDRCTRL_CH0_A_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH0_A_SYSACTIVE_SHIFT) /* 0x00000010 */ +#define PMU_DDR_STS_DDR_CH0_IO_RSTIOV_SHIFT (5U) +#define PMU_DDR_STS_DDR_CH0_IO_RSTIOV_MASK (0x1U << PMU_DDR_STS_DDR_CH0_IO_RSTIOV_SHIFT) /* 0x00000020 */ +#define PMU_DDR_STS_DDRCTRL_CH1_C_SYSACK_SHIFT (8U) +#define PMU_DDR_STS_DDRCTRL_CH1_C_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH1_C_SYSACK_SHIFT) /* 0x00000100 */ +#define PMU_DDR_STS_DDRCTRL_CH1_C_SYSACTIVE_SHIFT (9U) +#define PMU_DDR_STS_DDRCTRL_CH1_C_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH1_C_SYSACTIVE_SHIFT) /* 0x00000200 */ +#define PMU_DDR_STS_DDR_CH1_IO_RETON_SHIFT (10U) +#define PMU_DDR_STS_DDR_CH1_IO_RETON_MASK (0x1U << PMU_DDR_STS_DDR_CH1_IO_RETON_SHIFT) /* 0x00000400 */ +#define PMU_DDR_STS_DDRCTRL_CH1_A_SYSACK_SHIFT (11U) +#define PMU_DDR_STS_DDRCTRL_CH1_A_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH1_A_SYSACK_SHIFT) /* 0x00000800 */ +#define PMU_DDR_STS_DDRCTRL_CH1_A_SYSACTIVE_SHIFT (12U) +#define PMU_DDR_STS_DDRCTRL_CH1_A_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH1_A_SYSACTIVE_SHIFT) /* 0x00001000 */ +#define PMU_DDR_STS_DDR_CH1_IO_RSTIOV_SHIFT (13U) +#define PMU_DDR_STS_DDR_CH1_IO_RSTIOV_MASK (0x1U << PMU_DDR_STS_DDR_CH1_IO_RSTIOV_SHIFT) /* 0x00002000 */ +#define PMU_DDR_STS_DDRCTRL_CH2_C_SYSACK_SHIFT (16U) +#define PMU_DDR_STS_DDRCTRL_CH2_C_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH2_C_SYSACK_SHIFT) /* 0x00010000 */ +#define PMU_DDR_STS_DDRCTRL_CH2_C_SYSACTIVE_SHIFT (17U) +#define PMU_DDR_STS_DDRCTRL_CH2_C_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH2_C_SYSACTIVE_SHIFT) /* 0x00020000 */ +#define PMU_DDR_STS_DDR_CH2_IO_RETON_SHIFT (18U) +#define PMU_DDR_STS_DDR_CH2_IO_RETON_MASK (0x1U << PMU_DDR_STS_DDR_CH2_IO_RETON_SHIFT) /* 0x00040000 */ +#define PMU_DDR_STS_DDRCTRL_CH2_A_SYSACK_SHIFT (19U) +#define PMU_DDR_STS_DDRCTRL_CH2_A_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH2_A_SYSACK_SHIFT) /* 0x00080000 */ +#define PMU_DDR_STS_DDRCTRL_CH2_A_SYSACTIVE_SHIFT (20U) +#define PMU_DDR_STS_DDRCTRL_CH2_A_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH2_A_SYSACTIVE_SHIFT) /* 0x00100000 */ +#define PMU_DDR_STS_DDR_CH2_IO_RSTIOV_SHIFT (21U) +#define PMU_DDR_STS_DDR_CH2_IO_RSTIOV_MASK (0x1U << PMU_DDR_STS_DDR_CH2_IO_RSTIOV_SHIFT) /* 0x00200000 */ +#define PMU_DDR_STS_DDRCTRL_CH3_C_SYSACK_SHIFT (24U) +#define PMU_DDR_STS_DDRCTRL_CH3_C_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH3_C_SYSACK_SHIFT) /* 0x01000000 */ +#define PMU_DDR_STS_DDRCTRL_CH3_C_SYSACTIVE_SHIFT (25U) +#define PMU_DDR_STS_DDRCTRL_CH3_C_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH3_C_SYSACTIVE_SHIFT) /* 0x02000000 */ +#define PMU_DDR_STS_DDR_CH3_IO_RETON_SHIFT (26U) +#define PMU_DDR_STS_DDR_CH3_IO_RETON_MASK (0x1U << PMU_DDR_STS_DDR_CH3_IO_RETON_SHIFT) /* 0x04000000 */ +#define PMU_DDR_STS_DDRCTRL_CH3_A_SYSACK_SHIFT (27U) +#define PMU_DDR_STS_DDRCTRL_CH3_A_SYSACK_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH3_A_SYSACK_SHIFT) /* 0x08000000 */ +#define PMU_DDR_STS_DDRCTRL_CH3_A_SYSACTIVE_SHIFT (28U) +#define PMU_DDR_STS_DDRCTRL_CH3_A_SYSACTIVE_MASK (0x1U << PMU_DDR_STS_DDRCTRL_CH3_A_SYSACTIVE_SHIFT) /* 0x10000000 */ +#define PMU_DDR_STS_DDR_CH3_IO_RSTIOV_SHIFT (29U) +#define PMU_DDR_STS_DDR_CH3_IO_RSTIOV_MASK (0x1U << PMU_DDR_STS_DDR_CH3_IO_RSTIOV_SHIFT) /* 0x20000000 */ +/* CRU_PWR_CON */ +#define PMU_CRU_PWR_CON_OFFSET (0x4050U) +#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT (0U) +#define PMU_CRU_PWR_CON_ALIVE_32K_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_32K_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT (1U) +#define PMU_CRU_PWR_CON_OSC_DIS_ENA_MASK (0x1U << PMU_CRU_PWR_CON_OSC_DIS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT (2U) +#define PMU_CRU_PWR_CON_WAKEUP_RST_ENA_MASK (0x1U << PMU_CRU_PWR_CON_WAKEUP_RST_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT (3U) +#define PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_MASK (0x1U << PMU_CRU_PWR_CON_INPUT_CLAMP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT (4U) +#define PMU_CRU_PWR_CON_ALIVE_OSC_ENA_MASK (0x1U << PMU_CRU_PWR_CON_ALIVE_OSC_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT (5U) +#define PMU_CRU_PWR_CON_POWER_OFF_ENA_MASK (0x1U << PMU_CRU_PWR_CON_POWER_OFF_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT (6U) +#define PMU_CRU_PWR_CON_PWM_SWITCH_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT (7U) +#define PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PWM_GPIO_IOE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT (8U) +#define PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_MASK (0x1U << PMU_CRU_PWR_CON_PWM_SWITCH_IOUT_SHIFT) /* 0x00000100 */ +#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT (9U) +#define PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_MASK (0x1U << PMU_CRU_PWR_CON_PD_BUS_CLK_SRC_GATE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CRU_PWR_CON_POWER_OFF_IO_ENA_SHIFT (10U) +#define PMU_CRU_PWR_CON_POWER_OFF_IO_ENA_MASK (0x1U << PMU_CRU_PWR_CON_POWER_OFF_IO_ENA_SHIFT) /* 0x00000400 */ +/* CRU_PWR_SFTCON */ +#define PMU_CRU_PWR_SFTCON_OFFSET (0x4054U) +#define PMU_CRU_PWR_SFTCON_ALIVE_32K_SFTENA_SHIFT (0U) +#define PMU_CRU_PWR_SFTCON_ALIVE_32K_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_32K_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CRU_PWR_SFTCON_OSC_DIS_SFTENA_SHIFT (1U) +#define PMU_CRU_PWR_SFTCON_OSC_DIS_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_OSC_DIS_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_SFTENA_SHIFT (2U) +#define PMU_CRU_PWR_SFTCON_WAKEUP_RST_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_WAKEUP_RST_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_SFTENA_SHIFT (3U) +#define PMU_CRU_PWR_SFTCON_INPUT_CLAMP_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_INPUT_CLAMP_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_SFTENA_SHIFT (4U) +#define PMU_CRU_PWR_SFTCON_ALIVE_OSC_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_ALIVE_OSC_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_CRU_PWR_SFTCON_POWER_OFF_SFTENA_SHIFT (5U) +#define PMU_CRU_PWR_SFTCON_POWER_OFF_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_POWER_OFF_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_CRU_PWR_SFTCON_POWER_OFF_IO_SFTENA_SHIFT (6U) +#define PMU_CRU_PWR_SFTCON_POWER_OFF_IO_SFTENA_MASK (0x1U << PMU_CRU_PWR_SFTCON_POWER_OFF_IO_SFTENA_SHIFT) /* 0x00000040 */ +/* CRU_POWER_STS */ +#define PMU_CRU_POWER_STS_OFFSET (0x4058U) +#define PMU_CRU_POWER_STS (0x0U) +#define PMU_CRU_POWER_STS_CRU_POWER_STATE_SHIFT (0U) +#define PMU_CRU_POWER_STS_CRU_POWER_STATE_MASK (0xFU << PMU_CRU_POWER_STS_CRU_POWER_STATE_SHIFT) /* 0x0000000F */ +/* PLLPD_CON0 */ +#define PMU_PLLPD_CON0_OFFSET (0x4060U) +#define PMU_PLLPD_CON0_B0PLL_PD_ENA_SHIFT (0U) +#define PMU_PLLPD_CON0_B0PLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_B0PLL_PD_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_CON0_B1PLL_PD_ENA_SHIFT (1U) +#define PMU_PLLPD_CON0_B1PLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_B1PLL_PD_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PLLPD_CON0_LPLL_PD_ENA_SHIFT (2U) +#define PMU_PLLPD_CON0_LPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_LPLL_PD_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PLLPD_CON0_D0APLL_PD_ENA_SHIFT (3U) +#define PMU_PLLPD_CON0_D0APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D0APLL_PD_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PLLPD_CON0_D0BPLL_PD_ENA_SHIFT (4U) +#define PMU_PLLPD_CON0_D0BPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D0BPLL_PD_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PLLPD_CON0_D1APLL_PD_ENA_SHIFT (5U) +#define PMU_PLLPD_CON0_D1APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D1APLL_PD_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PLLPD_CON0_D1BPLL_PD_ENA_SHIFT (6U) +#define PMU_PLLPD_CON0_D1BPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D1BPLL_PD_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PLLPD_CON0_D2APLL_PD_ENA_SHIFT (7U) +#define PMU_PLLPD_CON0_D2APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D2APLL_PD_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PLLPD_CON0_D2BPLL_PD_ENA_SHIFT (8U) +#define PMU_PLLPD_CON0_D2BPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D2BPLL_PD_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PLLPD_CON0_D3APLL_PD_ENA_SHIFT (9U) +#define PMU_PLLPD_CON0_D3APLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D3APLL_PD_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PLLPD_CON0_D3BPLL_PD_ENA_SHIFT (10U) +#define PMU_PLLPD_CON0_D3BPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_D3BPLL_PD_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PLLPD_CON0_V0PLL_PD_ENA_SHIFT (11U) +#define PMU_PLLPD_CON0_V0PLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_V0PLL_PD_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PLLPD_CON0_AUPLL_PD_ENA_SHIFT (12U) +#define PMU_PLLPD_CON0_AUPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_AUPLL_PD_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PLLPD_CON0_GPLL_PD_ENA_SHIFT (13U) +#define PMU_PLLPD_CON0_GPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_GPLL_PD_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PLLPD_CON0_CPLL_PD_ENA_SHIFT (14U) +#define PMU_PLLPD_CON0_CPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_CPLL_PD_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PLLPD_CON0_NPLL_PD_ENA_SHIFT (15U) +#define PMU_PLLPD_CON0_NPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON0_NPLL_PD_ENA_SHIFT) /* 0x00008000 */ +/* PLLPD_CON1 */ +#define PMU_PLLPD_CON1_OFFSET (0x4064U) +#define PMU_PLLPD_CON1_PPLL_PD_ENA_SHIFT (0U) +#define PMU_PLLPD_CON1_PPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON1_PPLL_PD_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_CON1_SPLL_PD_ENA_SHIFT (1U) +#define PMU_PLLPD_CON1_SPLL_PD_ENA_MASK (0x1U << PMU_PLLPD_CON1_SPLL_PD_ENA_SHIFT) /* 0x00000002 */ +/* PLLPD_SFTCON0 */ +#define PMU_PLLPD_SFTCON0_OFFSET (0x4068U) +#define PMU_PLLPD_SFTCON0_B0PLL_PD_SFTENA_SHIFT (0U) +#define PMU_PLLPD_SFTCON0_B0PLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_B0PLL_PD_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_SFTCON0_B1PLL_PD_SFTENA_SHIFT (1U) +#define PMU_PLLPD_SFTCON0_B1PLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_B1PLL_PD_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_PLLPD_SFTCON0_LPLL_PD_SFTENA_SHIFT (2U) +#define PMU_PLLPD_SFTCON0_LPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_LPLL_PD_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_PLLPD_SFTCON0_D0APLL_PD_SFTENA_SHIFT (3U) +#define PMU_PLLPD_SFTCON0_D0APLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D0APLL_PD_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_PLLPD_SFTCON0_D0BPLL_PD_SFTENA_SHIFT (4U) +#define PMU_PLLPD_SFTCON0_D0BPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D0BPLL_PD_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_PLLPD_SFTCON0_D1APLL_PD_SFTENA_SHIFT (5U) +#define PMU_PLLPD_SFTCON0_D1APLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D1APLL_PD_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_PLLPD_SFTCON0_D1BPLL_PD_SFTENA_SHIFT (6U) +#define PMU_PLLPD_SFTCON0_D1BPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D1BPLL_PD_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_PLLPD_SFTCON0_D2APLL_PD_SFTENA_SHIFT (7U) +#define PMU_PLLPD_SFTCON0_D2APLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D2APLL_PD_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_PLLPD_SFTCON0_D2BPLL_PD_SFTENA_SHIFT (8U) +#define PMU_PLLPD_SFTCON0_D2BPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D2BPLL_PD_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_PLLPD_SFTCON0_D3APLL_PD_SFTENA_SHIFT (9U) +#define PMU_PLLPD_SFTCON0_D3APLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D3APLL_PD_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_PLLPD_SFTCON0_D3BPLL_PD_SFTENA_SHIFT (10U) +#define PMU_PLLPD_SFTCON0_D3BPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_D3BPLL_PD_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_PLLPD_SFTCON0_V0PLL_PD_SFTENA_SHIFT (11U) +#define PMU_PLLPD_SFTCON0_V0PLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_V0PLL_PD_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_PLLPD_SFTCON0_AUPLL_PD_SFTENA_SHIFT (12U) +#define PMU_PLLPD_SFTCON0_AUPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_AUPLL_PD_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_PLLPD_SFTCON0_GPLL_PD_SFTENA_SHIFT (13U) +#define PMU_PLLPD_SFTCON0_GPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_GPLL_PD_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_PLLPD_SFTCON0_CPLL_PD_SFTENA_SHIFT (14U) +#define PMU_PLLPD_SFTCON0_CPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_CPLL_PD_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_PLLPD_SFTCON0_NPLL_PD_SFTENA_SHIFT (15U) +#define PMU_PLLPD_SFTCON0_NPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON0_NPLL_PD_SFTENA_SHIFT) /* 0x00008000 */ +/* PLLPD_SFTCON1 */ +#define PMU_PLLPD_SFTCON1_OFFSET (0x406CU) +#define PMU_PLLPD_SFTCON1_PPLL_PD_SFTENA_SHIFT (0U) +#define PMU_PLLPD_SFTCON1_PPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON1_PPLL_PD_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_PLLPD_SFTCON1_SPLL_PD_SFTENA_SHIFT (1U) +#define PMU_PLLPD_SFTCON1_SPLL_PD_SFTENA_MASK (0x1U << PMU_PLLPD_SFTCON1_SPLL_PD_SFTENA_SHIFT) /* 0x00000002 */ +/* PMIC_STABLE_CNT */ +#define PMU_PMIC_STABLE_CNT_OFFSET (0x4080U) +#define PMU_PMIC_STABLE_CNT_PMIC_STABLE_CNT_SHIFT (0U) +#define PMU_PMIC_STABLE_CNT_PMIC_STABLE_CNT_MASK (0xFFFFFU << PMU_PMIC_STABLE_CNT_PMIC_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* OSC_STABLE_CNT */ +#define PMU_OSC_STABLE_CNT_OFFSET (0x4084U) +#define PMU_OSC_STABLE_CNT_OSC_STABLE_CNT_SHIFT (0U) +#define PMU_OSC_STABLE_CNT_OSC_STABLE_CNT_MASK (0xFFFFFU << PMU_OSC_STABLE_CNT_OSC_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* WAKEUP_RST_CLR_CNT */ +#define PMU_WAKEUP_RST_CLR_CNT_OFFSET (0x4088U) +#define PMU_WAKEUP_RST_CLR_CNT_WAKEUP_RST_CLR_CNT_SHIFT (0U) +#define PMU_WAKEUP_RST_CLR_CNT_WAKEUP_RST_CLR_CNT_MASK (0xFFFFFU << PMU_WAKEUP_RST_CLR_CNT_WAKEUP_RST_CLR_CNT_SHIFT) /* 0x000FFFFF */ +/* PLL_LOCK_CNT */ +#define PMU_PLL_LOCK_CNT_OFFSET (0x408CU) +#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT (0U) +#define PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_MASK (0xFFFFFU << PMU_PLL_LOCK_CNT_PLL_LOCK_CNT_SHIFT) /* 0x000FFFFF */ +/* WAKEUP_TIMEOUT_CNT */ +#define PMU_WAKEUP_TIMEOUT_CNT_OFFSET (0x4094U) +#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT (0U) +#define PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_MASK (0xFFFFFU << PMU_WAKEUP_TIMEOUT_CNT_WAKEUP_TIMEOUT_CNT_SHIFT) /* 0x000FFFFF */ +/* PWM_SWITCH_CNT */ +#define PMU_PWM_SWITCH_CNT_OFFSET (0x4098U) +#define PMU_PWM_SWITCH_CNT_PWM_SWITCH_CNT_SHIFT (0U) +#define PMU_PWM_SWITCH_CNT_PWM_SWITCH_CNT_MASK (0xFFFFFU << PMU_PWM_SWITCH_CNT_PWM_SWITCH_CNT_SHIFT) /* 0x000FFFFF */ +/* SYS_REG0 */ +#define PMU_SYS_REG0_OFFSET (0x4100U) +#define PMU_SYS_REG0_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG0_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG0_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG1 */ +#define PMU_SYS_REG1_OFFSET (0x4104U) +#define PMU_SYS_REG1_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG1_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG1_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG2 */ +#define PMU_SYS_REG2_OFFSET (0x4108U) +#define PMU_SYS_REG2_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG2_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG2_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG3 */ +#define PMU_SYS_REG3_OFFSET (0x410CU) +#define PMU_SYS_REG3_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG3_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG3_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG4 */ +#define PMU_SYS_REG4_OFFSET (0x4110U) +#define PMU_SYS_REG4_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG4_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG4_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG5 */ +#define PMU_SYS_REG5_OFFSET (0x4114U) +#define PMU_SYS_REG5_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG5_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG5_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG6 */ +#define PMU_SYS_REG6_OFFSET (0x4118U) +#define PMU_SYS_REG6_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG6_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG6_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* SYS_REG7 */ +#define PMU_SYS_REG7_OFFSET (0x411CU) +#define PMU_SYS_REG7_SYS_REG_SHIFT (0U) +#define PMU_SYS_REG7_SYS_REG_MASK (0xFFFFFFFFU << PMU_SYS_REG7_SYS_REG_SHIFT) /* 0xFFFFFFFF */ +/* PWR_CON2 */ +#define PMU_PWR_CON2_OFFSET (0x8000U) +#define PMU_PWR_CON2_CPU0_LP_BYPASS_SHIFT (0U) +#define PMU_PWR_CON2_CPU0_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU0_LP_BYPASS_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CON2_CPU1_LP_BYPASS_SHIFT (1U) +#define PMU_PWR_CON2_CPU1_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU1_LP_BYPASS_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CON2_CPU2_LP_BYPASS_SHIFT (2U) +#define PMU_PWR_CON2_CPU2_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU2_LP_BYPASS_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CON2_CPU3_LP_BYPASS_SHIFT (3U) +#define PMU_PWR_CON2_CPU3_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU3_LP_BYPASS_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CON2_CPU4_LP_BYPASS_SHIFT (4U) +#define PMU_PWR_CON2_CPU4_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU4_LP_BYPASS_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CON2_CPU5_LP_BYPASS_SHIFT (5U) +#define PMU_PWR_CON2_CPU5_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU5_LP_BYPASS_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CON2_CPU6_LP_BYPASS_SHIFT (6U) +#define PMU_PWR_CON2_CPU6_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU6_LP_BYPASS_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CON2_CPU7_LP_BYPASS_SHIFT (7U) +#define PMU_PWR_CON2_CPU7_LP_BYPASS_MASK (0x1U << PMU_PWR_CON2_CPU7_LP_BYPASS_SHIFT) /* 0x00000080 */ +/* DSU_PWR_CON */ +#define PMU_DSU_PWR_CON_OFFSET (0x8004U) +#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT (0U) +#define PMU_DSU_PWR_CON_DSU_PWRDN_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT (1U) +#define PMU_DSU_PWR_CON_DSU_PWROFF_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_PWROFF_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DSU_PWR_CON_DSU_CLUSTERPACTIVE_BIT_FULL_FLAG_SHIFT (2U) +#define PMU_DSU_PWR_CON_DSU_CLUSTERPACTIVE_BIT_FULL_FLAG_MASK (0x1U << PMU_DSU_PWR_CON_DSU_CLUSTERPACTIVE_BIT_FULL_FLAG_SHIFT) /* 0x00000004 */ +#define PMU_DSU_PWR_CON_DSU_FUNCRET_ENA_SHIFT (3U) +#define PMU_DSU_PWR_CON_DSU_FUNCRET_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_FUNCRET_ENA_SHIFT) /* 0x00000008 */ +#define PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_BYPASS_SHIFT (5U) +#define PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_BYPASS_MASK (0x1FU << PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_BYPASS_SHIFT) /* 0x000003E0 */ +#define PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_CLAMP_ENA_SHIFT (10U) +#define PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_CLAMP_ENA_MASK (0x1U << PMU_DSU_PWR_CON_DSU_MEM_DWN_ACK_CLAMP_ENA_SHIFT) /* 0x00000400 */ +/* DSU_PWR_SFTCON */ +#define PMU_DSU_PWR_SFTCON_OFFSET (0x8008U) +#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_DSU_PWR_SFTCON_DSU_PWRDN_SFTENA_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_DSU_PWR_SFTCON_DSU_PWROFF_SFTENA_SHIFT (1U) +#define PMU_DSU_PWR_SFTCON_DSU_PWROFF_SFTENA_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_PWROFF_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_OFF_SHIFT (2U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_OFF_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_OFF_SHIFT) /* 0x00000004 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FULLON_SHIFT (3U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FULLON_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FULLON_SHIFT) /* 0x00000008 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FUNCRET_SHIFT (4U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FUNCRET_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_FUNCRET_SHIFT) /* 0x00000010 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON3P4_SHIFT (5U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON3P4_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON3P4_SHIFT) /* 0x00000020 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P2_SHIFT (6U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P2_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P2_SHIFT) /* 0x00000040 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P4_SHIFT (7U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P4_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ON1P4_SHIFT) /* 0x00000080 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ONSF_SHIFT (8U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ONSF_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_ONSF_SHIFT) /* 0x00000100 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET3P4_SHIFT (9U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET3P4_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET3P4_SHIFT) /* 0x00000200 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P2_SHIFT (10U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P2_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P2_SHIFT) /* 0x00000400 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P4_SHIFT (11U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P4_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RET1P4_SHIFT) /* 0x00000800 */ +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RETSF_SHIFT (12U) +#define PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RETSF_MASK (0x1U << PMU_DSU_PWR_SFTCON_DSU_SFT_CLUSTERPACTIVE_RETSF_SHIFT) /* 0x00001000 */ +/* DSU_AUTO_PWR_CON */ +#define PMU_DSU_AUTO_PWR_CON_OFFSET (0x800CU) +#define PMU_DSU_AUTO_PWR_CON_DSU_LP_EN_SHIFT (0U) +#define PMU_DSU_AUTO_PWR_CON_DSU_LP_EN_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_LP_EN_SHIFT) /* 0x00000001 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_DSU_AUTO_PWR_CON_DSU_INT_WAKEUP_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_DSU_AUTO_PWR_CON_DSU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FUNCRET_ENA_SHIFT (4U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FUNCRET_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FUNCRET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FULLON_ENA_SHIFT (5U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FULLON_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_FULLON_ENA_SHIFT) /* 0x00000020 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON3P4_ENA_SHIFT (6U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON3P4_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON3P4_ENA_SHIFT) /* 0x00000040 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P2_ENA_SHIFT (7U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P2_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P2_ENA_SHIFT) /* 0x00000080 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P4_ENA_SHIFT (8U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P4_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ON1P4_ENA_SHIFT) /* 0x00000100 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ONSF_ENA_SHIFT (9U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ONSF_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_ONSF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET3P4_ENA_SHIFT (10U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET3P4_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET3P4_ENA_SHIFT) /* 0x00000400 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P2_ENA_SHIFT (11U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P2_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P2_ENA_SHIFT) /* 0x00000800 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P4_ENA_SHIFT (12U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P4_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RET1P4_ENA_SHIFT) /* 0x00001000 */ +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RETSF_ENA_SHIFT (13U) +#define PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RETSF_ENA_MASK (0x1U << PMU_DSU_AUTO_PWR_CON_DSU_AUTO_RETSF_ENA_SHIFT) /* 0x00002000 */ +/* CPU0_AUTO_PWR_CON */ +#define PMU_CPU0_AUTO_PWR_CON_OFFSET (0x8010U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_EMUOFF_ENA_SHIFT (8U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_EMUOFF_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_AUTO_EMUOFF_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU0_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU1_AUTO_PWR_CON */ +#define PMU_CPU1_AUTO_PWR_CON_OFFSET (0x8014U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU1_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU2_AUTO_PWR_CON */ +#define PMU_CPU2_AUTO_PWR_CON_OFFSET (0x8018U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU2_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU3_AUTO_PWR_CON */ +#define PMU_CPU3_AUTO_PWR_CON_OFFSET (0x801CU) +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU3_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU4_AUTO_PWR_CON */ +#define PMU_CPU4_AUTO_PWR_CON_OFFSET (0x8020U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU4_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU5_AUTO_PWR_CON */ +#define PMU_CPU5_AUTO_PWR_CON_OFFSET (0x8024U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU5_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU6_AUTO_PWR_CON */ +#define PMU_CPU6_AUTO_PWR_CON_OFFSET (0x8028U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU6_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU7_AUTO_PWR_CON */ +#define PMU_CPU7_AUTO_PWR_CON_OFFSET (0x802CU) +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT (0U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT (3U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_SFT_WAKEUP_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT (4U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_RET_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_RET_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT (6U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT (7U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_MEM_LS_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_MEM_LS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT (8U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_AUTO_EMU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT (9U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_ONLY_MEMOFF_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT (10U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCORERESET_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT (11U) +#define PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_MASK (0x1U << PMU_CPU7_AUTO_PWR_CON_CPU_DBGRCV_NCPUPORESET_ENA_SHIFT) /* 0x00000800 */ +/* CPU0_PWR_SFTCON */ +#define PMU_CPU0_PWR_SFTCON_OFFSET (0x8030U) +#define PMU_CPU0_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU0_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU0_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU0_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU0_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU1_PWR_SFTCON */ +#define PMU_CPU1_PWR_SFTCON_OFFSET (0x8034U) +#define PMU_CPU1_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU1_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU1_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU1_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU1_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU2_PWR_SFTCON */ +#define PMU_CPU2_PWR_SFTCON_OFFSET (0x8038U) +#define PMU_CPU2_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU2_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU2_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU2_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU2_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU3_PWR_SFTCON */ +#define PMU_CPU3_PWR_SFTCON_OFFSET (0x803CU) +#define PMU_CPU3_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU3_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU3_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU3_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU3_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU4_PWR_SFTCON */ +#define PMU_CPU4_PWR_SFTCON_OFFSET (0x8040U) +#define PMU_CPU4_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU4_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU4_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU4_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU4_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU5_PWR_SFTCON */ +#define PMU_CPU5_PWR_SFTCON_OFFSET (0x8044U) +#define PMU_CPU5_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU5_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU5_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU5_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU5_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU6_PWR_SFTCON */ +#define PMU_CPU6_PWR_SFTCON_OFFSET (0x8048U) +#define PMU_CPU6_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU6_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU6_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU6_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU6_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CPU7_PWR_SFTCON */ +#define PMU_CPU7_PWR_SFTCON_OFFSET (0x804CU) +#define PMU_CPU7_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CPU7_PWR_SFTCON_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT (1U) +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_OFF_SHIFT) /* 0x00000002 */ +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT (2U) +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_ON_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_ON_SHIFT) /* 0x00000004 */ +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT (3U) +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_RET_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_RET_SHIFT) /* 0x00000008 */ +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT (4U) +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_EMUOFF_SHIFT) /* 0x00000010 */ +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT (5U) +#define PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_SFT_PACTIVE_DBGRCV_SHIFT) /* 0x00000020 */ +#define PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT (6U) +#define PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCORERESET_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT (7U) +#define PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_DBGRCV_NCPUPORESET_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU7_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT (8U) +#define PMU_CPU7_PWR_SFTCON_CPU_MEM_LS_SFTENA_MASK (0x1U << PMU_CPU7_PWR_SFTCON_CPU_MEM_LS_SFTENA_SHIFT) /* 0x00000100 */ +/* CORE0_PWR_CON */ +#define PMU_CORE0_PWR_CON_OFFSET (0x8050U) +#define PMU_CORE0_PWR_CON_CORE_PWRDN_ENA_SHIFT (0U) +#define PMU_CORE0_PWR_CON_CORE_PWRDN_ENA_MASK (0x1U << PMU_CORE0_PWR_CON_CORE_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CORE0_PWR_CON_CORE_PWROFF_ENA_SHIFT (1U) +#define PMU_CORE0_PWR_CON_CORE_PWROFF_ENA_MASK (0x1U << PMU_CORE0_PWR_CON_CORE_PWROFF_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE0_PWR_CON_CORE_CPU_PWRDN_ENA_SHIFT (2U) +#define PMU_CORE0_PWR_CON_CORE_CPU_PWRDN_ENA_MASK (0x1U << PMU_CORE0_PWR_CON_CORE_CPU_PWRDN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CORE0_PWR_CON_CORE_PWR_CNT_ENA_SHIFT (3U) +#define PMU_CORE0_PWR_CON_CORE_PWR_CNT_ENA_MASK (0x1U << PMU_CORE0_PWR_CON_CORE_PWR_CNT_ENA_SHIFT) /* 0x00000008 */ +/* CORE1_PWR_CON */ +#define PMU_CORE1_PWR_CON_OFFSET (0x8054U) +#define PMU_CORE1_PWR_CON_CORE_PWRDN_ENA_SHIFT (0U) +#define PMU_CORE1_PWR_CON_CORE_PWRDN_ENA_MASK (0x1U << PMU_CORE1_PWR_CON_CORE_PWRDN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CORE1_PWR_CON_CORE_PWROFF_ENA_SHIFT (1U) +#define PMU_CORE1_PWR_CON_CORE_PWROFF_ENA_MASK (0x1U << PMU_CORE1_PWR_CON_CORE_PWROFF_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE1_PWR_CON_CORE_CPU_PWRDN_ENA_SHIFT (2U) +#define PMU_CORE1_PWR_CON_CORE_CPU_PWRDN_ENA_MASK (0x1U << PMU_CORE1_PWR_CON_CORE_CPU_PWRDN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CORE1_PWR_CON_CORE_PWR_CNT_ENA_SHIFT (3U) +#define PMU_CORE1_PWR_CON_CORE_PWR_CNT_ENA_MASK (0x1U << PMU_CORE1_PWR_CON_CORE_PWR_CNT_ENA_SHIFT) /* 0x00000008 */ +/* CORE0_PWR_SFTCON */ +#define PMU_CORE0_PWR_SFTCON_OFFSET (0x8058U) +#define PMU_CORE0_PWR_SFTCON_CORE_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CORE0_PWR_SFTCON_CORE_PWRDN_SFTENA_MASK (0x1U << PMU_CORE0_PWR_SFTCON_CORE_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CORE0_PWR_SFTCON_CORE_PWROFF_SFTENA_SHIFT (1U) +#define PMU_CORE0_PWR_SFTCON_CORE_PWROFF_SFTENA_MASK (0x1U << PMU_CORE0_PWR_SFTCON_CORE_PWROFF_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE0_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_SHIFT (2U) +#define PMU_CORE0_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CORE0_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_CORE0_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_SHIFT (3U) +#define PMU_CORE0_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_MASK (0x1U << PMU_CORE0_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_SHIFT) /* 0x00000008 */ +/* CORE1_PWR_SFTCON */ +#define PMU_CORE1_PWR_SFTCON_OFFSET (0x805CU) +#define PMU_CORE1_PWR_SFTCON_CORE_PWRDN_SFTENA_SHIFT (0U) +#define PMU_CORE1_PWR_SFTCON_CORE_PWRDN_SFTENA_MASK (0x1U << PMU_CORE1_PWR_SFTCON_CORE_PWRDN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CORE1_PWR_SFTCON_CORE_PWROFF_SFTENA_SHIFT (1U) +#define PMU_CORE1_PWR_SFTCON_CORE_PWROFF_SFTENA_MASK (0x1U << PMU_CORE1_PWR_SFTCON_CORE_PWROFF_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE1_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_SHIFT (2U) +#define PMU_CORE1_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_MASK (0x1U << PMU_CORE1_PWR_SFTCON_CORE_CPU_PWRDN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_CORE1_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_SHIFT (3U) +#define PMU_CORE1_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_MASK (0x1U << PMU_CORE1_PWR_SFTCON_CORE_DWN_ACK_CLAMP_ENA_SHIFT) /* 0x00000008 */ +/* CORE0_AUTO_PWR_CON */ +#define PMU_CORE0_AUTO_PWR_CON_OFFSET (0x8060U) +#define PMU_CORE0_AUTO_PWR_CON_CORE_LP_EN_SHIFT (0U) +#define PMU_CORE0_AUTO_PWR_CON_CORE_LP_EN_MASK (0x1U << PMU_CORE0_AUTO_PWR_CON_CORE_LP_EN_SHIFT) /* 0x00000001 */ +#define PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_MASK (0x1U << PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_SHIFT (3U) +#define PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_MASK (0x1U << PMU_CORE0_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_SHIFT) /* 0x00000008 */ +/* CORE1_AUTO_PWR_CON */ +#define PMU_CORE1_AUTO_PWR_CON_OFFSET (0x8064U) +#define PMU_CORE1_AUTO_PWR_CON_CORE_LP_EN_SHIFT (0U) +#define PMU_CORE1_AUTO_PWR_CON_CORE_LP_EN_MASK (0x1U << PMU_CORE1_AUTO_PWR_CON_CORE_LP_EN_SHIFT) /* 0x00000001 */ +#define PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_SHIFT (1U) +#define PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_MASK (0x1U << PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_SHIFT (3U) +#define PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_MASK (0x1U << PMU_CORE1_AUTO_PWR_CON_CORE_INT_WAKEUP_SFTENA_SHIFT) /* 0x00000008 */ +/* CLUSTER_BIU_AUTO_CON */ +#define PMU_CLUSTER_BIU_AUTO_CON_OFFSET (0x8068U) +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE0_ENA_SHIFT (0U) +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE0_ENA_MASK (0x1U << PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE0_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE1_ENA_SHIFT (1U) +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE1_ENA_MASK (0x1U << PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_BIGCORE1_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_DSU_ENA_SHIFT (2U) +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_DSU_ENA_MASK (0x1U << PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_DSU_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_LITDSU_ENA_SHIFT (3U) +#define PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_LITDSU_ENA_MASK (0x1U << PMU_CLUSTER_BIU_AUTO_CON_BIU_AUTO_LITDSU_ENA_SHIFT) /* 0x00000008 */ +/* CLUSTER_BIU_IDLE_CON */ +#define PMU_CLUSTER_BIU_IDLE_CON_OFFSET (0x8070U) +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE0_ENA_SHIFT (0U) +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE0_ENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE0_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE1_ENA_SHIFT (2U) +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE1_ENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_BIGCORE1_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_DSU_ENA_SHIFT (4U) +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_DSU_ENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_DSU_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_LITDSU_ENA_SHIFT (5U) +#define PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_LITDSU_ENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_CON_IDLE_REQ_LITDSU_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CLUSTER_BIU_IDLE_CON_ADB400_CORE_QCH_ENA_SHIFT (6U) +#define PMU_CLUSTER_BIU_IDLE_CON_ADB400_CORE_QCH_ENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_CON_ADB400_CORE_QCH_ENA_SHIFT) /* 0x00000040 */ +/* CLUSTER_BIU_IDLE_SFTCON */ +#define PMU_CLUSTER_BIU_IDLE_SFTCON_OFFSET (0x8074U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE0_SFTENA_SHIFT (0U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE0_SFTENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE0_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE1_SFTENA_SHIFT (2U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE1_SFTENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_BIGCORE1_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_DSU_SFTENA_SHIFT (4U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_DSU_SFTENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_DSU_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_LITDSU_SFTENA_SHIFT (5U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_LITDSU_SFTENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_SFTCON_IDLE_REQ_LITDSU_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_CLUSTER_BIU_IDLE_SFTCON_ADB400_CORE_QCH_SFTENA_SHIFT (6U) +#define PMU_CLUSTER_BIU_IDLE_SFTCON_ADB400_CORE_QCH_SFTENA_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_SFTCON_ADB400_CORE_QCH_SFTENA_SHIFT) /* 0x00000040 */ +/* CLUSTER_BIU_IDLE_ACK_STS */ +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_OFFSET (0x8078U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS (0x0U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE0_SHIFT (0U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE0_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE0_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE1_SHIFT (1U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE1_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_BIGCORE1_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_DSU_SHIFT (2U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_DSU_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_DSU_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_LITDSU_SHIFT (3U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_LITDSU_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_ACK_STS_IDLE_ACK_LITDSU_SHIFT) /* 0x00000008 */ +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_ADB400_CORE_PACCEPT_SHIFT (4U) +#define PMU_CLUSTER_BIU_IDLE_ACK_STS_ADB400_CORE_PACCEPT_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_ACK_STS_ADB400_CORE_PACCEPT_SHIFT) /* 0x00000010 */ +/* CLUSTER_BIU_IDLE_STS */ +#define PMU_CLUSTER_BIU_IDLE_STS_OFFSET (0x807CU) +#define PMU_CLUSTER_BIU_IDLE_STS (0x0U) +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE0_SHIFT (0U) +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE0_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE0_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE1_SHIFT (1U) +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE1_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_STS_IDLE_BIGCORE1_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_DSU_SHIFT (2U) +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_DSU_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_STS_IDLE_DSU_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_LITDSU_SHIFT (3U) +#define PMU_CLUSTER_BIU_IDLE_STS_IDLE_LITDSU_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_STS_IDLE_LITDSU_SHIFT) /* 0x00000008 */ +#define PMU_CLUSTER_BIU_IDLE_STS_ADB400_CORE_PACTIVE_SHIFT (4U) +#define PMU_CLUSTER_BIU_IDLE_STS_ADB400_CORE_PACTIVE_MASK (0x1U << PMU_CLUSTER_BIU_IDLE_STS_ADB400_CORE_PACTIVE_SHIFT) /* 0x00000010 */ +/* CLUSTER_STS */ +#define PMU_CLUSTER_STS_OFFSET (0x8080U) +#define PMU_CLUSTER_STS (0x0U) +#define PMU_CLUSTER_STS_PD_CPU0_DWN_STAT_SHIFT (0U) +#define PMU_CLUSTER_STS_PD_CPU0_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU0_DWN_STAT_SHIFT) /* 0x00000001 */ +#define PMU_CLUSTER_STS_PD_CPU1_DWN_STAT_SHIFT (1U) +#define PMU_CLUSTER_STS_PD_CPU1_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU1_DWN_STAT_SHIFT) /* 0x00000002 */ +#define PMU_CLUSTER_STS_PD_CPU2_DWN_STAT_SHIFT (2U) +#define PMU_CLUSTER_STS_PD_CPU2_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU2_DWN_STAT_SHIFT) /* 0x00000004 */ +#define PMU_CLUSTER_STS_PD_CPU3_DWN_STAT_SHIFT (3U) +#define PMU_CLUSTER_STS_PD_CPU3_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU3_DWN_STAT_SHIFT) /* 0x00000008 */ +#define PMU_CLUSTER_STS_PD_CPU4_DWN_STAT_SHIFT (4U) +#define PMU_CLUSTER_STS_PD_CPU4_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU4_DWN_STAT_SHIFT) /* 0x00000010 */ +#define PMU_CLUSTER_STS_PD_CPU5_DWN_STAT_SHIFT (5U) +#define PMU_CLUSTER_STS_PD_CPU5_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU5_DWN_STAT_SHIFT) /* 0x00000020 */ +#define PMU_CLUSTER_STS_PD_CPU6_DWN_STAT_SHIFT (6U) +#define PMU_CLUSTER_STS_PD_CPU6_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU6_DWN_STAT_SHIFT) /* 0x00000040 */ +#define PMU_CLUSTER_STS_PD_CPU7_DWN_STAT_SHIFT (7U) +#define PMU_CLUSTER_STS_PD_CPU7_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CPU7_DWN_STAT_SHIFT) /* 0x00000080 */ +#define PMU_CLUSTER_STS_PD_CORE0_DWN_STAT_SHIFT (8U) +#define PMU_CLUSTER_STS_PD_CORE0_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CORE0_DWN_STAT_SHIFT) /* 0x00000100 */ +#define PMU_CLUSTER_STS_PD_CORE1_DWN_STAT_SHIFT (9U) +#define PMU_CLUSTER_STS_PD_CORE1_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_CORE1_DWN_STAT_SHIFT) /* 0x00000200 */ +#define PMU_CLUSTER_STS_PD_DSU_DWN_STAT_SHIFT (10U) +#define PMU_CLUSTER_STS_PD_DSU_DWN_STAT_MASK (0x1U << PMU_CLUSTER_STS_PD_DSU_DWN_STAT_SHIFT) /* 0x00000400 */ +#define PMU_CLUSTER_STS_CPU0_HANDSHAKE_SHIFT (11U) +#define PMU_CLUSTER_STS_CPU0_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU0_HANDSHAKE_SHIFT) /* 0x00000800 */ +#define PMU_CLUSTER_STS_CPU1_HANDSHAKE_SHIFT (12U) +#define PMU_CLUSTER_STS_CPU1_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU1_HANDSHAKE_SHIFT) /* 0x00001000 */ +#define PMU_CLUSTER_STS_CPU2_HANDSHAKE_SHIFT (13U) +#define PMU_CLUSTER_STS_CPU2_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU2_HANDSHAKE_SHIFT) /* 0x00002000 */ +#define PMU_CLUSTER_STS_CPU3_HANDSHAKE_SHIFT (14U) +#define PMU_CLUSTER_STS_CPU3_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU3_HANDSHAKE_SHIFT) /* 0x00004000 */ +#define PMU_CLUSTER_STS_CPU4_HANDSHAKE_SHIFT (15U) +#define PMU_CLUSTER_STS_CPU4_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU4_HANDSHAKE_SHIFT) /* 0x00008000 */ +#define PMU_CLUSTER_STS_CPU5_HANDSHAKE_SHIFT (16U) +#define PMU_CLUSTER_STS_CPU5_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU5_HANDSHAKE_SHIFT) /* 0x00010000 */ +#define PMU_CLUSTER_STS_CPU6_HANDSHAKE_SHIFT (17U) +#define PMU_CLUSTER_STS_CPU6_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU6_HANDSHAKE_SHIFT) /* 0x00020000 */ +#define PMU_CLUSTER_STS_CPU7_HANDSHAKE_SHIFT (18U) +#define PMU_CLUSTER_STS_CPU7_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_CPU7_HANDSHAKE_SHIFT) /* 0x00040000 */ +#define PMU_CLUSTER_STS_DSU_HANDSHAKE_SHIFT (19U) +#define PMU_CLUSTER_STS_DSU_HANDSHAKE_MASK (0x1U << PMU_CLUSTER_STS_DSU_HANDSHAKE_SHIFT) /* 0x00080000 */ +#define PMU_CLUSTER_STS_CPU0_STANDBYWFI_SHIFT (20U) +#define PMU_CLUSTER_STS_CPU0_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU0_STANDBYWFI_SHIFT) /* 0x00100000 */ +#define PMU_CLUSTER_STS_CPU1_STANDBYWFI_SHIFT (21U) +#define PMU_CLUSTER_STS_CPU1_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU1_STANDBYWFI_SHIFT) /* 0x00200000 */ +#define PMU_CLUSTER_STS_CPU2_STANDBYWFI_SHIFT (22U) +#define PMU_CLUSTER_STS_CPU2_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU2_STANDBYWFI_SHIFT) /* 0x00400000 */ +#define PMU_CLUSTER_STS_CPU3_STANDBYWFI_SHIFT (23U) +#define PMU_CLUSTER_STS_CPU3_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU3_STANDBYWFI_SHIFT) /* 0x00800000 */ +#define PMU_CLUSTER_STS_CPU4_STANDBYWFI_SHIFT (24U) +#define PMU_CLUSTER_STS_CPU4_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU4_STANDBYWFI_SHIFT) /* 0x01000000 */ +#define PMU_CLUSTER_STS_CPU5_STANDBYWFI_SHIFT (25U) +#define PMU_CLUSTER_STS_CPU5_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU5_STANDBYWFI_SHIFT) /* 0x02000000 */ +#define PMU_CLUSTER_STS_CPU6_STANDBYWFI_SHIFT (26U) +#define PMU_CLUSTER_STS_CPU6_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU6_STANDBYWFI_SHIFT) /* 0x04000000 */ +#define PMU_CLUSTER_STS_CPU7_STANDBYWFI_SHIFT (27U) +#define PMU_CLUSTER_STS_CPU7_STANDBYWFI_MASK (0x1U << PMU_CLUSTER_STS_CPU7_STANDBYWFI_SHIFT) /* 0x08000000 */ +/* CLUSTER_POWER_STS0 */ +#define PMU_CLUSTER_POWER_STS0_OFFSET (0x8084U) +#define PMU_CLUSTER_POWER_STS0 (0x0U) +#define PMU_CLUSTER_POWER_STS0_CPU0_POWER_STATE_SHIFT (0U) +#define PMU_CLUSTER_POWER_STS0_CPU0_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU0_POWER_STATE_SHIFT) /* 0x00000007 */ +#define PMU_CLUSTER_POWER_STS0_CPU1_POWER_STATE_SHIFT (4U) +#define PMU_CLUSTER_POWER_STS0_CPU1_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU1_POWER_STATE_SHIFT) /* 0x00000070 */ +#define PMU_CLUSTER_POWER_STS0_CPU2_POWER_STATE_SHIFT (8U) +#define PMU_CLUSTER_POWER_STS0_CPU2_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU2_POWER_STATE_SHIFT) /* 0x00000700 */ +#define PMU_CLUSTER_POWER_STS0_CPU3_POWER_STATE_SHIFT (12U) +#define PMU_CLUSTER_POWER_STS0_CPU3_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU3_POWER_STATE_SHIFT) /* 0x00007000 */ +#define PMU_CLUSTER_POWER_STS0_CPU4_POWER_STATE_SHIFT (16U) +#define PMU_CLUSTER_POWER_STS0_CPU4_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU4_POWER_STATE_SHIFT) /* 0x00070000 */ +#define PMU_CLUSTER_POWER_STS0_CPU5_POWER_STATE_SHIFT (20U) +#define PMU_CLUSTER_POWER_STS0_CPU5_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU5_POWER_STATE_SHIFT) /* 0x00700000 */ +#define PMU_CLUSTER_POWER_STS0_CPU6_POWER_STATE_SHIFT (24U) +#define PMU_CLUSTER_POWER_STS0_CPU6_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU6_POWER_STATE_SHIFT) /* 0x07000000 */ +#define PMU_CLUSTER_POWER_STS0_CPU7_POWER_STATE_SHIFT (28U) +#define PMU_CLUSTER_POWER_STS0_CPU7_POWER_STATE_MASK (0x7U << PMU_CLUSTER_POWER_STS0_CPU7_POWER_STATE_SHIFT) /* 0x70000000 */ +/* CLUSTER_POWER_STS1 */ +#define PMU_CLUSTER_POWER_STS1_OFFSET (0x8088U) +#define PMU_CLUSTER_POWER_STS1 (0x0U) +#define PMU_CLUSTER_POWER_STS1_CORE0_POWER_STATE_SHIFT (0U) +#define PMU_CLUSTER_POWER_STS1_CORE0_POWER_STATE_MASK (0xFU << PMU_CLUSTER_POWER_STS1_CORE0_POWER_STATE_SHIFT) /* 0x0000000F */ +#define PMU_CLUSTER_POWER_STS1_CORE1_POWER_STATE_SHIFT (4U) +#define PMU_CLUSTER_POWER_STS1_CORE1_POWER_STATE_MASK (0xFU << PMU_CLUSTER_POWER_STS1_CORE1_POWER_STATE_SHIFT) /* 0x000000F0 */ +#define PMU_CLUSTER_POWER_STS1_DSU_POWER_STATE_SHIFT (8U) +#define PMU_CLUSTER_POWER_STS1_DSU_POWER_STATE_MASK (0xFU << PMU_CLUSTER_POWER_STS1_DSU_POWER_STATE_SHIFT) /* 0x00000F00 */ +/* CLUSTER_PCHANNEL_STS0 */ +#define PMU_CLUSTER_PCHANNEL_STS0_OFFSET (0x808CU) +#define PMU_CLUSTER_PCHANNEL_STS0 (0x0U) +#define PMU_CLUSTER_PCHANNEL_STS0_CPU0_PCHANNEL_STATUS_SHIFT (0U) +#define PMU_CLUSTER_PCHANNEL_STS0_CPU0_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS0_CPU0_PCHANNEL_STATUS_SHIFT) /* 0x0000003F */ +#define PMU_CLUSTER_PCHANNEL_STS0_CPU1_PCHANNEL_STATUS_SHIFT (8U) +#define PMU_CLUSTER_PCHANNEL_STS0_CPU1_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS0_CPU1_PCHANNEL_STATUS_SHIFT) /* 0x00003F00 */ +#define PMU_CLUSTER_PCHANNEL_STS0_CPU2_PCHANNEL_STATUS_SHIFT (16U) +#define PMU_CLUSTER_PCHANNEL_STS0_CPU2_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS0_CPU2_PCHANNEL_STATUS_SHIFT) /* 0x003F0000 */ +#define PMU_CLUSTER_PCHANNEL_STS0_CPU3_PCHANNEL_STATUS_SHIFT (24U) +#define PMU_CLUSTER_PCHANNEL_STS0_CPU3_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS0_CPU3_PCHANNEL_STATUS_SHIFT) /* 0x3F000000 */ +/* CLUSTER_PCHANNEL_STS1 */ +#define PMU_CLUSTER_PCHANNEL_STS1_OFFSET (0x8090U) +#define PMU_CLUSTER_PCHANNEL_STS1 (0x0U) +#define PMU_CLUSTER_PCHANNEL_STS1_CPU4_PCHANNEL_STATUS_SHIFT (0U) +#define PMU_CLUSTER_PCHANNEL_STS1_CPU4_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS1_CPU4_PCHANNEL_STATUS_SHIFT) /* 0x0000003F */ +#define PMU_CLUSTER_PCHANNEL_STS1_CPU5_PCHANNEL_STATUS_SHIFT (8U) +#define PMU_CLUSTER_PCHANNEL_STS1_CPU5_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS1_CPU5_PCHANNEL_STATUS_SHIFT) /* 0x00003F00 */ +#define PMU_CLUSTER_PCHANNEL_STS1_CPU6_PCHANNEL_STATUS_SHIFT (16U) +#define PMU_CLUSTER_PCHANNEL_STS1_CPU6_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS1_CPU6_PCHANNEL_STATUS_SHIFT) /* 0x003F0000 */ +#define PMU_CLUSTER_PCHANNEL_STS1_CPU7_PCHANNEL_STATUS_SHIFT (24U) +#define PMU_CLUSTER_PCHANNEL_STS1_CPU7_PCHANNEL_STATUS_MASK (0x3FU << PMU_CLUSTER_PCHANNEL_STS1_CPU7_PCHANNEL_STATUS_SHIFT) /* 0x3F000000 */ +/* CLUSTER_PCHANNEL_STS2 */ +#define PMU_CLUSTER_PCHANNEL_STS2_OFFSET (0x8094U) +#define PMU_CLUSTER_PCHANNEL_STS2 (0x0U) +#define PMU_CLUSTER_PCHANNEL_STS2_DSU_PCHANNEL_STATUS_SHIFT (0U) +#define PMU_CLUSTER_PCHANNEL_STS2_DSU_PCHANNEL_STATUS_MASK (0x1FFU << PMU_CLUSTER_PCHANNEL_STS2_DSU_PCHANNEL_STATUS_SHIFT) /* 0x000001FF */ +/* CPU_PWR_CHAIN_STABLE_CON */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_OFFSET (0x8098U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRUP_STABLE_ENA_SHIFT (0U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRUP_STABLE_ENA_SHIFT) /* 0x00000001 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRUP_STABLE_ENA_SHIFT (1U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRUP_STABLE_ENA_SHIFT) /* 0x00000002 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRUP_STABLE_ENA_SHIFT (2U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRUP_STABLE_ENA_SHIFT) /* 0x00000004 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRUP_STABLE_ENA_SHIFT (3U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRUP_STABLE_ENA_SHIFT) /* 0x00000008 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRUP_STABLE_ENA_SHIFT (4U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRUP_STABLE_ENA_SHIFT) /* 0x00000010 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRUP_STABLE_ENA_SHIFT (5U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRUP_STABLE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRUP_STABLE_ENA_SHIFT (6U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRUP_STABLE_ENA_SHIFT) /* 0x00000040 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRUP_STABLE_ENA_SHIFT (7U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRUP_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRUP_STABLE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRDN_STABLE_ENA_SHIFT (8U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU0_PWRDN_STABLE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRDN_STABLE_ENA_SHIFT (9U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU1_PWRDN_STABLE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRDN_STABLE_ENA_SHIFT (10U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU2_PWRDN_STABLE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRDN_STABLE_ENA_SHIFT (11U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU3_PWRDN_STABLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRDN_STABLE_ENA_SHIFT (12U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU4_PWRDN_STABLE_ENA_SHIFT) /* 0x00001000 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRDN_STABLE_ENA_SHIFT (13U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU5_PWRDN_STABLE_ENA_SHIFT) /* 0x00002000 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRDN_STABLE_ENA_SHIFT (14U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU6_PWRDN_STABLE_ENA_SHIFT) /* 0x00004000 */ +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRDN_STABLE_ENA_SHIFT (15U) +#define PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRDN_STABLE_ENA_MASK (0x1U << PMU_CPU_PWR_CHAIN_STABLE_CON_CPU7_PWRDN_STABLE_ENA_SHIFT) /* 0x00008000 */ +/* DSU_MEM_PWR_CON */ +#define PMU_DSU_MEM_PWR_CON_OFFSET (0x809CU) +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_ENA_SHIFT (0U) +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_ENA_MASK (0xFU << PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_ENA_SHIFT) /* 0x0000000F */ +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_ENA_SHIFT (4U) +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_ENA_MASK (0xFU << PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_ENA_SHIFT) /* 0x000000F0 */ +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_SFTENA_SHIFT (8U) +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_SFTENA_MASK (0xFU << PMU_DSU_MEM_PWR_CON_DSU_MEM_SD_SFTENA_SHIFT) /* 0x00000F00 */ +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_SFTENA_SHIFT (12U) +#define PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_SFTENA_MASK (0xFU << PMU_DSU_MEM_PWR_CON_DSU_MEM_LS_SFTENA_SHIFT) /* 0x0000F000 */ +/* DSU_STABLE_CNT */ +#define PMU_DSU_STABLE_CNT_OFFSET (0x80B0U) +#define PMU_DSU_STABLE_CNT_DSU_STABLE_CNT_SHIFT (0U) +#define PMU_DSU_STABLE_CNT_DSU_STABLE_CNT_MASK (0xFFFFFU << PMU_DSU_STABLE_CNT_DSU_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* DSU_PWRUP_CNT */ +#define PMU_DSU_PWRUP_CNT_OFFSET (0x80B4U) +#define PMU_DSU_PWRUP_CNT_DSU_PWRUP_CNT_SHIFT (0U) +#define PMU_DSU_PWRUP_CNT_DSU_PWRUP_CNT_MASK (0xFFFFFU << PMU_DSU_PWRUP_CNT_DSU_PWRUP_CNT_SHIFT) /* 0x000FFFFF */ +/* DSU_PWRDN_CNT */ +#define PMU_DSU_PWRDN_CNT_OFFSET (0x80B8U) +#define PMU_DSU_PWRDN_CNT_DSU_PWRDN_CNT_SHIFT (0U) +#define PMU_DSU_PWRDN_CNT_DSU_PWRDN_CNT_MASK (0xFFFFFU << PMU_DSU_PWRDN_CNT_DSU_PWRDN_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE0_STABLE_CNT */ +#define PMU_CORE0_STABLE_CNT_OFFSET (0x80BCU) +#define PMU_CORE0_STABLE_CNT_CORE0_STABLE_CNT_SHIFT (0U) +#define PMU_CORE0_STABLE_CNT_CORE0_STABLE_CNT_MASK (0xFFFFFU << PMU_CORE0_STABLE_CNT_CORE0_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE0_PWRUP_CNT */ +#define PMU_CORE0_PWRUP_CNT_OFFSET (0x80C0U) +#define PMU_CORE0_PWRUP_CNT_CORE0_PWRUP_CNT_SHIFT (0U) +#define PMU_CORE0_PWRUP_CNT_CORE0_PWRUP_CNT_MASK (0xFFFFFU << PMU_CORE0_PWRUP_CNT_CORE0_PWRUP_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE0_PWRDN_CNT */ +#define PMU_CORE0_PWRDN_CNT_OFFSET (0x80C4U) +#define PMU_CORE0_PWRDN_CNT_CORE0_PWRDN_CNT_SHIFT (0U) +#define PMU_CORE0_PWRDN_CNT_CORE0_PWRDN_CNT_MASK (0xFFFFFU << PMU_CORE0_PWRDN_CNT_CORE0_PWRDN_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE1_STABLE_CNT */ +#define PMU_CORE1_STABLE_CNT_OFFSET (0x80C8U) +#define PMU_CORE1_STABLE_CNT_CORE1_STABLE_CNT_SHIFT (0U) +#define PMU_CORE1_STABLE_CNT_CORE1_STABLE_CNT_MASK (0xFFFFFU << PMU_CORE1_STABLE_CNT_CORE1_STABLE_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE1_PWRUP_CNT */ +#define PMU_CORE1_PWRUP_CNT_OFFSET (0x80CCU) +#define PMU_CORE1_PWRUP_CNT_CORE1_PWRUP_CNT_SHIFT (0U) +#define PMU_CORE1_PWRUP_CNT_CORE1_PWRUP_CNT_MASK (0xFFFFFU << PMU_CORE1_PWRUP_CNT_CORE1_PWRUP_CNT_SHIFT) /* 0x000FFFFF */ +/* CORE1_PWRDN_CNT */ +#define PMU_CORE1_PWRDN_CNT_OFFSET (0x80D0U) +#define PMU_CORE1_PWRDN_CNT_CORE1_PWRDN_CNT_SHIFT (0U) +#define PMU_CORE1_PWRDN_CNT_CORE1_PWRDN_CNT_MASK (0xFFFFFU << PMU_CORE1_PWRDN_CNT_CORE1_PWRDN_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU0_DBG_RST_CNT */ +#define PMU_CPU0_DBG_RST_CNT_OFFSET (0x80D4U) +#define PMU_CPU0_DBG_RST_CNT_CPU0_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU0_DBG_RST_CNT_CPU0_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU0_DBG_RST_CNT_CPU0_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU1_DBG_RST_CNT */ +#define PMU_CPU1_DBG_RST_CNT_OFFSET (0x80D8U) +#define PMU_CPU1_DBG_RST_CNT_CPU1_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU1_DBG_RST_CNT_CPU1_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU1_DBG_RST_CNT_CPU1_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU2_DBG_RST_CNT */ +#define PMU_CPU2_DBG_RST_CNT_OFFSET (0x80DCU) +#define PMU_CPU2_DBG_RST_CNT_CPU2_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU2_DBG_RST_CNT_CPU2_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU2_DBG_RST_CNT_CPU2_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU3_DBG_RST_CNT */ +#define PMU_CPU3_DBG_RST_CNT_OFFSET (0x80E0U) +#define PMU_CPU3_DBG_RST_CNT_CPU3_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU3_DBG_RST_CNT_CPU3_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU3_DBG_RST_CNT_CPU3_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU4_DBG_RST_CNT */ +#define PMU_CPU4_DBG_RST_CNT_OFFSET (0x80E4U) +#define PMU_CPU4_DBG_RST_CNT_CPU4_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU4_DBG_RST_CNT_CPU4_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU4_DBG_RST_CNT_CPU4_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU5_DBG_RST_CNT */ +#define PMU_CPU5_DBG_RST_CNT_OFFSET (0x80E8U) +#define PMU_CPU5_DBG_RST_CNT_CPU5_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU5_DBG_RST_CNT_CPU5_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU5_DBG_RST_CNT_CPU5_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU6_DBG_RST_CNT */ +#define PMU_CPU6_DBG_RST_CNT_OFFSET (0x80ECU) +#define PMU_CPU6_DBG_RST_CNT_CPU6_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU6_DBG_RST_CNT_CPU6_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU6_DBG_RST_CNT_CPU6_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* CPU7_DBG_RST_CNT */ +#define PMU_CPU7_DBG_RST_CNT_OFFSET (0x80F0U) +#define PMU_CPU7_DBG_RST_CNT_CPU7_DBG_RST_CNT_SHIFT (0U) +#define PMU_CPU7_DBG_RST_CNT_CPU7_DBG_RST_CNT_MASK (0xFFFFFU << PMU_CPU7_DBG_RST_CNT_CPU7_DBG_RST_CNT_SHIFT) /* 0x000FFFFF */ +/* BIU_IDLE_CON0 */ +#define PMU_BIU_IDLE_CON0_OFFSET (0x8100U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_GPU_ENA_SHIFT (0U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_GPU_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_GPU_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPUTOP_ENA_SHIFT (1U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPUTOP_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_NPUTOP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPU1_ENA_SHIFT (2U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPU1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_NPU1_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPU2_ENA_SHIFT (3U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_NPU2_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_NPU2_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VENC0_ENA_SHIFT (4U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VENC0_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VENC0_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VENC1_ENA_SHIFT (5U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VENC1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VENC1_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC0_ENA_SHIFT (6U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC0_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC0_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC1_ENA_SHIFT (7U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_RKVDEC1_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VDPU_ENA_SHIFT (8U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VDPU_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VDPU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_AV1_ENA_SHIFT (9U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_AV1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_AV1_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VI_ENA_SHIFT (10U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VI_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VI_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_ISP1_ENA_SHIFT (11U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_ISP1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_ISP1_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RGA31_ENA_SHIFT (12U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_RGA31_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_RGA31_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_ENA_SHIFT (13U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_CHANNEL_ENA_SHIFT (14U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_CHANNEL_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VOP_CHANNEL_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VO0_ENA_SHIFT (15U) +#define PMU_BIU_IDLE_CON0_IDLE_REQ_VO0_ENA_MASK (0x1U << PMU_BIU_IDLE_CON0_IDLE_REQ_VO0_ENA_SHIFT) /* 0x00008000 */ +/* BIU_IDLE_CON1 */ +#define PMU_BIU_IDLE_CON1_OFFSET (0x8104U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_VO1_ENA_SHIFT (0U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_VO1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_VO1_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_AUDIO_ENA_SHIFT (1U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_AUDIO_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_AUDIO_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_NVM_ENA_SHIFT (2U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_NVM_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_NVM_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SDIO_ENA_SHIFT (3U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SDIO_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_SDIO_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_USB_ENA_SHIFT (4U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_USB_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_USB_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_PHP_ENA_SHIFT (5U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_PHP_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_PHP_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_VO1USBTOP_ENA_SHIFT (6U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_VO1USBTOP_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_VO1USBTOP_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_ENA_SHIFT (7U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_CENTER_CHANNEL_ENA_SHIFT (8U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_CENTER_CHANNEL_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_CENTER_CHANNEL_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_ENA_SHIFT (9U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_ENA_SHIFT (10U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_CHANNEL_ENA_SHIFT (11U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_CHANNEL_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_CENTER_CHANNEL_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH0_ENA_SHIFT (12U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH0_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH0_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH1_ENA_SHIFT (13U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH1_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH1_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH2_ENA_SHIFT (14U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH2_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH2_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH3_ENA_SHIFT (15U) +#define PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH3_ENA_MASK (0x1U << PMU_BIU_IDLE_CON1_IDLE_REQ_DDRSCH3_ENA_SHIFT) /* 0x00008000 */ +/* BIU_IDLE_CON2 */ +#define PMU_BIU_IDLE_CON2_OFFSET (0x8108U) +#define PMU_BIU_IDLE_CON2_IDLE_REQ_CENTER_DDRSCH_ENA_SHIFT (0U) +#define PMU_BIU_IDLE_CON2_IDLE_REQ_CENTER_DDRSCH_ENA_MASK (0x1U << PMU_BIU_IDLE_CON2_IDLE_REQ_CENTER_DDRSCH_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_CON2_IDLE_REQ_BUS_ENA_SHIFT (1U) +#define PMU_BIU_IDLE_CON2_IDLE_REQ_BUS_ENA_MASK (0x1U << PMU_BIU_IDLE_CON2_IDLE_REQ_BUS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_CON2_IDLE_REQ_TOP_ENA_SHIFT (2U) +#define PMU_BIU_IDLE_CON2_IDLE_REQ_TOP_ENA_MASK (0x1U << PMU_BIU_IDLE_CON2_IDLE_REQ_TOP_ENA_SHIFT) /* 0x00000004 */ +/* BIU_IDLE_SFTCON0 */ +#define PMU_BIU_IDLE_SFTCON0_OFFSET (0x810CU) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_GPU_SFTENA_SHIFT (0U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_GPU_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_GPU_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPUTOP_SFTENA_SHIFT (1U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPUTOP_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPUTOP_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU1_SFTENA_SHIFT (2U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU1_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU2_SFTENA_SHIFT (3U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU2_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_NPU2_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC0_SFTENA_SHIFT (4U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC0_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC0_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC1_SFTENA_SHIFT (5U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VENC1_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC0_SFTENA_SHIFT (6U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC0_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC0_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC1_SFTENA_SHIFT (7U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RKVDEC1_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VDPU_SFTENA_SHIFT (8U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VDPU_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VDPU_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_AV1_SFTENA_SHIFT (9U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_AV1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_AV1_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VI_SFTENA_SHIFT (10U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VI_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VI_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_ISP1_SFTENA_SHIFT (11U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_ISP1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_ISP1_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RGA31_SFTENA_SHIFT (12U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RGA31_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_RGA31_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_SFTENA_SHIFT (13U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_CHANNEL_SFTENA_SHIFT (14U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_CHANNEL_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VOP_CHANNEL_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VO0_SFTENA_SHIFT (15U) +#define PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VO0_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON0_IDLE_REQ_VO0_SFTENA_SHIFT) /* 0x00008000 */ +/* BIU_IDLE_SFTCON1 */ +#define PMU_BIU_IDLE_SFTCON1_OFFSET (0x8110U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1_SFTENA_SHIFT (0U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_AUDIO_SFTENA_SHIFT (1U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_AUDIO_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_AUDIO_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_NVM_SFTENA_SHIFT (2U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_NVM_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_NVM_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SDIO_SFTENA_SHIFT (3U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SDIO_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SDIO_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_USB_SFTENA_SHIFT (4U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_USB_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_USB_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_PHP_SFTENA_SHIFT (5U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_PHP_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_PHP_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1USBTOP_SFTENA_SHIFT (6U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1USBTOP_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_VO1USBTOP_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_SFTENA_SHIFT (7U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_CENTER_CHANNEL_SFTENA_SHIFT (8U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_CENTER_CHANNEL_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_CENTER_CHANNEL_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_SFTENA_SHIFT (9U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_SECURE_VO1USB_CHANNEL_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_SFTENA_SHIFT (10U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_CHANNEL_SFTENA_SHIFT (11U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_CHANNEL_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_CENTER_CHANNEL_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH0_SFTENA_SHIFT (12U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH0_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH0_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH1_SFTENA_SHIFT (13U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH1_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH1_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH2_SFTENA_SHIFT (14U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH2_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH2_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH3_SFTENA_SHIFT (15U) +#define PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH3_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON1_IDLE_REQ_DDRSCH3_SFTENA_SHIFT) /* 0x00008000 */ +/* BIU_IDLE_SFTCON2 */ +#define PMU_BIU_IDLE_SFTCON2_OFFSET (0x8114U) +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_CENTER_DDRSCH_SFTENA_SHIFT (0U) +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_CENTER_DDRSCH_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON2_IDLE_REQ_CENTER_DDRSCH_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_BUS_SFTENA_SHIFT (1U) +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_BUS_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON2_IDLE_REQ_BUS_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_TOP_SFTENA_SHIFT (2U) +#define PMU_BIU_IDLE_SFTCON2_IDLE_REQ_TOP_SFTENA_MASK (0x1U << PMU_BIU_IDLE_SFTCON2_IDLE_REQ_TOP_SFTENA_SHIFT) /* 0x00000004 */ +/* BIU_IDLE_ACK_STS0 */ +#define PMU_BIU_IDLE_ACK_STS0_OFFSET (0x8118U) +#define PMU_BIU_IDLE_ACK_STS0 (0x0U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_GPU_SHIFT (0U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_GPU_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_GPU_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPUTOP_SHIFT (1U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPUTOP_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPUTOP_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU1_SHIFT (2U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU1_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU2_SHIFT (3U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU2_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NPU2_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC0_SHIFT (4U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC0_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC0_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC1_SHIFT (5U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VENC1_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC0_SHIFT (6U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC0_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC0_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC1_SHIFT (7U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RKVDEC1_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VDPU_SHIFT (8U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VDPU_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VDPU_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AV1_SHIFT (9U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AV1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AV1_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VI_SHIFT (10U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VI_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VI_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_ISP1_SHIFT (11U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_ISP1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_ISP1_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RGA31_SHIFT (12U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RGA31_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_RGA31_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_SHIFT (13U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_CHANNEL_SHIFT (14U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VOP_CHANNEL_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO0_SHIFT (15U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO0_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO0_SHIFT) /* 0x00008000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1_SHIFT (16U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1_SHIFT) /* 0x00010000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AUDIO_SHIFT (17U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AUDIO_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_AUDIO_SHIFT) /* 0x00020000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NVM_SHIFT (18U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NVM_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_NVM_SHIFT) /* 0x00040000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SDIO_SHIFT (19U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SDIO_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SDIO_SHIFT) /* 0x00080000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_USB_SHIFT (20U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_USB_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_USB_SHIFT) /* 0x00100000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_PHP_SHIFT (21U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_PHP_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_PHP_SHIFT) /* 0x00200000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1USBTOP_SHIFT (22U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1USBTOP_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_VO1USBTOP_SHIFT) /* 0x00400000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_SHIFT (23U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_SHIFT) /* 0x00800000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_CENTER_CHANNEL_SHIFT (24U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_CENTER_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_CENTER_CHANNEL_SHIFT) /* 0x01000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_VO1USB_CHANNEL_SHIFT (25U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_VO1USB_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_SECURE_VO1USB_CHANNEL_SHIFT) /* 0x02000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_SHIFT (26U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_SHIFT) /* 0x04000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_CHANNEL_SHIFT (27U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_CENTER_CHANNEL_SHIFT) /* 0x08000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH0_SHIFT (28U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH0_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH0_SHIFT) /* 0x10000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH1_SHIFT (29U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH1_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH1_SHIFT) /* 0x20000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH2_SHIFT (30U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH2_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH2_SHIFT) /* 0x40000000 */ +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH3_SHIFT (31U) +#define PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH3_MASK (0x1U << PMU_BIU_IDLE_ACK_STS0_IDLE_ACK_DDRSCH3_SHIFT) /* 0x80000000 */ +/* BIU_IDLE_ACK_STS1 */ +#define PMU_BIU_IDLE_ACK_STS1_OFFSET (0x811CU) +#define PMU_BIU_IDLE_ACK_STS1 (0x0U) +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_CENTER_DDRSCH_SHIFT (0U) +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_CENTER_DDRSCH_MASK (0x1U << PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_CENTER_DDRSCH_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_BUS_SHIFT (1U) +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_BUS_MASK (0x1U << PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_BUS_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_TOP_SHIFT (2U) +#define PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_TOP_MASK (0x1U << PMU_BIU_IDLE_ACK_STS1_IDLE_ACK_TOP_SHIFT) /* 0x00000004 */ +/* BIU_IDLE_STS0 */ +#define PMU_BIU_IDLE_STS0_OFFSET (0x8120U) +#define PMU_BIU_IDLE_STS0 (0x0U) +#define PMU_BIU_IDLE_STS0_IDLE_GPU_SHIFT (0U) +#define PMU_BIU_IDLE_STS0_IDLE_GPU_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_GPU_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_STS0_IDLE_NPUTOP_SHIFT (1U) +#define PMU_BIU_IDLE_STS0_IDLE_NPUTOP_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_NPUTOP_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_STS0_IDLE_NPU1_SHIFT (2U) +#define PMU_BIU_IDLE_STS0_IDLE_NPU1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_NPU1_SHIFT) /* 0x00000004 */ +#define PMU_BIU_IDLE_STS0_IDLE_NPU2_SHIFT (3U) +#define PMU_BIU_IDLE_STS0_IDLE_NPU2_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_NPU2_SHIFT) /* 0x00000008 */ +#define PMU_BIU_IDLE_STS0_IDLE_VENC0_SHIFT (4U) +#define PMU_BIU_IDLE_STS0_IDLE_VENC0_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VENC0_SHIFT) /* 0x00000010 */ +#define PMU_BIU_IDLE_STS0_IDLE_VENC1_SHIFT (5U) +#define PMU_BIU_IDLE_STS0_IDLE_VENC1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VENC1_SHIFT) /* 0x00000020 */ +#define PMU_BIU_IDLE_STS0_IDLE_RKVDEC0_SHIFT (6U) +#define PMU_BIU_IDLE_STS0_IDLE_RKVDEC0_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_RKVDEC0_SHIFT) /* 0x00000040 */ +#define PMU_BIU_IDLE_STS0_IDLE_RKVDEC1_SHIFT (7U) +#define PMU_BIU_IDLE_STS0_IDLE_RKVDEC1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_RKVDEC1_SHIFT) /* 0x00000080 */ +#define PMU_BIU_IDLE_STS0_IDLE_VDPU_SHIFT (8U) +#define PMU_BIU_IDLE_STS0_IDLE_VDPU_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VDPU_SHIFT) /* 0x00000100 */ +#define PMU_BIU_IDLE_STS0_IDLE_AV1_SHIFT (9U) +#define PMU_BIU_IDLE_STS0_IDLE_AV1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_AV1_SHIFT) /* 0x00000200 */ +#define PMU_BIU_IDLE_STS0_IDLE_VI_SHIFT (10U) +#define PMU_BIU_IDLE_STS0_IDLE_VI_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VI_SHIFT) /* 0x00000400 */ +#define PMU_BIU_IDLE_STS0_IDLE_ISP1_SHIFT (11U) +#define PMU_BIU_IDLE_STS0_IDLE_ISP1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_ISP1_SHIFT) /* 0x00000800 */ +#define PMU_BIU_IDLE_STS0_IDLE_RGA31_SHIFT (12U) +#define PMU_BIU_IDLE_STS0_IDLE_RGA31_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_RGA31_SHIFT) /* 0x00001000 */ +#define PMU_BIU_IDLE_STS0_IDLE_VOP_SHIFT (13U) +#define PMU_BIU_IDLE_STS0_IDLE_VOP_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VOP_SHIFT) /* 0x00002000 */ +#define PMU_BIU_IDLE_STS0_IDLE_VOP_CHANNEL_SHIFT (14U) +#define PMU_BIU_IDLE_STS0_IDLE_VOP_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VOP_CHANNEL_SHIFT) /* 0x00004000 */ +#define PMU_BIU_IDLE_STS0_IDLE_VO0_SHIFT (15U) +#define PMU_BIU_IDLE_STS0_IDLE_VO0_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VO0_SHIFT) /* 0x00008000 */ +#define PMU_BIU_IDLE_STS0_IDLE_VO1_SHIFT (16U) +#define PMU_BIU_IDLE_STS0_IDLE_VO1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VO1_SHIFT) /* 0x00010000 */ +#define PMU_BIU_IDLE_STS0_IDLE_AUDIO_SHIFT (17U) +#define PMU_BIU_IDLE_STS0_IDLE_AUDIO_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_AUDIO_SHIFT) /* 0x00020000 */ +#define PMU_BIU_IDLE_STS0_IDLE_NVM_SHIFT (18U) +#define PMU_BIU_IDLE_STS0_IDLE_NVM_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_NVM_SHIFT) /* 0x00040000 */ +#define PMU_BIU_IDLE_STS0_IDLE_SDIO_SHIFT (19U) +#define PMU_BIU_IDLE_STS0_IDLE_SDIO_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_SDIO_SHIFT) /* 0x00080000 */ +#define PMU_BIU_IDLE_STS0_IDLE_USB_SHIFT (20U) +#define PMU_BIU_IDLE_STS0_IDLE_USB_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_USB_SHIFT) /* 0x00100000 */ +#define PMU_BIU_IDLE_STS0_IDLE_PHP_SHIFT (21U) +#define PMU_BIU_IDLE_STS0_IDLE_PHP_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_PHP_SHIFT) /* 0x00200000 */ +#define PMU_BIU_IDLE_STS0_IDLE_VO1USBTOP_SHIFT (22U) +#define PMU_BIU_IDLE_STS0_IDLE_VO1USBTOP_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_VO1USBTOP_SHIFT) /* 0x00400000 */ +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_SHIFT (23U) +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_SECURE_SHIFT) /* 0x00800000 */ +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_CENTER_CHANNEL_SHIFT (24U) +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_CENTER_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_SECURE_CENTER_CHANNEL_SHIFT) /* 0x01000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_VO1USB_CHANNEL_SHIFT (25U) +#define PMU_BIU_IDLE_STS0_IDLE_SECURE_VO1USB_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_SECURE_VO1USB_CHANNEL_SHIFT) /* 0x02000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_CENTER_SHIFT (26U) +#define PMU_BIU_IDLE_STS0_IDLE_CENTER_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_CENTER_SHIFT) /* 0x04000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_CENTER_CHANNEL_SHIFT (27U) +#define PMU_BIU_IDLE_STS0_IDLE_CENTER_CHANNEL_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_CENTER_CHANNEL_SHIFT) /* 0x08000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH0_SHIFT (28U) +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH0_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_DDRSCH0_SHIFT) /* 0x10000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH1_SHIFT (29U) +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH1_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_DDRSCH1_SHIFT) /* 0x20000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH2_SHIFT (30U) +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH2_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_DDRSCH2_SHIFT) /* 0x40000000 */ +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH3_SHIFT (31U) +#define PMU_BIU_IDLE_STS0_IDLE_DDRSCH3_MASK (0x1U << PMU_BIU_IDLE_STS0_IDLE_DDRSCH3_SHIFT) /* 0x80000000 */ +/* BIU_IDLE_STS1 */ +#define PMU_BIU_IDLE_STS1_OFFSET (0x8124U) +#define PMU_BIU_IDLE_STS1 (0x0U) +#define PMU_BIU_IDLE_STS1_IDLE_CENTER_DDRSCH_SHIFT (0U) +#define PMU_BIU_IDLE_STS1_IDLE_CENTER_DDRSCH_MASK (0x1U << PMU_BIU_IDLE_STS1_IDLE_CENTER_DDRSCH_SHIFT) /* 0x00000001 */ +#define PMU_BIU_IDLE_STS1_IDLE_BUS_SHIFT (1U) +#define PMU_BIU_IDLE_STS1_IDLE_BUS_MASK (0x1U << PMU_BIU_IDLE_STS1_IDLE_BUS_SHIFT) /* 0x00000002 */ +#define PMU_BIU_IDLE_STS1_IDLE_TOP_SHIFT (2U) +#define PMU_BIU_IDLE_STS1_IDLE_TOP_MASK (0x1U << PMU_BIU_IDLE_STS1_IDLE_TOP_SHIFT) /* 0x00000004 */ +/* BIU_AUTO_CON0 */ +#define PMU_BIU_AUTO_CON0_OFFSET (0x8128U) +#define PMU_BIU_AUTO_CON0_BIU_AUTO_GPU_ENA_SHIFT (0U) +#define PMU_BIU_AUTO_CON0_BIU_AUTO_GPU_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_BIU_AUTO_GPU_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPUTOP_ENA_SHIFT (1U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPUTOP_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_NPUTOP_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU1_ENA_SHIFT (2U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU1_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU2_ENA_SHIFT (3U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU2_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_NPU2_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC0_ENA_SHIFT (4U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC0_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC0_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC1_ENA_SHIFT (5U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VENC1_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC0_ENA_SHIFT (6U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC0_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC0_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC1_ENA_SHIFT (7U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_RKVDEC1_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VDPU_ENA_SHIFT (8U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VDPU_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VDPU_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_AV1_ENA_SHIFT (9U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_AV1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_AV1_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VI_ENA_SHIFT (10U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VI_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VI_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_ISP1_ENA_SHIFT (11U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_ISP1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_ISP1_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RGA31_ENA_SHIFT (12U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_RGA31_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_RGA31_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_ENA_SHIFT (13U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_CHANNEL_ENA_SHIFT (14U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_CHANNEL_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VOP_CHANNEL_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VO0_ENA_SHIFT (15U) +#define PMU_BIU_AUTO_CON0_IDLE_AUTO_VO0_ENA_MASK (0x1U << PMU_BIU_AUTO_CON0_IDLE_AUTO_VO0_ENA_SHIFT) /* 0x00008000 */ +/* BIU_AUTO_CON1 */ +#define PMU_BIU_AUTO_CON1_OFFSET (0x812CU) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1_ENA_SHIFT (0U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_AUDIO_ENA_SHIFT (1U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_AUDIO_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_AUDIO_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_NVM_ENA_SHIFT (2U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_NVM_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_NVM_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SDIO_ENA_SHIFT (3U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SDIO_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_SDIO_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_USB_ENA_SHIFT (4U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_USB_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_USB_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_PHP_ENA_SHIFT (5U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_PHP_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_PHP_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1USBTOP_ENA_SHIFT (6U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1USBTOP_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_VO1USBTOP_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_ENA_SHIFT (7U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_CENTER_CHANNEL_ENA_SHIFT (8U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_CENTER_CHANNEL_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_CENTER_CHANNEL_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_VO1USB_CHANNEL_ENA_SHIFT (9U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_VO1USB_CHANNEL_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_SECURE_VO1USB_CHANNEL_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_ENA_SHIFT (10U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_CHANNEL_ENA_SHIFT (11U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_CHANNEL_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_CENTER_CHANNEL_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH0_ENA_SHIFT (12U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH0_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH0_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH1_ENA_SHIFT (13U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH1_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH1_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH2_ENA_SHIFT (14U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH2_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH2_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH3_ENA_SHIFT (15U) +#define PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH3_ENA_MASK (0x1U << PMU_BIU_AUTO_CON1_IDLE_AUTO_DDRSCH3_ENA_SHIFT) /* 0x00008000 */ +/* BIU_AUTO_CON2 */ +#define PMU_BIU_AUTO_CON2_OFFSET (0x8130U) +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_CENTER_DDRSCH_ENA_SHIFT (0U) +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_CENTER_DDRSCH_ENA_MASK (0x1U << PMU_BIU_AUTO_CON2_IDLE_AUTO_CENTER_DDRSCH_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_BUS_ENA_SHIFT (1U) +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_BUS_ENA_MASK (0x1U << PMU_BIU_AUTO_CON2_IDLE_AUTO_BUS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_TOP_ENA_SHIFT (2U) +#define PMU_BIU_AUTO_CON2_IDLE_AUTO_TOP_ENA_MASK (0x1U << PMU_BIU_AUTO_CON2_IDLE_AUTO_TOP_ENA_SHIFT) /* 0x00000004 */ +/* PWR_GATE_CON0 */ +#define PMU_PWR_GATE_CON0_OFFSET (0x8140U) +#define PMU_PWR_GATE_CON0_PD_GPU_DWN_ENA_SHIFT (0U) +#define PMU_PWR_GATE_CON0_PD_GPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_GPU_DWN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_CON0_PD_NPU_DWN_ENA_SHIFT (1U) +#define PMU_PWR_GATE_CON0_PD_NPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_NPU_DWN_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_CON0_PD_VCODEC_DWN_ENA_SHIFT (2U) +#define PMU_PWR_GATE_CON0_PD_VCODEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_VCODEC_DWN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_CON0_PD_NPUTOP_DWN_ENA_SHIFT (3U) +#define PMU_PWR_GATE_CON0_PD_NPUTOP_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_NPUTOP_DWN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_CON0_PD_NPU1_DWN_ENA_SHIFT (4U) +#define PMU_PWR_GATE_CON0_PD_NPU1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_NPU1_DWN_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_CON0_PD_NPU2_DWN_ENA_SHIFT (5U) +#define PMU_PWR_GATE_CON0_PD_NPU2_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_NPU2_DWN_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_CON0_PD_VENC0_DWN_ENA_SHIFT (6U) +#define PMU_PWR_GATE_CON0_PD_VENC0_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_VENC0_DWN_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_CON0_PD_VENC1_DWN_ENA_SHIFT (7U) +#define PMU_PWR_GATE_CON0_PD_VENC1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_VENC1_DWN_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_CON0_PD_RKVDEC0_DWN_ENA_SHIFT (8U) +#define PMU_PWR_GATE_CON0_PD_RKVDEC0_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_RKVDEC0_DWN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_CON0_PD_RKVDEC1_DWN_ENA_SHIFT (9U) +#define PMU_PWR_GATE_CON0_PD_RKVDEC1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_RKVDEC1_DWN_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_GATE_CON0_PD_VDPU_DWN_ENA_SHIFT (10U) +#define PMU_PWR_GATE_CON0_PD_VDPU_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_VDPU_DWN_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_GATE_CON0_PD_RGA30_DWN_ENA_SHIFT (11U) +#define PMU_PWR_GATE_CON0_PD_RGA30_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_RGA30_DWN_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_GATE_CON0_PD_AV1_DWN_ENA_SHIFT (12U) +#define PMU_PWR_GATE_CON0_PD_AV1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_AV1_DWN_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_GATE_CON0_PD_VI_DWN_ENA_SHIFT (13U) +#define PMU_PWR_GATE_CON0_PD_VI_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_VI_DWN_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_GATE_CON0_PD_FEC_DWN_ENA_SHIFT (14U) +#define PMU_PWR_GATE_CON0_PD_FEC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_FEC_DWN_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_GATE_CON0_PD_ISP1_DWN_ENA_SHIFT (15U) +#define PMU_PWR_GATE_CON0_PD_ISP1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON0_PD_ISP1_DWN_ENA_SHIFT) /* 0x00008000 */ +/* PWR_GATE_CON1 */ +#define PMU_PWR_GATE_CON1_OFFSET (0x8144U) +#define PMU_PWR_GATE_CON1_PD_RGA31_DWN_ENA_SHIFT (0U) +#define PMU_PWR_GATE_CON1_PD_RGA31_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_RGA31_DWN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_CON1_PD_VOP_DWN_ENA_SHIFT (1U) +#define PMU_PWR_GATE_CON1_PD_VOP_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_VOP_DWN_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_CON1_PD_VO0_DWN_ENA_SHIFT (2U) +#define PMU_PWR_GATE_CON1_PD_VO0_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_VO0_DWN_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_CON1_PD_VO1_DWN_ENA_SHIFT (3U) +#define PMU_PWR_GATE_CON1_PD_VO1_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_VO1_DWN_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_CON1_PD_AUDIO_DWN_ENA_SHIFT (4U) +#define PMU_PWR_GATE_CON1_PD_AUDIO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_AUDIO_DWN_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_CON1_PD_PHP_DWN_ENA_SHIFT (5U) +#define PMU_PWR_GATE_CON1_PD_PHP_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_PHP_DWN_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_CON1_PD_GMAC_DWN_ENA_SHIFT (6U) +#define PMU_PWR_GATE_CON1_PD_GMAC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_GMAC_DWN_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_CON1_PD_PCIE_DWN_ENA_SHIFT (7U) +#define PMU_PWR_GATE_CON1_PD_PCIE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_PCIE_DWN_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_CON1_PD_NVM_DWN_ENA_SHIFT (8U) +#define PMU_PWR_GATE_CON1_PD_NVM_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_NVM_DWN_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_CON1_PD_NVM0_DWN_ENA_SHIFT (9U) +#define PMU_PWR_GATE_CON1_PD_NVM0_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_NVM0_DWN_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_GATE_CON1_PD_SDIO_DWN_ENA_SHIFT (10U) +#define PMU_PWR_GATE_CON1_PD_SDIO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_SDIO_DWN_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_GATE_CON1_PD_USB_DWN_ENA_SHIFT (11U) +#define PMU_PWR_GATE_CON1_PD_USB_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_USB_DWN_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_GATE_CON1_PD_SECURE_DWN_ENA_SHIFT (12U) +#define PMU_PWR_GATE_CON1_PD_SECURE_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_SECURE_DWN_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_GATE_CON1_PD_SDMMC_DWN_ENA_SHIFT (13U) +#define PMU_PWR_GATE_CON1_PD_SDMMC_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_SDMMC_DWN_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_GATE_CON1_PD_CRYPTO_DWN_ENA_SHIFT (14U) +#define PMU_PWR_GATE_CON1_PD_CRYPTO_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_CRYPTO_DWN_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_GATE_CON1_PD_CENTER_DWN_ENA_SHIFT (15U) +#define PMU_PWR_GATE_CON1_PD_CENTER_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON1_PD_CENTER_DWN_ENA_SHIFT) /* 0x00008000 */ +/* PWR_GATE_CON2 */ +#define PMU_PWR_GATE_CON2_OFFSET (0x8148U) +#define PMU_PWR_GATE_CON2_PD_DDR01_DWN_ENA_SHIFT (0U) +#define PMU_PWR_GATE_CON2_PD_DDR01_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON2_PD_DDR01_DWN_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_CON2_PD_DDR23_DWN_ENA_SHIFT (1U) +#define PMU_PWR_GATE_CON2_PD_DDR23_DWN_ENA_MASK (0x1U << PMU_PWR_GATE_CON2_PD_DDR23_DWN_ENA_SHIFT) /* 0x00000002 */ +/* PWR_GATE_SFTCON0 */ +#define PMU_PWR_GATE_SFTCON0_OFFSET (0x814CU) +#define PMU_PWR_GATE_SFTCON0_PD_GPU_DWN_SFTENA_SHIFT (0U) +#define PMU_PWR_GATE_SFTCON0_PD_GPU_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_GPU_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_SFTCON0_PD_NPU_DWN_SFTENA_SHIFT (1U) +#define PMU_PWR_GATE_SFTCON0_PD_NPU_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_NPU_DWN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_SFTCON0_PD_VCODEC_DWN_SFTENA_SHIFT (2U) +#define PMU_PWR_GATE_SFTCON0_PD_VCODEC_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_VCODEC_DWN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_SFTCON0_PD_NPUTOP_DWN_SFTENA_SHIFT (3U) +#define PMU_PWR_GATE_SFTCON0_PD_NPUTOP_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_NPUTOP_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_SFTCON0_PD_NPU1_DWN_SFTENA_SHIFT (4U) +#define PMU_PWR_GATE_SFTCON0_PD_NPU1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_NPU1_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_SFTCON0_PD_NPU2_DWN_SFTENA_SHIFT (5U) +#define PMU_PWR_GATE_SFTCON0_PD_NPU2_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_NPU2_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_SFTCON0_PD_VENC0_DWN_SFTENA_SHIFT (6U) +#define PMU_PWR_GATE_SFTCON0_PD_VENC0_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_VENC0_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_SFTCON0_PD_VENC1_DWN_SFTENA_SHIFT (7U) +#define PMU_PWR_GATE_SFTCON0_PD_VENC1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_VENC1_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_SFTCON0_PD_RKVDEC0_DWN_SFTENA_SHIFT (8U) +#define PMU_PWR_GATE_SFTCON0_PD_RKVDEC0_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_RKVDEC0_DWN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_SFTCON0_PD_RKVDEC1_DWN_SFTENA_SHIFT (9U) +#define PMU_PWR_GATE_SFTCON0_PD_RKVDEC1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_RKVDEC1_DWN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_GATE_SFTCON0_PD_VDPU_DWN_SFTENA_SHIFT (10U) +#define PMU_PWR_GATE_SFTCON0_PD_VDPU_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_VDPU_DWN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_GATE_SFTCON0_PD_RGA30_DWN_SFTENA_SHIFT (11U) +#define PMU_PWR_GATE_SFTCON0_PD_RGA30_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_RGA30_DWN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_GATE_SFTCON0_PD_AV1_DWN_SFTENA_SHIFT (12U) +#define PMU_PWR_GATE_SFTCON0_PD_AV1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_AV1_DWN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_GATE_SFTCON0_PD_VI_DWN_SFTENA_SHIFT (13U) +#define PMU_PWR_GATE_SFTCON0_PD_VI_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_VI_DWN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_GATE_SFTCON0_PD_FEC_DWN_SFTENA_SHIFT (14U) +#define PMU_PWR_GATE_SFTCON0_PD_FEC_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_FEC_DWN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_GATE_SFTCON0_PD_ISP1_DWN_SFTENA_SHIFT (15U) +#define PMU_PWR_GATE_SFTCON0_PD_ISP1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON0_PD_ISP1_DWN_SFTENA_SHIFT) /* 0x00008000 */ +/* PWR_GATE_SFTCON1 */ +#define PMU_PWR_GATE_SFTCON1_OFFSET (0x8150U) +#define PMU_PWR_GATE_SFTCON1_PD_RGA31_DWN_SFTENA_SHIFT (0U) +#define PMU_PWR_GATE_SFTCON1_PD_RGA31_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_RGA31_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_SFTCON1_PD_VOP_DWN_SFTENA_SHIFT (1U) +#define PMU_PWR_GATE_SFTCON1_PD_VOP_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_VOP_DWN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_SFTCON1_PD_VO0_DWN_SFTENA_SHIFT (2U) +#define PMU_PWR_GATE_SFTCON1_PD_VO0_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_VO0_DWN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_SFTCON1_PD_VO1_DWN_SFTENA_SHIFT (3U) +#define PMU_PWR_GATE_SFTCON1_PD_VO1_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_VO1_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_SFTCON1_PD_AUDIO_DWN_SFTENA_SHIFT (4U) +#define PMU_PWR_GATE_SFTCON1_PD_AUDIO_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_AUDIO_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_SFTCON1_PD_PHP_DWN_SFTENA_SHIFT (5U) +#define PMU_PWR_GATE_SFTCON1_PD_PHP_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_PHP_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_SFTCON1_PD_GMAC_DWN_SFTENA_SHIFT (6U) +#define PMU_PWR_GATE_SFTCON1_PD_GMAC_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_GMAC_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_SFTCON1_PD_PCIE_DWN_SFTENA_SHIFT (7U) +#define PMU_PWR_GATE_SFTCON1_PD_PCIE_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_PCIE_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_SFTCON1_PD_NVM_DWN_SFTENA_SHIFT (8U) +#define PMU_PWR_GATE_SFTCON1_PD_NVM_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_NVM_DWN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_SFTCON1_PD_NVM0_DWN_SFTENA_SHIFT (9U) +#define PMU_PWR_GATE_SFTCON1_PD_NVM0_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_NVM0_DWN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_GATE_SFTCON1_PD_SDIO_DWN_SFTENA_SHIFT (10U) +#define PMU_PWR_GATE_SFTCON1_PD_SDIO_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_SDIO_DWN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_GATE_SFTCON1_PD_USB_DWN_SFTENA_SHIFT (11U) +#define PMU_PWR_GATE_SFTCON1_PD_USB_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_USB_DWN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_GATE_SFTCON1_PD_SECURE_DWN_SFTENA_SHIFT (12U) +#define PMU_PWR_GATE_SFTCON1_PD_SECURE_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_SECURE_DWN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_GATE_SFTCON1_PD_SDMMC_DWN_SFTENA_SHIFT (13U) +#define PMU_PWR_GATE_SFTCON1_PD_SDMMC_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_SDMMC_DWN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_GATE_SFTCON1_PD_CRYPTO_DWN_SFTENA_SHIFT (14U) +#define PMU_PWR_GATE_SFTCON1_PD_CRYPTO_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_CRYPTO_DWN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_GATE_SFTCON1_PD_CENTER_DWN_SFTENA_SHIFT (15U) +#define PMU_PWR_GATE_SFTCON1_PD_CENTER_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON1_PD_CENTER_DWN_SFTENA_SHIFT) /* 0x00008000 */ +/* PWR_GATE_SFTCON2 */ +#define PMU_PWR_GATE_SFTCON2_OFFSET (0x8154U) +#define PMU_PWR_GATE_SFTCON2_PD_DDR01_DWN_SFTENA_SHIFT (0U) +#define PMU_PWR_GATE_SFTCON2_PD_DDR01_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON2_PD_DDR01_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_SFTCON2_PD_DDR23_DWN_SFTENA_SHIFT (1U) +#define PMU_PWR_GATE_SFTCON2_PD_DDR23_DWN_SFTENA_MASK (0x1U << PMU_PWR_GATE_SFTCON2_PD_DDR23_DWN_SFTENA_SHIFT) /* 0x00000002 */ +/* VOL_GATE_CON0 */ +#define PMU_VOL_GATE_CON0_OFFSET (0x8158U) +#define PMU_VOL_GATE_CON0_VD_GPU_OFF_ENA_SHIFT (0U) +#define PMU_VOL_GATE_CON0_VD_GPU_OFF_ENA_MASK (0x1U << PMU_VOL_GATE_CON0_VD_GPU_OFF_ENA_SHIFT) /* 0x00000001 */ +#define PMU_VOL_GATE_CON0_VD_NPU_OFF_ENA_SHIFT (1U) +#define PMU_VOL_GATE_CON0_VD_NPU_OFF_ENA_MASK (0x1U << PMU_VOL_GATE_CON0_VD_NPU_OFF_ENA_SHIFT) /* 0x00000002 */ +#define PMU_VOL_GATE_CON0_VD_VCODEC_OFF_ENA_SHIFT (2U) +#define PMU_VOL_GATE_CON0_VD_VCODEC_OFF_ENA_MASK (0x1U << PMU_VOL_GATE_CON0_VD_VCODEC_OFF_ENA_SHIFT) /* 0x00000004 */ +/* VOL_GATE_CON1 */ +#define PMU_VOL_GATE_CON1_OFFSET (0x8160U) +#define PMU_VOL_GATE_CON1_VD_DDR01_OFF_ENA_SHIFT (0U) +#define PMU_VOL_GATE_CON1_VD_DDR01_OFF_ENA_MASK (0x1U << PMU_VOL_GATE_CON1_VD_DDR01_OFF_ENA_SHIFT) /* 0x00000001 */ +#define PMU_VOL_GATE_CON1_VD_DDR23_OFF_ENA_SHIFT (1U) +#define PMU_VOL_GATE_CON1_VD_DDR23_OFF_ENA_MASK (0x1U << PMU_VOL_GATE_CON1_VD_DDR23_OFF_ENA_SHIFT) /* 0x00000002 */ +/* PWR_CHAIN_PWRUP_CON0 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_OFFSET (0x8164U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPUTOP_PWRUP_STABLE_ENA_SHIFT (3U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPUTOP_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_NPUTOP_PWRUP_STABLE_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU1_PWRUP_STABLE_ENA_SHIFT (4U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU1_PWRUP_STABLE_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU2_PWRUP_STABLE_ENA_SHIFT (5U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU2_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_NPU2_PWRUP_STABLE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC0_PWRUP_STABLE_ENA_SHIFT (6U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC0_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC0_PWRUP_STABLE_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC1_PWRUP_STABLE_ENA_SHIFT (7U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_VENC1_PWRUP_STABLE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC0_PWRUP_STABLE_ENA_SHIFT (8U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC0_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC0_PWRUP_STABLE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC1_PWRUP_STABLE_ENA_SHIFT (9U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_RKVDEC1_PWRUP_STABLE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VDPU_PWRUP_STABLE_ENA_SHIFT (10U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VDPU_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_VDPU_PWRUP_STABLE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RGA30_PWRUP_STABLE_ENA_SHIFT (11U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_RGA30_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_RGA30_PWRUP_STABLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_AV1_PWRUP_STABLE_ENA_SHIFT (12U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_AV1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_AV1_PWRUP_STABLE_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VI_PWRUP_STABLE_ENA_SHIFT (13U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_VI_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_VI_PWRUP_STABLE_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_FEC_PWRUP_STABLE_ENA_SHIFT (14U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_FEC_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_FEC_PWRUP_STABLE_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_ISP1_PWRUP_STABLE_ENA_SHIFT (15U) +#define PMU_PWR_CHAIN_PWRUP_CON0_PD_ISP1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON0_PD_ISP1_PWRUP_STABLE_ENA_SHIFT) /* 0x00008000 */ +/* PWR_CHAIN_PWRUP_CON1 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_OFFSET (0x8168U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_RGA31_PWRUP_STABLE_ENA_SHIFT (0U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_RGA31_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_RGA31_PWRUP_STABLE_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VOP_PWRUP_STABLE_ENA_SHIFT (1U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VOP_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_VOP_PWRUP_STABLE_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VO0_PWRUP_STABLE_ENA_SHIFT (2U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VO0_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_VO0_PWRUP_STABLE_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VO1_PWRUP_STABLE_ENA_SHIFT (3U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_VO1_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_VO1_PWRUP_STABLE_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_AUDIO_PWRUP_STABLE_ENA_SHIFT (4U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_AUDIO_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_AUDIO_PWRUP_STABLE_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_PHP_PWRUP_STABLE_ENA_SHIFT (5U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_PHP_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_PHP_PWRUP_STABLE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_GMAC_PWRUP_STABLE_ENA_SHIFT (6U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_GMAC_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_GMAC_PWRUP_STABLE_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_PCIE_PWRUP_STABLE_ENA_SHIFT (7U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_PCIE_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_PCIE_PWRUP_STABLE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM_PWRUP_STABLE_ENA_SHIFT (8U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM_PWRUP_STABLE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM0_PWRUP_STABLE_ENA_SHIFT (9U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM0_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_NVM0_PWRUP_STABLE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SDIO_PWRUP_STABLE_ENA_SHIFT (10U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SDIO_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_SDIO_PWRUP_STABLE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_USB_PWRUP_STABLE_ENA_SHIFT (11U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_USB_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_USB_PWRUP_STABLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SECURE_PWRUP_STABLE_ENA_SHIFT (12U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SECURE_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_SECURE_PWRUP_STABLE_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SDMMC_PWRUP_STABLE_ENA_SHIFT (13U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_SDMMC_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_SDMMC_PWRUP_STABLE_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_CRYPTO_PWRUP_STABLE_ENA_SHIFT (14U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_CRYPTO_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_CRYPTO_PWRUP_STABLE_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_CENTER_PWRUP_STABLE_ENA_SHIFT (15U) +#define PMU_PWR_CHAIN_PWRUP_CON1_PD_CENTER_PWRUP_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRUP_CON1_PD_CENTER_PWRUP_STABLE_ENA_SHIFT) /* 0x00008000 */ +/* PWR_CHAIN_PWRDN_CON0 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_OFFSET (0x8170U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPUTOP_PWRDN_STABLE_ENA_SHIFT (3U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPUTOP_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_NPUTOP_PWRDN_STABLE_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU1_PWRDN_STABLE_ENA_SHIFT (4U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU1_PWRDN_STABLE_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU2_PWRDN_STABLE_ENA_SHIFT (5U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU2_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_NPU2_PWRDN_STABLE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC0_PWRDN_STABLE_ENA_SHIFT (6U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC0_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC0_PWRDN_STABLE_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC1_PWRDN_STABLE_ENA_SHIFT (7U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_VENC1_PWRDN_STABLE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC0_PWRDN_STABLE_ENA_SHIFT (8U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC0_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC0_PWRDN_STABLE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC1_PWRDN_STABLE_ENA_SHIFT (9U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_RKVDEC1_PWRDN_STABLE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VDPU_PWRDN_STABLE_ENA_SHIFT (10U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VDPU_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_VDPU_PWRDN_STABLE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RGA30_PWRDN_STABLE_ENA_SHIFT (11U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_RGA30_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_RGA30_PWRDN_STABLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_AV1_PWRDN_STABLE_ENA_SHIFT (12U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_AV1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_AV1_PWRDN_STABLE_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VI_PWRDN_STABLE_ENA_SHIFT (13U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_VI_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_VI_PWRDN_STABLE_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_FEC_PWRDN_STABLE_ENA_SHIFT (14U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_FEC_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_FEC_PWRDN_STABLE_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_ISP1_PWRDN_STABLE_ENA_SHIFT (15U) +#define PMU_PWR_CHAIN_PWRDN_CON0_PD_ISP1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON0_PD_ISP1_PWRDN_STABLE_ENA_SHIFT) /* 0x00008000 */ +/* PWR_CHAIN_PWRDN_CON1 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_OFFSET (0x8174U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_RGA31_PWRDN_STABLE_ENA_SHIFT (0U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_RGA31_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_RGA31_PWRDN_STABLE_ENA_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VOP_PWRDN_STABLE_ENA_SHIFT (1U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VOP_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_VOP_PWRDN_STABLE_ENA_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VO0_PWRDN_STABLE_ENA_SHIFT (2U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VO0_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_VO0_PWRDN_STABLE_ENA_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VO1_PWRDN_STABLE_ENA_SHIFT (3U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_VO1_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_VO1_PWRDN_STABLE_ENA_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_AUDIO_PWRDN_STABLE_ENA_SHIFT (4U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_AUDIO_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_AUDIO_PWRDN_STABLE_ENA_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_PHP_PWRDN_STABLE_ENA_SHIFT (5U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_PHP_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_PHP_PWRDN_STABLE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_GMAC_PWRDN_STABLE_ENA_SHIFT (6U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_GMAC_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_GMAC_PWRDN_STABLE_ENA_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_PCIE_PWRDN_STABLE_ENA_SHIFT (7U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_PCIE_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_PCIE_PWRDN_STABLE_ENA_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM_PWRDN_STABLE_ENA_SHIFT (8U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM_PWRDN_STABLE_ENA_SHIFT) /* 0x00000100 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM0_PWRDN_STABLE_ENA_SHIFT (9U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM0_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_NVM0_PWRDN_STABLE_ENA_SHIFT) /* 0x00000200 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SDIO_PWRDN_STABLE_ENA_SHIFT (10U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SDIO_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_SDIO_PWRDN_STABLE_ENA_SHIFT) /* 0x00000400 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_USB_PWRDN_STABLE_ENA_SHIFT (11U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_USB_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_USB_PWRDN_STABLE_ENA_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SECURE_PWRDN_STABLE_ENA_SHIFT (12U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SECURE_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_SECURE_PWRDN_STABLE_ENA_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SDMMC_PWRDN_STABLE_ENA_SHIFT (13U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_SDMMC_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_SDMMC_PWRDN_STABLE_ENA_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_CRYPTO_PWRDN_STABLE_ENA_SHIFT (14U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_CRYPTO_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_CRYPTO_PWRDN_STABLE_ENA_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_CENTER_PWRDN_STABLE_ENA_SHIFT (15U) +#define PMU_PWR_CHAIN_PWRDN_CON1_PD_CENTER_PWRDN_STABLE_ENA_MASK (0x1U << PMU_PWR_CHAIN_PWRDN_CON1_PD_CENTER_PWRDN_STABLE_ENA_SHIFT) /* 0x00008000 */ +/* PWR_STABLE_CNT */ +#define PMU_PWR_STABLE_CNT_OFFSET (0x817CU) +#define PMU_PWR_STABLE_CNT_PWRUP_STABLE_CNT_SHIFT (0U) +#define PMU_PWR_STABLE_CNT_PWRUP_STABLE_CNT_MASK (0x1FU << PMU_PWR_STABLE_CNT_PWRUP_STABLE_CNT_SHIFT) /* 0x0000001F */ +#define PMU_PWR_STABLE_CNT_PWRDN_STABLE_CNT_SHIFT (16U) +#define PMU_PWR_STABLE_CNT_PWRDN_STABLE_CNT_MASK (0x1FU << PMU_PWR_STABLE_CNT_PWRDN_STABLE_CNT_SHIFT) /* 0x001F0000 */ +/* PWR_GATE_STS0 */ +#define PMU_PWR_GATE_STS0_OFFSET (0x8180U) +#define PMU_PWR_GATE_STS0 (0xFFFFFFU) +#define PMU_PWR_GATE_STS0_PD_GPU_DWN_STAT_SHIFT (0U) +#define PMU_PWR_GATE_STS0_PD_GPU_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_GPU_DWN_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_STS0_PD_NPU_DWN_STAT_SHIFT (1U) +#define PMU_PWR_GATE_STS0_PD_NPU_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NPU_DWN_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_GATE_STS0_PD_VCODEC_DWN_STAT_SHIFT (2U) +#define PMU_PWR_GATE_STS0_PD_VCODEC_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VCODEC_DWN_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_GATE_STS0_PD_NPUTOP_DWN_STAT_SHIFT (3U) +#define PMU_PWR_GATE_STS0_PD_NPUTOP_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NPUTOP_DWN_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_GATE_STS0_PD_NPU1_DWN_STAT_SHIFT (4U) +#define PMU_PWR_GATE_STS0_PD_NPU1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NPU1_DWN_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_GATE_STS0_PD_NPU2_DWN_STAT_SHIFT (5U) +#define PMU_PWR_GATE_STS0_PD_NPU2_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NPU2_DWN_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_GATE_STS0_PD_VENC0_DWN_STAT_SHIFT (6U) +#define PMU_PWR_GATE_STS0_PD_VENC0_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VENC0_DWN_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_GATE_STS0_PD_VENC1_DWN_STAT_SHIFT (7U) +#define PMU_PWR_GATE_STS0_PD_VENC1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VENC1_DWN_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_GATE_STS0_PD_RKVDEC0_DWN_STAT_SHIFT (8U) +#define PMU_PWR_GATE_STS0_PD_RKVDEC0_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_RKVDEC0_DWN_STAT_SHIFT) /* 0x00000100 */ +#define PMU_PWR_GATE_STS0_PD_RKVDEC1_DWN_STAT_SHIFT (9U) +#define PMU_PWR_GATE_STS0_PD_RKVDEC1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_RKVDEC1_DWN_STAT_SHIFT) /* 0x00000200 */ +#define PMU_PWR_GATE_STS0_PD_VDPU_DWN_STAT_SHIFT (10U) +#define PMU_PWR_GATE_STS0_PD_VDPU_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VDPU_DWN_STAT_SHIFT) /* 0x00000400 */ +#define PMU_PWR_GATE_STS0_PD_RGA30_DWN_STAT_SHIFT (11U) +#define PMU_PWR_GATE_STS0_PD_RGA30_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_RGA30_DWN_STAT_SHIFT) /* 0x00000800 */ +#define PMU_PWR_GATE_STS0_PD_AV1_DWN_STAT_SHIFT (12U) +#define PMU_PWR_GATE_STS0_PD_AV1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_AV1_DWN_STAT_SHIFT) /* 0x00001000 */ +#define PMU_PWR_GATE_STS0_PD_VI_DWN_STAT_SHIFT (13U) +#define PMU_PWR_GATE_STS0_PD_VI_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VI_DWN_STAT_SHIFT) /* 0x00002000 */ +#define PMU_PWR_GATE_STS0_PD_FEC_DWN_STAT_SHIFT (14U) +#define PMU_PWR_GATE_STS0_PD_FEC_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_FEC_DWN_STAT_SHIFT) /* 0x00004000 */ +#define PMU_PWR_GATE_STS0_PD_ISP1_DWN_STAT_SHIFT (15U) +#define PMU_PWR_GATE_STS0_PD_ISP1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_ISP1_DWN_STAT_SHIFT) /* 0x00008000 */ +#define PMU_PWR_GATE_STS0_PD_RGA31_DWN_STAT_SHIFT (16U) +#define PMU_PWR_GATE_STS0_PD_RGA31_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_RGA31_DWN_STAT_SHIFT) /* 0x00010000 */ +#define PMU_PWR_GATE_STS0_PD_VOP_DWN_STAT_SHIFT (17U) +#define PMU_PWR_GATE_STS0_PD_VOP_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VOP_DWN_STAT_SHIFT) /* 0x00020000 */ +#define PMU_PWR_GATE_STS0_PD_VO0_DWN_STAT_SHIFT (18U) +#define PMU_PWR_GATE_STS0_PD_VO0_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VO0_DWN_STAT_SHIFT) /* 0x00040000 */ +#define PMU_PWR_GATE_STS0_PD_VO1_DWN_STAT_SHIFT (19U) +#define PMU_PWR_GATE_STS0_PD_VO1_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_VO1_DWN_STAT_SHIFT) /* 0x00080000 */ +#define PMU_PWR_GATE_STS0_PD_AUDIO_DWN_STAT_SHIFT (20U) +#define PMU_PWR_GATE_STS0_PD_AUDIO_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_AUDIO_DWN_STAT_SHIFT) /* 0x00100000 */ +#define PMU_PWR_GATE_STS0_PD_PHP_DWN_STAT_SHIFT (21U) +#define PMU_PWR_GATE_STS0_PD_PHP_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_PHP_DWN_STAT_SHIFT) /* 0x00200000 */ +#define PMU_PWR_GATE_STS0_PD_GMAC_DWN_STAT_SHIFT (22U) +#define PMU_PWR_GATE_STS0_PD_GMAC_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_GMAC_DWN_STAT_SHIFT) /* 0x00400000 */ +#define PMU_PWR_GATE_STS0_PD_PCIE_DWN_STAT_SHIFT (23U) +#define PMU_PWR_GATE_STS0_PD_PCIE_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_PCIE_DWN_STAT_SHIFT) /* 0x00800000 */ +#define PMU_PWR_GATE_STS0_PD_NVM_DWN_STAT_SHIFT (24U) +#define PMU_PWR_GATE_STS0_PD_NVM_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NVM_DWN_STAT_SHIFT) /* 0x01000000 */ +#define PMU_PWR_GATE_STS0_PD_NVM0_DWN_STAT_SHIFT (25U) +#define PMU_PWR_GATE_STS0_PD_NVM0_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_NVM0_DWN_STAT_SHIFT) /* 0x02000000 */ +#define PMU_PWR_GATE_STS0_PD_SDIO_DWN_STAT_SHIFT (26U) +#define PMU_PWR_GATE_STS0_PD_SDIO_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_SDIO_DWN_STAT_SHIFT) /* 0x04000000 */ +#define PMU_PWR_GATE_STS0_PD_USB_DWN_STAT_SHIFT (27U) +#define PMU_PWR_GATE_STS0_PD_USB_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_USB_DWN_STAT_SHIFT) /* 0x08000000 */ +#define PMU_PWR_GATE_STS0_PD_SECURE_DWN_STAT_SHIFT (28U) +#define PMU_PWR_GATE_STS0_PD_SECURE_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_SECURE_DWN_STAT_SHIFT) /* 0x10000000 */ +#define PMU_PWR_GATE_STS0_PD_SDMMC_DWN_STAT_SHIFT (29U) +#define PMU_PWR_GATE_STS0_PD_SDMMC_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_SDMMC_DWN_STAT_SHIFT) /* 0x20000000 */ +#define PMU_PWR_GATE_STS0_PD_CRYPTO_DWN_STAT_SHIFT (30U) +#define PMU_PWR_GATE_STS0_PD_CRYPTO_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_CRYPTO_DWN_STAT_SHIFT) /* 0x40000000 */ +#define PMU_PWR_GATE_STS0_PD_CENTER_DWN_STAT_SHIFT (31U) +#define PMU_PWR_GATE_STS0_PD_CENTER_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS0_PD_CENTER_DWN_STAT_SHIFT) /* 0x80000000 */ +/* PWR_GATE_STS1 */ +#define PMU_PWR_GATE_STS1_OFFSET (0x8184U) +#define PMU_PWR_GATE_STS1 (0x0U) +#define PMU_PWR_GATE_STS1_PD_DDR01_DWN_STAT_SHIFT (0U) +#define PMU_PWR_GATE_STS1_PD_DDR01_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS1_PD_DDR01_DWN_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_GATE_STS1_PD_DDR23_DWN_STAT_SHIFT (1U) +#define PMU_PWR_GATE_STS1_PD_DDR23_DWN_STAT_MASK (0x1U << PMU_PWR_GATE_STS1_PD_DDR23_DWN_STAT_SHIFT) /* 0x00000002 */ +/* PWR_GATE_POWER_STS */ +#define PMU_PWR_GATE_POWER_STS_OFFSET (0x8188U) +#define PMU_PWR_GATE_POWER_STS (0x0U) +#define PMU_PWR_GATE_POWER_STS_POWER_GATE_STATE_SHIFT (0U) +#define PMU_PWR_GATE_POWER_STS_POWER_GATE_STATE_MASK (0x7U << PMU_PWR_GATE_POWER_STS_POWER_GATE_STATE_SHIFT) /* 0x00000007 */ +/* VOL_GATE_FAST_CON */ +#define PMU_VOL_GATE_FAST_CON_OFFSET (0x818CU) +#define PMU_VOL_GATE_FAST_CON_VD_GPU_FAST_ENA_SHIFT (0U) +#define PMU_VOL_GATE_FAST_CON_VD_GPU_FAST_ENA_MASK (0x1U << PMU_VOL_GATE_FAST_CON_VD_GPU_FAST_ENA_SHIFT) /* 0x00000001 */ +#define PMU_VOL_GATE_FAST_CON_VD_NPU_FAST_ENA_SHIFT (1U) +#define PMU_VOL_GATE_FAST_CON_VD_NPU_FAST_ENA_MASK (0x1U << PMU_VOL_GATE_FAST_CON_VD_NPU_FAST_ENA_SHIFT) /* 0x00000002 */ +/* GPU_PWRUP_CNT */ +#define PMU_GPU_PWRUP_CNT_OFFSET (0x8190U) +#define PMU_GPU_PWRUP_CNT_GPU_PWRUP_CNT_SHIFT (0U) +#define PMU_GPU_PWRUP_CNT_GPU_PWRUP_CNT_MASK (0xFFFFFU << PMU_GPU_PWRUP_CNT_GPU_PWRUP_CNT_SHIFT) /* 0x000FFFFF */ +/* GPU_PWRDN_CNT */ +#define PMU_GPU_PWRDN_CNT_OFFSET (0x8194U) +#define PMU_GPU_PWRDN_CNT_GPU_PWRDN_CNT_SHIFT (0U) +#define PMU_GPU_PWRDN_CNT_GPU_PWRDN_CNT_MASK (0xFFFFFU << PMU_GPU_PWRDN_CNT_GPU_PWRDN_CNT_SHIFT) /* 0x000FFFFF */ +/* NPU_PWRUP_CNT */ +#define PMU_NPU_PWRUP_CNT_OFFSET (0x8198U) +#define PMU_NPU_PWRUP_CNT_NPU_PWRUP_CNT_SHIFT (0U) +#define PMU_NPU_PWRUP_CNT_NPU_PWRUP_CNT_MASK (0xFFFFFU << PMU_NPU_PWRUP_CNT_NPU_PWRUP_CNT_SHIFT) /* 0x000FFFFF */ +/* NPU_PWRDN_CNT */ +#define PMU_NPU_PWRDN_CNT_OFFSET (0x819CU) +#define PMU_NPU_PWRDN_CNT_NPU_PWRDN_CNT_SHIFT (0U) +#define PMU_NPU_PWRDN_CNT_NPU_PWRDN_CNT_MASK (0xFFFFFU << PMU_NPU_PWRDN_CNT_NPU_PWRDN_CNT_SHIFT) /* 0x000FFFFF */ +/* MEM_PWR_GATE_SFTCON0 */ +#define PMU_MEM_PWR_GATE_SFTCON0_OFFSET (0x81A0U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPUTOP_MEM_DWN_SFTENA_SHIFT (3U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPUTOP_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_NPUTOP_MEM_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPU1_MEM_DWN_SFTENA_SHIFT (4U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPU1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_NPU1_MEM_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPU2_MEM_DWN_SFTENA_SHIFT (5U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_NPU2_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_NPU2_MEM_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VENC0_MEM_DWN_SFTENA_SHIFT (6U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VENC0_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_VENC0_MEM_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VENC1_MEM_DWN_SFTENA_SHIFT (7U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VENC1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_VENC1_MEM_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC0_MEM_DWN_SFTENA_SHIFT (8U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC0_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC0_MEM_DWN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC1_MEM_DWN_SFTENA_SHIFT (9U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_RKVDEC1_MEM_DWN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RGA30_MEM_DWN_SFTENA_SHIFT (11U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_RGA30_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_RGA30_MEM_DWN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_AV1_MEM_DWN_SFTENA_SHIFT (12U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_AV1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_AV1_MEM_DWN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VI_MEM_DWN_SFTENA_SHIFT (13U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_VI_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_VI_MEM_DWN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_FEC_MEM_DWN_SFTENA_SHIFT (14U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_FEC_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_FEC_MEM_DWN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_MEM_PWR_GATE_SFTCON0_PD_ISP1_MEM_DWN_SFTENA_SHIFT (15U) +#define PMU_MEM_PWR_GATE_SFTCON0_PD_ISP1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON0_PD_ISP1_MEM_DWN_SFTENA_SHIFT) /* 0x00008000 */ +/* MEM_PWR_GATE_SFTCON1 */ +#define PMU_MEM_PWR_GATE_SFTCON1_OFFSET (0x81A4U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_RGA31_MEM_DWN_SFTENA_SHIFT (0U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_RGA31_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_RGA31_MEM_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VOP_MEM_DWN_SFTENA_SHIFT (1U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VOP_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_VOP_MEM_DWN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VO0_MEM_DWN_SFTENA_SHIFT (2U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VO0_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_VO0_MEM_DWN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VO1_MEM_DWN_SFTENA_SHIFT (3U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_VO1_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_VO1_MEM_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_AUDIO_MEM_DWN_SFTENA_SHIFT (4U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_AUDIO_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_AUDIO_MEM_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_PHP_MEM_DWN_SFTENA_SHIFT (5U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_PHP_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_PHP_MEM_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_GMAC_MEM_DWN_SFTENA_SHIFT (6U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_GMAC_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_GMAC_MEM_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_PCIE_MEM_DWN_SFTENA_SHIFT (7U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_PCIE_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_PCIE_MEM_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_NVM0_MEM_DWN_SFTENA_SHIFT (9U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_NVM0_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_NVM0_MEM_DWN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_SDIO_MEM_DWN_SFTENA_SHIFT (10U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_SDIO_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_SDIO_MEM_DWN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_USB_MEM_DWN_SFTENA_SHIFT (11U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_USB_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_USB_MEM_DWN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_SDMMC_MEM_DWN_SFTENA_SHIFT (13U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_SDMMC_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_SDMMC_MEM_DWN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_CRYPTO_MEM_DWN_SFTENA_SHIFT (14U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_CRYPTO_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_CRYPTO_MEM_DWN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_MEM_PWR_GATE_SFTCON1_PD_CENTER_MEM_DWN_SFTENA_SHIFT (15U) +#define PMU_MEM_PWR_GATE_SFTCON1_PD_CENTER_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON1_PD_CENTER_MEM_DWN_SFTENA_SHIFT) /* 0x00008000 */ +/* MEM_PWR_GATE_SFTCON2 */ +#define PMU_MEM_PWR_GATE_SFTCON2_OFFSET (0x81A8U) +#define PMU_MEM_PWR_GATE_SFTCON2_PD_DDR01_MEM_DWN_SFTENA_SHIFT (0U) +#define PMU_MEM_PWR_GATE_SFTCON2_PD_DDR01_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON2_PD_DDR01_MEM_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_MEM_PWR_GATE_SFTCON2_PD_DDR23_MEM_DWN_SFTENA_SHIFT (1U) +#define PMU_MEM_PWR_GATE_SFTCON2_PD_DDR23_MEM_DWN_SFTENA_MASK (0x1U << PMU_MEM_PWR_GATE_SFTCON2_PD_DDR23_MEM_DWN_SFTENA_SHIFT) /* 0x00000002 */ +/* SUBMEM_PWR_GATE_SFTCON0 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_OFFSET (0x81B0U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_ENA_SHIFT (0U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_ENA_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_ENA_SHIFT (1U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_ENA_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_ENA_SHIFT (2U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_ENA_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_ENA_SHIFT (3U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_ENA_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_ENA_SHIFT (4U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_ENA_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_ENA_SHIFT (5U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_ENA_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_ENA_SHIFT (6U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_ENA_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_ENA_SHIFT (7U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_CTRL_SHIFT (8U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_SD_CTRL_SHIFT) /* 0x00000100 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_CTRL_SHIFT (9U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_SD_CTRL_SHIFT) /* 0x00000200 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_CTRL_SHIFT (10U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_SD_CTRL_SHIFT) /* 0x00000400 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_CTRL_SHIFT (11U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_SD_CTRL_SHIFT) /* 0x00000800 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_CTRL_SHIFT (12U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK0_DS_CTRL_SHIFT) /* 0x00001000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_CTRL_SHIFT (13U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK1_DS_CTRL_SHIFT) /* 0x00002000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_CTRL_SHIFT (14U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK2_DS_CTRL_SHIFT) /* 0x00004000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_CTRL_SHIFT (15U) +#define PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_CTRL_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON0_SHRM_BLK3_DS_CTRL_SHIFT) /* 0x00008000 */ +/* SUBMEM_PWR_GATE_SFTCON1 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_OFFSET (0x81B4U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L0_MEM_DWN_SFTENA_SHIFT (0U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L0_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L0_MEM_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L1_MEM_DWN_SFTENA_SHIFT (1U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L1_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L1_MEM_DWN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L2_MEM_DWN_SFTENA_SHIFT (2U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L2_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_PCIE1L2_MEM_DWN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIEMMU_MEM_DWN_SFTENA_SHIFT (3U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PCIEMMU_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_PCIEMMU_MEM_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PHPMMU_MEM_DWN_SFTENA_SHIFT (4U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_PHPMMU_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_PHPMMU_MEM_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_SATA_MEM_DWN_SFTENA_SHIFT (5U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_SATA_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_SATA_MEM_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_USB3_MEM_DWN_SFTENA_SHIFT (6U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_USB3_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_USB3_MEM_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_VDPU_MEM_DWN_SFTENA_SHIFT (7U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_VDPU_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_VDPU_MEM_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_RGA2_MEM_DWN_SFTENA_SHIFT (8U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_RGA2_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_RGA2_MEM_DWN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_IEP_MEM_DWN_SFTENA_SHIFT (9U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_IEP_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_IEP_MEM_DWN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGDEC_MEM_DWN_SFTENA_SHIFT (10U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGDEC_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGDEC_MEM_DWN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC0_MEM_DWN_SFTENA_SHIFT (11U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC0_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC0_MEM_DWN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC1_MEM_DWN_SFTENA_SHIFT (12U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC1_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC1_MEM_DWN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC2_MEM_DWN_SFTENA_SHIFT (13U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC2_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC2_MEM_DWN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC3_MEM_DWN_SFTENA_SHIFT (14U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC3_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_JPEGENC3_MEM_DWN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON1_VOPPOST0_MEM_DWN_SFTENA_SHIFT (15U) +#define PMU_SUBMEM_PWR_GATE_SFTCON1_VOPPOST0_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON1_VOPPOST0_MEM_DWN_SFTENA_SHIFT) /* 0x00008000 */ +/* SUBMEM_PWR_GATE_SFTCON2 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_OFFSET (0x81B8U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST1_MEM_DWN_SFTENA_SHIFT (0U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST1_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST1_MEM_DWN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST2_MEM_DWN_SFTENA_SHIFT (1U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST2_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST2_MEM_DWN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST3_MEM_DWN_SFTENA_SHIFT (2U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST3_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPPOST3_MEM_DWN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY1_MEM_DWN_SFTENA_SHIFT (3U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY1_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY1_MEM_DWN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY2_MEM_DWN_SFTENA_SHIFT (4U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY2_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY2_MEM_DWN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY3_MEM_DWN_SFTENA_SHIFT (5U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY3_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPDOLBY3_MEM_DWN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPWB_MEM_DWN_SFTENA_SHIFT (6U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_VOPWB_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_VOPWB_MEM_DWN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST0_MEM_DWN_SFTENA_SHIFT (7U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST0_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST0_MEM_DWN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST1_MEM_DWN_SFTENA_SHIFT (8U) +#define PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST1_MEM_DWN_SFTENA_MASK (0x1U << PMU_SUBMEM_PWR_GATE_SFTCON2_DSIHOST1_MEM_DWN_SFTENA_SHIFT) /* 0x00000100 */ +/* SUBMEM_PWR_GATE_STS */ +#define PMU_SUBMEM_PWR_GATE_STS_OFFSET (0x81BCU) +#define PMU_SUBMEM_PWR_GATE_STS (0x0U) +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK0_PWR_STAT_SHIFT (0U) +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK0_PWR_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK0_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK1_PWR_STAT_SHIFT (1U) +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK1_PWR_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK1_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK2_PWR_STAT_SHIFT (2U) +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK2_PWR_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK2_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK3_PWR_STAT_SHIFT (3U) +#define PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK3_PWR_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_SHRM_BLK3_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L0_MEM_PWR_STAT_SHIFT (4U) +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L0_MEM_PWR_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_PCIE1L0_MEM_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L1_MEM_DWN_STAT_SHIFT (5U) +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L1_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_PCIE1L1_MEM_DWN_STAT_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L2_MEM_DWN_STAT_SHIFT (6U) +#define PMU_SUBMEM_PWR_GATE_STS_PCIE1L2_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_PCIE1L2_MEM_DWN_STAT_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_GATE_STS_PCIEMMU_MEM_DWN_STAT_SHIFT (7U) +#define PMU_SUBMEM_PWR_GATE_STS_PCIEMMU_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_PCIEMMU_MEM_DWN_STAT_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_GATE_STS_PHPMMU_MEM_DWN_STAT_SHIFT (8U) +#define PMU_SUBMEM_PWR_GATE_STS_PHPMMU_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_PHPMMU_MEM_DWN_STAT_SHIFT) /* 0x00000100 */ +#define PMU_SUBMEM_PWR_GATE_STS_SATA_MEM_DWN_STAT_SHIFT (9U) +#define PMU_SUBMEM_PWR_GATE_STS_SATA_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_SATA_MEM_DWN_STAT_SHIFT) /* 0x00000200 */ +#define PMU_SUBMEM_PWR_GATE_STS_USB3_MEM_DWN_STAT_SHIFT (10U) +#define PMU_SUBMEM_PWR_GATE_STS_USB3_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_USB3_MEM_DWN_STAT_SHIFT) /* 0x00000400 */ +#define PMU_SUBMEM_PWR_GATE_STS_VDPU_MEM_DWN_STAT_SHIFT (11U) +#define PMU_SUBMEM_PWR_GATE_STS_VDPU_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VDPU_MEM_DWN_STAT_SHIFT) /* 0x00000800 */ +#define PMU_SUBMEM_PWR_GATE_STS_RGA2_MEM_DWN_STAT_SHIFT (12U) +#define PMU_SUBMEM_PWR_GATE_STS_RGA2_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_RGA2_MEM_DWN_STAT_SHIFT) /* 0x00001000 */ +#define PMU_SUBMEM_PWR_GATE_STS_IEP_MEM_DWN_STAT_SHIFT (13U) +#define PMU_SUBMEM_PWR_GATE_STS_IEP_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_IEP_MEM_DWN_STAT_SHIFT) /* 0x00002000 */ +#define PMU_SUBMEM_PWR_GATE_STS_JPEGDEC_MEM_DWN_STAT_SHIFT (14U) +#define PMU_SUBMEM_PWR_GATE_STS_JPEGDEC_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_JPEGDEC_MEM_DWN_STAT_SHIFT) /* 0x00004000 */ +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC0_MEM_DWN_STAT_SHIFT (15U) +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC0_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_JPEGENC0_MEM_DWN_STAT_SHIFT) /* 0x00008000 */ +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC1_MEM_DWN_STAT_SHIFT (16U) +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC1_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_JPEGENC1_MEM_DWN_STAT_SHIFT) /* 0x00010000 */ +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC2_MEM_DWN_STAT_SHIFT (17U) +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC2_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_JPEGENC2_MEM_DWN_STAT_SHIFT) /* 0x00020000 */ +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC3_MEM_DWN_STAT_SHIFT (18U) +#define PMU_SUBMEM_PWR_GATE_STS_JPEGENC3_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_JPEGENC3_MEM_DWN_STAT_SHIFT) /* 0x00040000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST0_MEM_DWN_STAT_SHIFT (19U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST0_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPPOST0_MEM_DWN_STAT_SHIFT) /* 0x00080000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST1_MEM_DWN_STAT_SHIFT (20U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST1_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPPOST1_MEM_DWN_STAT_SHIFT) /* 0x00100000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST2_MEM_DWN_STAT_SHIFT (21U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST2_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPPOST2_MEM_DWN_STAT_SHIFT) /* 0x00200000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST3_MEM_DWN_STAT_SHIFT (22U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPPOST3_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPPOST3_MEM_DWN_STAT_SHIFT) /* 0x00400000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY1_MEM_DWN_STAT_SHIFT (23U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY1_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY1_MEM_DWN_STAT_SHIFT) /* 0x00800000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY2_MEM_DWN_STAT_SHIFT (24U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY2_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY2_MEM_DWN_STAT_SHIFT) /* 0x01000000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY3_MEM_DWN_STAT_SHIFT (25U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY3_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPDOLBY3_MEM_DWN_STAT_SHIFT) /* 0x02000000 */ +#define PMU_SUBMEM_PWR_GATE_STS_VOPWB_MEM_DWN_STAT_SHIFT (26U) +#define PMU_SUBMEM_PWR_GATE_STS_VOPWB_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_VOPWB_MEM_DWN_STAT_SHIFT) /* 0x04000000 */ +#define PMU_SUBMEM_PWR_GATE_STS_DSIHOST0_MEM_DWN_STAT_SHIFT (27U) +#define PMU_SUBMEM_PWR_GATE_STS_DSIHOST0_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_DSIHOST0_MEM_DWN_STAT_SHIFT) /* 0x08000000 */ +#define PMU_SUBMEM_PWR_GATE_STS_DSIHOST1_MEM_DWN_STAT_SHIFT (28U) +#define PMU_SUBMEM_PWR_GATE_STS_DSIHOST1_MEM_DWN_STAT_MASK (0x1U << PMU_SUBMEM_PWR_GATE_STS_DSIHOST1_MEM_DWN_STAT_SHIFT) /* 0x10000000 */ +/* SUBMEM_PWR_ACK_BYPASS_CON0 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_OFFSET (0x81C0U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L0_MEM_PWR_ACK_BYPASS_ENA_SHIFT (0U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L0_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L0_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L1_MEM_PWR_ACK_BYPASS_ENA_SHIFT (1U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L1_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L1_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L2_MEM_PWR_ACK_BYPASS_ENA_SHIFT (2U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L2_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIE1L2_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIEMMU_MEM_PWR_ACK_BYPASS_ENA_SHIFT (3U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIEMMU_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PCIEMMU_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PHPMMU_MEM_PWR_ACK_BYPASS_ENA_SHIFT (4U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PHPMMU_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_PHPMMU_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_SATA_MEM_PWR_ACK_BYPASS_ENA_SHIFT (5U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_SATA_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_SATA_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_USB3_MEM_PWR_ACK_BYPASS_ENA_SHIFT (6U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_USB3_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_USB3_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VDPU_MEM_PWR_ACK_BYPASS_ENA_SHIFT (7U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VDPU_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VDPU_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_RGA2_MEM_PWR_ACK_BYPASS_ENA_SHIFT (8U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_RGA2_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_RGA2_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000100 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_IEP_MEM_PWR_ACK_BYPASS_ENA_SHIFT (9U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_IEP_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_IEP_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000200 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGDEC_MEM_PWR_ACK_BYPASS_ENA_SHIFT (10U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGDEC_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGDEC_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000400 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC0_MEM_PWR_ACK_BYPASS_ENA_SHIFT (11U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC0_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC0_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000800 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC1_MEM_PWR_ACK_BYPASS_ENA_SHIFT (12U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC1_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC1_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00001000 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC2_MEM_PWR_ACK_BYPASS_ENA_SHIFT (13U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC2_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC2_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00002000 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC3_MEM_PWR_ACK_BYPASS_ENA_SHIFT (14U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC3_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_JPEGENC3_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00004000 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VOPPOST0_MEM_PWR_ACK_BYPASS_ENA_SHIFT (15U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VOPPOST0_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON0_VOPPOST0_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00008000 */ +/* SUBMEM_PWR_ACK_BYPASS_CON1 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_OFFSET (0x81C4U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST1_DWN_ACK_BYPASS_ENA_SHIFT (0U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST1_DWN_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST1_DWN_ACK_BYPASS_ENA_SHIFT) /* 0x00000001 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST2_MEM_PWR_ACK_BYPASS_ENA_SHIFT (1U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST2_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST2_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000002 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST3_MEM_PWR_ACK_BYPASS_ENA_SHIFT (2U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST3_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPPOST3_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000004 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY1_MEM_PWR_ACK_BYPASS_ENA_SHIFT (3U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY1_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY1_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000008 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY2_MEM_PWR_ACK_BYPASS_ENA_SHIFT (4U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY2_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY2_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000010 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY3_MEM_PWR_ACK_BYPASS_ENA_SHIFT (5U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY3_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPDOLBY3_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000020 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPWB_MEM_PWR_ACK_BYPASS_ENA_SHIFT (6U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPWB_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_VOPWB_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000040 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST0_MEM_PWR_ACK_BYPASS_ENA_SHIFT (7U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST0_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST0_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000080 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST1_MEM_PWR_ACK_BYPASS_ENA_SHIFT (8U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST1_MEM_PWR_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_DSIHOST1_MEM_PWR_ACK_BYPASS_ENA_SHIFT) /* 0x00000100 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK0_DWN_ACK_BYPASS_ENA_SHIFT (9U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK0_DWN_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK0_DWN_ACK_BYPASS_ENA_SHIFT) /* 0x00000200 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK1_DWN_ACK_BYPASS_ENA_SHIFT (10U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK1_DWN_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK1_DWN_ACK_BYPASS_ENA_SHIFT) /* 0x00000400 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK2_DWN_ACK_BYPASS_ENA_SHIFT (11U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK2_DWN_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK2_DWN_ACK_BYPASS_ENA_SHIFT) /* 0x00000800 */ +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK3_DWN_ACK_BYPASS_ENA_SHIFT (12U) +#define PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK3_DWN_ACK_BYPASS_ENA_MASK (0x1U << PMU_SUBMEM_PWR_ACK_BYPASS_CON1_SHRM_BLK3_DWN_ACK_BYPASS_ENA_SHIFT) /* 0x00001000 */ +/* QCHANNEL_PWR_CON */ +#define PMU_QCHANNEL_PWR_CON_OFFSET (0x81D0U) +#define PMU_QCHANNEL_PWR_CON_PHPMMU_TBU_QCH_ENA_SHIFT (0U) +#define PMU_QCHANNEL_PWR_CON_PHPMMU_TBU_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_PHPMMU_TBU_QCH_ENA_SHIFT) /* 0x00000001 */ +#define PMU_QCHANNEL_PWR_CON_PHPMMU_TCU_QCH_ENA_SHIFT (1U) +#define PMU_QCHANNEL_PWR_CON_PHPMMU_TCU_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_PHPMMU_TCU_QCH_ENA_SHIFT) /* 0x00000002 */ +#define PMU_QCHANNEL_PWR_CON_PCIEMMU_TBU_QCH_ENA_SHIFT (2U) +#define PMU_QCHANNEL_PWR_CON_PCIEMMU_TBU_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_PCIEMMU_TBU_QCH_ENA_SHIFT) /* 0x00000004 */ +#define PMU_QCHANNEL_PWR_CON_PCIEMMU_TCU_QCH_ENA_SHIFT (3U) +#define PMU_QCHANNEL_PWR_CON_PCIEMMU_TCU_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_PCIEMMU_TCU_QCH_ENA_SHIFT) /* 0x00000008 */ +#define PMU_QCHANNEL_PWR_CON_PHPGIC_ITS_QCH_ENA_SHIFT (4U) +#define PMU_QCHANNEL_PWR_CON_PHPGIC_ITS_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_PHPGIC_ITS_QCH_ENA_SHIFT) /* 0x00000010 */ +#define PMU_QCHANNEL_PWR_CON_BUSGIC_ITS0_QCH_ENA_SHIFT (5U) +#define PMU_QCHANNEL_PWR_CON_BUSGIC_ITS0_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_BUSGIC_ITS0_QCH_ENA_SHIFT) /* 0x00000020 */ +#define PMU_QCHANNEL_PWR_CON_BUSGIC_ITS1_QCH_ENA_SHIFT (6U) +#define PMU_QCHANNEL_PWR_CON_BUSGIC_ITS1_QCH_ENA_MASK (0x1U << PMU_QCHANNEL_PWR_CON_BUSGIC_ITS1_QCH_ENA_SHIFT) /* 0x00000040 */ +/* QCHANNEL_PWR_SFTCON */ +#define PMU_QCHANNEL_PWR_SFTCON_OFFSET (0x81D4U) +#define PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TBU_QCH_SFTENA_SHIFT (0U) +#define PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TBU_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TBU_QCH_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TCU_QCH_SFTENA_SHIFT (1U) +#define PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TCU_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_PHPMMU_TCU_QCH_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TBU_QCH_SFTENA_SHIFT (2U) +#define PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TBU_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TBU_QCH_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TCU_QCH_SFTENA_SHIFT (3U) +#define PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TCU_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_PCIEMMU_TCU_QCH_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_QCHANNEL_PWR_SFTCON_PHPGIC_ITS_QCH_SFTENA_SHIFT (4U) +#define PMU_QCHANNEL_PWR_SFTCON_PHPGIC_ITS_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_PHPGIC_ITS_QCH_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS0_QCH_SFTENA_SHIFT (5U) +#define PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS0_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS0_QCH_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS1_QCH_SFTENA_SHIFT (6U) +#define PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS1_QCH_SFTENA_MASK (0x1U << PMU_QCHANNEL_PWR_SFTCON_BUSGIC_ITS1_QCH_SFTENA_SHIFT) /* 0x00000040 */ +/* QCHANNEL_PWR_STS */ +#define PMU_QCHANNEL_PWR_STS_OFFSET (0x81D8U) +#define PMU_QCHANNEL_PWR_STS (0x0U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACCEPT_SHIFT (0U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACCEPT_SHIFT) /* 0x00000001 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACCEPT_SHIFT (1U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACCEPT_SHIFT) /* 0x00000002 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACCEPT_SHIFT (2U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACCEPT_SHIFT) /* 0x00000004 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACCEPT_SHIFT (3U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACCEPT_SHIFT) /* 0x00000008 */ +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACCEPT_SHIFT (4U) +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACCEPT_SHIFT) /* 0x00000010 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACCEPT_SHIFT (5U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACCEPT_SHIFT) /* 0x00000020 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACCEPT_SHIFT (6U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACCEPT_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACCEPT_SHIFT) /* 0x00000040 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_DENY_SHIFT (7U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_DENY_SHIFT) /* 0x00000080 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_DENY_SHIFT (8U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_DENY_SHIFT) /* 0x00000100 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_DENY_SHIFT (9U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_DENY_SHIFT) /* 0x00000200 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_DENY_SHIFT (10U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_DENY_SHIFT) /* 0x00000400 */ +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_DENY_SHIFT (11U) +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_DENY_SHIFT) /* 0x00000800 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_DENY_SHIFT (12U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_DENY_SHIFT) /* 0x00001000 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_DENY_SHIFT (13U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_DENY_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_DENY_SHIFT) /* 0x00002000 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACTIVE_SHIFT (14U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_ACTIVE_SHIFT) /* 0x00004000 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACTIVE_SHIFT (15U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_ACTIVE_SHIFT) /* 0x00008000 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACTIVE_SHIFT (16U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_ACTIVE_SHIFT) /* 0x00010000 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACTIVE_SHIFT (17U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_ACTIVE_SHIFT) /* 0x00020000 */ +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACTIVE_SHIFT (18U) +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_ACTIVE_SHIFT) /* 0x00040000 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACTIVE_SHIFT (19U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_ACTIVE_SHIFT) /* 0x00080000 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACTIVE_SHIFT (20U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACTIVE_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_ACTIVE_SHIFT) /* 0x00100000 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_REQ_SHIFT (21U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TBU_QCH_REQ_SHIFT) /* 0x00200000 */ +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_REQ_SHIFT (22U) +#define PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPMMU_TCU_QCH_REQ_SHIFT) /* 0x00400000 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_REQ_SHIFT (23U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TBU_QCH_REQ_SHIFT) /* 0x00800000 */ +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_REQ_SHIFT (24U) +#define PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PCIEMMU_TCU_QCH_REQ_SHIFT) /* 0x01000000 */ +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_REQ_SHIFT (25U) +#define PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_PHPGIC_ITS_QCH_REQ_SHIFT) /* 0x02000000 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_REQ_SHIFT (26U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS0_QCH_REQ_SHIFT) /* 0x04000000 */ +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_REQ_SHIFT (27U) +#define PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_REQ_MASK (0x1U << PMU_QCHANNEL_PWR_STS_BUSGIC_ITS1_QCH_REQ_SHIFT) /* 0x08000000 */ +/* DEBUG_INFO_CON */ +#define PMU_DEBUG_INFO_CON_OFFSET (0x81E0U) +#define PMU_DEBUG_INFO_CON_CPU0_POWER_STATE_SEL_SHIFT (0U) +#define PMU_DEBUG_INFO_CON_CPU0_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU0_POWER_STATE_SEL_SHIFT) /* 0x00000001 */ +#define PMU_DEBUG_INFO_CON_CPU1_POWER_STATE_SEL_SHIFT (1U) +#define PMU_DEBUG_INFO_CON_CPU1_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU1_POWER_STATE_SEL_SHIFT) /* 0x00000002 */ +#define PMU_DEBUG_INFO_CON_CPU2_POWER_STATE_SEL_SHIFT (2U) +#define PMU_DEBUG_INFO_CON_CPU2_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU2_POWER_STATE_SEL_SHIFT) /* 0x00000004 */ +#define PMU_DEBUG_INFO_CON_CPU3_POWER_STATE_SEL_SHIFT (3U) +#define PMU_DEBUG_INFO_CON_CPU3_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU3_POWER_STATE_SEL_SHIFT) /* 0x00000008 */ +#define PMU_DEBUG_INFO_CON_CPU4_POWER_STATE_SEL_SHIFT (4U) +#define PMU_DEBUG_INFO_CON_CPU4_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU4_POWER_STATE_SEL_SHIFT) /* 0x00000010 */ +#define PMU_DEBUG_INFO_CON_CPU5_POWER_STATE_SEL_SHIFT (5U) +#define PMU_DEBUG_INFO_CON_CPU5_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU5_POWER_STATE_SEL_SHIFT) /* 0x00000020 */ +#define PMU_DEBUG_INFO_CON_CPU6_POWER_STATE_SEL_SHIFT (6U) +#define PMU_DEBUG_INFO_CON_CPU6_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU6_POWER_STATE_SEL_SHIFT) /* 0x00000040 */ +#define PMU_DEBUG_INFO_CON_CPU7_POWER_STATE_SEL_SHIFT (7U) +#define PMU_DEBUG_INFO_CON_CPU7_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU7_POWER_STATE_SEL_SHIFT) /* 0x00000080 */ +#define PMU_DEBUG_INFO_CON_CORE0_POWER_STATE_SEL_SHIFT (8U) +#define PMU_DEBUG_INFO_CON_CORE0_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CORE0_POWER_STATE_SEL_SHIFT) /* 0x00000100 */ +#define PMU_DEBUG_INFO_CON_CORE1_POWER_STATE_SEL_SHIFT (9U) +#define PMU_DEBUG_INFO_CON_CORE1_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CORE1_POWER_STATE_SEL_SHIFT) /* 0x00000200 */ +#define PMU_DEBUG_INFO_CON_CPU_POWER_STATE_SEL_SHIFT (10U) +#define PMU_DEBUG_INFO_CON_CPU_POWER_STATE_SEL_MASK (0x1U << PMU_DEBUG_INFO_CON_CPU_POWER_STATE_SEL_SHIFT) /* 0x00000400 */ +/* VOP_SUBPD_PWR_CHAIN_STS */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_OFFSET (0x81E4U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS (0x49249U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_MEM_PWR_STAT_SHIFT (0U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_MEM_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C1_PWR_STAT_SHIFT (1U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C1_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C0_PWR_STAT_SHIFT (2U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER0_C0_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_MEM_PWR_STAT_SHIFT (3U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_MEM_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C1_PWR_STAT_SHIFT (4U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C1_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C0_PWR_STAT_SHIFT (5U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER1_C0_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_MEM_PWR_STAT_SHIFT (6U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_MEM_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C1_PWR_STAT_SHIFT (7U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C1_PWR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C0_PWR_STAT_SHIFT (8U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER2_C0_PWR_STAT_SHIFT) /* 0x00000100 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_MEM_PWR_STAT_SHIFT (9U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_MEM_PWR_STAT_SHIFT) /* 0x00000200 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C1_PWR_STAT_SHIFT (10U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C1_PWR_STAT_SHIFT) /* 0x00000400 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C0_PWR_STAT_SHIFT (11U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_CLUSTER3_C0_PWR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_MEM_PWR_STAT_SHIFT (12U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_MEM_PWR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C1_PWR_STAT_SHIFT (13U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C1_PWR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C0_PWR_STAT_SHIFT (14U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_ESMART_C0_PWR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_MEM_PWR_STAT_SHIFT (15U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_MEM_PWR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C1_PWR_STAT_SHIFT (16U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C1_PWR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C0_PWR_STAT_SHIFT (17U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC4K_C0_PWR_STAT_SHIFT) /* 0x00020000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_MEM_PWR_STAT_SHIFT (18U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_MEM_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_MEM_PWR_STAT_SHIFT) /* 0x00040000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C1_PWR_STAT_SHIFT (19U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C1_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C1_PWR_STAT_SHIFT) /* 0x00080000 */ +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C0_PWR_STAT_SHIFT (20U) +#define PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C0_PWR_STAT_MASK (0x1U << PMU_VOP_SUBPD_PWR_CHAIN_STS_VOP_DSC8K_C0_PWR_STAT_SHIFT) /* 0x00100000 */ +/* PWR_CHAIN0_STS0 */ +#define PMU_PWR_CHAIN0_STS0_OFFSET (0x81E8U) +#define PMU_PWR_CHAIN0_STS0 (0xFFU) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_0_C0_PWR_STAT_SHIFT (0U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_0_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_0_C0_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_1_C0_PWR_STAT_SHIFT (1U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_1_C0_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_2_C0_PWR_STAT_SHIFT (2U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_2_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_2_C0_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_3_C0_PWR_STAT_SHIFT (3U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_3_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_3_C0_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_4_C0_PWR_STAT_SHIFT (4U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_4_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_4_C0_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_5_C0_PWR_STAT_SHIFT (5U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_5_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_5_C0_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_6_C0_PWR_STAT_SHIFT (6U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_6_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_6_C0_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN0_STS0_PD_CPU_7_C0_PWR_STAT_SHIFT (7U) +#define PMU_PWR_CHAIN0_STS0_PD_CPU_7_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_CPU_7_C0_PWR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN0_STS0_PD_NPUTOP_C0_PWR_STAT_SHIFT (11U) +#define PMU_PWR_CHAIN0_STS0_PD_NPUTOP_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_NPUTOP_C0_PWR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN0_STS0_PD_NPU1_C0_PWR_STAT_SHIFT (12U) +#define PMU_PWR_CHAIN0_STS0_PD_NPU1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_NPU1_C0_PWR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN0_STS0_PD_NPU2_C0_PWR_STAT_SHIFT (13U) +#define PMU_PWR_CHAIN0_STS0_PD_NPU2_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_NPU2_C0_PWR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VENC0_C0_PWR_STAT_SHIFT (14U) +#define PMU_PWR_CHAIN0_STS0_PD_VENC0_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VENC0_C0_PWR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VENC1_C0_PWR_STAT_SHIFT (15U) +#define PMU_PWR_CHAIN0_STS0_PD_VENC1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VENC1_C0_PWR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_PWR_CHAIN0_STS0_PD_RKVDEC0_C0_PWR_STAT_SHIFT (16U) +#define PMU_PWR_CHAIN0_STS0_PD_RKVDEC0_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_RKVDEC0_C0_PWR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_PWR_CHAIN0_STS0_PD_RKVDEC1_C0_PWR_STAT_SHIFT (17U) +#define PMU_PWR_CHAIN0_STS0_PD_RKVDEC1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_RKVDEC1_C0_PWR_STAT_SHIFT) /* 0x00020000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VDPU_C0_PWR_STAT_SHIFT (18U) +#define PMU_PWR_CHAIN0_STS0_PD_VDPU_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VDPU_C0_PWR_STAT_SHIFT) /* 0x00040000 */ +#define PMU_PWR_CHAIN0_STS0_PD_RGA30_C0_PWR_STAT_SHIFT (19U) +#define PMU_PWR_CHAIN0_STS0_PD_RGA30_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_RGA30_C0_PWR_STAT_SHIFT) /* 0x00080000 */ +#define PMU_PWR_CHAIN0_STS0_PD_AV1_C0_PWR_STAT_SHIFT (20U) +#define PMU_PWR_CHAIN0_STS0_PD_AV1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_AV1_C0_PWR_STAT_SHIFT) /* 0x00100000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VI_C0_PWR_STAT_SHIFT (21U) +#define PMU_PWR_CHAIN0_STS0_PD_VI_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VI_C0_PWR_STAT_SHIFT) /* 0x00200000 */ +#define PMU_PWR_CHAIN0_STS0_PD_FEC_C0_PWR_STAT_SHIFT (22U) +#define PMU_PWR_CHAIN0_STS0_PD_FEC_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_FEC_C0_PWR_STAT_SHIFT) /* 0x00400000 */ +#define PMU_PWR_CHAIN0_STS0_PD_ISP1_C0_PWR_STAT_SHIFT (23U) +#define PMU_PWR_CHAIN0_STS0_PD_ISP1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_ISP1_C0_PWR_STAT_SHIFT) /* 0x00800000 */ +#define PMU_PWR_CHAIN0_STS0_PD_RGA31_C0_PWR_STAT_SHIFT (24U) +#define PMU_PWR_CHAIN0_STS0_PD_RGA31_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_RGA31_C0_PWR_STAT_SHIFT) /* 0x01000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VOP_C0_PWR_STAT_SHIFT (25U) +#define PMU_PWR_CHAIN0_STS0_PD_VOP_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VOP_C0_PWR_STAT_SHIFT) /* 0x02000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VO0_C0_PWR_STAT_SHIFT (26U) +#define PMU_PWR_CHAIN0_STS0_PD_VO0_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VO0_C0_PWR_STAT_SHIFT) /* 0x04000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_VO1_C0_PWR_STAT_SHIFT (27U) +#define PMU_PWR_CHAIN0_STS0_PD_VO1_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_VO1_C0_PWR_STAT_SHIFT) /* 0x08000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_AUDIO_C0_PWR_STAT_SHIFT (28U) +#define PMU_PWR_CHAIN0_STS0_PD_AUDIO_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_AUDIO_C0_PWR_STAT_SHIFT) /* 0x10000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_PHP_C0_PWR_STAT_SHIFT (29U) +#define PMU_PWR_CHAIN0_STS0_PD_PHP_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_PHP_C0_PWR_STAT_SHIFT) /* 0x20000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_GMAC_C0_PWR_STAT_SHIFT (30U) +#define PMU_PWR_CHAIN0_STS0_PD_GMAC_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_GMAC_C0_PWR_STAT_SHIFT) /* 0x40000000 */ +#define PMU_PWR_CHAIN0_STS0_PD_PCIE_C0_PWR_STAT_SHIFT (31U) +#define PMU_PWR_CHAIN0_STS0_PD_PCIE_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS0_PD_PCIE_C0_PWR_STAT_SHIFT) /* 0x80000000 */ +/* PWR_CHAIN0_STS1 */ +#define PMU_PWR_CHAIN0_STS1_OFFSET (0x81ECU) +#define PMU_PWR_CHAIN0_STS1 (0xFFU) +#define PMU_PWR_CHAIN0_STS1_PD_NVM_C0_PWR_STAT_SHIFT (0U) +#define PMU_PWR_CHAIN0_STS1_PD_NVM_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_NVM_C0_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN0_STS1_PD_NVM0_C0_PWR_STAT_SHIFT (1U) +#define PMU_PWR_CHAIN0_STS1_PD_NVM0_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_NVM0_C0_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN0_STS1_PD_SDIO_C0_PWR_STAT_SHIFT (2U) +#define PMU_PWR_CHAIN0_STS1_PD_SDIO_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_SDIO_C0_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN0_STS1_PD_USB_C0_PWR_STAT_SHIFT (3U) +#define PMU_PWR_CHAIN0_STS1_PD_USB_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_USB_C0_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN0_STS1_PD_SECURE_C0_PWR_STAT_SHIFT (4U) +#define PMU_PWR_CHAIN0_STS1_PD_SECURE_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_SECURE_C0_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN0_STS1_PD_SDMMC_C0_PWR_STAT_SHIFT (5U) +#define PMU_PWR_CHAIN0_STS1_PD_SDMMC_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_SDMMC_C0_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN0_STS1_PD_CRYPTO_C0_PWR_STAT_SHIFT (6U) +#define PMU_PWR_CHAIN0_STS1_PD_CRYPTO_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_CRYPTO_C0_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN0_STS1_PD_CENTER_C0_PWR_STAT_SHIFT (7U) +#define PMU_PWR_CHAIN0_STS1_PD_CENTER_C0_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN0_STS1_PD_CENTER_C0_PWR_STAT_SHIFT) /* 0x00000080 */ +/* PWR_CHAIN1_STS0 */ +#define PMU_PWR_CHAIN1_STS0_OFFSET (0x81F0U) +#define PMU_PWR_CHAIN1_STS0 (0xFFU) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_0_C1_PWR_STAT_SHIFT (0U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_0_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_0_C1_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_1_C1_PWR_STAT_SHIFT (1U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_1_C1_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_2_C1_PWR_STAT_SHIFT (2U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_2_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_2_C1_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_3_C1_PWR_STAT_SHIFT (3U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_3_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_3_C1_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_4_C1_PWR_STAT_SHIFT (4U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_4_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_4_C1_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_5_C1_PWR_STAT_SHIFT (5U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_5_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_5_C1_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_6_C1_PWR_STAT_SHIFT (6U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_6_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_6_C1_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN1_STS0_PD_CPU_7_C1_PWR_STAT_SHIFT (7U) +#define PMU_PWR_CHAIN1_STS0_PD_CPU_7_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_CPU_7_C1_PWR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_CHAIN1_STS0_PD_NPUTOP_C1_PWR_STAT_SHIFT (11U) +#define PMU_PWR_CHAIN1_STS0_PD_NPUTOP_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_NPUTOP_C1_PWR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_PWR_CHAIN1_STS0_PD_NPU1_C1_PWR_STAT_SHIFT (12U) +#define PMU_PWR_CHAIN1_STS0_PD_NPU1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_NPU1_C1_PWR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_PWR_CHAIN1_STS0_PD_NPU2_C1_PWR_STAT_SHIFT (13U) +#define PMU_PWR_CHAIN1_STS0_PD_NPU2_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_NPU2_C1_PWR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VENC0_C1_PWR_STAT_SHIFT (14U) +#define PMU_PWR_CHAIN1_STS0_PD_VENC0_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VENC0_C1_PWR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VENC1_C1_PWR_STAT_SHIFT (15U) +#define PMU_PWR_CHAIN1_STS0_PD_VENC1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VENC1_C1_PWR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_PWR_CHAIN1_STS0_PD_RKVDEC0_C1_PWR_STAT_SHIFT (16U) +#define PMU_PWR_CHAIN1_STS0_PD_RKVDEC0_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_RKVDEC0_C1_PWR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_PWR_CHAIN1_STS0_PD_RKVDEC1_C1_PWR_STAT_SHIFT (17U) +#define PMU_PWR_CHAIN1_STS0_PD_RKVDEC1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_RKVDEC1_C1_PWR_STAT_SHIFT) /* 0x00020000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VDPU_C1_PWR_STAT_SHIFT (18U) +#define PMU_PWR_CHAIN1_STS0_PD_VDPU_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VDPU_C1_PWR_STAT_SHIFT) /* 0x00040000 */ +#define PMU_PWR_CHAIN1_STS0_PD_RGA30_C1_PWR_STAT_SHIFT (19U) +#define PMU_PWR_CHAIN1_STS0_PD_RGA30_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_RGA30_C1_PWR_STAT_SHIFT) /* 0x00080000 */ +#define PMU_PWR_CHAIN1_STS0_PD_AV1_C1_PWR_STAT_SHIFT (20U) +#define PMU_PWR_CHAIN1_STS0_PD_AV1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_AV1_C1_PWR_STAT_SHIFT) /* 0x00100000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VI_C1_PWR_STAT_SHIFT (21U) +#define PMU_PWR_CHAIN1_STS0_PD_VI_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VI_C1_PWR_STAT_SHIFT) /* 0x00200000 */ +#define PMU_PWR_CHAIN1_STS0_PD_FEC_C1_PWR_STAT_SHIFT (22U) +#define PMU_PWR_CHAIN1_STS0_PD_FEC_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_FEC_C1_PWR_STAT_SHIFT) /* 0x00400000 */ +#define PMU_PWR_CHAIN1_STS0_PD_ISP1_C1_PWR_STAT_SHIFT (23U) +#define PMU_PWR_CHAIN1_STS0_PD_ISP1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_ISP1_C1_PWR_STAT_SHIFT) /* 0x00800000 */ +#define PMU_PWR_CHAIN1_STS0_PD_RGA31_C1_PWR_STAT_SHIFT (24U) +#define PMU_PWR_CHAIN1_STS0_PD_RGA31_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_RGA31_C1_PWR_STAT_SHIFT) /* 0x01000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VOP_C1_PWR_STAT_SHIFT (25U) +#define PMU_PWR_CHAIN1_STS0_PD_VOP_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VOP_C1_PWR_STAT_SHIFT) /* 0x02000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VO0_C1_PWR_STAT_SHIFT (26U) +#define PMU_PWR_CHAIN1_STS0_PD_VO0_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VO0_C1_PWR_STAT_SHIFT) /* 0x04000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_VO1_C1_PWR_STAT_SHIFT (27U) +#define PMU_PWR_CHAIN1_STS0_PD_VO1_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_VO1_C1_PWR_STAT_SHIFT) /* 0x08000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_AUDIO_C1_PWR_STAT_SHIFT (28U) +#define PMU_PWR_CHAIN1_STS0_PD_AUDIO_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_AUDIO_C1_PWR_STAT_SHIFT) /* 0x10000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_PHP_C1_PWR_STAT_SHIFT (29U) +#define PMU_PWR_CHAIN1_STS0_PD_PHP_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_PHP_C1_PWR_STAT_SHIFT) /* 0x20000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_GMAC_C1_PWR_STAT_SHIFT (30U) +#define PMU_PWR_CHAIN1_STS0_PD_GMAC_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_GMAC_C1_PWR_STAT_SHIFT) /* 0x40000000 */ +#define PMU_PWR_CHAIN1_STS0_PD_PCIE_C1_PWR_STAT_SHIFT (31U) +#define PMU_PWR_CHAIN1_STS0_PD_PCIE_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS0_PD_PCIE_C1_PWR_STAT_SHIFT) /* 0x80000000 */ +/* PWR_CHAIN1_STS1 */ +#define PMU_PWR_CHAIN1_STS1_OFFSET (0x81F4U) +#define PMU_PWR_CHAIN1_STS1 (0xFFU) +#define PMU_PWR_CHAIN1_STS1_PD_NVM_C1_PWR_STAT_SHIFT (0U) +#define PMU_PWR_CHAIN1_STS1_PD_NVM_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_NVM_C1_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_CHAIN1_STS1_PD_NVM0_C1_PWR_STAT_SHIFT (1U) +#define PMU_PWR_CHAIN1_STS1_PD_NVM0_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_NVM0_C1_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_CHAIN1_STS1_PD_SDIO_C1_PWR_STAT_SHIFT (2U) +#define PMU_PWR_CHAIN1_STS1_PD_SDIO_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_SDIO_C1_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_CHAIN1_STS1_PD_USB_C1_PWR_STAT_SHIFT (3U) +#define PMU_PWR_CHAIN1_STS1_PD_USB_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_USB_C1_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_CHAIN1_STS1_PD_SECURE_C1_PWR_STAT_SHIFT (4U) +#define PMU_PWR_CHAIN1_STS1_PD_SECURE_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_SECURE_C1_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_CHAIN1_STS1_PD_SDMMC_C1_PWR_STAT_SHIFT (5U) +#define PMU_PWR_CHAIN1_STS1_PD_SDMMC_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_SDMMC_C1_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_CHAIN1_STS1_PD_CRYPTO_C1_PWR_STAT_SHIFT (6U) +#define PMU_PWR_CHAIN1_STS1_PD_CRYPTO_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_CRYPTO_C1_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_CHAIN1_STS1_PD_CENTER_C1_PWR_STAT_SHIFT (7U) +#define PMU_PWR_CHAIN1_STS1_PD_CENTER_C1_PWR_STAT_MASK (0x1U << PMU_PWR_CHAIN1_STS1_PD_CENTER_C1_PWR_STAT_SHIFT) /* 0x00000080 */ +/* PWR_MEM_STS0 */ +#define PMU_PWR_MEM_STS0_OFFSET (0x81F8U) +#define PMU_PWR_MEM_STS0 (0xFFFBF800U) +#define PMU_PWR_MEM_STS0_PD_CPU_0_MEM_PWR_STAT_SHIFT (0U) +#define PMU_PWR_MEM_STS0_PD_CPU_0_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_0_MEM_PWR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_PWR_MEM_STS0_PD_CPU_1_MEM_PWR_STAT_SHIFT (1U) +#define PMU_PWR_MEM_STS0_PD_CPU_1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_1_MEM_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_MEM_STS0_PD_CPU_2_MEM_PWR_STAT_SHIFT (2U) +#define PMU_PWR_MEM_STS0_PD_CPU_2_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_2_MEM_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_MEM_STS0_PD_CPU_3_MEM_PWR_STAT_SHIFT (3U) +#define PMU_PWR_MEM_STS0_PD_CPU_3_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_3_MEM_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_MEM_STS0_PD_CPU_4_MEM_PWR_STAT_SHIFT (4U) +#define PMU_PWR_MEM_STS0_PD_CPU_4_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_4_MEM_PWR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_PWR_MEM_STS0_PD_CPU_5_MEM_PWR_STAT_SHIFT (5U) +#define PMU_PWR_MEM_STS0_PD_CPU_5_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_5_MEM_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_MEM_STS0_PD_CPU_6_MEM_PWR_STAT_SHIFT (6U) +#define PMU_PWR_MEM_STS0_PD_CPU_6_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_6_MEM_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_MEM_STS0_PD_CPU_7_MEM_PWR_STAT_SHIFT (7U) +#define PMU_PWR_MEM_STS0_PD_CPU_7_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_CPU_7_MEM_PWR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_MEM_STS0_PD_NPUTOP_MEM_PWR_STAT_SHIFT (11U) +#define PMU_PWR_MEM_STS0_PD_NPUTOP_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_NPUTOP_MEM_PWR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_PWR_MEM_STS0_PD_NPU1_MEM_PWR_STAT_SHIFT (12U) +#define PMU_PWR_MEM_STS0_PD_NPU1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_NPU1_MEM_PWR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_PWR_MEM_STS0_PD_NPU2_MEM_PWR_STAT_SHIFT (13U) +#define PMU_PWR_MEM_STS0_PD_NPU2_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_NPU2_MEM_PWR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_PWR_MEM_STS0_PD_VENC0_MEM_PWR_STAT_SHIFT (14U) +#define PMU_PWR_MEM_STS0_PD_VENC0_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VENC0_MEM_PWR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_PWR_MEM_STS0_PD_VENC1_MEM_PWR_STAT_SHIFT (15U) +#define PMU_PWR_MEM_STS0_PD_VENC1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VENC1_MEM_PWR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_PWR_MEM_STS0_PD_RKVDEC0_MEM_PWR_STAT_SHIFT (16U) +#define PMU_PWR_MEM_STS0_PD_RKVDEC0_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_RKVDEC0_MEM_PWR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_PWR_MEM_STS0_PD_RKVDEC1_MEM_PWR_STAT_SHIFT (17U) +#define PMU_PWR_MEM_STS0_PD_RKVDEC1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_RKVDEC1_MEM_PWR_STAT_SHIFT) /* 0x00020000 */ +#define PMU_PWR_MEM_STS0_PD_RGA30_MEM_PWR_STAT_SHIFT (19U) +#define PMU_PWR_MEM_STS0_PD_RGA30_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_RGA30_MEM_PWR_STAT_SHIFT) /* 0x00080000 */ +#define PMU_PWR_MEM_STS0_PD_AV1_MEM_PWR_STAT_SHIFT (20U) +#define PMU_PWR_MEM_STS0_PD_AV1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_AV1_MEM_PWR_STAT_SHIFT) /* 0x00100000 */ +#define PMU_PWR_MEM_STS0_PD_VI_MEM_PWR_STAT_SHIFT (21U) +#define PMU_PWR_MEM_STS0_PD_VI_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VI_MEM_PWR_STAT_SHIFT) /* 0x00200000 */ +#define PMU_PWR_MEM_STS0_PD_FEC_MEM_PWR_STAT_SHIFT (22U) +#define PMU_PWR_MEM_STS0_PD_FEC_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_FEC_MEM_PWR_STAT_SHIFT) /* 0x00400000 */ +#define PMU_PWR_MEM_STS0_PD_ISP1_MEM_PWR_STAT_SHIFT (23U) +#define PMU_PWR_MEM_STS0_PD_ISP1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_ISP1_MEM_PWR_STAT_SHIFT) /* 0x00800000 */ +#define PMU_PWR_MEM_STS0_PD_RGA31_MEM_PWR_STAT_SHIFT (24U) +#define PMU_PWR_MEM_STS0_PD_RGA31_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_RGA31_MEM_PWR_STAT_SHIFT) /* 0x01000000 */ +#define PMU_PWR_MEM_STS0_PD_VOP_MEM_PWR_STAT_SHIFT (25U) +#define PMU_PWR_MEM_STS0_PD_VOP_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VOP_MEM_PWR_STAT_SHIFT) /* 0x02000000 */ +#define PMU_PWR_MEM_STS0_PD_VO0_MEM_PWR_STAT_SHIFT (26U) +#define PMU_PWR_MEM_STS0_PD_VO0_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VO0_MEM_PWR_STAT_SHIFT) /* 0x04000000 */ +#define PMU_PWR_MEM_STS0_PD_VO1_MEM_PWR_STAT_SHIFT (27U) +#define PMU_PWR_MEM_STS0_PD_VO1_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_VO1_MEM_PWR_STAT_SHIFT) /* 0x08000000 */ +#define PMU_PWR_MEM_STS0_PD_AUDIO_MEM_PWR_STAT_SHIFT (28U) +#define PMU_PWR_MEM_STS0_PD_AUDIO_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_AUDIO_MEM_PWR_STAT_SHIFT) /* 0x10000000 */ +#define PMU_PWR_MEM_STS0_PD_PHP_MEM_PWR_STAT_SHIFT (29U) +#define PMU_PWR_MEM_STS0_PD_PHP_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_PHP_MEM_PWR_STAT_SHIFT) /* 0x20000000 */ +#define PMU_PWR_MEM_STS0_PD_GMAC_MEM_PWR_STAT_SHIFT (30U) +#define PMU_PWR_MEM_STS0_PD_GMAC_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_GMAC_MEM_PWR_STAT_SHIFT) /* 0x40000000 */ +#define PMU_PWR_MEM_STS0_PD_PCIE_MEM_PWR_STAT_SHIFT (31U) +#define PMU_PWR_MEM_STS0_PD_PCIE_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS0_PD_PCIE_MEM_PWR_STAT_SHIFT) /* 0x80000000 */ +/* PWR_MEM_STS1 */ +#define PMU_PWR_MEM_STS1_OFFSET (0x81FCU) +#define PMU_PWR_MEM_STS1 (0x0U) +#define PMU_PWR_MEM_STS1_PD_NVM0_MEM_PWR_STAT_SHIFT (1U) +#define PMU_PWR_MEM_STS1_PD_NVM0_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_NVM0_MEM_PWR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_PWR_MEM_STS1_PD_SDIO_MEM_PWR_STAT_SHIFT (2U) +#define PMU_PWR_MEM_STS1_PD_SDIO_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_SDIO_MEM_PWR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_PWR_MEM_STS1_PD_USB_MEM_PWR_STAT_SHIFT (3U) +#define PMU_PWR_MEM_STS1_PD_USB_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_USB_MEM_PWR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_PWR_MEM_STS1_PD_SDMMC_MEM_PWR_STAT_SHIFT (5U) +#define PMU_PWR_MEM_STS1_PD_SDMMC_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_SDMMC_MEM_PWR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_PWR_MEM_STS1_PD_CRYPTO_MEM_PWR_STAT_SHIFT (6U) +#define PMU_PWR_MEM_STS1_PD_CRYPTO_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_CRYPTO_MEM_PWR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_PWR_MEM_STS1_PD_CENTER_MEM_PWR_STAT_SHIFT (7U) +#define PMU_PWR_MEM_STS1_PD_CENTER_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_CENTER_MEM_PWR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_PWR_MEM_STS1_PD_DDR01_MEM_PWR_STAT_SHIFT (8U) +#define PMU_PWR_MEM_STS1_PD_DDR01_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_DDR01_MEM_PWR_STAT_SHIFT) /* 0x00000100 */ +#define PMU_PWR_MEM_STS1_PD_DDR23_MEM_PWR_STAT_SHIFT (9U) +#define PMU_PWR_MEM_STS1_PD_DDR23_MEM_PWR_STAT_MASK (0x1U << PMU_PWR_MEM_STS1_PD_DDR23_MEM_PWR_STAT_SHIFT) /* 0x00000200 */ +#define PMU_PWR_MEM_STS1_PD_DSU_MEM_PWR_STAT_SHIFT (10U) +#define PMU_PWR_MEM_STS1_PD_DSU_MEM_PWR_STAT_MASK (0x1FU << PMU_PWR_MEM_STS1_PD_DSU_MEM_PWR_STAT_SHIFT) /* 0x00007C00 */ +/* BISR_CON0 */ +#define PMU_BISR_CON0_OFFSET (0x8200U) +#define PMU_BISR_CON0_BISR_INIT_SHIFT (0U) +#define PMU_BISR_CON0_BISR_INIT_MASK (0x1U << PMU_BISR_CON0_BISR_INIT_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON0_BISR_PDGDONE_SEL_SHIFT (1U) +#define PMU_BISR_CON0_BISR_PDGDONE_SEL_MASK (0xFU << PMU_BISR_CON0_BISR_PDGDONE_SEL_SHIFT) /* 0x0000001E */ +#define PMU_BISR_CON0_BISR_CLKGATE_ENA_SHIFT (5U) +#define PMU_BISR_CON0_BISR_CLKGATE_ENA_MASK (0x1U << PMU_BISR_CON0_BISR_CLKGATE_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON0_BISR_CLKGATE_SFTENA_SHIFT (6U) +#define PMU_BISR_CON0_BISR_CLKGATE_SFTENA_MASK (0x1U << PMU_BISR_CON0_BISR_CLKGATE_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON0_BISR_TIMEOUT_ENA_SHIFT (7U) +#define PMU_BISR_CON0_BISR_TIMEOUT_ENA_MASK (0x1U << PMU_BISR_CON0_BISR_TIMEOUT_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON0_BISR_REPAIR_MODE_SHIFT (8U) +#define PMU_BISR_CON0_BISR_REPAIR_MODE_MASK (0x1U << PMU_BISR_CON0_BISR_REPAIR_MODE_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON0_BISR_RESETN_SFT_SHIFT (9U) +#define PMU_BISR_CON0_BISR_RESETN_SFT_MASK (0x1U << PMU_BISR_CON0_BISR_RESETN_SFT_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON0_BISR_SFT_ENA_SHIFT (10U) +#define PMU_BISR_CON0_BISR_SFT_ENA_MASK (0x1U << PMU_BISR_CON0_BISR_SFT_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON0_BISR_INITRSTN_DIS_SHIFT (11U) +#define PMU_BISR_CON0_BISR_INITRSTN_DIS_MASK (0x1U << PMU_BISR_CON0_BISR_INITRSTN_DIS_SHIFT) /* 0x00000800 */ +/* BISR_CON1 */ +#define PMU_BISR_CON1_OFFSET (0x8204U) +#define PMU_BISR_CON1_PD_GPU_BISR_ENA_SHIFT (1U) +#define PMU_BISR_CON1_PD_GPU_BISR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_GPU_BISR_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON1_PD_NPUTOP_REPAIR_ENA_SHIFT (2U) +#define PMU_BISR_CON1_PD_NPUTOP_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_NPUTOP_REPAIR_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON1_PD_NPU1_REPAIR_ENA_SHIFT (3U) +#define PMU_BISR_CON1_PD_NPU1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_NPU1_REPAIR_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON1_PD_NPU2_REPAIR_ENA_SHIFT (4U) +#define PMU_BISR_CON1_PD_NPU2_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_NPU2_REPAIR_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON1_PD_VENC0_REPAIR_ENA_SHIFT (5U) +#define PMU_BISR_CON1_PD_VENC0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_VENC0_REPAIR_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON1_PD_VENC1_REPAIR_ENA_SHIFT (6U) +#define PMU_BISR_CON1_PD_VENC1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_VENC1_REPAIR_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON1_PD_RKVDEC0_REPAIR_ENA_SHIFT (7U) +#define PMU_BISR_CON1_PD_RKVDEC0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_RKVDEC0_REPAIR_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON1_PD_RKVDEC1_REPAIR_ENA_SHIFT (8U) +#define PMU_BISR_CON1_PD_RKVDEC1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_RKVDEC1_REPAIR_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON1_PD_VDPU_REPAIR_ENA_SHIFT (9U) +#define PMU_BISR_CON1_PD_VDPU_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_VDPU_REPAIR_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON1_PD_RGA30_REPAIR_ENA_SHIFT (10U) +#define PMU_BISR_CON1_PD_RGA30_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_RGA30_REPAIR_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON1_PD_AV1_REPAIR_ENA_SHIFT (11U) +#define PMU_BISR_CON1_PD_AV1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_AV1_REPAIR_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON1_PD_VI_REPAIR_ENA_SHIFT (12U) +#define PMU_BISR_CON1_PD_VI_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_VI_REPAIR_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON1_PD_FEC_REPAIR_ENA_SHIFT (13U) +#define PMU_BISR_CON1_PD_FEC_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_FEC_REPAIR_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON1_PD_ISP1_REPAIR_ENA_SHIFT (14U) +#define PMU_BISR_CON1_PD_ISP1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_ISP1_REPAIR_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON1_PD_RGA31_REPAIR_ENA_SHIFT (15U) +#define PMU_BISR_CON1_PD_RGA31_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON1_PD_RGA31_REPAIR_ENA_SHIFT) /* 0x00008000 */ +/* BISR_CON2 */ +#define PMU_BISR_CON2_OFFSET (0x8208U) +#define PMU_BISR_CON2_PD_VOP_REPAIR_ENA_SHIFT (0U) +#define PMU_BISR_CON2_PD_VOP_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_VOP_REPAIR_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON2_PD_VO0_REPAIR_ENA_SHIFT (1U) +#define PMU_BISR_CON2_PD_VO0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_VO0_REPAIR_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON2_PD_VO1_REPAIR_ENA_SHIFT (2U) +#define PMU_BISR_CON2_PD_VO1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_VO1_REPAIR_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON2_PD_AUDIO_REPAIR_ENA_SHIFT (3U) +#define PMU_BISR_CON2_PD_AUDIO_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_AUDIO_REPAIR_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON2_PD_PHP_REPAIR_ENA_SHIFT (4U) +#define PMU_BISR_CON2_PD_PHP_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_PHP_REPAIR_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON2_PD_GMAC_REPAIR_ENA_SHIFT (5U) +#define PMU_BISR_CON2_PD_GMAC_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_GMAC_REPAIR_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON2_PD_PCIE_REPAIR_ENA_SHIFT (6U) +#define PMU_BISR_CON2_PD_PCIE_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_PCIE_REPAIR_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON2_PD_NVM0_REPAIR_ENA_SHIFT (7U) +#define PMU_BISR_CON2_PD_NVM0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_NVM0_REPAIR_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON2_PD_SDIO_REPAIR_ENA_SHIFT (8U) +#define PMU_BISR_CON2_PD_SDIO_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_SDIO_REPAIR_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON2_PD_USB_REPAIR_ENA_SHIFT (9U) +#define PMU_BISR_CON2_PD_USB_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_USB_REPAIR_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON2_PD_SDMMC_REPAIR_ENA_SHIFT (10U) +#define PMU_BISR_CON2_PD_SDMMC_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_SDMMC_REPAIR_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON2_PD_CRYPTO_REPAIR_ENA_SHIFT (11U) +#define PMU_BISR_CON2_PD_CRYPTO_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_CRYPTO_REPAIR_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON2_PD_CENTER_REPAIR_ENA_SHIFT (12U) +#define PMU_BISR_CON2_PD_CENTER_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_CENTER_REPAIR_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON2_PD_DDR01_REPAIR_ENA_SHIFT (13U) +#define PMU_BISR_CON2_PD_DDR01_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_DDR01_REPAIR_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON2_PD_DDR23_REPAIR_ENA_SHIFT (14U) +#define PMU_BISR_CON2_PD_DDR23_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_DDR23_REPAIR_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON2_PD_BUS_REPAIR_ENA_SHIFT (15U) +#define PMU_BISR_CON2_PD_BUS_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON2_PD_BUS_REPAIR_ENA_SHIFT) /* 0x00008000 */ +/* BISR_CON3 */ +#define PMU_BISR_CON3_OFFSET (0x820CU) +#define PMU_BISR_CON3_PD_DSU_REPAIR_ENA_SHIFT (0U) +#define PMU_BISR_CON3_PD_DSU_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_DSU_REPAIR_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON3_PD_CPU7_REPAIR_ENA_SHIFT (1U) +#define PMU_BISR_CON3_PD_CPU7_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU7_REPAIR_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON3_PD_CPU6_REPAIR_ENA_SHIFT (2U) +#define PMU_BISR_CON3_PD_CPU6_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU6_REPAIR_ENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON3_PD_CPU5_REPAIR_ENA_SHIFT (3U) +#define PMU_BISR_CON3_PD_CPU5_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU5_REPAIR_ENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON3_PD_CPU4_REPAIR_ENA_SHIFT (4U) +#define PMU_BISR_CON3_PD_CPU4_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU4_REPAIR_ENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON3_PD_CPU3_REPAIR_ENA_SHIFT (5U) +#define PMU_BISR_CON3_PD_CPU3_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU3_REPAIR_ENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON3_PD_CPU2_REPAIR_ENA_SHIFT (6U) +#define PMU_BISR_CON3_PD_CPU2_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU2_REPAIR_ENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON3_PD_CPU1_REPAIR_ENA_SHIFT (7U) +#define PMU_BISR_CON3_PD_CPU1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU1_REPAIR_ENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON3_PD_CPU0_REPAIR_ENA_SHIFT (8U) +#define PMU_BISR_CON3_PD_CPU0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_CPU0_REPAIR_ENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON3_PD_VOPCLUSTER0_REPAIR_ENA_SHIFT (9U) +#define PMU_BISR_CON3_PD_VOPCLUSTER0_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPCLUSTER0_REPAIR_ENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON3_PD_VOPCLUSTER1_REPAIR_ENA_SHIFT (10U) +#define PMU_BISR_CON3_PD_VOPCLUSTER1_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPCLUSTER1_REPAIR_ENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON3_PD_VOPCLUSTER2_REPAIR_ENA_SHIFT (11U) +#define PMU_BISR_CON3_PD_VOPCLUSTER2_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPCLUSTER2_REPAIR_ENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON3_PD_VOPCLUSTER3_REPAIR_ENA_SHIFT (12U) +#define PMU_BISR_CON3_PD_VOPCLUSTER3_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPCLUSTER3_REPAIR_ENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON3_PD_VOPDSC8K_REPAIR_ENA_SHIFT (13U) +#define PMU_BISR_CON3_PD_VOPDSC8K_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPDSC8K_REPAIR_ENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON3_PD_VOPDSC4K_REPAIR_ENA_SHIFT (14U) +#define PMU_BISR_CON3_PD_VOPDSC4K_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPDSC4K_REPAIR_ENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON3_PD_VOPESMART_REPAIR_ENA_SHIFT (15U) +#define PMU_BISR_CON3_PD_VOPESMART_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON3_PD_VOPESMART_REPAIR_ENA_SHIFT) /* 0x00008000 */ +/* BISR_CON4 */ +#define PMU_BISR_CON4_OFFSET (0x8210U) +#define PMU_BISR_CON4_PD_PMU1_REPAIR_SFTENA_SHIFT (0U) +#define PMU_BISR_CON4_PD_PMU1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_PMU1_REPAIR_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON4_PD_GPU_BISR_SFTENA_SHIFT (1U) +#define PMU_BISR_CON4_PD_GPU_BISR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_GPU_BISR_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON4_PD_NPUTOP_REPAIR_SFTENA_SHIFT (2U) +#define PMU_BISR_CON4_PD_NPUTOP_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_NPUTOP_REPAIR_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON4_PD_NPU1_REPAIR_SFTENA_SHIFT (3U) +#define PMU_BISR_CON4_PD_NPU1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_NPU1_REPAIR_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON4_PD_NPU2_REPAIR_SFTENA_SHIFT (4U) +#define PMU_BISR_CON4_PD_NPU2_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_NPU2_REPAIR_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON4_PD_VENC0_REPAIR_SFTENA_SHIFT (5U) +#define PMU_BISR_CON4_PD_VENC0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_VENC0_REPAIR_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON4_PD_VENC1_REPAIR_SFTENA_SHIFT (6U) +#define PMU_BISR_CON4_PD_VENC1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_VENC1_REPAIR_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON4_PD_RKVDEC0_REPAIR_SFTENA_SHIFT (7U) +#define PMU_BISR_CON4_PD_RKVDEC0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_RKVDEC0_REPAIR_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON4_PD_RKVDEC1_REPAIR_SFTENA_SHIFT (8U) +#define PMU_BISR_CON4_PD_RKVDEC1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_RKVDEC1_REPAIR_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON4_PD_VDPU_REPAIR_SFTENA_SHIFT (9U) +#define PMU_BISR_CON4_PD_VDPU_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_VDPU_REPAIR_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON4_PD_RGA30_REPAIR_SFTENA_SHIFT (10U) +#define PMU_BISR_CON4_PD_RGA30_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_RGA30_REPAIR_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON4_PD_AV1_REPAIR_SFTENA_SHIFT (11U) +#define PMU_BISR_CON4_PD_AV1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_AV1_REPAIR_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON4_PD_VI_REPAIR_SFTENA_SHIFT (12U) +#define PMU_BISR_CON4_PD_VI_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_VI_REPAIR_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON4_PD_FEC_REPAIR_SFTENA_SHIFT (13U) +#define PMU_BISR_CON4_PD_FEC_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_FEC_REPAIR_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON4_PD_ISP1_REPAIR_SFTENA_SHIFT (14U) +#define PMU_BISR_CON4_PD_ISP1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_ISP1_REPAIR_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON4_PD_RGA31_REPAIR_SFTENA_SHIFT (15U) +#define PMU_BISR_CON4_PD_RGA31_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON4_PD_RGA31_REPAIR_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON5 */ +#define PMU_BISR_CON5_OFFSET (0x8214U) +#define PMU_BISR_CON5_PD_VOP_REPAIR_SFTENA_SHIFT (0U) +#define PMU_BISR_CON5_PD_VOP_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_VOP_REPAIR_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON5_PD_VO0_REPAIR_SFTENA_SHIFT (1U) +#define PMU_BISR_CON5_PD_VO0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_VO0_REPAIR_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON5_PD_VO1_REPAIR_SFTENA_SHIFT (2U) +#define PMU_BISR_CON5_PD_VO1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_VO1_REPAIR_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON5_PD_AUDIO_REPAIR_SFTENA_SHIFT (3U) +#define PMU_BISR_CON5_PD_AUDIO_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_AUDIO_REPAIR_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON5_PD_PHP_REPAIR_SFTENA_SHIFT (4U) +#define PMU_BISR_CON5_PD_PHP_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_PHP_REPAIR_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON5_PD_GMAC_REPAIR_SFTENA_SHIFT (5U) +#define PMU_BISR_CON5_PD_GMAC_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_GMAC_REPAIR_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON5_PD_PCIE_REPAIR_SFTENA_SHIFT (6U) +#define PMU_BISR_CON5_PD_PCIE_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_PCIE_REPAIR_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON5_PD_NVM0_REPAIR_SFTENA_SHIFT (7U) +#define PMU_BISR_CON5_PD_NVM0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_NVM0_REPAIR_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON5_PD_SDIO_REPAIR_SFTENA_SHIFT (8U) +#define PMU_BISR_CON5_PD_SDIO_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_SDIO_REPAIR_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON5_PD_USB_REPAIR_SFTENA_SHIFT (9U) +#define PMU_BISR_CON5_PD_USB_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_USB_REPAIR_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON5_PD_SDMMC_REPAIR_SFTENA_SHIFT (10U) +#define PMU_BISR_CON5_PD_SDMMC_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_SDMMC_REPAIR_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON5_PD_CRYPTO_REPAIR_SFTENA_SHIFT (11U) +#define PMU_BISR_CON5_PD_CRYPTO_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_CRYPTO_REPAIR_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON5_PD_CENTER_REPAIR_SFTENA_SHIFT (12U) +#define PMU_BISR_CON5_PD_CENTER_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_CENTER_REPAIR_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON5_PD_DDR01_REPAIR_SFTENA_SHIFT (13U) +#define PMU_BISR_CON5_PD_DDR01_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_DDR01_REPAIR_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON5_PD_DDR23_REPAIR_SFTENA_SHIFT (14U) +#define PMU_BISR_CON5_PD_DDR23_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_DDR23_REPAIR_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON5_PD_BUS_REPAIR_SFTENA_SHIFT (15U) +#define PMU_BISR_CON5_PD_BUS_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON5_PD_BUS_REPAIR_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON6 */ +#define PMU_BISR_CON6_OFFSET (0x8218U) +#define PMU_BISR_CON6_PD_DSU_REPAIR_SFTENA_SHIFT (0U) +#define PMU_BISR_CON6_PD_DSU_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_DSU_REPAIR_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON6_PD_CPU7_REPAIR_SFTENA_SHIFT (1U) +#define PMU_BISR_CON6_PD_CPU7_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU7_REPAIR_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON6_PD_CPU6_REPAIR_SFTENA_SHIFT (2U) +#define PMU_BISR_CON6_PD_CPU6_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU6_REPAIR_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON6_PD_CPU5_REPAIR_SFTENA_SHIFT (3U) +#define PMU_BISR_CON6_PD_CPU5_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU5_REPAIR_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON6_PD_CPU4_REPAIR_SFTENA_SHIFT (4U) +#define PMU_BISR_CON6_PD_CPU4_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU4_REPAIR_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON6_PD_CPU3_REPAIR_SFTENA_SHIFT (5U) +#define PMU_BISR_CON6_PD_CPU3_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU3_REPAIR_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON6_PD_CPU2_REPAIR_SFTENA_SHIFT (6U) +#define PMU_BISR_CON6_PD_CPU2_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU2_REPAIR_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON6_PD_CPU1_REPAIR_SFTENA_SHIFT (7U) +#define PMU_BISR_CON6_PD_CPU1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU1_REPAIR_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON6_PD_CPU0_REPAIR_SFTENA_SHIFT (8U) +#define PMU_BISR_CON6_PD_CPU0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_CPU0_REPAIR_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON6_PD_VOPCLUSTER0_REPAIR_SFTENA_SHIFT (9U) +#define PMU_BISR_CON6_PD_VOPCLUSTER0_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPCLUSTER0_REPAIR_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON6_PD_VOPCLUSTER1_REPAIR_SFTENA_SHIFT (10U) +#define PMU_BISR_CON6_PD_VOPCLUSTER1_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPCLUSTER1_REPAIR_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON6_PD_VOPCLUSTER2_REPAIR_SFTENA_SHIFT (11U) +#define PMU_BISR_CON6_PD_VOPCLUSTER2_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPCLUSTER2_REPAIR_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON6_PD_VOPCLUSTER3_REPAIR_SFTENA_SHIFT (12U) +#define PMU_BISR_CON6_PD_VOPCLUSTER3_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPCLUSTER3_REPAIR_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON6_PD_VOPDSC8K_REPAIR_SFTENA_SHIFT (13U) +#define PMU_BISR_CON6_PD_VOPDSC8K_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPDSC8K_REPAIR_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON6_PD_VOPDSC4K_REPAIR_SFTENA_SHIFT (14U) +#define PMU_BISR_CON6_PD_VOPDSC4K_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPDSC4K_REPAIR_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON6_PD_VOPESMART_REPAIR_SFTENA_SHIFT (15U) +#define PMU_BISR_CON6_PD_VOPESMART_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON6_PD_VOPESMART_REPAIR_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON7 */ +#define PMU_BISR_CON7_OFFSET (0x821CU) +#define PMU_BISR_CON7_PD_PMU1_PDGDONE_SFTENA_SHIFT (0U) +#define PMU_BISR_CON7_PD_PMU1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_PMU1_PDGDONE_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON7_PD_GPU_PDGDONE_SFTENA_SHIFT (1U) +#define PMU_BISR_CON7_PD_GPU_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_GPU_PDGDONE_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON7_PD_NPUTOP_PDGDONE_SFTENA_SHIFT (2U) +#define PMU_BISR_CON7_PD_NPUTOP_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_NPUTOP_PDGDONE_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON7_PD_NPU1_PDGDONE_SFTENA_SHIFT (3U) +#define PMU_BISR_CON7_PD_NPU1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_NPU1_PDGDONE_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON7_PD_NPU2_PDGDONE_SFTENA_SHIFT (4U) +#define PMU_BISR_CON7_PD_NPU2_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_NPU2_PDGDONE_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON7_PD_VENC0_PDGDONE_SFTENA_SHIFT (5U) +#define PMU_BISR_CON7_PD_VENC0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_VENC0_PDGDONE_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON7_PD_VENC1_PDGDONE_SFTENA_SHIFT (6U) +#define PMU_BISR_CON7_PD_VENC1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_VENC1_PDGDONE_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON7_PD_RKVDEC0_PDGDONE_SFTENA_SHIFT (7U) +#define PMU_BISR_CON7_PD_RKVDEC0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_RKVDEC0_PDGDONE_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON7_PD_RKVDEC1_PDGDONE_SFTENA_SHIFT (8U) +#define PMU_BISR_CON7_PD_RKVDEC1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_RKVDEC1_PDGDONE_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON7_PD_VDPU_PDGDONE_SFTENA_SHIFT (9U) +#define PMU_BISR_CON7_PD_VDPU_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_VDPU_PDGDONE_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON7_PD_RGA30_PDGDONE_SFTENA_SHIFT (10U) +#define PMU_BISR_CON7_PD_RGA30_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_RGA30_PDGDONE_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON7_PD_AV1_PDGDONE_SFTENA_SHIFT (11U) +#define PMU_BISR_CON7_PD_AV1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_AV1_PDGDONE_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON7_PD_VI_PDGDONE_SFTENA_SHIFT (12U) +#define PMU_BISR_CON7_PD_VI_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_VI_PDGDONE_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON7_PD_FEC_PDGDONE_SFTENA_SHIFT (13U) +#define PMU_BISR_CON7_PD_FEC_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_FEC_PDGDONE_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON7_PD_ISP1_PDGDONE_SFTENA_SHIFT (14U) +#define PMU_BISR_CON7_PD_ISP1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_ISP1_PDGDONE_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON7_PD_RGA31_PDGDONE_SFTENA_SHIFT (15U) +#define PMU_BISR_CON7_PD_RGA31_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON7_PD_RGA31_PDGDONE_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON8 */ +#define PMU_BISR_CON8_OFFSET (0x8220U) +#define PMU_BISR_CON8_PD_VOP_PDGDONE_SFTENA_SHIFT (0U) +#define PMU_BISR_CON8_PD_VOP_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_VOP_PDGDONE_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON8_PD_VO0_PDGDONE_SFTENA_SHIFT (1U) +#define PMU_BISR_CON8_PD_VO0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_VO0_PDGDONE_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON8_PD_VO1_PDGDONE_SFTENA_SHIFT (2U) +#define PMU_BISR_CON8_PD_VO1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_VO1_PDGDONE_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON8_PD_AUDIO_PDGDONE_SFTENA_SHIFT (3U) +#define PMU_BISR_CON8_PD_AUDIO_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_AUDIO_PDGDONE_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON8_PD_PHP_PDGDONE_SFTENA_SHIFT (4U) +#define PMU_BISR_CON8_PD_PHP_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_PHP_PDGDONE_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON8_PD_GMAC_PDGDONE_SFTENA_SHIFT (5U) +#define PMU_BISR_CON8_PD_GMAC_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_GMAC_PDGDONE_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON8_PD_PCIE_PDGDONE_SFTENA_SHIFT (6U) +#define PMU_BISR_CON8_PD_PCIE_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_PCIE_PDGDONE_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON8_PD_NVM0_PDGDONE_SFTENA_SHIFT (7U) +#define PMU_BISR_CON8_PD_NVM0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_NVM0_PDGDONE_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON8_PD_SDIO_PDGDONE_SFTENA_SHIFT (8U) +#define PMU_BISR_CON8_PD_SDIO_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_SDIO_PDGDONE_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON8_PD_USB_PDGDONE_SFTENA_SHIFT (9U) +#define PMU_BISR_CON8_PD_USB_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_USB_PDGDONE_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON8_PD_SDMMC_PDGDONE_SFTENA_SHIFT (10U) +#define PMU_BISR_CON8_PD_SDMMC_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_SDMMC_PDGDONE_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON8_PD_CRYPTO_PDGDONE_SFTENA_SHIFT (11U) +#define PMU_BISR_CON8_PD_CRYPTO_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_CRYPTO_PDGDONE_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON8_PD_CENTER_PDGDONE_SFTENA_SHIFT (12U) +#define PMU_BISR_CON8_PD_CENTER_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_CENTER_PDGDONE_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON8_PD_DDR01_PDGDONE_SFTENA_SHIFT (13U) +#define PMU_BISR_CON8_PD_DDR01_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_DDR01_PDGDONE_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON8_PD_DDR23_PDGDONE_SFTENA_SHIFT (14U) +#define PMU_BISR_CON8_PD_DDR23_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_DDR23_PDGDONE_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON8_PD_BUS_PDGDONE_SFTENA_SHIFT (15U) +#define PMU_BISR_CON8_PD_BUS_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON8_PD_BUS_PDGDONE_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON9 */ +#define PMU_BISR_CON9_OFFSET (0x8224U) +#define PMU_BISR_CON9_PD_DSU_PDGDONE_SFTENA_SHIFT (0U) +#define PMU_BISR_CON9_PD_DSU_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_DSU_PDGDONE_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON9_PD_CPU7_PDGDONE_SFTENA_SHIFT (1U) +#define PMU_BISR_CON9_PD_CPU7_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU7_PDGDONE_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON9_PD_CPU6_PDGDONE_SFTENA_SHIFT (2U) +#define PMU_BISR_CON9_PD_CPU6_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU6_PDGDONE_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON9_PD_CPU5_PDGDONE_SFTENA_SHIFT (3U) +#define PMU_BISR_CON9_PD_CPU5_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU5_PDGDONE_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON9_PD_CPU4_PDGDONE_SFTENA_SHIFT (4U) +#define PMU_BISR_CON9_PD_CPU4_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU4_PDGDONE_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON9_PD_CPU3_PDGDONE_SFTENA_SHIFT (5U) +#define PMU_BISR_CON9_PD_CPU3_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU3_PDGDONE_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON9_PD_CPU2_PDGDONE_SFTENA_SHIFT (6U) +#define PMU_BISR_CON9_PD_CPU2_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU2_PDGDONE_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON9_PD_CPU1_PDGDONE_SFTENA_SHIFT (7U) +#define PMU_BISR_CON9_PD_CPU1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU1_PDGDONE_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON9_PD_CPU0_PDGDONE_SFTENA_SHIFT (8U) +#define PMU_BISR_CON9_PD_CPU0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_CPU0_PDGDONE_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON9_PD_VOPCLUSTER0_PDGDONE_SFTENA_SHIFT (9U) +#define PMU_BISR_CON9_PD_VOPCLUSTER0_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPCLUSTER0_PDGDONE_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON9_PD_VOPCLUSTER1_PDGDONE_SFTENA_SHIFT (10U) +#define PMU_BISR_CON9_PD_VOPCLUSTER1_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPCLUSTER1_PDGDONE_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON9_PD_VOPCLUSTER2_PDGDONE_SFTENA_SHIFT (11U) +#define PMU_BISR_CON9_PD_VOPCLUSTER2_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPCLUSTER2_PDGDONE_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON9_PD_VOPCLUSTER3_PDGDONE_SFTENA_SHIFT (12U) +#define PMU_BISR_CON9_PD_VOPCLUSTER3_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPCLUSTER3_PDGDONE_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON9_PD_VOPDSC8K_PDGDONE_SFTENA_SHIFT (13U) +#define PMU_BISR_CON9_PD_VOPDSC8K_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPDSC8K_PDGDONE_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON9_PD_VOPDSC4K_PDGDONE_SFTENA_SHIFT (14U) +#define PMU_BISR_CON9_PD_VOPDSC4K_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPDSC4K_PDGDONE_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON9_PD_VOPESMART_PDGDONE_SFTENA_SHIFT (15U) +#define PMU_BISR_CON9_PD_VOPESMART_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON9_PD_VOPESMART_PDGDONE_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON10 */ +#define PMU_BISR_CON10_OFFSET (0x8228U) +#define PMU_BISR_CON10_PD_PMU1_INITRSTN_SFTENA_SHIFT (0U) +#define PMU_BISR_CON10_PD_PMU1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_PMU1_INITRSTN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON10_PD_GPU_INITRSTN_SFTENA_SHIFT (1U) +#define PMU_BISR_CON10_PD_GPU_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_GPU_INITRSTN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON10_PD_NPUTOP_INITRSTN_SFTENA_SHIFT (2U) +#define PMU_BISR_CON10_PD_NPUTOP_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_NPUTOP_INITRSTN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON10_PD_NPU1_INITRSTN_SFTENA_SHIFT (3U) +#define PMU_BISR_CON10_PD_NPU1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_NPU1_INITRSTN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON10_PD_NPU2_INITRSTN_SFTENA_SHIFT (4U) +#define PMU_BISR_CON10_PD_NPU2_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_NPU2_INITRSTN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON10_PD_VENC0_INITRSTN_SFTENA_SHIFT (5U) +#define PMU_BISR_CON10_PD_VENC0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_VENC0_INITRSTN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON10_PD_VENC1_INITRSTN_SFTENA_SHIFT (6U) +#define PMU_BISR_CON10_PD_VENC1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_VENC1_INITRSTN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON10_PD_RKVDEC0_INITRSTN_SFTENA_SHIFT (7U) +#define PMU_BISR_CON10_PD_RKVDEC0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_RKVDEC0_INITRSTN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON10_PD_RKVDEC1_INITRSTN_SFTENA_SHIFT (8U) +#define PMU_BISR_CON10_PD_RKVDEC1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_RKVDEC1_INITRSTN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON10_PD_VDPU_INITRSTN_SFTENA_SHIFT (9U) +#define PMU_BISR_CON10_PD_VDPU_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_VDPU_INITRSTN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON10_PD_RGA30_INITRSTN_SFTENA_SHIFT (10U) +#define PMU_BISR_CON10_PD_RGA30_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_RGA30_INITRSTN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON10_PD_AV1_INITRSTN_SFTENA_SHIFT (11U) +#define PMU_BISR_CON10_PD_AV1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_AV1_INITRSTN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON10_PD_VI_INITRSTN_SFTENA_SHIFT (12U) +#define PMU_BISR_CON10_PD_VI_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_VI_INITRSTN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON10_PD_FEC_INITRSTN_SFTENA_SHIFT (13U) +#define PMU_BISR_CON10_PD_FEC_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_FEC_INITRSTN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON10_PD_ISP1_INITRSTN_SFTENA_SHIFT (14U) +#define PMU_BISR_CON10_PD_ISP1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_ISP1_INITRSTN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON10_PD_RGA31_INITRSTN_SFTENA_SHIFT (15U) +#define PMU_BISR_CON10_PD_RGA31_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON10_PD_RGA31_INITRSTN_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON11 */ +#define PMU_BISR_CON11_OFFSET (0x822CU) +#define PMU_BISR_CON11_PD_VOP_INITRSTN_SFTENA_SHIFT (0U) +#define PMU_BISR_CON11_PD_VOP_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_VOP_INITRSTN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON11_PD_VO0_INITRSTN_SFTENA_SHIFT (1U) +#define PMU_BISR_CON11_PD_VO0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_VO0_INITRSTN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON11_PD_VO1_INITRSTN_SFTENA_SHIFT (2U) +#define PMU_BISR_CON11_PD_VO1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_VO1_INITRSTN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON11_PD_AUDIO_INITRSTN_SFTENA_SHIFT (3U) +#define PMU_BISR_CON11_PD_AUDIO_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_AUDIO_INITRSTN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON11_PD_PHP_INITRSTN_SFTENA_SHIFT (4U) +#define PMU_BISR_CON11_PD_PHP_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_PHP_INITRSTN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON11_PD_GMAC_INITRSTN_SFTENA_SHIFT (5U) +#define PMU_BISR_CON11_PD_GMAC_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_GMAC_INITRSTN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON11_PD_PCIE_INITRSTN_SFTENA_SHIFT (6U) +#define PMU_BISR_CON11_PD_PCIE_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_PCIE_INITRSTN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON11_PD_NVM0_INITRSTN_SFTENA_SHIFT (7U) +#define PMU_BISR_CON11_PD_NVM0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_NVM0_INITRSTN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON11_PD_SDIO_INITRSTN_SFTENA_SHIFT (8U) +#define PMU_BISR_CON11_PD_SDIO_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_SDIO_INITRSTN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON11_PD_USB_INITRSTN_SFTENA_SHIFT (9U) +#define PMU_BISR_CON11_PD_USB_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_USB_INITRSTN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON11_PD_SDMMC_INITRSTN_SFTENA_SHIFT (10U) +#define PMU_BISR_CON11_PD_SDMMC_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_SDMMC_INITRSTN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON11_PD_CRYPTO_INITRSTN_SFTENA_SHIFT (11U) +#define PMU_BISR_CON11_PD_CRYPTO_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_CRYPTO_INITRSTN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON11_PD_CENTER_INITRSTN_SFTENA_SHIFT (12U) +#define PMU_BISR_CON11_PD_CENTER_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_CENTER_INITRSTN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON11_PD_DDR01_INITRSTN_SFTENA_SHIFT (13U) +#define PMU_BISR_CON11_PD_DDR01_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_DDR01_INITRSTN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON11_PD_DDR23_INITRSTN_SFTENA_SHIFT (14U) +#define PMU_BISR_CON11_PD_DDR23_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_DDR23_INITRSTN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON11_PD_BUS_INITRSTN_SFTENA_SHIFT (15U) +#define PMU_BISR_CON11_PD_BUS_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON11_PD_BUS_INITRSTN_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON12 */ +#define PMU_BISR_CON12_OFFSET (0x8230U) +#define PMU_BISR_CON12_PD_DSU_INITRSTN_SFTENA_SHIFT (0U) +#define PMU_BISR_CON12_PD_DSU_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_DSU_INITRSTN_SFTENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON12_PD_CPU7_INITRSTN_SFTENA_SHIFT (1U) +#define PMU_BISR_CON12_PD_CPU7_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU7_INITRSTN_SFTENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON12_PD_CPU6_INITRSTN_SFTENA_SHIFT (2U) +#define PMU_BISR_CON12_PD_CPU6_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU6_INITRSTN_SFTENA_SHIFT) /* 0x00000004 */ +#define PMU_BISR_CON12_PD_CPU5_INITRSTN_SFTENA_SHIFT (3U) +#define PMU_BISR_CON12_PD_CPU5_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU5_INITRSTN_SFTENA_SHIFT) /* 0x00000008 */ +#define PMU_BISR_CON12_PD_CPU4_INITRSTN_SFTENA_SHIFT (4U) +#define PMU_BISR_CON12_PD_CPU4_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU4_INITRSTN_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON12_PD_CPU3_INITRSTN_SFTENA_SHIFT (5U) +#define PMU_BISR_CON12_PD_CPU3_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU3_INITRSTN_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON12_PD_CPU2_INITRSTN_SFTENA_SHIFT (6U) +#define PMU_BISR_CON12_PD_CPU2_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU2_INITRSTN_SFTENA_SHIFT) /* 0x00000040 */ +#define PMU_BISR_CON12_PD_CPU1_INITRSTN_SFTENA_SHIFT (7U) +#define PMU_BISR_CON12_PD_CPU1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU1_INITRSTN_SFTENA_SHIFT) /* 0x00000080 */ +#define PMU_BISR_CON12_PD_CPU0_INITRSTN_SFTENA_SHIFT (8U) +#define PMU_BISR_CON12_PD_CPU0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_CPU0_INITRSTN_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON12_PD_VOPCLUSTER0_INITRSTN_SFTENA_SHIFT (9U) +#define PMU_BISR_CON12_PD_VOPCLUSTER0_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPCLUSTER0_INITRSTN_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON12_PD_VOPCLUSTER1_INITRSTN_SFTENA_SHIFT (10U) +#define PMU_BISR_CON12_PD_VOPCLUSTER1_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPCLUSTER1_INITRSTN_SFTENA_SHIFT) /* 0x00000400 */ +#define PMU_BISR_CON12_PD_VOPCLUSTER2_INITRSTN_SFTENA_SHIFT (11U) +#define PMU_BISR_CON12_PD_VOPCLUSTER2_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPCLUSTER2_INITRSTN_SFTENA_SHIFT) /* 0x00000800 */ +#define PMU_BISR_CON12_PD_VOPCLUSTER3_INITRSTN_SFTENA_SHIFT (12U) +#define PMU_BISR_CON12_PD_VOPCLUSTER3_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPCLUSTER3_INITRSTN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON12_PD_VOPDSC8K_INITRSTN_SFTENA_SHIFT (13U) +#define PMU_BISR_CON12_PD_VOPDSC8K_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPDSC8K_INITRSTN_SFTENA_SHIFT) /* 0x00002000 */ +#define PMU_BISR_CON12_PD_VOPDSC4K_INITRSTN_SFTENA_SHIFT (14U) +#define PMU_BISR_CON12_PD_VOPDSC4K_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPDSC4K_INITRSTN_SFTENA_SHIFT) /* 0x00004000 */ +#define PMU_BISR_CON12_PD_VOPESMART_INITRSTN_SFTENA_SHIFT (15U) +#define PMU_BISR_CON12_PD_VOPESMART_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON12_PD_VOPESMART_INITRSTN_SFTENA_SHIFT) /* 0x00008000 */ +/* BISR_CON13 */ +#define PMU_BISR_CON13_OFFSET (0x8234U) +#define PMU_BISR_CON13_HDMIRXPHY_REPAIR_ENA_SHIFT (0U) +#define PMU_BISR_CON13_HDMIRXPHY_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON13_HDMIRXPHY_REPAIR_ENA_SHIFT) /* 0x00000001 */ +#define PMU_BISR_CON13_PCIEPHY_REPAIR_ENA_SHIFT (1U) +#define PMU_BISR_CON13_PCIEPHY_REPAIR_ENA_MASK (0x1U << PMU_BISR_CON13_PCIEPHY_REPAIR_ENA_SHIFT) /* 0x00000002 */ +#define PMU_BISR_CON13_HDMIRXPHY_REPAIR_SFTENA_SHIFT (4U) +#define PMU_BISR_CON13_HDMIRXPHY_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON13_HDMIRXPHY_REPAIR_SFTENA_SHIFT) /* 0x00000010 */ +#define PMU_BISR_CON13_PCIEPHY_REPAIR_SFTENA_SHIFT (5U) +#define PMU_BISR_CON13_PCIEPHY_REPAIR_SFTENA_MASK (0x1U << PMU_BISR_CON13_PCIEPHY_REPAIR_SFTENA_SHIFT) /* 0x00000020 */ +#define PMU_BISR_CON13_HDMIRXPHY_PDGDONE_SFTENA_SHIFT (8U) +#define PMU_BISR_CON13_HDMIRXPHY_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON13_HDMIRXPHY_PDGDONE_SFTENA_SHIFT) /* 0x00000100 */ +#define PMU_BISR_CON13_PCIEPHY_PDGDONE_SFTENA_SHIFT (9U) +#define PMU_BISR_CON13_PCIEPHY_PDGDONE_SFTENA_MASK (0x1U << PMU_BISR_CON13_PCIEPHY_PDGDONE_SFTENA_SHIFT) /* 0x00000200 */ +#define PMU_BISR_CON13_HDMIRXPHY_INITRSTN_SFTENA_SHIFT (12U) +#define PMU_BISR_CON13_HDMIRXPHY_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON13_HDMIRXPHY_INITRSTN_SFTENA_SHIFT) /* 0x00001000 */ +#define PMU_BISR_CON13_PCIEPHY_INITRSTN_SFTENA_SHIFT (13U) +#define PMU_BISR_CON13_PCIEPHY_INITRSTN_SFTENA_MASK (0x1U << PMU_BISR_CON13_PCIEPHY_INITRSTN_SFTENA_SHIFT) /* 0x00002000 */ +/* BISR_CON14 */ +#define PMU_BISR_CON14_OFFSET (0x8238U) +#define PMU_BISR_CON14_BISR_TIMEOUT_CNT_SHIFT (0U) +#define PMU_BISR_CON14_BISR_TIMEOUT_CNT_MASK (0xFFFFFFFFU << PMU_BISR_CON14_BISR_TIMEOUT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* BISR_STS0 */ +#define PMU_BISR_STS0_OFFSET (0x8280U) +#define PMU_BISR_STS0 (0x0U) +#define PMU_BISR_STS0_PD_PMU1_REPAIR_PDGDONE_SHIFT (0U) +#define PMU_BISR_STS0_PD_PMU1_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_PMU1_REPAIR_PDGDONE_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS0_PD_GPU_BISR_PDGDONE_SHIFT (1U) +#define PMU_BISR_STS0_PD_GPU_BISR_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_GPU_BISR_PDGDONE_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS0_PD_NPUTOP_DWN_PDGDONE_SHIFT (2U) +#define PMU_BISR_STS0_PD_NPUTOP_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_NPUTOP_DWN_PDGDONE_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS0_PD_NPU1_DWN_PDGDONE_SHIFT (3U) +#define PMU_BISR_STS0_PD_NPU1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_NPU1_DWN_PDGDONE_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS0_PD_NPU2_DWN_PDGDONE_SHIFT (4U) +#define PMU_BISR_STS0_PD_NPU2_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_NPU2_DWN_PDGDONE_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS0_PD_VENC0_DWN_PDGDONE_SHIFT (5U) +#define PMU_BISR_STS0_PD_VENC0_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VENC0_DWN_PDGDONE_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS0_PD_VENC1_DWN_PDGDONE_SHIFT (6U) +#define PMU_BISR_STS0_PD_VENC1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VENC1_DWN_PDGDONE_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS0_PD_RKVDEC0_DWN_PDGDONE_SHIFT (7U) +#define PMU_BISR_STS0_PD_RKVDEC0_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_RKVDEC0_DWN_PDGDONE_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS0_PD_RKVDEC1_DWN_PDGDONE_SHIFT (8U) +#define PMU_BISR_STS0_PD_RKVDEC1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_RKVDEC1_DWN_PDGDONE_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS0_PD_VDPU_DWN_PDGDONE_SHIFT (9U) +#define PMU_BISR_STS0_PD_VDPU_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VDPU_DWN_PDGDONE_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS0_PD_RGA30_DWN_PDGDONE_SHIFT (10U) +#define PMU_BISR_STS0_PD_RGA30_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_RGA30_DWN_PDGDONE_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS0_PD_AV1_DWN_PDGDONE_SHIFT (11U) +#define PMU_BISR_STS0_PD_AV1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_AV1_DWN_PDGDONE_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS0_PD_VI_DWN_PDGDONE_SHIFT (12U) +#define PMU_BISR_STS0_PD_VI_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VI_DWN_PDGDONE_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS0_PD_FEC_DWN_PDGDONE_SHIFT (13U) +#define PMU_BISR_STS0_PD_FEC_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_FEC_DWN_PDGDONE_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS0_PD_ISP1_DWN_PDGDONE_SHIFT (14U) +#define PMU_BISR_STS0_PD_ISP1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_ISP1_DWN_PDGDONE_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS0_PD_RGA31_DWN_PDGDONE_SHIFT (15U) +#define PMU_BISR_STS0_PD_RGA31_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_RGA31_DWN_PDGDONE_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS0_PD_VOP_DWN_PDGDONE_SHIFT (16U) +#define PMU_BISR_STS0_PD_VOP_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VOP_DWN_PDGDONE_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS0_PD_VO0_DWN_PDGDONE_SHIFT (17U) +#define PMU_BISR_STS0_PD_VO0_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VO0_DWN_PDGDONE_SHIFT) /* 0x00020000 */ +#define PMU_BISR_STS0_PD_VO1_DWN_PDGDONE_SHIFT (18U) +#define PMU_BISR_STS0_PD_VO1_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_VO1_DWN_PDGDONE_SHIFT) /* 0x00040000 */ +#define PMU_BISR_STS0_PD_AUDIO_DWN_PDGDONE_SHIFT (19U) +#define PMU_BISR_STS0_PD_AUDIO_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_AUDIO_DWN_PDGDONE_SHIFT) /* 0x00080000 */ +#define PMU_BISR_STS0_PD_PHP_DWN_PDGDONE_SHIFT (20U) +#define PMU_BISR_STS0_PD_PHP_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_PHP_DWN_PDGDONE_SHIFT) /* 0x00100000 */ +#define PMU_BISR_STS0_PD_GMAC_DWN_PDGDONE_SHIFT (21U) +#define PMU_BISR_STS0_PD_GMAC_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_GMAC_DWN_PDGDONE_SHIFT) /* 0x00200000 */ +#define PMU_BISR_STS0_PD_PCIE_DWN_PDGDONE_SHIFT (22U) +#define PMU_BISR_STS0_PD_PCIE_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_PCIE_DWN_PDGDONE_SHIFT) /* 0x00400000 */ +#define PMU_BISR_STS0_PD_NVM0_DWN_PDGDONE_SHIFT (23U) +#define PMU_BISR_STS0_PD_NVM0_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_NVM0_DWN_PDGDONE_SHIFT) /* 0x00800000 */ +#define PMU_BISR_STS0_PD_SDIO_DWN_PDGDONE_SHIFT (24U) +#define PMU_BISR_STS0_PD_SDIO_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_SDIO_DWN_PDGDONE_SHIFT) /* 0x01000000 */ +#define PMU_BISR_STS0_PD_USB_DWN_PDGDONE_SHIFT (25U) +#define PMU_BISR_STS0_PD_USB_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_USB_DWN_PDGDONE_SHIFT) /* 0x02000000 */ +#define PMU_BISR_STS0_PD_SDMMC_DWN_PDGDONE_SHIFT (26U) +#define PMU_BISR_STS0_PD_SDMMC_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_SDMMC_DWN_PDGDONE_SHIFT) /* 0x04000000 */ +#define PMU_BISR_STS0_PD_CRYPTO_DWN_PDGDONE_SHIFT (27U) +#define PMU_BISR_STS0_PD_CRYPTO_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_CRYPTO_DWN_PDGDONE_SHIFT) /* 0x08000000 */ +#define PMU_BISR_STS0_PD_CENTER_DWN_PDGDONE_SHIFT (28U) +#define PMU_BISR_STS0_PD_CENTER_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_CENTER_DWN_PDGDONE_SHIFT) /* 0x10000000 */ +#define PMU_BISR_STS0_PD_DDR01_DWN_PDGDONE_SHIFT (29U) +#define PMU_BISR_STS0_PD_DDR01_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_DDR01_DWN_PDGDONE_SHIFT) /* 0x20000000 */ +#define PMU_BISR_STS0_PD_DDR23_DWN_PDGDONE_SHIFT (30U) +#define PMU_BISR_STS0_PD_DDR23_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_DDR23_DWN_PDGDONE_SHIFT) /* 0x40000000 */ +#define PMU_BISR_STS0_PD_BUS_DWN_PDGDONE_SHIFT (31U) +#define PMU_BISR_STS0_PD_BUS_DWN_PDGDONE_MASK (0x1U << PMU_BISR_STS0_PD_BUS_DWN_PDGDONE_SHIFT) /* 0x80000000 */ +/* BISR_STS1 */ +#define PMU_BISR_STS1_OFFSET (0x8284U) +#define PMU_BISR_STS1 (0x0U) +#define PMU_BISR_STS1_PD_DSU_REPAIR_PDGDONE_SHIFT (0U) +#define PMU_BISR_STS1_PD_DSU_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_DSU_REPAIR_PDGDONE_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS1_PD_CPU7_REPAIR_PDGDONE_SHIFT (1U) +#define PMU_BISR_STS1_PD_CPU7_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU7_REPAIR_PDGDONE_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS1_PD_CPU6_REPAIR_PDGDONE_SHIFT (2U) +#define PMU_BISR_STS1_PD_CPU6_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU6_REPAIR_PDGDONE_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS1_PD_CPU5_REPAIR_PDGDONE_SHIFT (3U) +#define PMU_BISR_STS1_PD_CPU5_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU5_REPAIR_PDGDONE_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS1_PD_CPU4_REPAIR_PDGDONE_SHIFT (4U) +#define PMU_BISR_STS1_PD_CPU4_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU4_REPAIR_PDGDONE_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS1_PD_CPU3_REPAIR_PDGDONE_SHIFT (5U) +#define PMU_BISR_STS1_PD_CPU3_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU3_REPAIR_PDGDONE_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS1_PD_CPU2_REPAIR_PDGDONE_SHIFT (6U) +#define PMU_BISR_STS1_PD_CPU2_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU2_REPAIR_PDGDONE_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS1_PD_CPU1_REPAIR_PDGDONE_SHIFT (7U) +#define PMU_BISR_STS1_PD_CPU1_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU1_REPAIR_PDGDONE_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS1_PD_CPU0_REPAIR_PDGDONE_SHIFT (8U) +#define PMU_BISR_STS1_PD_CPU0_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_CPU0_REPAIR_PDGDONE_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS1_PD_VOPCLUSTER0_REPAIR_PDGDONE_SHIFT (9U) +#define PMU_BISR_STS1_PD_VOPCLUSTER0_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPCLUSTER0_REPAIR_PDGDONE_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS1_PD_VOPCLUSTER1_REPAIR_PDGDONE_SHIFT (10U) +#define PMU_BISR_STS1_PD_VOPCLUSTER1_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPCLUSTER1_REPAIR_PDGDONE_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS1_PD_VOPCLUSTER2_REPAIR_PDGDONE_SHIFT (11U) +#define PMU_BISR_STS1_PD_VOPCLUSTER2_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPCLUSTER2_REPAIR_PDGDONE_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS1_PD_VOPCLUSTER3_REPAIR_PDGDONE_SHIFT (12U) +#define PMU_BISR_STS1_PD_VOPCLUSTER3_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPCLUSTER3_REPAIR_PDGDONE_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS1_PD_VOPDSC8K_REPAIR_PDGDONE_SHIFT (13U) +#define PMU_BISR_STS1_PD_VOPDSC8K_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPDSC8K_REPAIR_PDGDONE_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS1_PD_VOPDSC4K_REPAIR_PDGDONE_SHIFT (14U) +#define PMU_BISR_STS1_PD_VOPDSC4K_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPDSC4K_REPAIR_PDGDONE_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS1_PD_VOPESMART_REPAIR_PDGDONE_SHIFT (15U) +#define PMU_BISR_STS1_PD_VOPESMART_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PD_VOPESMART_REPAIR_PDGDONE_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS1_HDMIRXPHY_REPAIR_PDGDONE_SHIFT (16U) +#define PMU_BISR_STS1_HDMIRXPHY_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_HDMIRXPHY_REPAIR_PDGDONE_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS1_PCIEPHY_REPAIR_PDGDONE_SHIFT (17U) +#define PMU_BISR_STS1_PCIEPHY_REPAIR_PDGDONE_MASK (0x1U << PMU_BISR_STS1_PCIEPHY_REPAIR_PDGDONE_SHIFT) /* 0x00020000 */ +/* BISR_STS2 */ +#define PMU_BISR_STS2_OFFSET (0x8288U) +#define PMU_BISR_STS2 (0x0U) +#define PMU_BISR_STS2_PD_PMU1_REPAIR_CEDIS_SHIFT (0U) +#define PMU_BISR_STS2_PD_PMU1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_PMU1_REPAIR_CEDIS_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS2_PD_GPU_BISR_CEDIS_SHIFT (1U) +#define PMU_BISR_STS2_PD_GPU_BISR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_GPU_BISR_CEDIS_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS2_PD_NPUTOP_REPAIR_CEDIS_SHIFT (2U) +#define PMU_BISR_STS2_PD_NPUTOP_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_NPUTOP_REPAIR_CEDIS_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS2_PD_NPU1_REPAIR_CEDIS_SHIFT (3U) +#define PMU_BISR_STS2_PD_NPU1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_NPU1_REPAIR_CEDIS_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS2_PD_NPU2_REPAIR_CEDIS_SHIFT (4U) +#define PMU_BISR_STS2_PD_NPU2_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_NPU2_REPAIR_CEDIS_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS2_PD_VENC0_REPAIR_CEDIS_SHIFT (5U) +#define PMU_BISR_STS2_PD_VENC0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VENC0_REPAIR_CEDIS_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS2_PD_VENC1_REPAIR_CEDIS_SHIFT (6U) +#define PMU_BISR_STS2_PD_VENC1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VENC1_REPAIR_CEDIS_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS2_PD_RKVDEC0_REPAIR_CEDIS_SHIFT (7U) +#define PMU_BISR_STS2_PD_RKVDEC0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_RKVDEC0_REPAIR_CEDIS_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS2_PD_RKVDEC1_REPAIR_CEDIS_SHIFT (8U) +#define PMU_BISR_STS2_PD_RKVDEC1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_RKVDEC1_REPAIR_CEDIS_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS2_PD_VDPU_REPAIR_CEDIS_SHIFT (9U) +#define PMU_BISR_STS2_PD_VDPU_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VDPU_REPAIR_CEDIS_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS2_PD_RGA30_REPAIR_CEDIS_SHIFT (10U) +#define PMU_BISR_STS2_PD_RGA30_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_RGA30_REPAIR_CEDIS_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS2_PD_AV1_REPAIR_CEDIS_SHIFT (11U) +#define PMU_BISR_STS2_PD_AV1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_AV1_REPAIR_CEDIS_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS2_PD_VI_REPAIR_CEDIS_SHIFT (12U) +#define PMU_BISR_STS2_PD_VI_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VI_REPAIR_CEDIS_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS2_PD_FEC_REPAIR_CEDIS_SHIFT (13U) +#define PMU_BISR_STS2_PD_FEC_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_FEC_REPAIR_CEDIS_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS2_PD_ISP1_REPAIR_CEDIS_SHIFT (14U) +#define PMU_BISR_STS2_PD_ISP1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_ISP1_REPAIR_CEDIS_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS2_PD_RGA31_REPAIR_CEDIS_SHIFT (15U) +#define PMU_BISR_STS2_PD_RGA31_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_RGA31_REPAIR_CEDIS_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS2_PD_VOP_REPAIR_CEDIS_SHIFT (16U) +#define PMU_BISR_STS2_PD_VOP_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VOP_REPAIR_CEDIS_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS2_PD_VO0_REPAIR_CEDIS_SHIFT (17U) +#define PMU_BISR_STS2_PD_VO0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VO0_REPAIR_CEDIS_SHIFT) /* 0x00020000 */ +#define PMU_BISR_STS2_PD_VO1_REPAIR_CEDIS_SHIFT (18U) +#define PMU_BISR_STS2_PD_VO1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_VO1_REPAIR_CEDIS_SHIFT) /* 0x00040000 */ +#define PMU_BISR_STS2_PD_AUDIO_REPAIR_CEDIS_SHIFT (19U) +#define PMU_BISR_STS2_PD_AUDIO_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_AUDIO_REPAIR_CEDIS_SHIFT) /* 0x00080000 */ +#define PMU_BISR_STS2_PD_PHP_REPAIR_CEDIS_SHIFT (20U) +#define PMU_BISR_STS2_PD_PHP_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_PHP_REPAIR_CEDIS_SHIFT) /* 0x00100000 */ +#define PMU_BISR_STS2_PD_GMAC_REPAIR_CEDIS_SHIFT (21U) +#define PMU_BISR_STS2_PD_GMAC_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_GMAC_REPAIR_CEDIS_SHIFT) /* 0x00200000 */ +#define PMU_BISR_STS2_PD_PCIE_REPAIR_CEDIS_SHIFT (22U) +#define PMU_BISR_STS2_PD_PCIE_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_PCIE_REPAIR_CEDIS_SHIFT) /* 0x00400000 */ +#define PMU_BISR_STS2_PD_NVM0_REPAIR_CEDIS_SHIFT (23U) +#define PMU_BISR_STS2_PD_NVM0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_NVM0_REPAIR_CEDIS_SHIFT) /* 0x00800000 */ +#define PMU_BISR_STS2_PD_SDIO_REPAIR_CEDIS_SHIFT (24U) +#define PMU_BISR_STS2_PD_SDIO_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_SDIO_REPAIR_CEDIS_SHIFT) /* 0x01000000 */ +#define PMU_BISR_STS2_PD_USB_REPAIR_CEDIS_SHIFT (25U) +#define PMU_BISR_STS2_PD_USB_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_USB_REPAIR_CEDIS_SHIFT) /* 0x02000000 */ +#define PMU_BISR_STS2_PD_SDMMC_REPAIR_CEDIS_SHIFT (26U) +#define PMU_BISR_STS2_PD_SDMMC_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_SDMMC_REPAIR_CEDIS_SHIFT) /* 0x04000000 */ +#define PMU_BISR_STS2_PD_CRYPTO_REPAIR_CEDIS_SHIFT (27U) +#define PMU_BISR_STS2_PD_CRYPTO_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_CRYPTO_REPAIR_CEDIS_SHIFT) /* 0x08000000 */ +#define PMU_BISR_STS2_PD_CENTER_REPAIR_CEDIS_SHIFT (28U) +#define PMU_BISR_STS2_PD_CENTER_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_CENTER_REPAIR_CEDIS_SHIFT) /* 0x10000000 */ +#define PMU_BISR_STS2_PD_DDR01_REPAIR_CEDIS_SHIFT (29U) +#define PMU_BISR_STS2_PD_DDR01_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_DDR01_REPAIR_CEDIS_SHIFT) /* 0x20000000 */ +#define PMU_BISR_STS2_PD_DDR23_REPAIR_CEDIS_SHIFT (30U) +#define PMU_BISR_STS2_PD_DDR23_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_DDR23_REPAIR_CEDIS_SHIFT) /* 0x40000000 */ +#define PMU_BISR_STS2_PD_BUS_REPAIR_CEDIS_SHIFT (31U) +#define PMU_BISR_STS2_PD_BUS_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS2_PD_BUS_REPAIR_CEDIS_SHIFT) /* 0x80000000 */ +/* BISR_STS3 */ +#define PMU_BISR_STS3_OFFSET (0x828CU) +#define PMU_BISR_STS3 (0x0U) +#define PMU_BISR_STS3_PD_DSU_REPAIR_CEDIS_SHIFT (0U) +#define PMU_BISR_STS3_PD_DSU_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_DSU_REPAIR_CEDIS_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS3_PD_CPU7_REPAIR_CEDIS_SHIFT (1U) +#define PMU_BISR_STS3_PD_CPU7_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU7_REPAIR_CEDIS_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS3_PD_CPU6_REPAIR_CEDIS_SHIFT (2U) +#define PMU_BISR_STS3_PD_CPU6_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU6_REPAIR_CEDIS_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS3_PD_CPU5_REPAIR_CEDIS_SHIFT (3U) +#define PMU_BISR_STS3_PD_CPU5_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU5_REPAIR_CEDIS_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS3_PD_CPU4_REPAIR_CEDIS_SHIFT (4U) +#define PMU_BISR_STS3_PD_CPU4_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU4_REPAIR_CEDIS_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS3_PD_CPU3_REPAIR_CEDIS_SHIFT (5U) +#define PMU_BISR_STS3_PD_CPU3_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU3_REPAIR_CEDIS_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS3_PD_CPU2_REPAIR_CEDIS_SHIFT (6U) +#define PMU_BISR_STS3_PD_CPU2_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU2_REPAIR_CEDIS_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS3_PD_CPU1_REPAIR_CEDIS_SHIFT (7U) +#define PMU_BISR_STS3_PD_CPU1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU1_REPAIR_CEDIS_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS3_PD_CPU0_REPAIR_CEDIS_SHIFT (8U) +#define PMU_BISR_STS3_PD_CPU0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_CPU0_REPAIR_CEDIS_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS3_PD_VOPCLUSTER0_REPAIR_CEDIS_SHIFT (9U) +#define PMU_BISR_STS3_PD_VOPCLUSTER0_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPCLUSTER0_REPAIR_CEDIS_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS3_PD_VOPCLUSTER1_REPAIR_CEDIS_SHIFT (10U) +#define PMU_BISR_STS3_PD_VOPCLUSTER1_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPCLUSTER1_REPAIR_CEDIS_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS3_PD_VOPCLUSTER2_REPAIR_CEDIS_SHIFT (11U) +#define PMU_BISR_STS3_PD_VOPCLUSTER2_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPCLUSTER2_REPAIR_CEDIS_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS3_PD_VOPCLUSTER3_REPAIR_CEDIS_SHIFT (12U) +#define PMU_BISR_STS3_PD_VOPCLUSTER3_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPCLUSTER3_REPAIR_CEDIS_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS3_PD_VOPDSC8K_REPAIR_CEDIS_SHIFT (13U) +#define PMU_BISR_STS3_PD_VOPDSC8K_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPDSC8K_REPAIR_CEDIS_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS3_PD_VOPDSC4K_REPAIR_CEDIS_SHIFT (14U) +#define PMU_BISR_STS3_PD_VOPDSC4K_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPDSC4K_REPAIR_CEDIS_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS3_PD_VOPESMART_REPAIR_CEDIS_SHIFT (15U) +#define PMU_BISR_STS3_PD_VOPESMART_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PD_VOPESMART_REPAIR_CEDIS_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS3_HDMIRXPHY_REPAIR_CEDIS_SHIFT (16U) +#define PMU_BISR_STS3_HDMIRXPHY_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_HDMIRXPHY_REPAIR_CEDIS_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS3_PCIEPHY_REPAIR_CEDIS_SHIFT (17U) +#define PMU_BISR_STS3_PCIEPHY_REPAIR_CEDIS_MASK (0x1U << PMU_BISR_STS3_PCIEPHY_REPAIR_CEDIS_SHIFT) /* 0x00020000 */ +/* BISR_STS4 */ +#define PMU_BISR_STS4_OFFSET (0x8290U) +#define PMU_BISR_STS4 (0x0U) +#define PMU_BISR_STS4_PD_PMU1_PWR_REPAIR_STAT_SHIFT (0U) +#define PMU_BISR_STS4_PD_PMU1_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_PMU1_PWR_REPAIR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS4_PD_GPU_BISR_PWR_REPAIR_STAT_SHIFT (1U) +#define PMU_BISR_STS4_PD_GPU_BISR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_GPU_BISR_PWR_REPAIR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS4_PD_NPUTOP_DWN_PWR_REPAIR_STAT_SHIFT (2U) +#define PMU_BISR_STS4_PD_NPUTOP_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_NPUTOP_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS4_PD_NPU1_DWN_PWR_REPAIR_STAT_SHIFT (3U) +#define PMU_BISR_STS4_PD_NPU1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_NPU1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS4_PD_NPU2_DWN_PWR_REPAIR_STAT_SHIFT (4U) +#define PMU_BISR_STS4_PD_NPU2_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_NPU2_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS4_PD_VENC0_DWN_PWR_REPAIR_STAT_SHIFT (5U) +#define PMU_BISR_STS4_PD_VENC0_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VENC0_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS4_PD_VENC1_DWN_PWR_REPAIR_STAT_SHIFT (6U) +#define PMU_BISR_STS4_PD_VENC1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VENC1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS4_PD_RKVDEC0_DWN_PWR_REPAIR_STAT_SHIFT (7U) +#define PMU_BISR_STS4_PD_RKVDEC0_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_RKVDEC0_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS4_PD_RKVDEC1_DWN_PWR_REPAIR_STAT_SHIFT (8U) +#define PMU_BISR_STS4_PD_RKVDEC1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_RKVDEC1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS4_PD_VDPU_DWN_PWR_REPAIR_STAT_SHIFT (9U) +#define PMU_BISR_STS4_PD_VDPU_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VDPU_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS4_PD_RGA30_DWN_PWR_REPAIR_STAT_SHIFT (10U) +#define PMU_BISR_STS4_PD_RGA30_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_RGA30_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS4_PD_AV1_DWN_PWR_REPAIR_STAT_SHIFT (11U) +#define PMU_BISR_STS4_PD_AV1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_AV1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS4_PD_VI_DWN_PWR_REPAIR_STAT_SHIFT (12U) +#define PMU_BISR_STS4_PD_VI_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VI_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS4_PD_FEC_DWN_PWR_REPAIR_STAT_SHIFT (13U) +#define PMU_BISR_STS4_PD_FEC_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_FEC_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS4_PD_ISP1_DWN_PWR_REPAIR_STAT_SHIFT (14U) +#define PMU_BISR_STS4_PD_ISP1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_ISP1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS4_PD_RGA31_DWN_PWR_REPAIR_STAT_SHIFT (15U) +#define PMU_BISR_STS4_PD_RGA31_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_RGA31_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS4_PD_VOP_DWN_PWR_REPAIR_STAT_SHIFT (16U) +#define PMU_BISR_STS4_PD_VOP_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VOP_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS4_PD_VO0_DWN_PWR_REPAIR_STAT_SHIFT (17U) +#define PMU_BISR_STS4_PD_VO0_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VO0_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00020000 */ +#define PMU_BISR_STS4_PD_VO1_DWN_PWR_REPAIR_STAT_SHIFT (18U) +#define PMU_BISR_STS4_PD_VO1_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_VO1_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00040000 */ +#define PMU_BISR_STS4_PD_AUDIO_DWN_PWR_REPAIR_STAT_SHIFT (19U) +#define PMU_BISR_STS4_PD_AUDIO_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_AUDIO_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00080000 */ +#define PMU_BISR_STS4_PD_PHP_DWN_PWR_REPAIR_STAT_SHIFT (20U) +#define PMU_BISR_STS4_PD_PHP_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_PHP_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00100000 */ +#define PMU_BISR_STS4_PD_GMAC_DWN_PWR_REPAIR_STAT_SHIFT (21U) +#define PMU_BISR_STS4_PD_GMAC_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_GMAC_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00200000 */ +#define PMU_BISR_STS4_PD_PCIE_DWN_PWR_REPAIR_STAT_SHIFT (22U) +#define PMU_BISR_STS4_PD_PCIE_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_PCIE_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00400000 */ +#define PMU_BISR_STS4_PD_NVM0_DWN_PWR_REPAIR_STAT_SHIFT (23U) +#define PMU_BISR_STS4_PD_NVM0_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_NVM0_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x00800000 */ +#define PMU_BISR_STS4_PD_SDIO_DWN_PWR_REPAIR_STAT_SHIFT (24U) +#define PMU_BISR_STS4_PD_SDIO_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_SDIO_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x01000000 */ +#define PMU_BISR_STS4_PD_USB_DWN_PWR_REPAIR_STAT_SHIFT (25U) +#define PMU_BISR_STS4_PD_USB_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_USB_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x02000000 */ +#define PMU_BISR_STS4_PD_SDMMC_DWN_PWR_REPAIR_STAT_SHIFT (26U) +#define PMU_BISR_STS4_PD_SDMMC_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_SDMMC_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x04000000 */ +#define PMU_BISR_STS4_PD_CRYPTO_DWN_PWR_REPAIR_STAT_SHIFT (27U) +#define PMU_BISR_STS4_PD_CRYPTO_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_CRYPTO_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x08000000 */ +#define PMU_BISR_STS4_PD_CENTER_DWN_PWR_REPAIR_STAT_SHIFT (28U) +#define PMU_BISR_STS4_PD_CENTER_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_CENTER_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x10000000 */ +#define PMU_BISR_STS4_PD_DDR01_DWN_PWR_REPAIR_STAT_SHIFT (29U) +#define PMU_BISR_STS4_PD_DDR01_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_DDR01_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x20000000 */ +#define PMU_BISR_STS4_PD_DDR23_DWN_PWR_REPAIR_STAT_SHIFT (30U) +#define PMU_BISR_STS4_PD_DDR23_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_DDR23_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x40000000 */ +#define PMU_BISR_STS4_PD_BUS_DWN_PWR_REPAIR_STAT_SHIFT (31U) +#define PMU_BISR_STS4_PD_BUS_DWN_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS4_PD_BUS_DWN_PWR_REPAIR_STAT_SHIFT) /* 0x80000000 */ +/* BISR_STS5 */ +#define PMU_BISR_STS5_OFFSET (0x8294U) +#define PMU_BISR_STS5 (0x0U) +#define PMU_BISR_STS5_PD_DSU_REPAIR_PWR_REPAIR_STAT_SHIFT (0U) +#define PMU_BISR_STS5_PD_DSU_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_DSU_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000001 */ +#define PMU_BISR_STS5_PD_CPU7_REPAIR_PWR_REPAIR_STAT_SHIFT (1U) +#define PMU_BISR_STS5_PD_CPU7_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU7_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000002 */ +#define PMU_BISR_STS5_PD_CPU6_REPAIR_PWR_REPAIR_STAT_SHIFT (2U) +#define PMU_BISR_STS5_PD_CPU6_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU6_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000004 */ +#define PMU_BISR_STS5_PD_CPU5_REPAIR_PWR_REPAIR_STAT_SHIFT (3U) +#define PMU_BISR_STS5_PD_CPU5_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU5_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000008 */ +#define PMU_BISR_STS5_PD_CPU4_REPAIR_PWR_REPAIR_STAT_SHIFT (4U) +#define PMU_BISR_STS5_PD_CPU4_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU4_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000010 */ +#define PMU_BISR_STS5_PD_CPU3_REPAIR_PWR_REPAIR_STAT_SHIFT (5U) +#define PMU_BISR_STS5_PD_CPU3_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU3_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000020 */ +#define PMU_BISR_STS5_PD_CPU2_REPAIR_PWR_REPAIR_STAT_SHIFT (6U) +#define PMU_BISR_STS5_PD_CPU2_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU2_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000040 */ +#define PMU_BISR_STS5_PD_CPU1_REPAIR_PWR_REPAIR_STAT_SHIFT (7U) +#define PMU_BISR_STS5_PD_CPU1_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU1_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000080 */ +#define PMU_BISR_STS5_PD_CPU0_REPAIR_PWR_REPAIR_STAT_SHIFT (8U) +#define PMU_BISR_STS5_PD_CPU0_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_CPU0_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000100 */ +#define PMU_BISR_STS5_PD_VOPCLUSTER0_REPAIR_PWR_REPAIR_STAT_SHIFT (9U) +#define PMU_BISR_STS5_PD_VOPCLUSTER0_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPCLUSTER0_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000200 */ +#define PMU_BISR_STS5_PD_VOPCLUSTER1_REPAIR_PWR_REPAIR_STAT_SHIFT (10U) +#define PMU_BISR_STS5_PD_VOPCLUSTER1_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPCLUSTER1_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000400 */ +#define PMU_BISR_STS5_PD_VOPCLUSTER2_REPAIR_PWR_REPAIR_STAT_SHIFT (11U) +#define PMU_BISR_STS5_PD_VOPCLUSTER2_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPCLUSTER2_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00000800 */ +#define PMU_BISR_STS5_PD_VOPCLUSTER3_REPAIR_PWR_REPAIR_STAT_SHIFT (12U) +#define PMU_BISR_STS5_PD_VOPCLUSTER3_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPCLUSTER3_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00001000 */ +#define PMU_BISR_STS5_PD_VOPDSC8K_REPAIR_PWR_REPAIR_STAT_SHIFT (13U) +#define PMU_BISR_STS5_PD_VOPDSC8K_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPDSC8K_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00002000 */ +#define PMU_BISR_STS5_PD_VOPDSC4K_REPAIR_PWR_REPAIR_STAT_SHIFT (14U) +#define PMU_BISR_STS5_PD_VOPDSC4K_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPDSC4K_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00004000 */ +#define PMU_BISR_STS5_PD_VOPESMART_REPAIR_PWR_REPAIR_STAT_SHIFT (15U) +#define PMU_BISR_STS5_PD_VOPESMART_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PD_VOPESMART_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00008000 */ +#define PMU_BISR_STS5_HDMIRXPHY_REPAIR_PWR_REPAIR_STAT_SHIFT (16U) +#define PMU_BISR_STS5_HDMIRXPHY_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_HDMIRXPHY_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00010000 */ +#define PMU_BISR_STS5_PCIEPHY_REPAIR_PWR_REPAIR_STAT_SHIFT (17U) +#define PMU_BISR_STS5_PCIEPHY_REPAIR_PWR_REPAIR_STAT_MASK (0x1U << PMU_BISR_STS5_PCIEPHY_REPAIR_PWR_REPAIR_STAT_SHIFT) /* 0x00020000 */ +/******************************************CAN*******************************************/ +/* MODE */ +#define CAN_MODE_OFFSET (0x0U) +#define CAN_MODE_WORK_MODE_SHIFT (0U) +#define CAN_MODE_WORK_MODE_MASK (0x1U << CAN_MODE_WORK_MODE_SHIFT) /* 0x00000001 */ +#define CAN_MODE_SLEEP_MODE_SHIFT (1U) +#define CAN_MODE_SLEEP_MODE_MASK (0x1U << CAN_MODE_SLEEP_MODE_SHIFT) /* 0x00000002 */ +#define CAN_MODE_SELF_TEST_SHIFT (2U) +#define CAN_MODE_SELF_TEST_MASK (0x1U << CAN_MODE_SELF_TEST_SHIFT) /* 0x00000004 */ +#define CAN_MODE_SILENT_MODE_SHIFT (3U) +#define CAN_MODE_SILENT_MODE_MASK (0x1U << CAN_MODE_SILENT_MODE_SHIFT) /* 0x00000008 */ +#define CAN_MODE_LBACK_MODE_SHIFT (4U) +#define CAN_MODE_LBACK_MODE_MASK (0x1U << CAN_MODE_LBACK_MODE_SHIFT) /* 0x00000010 */ +#define CAN_MODE_RXSTX_MODE_SHIFT (5U) +#define CAN_MODE_RXSTX_MODE_MASK (0x1U << CAN_MODE_RXSTX_MODE_SHIFT) /* 0x00000020 */ +#define CAN_MODE_TXORDER_MODE_SHIFT (6U) +#define CAN_MODE_TXORDER_MODE_MASK (0x1U << CAN_MODE_TXORDER_MODE_SHIFT) /* 0x00000040 */ +#define CAN_MODE_RXSORT_MODE_SHIFT (7U) +#define CAN_MODE_RXSORT_MODE_MASK (0x1U << CAN_MODE_RXSORT_MODE_SHIFT) /* 0x00000080 */ +#define CAN_MODE_COVER_MODE_SHIFT (8U) +#define CAN_MODE_COVER_MODE_MASK (0x1U << CAN_MODE_COVER_MODE_SHIFT) /* 0x00000100 */ +#define CAN_MODE_OVLD_MODE_SHIFT (9U) +#define CAN_MODE_OVLD_MODE_MASK (0x1U << CAN_MODE_OVLD_MODE_SHIFT) /* 0x00000200 */ +#define CAN_MODE_AUTO_RETX_MODE_SHIFT (10U) +#define CAN_MODE_AUTO_RETX_MODE_MASK (0x1U << CAN_MODE_AUTO_RETX_MODE_SHIFT) /* 0x00000400 */ +#define CAN_MODE_AUTO_BUS_ON_SHIFT (11U) +#define CAN_MODE_AUTO_BUS_ON_MASK (0x1U << CAN_MODE_AUTO_BUS_ON_SHIFT) /* 0x00000800 */ +#define CAN_MODE_SPACE_RX_MODE_SHIFT (12U) +#define CAN_MODE_SPACE_RX_MODE_MASK (0x1U << CAN_MODE_SPACE_RX_MODE_SHIFT) /* 0x00001000 */ +#define CAN_MODE_BRSD_SHIFT (13U) +#define CAN_MODE_BRSD_MASK (0x1U << CAN_MODE_BRSD_SHIFT) /* 0x00002000 */ +#define CAN_MODE_DPEE_SHIFT (14U) +#define CAN_MODE_DPEE_MASK (0x1U << CAN_MODE_DPEE_SHIFT) /* 0x00004000 */ +#define CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT (15U) +#define CAN_MODE_CAN_FD_MODE_ENABLE_MASK (0x1U << CAN_MODE_CAN_FD_MODE_ENABLE_SHIFT) /* 0x00008000 */ +/* CMD */ +#define CAN_CMD_OFFSET (0x4U) +#define CAN_CMD_TX0_REQ_SHIFT (0U) +#define CAN_CMD_TX0_REQ_MASK (0x1U << CAN_CMD_TX0_REQ_SHIFT) /* 0x00000001 */ +#define CAN_CMD_TX1_REQ_SHIFT (1U) +#define CAN_CMD_TX1_REQ_MASK (0x1U << CAN_CMD_TX1_REQ_SHIFT) /* 0x00000002 */ +/* STATE */ +#define CAN_STATE_OFFSET (0x8U) +#define CAN_STATE (0x0U) +#define CAN_STATE_RX_BUFFER_FULL_SHIFT (0U) +#define CAN_STATE_RX_BUFFER_FULL_MASK (0x1U << CAN_STATE_RX_BUFFER_FULL_SHIFT) /* 0x00000001 */ +#define CAN_STATE_TX_BUFFER_FULL_SHIFT (1U) +#define CAN_STATE_TX_BUFFER_FULL_MASK (0x1U << CAN_STATE_TX_BUFFER_FULL_SHIFT) /* 0x00000002 */ +#define CAN_STATE_RX_PERIOD_SHIFT (2U) +#define CAN_STATE_RX_PERIOD_MASK (0x1U << CAN_STATE_RX_PERIOD_SHIFT) /* 0x00000004 */ +#define CAN_STATE_TX_PERIOD_SHIFT (3U) +#define CAN_STATE_TX_PERIOD_MASK (0x1U << CAN_STATE_TX_PERIOD_SHIFT) /* 0x00000008 */ +#define CAN_STATE_ERROR_WARNING_STATE_SHIFT (4U) +#define CAN_STATE_ERROR_WARNING_STATE_MASK (0x1U << CAN_STATE_ERROR_WARNING_STATE_SHIFT) /* 0x00000010 */ +#define CAN_STATE_BUS_OFF_STATE_SHIFT (5U) +#define CAN_STATE_BUS_OFF_STATE_MASK (0x1U << CAN_STATE_BUS_OFF_STATE_SHIFT) /* 0x00000020 */ +#define CAN_STATE_SLEEP_STATE_SHIFT (6U) +#define CAN_STATE_SLEEP_STATE_MASK (0x1U << CAN_STATE_SLEEP_STATE_SHIFT) /* 0x00000040 */ +/* INT */ +#define CAN_INT_OFFSET (0xCU) +#define CAN_INT_RX_FINISH_INT_SHIFT (0U) +#define CAN_INT_RX_FINISH_INT_MASK (0x1U << CAN_INT_RX_FINISH_INT_SHIFT) /* 0x00000001 */ +#define CAN_INT_TX_FINISH_INT_SHIFT (1U) +#define CAN_INT_TX_FINISH_INT_MASK (0x1U << CAN_INT_TX_FINISH_INT_SHIFT) /* 0x00000002 */ +#define CAN_INT_ERROR_WARNING_INT_SHIFT (2U) +#define CAN_INT_ERROR_WARNING_INT_MASK (0x1U << CAN_INT_ERROR_WARNING_INT_SHIFT) /* 0x00000004 */ +#define CAN_INT_OVERLOAD_INT_SHIFT (3U) +#define CAN_INT_OVERLOAD_INT_MASK (0x1U << CAN_INT_OVERLOAD_INT_SHIFT) /* 0x00000008 */ +#define CAN_INT_PASSIVE_ERROR_INT_SHIFT (4U) +#define CAN_INT_PASSIVE_ERROR_INT_MASK (0x1U << CAN_INT_PASSIVE_ERROR_INT_SHIFT) /* 0x00000010 */ +#define CAN_INT_TX_ARBIT_FAIL_INT_SHIFT (5U) +#define CAN_INT_TX_ARBIT_FAIL_INT_MASK (0x1U << CAN_INT_TX_ARBIT_FAIL_INT_SHIFT) /* 0x00000020 */ +#define CAN_INT_ERROR_INT_SHIFT (6U) +#define CAN_INT_ERROR_INT_MASK (0x1U << CAN_INT_ERROR_INT_SHIFT) /* 0x00000040 */ +#define CAN_INT_RX_FIFO_FULL_INT_SHIFT (7U) +#define CAN_INT_RX_FIFO_FULL_INT_MASK (0x1U << CAN_INT_RX_FIFO_FULL_INT_SHIFT) /* 0x00000080 */ +#define CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT (8U) +#define CAN_INT_RX_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_RX_FIFO_OVERFLOW_INT_SHIFT) /* 0x00000100 */ +#define CAN_INT_BUS_OFF_INT_SHIFT (9U) +#define CAN_INT_BUS_OFF_INT_MASK (0x1U << CAN_INT_BUS_OFF_INT_SHIFT) /* 0x00000200 */ +#define CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT (10U) +#define CAN_INT_BUS_OFF_RECOVERY_INT_MASK (0x1U << CAN_INT_BUS_OFF_RECOVERY_INT_SHIFT) /* 0x00000400 */ +#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT (11U) +#define CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK (0x1U << CAN_INT_TIMESTAMP_COUNTER_OVERFLOW_INT_SHIFT) /* 0x00000800 */ +#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT (12U) +#define CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_OVERFLOW_INT_SHIFT) /* 0x00001000 */ +#define CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT (13U) +#define CAN_INT_TX_EVENT_FIFO_FULL_INT_MASK (0x1U << CAN_INT_TX_EVENT_FIFO_FULL_INT_SHIFT) /* 0x00002000 */ +#define CAN_INT_WAKEUP_INT_SHIFT (14U) +#define CAN_INT_WAKEUP_INT_MASK (0x1U << CAN_INT_WAKEUP_INT_SHIFT) /* 0x00004000 */ +/* INT_MASK */ +#define CAN_INT_MASK_OFFSET (0x10U) +#define CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT (0U) +#define CAN_INT_MASK_RX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FINISH_INT_MASK_SHIFT) /* 0x00000001 */ +#define CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT (1U) +#define CAN_INT_MASK_TX_FINISH_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_FINISH_INT_MASK_SHIFT) /* 0x00000002 */ +#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT (2U) +#define CAN_INT_MASK_ERROR_WARNING_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_WARNING_INT_MASK_SHIFT) /* 0x00000004 */ +#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT (3U) +#define CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_BUFFER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000008 */ +#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT (4U) +#define CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_PASSIVE_ERROR_INT_MASK_SHIFT) /* 0x00000010 */ +#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT (5U) +#define CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_ARBIT_FAIL_INT_MASK_SHIFT) /* 0x00000020 */ +#define CAN_INT_MASK_ERROR_INT_MASK_SHIFT (6U) +#define CAN_INT_MASK_ERROR_INT_MASK_MASK (0x1U << CAN_INT_MASK_ERROR_INT_MASK_SHIFT) /* 0x00000040 */ +#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT (7U) +#define CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_FULL_INT_MASK_SHIFT) /* 0x00000080 */ +#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT (8U) +#define CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_RX_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00000100 */ +#define CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT (9U) +#define CAN_INT_MASK_BUS_OFF_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_INT_MASK_SHIFT) /* 0x00000200 */ +#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT (10U) +#define CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_MASK (0x1U << CAN_INT_MASK_BUS_OFF_RECOVERY_INT_MASK_SHIFT) /* 0x00000400 */ +#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT (11U) +#define CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TIMESTAMP_COUNTER_OVERFLOW_INT_MASK_SHIFT) /* 0x00000800 */ +#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT (12U) +#define CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_OVERFLOW_INT_MASK_SHIFT) /* 0x00001000 */ +#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT (13U) +#define CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_MASK (0x1U << CAN_INT_MASK_TX_EVENT_FIFO_FULL_INT_MASK_SHIFT) /* 0x00002000 */ +#define CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT (14U) +#define CAN_INT_MASK_WAKEUP_INT_MASK_MASK (0x1U << CAN_INT_MASK_WAKEUP_INT_MASK_SHIFT) /* 0x00004000 */ +/* DMA_CTRL */ +#define CAN_DMA_CTRL_OFFSET (0x14U) +#define CAN_DMA_CTRL_DMA_TX_MODE_SHIFT (0U) +#define CAN_DMA_CTRL_DMA_TX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_TX_MODE_SHIFT) /* 0x00000001 */ +#define CAN_DMA_CTRL_DMA_RX_MODE_SHIFT (1U) +#define CAN_DMA_CTRL_DMA_RX_MODE_MASK (0x1U << CAN_DMA_CTRL_DMA_RX_MODE_SHIFT) /* 0x00000002 */ +/* BITTIMING */ +#define CAN_BITTIMING_OFFSET (0x18U) +#define CAN_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_BITTIMING_TSEG1_MASK (0xFU << CAN_BITTIMING_TSEG1_SHIFT) /* 0x0000000F */ +#define CAN_BITTIMING_TSEG2_SHIFT (4U) +#define CAN_BITTIMING_TSEG2_MASK (0x7U << CAN_BITTIMING_TSEG2_SHIFT) /* 0x00000070 */ +#define CAN_BITTIMING_BRP_SHIFT (8U) +#define CAN_BITTIMING_BRP_MASK (0x3FU << CAN_BITTIMING_BRP_SHIFT) /* 0x00003F00 */ +#define CAN_BITTIMING_SJW_SHIFT (14U) +#define CAN_BITTIMING_SJW_MASK (0x3U << CAN_BITTIMING_SJW_SHIFT) /* 0x0000C000 */ +#define CAN_BITTIMING_SAMPLE_MODE_SHIFT (16U) +#define CAN_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00010000 */ +/* ARBITFAIL */ +#define CAN_ARBITFAIL_OFFSET (0x28U) +#define CAN_ARBITFAIL (0x0U) +#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT (0U) +#define CAN_ARBITFAIL_ARBIT_FAIL_CODE_MASK (0x7FU << CAN_ARBITFAIL_ARBIT_FAIL_CODE_SHIFT) /* 0x0000007F */ +/* ERROR_CODE */ +#define CAN_ERROR_CODE_OFFSET (0x2CU) +#define CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT (0U) +#define CAN_ERROR_CODE_RX_ERROR_POSITION_MASK (0xFFFFU << CAN_ERROR_CODE_RX_ERROR_POSITION_SHIFT) /* 0x0000FFFF */ +#define CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT (16U) +#define CAN_ERROR_CODE_TX_ERROR_POSITION_MASK (0x1FFU << CAN_ERROR_CODE_TX_ERROR_POSITION_SHIFT) /* 0x01FF0000 */ +#define CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT (25U) +#define CAN_ERROR_CODE_ERROR_DIRECTION_MASK (0x1U << CAN_ERROR_CODE_ERROR_DIRECTION_SHIFT) /* 0x02000000 */ +#define CAN_ERROR_CODE_ERROR_TYPE_SHIFT (26U) +#define CAN_ERROR_CODE_ERROR_TYPE_MASK (0x7U << CAN_ERROR_CODE_ERROR_TYPE_SHIFT) /* 0x1C000000 */ +#define CAN_ERROR_CODE_ERROR_PHASE_SHIFT (29U) +#define CAN_ERROR_CODE_ERROR_PHASE_MASK (0x1U << CAN_ERROR_CODE_ERROR_PHASE_SHIFT) /* 0x20000000 */ +/* RXERRORCNT */ +#define CAN_RXERRORCNT_OFFSET (0x34U) +#define CAN_RXERRORCNT (0x0U) +#define CAN_RXERRORCNT_RX_ERR_CNT_SHIFT (0U) +#define CAN_RXERRORCNT_RX_ERR_CNT_MASK (0xFFU << CAN_RXERRORCNT_RX_ERR_CNT_SHIFT) /* 0x000000FF */ +/* TXERRORCNT */ +#define CAN_TXERRORCNT_OFFSET (0x38U) +#define CAN_TXERRORCNT (0x0U) +#define CAN_TXERRORCNT_TX_ERR_CNT_SHIFT (0U) +#define CAN_TXERRORCNT_TX_ERR_CNT_MASK (0x1FFU << CAN_TXERRORCNT_TX_ERR_CNT_SHIFT) /* 0x000001FF */ +/* IDCODE */ +#define CAN_IDCODE_OFFSET (0x3CU) +#define CAN_IDCODE_ID_CODE_SHIFT (0U) +#define CAN_IDCODE_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK */ +#define CAN_IDMASK_OFFSET (0x40U) +#define CAN_IDMASK_ID_MASK_SHIFT (0U) +#define CAN_IDMASK_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* TXFRAMEINFO */ +#define CAN_TXFRAMEINFO_OFFSET (0x50U) +#define CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U) +#define CAN_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_TXFRAMEINFO_TX_RTR_SHIFT (6U) +#define CAN_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U) +#define CAN_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* TXID */ +#define CAN_TXID_OFFSET (0x54U) +#define CAN_TXID_TX_ID_SHIFT (0U) +#define CAN_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */ +/* TXDATA0 */ +#define CAN_TXDATA0_OFFSET (0x58U) +#define CAN_TXDATA0_TX_DATA0_SHIFT (0U) +#define CAN_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* TXDATA1 */ +#define CAN_TXDATA1_OFFSET (0x5CU) +#define CAN_TXDATA1_TX_DATA1_SHIFT (0U) +#define CAN_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* RXFRAMEINFO */ +#define CAN_RXFRAMEINFO_OFFSET (0x60U) +#define CAN_RXFRAMEINFO (0x0U) +#define CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U) +#define CAN_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_RXFRAMEINFO_RX_RTR_SHIFT (6U) +#define CAN_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U) +#define CAN_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* RXID */ +#define CAN_RXID_OFFSET (0x64U) +#define CAN_RXID (0x0U) +#define CAN_RXID_RX_ID_SHIFT (0U) +#define CAN_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */ +/* RXDATA0 */ +#define CAN_RXDATA0_OFFSET (0x68U) +#define CAN_RXDATA0 (0x0U) +#define CAN_RXDATA0_RX_DATA0_SHIFT (0U) +#define CAN_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* RXDATA1 */ +#define CAN_RXDATA1_OFFSET (0x6CU) +#define CAN_RXDATA1 (0x0U) +#define CAN_RXDATA1_RX_DATA1_SHIFT (0U) +#define CAN_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* RTL_VERSION */ +#define CAN_RTL_VERSION_OFFSET (0x70U) +#define CAN_RTL_VERSION (0x21U) +#define CAN_RTL_VERSION_VERSION_SHIFT (0U) +#define CAN_RTL_VERSION_VERSION_MASK (0xFFFFFFFFU << CAN_RTL_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* FD_NOMINAL_BITTIMING */ +#define CAN_FD_NOMINAL_BITTIMING_OFFSET (0x100U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG1_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_TSEG1_SHIFT) /* 0x000000FF */ +#define CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT (8U) +#define CAN_FD_NOMINAL_BITTIMING_TSEG2_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_TSEG2_SHIFT) /* 0x00007F00 */ +#define CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT (16U) +#define CAN_FD_NOMINAL_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_NOMINAL_BITTIMING_BRQ_SHIFT) /* 0x00FF0000 */ +#define CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT (24U) +#define CAN_FD_NOMINAL_BITTIMING_SJW_MASK (0x7FU << CAN_FD_NOMINAL_BITTIMING_SJW_SHIFT) /* 0x7F000000 */ +#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT (31U) +#define CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_NOMINAL_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x80000000 */ +/* FD_DATA_BITTIMING */ +#define CAN_FD_DATA_BITTIMING_OFFSET (0x104U) +#define CAN_FD_DATA_BITTIMING_TSEG1_SHIFT (0U) +#define CAN_FD_DATA_BITTIMING_TSEG1_MASK (0x1FU << CAN_FD_DATA_BITTIMING_TSEG1_SHIFT) /* 0x0000001F */ +#define CAN_FD_DATA_BITTIMING_TSEG2_SHIFT (5U) +#define CAN_FD_DATA_BITTIMING_TSEG2_MASK (0xFU << CAN_FD_DATA_BITTIMING_TSEG2_SHIFT) /* 0x000001E0 */ +#define CAN_FD_DATA_BITTIMING_BRQ_SHIFT (9U) +#define CAN_FD_DATA_BITTIMING_BRQ_MASK (0xFFU << CAN_FD_DATA_BITTIMING_BRQ_SHIFT) /* 0x0001FE00 */ +#define CAN_FD_DATA_BITTIMING_SJW_SHIFT (17U) +#define CAN_FD_DATA_BITTIMING_SJW_MASK (0xFU << CAN_FD_DATA_BITTIMING_SJW_SHIFT) /* 0x001E0000 */ +#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT (21U) +#define CAN_FD_DATA_BITTIMING_SAMPLE_MODE_MASK (0x1U << CAN_FD_DATA_BITTIMING_SAMPLE_MODE_SHIFT) /* 0x00200000 */ +/* TRANSMIT_DELAY_COMPENSATION */ +#define CAN_TRANSMIT_DELAY_COMPENSATION_OFFSET (0x108U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT (0U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_MASK (0x1U << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT (1U) +#define CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_MASK (0x3FU << CAN_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET_SHIFT) /* 0x0000007E */ +/* TIMESTAMP_CTRL */ +#define CAN_TIMESTAMP_CTRL_OFFSET (0x10CU) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT (0U) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_MASK (0x1U << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT (1U) +#define CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_MASK (0x3FU << CAN_TIMESTAMP_CTRL_TIME_BASE_COUNTER_PRESCALE_SHIFT) /* 0x0000007E */ +/* TIMESTAMP */ +#define CAN_TIMESTAMP_OFFSET (0x110U) +#define CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT (0U) +#define CAN_TIMESTAMP_TIME_BASE_COUNTER_MASK (0xFFFFFFFFU << CAN_TIMESTAMP_TIME_BASE_COUNTER_SHIFT) /* 0xFFFFFFFF */ +/* TXEVENT_FIFO_CTRL */ +#define CAN_TXEVENT_FIFO_CTRL_OFFSET (0x114U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT (0U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_MASK (0x1U << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT (1U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_WATERMARK_SHIFT) /* 0x0000001E */ +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT (5U) +#define CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_MASK (0xFU << CAN_TXEVENT_FIFO_CTRL_TXE_FIFO_CNT_SHIFT) /* 0x000001E0 */ +/* RX_FIFO_CTRL */ +#define CAN_RX_FIFO_CTRL_OFFSET (0x118U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT (0U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_MASK (0x1U << CAN_RX_FIFO_CTRL_RX_FIFO_ENABLE_SHIFT) /* 0x00000001 */ +#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT (1U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK_SHIFT) /* 0x0000000E */ +#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT (4U) +#define CAN_RX_FIFO_CTRL_RX_FIFO_CNT_MASK (0x7U << CAN_RX_FIFO_CTRL_RX_FIFO_CNT_SHIFT) /* 0x00000070 */ +/* AFR_CTRL */ +#define CAN_AFR_CTRL_OFFSET (0x11CU) +#define CAN_AFR_CTRL_UAF1_SHIFT (0U) +#define CAN_AFR_CTRL_UAF1_MASK (0x1U << CAN_AFR_CTRL_UAF1_SHIFT) /* 0x00000001 */ +#define CAN_AFR_CTRL_UAF2_SHIFT (1U) +#define CAN_AFR_CTRL_UAF2_MASK (0x1U << CAN_AFR_CTRL_UAF2_SHIFT) /* 0x00000002 */ +#define CAN_AFR_CTRL_UAF3_SHIFT (2U) +#define CAN_AFR_CTRL_UAF3_MASK (0x1U << CAN_AFR_CTRL_UAF3_SHIFT) /* 0x00000004 */ +#define CAN_AFR_CTRL_UAF4_SHIFT (3U) +#define CAN_AFR_CTRL_UAF4_MASK (0x1U << CAN_AFR_CTRL_UAF4_SHIFT) /* 0x00000008 */ +#define CAN_AFR_CTRL_UAF5_SHIFT (4U) +#define CAN_AFR_CTRL_UAF5_MASK (0x1U << CAN_AFR_CTRL_UAF5_SHIFT) /* 0x00000010 */ +/* IDCODE0 */ +#define CAN_IDCODE0_OFFSET (0x120U) +#define CAN_IDCODE0_ID_CODE_SHIFT (0U) +#define CAN_IDCODE0_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE0_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK0 */ +#define CAN_IDMASK0_OFFSET (0x124U) +#define CAN_IDMASK0_ID_MASK_SHIFT (0U) +#define CAN_IDMASK0_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK0_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE1 */ +#define CAN_IDCODE1_OFFSET (0x128U) +#define CAN_IDCODE1_ID_CODE_SHIFT (0U) +#define CAN_IDCODE1_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE1_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK1 */ +#define CAN_IDMASK1_OFFSET (0x12CU) +#define CAN_IDMASK1_ID_MASK_SHIFT (0U) +#define CAN_IDMASK1_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK1_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE2 */ +#define CAN_IDCODE2_OFFSET (0x130U) +#define CAN_IDCODE2_ID_CODE_SHIFT (0U) +#define CAN_IDCODE2_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE2_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK2 */ +#define CAN_IDMASK2_OFFSET (0x134U) +#define CAN_IDMASK2_ID_MASK_SHIFT (0U) +#define CAN_IDMASK2_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK2_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE3 */ +#define CAN_IDCODE3_OFFSET (0x138U) +#define CAN_IDCODE3_ID_CODE_SHIFT (0U) +#define CAN_IDCODE3_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE3_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK3 */ +#define CAN_IDMASK3_OFFSET (0x13CU) +#define CAN_IDMASK3_ID_MASK_SHIFT (0U) +#define CAN_IDMASK3_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK3_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* IDCODE4 */ +#define CAN_IDCODE4_OFFSET (0x140U) +#define CAN_IDCODE4_ID_CODE_SHIFT (0U) +#define CAN_IDCODE4_ID_CODE_MASK (0x1FFFFFFFU << CAN_IDCODE4_ID_CODE_SHIFT) /* 0x1FFFFFFF */ +/* IDMASK4 */ +#define CAN_IDMASK4_OFFSET (0x144U) +#define CAN_IDMASK4_ID_MASK_SHIFT (0U) +#define CAN_IDMASK4_ID_MASK_MASK (0x1FFFFFFFU << CAN_IDMASK4_ID_MASK_SHIFT) /* 0x1FFFFFFF */ +/* FD_TXFRAMEINFO */ +#define CAN_FD_TXFRAMEINFO_OFFSET (0x200U) +#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT (0U) +#define CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_MASK (0xFU << CAN_FD_TXFRAMEINFO_TXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT (4U) +#define CAN_FD_TXFRAMEINFO_TX_BRS_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_BRS_SHIFT) /* 0x00000010 */ +#define CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT (5U) +#define CAN_FD_TXFRAMEINFO_TX_FDF_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_FDF_SHIFT) /* 0x00000020 */ +#define CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT (6U) +#define CAN_FD_TXFRAMEINFO_TX_RTR_MASK (0x1U << CAN_FD_TXFRAMEINFO_TX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT (7U) +#define CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_MASK (0x1U << CAN_FD_TXFRAMEINFO_TXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* FD_TXID */ +#define CAN_FD_TXID_OFFSET (0x204U) +#define CAN_FD_TXID_TX_ID_SHIFT (0U) +#define CAN_FD_TXID_TX_ID_MASK (0x1FFFFFFFU << CAN_FD_TXID_TX_ID_SHIFT) /* 0x1FFFFFFF */ +/* FD_TXDATA0 */ +#define CAN_FD_TXDATA0_OFFSET (0x208U) +#define CAN_FD_TXDATA0_TX_DATA0_SHIFT (0U) +#define CAN_FD_TXDATA0_TX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_TXDATA0_TX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA1 */ +#define CAN_FD_TXDATA1_OFFSET (0x20CU) +#define CAN_FD_TXDATA1_TX_DATA1_SHIFT (0U) +#define CAN_FD_TXDATA1_TX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_TXDATA1_TX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA2 */ +#define CAN_FD_TXDATA2_OFFSET (0x210U) +#define CAN_FD_TXDATA2_TX_DATA2_SHIFT (0U) +#define CAN_FD_TXDATA2_TX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_TXDATA2_TX_DATA2_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA3 */ +#define CAN_FD_TXDATA3_OFFSET (0x214U) +#define CAN_FD_TXDATA3_TX_DATA3_SHIFT (0U) +#define CAN_FD_TXDATA3_TX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_TXDATA3_TX_DATA3_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA4 */ +#define CAN_FD_TXDATA4_OFFSET (0x218U) +#define CAN_FD_TXDATA4_TX_DATA4_SHIFT (0U) +#define CAN_FD_TXDATA4_TX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_TXDATA4_TX_DATA4_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA5 */ +#define CAN_FD_TXDATA5_OFFSET (0x21CU) +#define CAN_FD_TXDATA5_TX_DATA5_SHIFT (0U) +#define CAN_FD_TXDATA5_TX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_TXDATA5_TX_DATA5_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA6 */ +#define CAN_FD_TXDATA6_OFFSET (0x220U) +#define CAN_FD_TXDATA6_TX_DATA6_SHIFT (0U) +#define CAN_FD_TXDATA6_TX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_TXDATA6_TX_DATA6_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA7 */ +#define CAN_FD_TXDATA7_OFFSET (0x224U) +#define CAN_FD_TXDATA7_TX_DATA7_SHIFT (0U) +#define CAN_FD_TXDATA7_TX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_TXDATA7_TX_DATA7_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA8 */ +#define CAN_FD_TXDATA8_OFFSET (0x228U) +#define CAN_FD_TXDATA8_TX_DATA8_SHIFT (0U) +#define CAN_FD_TXDATA8_TX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_TXDATA8_TX_DATA8_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA9 */ +#define CAN_FD_TXDATA9_OFFSET (0x22CU) +#define CAN_FD_TXDATA9_TX_DATA9_SHIFT (0U) +#define CAN_FD_TXDATA9_TX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_TXDATA9_TX_DATA9_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA10 */ +#define CAN_FD_TXDATA10_OFFSET (0x230U) +#define CAN_FD_TXDATA10_TX_DATA10_SHIFT (0U) +#define CAN_FD_TXDATA10_TX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_TXDATA10_TX_DATA10_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA11 */ +#define CAN_FD_TXDATA11_OFFSET (0x234U) +#define CAN_FD_TXDATA11_TX_DATA11_SHIFT (0U) +#define CAN_FD_TXDATA11_TX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_TXDATA11_TX_DATA11_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA12 */ +#define CAN_FD_TXDATA12_OFFSET (0x238U) +#define CAN_FD_TXDATA12_TX_DATA12_SHIFT (0U) +#define CAN_FD_TXDATA12_TX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_TXDATA12_TX_DATA12_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA13 */ +#define CAN_FD_TXDATA13_OFFSET (0x23CU) +#define CAN_FD_TXDATA13_TX_DATA13_SHIFT (0U) +#define CAN_FD_TXDATA13_TX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_TXDATA13_TX_DATA13_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA14 */ +#define CAN_FD_TXDATA14_OFFSET (0x240U) +#define CAN_FD_TXDATA14_TX_DATA14_SHIFT (0U) +#define CAN_FD_TXDATA14_TX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_TXDATA14_TX_DATA14_SHIFT) /* 0xFFFFFFFF */ +/* FD_TXDATA15 */ +#define CAN_FD_TXDATA15_OFFSET (0x244U) +#define CAN_FD_TXDATA15_TX_DATA15_SHIFT (0U) +#define CAN_FD_TXDATA15_TX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_TXDATA15_TX_DATA15_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXFRAMEINFO */ +#define CAN_FD_RXFRAMEINFO_OFFSET (0x300U) +#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT (0U) +#define CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_MASK (0xFU << CAN_FD_RXFRAMEINFO_RXDATA_LENGTH_SHIFT) /* 0x0000000F */ +#define CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT (4U) +#define CAN_FD_RXFRAMEINFO_RX_BRS_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_BRS_SHIFT) /* 0x00000010 */ +#define CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT (5U) +#define CAN_FD_RXFRAMEINFO_RX_FDF_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_FDF_SHIFT) /* 0x00000020 */ +#define CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT (6U) +#define CAN_FD_RXFRAMEINFO_RX_RTR_MASK (0x1U << CAN_FD_RXFRAMEINFO_RX_RTR_SHIFT) /* 0x00000040 */ +#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT (7U) +#define CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_MASK (0x1U << CAN_FD_RXFRAMEINFO_RXFRAME_FORMAT_SHIFT) /* 0x00000080 */ +/* FD_RXID */ +#define CAN_FD_RXID_OFFSET (0x304U) +#define CAN_FD_RXID (0x0U) +#define CAN_FD_RXID_RX_ID_SHIFT (0U) +#define CAN_FD_RXID_RX_ID_MASK (0x1FFFFFFFU << CAN_FD_RXID_RX_ID_SHIFT) /* 0x1FFFFFFF */ +/* FD_RXTIMESTAMP */ +#define CAN_FD_RXTIMESTAMP_OFFSET (0x308U) +#define CAN_FD_RXTIMESTAMP (0x0U) +#define CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT (0U) +#define CAN_FD_RXTIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFU << CAN_FD_RXTIMESTAMP_TIMESTAMP_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA0 */ +#define CAN_FD_RXDATA0_OFFSET (0x30CU) +#define CAN_FD_RXDATA0 (0x0U) +#define CAN_FD_RXDATA0_RX_DATA0_SHIFT (0U) +#define CAN_FD_RXDATA0_RX_DATA0_MASK (0xFFFFFFFFU << CAN_FD_RXDATA0_RX_DATA0_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA1 */ +#define CAN_FD_RXDATA1_OFFSET (0x310U) +#define CAN_FD_RXDATA1 (0x0U) +#define CAN_FD_RXDATA1_RX_DATA1_SHIFT (0U) +#define CAN_FD_RXDATA1_RX_DATA1_MASK (0xFFFFFFFFU << CAN_FD_RXDATA1_RX_DATA1_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA2 */ +#define CAN_FD_RXDATA2_OFFSET (0x314U) +#define CAN_FD_RXDATA2 (0x0U) +#define CAN_FD_RXDATA2_RX_DATA2_SHIFT (0U) +#define CAN_FD_RXDATA2_RX_DATA2_MASK (0xFFFFFFFFU << CAN_FD_RXDATA2_RX_DATA2_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA3 */ +#define CAN_FD_RXDATA3_OFFSET (0x318U) +#define CAN_FD_RXDATA3 (0x0U) +#define CAN_FD_RXDATA3_RX_DATA3_SHIFT (0U) +#define CAN_FD_RXDATA3_RX_DATA3_MASK (0xFFFFFFFFU << CAN_FD_RXDATA3_RX_DATA3_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA4 */ +#define CAN_FD_RXDATA4_OFFSET (0x31CU) +#define CAN_FD_RXDATA4 (0x0U) +#define CAN_FD_RXDATA4_RX_DATA4_SHIFT (0U) +#define CAN_FD_RXDATA4_RX_DATA4_MASK (0xFFFFFFFFU << CAN_FD_RXDATA4_RX_DATA4_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA5 */ +#define CAN_FD_RXDATA5_OFFSET (0x320U) +#define CAN_FD_RXDATA5 (0x0U) +#define CAN_FD_RXDATA5_RX_DATA5_SHIFT (0U) +#define CAN_FD_RXDATA5_RX_DATA5_MASK (0xFFFFFFFFU << CAN_FD_RXDATA5_RX_DATA5_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA6 */ +#define CAN_FD_RXDATA6_OFFSET (0x324U) +#define CAN_FD_RXDATA6 (0x0U) +#define CAN_FD_RXDATA6_RX_DATA6_SHIFT (0U) +#define CAN_FD_RXDATA6_RX_DATA6_MASK (0xFFFFFFFFU << CAN_FD_RXDATA6_RX_DATA6_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA7 */ +#define CAN_FD_RXDATA7_OFFSET (0x328U) +#define CAN_FD_RXDATA7 (0x0U) +#define CAN_FD_RXDATA7_RX_DATA7_SHIFT (0U) +#define CAN_FD_RXDATA7_RX_DATA7_MASK (0xFFFFFFFFU << CAN_FD_RXDATA7_RX_DATA7_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA8 */ +#define CAN_FD_RXDATA8_OFFSET (0x32CU) +#define CAN_FD_RXDATA8 (0x0U) +#define CAN_FD_RXDATA8_RX_DATA8_SHIFT (0U) +#define CAN_FD_RXDATA8_RX_DATA8_MASK (0xFFFFFFFFU << CAN_FD_RXDATA8_RX_DATA8_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA9 */ +#define CAN_FD_RXDATA9_OFFSET (0x330U) +#define CAN_FD_RXDATA9 (0x0U) +#define CAN_FD_RXDATA9_RX_DATA9_SHIFT (0U) +#define CAN_FD_RXDATA9_RX_DATA9_MASK (0xFFFFFFFFU << CAN_FD_RXDATA9_RX_DATA9_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA10 */ +#define CAN_FD_RXDATA10_OFFSET (0x334U) +#define CAN_FD_RXDATA10 (0x0U) +#define CAN_FD_RXDATA10_RX_DATA10_SHIFT (0U) +#define CAN_FD_RXDATA10_RX_DATA10_MASK (0xFFFFFFFFU << CAN_FD_RXDATA10_RX_DATA10_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA11 */ +#define CAN_FD_RXDATA11_OFFSET (0x338U) +#define CAN_FD_RXDATA11 (0x0U) +#define CAN_FD_RXDATA11_RX_DATA11_SHIFT (0U) +#define CAN_FD_RXDATA11_RX_DATA11_MASK (0xFFFFFFFFU << CAN_FD_RXDATA11_RX_DATA11_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA12 */ +#define CAN_FD_RXDATA12_OFFSET (0x33CU) +#define CAN_FD_RXDATA12 (0x0U) +#define CAN_FD_RXDATA12_RX_DATA12_SHIFT (0U) +#define CAN_FD_RXDATA12_RX_DATA12_MASK (0xFFFFFFFFU << CAN_FD_RXDATA12_RX_DATA12_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA13 */ +#define CAN_FD_RXDATA13_OFFSET (0x340U) +#define CAN_FD_RXDATA13 (0x0U) +#define CAN_FD_RXDATA13_RX_DATA13_SHIFT (0U) +#define CAN_FD_RXDATA13_RX_DATA13_MASK (0xFFFFFFFFU << CAN_FD_RXDATA13_RX_DATA13_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA14 */ +#define CAN_FD_RXDATA14_OFFSET (0x344U) +#define CAN_FD_RXDATA14 (0x0U) +#define CAN_FD_RXDATA14_RX_DATA14_SHIFT (0U) +#define CAN_FD_RXDATA14_RX_DATA14_MASK (0xFFFFFFFFU << CAN_FD_RXDATA14_RX_DATA14_SHIFT) /* 0xFFFFFFFF */ +/* FD_RXDATA15 */ +#define CAN_FD_RXDATA15_OFFSET (0x348U) +#define CAN_FD_RXDATA15 (0x0U) +#define CAN_FD_RXDATA15_RX_DATA15_SHIFT (0U) +#define CAN_FD_RXDATA15_RX_DATA15_MASK (0xFFFFFFFFU << CAN_FD_RXDATA15_RX_DATA15_SHIFT) /* 0xFFFFFFFF */ +/* RX_FIFO_RDATA */ +#define CAN_RX_FIFO_RDATA_OFFSET (0x400U) +#define CAN_RX_FIFO_RDATA (0x0U) +#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT (0U) +#define CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_RX_FIFO_RDATA_RX_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */ +/* TXE_FIFO_RDATA */ +#define CAN_TXE_FIFO_RDATA_OFFSET (0x500U) +#define CAN_TXE_FIFO_RDATA (0x0U) +#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT (0U) +#define CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_MASK (0xFFFFFFFFU << CAN_TXE_FIFO_RDATA_TXE_FIFO_RDATA_SHIFT) /* 0xFFFFFFFF */ +/******************************************WDT*******************************************/ +/* CR */ +#define WDT_CR_OFFSET (0x0U) +#define WDT_CR_EN_SHIFT (0U) +#define WDT_CR_EN_MASK (0x1U << WDT_CR_EN_SHIFT) /* 0x00000001 */ +#define WDT_CR_RESP_MODE_SHIFT (1U) +#define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) /* 0x00000002 */ +#define WDT_CR_RST_PLUSE_LENGTH_SHIFT (2U) +#define WDT_CR_RST_PLUSE_LENGTH_MASK (0x7U << WDT_CR_RST_PLUSE_LENGTH_SHIFT) /* 0x0000001C */ +/* TORR */ +#define WDT_TORR_OFFSET (0x4U) +#define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U) +#define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) /* 0x0000000F */ +/* CCVR */ +#define WDT_CCVR_OFFSET (0x8U) +#define WDT_CCVR (0xFFFFU) +#define WDT_CCVR_CUR_CNT_SHIFT (0U) +#define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) /* 0xFFFFFFFF */ +/* CRR */ +#define WDT_CRR_OFFSET (0xCU) +#define WDT_CRR_CNT_RESTART_SHIFT (0U) +#define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) /* 0x000000FF */ +/* STAT */ +#define WDT_STAT_OFFSET (0x10U) +#define WDT_STAT (0x0U) +#define WDT_STAT_STATUS_SHIFT (0U) +#define WDT_STAT_STATUS_MASK (0x1U << WDT_STAT_STATUS_SHIFT) /* 0x00000001 */ +/* EOI */ +#define WDT_EOI_OFFSET (0x14U) +#define WDT_EOI (0x0U) +#define WDT_EOI_INT_CLR_SHIFT (0U) +#define WDT_EOI_INT_CLR_MASK (0x1U << WDT_EOI_INT_CLR_SHIFT) +/******************************************SPI*******************************************/ +/* CTRLR0 */ +#define SPI_CTRLR0_OFFSET (0x0U) +#define SPI_CTRLR0_DFS_SHIFT (0U) +#define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) /* 0x00000003 */ +#define SPI_CTRLR0_CFS_SHIFT (2U) +#define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) /* 0x0000003C */ +#define SPI_CTRLR0_SCPH_SHIFT (6U) +#define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) /* 0x00000040 */ +#define SPI_CTRLR0_SCPOL_SHIFT (7U) +#define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) /* 0x00000080 */ +#define SPI_CTRLR0_CSM_SHIFT (8U) +#define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) /* 0x00000300 */ +#define SPI_CTRLR0_SSD_SHIFT (10U) +#define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) /* 0x00000400 */ +#define SPI_CTRLR0_EM_SHIFT (11U) +#define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) /* 0x00000800 */ +#define SPI_CTRLR0_FBM_SHIFT (12U) +#define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) /* 0x00001000 */ +#define SPI_CTRLR0_BHT_SHIFT (13U) +#define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) /* 0x00002000 */ +#define SPI_CTRLR0_RSD_SHIFT (14U) +#define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) /* 0x0000C000 */ +#define SPI_CTRLR0_FRF_SHIFT (16U) +#define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) /* 0x00030000 */ +#define SPI_CTRLR0_XFM_SHIFT (18U) +#define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) /* 0x000C0000 */ +#define SPI_CTRLR0_OPM_SHIFT (20U) +#define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) /* 0x00100000 */ +#define SPI_CTRLR0_MTM_SHIFT (21U) +#define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) /* 0x00200000 */ +#define SPI_CTRLR0_SM_SHIFT (22U) +#define SPI_CTRLR0_SM_MASK (0x1U << SPI_CTRLR0_SM_SHIFT) /* 0x00400000 */ +#define SPI_CTRLR0_SOI_SHIFT (23U) +#define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) /* 0x01800000 */ +#define SPI_CTRLR0_LBK_SHIFT (25U) +#define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) /* 0x02000000 */ +/* CTRLR1 */ +#define SPI_CTRLR1_OFFSET (0x4U) +#define SPI_CTRLR1_NDM_SHIFT (0U) +#define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) /* 0xFFFFFFFF */ +/* ENR */ +#define SPI_ENR_OFFSET (0x8U) +#define SPI_ENR_ENR_SHIFT (0U) +#define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) /* 0x00000001 */ +/* SER */ +#define SPI_SER_OFFSET (0xCU) +#define SPI_SER_SER_SHIFT (0U) +#define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) /* 0x00000003 */ +/* BAUDR */ +#define SPI_BAUDR_OFFSET (0x10U) +#define SPI_BAUDR_BAUDR_SHIFT (0U) +#define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) /* 0x0000FFFF */ +/* TXFTLR */ +#define SPI_TXFTLR_OFFSET (0x14U) +#define SPI_TXFTLR_XFTLR_SHIFT (0U) +#define SPI_TXFTLR_XFTLR_MASK (0x3FU << SPI_TXFTLR_XFTLR_SHIFT) /* 0x0000003F */ +/* RXFTLR */ +#define SPI_RXFTLR_OFFSET (0x18U) +#define SPI_RXFTLR_RXFTLR_SHIFT (0U) +#define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) /* 0x0000003F */ +/* TXFLR */ +#define SPI_TXFLR_OFFSET (0x1CU) +#define SPI_TXFLR (0x0U) +#define SPI_TXFLR_TXFLR_SHIFT (0U) +#define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) /* 0x0000007F */ +/* RXFLR */ +#define SPI_RXFLR_OFFSET (0x20U) +#define SPI_RXFLR (0x0U) +#define SPI_RXFLR_RXFLR_SHIFT (0U) +#define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) /* 0x0000007F */ +/* SR */ +#define SPI_SR_OFFSET (0x24U) +#define SPI_SR (0x4CU) +#define SPI_SR_BSF_SHIFT (0U) +#define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) /* 0x00000001 */ +#define SPI_SR_TFF_SHIFT (1U) +#define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) /* 0x00000002 */ +#define SPI_SR_TFE_SHIFT (2U) +#define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) /* 0x00000004 */ +#define SPI_SR_RFE_SHIFT (3U) +#define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) /* 0x00000008 */ +#define SPI_SR_RFF_SHIFT (4U) +#define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) /* 0x00000010 */ +#define SPI_SR_STB_SHIFT (5U) +#define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) /* 0x00000020 */ +#define SPI_SR_SSI_SHIFT (6U) +#define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) /* 0x00000040 */ +/* IPR */ +#define SPI_IPR_OFFSET (0x28U) +#define SPI_IPR_IPR_SHIFT (0U) +#define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) /* 0x00000001 */ +/* IMR */ +#define SPI_IMR_OFFSET (0x2CU) +#define SPI_IMR_TFEIM_SHIFT (0U) +#define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) /* 0x00000001 */ +#define SPI_IMR_TFOIM_SHIFT (1U) +#define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) /* 0x00000002 */ +#define SPI_IMR_RFUIM_SHIFT (2U) +#define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) /* 0x00000004 */ +#define SPI_IMR_RFOIM_SHIFT (3U) +#define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) /* 0x00000008 */ +#define SPI_IMR_RFFIM_SHIFT (4U) +#define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) /* 0x00000010 */ +#define SPI_IMR_TOIM_SHIFT (5U) +#define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) /* 0x00000020 */ +#define SPI_IMR_SSPIM_SHIFT (6U) +#define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) /* 0x00000040 */ +#define SPI_IMR_TXFIM_SHIFT (7U) +#define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) /* 0x00000080 */ +/* ISR */ +#define SPI_ISR_OFFSET (0x30U) +#define SPI_ISR_TFEIS_SHIFT (0U) +#define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) /* 0x00000001 */ +#define SPI_ISR_TFOIS_SHIFT (1U) +#define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) /* 0x00000002 */ +#define SPI_ISR_RFUIS_SHIFT (2U) +#define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) /* 0x00000004 */ +#define SPI_ISR_RFOIS_SHIFT (3U) +#define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) /* 0x00000008 */ +#define SPI_ISR_RFFIS_SHIFT (4U) +#define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) /* 0x00000010 */ +#define SPI_ISR_TOIS_SHIFT (5U) +#define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) /* 0x00000020 */ +#define SPI_ISR_SSPIS_SHIFT (6U) +#define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) /* 0x00000040 */ +#define SPI_ISR_TXFIS_SHIFT (7U) +#define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) /* 0x00000080 */ +/* RISR */ +#define SPI_RISR_OFFSET (0x34U) +#define SPI_RISR_TFERIS_SHIFT (0U) +#define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) /* 0x00000001 */ +#define SPI_RISR_TFORIS_SHIFT (1U) +#define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) /* 0x00000002 */ +#define SPI_RISR_RFURIS_SHIFT (2U) +#define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) /* 0x00000004 */ +#define SPI_RISR_RFORIS_SHIFT (3U) +#define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) /* 0x00000008 */ +#define SPI_RISR_RFFRIS_SHIFT (4U) +#define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) /* 0x00000010 */ +#define SPI_RISR_TORIS_SHIFT (5U) +#define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) /* 0x00000020 */ +#define SPI_RISR_SSPRIS_SHIFT (6U) +#define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) /* 0x00000040 */ +#define SPI_RISR_TXFRIS_SHIFT (7U) +#define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) /* 0x00000080 */ +/* ICR */ +#define SPI_ICR_OFFSET (0x38U) +#define SPI_ICR_CCI_SHIFT (0U) +#define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) /* 0x00000001 */ +#define SPI_ICR_CRFUI_SHIFT (1U) +#define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) /* 0x00000002 */ +#define SPI_ICR_CRFOI_SHIFT (2U) +#define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) /* 0x00000004 */ +#define SPI_ICR_CTFOI_SHIFT (3U) +#define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) /* 0x00000008 */ +#define SPI_ICR_CTOI_SHIFT (4U) +#define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) /* 0x00000010 */ +#define SPI_ICR_CSSPI_SHIFT (5U) +#define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) /* 0x00000020 */ +#define SPI_ICR_CTXFI_SHIFT (6U) +#define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) /* 0x00000040 */ +/* DMACR */ +#define SPI_DMACR_OFFSET (0x3CU) +#define SPI_DMACR_RDE_SHIFT (0U) +#define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) /* 0x00000001 */ +#define SPI_DMACR_TDE_SHIFT (1U) +#define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) /* 0x00000002 */ +/* DMATDLR */ +#define SPI_DMATDLR_OFFSET (0x40U) +#define SPI_DMATDLR_TDL_SHIFT (0U) +#define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) /* 0x0000003F */ +/* DMARDLR */ +#define SPI_DMARDLR_OFFSET (0x44U) +#define SPI_DMARDLR_RDL_SHIFT (0U) +#define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) /* 0x0000003F */ +/* TIMEOUT */ +#define SPI_TIMEOUT_OFFSET (0x4CU) +#define SPI_TIMEOUT_TOV_SHIFT (0U) +#define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) /* 0x0000FFFF */ +#define SPI_TIMEOUT_TOE_SHIFT (16U) +#define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) /* 0x00010000 */ +/* BYPASS */ +#define SPI_BYPASS_OFFSET (0x50U) +#define SPI_BYPASS_BYEN_SHIFT (0U) +#define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) /* 0x00000001 */ +#define SPI_BYPASS_FBM_SHIFT (1U) +#define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) /* 0x00000002 */ +#define SPI_BYPASS_END_SHIFT (2U) +#define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) /* 0x00000004 */ +#define SPI_BYPASS_RXCP_SHIFT (3U) +#define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) /* 0x00000008 */ +#define SPI_BYPASS_TXCP_SHIFT (4U) +#define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) /* 0x00000010 */ +/* TXDR */ +#define SPI_TXDR_OFFSET (0x400U) +#define SPI_TXDR_TXDR_SHIFT (0U) +#define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) /* 0x0000FFFF */ +/* RXDR */ +#define SPI_RXDR_OFFSET (0x800U) +#define SPI_RXDR (0x0U) +#define SPI_RXDR_RXDR_SHIFT (0U) +#define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) +/******************************************PDM*******************************************/ +/* SYSCONFIG */ +#define PDM_SYSCONFIG_OFFSET (0x0U) +#define PDM_SYSCONFIG_RX_CLR_SHIFT (0U) +#define PDM_SYSCONFIG_RX_CLR_MASK (0x1U << PDM_SYSCONFIG_RX_CLR_SHIFT) /* 0x00000001 */ +#define PDM_SYSCONFIG_RX_START_SHIFT (2U) +#define PDM_SYSCONFIG_RX_START_MASK (0x1U << PDM_SYSCONFIG_RX_START_SHIFT) /* 0x00000004 */ +/* CTRL0 */ +#define PDM_CTRL0_OFFSET (0x4U) +#define PDM_CTRL0_DATA_VLD_WIDTH_SHIFT (0U) +#define PDM_CTRL0_DATA_VLD_WIDTH_MASK (0x1FU << PDM_CTRL0_DATA_VLD_WIDTH_SHIFT) /* 0x0000001F */ +#define PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT (5U) +#define PDM_CTRL0_SAMPLE_RATE_SEL_MASK (0x7U << PDM_CTRL0_SAMPLE_RATE_SEL_SHIFT) /* 0x000000E0 */ +#define PDM_CTRL0_INT_DIV_CON_SHIFT (8U) +#define PDM_CTRL0_INT_DIV_CON_MASK (0xFFU << PDM_CTRL0_INT_DIV_CON_SHIFT) /* 0x0000FF00 */ +#define PDM_CTRL0_SIG_SCALE_MODE_SHIFT (24U) +#define PDM_CTRL0_SIG_SCALE_MODE_MASK (0x1U << PDM_CTRL0_SIG_SCALE_MODE_SHIFT) /* 0x01000000 */ +#define PDM_CTRL0_FILTER_GATE_EN_SHIFT (25U) +#define PDM_CTRL0_FILTER_GATE_EN_MASK (0x1U << PDM_CTRL0_FILTER_GATE_EN_SHIFT) /* 0x02000000 */ +#define PDM_CTRL0_HWT_EN_SHIFT (26U) +#define PDM_CTRL0_HWT_EN_MASK (0x1U << PDM_CTRL0_HWT_EN_SHIFT) /* 0x04000000 */ +#define PDM_CTRL0_PATH0_EN_SHIFT (27U) +#define PDM_CTRL0_PATH0_EN_MASK (0x1U << PDM_CTRL0_PATH0_EN_SHIFT) /* 0x08000000 */ +#define PDM_CTRL0_PATH1_EN_SHIFT (28U) +#define PDM_CTRL0_PATH1_EN_MASK (0x1U << PDM_CTRL0_PATH1_EN_SHIFT) /* 0x10000000 */ +#define PDM_CTRL0_PATH2_EN_SHIFT (29U) +#define PDM_CTRL0_PATH2_EN_MASK (0x1U << PDM_CTRL0_PATH2_EN_SHIFT) /* 0x20000000 */ +#define PDM_CTRL0_PATH3_EN_SHIFT (30U) +#define PDM_CTRL0_PATH3_EN_MASK (0x1U << PDM_CTRL0_PATH3_EN_SHIFT) /* 0x40000000 */ +#define PDM_CTRL0_SJM_SEL_SHIFT (31U) +#define PDM_CTRL0_SJM_SEL_MASK (0x1U << PDM_CTRL0_SJM_SEL_SHIFT) /* 0x80000000 */ +/* CTRL1 */ +#define PDM_CTRL1_OFFSET (0x8U) +#define PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT (0U) +#define PDM_CTRL1_FRAC_DIV_DENOMONATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_DENOMONATOR_SHIFT) /* 0x0000FFFF */ +#define PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT (16U) +#define PDM_CTRL1_FRAC_DIV_NUMERATOR_MASK (0xFFFFU << PDM_CTRL1_FRAC_DIV_NUMERATOR_SHIFT) /* 0xFFFF0000 */ +/* CLK_CTRL */ +#define PDM_CLK_CTRL_OFFSET (0xCU) +#define PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT (0U) +#define PDM_CLK_CTRL_CIC_DS_RATIO_MASK (0x3U << PDM_CLK_CTRL_CIC_DS_RATIO_SHIFT) /* 0x00000003 */ +#define PDM_CLK_CTRL_FIR_COM_BPS_SHIFT (2U) +#define PDM_CLK_CTRL_FIR_COM_BPS_MASK (0x1U << PDM_CLK_CTRL_FIR_COM_BPS_SHIFT) /* 0x00000004 */ +#define PDM_CLK_CTRL_LR_CH_EX_SHIFT (3U) +#define PDM_CLK_CTRL_LR_CH_EX_MASK (0x1U << PDM_CLK_CTRL_LR_CH_EX_SHIFT) /* 0x00000008 */ +#define PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT (4U) +#define PDM_CLK_CTRL_DIV_TYPE_SEL_MASK (0x1U << PDM_CLK_CTRL_DIV_TYPE_SEL_SHIFT) /* 0x00000010 */ +#define PDM_CLK_CTRL_PDM_CLK_EN_SHIFT (5U) +#define PDM_CLK_CTRL_PDM_CLK_EN_MASK (0x1U << PDM_CLK_CTRL_PDM_CLK_EN_SHIFT) /* 0x00000020 */ +/* HPF_CTRL */ +#define PDM_HPF_CTRL_OFFSET (0x10U) +#define PDM_HPF_CTRL_HPF_CF_SHIFT (0U) +#define PDM_HPF_CTRL_HPF_CF_MASK (0x3U << PDM_HPF_CTRL_HPF_CF_SHIFT) /* 0x00000003 */ +#define PDM_HPF_CTRL_HPFRE_SHIFT (2U) +#define PDM_HPF_CTRL_HPFRE_MASK (0x1U << PDM_HPF_CTRL_HPFRE_SHIFT) /* 0x00000004 */ +#define PDM_HPF_CTRL_HPFLE_SHIFT (3U) +#define PDM_HPF_CTRL_HPFLE_MASK (0x1U << PDM_HPF_CTRL_HPFLE_SHIFT) /* 0x00000008 */ +/* FIFO_CTRL */ +#define PDM_FIFO_CTRL_OFFSET (0x14U) +#define PDM_FIFO_CTRL_RFL_SHIFT (0U) +#define PDM_FIFO_CTRL_RFL_MASK (0xFFU << PDM_FIFO_CTRL_RFL_SHIFT) /* 0x000000FF */ +#define PDM_FIFO_CTRL_RFT_SHIFT (8U) +#define PDM_FIFO_CTRL_RFT_MASK (0x7FU << PDM_FIFO_CTRL_RFT_SHIFT) /* 0x00007F00 */ +/* DMA_CTRL */ +#define PDM_DMA_CTRL_OFFSET (0x18U) +#define PDM_DMA_CTRL_RDL_SHIFT (0U) +#define PDM_DMA_CTRL_RDL_MASK (0x7FU << PDM_DMA_CTRL_RDL_SHIFT) /* 0x0000007F */ +#define PDM_DMA_CTRL_RDE_SHIFT (8U) +#define PDM_DMA_CTRL_RDE_MASK (0x1U << PDM_DMA_CTRL_RDE_SHIFT) /* 0x00000100 */ +/* INT_EN */ +#define PDM_INT_EN_OFFSET (0x1CU) +#define PDM_INT_EN_RXTIE_SHIFT (0U) +#define PDM_INT_EN_RXTIE_MASK (0x1U << PDM_INT_EN_RXTIE_SHIFT) /* 0x00000001 */ +#define PDM_INT_EN_RXOIE_SHIFT (1U) +#define PDM_INT_EN_RXOIE_MASK (0x1U << PDM_INT_EN_RXOIE_SHIFT) /* 0x00000002 */ +/* INT_CLR */ +#define PDM_INT_CLR_OFFSET (0x20U) +#define PDM_INT_CLR_RXOIC_SHIFT (1U) +#define PDM_INT_CLR_RXOIC_MASK (0x1U << PDM_INT_CLR_RXOIC_SHIFT) /* 0x00000002 */ +/* INT_ST */ +#define PDM_INT_ST_OFFSET (0x24U) +#define PDM_INT_ST (0x0U) +#define PDM_INT_ST_RXFI_SHIFT (0U) +#define PDM_INT_ST_RXFI_MASK (0x1U << PDM_INT_ST_RXFI_SHIFT) /* 0x00000001 */ +#define PDM_INT_ST_RXOI_SHIFT (1U) +#define PDM_INT_ST_RXOI_MASK (0x1U << PDM_INT_ST_RXOI_SHIFT) /* 0x00000002 */ +/* RXFIFO_DATA_REG */ +#define PDM_RXFIFO_DATA_REG_OFFSET (0x30U) +#define PDM_RXFIFO_DATA_REG (0x0U) +#define PDM_RXFIFO_DATA_REG_RXDR_SHIFT (0U) +#define PDM_RXFIFO_DATA_REG_RXDR_MASK (0xFFFFFFFFU << PDM_RXFIFO_DATA_REG_RXDR_SHIFT) /* 0xFFFFFFFF */ +/* DATA0R_REG */ +#define PDM_DATA0R_REG_OFFSET (0x34U) +#define PDM_DATA0R_REG (0x0U) +#define PDM_DATA0R_REG_DATA0R_SHIFT (0U) +#define PDM_DATA0R_REG_DATA0R_MASK (0xFFFFFFFFU << PDM_DATA0R_REG_DATA0R_SHIFT) /* 0xFFFFFFFF */ +/* DATA0L_REG */ +#define PDM_DATA0L_REG_OFFSET (0x38U) +#define PDM_DATA0L_REG (0x0U) +#define PDM_DATA0L_REG_DATA0L_SHIFT (0U) +#define PDM_DATA0L_REG_DATA0L_MASK (0xFFFFFFFFU << PDM_DATA0L_REG_DATA0L_SHIFT) /* 0xFFFFFFFF */ +/* DATA1R_REG */ +#define PDM_DATA1R_REG_OFFSET (0x3CU) +#define PDM_DATA1R_REG (0x0U) +#define PDM_DATA1R_REG_DATA1R_SHIFT (0U) +#define PDM_DATA1R_REG_DATA1R_MASK (0x1U << PDM_DATA1R_REG_DATA1R_SHIFT) /* 0x00000001 */ +/* DATA1L_REG */ +#define PDM_DATA1L_REG_OFFSET (0x40U) +#define PDM_DATA1L_REG (0x0U) +#define PDM_DATA1L_REG_DATA1L_SHIFT (0U) +#define PDM_DATA1L_REG_DATA1L_MASK (0xFFFFFFFFU << PDM_DATA1L_REG_DATA1L_SHIFT) /* 0xFFFFFFFF */ +/* DATA2R_REG */ +#define PDM_DATA2R_REG_OFFSET (0x44U) +#define PDM_DATA2R_REG (0x0U) +#define PDM_DATA2R_REG_DATA2R_SHIFT (0U) +#define PDM_DATA2R_REG_DATA2R_MASK (0xFFFFFFFFU << PDM_DATA2R_REG_DATA2R_SHIFT) /* 0xFFFFFFFF */ +/* DATA2L_REG */ +#define PDM_DATA2L_REG_OFFSET (0x48U) +#define PDM_DATA2L_REG (0x0U) +#define PDM_DATA2L_REG_DATA2L_SHIFT (0U) +#define PDM_DATA2L_REG_DATA2L_MASK (0xFFFFFFFFU << PDM_DATA2L_REG_DATA2L_SHIFT) /* 0xFFFFFFFF */ +/* DATA3R_REG */ +#define PDM_DATA3R_REG_OFFSET (0x4CU) +#define PDM_DATA3R_REG (0x0U) +#define PDM_DATA3R_REG_DATA3R_SHIFT (0U) +#define PDM_DATA3R_REG_DATA3R_MASK (0xFFFFFFFFU << PDM_DATA3R_REG_DATA3R_SHIFT) /* 0xFFFFFFFF */ +/* DATA3L_REG */ +#define PDM_DATA3L_REG_OFFSET (0x50U) +#define PDM_DATA3L_REG (0x0U) +#define PDM_DATA3L_REG_DATA3L_SHIFT (0U) +#define PDM_DATA3L_REG_DATA3L_MASK (0xFFFFFFFFU << PDM_DATA3L_REG_DATA3L_SHIFT) /* 0xFFFFFFFF */ +/* DATA_VALID */ +#define PDM_DATA_VALID_OFFSET (0x54U) +#define PDM_DATA_VALID (0x0U) +#define PDM_DATA_VALID_PATH3_VLD_SHIFT (0U) +#define PDM_DATA_VALID_PATH3_VLD_MASK (0x1U << PDM_DATA_VALID_PATH3_VLD_SHIFT) /* 0x00000001 */ +#define PDM_DATA_VALID_PATH2_VLD_SHIFT (1U) +#define PDM_DATA_VALID_PATH2_VLD_MASK (0x1U << PDM_DATA_VALID_PATH2_VLD_SHIFT) /* 0x00000002 */ +#define PDM_DATA_VALID_PATH1_VLD_SHIFT (2U) +#define PDM_DATA_VALID_PATH1_VLD_MASK (0x1U << PDM_DATA_VALID_PATH1_VLD_SHIFT) /* 0x00000004 */ +#define PDM_DATA_VALID_PATH0_VLD_SHIFT (3U) +#define PDM_DATA_VALID_PATH0_VLD_MASK (0x1U << PDM_DATA_VALID_PATH0_VLD_SHIFT) /* 0x00000008 */ +/* VERSION */ +#define PDM_VERSION_OFFSET (0x58U) +#define PDM_VERSION (0x59313030U) +#define PDM_VERSION_VERSION_SHIFT (0U) +#define PDM_VERSION_VERSION_MASK (0xFFFFFFFFU << PDM_VERSION_VERSION_SHIFT) /* 0xFFFFFFFF */ +/* INCR_RXDR */ +#define PDM_INCR_RXDR_OFFSET (0x400U) +#define PDM_INCR_RXDR (0x0U) +#define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT (0U) +#define PDM_INCR_RXDR_RECEIVE_FIFO_DATA_MASK (0xFFFFFFFFU << PDM_INCR_RXDR_RECEIVE_FIFO_DATA_SHIFT) /* 0xFFFFFFFF */ +/******************************************VAD*******************************************/ +/* CONTROL */ +#define VAD_CONTROL_OFFSET (0x0U) +#define VAD_CONTROL_VAD_EN_SHIFT (0U) +#define VAD_CONTROL_VAD_EN_MASK (0x1U << VAD_CONTROL_VAD_EN_SHIFT) /* 0x00000001 */ +#define VAD_CONTROL_SOURCE_SELECT_SHIFT (1U) +#define VAD_CONTROL_SOURCE_SELECT_MASK (0x7U << VAD_CONTROL_SOURCE_SELECT_SHIFT) /* 0x0000000E */ +#define VAD_CONTROL_SOURCE_BURST_SHIFT (4U) +#define VAD_CONTROL_SOURCE_BURST_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_SHIFT) /* 0x00000070 */ +#define VAD_CONTROL_SOURCE_BURST_NUM_SHIFT (7U) +#define VAD_CONTROL_SOURCE_BURST_NUM_MASK (0x7U << VAD_CONTROL_SOURCE_BURST_NUM_SHIFT) /* 0x00000380 */ +#define VAD_CONTROL_INCR_LENGTH_SHIFT (10U) +#define VAD_CONTROL_INCR_LENGTH_MASK (0xFU << VAD_CONTROL_INCR_LENGTH_SHIFT) /* 0x00003C00 */ +#define VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT (14U) +#define VAD_CONTROL_SOURCE_FIXADDR_EN_MASK (0x1U << VAD_CONTROL_SOURCE_FIXADDR_EN_SHIFT) /* 0x00004000 */ +#define VAD_CONTROL_VAD_MODE_SHIFT (20U) +#define VAD_CONTROL_VAD_MODE_MASK (0x3U << VAD_CONTROL_VAD_MODE_SHIFT) /* 0x00300000 */ +#define VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT (23U) +#define VAD_CONTROL_VOICE_CHANNEL_NUM_MASK (0x7U << VAD_CONTROL_VOICE_CHANNEL_NUM_SHIFT) /* 0x03800000 */ +#define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT (26U) +#define VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_MASK (0x1U << VAD_CONTROL_VOICE_CHANNEL_BITWIDTH_SHIFT) /* 0x04000000 */ +#define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT (27U) +#define VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_ALIGN_MODE_SHIFT) /* 0x08000000 */ +#define VAD_CONTROL_VOICE_24BIT_SAT_SHIFT (28U) +#define VAD_CONTROL_VOICE_24BIT_SAT_MASK (0x1U << VAD_CONTROL_VOICE_24BIT_SAT_SHIFT) /* 0x10000000 */ +#define VAD_CONTROL_VAD_DET_CHANNEL_SHIFT (29U) +#define VAD_CONTROL_VAD_DET_CHANNEL_MASK (0x7U << VAD_CONTROL_VAD_DET_CHANNEL_SHIFT) /* 0xE0000000 */ +/* VS_ADDR */ +#define VAD_VS_ADDR_OFFSET (0x4U) +#define VAD_VS_ADDR_VS_ADDR_SHIFT (0U) +#define VAD_VS_ADDR_VS_ADDR_MASK (0xFFFFFFFFU << VAD_VS_ADDR_VS_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* TIMEOUT */ +#define VAD_TIMEOUT_OFFSET (0x4CU) +#define VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT (0U) +#define VAD_TIMEOUT_IDLE_TIMEOUT_THD_MASK (0xFFFFFU << VAD_TIMEOUT_IDLE_TIMEOUT_THD_SHIFT) /* 0x000FFFFF */ +#define VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT (20U) +#define VAD_TIMEOUT_WORK_TIMEOUT_THD_MASK (0x3FFU << VAD_TIMEOUT_WORK_TIMEOUT_THD_SHIFT) /* 0x3FF00000 */ +#define VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT (30U) +#define VAD_TIMEOUT_IDLE_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_IDLE_TIMEOUT_EN_SHIFT) /* 0x40000000 */ +#define VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT (31U) +#define VAD_TIMEOUT_WORK_TIMEOUT_EN_MASK (0x1U << VAD_TIMEOUT_WORK_TIMEOUT_EN_SHIFT) /* 0x80000000 */ +/* RAM_START_ADDR */ +#define VAD_RAM_START_ADDR_OFFSET (0x50U) +#define VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT (0U) +#define VAD_RAM_START_ADDR_RAM_START_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_START_ADDR_RAM_START_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* RAM_END_ADDR */ +#define VAD_RAM_END_ADDR_OFFSET (0x54U) +#define VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT (0U) +#define VAD_RAM_END_ADDR_RAM_END_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_END_ADDR_RAM_END_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* RAM_CUR_ADDR */ +#define VAD_RAM_CUR_ADDR_OFFSET (0x58U) +#define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT (0U) +#define VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_MASK (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_RAM_CUR_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* DET_CON0 */ +#define VAD_DET_CON0_OFFSET (0x5CU) +#define VAD_DET_CON0_GAIN_SHIFT (0U) +#define VAD_DET_CON0_GAIN_MASK (0xFFFU << VAD_DET_CON0_GAIN_SHIFT) /* 0x00000FFF */ +#define VAD_DET_CON0_NOISE_LEVEL_SHIFT (12U) +#define VAD_DET_CON0_NOISE_LEVEL_MASK (0x7U << VAD_DET_CON0_NOISE_LEVEL_SHIFT) /* 0x00007000 */ +#define VAD_DET_CON0_VAD_CON_THD_SHIFT (16U) +#define VAD_DET_CON0_VAD_CON_THD_MASK (0xFFU << VAD_DET_CON0_VAD_CON_THD_SHIFT) /* 0x00FF0000 */ +#define VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT (24U) +#define VAD_DET_CON0_DIS_VAD_CON_THD_MASK (0xFU << VAD_DET_CON0_DIS_VAD_CON_THD_SHIFT) /* 0x0F000000 */ +#define VAD_DET_CON0_VAD_THD_MODE_SHIFT (28U) +#define VAD_DET_CON0_VAD_THD_MODE_MASK (0x3U << VAD_DET_CON0_VAD_THD_MODE_SHIFT) /* 0x30000000 */ +/* DET_CON1 */ +#define VAD_DET_CON1_OFFSET (0x60U) +#define VAD_DET_CON1_SOUND_THD_SHIFT (0U) +#define VAD_DET_CON1_SOUND_THD_MASK (0xFFFFU << VAD_DET_CON1_SOUND_THD_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT (16U) +#define VAD_DET_CON1_NOISE_SAMPLE_NUM_MASK (0x3FFU << VAD_DET_CON1_NOISE_SAMPLE_NUM_SHIFT) /* 0x03FF0000 */ +#define VAD_DET_CON1_CLEAN_IIR_EN_SHIFT (26U) +#define VAD_DET_CON1_CLEAN_IIR_EN_MASK (0x1U << VAD_DET_CON1_CLEAN_IIR_EN_SHIFT) /* 0x04000000 */ +#define VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT (28U) +#define VAD_DET_CON1_FORCE_NOISE_CLK_EN_MASK (0x1U << VAD_DET_CON1_FORCE_NOISE_CLK_EN_SHIFT) /* 0x10000000 */ +#define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT (29U) +#define VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_MASK (0x1U << VAD_DET_CON1_CLEAN_NOISE_AT_BEGIN_SHIFT) /* 0x20000000 */ +#define VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT (30U) +#define VAD_DET_CON1_MIN_NOISE_FIND_MODE_MASK (0x1U << VAD_DET_CON1_MIN_NOISE_FIND_MODE_SHIFT) /* 0x40000000 */ +/* DET_CON2 */ +#define VAD_DET_CON2_OFFSET (0x64U) +#define VAD_DET_CON2_NOISE_FRM_NUM_SHIFT (0U) +#define VAD_DET_CON2_NOISE_FRM_NUM_MASK (0x7FU << VAD_DET_CON2_NOISE_FRM_NUM_SHIFT) /* 0x0000007F */ +#define VAD_DET_CON2_NOISE_ALPHA_SHIFT (8U) +#define VAD_DET_CON2_NOISE_ALPHA_MASK (0xFFU << VAD_DET_CON2_NOISE_ALPHA_SHIFT) /* 0x0000FF00 */ +#define VAD_DET_CON2_IIR_ANUM_0_SHIFT (16U) +#define VAD_DET_CON2_IIR_ANUM_0_MASK (0xFFFFU << VAD_DET_CON2_IIR_ANUM_0_SHIFT) /* 0xFFFF0000 */ +/* DET_CON3 */ +#define VAD_DET_CON3_OFFSET (0x68U) +#define VAD_DET_CON3_IIR_ANUM_1_SHIFT (0U) +#define VAD_DET_CON3_IIR_ANUM_1_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_1_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON3_IIR_ANUM_2_SHIFT (16U) +#define VAD_DET_CON3_IIR_ANUM_2_MASK (0xFFFFU << VAD_DET_CON3_IIR_ANUM_2_SHIFT) /* 0xFFFF0000 */ +/* DET_CON4 */ +#define VAD_DET_CON4_OFFSET (0x6CU) +#define VAD_DET_CON4_IIR_ADEN_1_SHIFT (0U) +#define VAD_DET_CON4_IIR_ADEN_1_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_1_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON4_IIR_ADEN_2_SHIFT (16U) +#define VAD_DET_CON4_IIR_ADEN_2_MASK (0xFFFFU << VAD_DET_CON4_IIR_ADEN_2_SHIFT) /* 0xFFFF0000 */ +/* DET_CON5 */ +#define VAD_DET_CON5_OFFSET (0x70U) +#define VAD_DET_CON5_NOISE_ABS_SHIFT (0U) +#define VAD_DET_CON5_NOISE_ABS_MASK (0xFFFFU << VAD_DET_CON5_NOISE_ABS_SHIFT) /* 0x0000FFFF */ +#define VAD_DET_CON5_IIR_RESULT_SHIFT (16U) +#define VAD_DET_CON5_IIR_RESULT_MASK (0xFFFFU << VAD_DET_CON5_IIR_RESULT_SHIFT) /* 0xFFFF0000 */ +/* INT */ +#define VAD_INT_OFFSET (0x74U) +#define VAD_INT_VAD_DET_INT_EN_SHIFT (0U) +#define VAD_INT_VAD_DET_INT_EN_MASK (0x1U << VAD_INT_VAD_DET_INT_EN_SHIFT) /* 0x00000001 */ +#define VAD_INT_ERROR_INT_EN_SHIFT (1U) +#define VAD_INT_ERROR_INT_EN_MASK (0x1U << VAD_INT_ERROR_INT_EN_SHIFT) /* 0x00000002 */ +#define VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT (2U) +#define VAD_INT_IDLE_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_EN_SHIFT) /* 0x00000004 */ +#define VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT (3U) +#define VAD_INT_WORK_TIMEOUT_INT_EN_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_EN_SHIFT) /* 0x00000008 */ +#define VAD_INT_VAD_DET_INT_SHIFT (4U) +#define VAD_INT_VAD_DET_INT_MASK (0x1U << VAD_INT_VAD_DET_INT_SHIFT) /* 0x00000010 */ +#define VAD_INT_ERROR_INT_SHIFT (5U) +#define VAD_INT_ERROR_INT_MASK (0x1U << VAD_INT_ERROR_INT_SHIFT) /* 0x00000020 */ +#define VAD_INT_IDLE_TIMEOUT_INT_SHIFT (6U) +#define VAD_INT_IDLE_TIMEOUT_INT_MASK (0x1U << VAD_INT_IDLE_TIMEOUT_INT_SHIFT) /* 0x00000040 */ +#define VAD_INT_WORK_TIMEOUT_INT_SHIFT (7U) +#define VAD_INT_WORK_TIMEOUT_INT_MASK (0x1U << VAD_INT_WORK_TIMEOUT_INT_SHIFT) /* 0x00000080 */ +#define VAD_INT_RAMP_LOOP_FLAG_SHIFT (8U) +#define VAD_INT_RAMP_LOOP_FLAG_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_SHIFT) /* 0x00000100 */ +#define VAD_INT_VAD_IDLE_SHIFT (9U) +#define VAD_INT_VAD_IDLE_MASK (0x1U << VAD_INT_VAD_IDLE_SHIFT) /* 0x00000200 */ +#define VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT (10U) +#define VAD_INT_VAD_DATA_TRANS_INT_EN_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_EN_SHIFT) /* 0x00000400 */ +#define VAD_INT_VAD_DATA_TRANS_INT_SHIFT (11U) +#define VAD_INT_VAD_DATA_TRANS_INT_MASK (0x1U << VAD_INT_VAD_DATA_TRANS_INT_SHIFT) /* 0x00000800 */ +#define VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT (12U) +#define VAD_INT_RAMP_LOOP_FLAG_BUS_MASK (0x1U << VAD_INT_RAMP_LOOP_FLAG_BUS_SHIFT) /* 0x00001000 */ +/* AUX_CON0 */ +#define VAD_AUX_CON0_OFFSET (0x78U) +#define VAD_AUX_CON0_BUS_WRITE_EN_SHIFT (0U) +#define VAD_AUX_CON0_BUS_WRITE_EN_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_EN_SHIFT) /* 0x00000001 */ +#define VAD_AUX_CON0_DIS_RAM_ITF_SHIFT (1U) +#define VAD_AUX_CON0_DIS_RAM_ITF_MASK (0x1U << VAD_AUX_CON0_DIS_RAM_ITF_SHIFT) /* 0x00000002 */ +#define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT (2U) +#define VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_MASK (0x1U << VAD_AUX_CON0_DATA_TRANS_TRIG_INT_EN_SHIFT) /* 0x00000004 */ +#define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT (4U) +#define VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_MASK (0xFFU << VAD_AUX_CON0_DATA_TRANS_KBYTE_THD_SHIFT) /* 0x00000FF0 */ +#define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT (12U) +#define VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_ADDR_MODE_SHIFT) /* 0x00001000 */ +#define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT (13U) +#define VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_BUS_WRITE_REWORK_ADDR_MODE_SHIFT) /* 0x00002000 */ +#define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT (14U) +#define VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_MASK (0x1U << VAD_AUX_CON0_RAM_WRITE_REWORK_ADDR_MODE_SHIFT) /* 0x00004000 */ +#define VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT (16U) +#define VAD_AUX_CON0_INT_TRIG_VALID_THD_MASK (0xFFFU << VAD_AUX_CON0_INT_TRIG_VALID_THD_SHIFT) /* 0x0FFF0000 */ +#define VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT (28U) +#define VAD_AUX_CON0_INT_TRIG_CTRL_EN_MASK (0x1U << VAD_AUX_CON0_INT_TRIG_CTRL_EN_SHIFT) /* 0x10000000 */ +#define VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT (29U) +#define VAD_AUX_CON0_SAMPLE_CNT_EN_MASK (0x1U << VAD_AUX_CON0_SAMPLE_CNT_EN_SHIFT) /* 0x20000000 */ +/* SAMPLE_CNT */ +#define VAD_SAMPLE_CNT_OFFSET (0x7CU) +#define VAD_SAMPLE_CNT (0x0U) +#define VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT (0U) +#define VAD_SAMPLE_CNT_SAMPLE_CNT_MASK (0xFFFFFFFFU << VAD_SAMPLE_CNT_SAMPLE_CNT_SHIFT) /* 0xFFFFFFFF */ +/* RAM_START_ADDR_BUS */ +#define VAD_RAM_START_ADDR_BUS_OFFSET (0x80U) +#define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_START_ADDR_BUS_RAM_START_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* RAM_END_ADDR_BUS */ +#define VAD_RAM_END_ADDR_BUS_OFFSET (0x84U) +#define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_END_ADDR_BUS_RAM_BEGIN_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* RAM_CUR_ADDR_BUS */ +#define VAD_RAM_CUR_ADDR_BUS_OFFSET (0x88U) +#define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT (0U) +#define VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_MASK (0xFFFFFFFFU << VAD_RAM_CUR_ADDR_BUS_RAM_CUR_ADDR_BUS_SHIFT) /* 0xFFFFFFFF */ +/* AUX_CON1 */ +#define VAD_AUX_CON1_OFFSET (0x8CU) +#define VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT (0U) +#define VAD_AUX_CON1_DATA_TRANS_WORD_THD_MASK (0xFFFFU << VAD_AUX_CON1_DATA_TRANS_WORD_THD_SHIFT) /* 0x0000FFFF */ +#define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT (16U) +#define VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_MASK (0x1U << VAD_AUX_CON1_DATA_TRANS_INT_MODE_SEL_SHIFT) /* 0x00010000 */ +/* NOISE_FIRST_DATA */ +#define VAD_NOISE_FIRST_DATA_OFFSET (0x100U) +#define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT (0U) +#define VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_MASK (0xFFFFU << VAD_NOISE_FIRST_DATA_NOISE_FIRST_DATA_SHIFT) /* 0x0000FFFF */ +/* NOISE_LAST_DATA */ +#define VAD_NOISE_LAST_DATA_OFFSET (0x2FCU) +#define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT (0U) +#define VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_MASK (0xFFFFU << VAD_NOISE_LAST_DATA_NOISE_LAST_DATA_SHIFT) /* 0x0000FFFF */ +/******************************************DMA*******************************************/ +/* DSR */ +#define DMA_DSR_OFFSET (0x0U) +#define DMA_DSR (0x0U) +#define DMA_DSR_FIELD0000_SHIFT (0U) +#define DMA_DSR_FIELD0000_MASK (0xFU << DMA_DSR_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_DSR_FIELD0002_SHIFT (4U) +#define DMA_DSR_FIELD0002_MASK (0x1FU << DMA_DSR_FIELD0002_SHIFT) /* 0x000001F0 */ +#define DMA_DSR_FIELD0001_SHIFT (9U) +#define DMA_DSR_FIELD0001_MASK (0x1U << DMA_DSR_FIELD0001_SHIFT) /* 0x00000200 */ +/* DPC */ +#define DMA_DPC_OFFSET (0x4U) +#define DMA_DPC (0x0U) +#define DMA_DPC_FIELD0000_SHIFT (0U) +#define DMA_DPC_FIELD0000_MASK (0xFFFFFFFFU << DMA_DPC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTEN */ +#define DMA_INTEN_OFFSET (0x20U) +#define DMA_INTEN_FIELD0000_SHIFT (0U) +#define DMA_INTEN_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTEN_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* EVENT_RIS */ +#define DMA_EVENT_RIS_OFFSET (0x24U) +#define DMA_EVENT_RIS (0x0U) +#define DMA_EVENT_RIS_FIELD0000_SHIFT (0U) +#define DMA_EVENT_RIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_EVENT_RIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTMIS */ +#define DMA_INTMIS_OFFSET (0x28U) +#define DMA_INTMIS (0x0U) +#define DMA_INTMIS_FIELD0000_SHIFT (0U) +#define DMA_INTMIS_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTMIS_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* INTCLR */ +#define DMA_INTCLR_OFFSET (0x2CU) +#define DMA_INTCLR_FIELD0000_SHIFT (0U) +#define DMA_INTCLR_FIELD0000_MASK (0xFFFFFFFFU << DMA_INTCLR_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRD */ +#define DMA_FSRD_OFFSET (0x30U) +#define DMA_FSRD (0x0U) +#define DMA_FSRD_FIELD0000_SHIFT (0U) +#define DMA_FSRD_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRD_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FSRC */ +#define DMA_FSRC_OFFSET (0x34U) +#define DMA_FSRC (0x0U) +#define DMA_FSRC_FIELD0000_SHIFT (0U) +#define DMA_FSRC_FIELD0000_MASK (0xFFFFFFFFU << DMA_FSRC_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* FTRD */ +#define DMA_FTRD_OFFSET (0x38U) +#define DMA_FTRD_FIELD0000_SHIFT (0U) +#define DMA_FTRD_FIELD0000_MASK (0x1U << DMA_FTRD_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTRD_FIELD0005_SHIFT (1U) +#define DMA_FTRD_FIELD0005_MASK (0x1U << DMA_FTRD_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_FTRD_FIELD0004_SHIFT (4U) +#define DMA_FTRD_FIELD0004_MASK (0x1U << DMA_FTRD_FIELD0004_SHIFT) /* 0x00000010 */ +#define DMA_FTRD_FIELD0003_SHIFT (5U) +#define DMA_FTRD_FIELD0003_MASK (0x1U << DMA_FTRD_FIELD0003_SHIFT) /* 0x00000020 */ +#define DMA_FTRD_FIELD0002_SHIFT (16U) +#define DMA_FTRD_FIELD0002_MASK (0x1U << DMA_FTRD_FIELD0002_SHIFT) /* 0x00010000 */ +#define DMA_FTRD_FIELD0001_SHIFT (30U) +#define DMA_FTRD_FIELD0001_MASK (0x1U << DMA_FTRD_FIELD0001_SHIFT) /* 0x40000000 */ +/* FTR0 */ +#define DMA_FTR0_OFFSET (0x40U) +#define DMA_FTR0 (0x0U) +#define DMA_FTR0_FIELD0000_SHIFT (0U) +#define DMA_FTR0_FIELD0000_MASK (0x1U << DMA_FTR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR0_FIELD0011_SHIFT (1U) +#define DMA_FTR0_FIELD0011_MASK (0x1U << DMA_FTR0_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR0_FIELD0010_SHIFT (5U) +#define DMA_FTR0_FIELD0010_MASK (0x1U << DMA_FTR0_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR0_FIELD0009_SHIFT (6U) +#define DMA_FTR0_FIELD0009_MASK (0x1U << DMA_FTR0_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR0_FIELD0008_SHIFT (7U) +#define DMA_FTR0_FIELD0008_MASK (0x1U << DMA_FTR0_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR0_FIELD0007_SHIFT (12U) +#define DMA_FTR0_FIELD0007_MASK (0x1U << DMA_FTR0_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR0_FIELD0006_SHIFT (13U) +#define DMA_FTR0_FIELD0006_MASK (0x1U << DMA_FTR0_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR0_FIELD0005_SHIFT (16U) +#define DMA_FTR0_FIELD0005_MASK (0x1U << DMA_FTR0_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR0_FIELD0004_SHIFT (17U) +#define DMA_FTR0_FIELD0004_MASK (0x1U << DMA_FTR0_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR0_FIELD0003_SHIFT (18U) +#define DMA_FTR0_FIELD0003_MASK (0x1U << DMA_FTR0_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR0_FIELD0002_SHIFT (30U) +#define DMA_FTR0_FIELD0002_MASK (0x1U << DMA_FTR0_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR0_FIELD0001_SHIFT (31U) +#define DMA_FTR0_FIELD0001_MASK (0x1U << DMA_FTR0_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR1 */ +#define DMA_FTR1_OFFSET (0x44U) +#define DMA_FTR1 (0x0U) +#define DMA_FTR1_FIELD0000_SHIFT (0U) +#define DMA_FTR1_FIELD0000_MASK (0x1U << DMA_FTR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR1_FIELD0011_SHIFT (1U) +#define DMA_FTR1_FIELD0011_MASK (0x1U << DMA_FTR1_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR1_FIELD0010_SHIFT (5U) +#define DMA_FTR1_FIELD0010_MASK (0x1U << DMA_FTR1_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR1_FIELD0009_SHIFT (6U) +#define DMA_FTR1_FIELD0009_MASK (0x1U << DMA_FTR1_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR1_FIELD0008_SHIFT (7U) +#define DMA_FTR1_FIELD0008_MASK (0x1U << DMA_FTR1_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR1_FIELD0007_SHIFT (12U) +#define DMA_FTR1_FIELD0007_MASK (0x1U << DMA_FTR1_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR1_FIELD0006_SHIFT (13U) +#define DMA_FTR1_FIELD0006_MASK (0x1U << DMA_FTR1_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR1_FIELD0005_SHIFT (16U) +#define DMA_FTR1_FIELD0005_MASK (0x1U << DMA_FTR1_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR1_FIELD0004_SHIFT (17U) +#define DMA_FTR1_FIELD0004_MASK (0x1U << DMA_FTR1_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR1_FIELD0003_SHIFT (18U) +#define DMA_FTR1_FIELD0003_MASK (0x1U << DMA_FTR1_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR1_FIELD0002_SHIFT (30U) +#define DMA_FTR1_FIELD0002_MASK (0x1U << DMA_FTR1_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR1_FIELD0001_SHIFT (31U) +#define DMA_FTR1_FIELD0001_MASK (0x1U << DMA_FTR1_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR2 */ +#define DMA_FTR2_OFFSET (0x48U) +#define DMA_FTR2 (0x0U) +#define DMA_FTR2_FIELD0000_SHIFT (0U) +#define DMA_FTR2_FIELD0000_MASK (0x1U << DMA_FTR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR2_FIELD0011_SHIFT (1U) +#define DMA_FTR2_FIELD0011_MASK (0x1U << DMA_FTR2_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR2_FIELD0010_SHIFT (5U) +#define DMA_FTR2_FIELD0010_MASK (0x1U << DMA_FTR2_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR2_FIELD0009_SHIFT (6U) +#define DMA_FTR2_FIELD0009_MASK (0x1U << DMA_FTR2_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR2_FIELD0008_SHIFT (7U) +#define DMA_FTR2_FIELD0008_MASK (0x1U << DMA_FTR2_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR2_FIELD0007_SHIFT (12U) +#define DMA_FTR2_FIELD0007_MASK (0x1U << DMA_FTR2_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR2_FIELD0006_SHIFT (13U) +#define DMA_FTR2_FIELD0006_MASK (0x1U << DMA_FTR2_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR2_FIELD0005_SHIFT (16U) +#define DMA_FTR2_FIELD0005_MASK (0x1U << DMA_FTR2_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR2_FIELD0004_SHIFT (17U) +#define DMA_FTR2_FIELD0004_MASK (0x1U << DMA_FTR2_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR2_FIELD0003_SHIFT (18U) +#define DMA_FTR2_FIELD0003_MASK (0x1U << DMA_FTR2_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR2_FIELD0002_SHIFT (30U) +#define DMA_FTR2_FIELD0002_MASK (0x1U << DMA_FTR2_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR2_FIELD0001_SHIFT (31U) +#define DMA_FTR2_FIELD0001_MASK (0x1U << DMA_FTR2_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR3 */ +#define DMA_FTR3_OFFSET (0x4CU) +#define DMA_FTR3 (0x0U) +#define DMA_FTR3_FIELD0000_SHIFT (0U) +#define DMA_FTR3_FIELD0000_MASK (0x1U << DMA_FTR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR3_FIELD0011_SHIFT (1U) +#define DMA_FTR3_FIELD0011_MASK (0x1U << DMA_FTR3_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR3_FIELD0010_SHIFT (5U) +#define DMA_FTR3_FIELD0010_MASK (0x1U << DMA_FTR3_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR3_FIELD0009_SHIFT (6U) +#define DMA_FTR3_FIELD0009_MASK (0x1U << DMA_FTR3_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR3_FIELD0008_SHIFT (7U) +#define DMA_FTR3_FIELD0008_MASK (0x1U << DMA_FTR3_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR3_FIELD0007_SHIFT (12U) +#define DMA_FTR3_FIELD0007_MASK (0x1U << DMA_FTR3_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR3_FIELD0006_SHIFT (13U) +#define DMA_FTR3_FIELD0006_MASK (0x1U << DMA_FTR3_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR3_FIELD0005_SHIFT (16U) +#define DMA_FTR3_FIELD0005_MASK (0x1U << DMA_FTR3_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR3_FIELD0004_SHIFT (17U) +#define DMA_FTR3_FIELD0004_MASK (0x1U << DMA_FTR3_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR3_FIELD0003_SHIFT (18U) +#define DMA_FTR3_FIELD0003_MASK (0x1U << DMA_FTR3_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR3_FIELD0002_SHIFT (30U) +#define DMA_FTR3_FIELD0002_MASK (0x1U << DMA_FTR3_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR3_FIELD0001_SHIFT (31U) +#define DMA_FTR3_FIELD0001_MASK (0x1U << DMA_FTR3_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR4 */ +#define DMA_FTR4_OFFSET (0x50U) +#define DMA_FTR4 (0x0U) +#define DMA_FTR4_FIELD0000_SHIFT (0U) +#define DMA_FTR4_FIELD0000_MASK (0x1U << DMA_FTR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR4_FIELD0011_SHIFT (1U) +#define DMA_FTR4_FIELD0011_MASK (0x1U << DMA_FTR4_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR4_FIELD0010_SHIFT (5U) +#define DMA_FTR4_FIELD0010_MASK (0x1U << DMA_FTR4_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR4_FIELD0009_SHIFT (6U) +#define DMA_FTR4_FIELD0009_MASK (0x1U << DMA_FTR4_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR4_FIELD0008_SHIFT (7U) +#define DMA_FTR4_FIELD0008_MASK (0x1U << DMA_FTR4_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR4_FIELD0007_SHIFT (12U) +#define DMA_FTR4_FIELD0007_MASK (0x1U << DMA_FTR4_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR4_FIELD0006_SHIFT (13U) +#define DMA_FTR4_FIELD0006_MASK (0x1U << DMA_FTR4_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR4_FIELD0005_SHIFT (16U) +#define DMA_FTR4_FIELD0005_MASK (0x1U << DMA_FTR4_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR4_FIELD0004_SHIFT (17U) +#define DMA_FTR4_FIELD0004_MASK (0x1U << DMA_FTR4_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR4_FIELD0003_SHIFT (18U) +#define DMA_FTR4_FIELD0003_MASK (0x1U << DMA_FTR4_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR4_FIELD0002_SHIFT (30U) +#define DMA_FTR4_FIELD0002_MASK (0x1U << DMA_FTR4_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR4_FIELD0001_SHIFT (31U) +#define DMA_FTR4_FIELD0001_MASK (0x1U << DMA_FTR4_FIELD0001_SHIFT) /* 0x80000000 */ +/* FTR5 */ +#define DMA_FTR5_OFFSET (0x54U) +#define DMA_FTR5 (0x0U) +#define DMA_FTR5_FIELD0000_SHIFT (0U) +#define DMA_FTR5_FIELD0000_MASK (0x1U << DMA_FTR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_FTR5_FIELD0011_SHIFT (1U) +#define DMA_FTR5_FIELD0011_MASK (0x1U << DMA_FTR5_FIELD0011_SHIFT) /* 0x00000002 */ +#define DMA_FTR5_FIELD0010_SHIFT (5U) +#define DMA_FTR5_FIELD0010_MASK (0x1U << DMA_FTR5_FIELD0010_SHIFT) /* 0x00000020 */ +#define DMA_FTR5_FIELD0009_SHIFT (6U) +#define DMA_FTR5_FIELD0009_MASK (0x1U << DMA_FTR5_FIELD0009_SHIFT) /* 0x00000040 */ +#define DMA_FTR5_FIELD0008_SHIFT (7U) +#define DMA_FTR5_FIELD0008_MASK (0x1U << DMA_FTR5_FIELD0008_SHIFT) /* 0x00000080 */ +#define DMA_FTR5_FIELD0007_SHIFT (12U) +#define DMA_FTR5_FIELD0007_MASK (0x1U << DMA_FTR5_FIELD0007_SHIFT) /* 0x00001000 */ +#define DMA_FTR5_FIELD0006_SHIFT (13U) +#define DMA_FTR5_FIELD0006_MASK (0x1U << DMA_FTR5_FIELD0006_SHIFT) /* 0x00002000 */ +#define DMA_FTR5_FIELD0005_SHIFT (16U) +#define DMA_FTR5_FIELD0005_MASK (0x1U << DMA_FTR5_FIELD0005_SHIFT) /* 0x00010000 */ +#define DMA_FTR5_FIELD0004_SHIFT (17U) +#define DMA_FTR5_FIELD0004_MASK (0x1U << DMA_FTR5_FIELD0004_SHIFT) /* 0x00020000 */ +#define DMA_FTR5_FIELD0003_SHIFT (18U) +#define DMA_FTR5_FIELD0003_MASK (0x1U << DMA_FTR5_FIELD0003_SHIFT) /* 0x00040000 */ +#define DMA_FTR5_FIELD0002_SHIFT (30U) +#define DMA_FTR5_FIELD0002_MASK (0x1U << DMA_FTR5_FIELD0002_SHIFT) /* 0x40000000 */ +#define DMA_FTR5_FIELD0001_SHIFT (31U) +#define DMA_FTR5_FIELD0001_MASK (0x1U << DMA_FTR5_FIELD0001_SHIFT) /* 0x80000000 */ +/* CSR0 */ +#define DMA_CSR0_OFFSET (0x100U) +#define DMA_CSR0 (0x0U) +#define DMA_CSR0_FIELD0000_SHIFT (0U) +#define DMA_CSR0_FIELD0000_MASK (0xFU << DMA_CSR0_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR0_FIELD0004_SHIFT (4U) +#define DMA_CSR0_FIELD0004_MASK (0x1FU << DMA_CSR0_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR0_FIELD0003_SHIFT (14U) +#define DMA_CSR0_FIELD0003_MASK (0x1U << DMA_CSR0_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR0_FIELD0002_SHIFT (15U) +#define DMA_CSR0_FIELD0002_MASK (0x1U << DMA_CSR0_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR0_FIELD0001_SHIFT (21U) +#define DMA_CSR0_FIELD0001_MASK (0x1U << DMA_CSR0_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC0 */ +#define DMA_CPC0_OFFSET (0x104U) +#define DMA_CPC0 (0x0U) +#define DMA_CPC0_FIELD0000_SHIFT (0U) +#define DMA_CPC0_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR1 */ +#define DMA_CSR1_OFFSET (0x108U) +#define DMA_CSR1 (0x0U) +#define DMA_CSR1_FIELD0000_SHIFT (0U) +#define DMA_CSR1_FIELD0000_MASK (0xFU << DMA_CSR1_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR1_FIELD0004_SHIFT (4U) +#define DMA_CSR1_FIELD0004_MASK (0x1FU << DMA_CSR1_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR1_FIELD0003_SHIFT (14U) +#define DMA_CSR1_FIELD0003_MASK (0x1U << DMA_CSR1_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR1_FIELD0002_SHIFT (15U) +#define DMA_CSR1_FIELD0002_MASK (0x1U << DMA_CSR1_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR1_FIELD0001_SHIFT (21U) +#define DMA_CSR1_FIELD0001_MASK (0x1U << DMA_CSR1_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC1 */ +#define DMA_CPC1_OFFSET (0x10CU) +#define DMA_CPC1 (0x0U) +#define DMA_CPC1_FIELD0000_SHIFT (0U) +#define DMA_CPC1_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR2 */ +#define DMA_CSR2_OFFSET (0x110U) +#define DMA_CSR2 (0x0U) +#define DMA_CSR2_FIELD0000_SHIFT (0U) +#define DMA_CSR2_FIELD0000_MASK (0xFU << DMA_CSR2_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR2_FIELD0004_SHIFT (4U) +#define DMA_CSR2_FIELD0004_MASK (0x1FU << DMA_CSR2_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR2_FIELD0003_SHIFT (14U) +#define DMA_CSR2_FIELD0003_MASK (0x1U << DMA_CSR2_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR2_FIELD0002_SHIFT (15U) +#define DMA_CSR2_FIELD0002_MASK (0x1U << DMA_CSR2_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR2_FIELD0001_SHIFT (21U) +#define DMA_CSR2_FIELD0001_MASK (0x1U << DMA_CSR2_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC2 */ +#define DMA_CPC2_OFFSET (0x114U) +#define DMA_CPC2 (0x0U) +#define DMA_CPC2_FIELD0000_SHIFT (0U) +#define DMA_CPC2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR3 */ +#define DMA_CSR3_OFFSET (0x118U) +#define DMA_CSR3 (0x0U) +#define DMA_CSR3_FIELD0000_SHIFT (0U) +#define DMA_CSR3_FIELD0000_MASK (0xFU << DMA_CSR3_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR3_FIELD0004_SHIFT (4U) +#define DMA_CSR3_FIELD0004_MASK (0x1FU << DMA_CSR3_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR3_FIELD0003_SHIFT (14U) +#define DMA_CSR3_FIELD0003_MASK (0x1U << DMA_CSR3_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR3_FIELD0002_SHIFT (15U) +#define DMA_CSR3_FIELD0002_MASK (0x1U << DMA_CSR3_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR3_FIELD0001_SHIFT (21U) +#define DMA_CSR3_FIELD0001_MASK (0x1U << DMA_CSR3_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC3 */ +#define DMA_CPC3_OFFSET (0x11CU) +#define DMA_CPC3 (0x0U) +#define DMA_CPC3_FIELD0000_SHIFT (0U) +#define DMA_CPC3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR4 */ +#define DMA_CSR4_OFFSET (0x120U) +#define DMA_CSR4 (0x0U) +#define DMA_CSR4_FIELD0000_SHIFT (0U) +#define DMA_CSR4_FIELD0000_MASK (0xFU << DMA_CSR4_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR4_FIELD0004_SHIFT (4U) +#define DMA_CSR4_FIELD0004_MASK (0x1FU << DMA_CSR4_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR4_FIELD0003_SHIFT (14U) +#define DMA_CSR4_FIELD0003_MASK (0x1U << DMA_CSR4_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR4_FIELD0002_SHIFT (15U) +#define DMA_CSR4_FIELD0002_MASK (0x1U << DMA_CSR4_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR4_FIELD0001_SHIFT (21U) +#define DMA_CSR4_FIELD0001_MASK (0x1U << DMA_CSR4_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC4 */ +#define DMA_CPC4_OFFSET (0x124U) +#define DMA_CPC4 (0x0U) +#define DMA_CPC4_FIELD0000_SHIFT (0U) +#define DMA_CPC4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CSR5 */ +#define DMA_CSR5_OFFSET (0x128U) +#define DMA_CSR5 (0x0U) +#define DMA_CSR5_FIELD0000_SHIFT (0U) +#define DMA_CSR5_FIELD0000_MASK (0xFU << DMA_CSR5_FIELD0000_SHIFT) /* 0x0000000F */ +#define DMA_CSR5_FIELD0004_SHIFT (4U) +#define DMA_CSR5_FIELD0004_MASK (0x1FU << DMA_CSR5_FIELD0004_SHIFT) /* 0x000001F0 */ +#define DMA_CSR5_FIELD0003_SHIFT (14U) +#define DMA_CSR5_FIELD0003_MASK (0x1U << DMA_CSR5_FIELD0003_SHIFT) /* 0x00004000 */ +#define DMA_CSR5_FIELD0002_SHIFT (15U) +#define DMA_CSR5_FIELD0002_MASK (0x1U << DMA_CSR5_FIELD0002_SHIFT) /* 0x00008000 */ +#define DMA_CSR5_FIELD0001_SHIFT (21U) +#define DMA_CSR5_FIELD0001_MASK (0x1U << DMA_CSR5_FIELD0001_SHIFT) /* 0x00200000 */ +/* CPC5 */ +#define DMA_CPC5_OFFSET (0x12CU) +#define DMA_CPC5 (0x0U) +#define DMA_CPC5_FIELD0000_SHIFT (0U) +#define DMA_CPC5_FIELD0000_MASK (0xFFFFFFFFU << DMA_CPC5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* SAR0 */ +#define DMA_SAR0_OFFSET (0x400U) +#define DMA_SAR0 (0x0U) +#define DMA_SAR0_FIELD0000_SHIFT (0U) +#define DMA_SAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR0 */ +#define DMA_DAR0_OFFSET (0x404U) +#define DMA_DAR0 (0x0U) +#define DMA_DAR0_FIELD0000_SHIFT (0U) +#define DMA_DAR0_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR0_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR0 */ +#define DMA_CCR0_OFFSET (0x408U) +#define DMA_CCR0 (0x0U) +#define DMA_CCR0_FIELD0000_SHIFT (0U) +#define DMA_CCR0_FIELD0000_MASK (0x1U << DMA_CCR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR0_FIELD0009_SHIFT (1U) +#define DMA_CCR0_FIELD0009_MASK (0x7U << DMA_CCR0_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR0_FIELD0008_SHIFT (4U) +#define DMA_CCR0_FIELD0008_MASK (0xFU << DMA_CCR0_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR0_FIELD0007_SHIFT (8U) +#define DMA_CCR0_FIELD0007_MASK (0x7U << DMA_CCR0_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR0_FIELD0006_SHIFT (11U) +#define DMA_CCR0_FIELD0006_MASK (0x7U << DMA_CCR0_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR0_FIELD0005_SHIFT (14U) +#define DMA_CCR0_FIELD0005_MASK (0x1U << DMA_CCR0_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR0_FIELD0004_SHIFT (15U) +#define DMA_CCR0_FIELD0004_MASK (0x7U << DMA_CCR0_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR0_FIELD0003_SHIFT (18U) +#define DMA_CCR0_FIELD0003_MASK (0xFU << DMA_CCR0_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR0_FIELD0002_SHIFT (22U) +#define DMA_CCR0_FIELD0002_MASK (0x7U << DMA_CCR0_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR0_FIELD0001_SHIFT (25U) +#define DMA_CCR0_FIELD0001_MASK (0x7U << DMA_CCR0_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_0 */ +#define DMA_LC0_0_OFFSET (0x40CU) +#define DMA_LC0_0 (0x0U) +#define DMA_LC0_0_FIELD0000_SHIFT (0U) +#define DMA_LC0_0_FIELD0000_MASK (0xFFU << DMA_LC0_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_0 */ +#define DMA_LC1_0_OFFSET (0x410U) +#define DMA_LC1_0 (0x0U) +#define DMA_LC1_0_FIELD0000_SHIFT (0U) +#define DMA_LC1_0_FIELD0000_MASK (0xFFU << DMA_LC1_0_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING0_0 */ +#define DMA_PADDING0_0_OFFSET (0x414U) +/* PADDING0_1 */ +#define DMA_PADDING0_1_OFFSET (0x418U) +/* PADDING0_2 */ +#define DMA_PADDING0_2_OFFSET (0x41CU) +/* SAR1 */ +#define DMA_SAR1_OFFSET (0x420U) +#define DMA_SAR1 (0x0U) +#define DMA_SAR1_FIELD0000_SHIFT (0U) +#define DMA_SAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR1 */ +#define DMA_DAR1_OFFSET (0x424U) +#define DMA_DAR1 (0x0U) +#define DMA_DAR1_FIELD0000_SHIFT (0U) +#define DMA_DAR1_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR1_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR1 */ +#define DMA_CCR1_OFFSET (0x428U) +#define DMA_CCR1 (0x0U) +#define DMA_CCR1_FIELD0000_SHIFT (0U) +#define DMA_CCR1_FIELD0000_MASK (0x1U << DMA_CCR1_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR1_FIELD0009_SHIFT (1U) +#define DMA_CCR1_FIELD0009_MASK (0x7U << DMA_CCR1_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR1_FIELD0008_SHIFT (4U) +#define DMA_CCR1_FIELD0008_MASK (0xFU << DMA_CCR1_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR1_FIELD0007_SHIFT (8U) +#define DMA_CCR1_FIELD0007_MASK (0x7U << DMA_CCR1_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR1_FIELD0006_SHIFT (11U) +#define DMA_CCR1_FIELD0006_MASK (0x7U << DMA_CCR1_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR1_FIELD0005_SHIFT (14U) +#define DMA_CCR1_FIELD0005_MASK (0x1U << DMA_CCR1_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR1_FIELD0004_SHIFT (15U) +#define DMA_CCR1_FIELD0004_MASK (0x7U << DMA_CCR1_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR1_FIELD0003_SHIFT (18U) +#define DMA_CCR1_FIELD0003_MASK (0xFU << DMA_CCR1_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR1_FIELD0002_SHIFT (22U) +#define DMA_CCR1_FIELD0002_MASK (0x7U << DMA_CCR1_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR1_FIELD0001_SHIFT (25U) +#define DMA_CCR1_FIELD0001_MASK (0x7U << DMA_CCR1_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_1 */ +#define DMA_LC0_1_OFFSET (0x42CU) +#define DMA_LC0_1 (0x0U) +#define DMA_LC0_1_FIELD0000_SHIFT (0U) +#define DMA_LC0_1_FIELD0000_MASK (0xFFU << DMA_LC0_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_1 */ +#define DMA_LC1_1_OFFSET (0x430U) +#define DMA_LC1_1 (0x0U) +#define DMA_LC1_1_FIELD0000_SHIFT (0U) +#define DMA_LC1_1_FIELD0000_MASK (0xFFU << DMA_LC1_1_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING1_0 */ +#define DMA_PADDING1_0_OFFSET (0x434U) +/* PADDING1_1 */ +#define DMA_PADDING1_1_OFFSET (0x438U) +/* PADDING1_2 */ +#define DMA_PADDING1_2_OFFSET (0x43CU) +/* SAR2 */ +#define DMA_SAR2_OFFSET (0x440U) +#define DMA_SAR2 (0x0U) +#define DMA_SAR2_FIELD0000_SHIFT (0U) +#define DMA_SAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR2 */ +#define DMA_DAR2_OFFSET (0x444U) +#define DMA_DAR2 (0x0U) +#define DMA_DAR2_FIELD0000_SHIFT (0U) +#define DMA_DAR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR2 */ +#define DMA_CCR2_OFFSET (0x448U) +#define DMA_CCR2 (0x0U) +#define DMA_CCR2_FIELD0000_SHIFT (0U) +#define DMA_CCR2_FIELD0000_MASK (0x1U << DMA_CCR2_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR2_FIELD0009_SHIFT (1U) +#define DMA_CCR2_FIELD0009_MASK (0x7U << DMA_CCR2_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR2_FIELD0008_SHIFT (4U) +#define DMA_CCR2_FIELD0008_MASK (0xFU << DMA_CCR2_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR2_FIELD0007_SHIFT (8U) +#define DMA_CCR2_FIELD0007_MASK (0x7U << DMA_CCR2_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR2_FIELD0006_SHIFT (11U) +#define DMA_CCR2_FIELD0006_MASK (0x7U << DMA_CCR2_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR2_FIELD0005_SHIFT (14U) +#define DMA_CCR2_FIELD0005_MASK (0x1U << DMA_CCR2_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR2_FIELD0004_SHIFT (15U) +#define DMA_CCR2_FIELD0004_MASK (0x7U << DMA_CCR2_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR2_FIELD0003_SHIFT (18U) +#define DMA_CCR2_FIELD0003_MASK (0xFU << DMA_CCR2_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR2_FIELD0002_SHIFT (22U) +#define DMA_CCR2_FIELD0002_MASK (0x7U << DMA_CCR2_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR2_FIELD0001_SHIFT (25U) +#define DMA_CCR2_FIELD0001_MASK (0x7U << DMA_CCR2_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_2 */ +#define DMA_LC0_2_OFFSET (0x44CU) +#define DMA_LC0_2 (0x0U) +#define DMA_LC0_2_FIELD0000_SHIFT (0U) +#define DMA_LC0_2_FIELD0000_MASK (0xFFU << DMA_LC0_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_2 */ +#define DMA_LC1_2_OFFSET (0x450U) +#define DMA_LC1_2 (0x0U) +#define DMA_LC1_2_FIELD0000_SHIFT (0U) +#define DMA_LC1_2_FIELD0000_MASK (0xFFU << DMA_LC1_2_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING2_0 */ +#define DMA_PADDING2_0_OFFSET (0x454U) +/* PADDING2_1 */ +#define DMA_PADDING2_1_OFFSET (0x458U) +/* PADDING2_2 */ +#define DMA_PADDING2_2_OFFSET (0x45CU) +/* SAR3 */ +#define DMA_SAR3_OFFSET (0x460U) +#define DMA_SAR3 (0x0U) +#define DMA_SAR3_FIELD0000_SHIFT (0U) +#define DMA_SAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR3 */ +#define DMA_DAR3_OFFSET (0x464U) +#define DMA_DAR3 (0x0U) +#define DMA_DAR3_FIELD0000_SHIFT (0U) +#define DMA_DAR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR3 */ +#define DMA_CCR3_OFFSET (0x468U) +#define DMA_CCR3 (0x0U) +#define DMA_CCR3_FIELD0000_SHIFT (0U) +#define DMA_CCR3_FIELD0000_MASK (0x1U << DMA_CCR3_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR3_FIELD0009_SHIFT (1U) +#define DMA_CCR3_FIELD0009_MASK (0x7U << DMA_CCR3_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR3_FIELD0008_SHIFT (4U) +#define DMA_CCR3_FIELD0008_MASK (0xFU << DMA_CCR3_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR3_FIELD0007_SHIFT (8U) +#define DMA_CCR3_FIELD0007_MASK (0x7U << DMA_CCR3_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR3_FIELD0006_SHIFT (11U) +#define DMA_CCR3_FIELD0006_MASK (0x7U << DMA_CCR3_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR3_FIELD0005_SHIFT (14U) +#define DMA_CCR3_FIELD0005_MASK (0x1U << DMA_CCR3_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR3_FIELD0004_SHIFT (15U) +#define DMA_CCR3_FIELD0004_MASK (0x7U << DMA_CCR3_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR3_FIELD0003_SHIFT (18U) +#define DMA_CCR3_FIELD0003_MASK (0xFU << DMA_CCR3_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR3_FIELD0002_SHIFT (22U) +#define DMA_CCR3_FIELD0002_MASK (0x7U << DMA_CCR3_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR3_FIELD0001_SHIFT (25U) +#define DMA_CCR3_FIELD0001_MASK (0x7U << DMA_CCR3_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_3 */ +#define DMA_LC0_3_OFFSET (0x46CU) +#define DMA_LC0_3 (0x0U) +#define DMA_LC0_3_FIELD0000_SHIFT (0U) +#define DMA_LC0_3_FIELD0000_MASK (0xFFU << DMA_LC0_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_3 */ +#define DMA_LC1_3_OFFSET (0x470U) +#define DMA_LC1_3 (0x0U) +#define DMA_LC1_3_FIELD0000_SHIFT (0U) +#define DMA_LC1_3_FIELD0000_MASK (0xFFU << DMA_LC1_3_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING3_0 */ +#define DMA_PADDING3_0_OFFSET (0x474U) +/* PADDING3_1 */ +#define DMA_PADDING3_1_OFFSET (0x478U) +/* PADDING3_2 */ +#define DMA_PADDING3_2_OFFSET (0x47CU) +/* SAR4 */ +#define DMA_SAR4_OFFSET (0x480U) +#define DMA_SAR4 (0x0U) +#define DMA_SAR4_FIELD0000_SHIFT (0U) +#define DMA_SAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR4 */ +#define DMA_DAR4_OFFSET (0x484U) +#define DMA_DAR4 (0x0U) +#define DMA_DAR4_FIELD0000_SHIFT (0U) +#define DMA_DAR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR4 */ +#define DMA_CCR4_OFFSET (0x488U) +#define DMA_CCR4 (0x0U) +#define DMA_CCR4_FIELD0000_SHIFT (0U) +#define DMA_CCR4_FIELD0000_MASK (0x1U << DMA_CCR4_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR4_FIELD0009_SHIFT (1U) +#define DMA_CCR4_FIELD0009_MASK (0x7U << DMA_CCR4_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR4_FIELD0008_SHIFT (4U) +#define DMA_CCR4_FIELD0008_MASK (0xFU << DMA_CCR4_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR4_FIELD0007_SHIFT (8U) +#define DMA_CCR4_FIELD0007_MASK (0x7U << DMA_CCR4_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR4_FIELD0006_SHIFT (11U) +#define DMA_CCR4_FIELD0006_MASK (0x7U << DMA_CCR4_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR4_FIELD0005_SHIFT (14U) +#define DMA_CCR4_FIELD0005_MASK (0x1U << DMA_CCR4_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR4_FIELD0004_SHIFT (15U) +#define DMA_CCR4_FIELD0004_MASK (0x7U << DMA_CCR4_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR4_FIELD0003_SHIFT (18U) +#define DMA_CCR4_FIELD0003_MASK (0xFU << DMA_CCR4_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR4_FIELD0002_SHIFT (22U) +#define DMA_CCR4_FIELD0002_MASK (0x7U << DMA_CCR4_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR4_FIELD0001_SHIFT (25U) +#define DMA_CCR4_FIELD0001_MASK (0x7U << DMA_CCR4_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_4 */ +#define DMA_LC0_4_OFFSET (0x48CU) +#define DMA_LC0_4 (0x0U) +#define DMA_LC0_4_FIELD0000_SHIFT (0U) +#define DMA_LC0_4_FIELD0000_MASK (0xFFU << DMA_LC0_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_4 */ +#define DMA_LC1_4_OFFSET (0x490U) +#define DMA_LC1_4 (0x0U) +#define DMA_LC1_4_FIELD0000_SHIFT (0U) +#define DMA_LC1_4_FIELD0000_MASK (0xFFU << DMA_LC1_4_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING4_0 */ +#define DMA_PADDING4_0_OFFSET (0x494U) +/* PADDING4_1 */ +#define DMA_PADDING4_1_OFFSET (0x498U) +/* PADDING4_2 */ +#define DMA_PADDING4_2_OFFSET (0x49CU) +/* SAR5 */ +#define DMA_SAR5_OFFSET (0x4A0U) +#define DMA_SAR5 (0x0U) +#define DMA_SAR5_FIELD0000_SHIFT (0U) +#define DMA_SAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_SAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* DAR5 */ +#define DMA_DAR5_OFFSET (0x4A4U) +#define DMA_DAR5 (0x0U) +#define DMA_DAR5_FIELD0000_SHIFT (0U) +#define DMA_DAR5_FIELD0000_MASK (0xFFFFFFFFU << DMA_DAR5_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CCR5 */ +#define DMA_CCR5_OFFSET (0x4A8U) +#define DMA_CCR5 (0x0U) +#define DMA_CCR5_FIELD0000_SHIFT (0U) +#define DMA_CCR5_FIELD0000_MASK (0x1U << DMA_CCR5_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CCR5_FIELD0009_SHIFT (1U) +#define DMA_CCR5_FIELD0009_MASK (0x7U << DMA_CCR5_FIELD0009_SHIFT) /* 0x0000000E */ +#define DMA_CCR5_FIELD0008_SHIFT (4U) +#define DMA_CCR5_FIELD0008_MASK (0xFU << DMA_CCR5_FIELD0008_SHIFT) /* 0x000000F0 */ +#define DMA_CCR5_FIELD0007_SHIFT (8U) +#define DMA_CCR5_FIELD0007_MASK (0x7U << DMA_CCR5_FIELD0007_SHIFT) /* 0x00000700 */ +#define DMA_CCR5_FIELD0006_SHIFT (11U) +#define DMA_CCR5_FIELD0006_MASK (0x7U << DMA_CCR5_FIELD0006_SHIFT) /* 0x00003800 */ +#define DMA_CCR5_FIELD0005_SHIFT (14U) +#define DMA_CCR5_FIELD0005_MASK (0x1U << DMA_CCR5_FIELD0005_SHIFT) /* 0x00004000 */ +#define DMA_CCR5_FIELD0004_SHIFT (15U) +#define DMA_CCR5_FIELD0004_MASK (0x7U << DMA_CCR5_FIELD0004_SHIFT) /* 0x00038000 */ +#define DMA_CCR5_FIELD0003_SHIFT (18U) +#define DMA_CCR5_FIELD0003_MASK (0xFU << DMA_CCR5_FIELD0003_SHIFT) /* 0x003C0000 */ +#define DMA_CCR5_FIELD0002_SHIFT (22U) +#define DMA_CCR5_FIELD0002_MASK (0x7U << DMA_CCR5_FIELD0002_SHIFT) /* 0x01C00000 */ +#define DMA_CCR5_FIELD0001_SHIFT (25U) +#define DMA_CCR5_FIELD0001_MASK (0x7U << DMA_CCR5_FIELD0001_SHIFT) /* 0x0E000000 */ +/* LC0_5 */ +#define DMA_LC0_5_OFFSET (0x4ACU) +#define DMA_LC0_5 (0x0U) +#define DMA_LC0_5_FIELD0000_SHIFT (0U) +#define DMA_LC0_5_FIELD0000_MASK (0xFFU << DMA_LC0_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* LC1_5 */ +#define DMA_LC1_5_OFFSET (0x4B0U) +#define DMA_LC1_5 (0x0U) +#define DMA_LC1_5_FIELD0000_SHIFT (0U) +#define DMA_LC1_5_FIELD0000_MASK (0xFFU << DMA_LC1_5_FIELD0000_SHIFT) /* 0x000000FF */ +/* PADDING5_0 */ +#define DMA_PADDING5_0_OFFSET (0x4B4U) +/* PADDING5_1 */ +#define DMA_PADDING5_1_OFFSET (0x4B8U) +/* PADDING5_2 */ +#define DMA_PADDING5_2_OFFSET (0x4BCU) +/* DBGSTATUS */ +#define DMA_DBGSTATUS_OFFSET (0xD00U) +#define DMA_DBGSTATUS (0x0U) +#define DMA_DBGSTATUS_FIELD0000_SHIFT (0U) +#define DMA_DBGSTATUS_FIELD0000_MASK (0x3U << DMA_DBGSTATUS_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGCMD */ +#define DMA_DBGCMD_OFFSET (0xD04U) +#define DMA_DBGCMD_FIELD0000_SHIFT (0U) +#define DMA_DBGCMD_FIELD0000_MASK (0x3U << DMA_DBGCMD_FIELD0000_SHIFT) /* 0x00000003 */ +/* DBGINST0 */ +#define DMA_DBGINST0_OFFSET (0xD08U) +#define DMA_DBGINST0_FIELD0000_SHIFT (0U) +#define DMA_DBGINST0_FIELD0000_MASK (0x1U << DMA_DBGINST0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_DBGINST0_FIELD0003_SHIFT (8U) +#define DMA_DBGINST0_FIELD0003_MASK (0x7U << DMA_DBGINST0_FIELD0003_SHIFT) /* 0x00000700 */ +#define DMA_DBGINST0_FIELD0002_SHIFT (16U) +#define DMA_DBGINST0_FIELD0002_MASK (0xFFU << DMA_DBGINST0_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST0_FIELD0001_SHIFT (24U) +#define DMA_DBGINST0_FIELD0001_MASK (0xFFU << DMA_DBGINST0_FIELD0001_SHIFT) /* 0xFF000000 */ +/* DBGINST1 */ +#define DMA_DBGINST1_OFFSET (0xD0CU) +#define DMA_DBGINST1_FIELD0000_SHIFT (0U) +#define DMA_DBGINST1_FIELD0000_MASK (0xFFU << DMA_DBGINST1_FIELD0000_SHIFT) /* 0x000000FF */ +#define DMA_DBGINST1_FIELD0003_SHIFT (8U) +#define DMA_DBGINST1_FIELD0003_MASK (0xFFU << DMA_DBGINST1_FIELD0003_SHIFT) /* 0x0000FF00 */ +#define DMA_DBGINST1_FIELD0002_SHIFT (16U) +#define DMA_DBGINST1_FIELD0002_MASK (0xFFU << DMA_DBGINST1_FIELD0002_SHIFT) /* 0x00FF0000 */ +#define DMA_DBGINST1_FIELD0001_SHIFT (24U) +#define DMA_DBGINST1_FIELD0001_MASK (0xFFU << DMA_DBGINST1_FIELD0001_SHIFT) /* 0xFF000000 */ +/* CR0 */ +#define DMA_CR0_OFFSET (0xE00U) +#define DMA_CR0 (0x47051U) +#define DMA_CR0_FIELD0000_SHIFT (0U) +#define DMA_CR0_FIELD0000_MASK (0x1U << DMA_CR0_FIELD0000_SHIFT) /* 0x00000001 */ +#define DMA_CR0_FIELD0005_SHIFT (1U) +#define DMA_CR0_FIELD0005_MASK (0x1U << DMA_CR0_FIELD0005_SHIFT) /* 0x00000002 */ +#define DMA_CR0_FIELD0004_SHIFT (2U) +#define DMA_CR0_FIELD0004_MASK (0x1U << DMA_CR0_FIELD0004_SHIFT) /* 0x00000004 */ +#define DMA_CR0_FIELD0003_SHIFT (4U) +#define DMA_CR0_FIELD0003_MASK (0x7U << DMA_CR0_FIELD0003_SHIFT) /* 0x00000070 */ +#define DMA_CR0_FIELD0002_SHIFT (12U) +#define DMA_CR0_FIELD0002_MASK (0x1FU << DMA_CR0_FIELD0002_SHIFT) /* 0x0001F000 */ +#define DMA_CR0_FIELD0001_SHIFT (17U) +#define DMA_CR0_FIELD0001_MASK (0x1FU << DMA_CR0_FIELD0001_SHIFT) /* 0x003E0000 */ +/* CR1 */ +#define DMA_CR1_OFFSET (0xE04U) +#define DMA_CR1 (0x57U) +#define DMA_CR1_FIELD0000_SHIFT (0U) +#define DMA_CR1_FIELD0000_MASK (0x7U << DMA_CR1_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CR1_FIELD0001_SHIFT (4U) +#define DMA_CR1_FIELD0001_MASK (0xFU << DMA_CR1_FIELD0001_SHIFT) /* 0x000000F0 */ +/* CR2 */ +#define DMA_CR2_OFFSET (0xE08U) +#define DMA_CR2 (0x0U) +#define DMA_CR2_FIELD0000_SHIFT (0U) +#define DMA_CR2_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR2_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR3 */ +#define DMA_CR3_OFFSET (0xE0CU) +#define DMA_CR3 (0x0U) +#define DMA_CR3_FIELD0000_SHIFT (0U) +#define DMA_CR3_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR3_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CR4 */ +#define DMA_CR4_OFFSET (0xE10U) +#define DMA_CR4 (0x6U) +#define DMA_CR4_FIELD0000_SHIFT (0U) +#define DMA_CR4_FIELD0000_MASK (0xFFFFFFFFU << DMA_CR4_FIELD0000_SHIFT) /* 0xFFFFFFFF */ +/* CRDN */ +#define DMA_CRDN_OFFSET (0xE14U) +#define DMA_CRDN (0x2094733U) +#define DMA_CRDN_FIELD0000_SHIFT (0U) +#define DMA_CRDN_FIELD0000_MASK (0x7U << DMA_CRDN_FIELD0000_SHIFT) /* 0x00000007 */ +#define DMA_CRDN_FIELD0005_SHIFT (4U) +#define DMA_CRDN_FIELD0005_MASK (0x7U << DMA_CRDN_FIELD0005_SHIFT) /* 0x00000070 */ +#define DMA_CRDN_FIELD0004_SHIFT (8U) +#define DMA_CRDN_FIELD0004_MASK (0xFU << DMA_CRDN_FIELD0004_SHIFT) /* 0x00000F00 */ +#define DMA_CRDN_FIELD0003_SHIFT (12U) +#define DMA_CRDN_FIELD0003_MASK (0x7U << DMA_CRDN_FIELD0003_SHIFT) /* 0x00007000 */ +#define DMA_CRDN_FIELD0002_SHIFT (16U) +#define DMA_CRDN_FIELD0002_MASK (0xFU << DMA_CRDN_FIELD0002_SHIFT) /* 0x000F0000 */ +#define DMA_CRDN_FIELD0001_SHIFT (20U) +#define DMA_CRDN_FIELD0001_MASK (0x3FFU << DMA_CRDN_FIELD0001_SHIFT) /* 0x3FF00000 */ +/* WD */ +#define DMA_WD_OFFSET (0xE80U) +#define DMA_WD_FIELD0000_SHIFT (0U) +#define DMA_WD_FIELD0000_MASK (0x1U << DMA_WD_FIELD0000_SHIFT) /* 0x00000001 */ +/*****************************************TIMER******************************************/ +/* LOAD_COUNT0 */ +#define TIMER_LOAD_COUNT0_OFFSET (0x0U) +#define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U) +#define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) /* 0xFFFFFFFF */ +/* LOAD_COUNT1 */ +#define TIMER_LOAD_COUNT1_OFFSET (0x4U) +#define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U) +#define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE0 */ +#define TIMER_CURRENT_VALUE0_OFFSET (0x8U) +#define TIMER_CURRENT_VALUE0 (0x0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE1 */ +#define TIMER_CURRENT_VALUE1_OFFSET (0xCU) +#define TIMER_CURRENT_VALUE1 (0x0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) /* 0xFFFFFFFF */ +/* CONTROLREG */ +#define TIMER_CONTROLREG_OFFSET (0x10U) +#define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U) +#define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) /* 0x00000001 */ +#define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U) +#define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) /* 0x00000002 */ +#define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U) +#define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) /* 0x00000004 */ +/* INTSTATUS */ +#define TIMER_INTSTATUS_OFFSET (0x18U) +#define TIMER_INTSTATUS_INT_PD_SHIFT (0U) +#define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) /* 0x00000001 */ +/******************************************MBOX******************************************/ +/* A2B_INTEN */ +#define MBOX_A2B_INTEN_OFFSET (0x0U) +#define MBOX_A2B_INTEN_INT0_SHIFT (0U) +#define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_INTEN_INT1_SHIFT (1U) +#define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_INTEN_INT2_SHIFT (2U) +#define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_INTEN_INT3_SHIFT (3U) +#define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* A2B_STATUS */ +#define MBOX_A2B_STATUS_OFFSET (0x4U) +#define MBOX_A2B_STATUS_INT0_SHIFT (0U) +#define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_STATUS_INT1_SHIFT (1U) +#define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_STATUS_INT2_SHIFT (2U) +#define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_STATUS_INT3_SHIFT (3U) +#define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* A2B_CMD_0 */ +#define MBOX_A2B_CMD_0_OFFSET (0x8U) +#define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_0 */ +#define MBOX_A2B_DAT_0_OFFSET (0xCU) +#define MBOX_A2B_DAT_0_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_1 */ +#define MBOX_A2B_CMD_1_OFFSET (0x10U) +#define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_1 */ +#define MBOX_A2B_DAT_1_OFFSET (0x14U) +#define MBOX_A2B_DAT_1_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_2 */ +#define MBOX_A2B_CMD_2_OFFSET (0x18U) +#define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_2 */ +#define MBOX_A2B_DAT_2_OFFSET (0x1CU) +#define MBOX_A2B_DAT_2_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_3 */ +#define MBOX_A2B_CMD_3_OFFSET (0x20U) +#define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_3 */ +#define MBOX_A2B_DAT_3_OFFSET (0x24U) +#define MBOX_A2B_DAT_3_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_INTEN */ +#define MBOX_B2A_INTEN_OFFSET (0x28U) +#define MBOX_B2A_INTEN_INT0_SHIFT (0U) +#define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_INTEN_INT1_SHIFT (1U) +#define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_INTEN_INT2_SHIFT (2U) +#define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_INTEN_INT3_SHIFT (3U) +#define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* B2A_STATUS */ +#define MBOX_B2A_STATUS_OFFSET (0x2CU) +#define MBOX_B2A_STATUS_INT0_SHIFT (0U) +#define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_STATUS_INT1_SHIFT (1U) +#define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_STATUS_INT2_SHIFT (2U) +#define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_STATUS_INT3_SHIFT (3U) +#define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* B2A_CMD_0 */ +#define MBOX_B2A_CMD_0_OFFSET (0x30U) +#define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_0 */ +#define MBOX_B2A_DAT_0_OFFSET (0x34U) +#define MBOX_B2A_DAT_0_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_1 */ +#define MBOX_B2A_CMD_1_OFFSET (0x38U) +#define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_1 */ +#define MBOX_B2A_DAT_1_OFFSET (0x3CU) +#define MBOX_B2A_DAT_1_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_2 */ +#define MBOX_B2A_CMD_2_OFFSET (0x40U) +#define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_2 */ +#define MBOX_B2A_DAT_2_OFFSET (0x44U) +#define MBOX_B2A_DAT_2_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_3 */ +#define MBOX_B2A_CMD_3_OFFSET (0x48U) +#define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_3 */ +#define MBOX_B2A_DAT_3_OFFSET (0x4CU) +#define MBOX_B2A_DAT_3_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* ATOMIC_LOCK_00 */ +#define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_01 */ +#define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_02 */ +#define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_03 */ +#define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_04 */ +#define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_05 */ +#define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_06 */ +#define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_07 */ +#define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_08 */ +#define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_09 */ +#define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_10 */ +#define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_11 */ +#define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_12 */ +#define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_13 */ +#define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_14 */ +#define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_15 */ +#define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_16 */ +#define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_17 */ +#define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_18 */ +#define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_19 */ +#define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_20 */ +#define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_21 */ +#define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_22 */ +#define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_23 */ +#define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_24 */ +#define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_25 */ +#define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_26 */ +#define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_27 */ +#define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_28 */ +#define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_29 */ +#define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_30 */ +#define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_31 */ +#define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) /* 0x00000001 */ + +// ========================= CRU module definition bank=0 ========================= +// CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_ARESETN_TOP_BIU 0x00000013 +#define SRST_PRESETN_TOP_BIU 0x00000014 +#define SRST_PRESETN_CSIPHY0 0x00000016 +#define SRST_PRESETN_CSIPHY1 0x00000018 +#define SRST_ARESETN_TOP_M500_BIU 0x0000001F + +// CRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_ARESETN_TOP_M400_BIU 0x00000020 +#define SRST_ARESETN_TOP_S200_BIU 0x00000021 +#define SRST_ARESETN_TOP_S400_BIU 0x00000022 +#define SRST_ARESETN_TOP_M300_BIU 0x00000023 +#define SRST_RESETN_USBDP_COMBO_PHY0_INIT 0x00000028 +#define SRST_RESETN_USBDP_COMBO_PHY0_CMN 0x00000029 +#define SRST_RESETN_USBDP_COMBO_PHY0_LANE 0x0000002A +#define SRST_RESETN_USBDP_COMBO_PHY0_PCS 0x0000002B +#define SRST_RESETN_USBDP_COMBO_PHY1_INIT 0x0000002F + +// CRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_RESETN_USBDP_COMBO_PHY1_CMN 0x00000030 +#define SRST_RESETN_USBDP_COMBO_PHY1_LANE 0x00000031 +#define SRST_RESETN_USBDP_COMBO_PHY1_PCS 0x00000032 +#define SRST_PRESETN_MIPI_DCPHY0 0x0000003E +#define SRST_PRESETN_MIPI_DCPHY0_GRF 0x0000003F + +// CRU_SOFTRST_CON04(Offset:0xA10) +#define SRST_PRESETN_MIPI_DCPHY1 0x00000043 +#define SRST_PRESETN_MIPI_DCPHY1_GRF 0x00000044 +#define SRST_PRESETN_APB2ASB_SLV_CDPHY 0x00000045 +#define SRST_PRESETN_APB2ASB_SLV_CSIPHY 0x00000046 +#define SRST_PRESETN_APB2ASB_SLV_VCCIO3_5 0x00000047 +#define SRST_PRESETN_APB2ASB_SLV_VCCIO6 0x00000048 +#define SRST_PRESETN_APB2ASB_SLV_EMMCIO 0x00000049 +#define SRST_PRESETN_APB2ASB_SLV_IOC_TOP 0x0000004A +#define SRST_PRESETN_APB2ASB_SLV_IOC_RIGHT 0x0000004B + +// CRU_SOFTRST_CON05(Offset:0xA14) +#define SRST_PRESETN_CRU 0x00000050 +#define SRST_ARESETN_CHANNEL_SECURE2VO1USB 0x00000057 +#define SRST_ARESETN_CHANNEL_SECURE2CENTER 0x00000058 +#define SRST_HRESETN_CHANNEL_SECURE2VO1USB 0x0000005E +#define SRST_HRESETN_CHANNEL_SECURE2CENTER 0x0000005F + +// CRU_SOFTRST_CON06(Offset:0xA18) +#define SRST_PRESETN_CHANNEL_SECURE2VO1USB 0x00000060 +#define SRST_PRESETN_CHANNEL_SECURE2CENTER 0x00000061 + +// CRU_SOFTRST_CON07(Offset:0xA1C) +#define SRST_HRESETN_AUDIO_BIU 0x00000072 +#define SRST_PRESETN_AUDIO_BIU 0x00000073 +#define SRST_HRESETN_I2S0_8CH 0x00000074 +#define SRST_MRESETN_I2S0_8CH_TX 0x00000077 +#define SRST_MRESETN_I2S0_8CH_RX 0x0000007A +#define SRST_PRESETN_ACDCDIG 0x0000007B +#define SRST_HRESETN_I2S2_2CH 0x0000007C +#define SRST_HRESETN_I2S3_2CH 0x0000007D + +// CRU_SOFTRST_CON08(Offset:0xA20) +#define SRST_MRESETN_I2S2_2CH 0x00000080 +#define SRST_MRESETN_I2S3_2CH 0x00000083 +#define SRST_RESETN_DAC_ACDCDIG 0x00000084 +#define SRST_HRESETN_SPDIF0 0x0000008E + +// CRU_SOFTRST_CON09(Offset:0xA24) +#define SRST_MRESETN_SPDIF0 0x00000091 +#define SRST_HRESETN_SPDIF1 0x00000092 +#define SRST_MRESETN_SPDIF1 0x00000095 +#define SRST_HRESETN_PDM1 0x00000096 +#define SRST_RESETN_PDM1 0x00000097 + +// CRU_SOFTRST_CON10(Offset:0xA28) +#define SRST_ARESETN_BUS_BIU 0x000000A1 +#define SRST_PRESETN_BUS_BIU 0x000000A2 +#define SRST_ARESETN_GIC 0x000000A3 +#define SRST_ARESETN_GIC_DBG 0x000000A4 +#define SRST_ARESETN_DMAC0 0x000000A5 +#define SRST_ARESETN_DMAC1 0x000000A6 +#define SRST_ARESETN_DMAC2 0x000000A7 +#define SRST_PRESETN_I2C1 0x000000A8 +#define SRST_PRESETN_I2C2 0x000000A9 +#define SRST_PRESETN_I2C3 0x000000AA +#define SRST_PRESETN_I2C4 0x000000AB +#define SRST_PRESETN_I2C5 0x000000AC +#define SRST_PRESETN_I2C6 0x000000AD +#define SRST_PRESETN_I2C7 0x000000AE +#define SRST_PRESETN_I2C8 0x000000AF + +// CRU_SOFTRST_CON11(Offset:0xA2C) +#define SRST_RESETN_I2C1 0x000000B0 +#define SRST_RESETN_I2C2 0x000000B1 +#define SRST_RESETN_I2C3 0x000000B2 +#define SRST_RESETN_I2C4 0x000000B3 +#define SRST_RESETN_I2C5 0x000000B4 +#define SRST_RESETN_I2C6 0x000000B5 +#define SRST_RESETN_I2C7 0x000000B6 +#define SRST_RESETN_I2C8 0x000000B7 +#define SRST_PRESETN_CAN0 0x000000B8 +#define SRST_RESETN_CAN0 0x000000B9 +#define SRST_PRESETN_CAN1 0x000000BA +#define SRST_RESETN_CAN1 0x000000BB +#define SRST_PRESETN_CAN2 0x000000BC +#define SRST_RESETN_CAN2 0x000000BD +#define SRST_PRESETN_SARADC 0x000000BE + +// CRU_SOFTRST_CON12(Offset:0xA30) +#define SRST_PRESETN_TSADC 0x000000C0 +#define SRST_RESETN_TSADC 0x000000C1 +#define SRST_PRESETN_UART1 0x000000C2 +#define SRST_PRESETN_UART2 0x000000C3 +#define SRST_PRESETN_UART3 0x000000C4 +#define SRST_PRESETN_UART4 0x000000C5 +#define SRST_PRESETN_UART5 0x000000C6 +#define SRST_PRESETN_UART6 0x000000C7 +#define SRST_PRESETN_UART7 0x000000C8 +#define SRST_PRESETN_UART8 0x000000C9 +#define SRST_PRESETN_UART9 0x000000CA +#define SRST_SRESETN_UART1 0x000000CD + +// CRU_SOFTRST_CON13(Offset:0xA34) +#define SRST_SRESETN_UART2 0x000000D0 +#define SRST_SRESETN_UART3 0x000000D3 +#define SRST_SRESETN_UART4 0x000000D6 +#define SRST_SRESETN_UART5 0x000000D9 +#define SRST_SRESETN_UART6 0x000000DC +#define SRST_SRESETN_UART7 0x000000DF + +// CRU_SOFTRST_CON14(Offset:0xA38) +#define SRST_SRESETN_UART8 0x000000E2 +#define SRST_SRESETN_UART9 0x000000E5 +#define SRST_PRESETN_SPI0 0x000000E6 +#define SRST_PRESETN_SPI1 0x000000E7 +#define SRST_PRESETN_SPI2 0x000000E8 +#define SRST_PRESETN_SPI3 0x000000E9 +#define SRST_PRESETN_SPI4 0x000000EA +#define SRST_RESETN_SPI0 0x000000EB +#define SRST_RESETN_SPI1 0x000000EC +#define SRST_RESETN_SPI2 0x000000ED +#define SRST_RESETN_SPI3 0x000000EE +#define SRST_RESETN_SPI4 0x000000EF + +// CRU_SOFTRST_CON15(Offset:0xA3C) +#define SRST_PRESETN_WDT0 0x000000F0 +#define SRST_TRESETN_WDT0 0x000000F1 +#define SRST_PRESETN_SYS_GRF 0x000000F2 +#define SRST_PRESETN_PWM1 0x000000F3 +#define SRST_RESETN_PWM1 0x000000F4 +#define SRST_PRESETN_PWM2 0x000000F6 +#define SRST_RESETN_PWM2 0x000000F7 +#define SRST_PRESETN_PWM3 0x000000F9 +#define SRST_RESETN_PWM3 0x000000FA +#define SRST_PRESETN_BUSTIMER0 0x000000FC +#define SRST_PRESETN_BUSTIMER1 0x000000FD +#define SRST_RESETN_BUSTIMER0 0x000000FF + +// CRU_SOFTRST_CON16(Offset:0xA40) +#define SRST_RESETN_BUSTIMER1 0x00000100 +#define SRST_RESETN_BUSTIMER2 0x00000101 +#define SRST_RESETN_BUSTIMER3 0x00000102 +#define SRST_RESETN_BUSTIMER4 0x00000103 +#define SRST_RESETN_BUSTIMER5 0x00000104 +#define SRST_RESETN_BUSTIMER6 0x00000105 +#define SRST_RESETN_BUSTIMER7 0x00000106 +#define SRST_RESETN_BUSTIMER8 0x00000107 +#define SRST_RESETN_BUSTIMER9 0x00000108 +#define SRST_RESETN_BUSTIMER10 0x00000109 +#define SRST_RESETN_BUSTIMER11 0x0000010A +#define SRST_PRESETN_MAILBOX0 0x0000010B +#define SRST_PRESETN_MAILBOX1 0x0000010C +#define SRST_PRESETN_MAILBOX2 0x0000010D +#define SRST_PRESETN_GPIO1 0x0000010E +#define SRST_DBRESETN_GPIO1 0x0000010F + +// CRU_SOFTRST_CON17(Offset:0xA44) +#define SRST_PRESETN_GPIO2 0x00000110 +#define SRST_DBRESETN_GPIO2 0x00000111 +#define SRST_PRESETN_GPIO3 0x00000112 +#define SRST_DBRESETN_GPIO3 0x00000113 +#define SRST_PRESETN_GPIO4 0x00000114 +#define SRST_DBRESETN_GPIO4 0x00000115 +#define SRST_ARESETN_DECOM 0x00000116 +#define SRST_PRESETN_DECOM 0x00000117 +#define SRST_DRESETN_DECOM 0x00000118 +#define SRST_PRESETN_TOP 0x00000119 +#define SRST_ARESETN_GICADB_GIC2CORE_BUS 0x0000011B +#define SRST_PRESETN_DFT2APB 0x0000011C +#define SRST_PRESETN_APB2ASB_MST_TOP 0x0000011D +#define SRST_PRESETN_APB2ASB_MST_CDPHY 0x0000011E +#define SRST_PRESETN_APB2ASB_MST_BOT_RIGHT 0x0000011F + +// CRU_SOFTRST_CON18(Offset:0xA48) +#define SRST_PRESETN_APB2ASB_MST_IOC_TOP 0x00000120 +#define SRST_PRESETN_APB2ASB_MST_IOC_RIGHT 0x00000121 +#define SRST_PRESETN_APB2ASB_MST_CSIPHY 0x00000122 +#define SRST_PRESETN_APB2ASB_MST_VCCIO3_5 0x00000123 +#define SRST_PRESETN_APB2ASB_MST_VCCIO6 0x00000124 +#define SRST_PRESETN_APB2ASB_MST_EMMCIO 0x00000125 +#define SRST_ARESETN_SPINLOCK 0x00000126 +#define SRST_PRESETN_OTPC_NS 0x00000129 +#define SRST_RESETN_OTPC_NS 0x0000012A +#define SRST_RESETN_OTPC_ARB 0x0000012B + +// CRU_SOFTRST_CON19(Offset:0xA4C) +#define SRST_PRESETN_BUSIOC 0x00000130 +#define SRST_PRESETN_PMUCM0_INTMUX 0x00000134 +#define SRST_PRESETN_DDRCM0_INTMUX 0x00000135 + +// CRU_SOFTRST_CON20(Offset:0xA50) +#define SRST_PRESETN_DDR_DFICTL_CH0 0x00000140 +#define SRST_PRESETN_DDR_MON_CH0 0x00000141 +#define SRST_PRESETN_DDR_STANDBY_CH0 0x00000142 +#define SRST_PRESETN_DDR_UPCTL_CH0 0x00000143 +#define SRST_TMRESETN_DDR_MON_CH0 0x00000144 +#define SRST_PRESETN_DDR_GRF_CH01 0x00000145 +#define SRST_RESETN_DFI_CH0 0x00000146 +#define SRST_RESETN_SBR_CH0 0x00000147 +#define SRST_RESETN_DDR_UPCTL_CH0 0x00000148 +#define SRST_RESETN_DDR_DFICTL_CH0 0x00000149 +#define SRST_RESETN_DDR_MON_CH0 0x0000014A +#define SRST_RESETN_DDR_STANDBY_CH0 0x0000014B +#define SRST_ARESETN_DDR_UPCTL_CH0 0x0000014C +#define SRST_PRESETN_DDR_DFICTL_CH1 0x0000014D +#define SRST_PRESETN_DDR_MON_CH1 0x0000014E +#define SRST_PRESETN_DDR_STANDBY_CH1 0x0000014F + +// CRU_SOFTRST_CON21(Offset:0xA54) +#define SRST_PRESETN_DDR_UPCTL_CH1 0x00000150 +#define SRST_TMRESETN_DDR_MON_CH1 0x00000151 +#define SRST_RESETN_DFI_CH1 0x00000152 +#define SRST_RESETN_SBR_CH1 0x00000153 +#define SRST_RESETN_DDR_UPCTL_CH1 0x00000154 +#define SRST_RESETN_DDR_DFICTL_CH1 0x00000155 +#define SRST_RESETN_DDR_MON_CH1 0x00000156 +#define SRST_RESETN_DDR_STANDBY_CH1 0x00000157 +#define SRST_ARESETN_DDR_UPCTL_CH1 0x00000158 +#define SRST_ARESETN_DDR_DDRSCH0 0x0000015D +#define SRST_ARESETN_DDR_RS_DDRSCH0 0x0000015E +#define SRST_ARESETN_DDR_FRS_DDRSCH0 0x0000015F + +// CRU_SOFTRST_CON22(Offset:0xA58) +#define SRST_ARESETN_DDR_SCRAMBLE0 0x00000160 +#define SRST_ARESETN_DDR_FRS_SCRAMBLE0 0x00000161 +#define SRST_ARESETN_DDR_DDRSCH1 0x00000162 +#define SRST_ARESETN_DDR_RS_DDRSCH1 0x00000163 +#define SRST_ARESETN_DDR_FRS_DDRSCH1 0x00000164 +#define SRST_ARESETN_DDR_SCRAMBLE1 0x00000165 +#define SRST_ARESETN_DDR_FRS_SCRAMBLE1 0x00000166 +#define SRST_PRESETN_DDR_DDRSCH0 0x00000167 +#define SRST_PRESETN_DDR_DDRSCH1 0x00000168 + +// CRU_SOFTRST_CON23(Offset:0xA5C) +#define SRST_PRESETN_DDR_DFICTL_CH2 0x00000170 +#define SRST_PRESETN_DDR_MON_CH2 0x00000171 +#define SRST_PRESETN_DDR_STANDBY_CH2 0x00000172 +#define SRST_PRESETN_DDR_UPCTL_CH2 0x00000173 +#define SRST_TMRESETN_DDR_MON_CH2 0x00000174 +#define SRST_PRESETN_DDR_GRF_CH23 0x00000175 +#define SRST_RESETN_DFI_CH2 0x00000176 +#define SRST_RESETN_SBR_CH2 0x00000177 +#define SRST_RESETN_DDR_UPCTL_CH2 0x00000178 +#define SRST_RESETN_DDR_DFICTL_CH2 0x00000179 +#define SRST_RESETN_DDR_MON_CH2 0x0000017A +#define SRST_RESETN_DDR_STANDBY_CH2 0x0000017B +#define SRST_ARESETN_DDR_UPCTL_CH2 0x0000017C +#define SRST_PRESETN_DDR_DFICTL_CH3 0x0000017D +#define SRST_PRESETN_DDR_MON_CH3 0x0000017E +#define SRST_PRESETN_DDR_STANDBY_CH3 0x0000017F + +// CRU_SOFTRST_CON24(Offset:0xA60) +#define SRST_PRESETN_DDR_UPCTL_CH3 0x00000180 +#define SRST_TMRESETN_DDR_MON_CH3 0x00000181 +#define SRST_RESETN_DFI_CH3 0x00000182 +#define SRST_RESETN_SBR_CH3 0x00000183 +#define SRST_RESETN_DDR_UPCTL_CH3 0x00000184 +#define SRST_RESETN_DDR_DFICTL_CH3 0x00000185 +#define SRST_RESETN_DDR_MON_CH3 0x00000186 +#define SRST_RESETN_DDR_STANDBY_CH3 0x00000187 +#define SRST_ARESETN_DDR_UPCTL_CH3 0x00000188 +#define SRST_ARESETN_DDR_DDRSCH2 0x0000018D +#define SRST_ARESETN_DDR_RS_DDRSCH2 0x0000018E +#define SRST_ARESETN_DDR_FRS_DDRSCH2 0x0000018F + +// CRU_SOFTRST_CON25(Offset:0xA64) +#define SRST_ARESETN_DDR_SCRAMBLE2 0x00000190 +#define SRST_ARESETN_DDR_FRS_SCRAMBLE2 0x00000191 +#define SRST_ARESETN_DDR_DDRSCH3 0x00000192 +#define SRST_ARESETN_DDR_RS_DDRSCH3 0x00000193 +#define SRST_ARESETN_DDR_FRS_DDRSCH3 0x00000194 +#define SRST_ARESETN_DDR_SCRAMBLE3 0x00000195 +#define SRST_ARESETN_DDR_FRS_SCRAMBLE3 0x00000196 +#define SRST_PRESETN_DDR_DDRSCH2 0x00000197 +#define SRST_PRESETN_DDR_DDRSCH3 0x00000198 + +// CRU_SOFTRST_CON26(Offset:0xA68) +#define SRST_RESETN_ISP1 0x000001A3 +#define SRST_RESETN_ISP1_VICAP 0x000001A4 +#define SRST_ARESETN_ISP1_BIU 0x000001A6 +#define SRST_HRESETN_ISP1_BIU 0x000001A8 + +// CRU_SOFTRST_CON27(Offset:0xA6C) +#define SRST_ARESETN_RKNN1 0x000001B0 +#define SRST_ARESETN_RKNN1_BIU 0x000001B1 +#define SRST_HRESETN_RKNN1 0x000001B2 +#define SRST_HRESETN_RKNN1_BIU 0x000001B3 + +// CRU_SOFTRST_CON28(Offset:0xA70) +#define SRST_ARESETN_RKNN2 0x000001C0 +#define SRST_ARESETN_RKNN2_BIU 0x000001C1 +#define SRST_HRESETN_RKNN2 0x000001C2 +#define SRST_HRESETN_RKNN2_BIU 0x000001C3 + +// CRU_SOFTRST_CON29(Offset:0xA74) +#define SRST_ARESETN_RKNN_DSU0 0x000001D3 +#define SRST_PRESETN_NPUTOP_BIU 0x000001D5 +#define SRST_PRESETN_NPU_TIMER 0x000001D6 +#define SRST_RESETN_NPUTIMER0 0x000001D8 +#define SRST_RESETN_NPUTIMER1 0x000001D9 +#define SRST_PRESETN_NPU_WDT 0x000001DA +#define SRST_TRESETN_NPU_WDT 0x000001DB +#define SRST_PRESETN_PVTM1 0x000001DC +#define SRST_PRESETN_NPU_GRF 0x000001DD +#define SRST_RESETN_PVTM1 0x000001DE + +// CRU_SOFTRST_CON30(Offset:0xA78) +#define SRST_RESETN_NPU_PVTPLL 0x000001E0 +#define SRST_HRESETN_NPU_CM0_BIU 0x000001E2 +#define SRST_FRESETN_NPU_CM0_CORE 0x000001E3 +#define SRST_TRESETN_NPU_CM0_JTAG 0x000001E4 +#define SRST_ARESETN_RKNN0 0x000001E6 +#define SRST_ARESETN_RKNN0_BIU 0x000001E7 +#define SRST_HRESETN_RKNN0 0x000001E8 +#define SRST_HRESETN_RKNN0_BIU 0x000001E9 + +// CRU_SOFTRST_CON31(Offset:0xA7C) +#define SRST_HRESETN_NVM_BIU 0x000001F2 +#define SRST_ARESETN_NVM_BIU 0x000001F3 +#define SRST_HRESETN_EMMC 0x000001F4 +#define SRST_ARESETN_EMMC 0x000001F5 +#define SRST_CRESETN_EMMC 0x000001F6 +#define SRST_BRESETN_EMMC 0x000001F7 +#define SRST_TRESETN_EMMC 0x000001F8 +#define SRST_SRESETN_SFC 0x000001F9 +#define SRST_HRESETN_SFC 0x000001FA +#define SRST_HRESETN_SFC_XIP 0x000001FB + +// CRU_SOFTRST_CON32(Offset:0xA80) +#define SRST_PRESETN_GRF 0x00000201 +#define SRST_PRESETN_DEC_BIU 0x00000202 +#define SRST_PRESETN_PHP_BIU 0x00000205 +#define SRST_ARESETN_PCIE_BRIDGE 0x00000208 +#define SRST_ARESETN_PHP_BIU 0x00000209 +#define SRST_ARESETN_GMAC0 0x0000020A +#define SRST_ARESETN_GMAC1 0x0000020B +#define SRST_ARESETN_PCIE_BIU 0x0000020C +#define SRST_RESETN_PCIE_4L_POWER_UP 0x0000020D +#define SRST_RESETN_PCIE_2L_POWER_UP 0x0000020E +#define SRST_RESETN_PCIE_1L0_POWER_UP 0x0000020F + +// CRU_SOFTRST_CON33(Offset:0xA84) +#define SRST_RESETN_PCIE_1L1_POWER_UP 0x00000210 +#define SRST_RESETN_PCIE_1L2_POWER_UP 0x00000211 +#define SRST_PRESETN_PCIE_4L 0x0000021C +#define SRST_PRESETN_PCIE_2L 0x0000021D +#define SRST_PRESETN_PCIE_1L0 0x0000021E +#define SRST_PRESETN_PCIE_1L1 0x0000021F + +// CRU_SOFTRST_CON34(Offset:0xA88) +#define SRST_PRESETN_PCIE_1L2 0x00000220 +#define SRST_ARESETN_PHP_GIC_ITS 0x00000226 +#define SRST_ARESETN_MMU_PCIE 0x00000227 +#define SRST_ARESETN_MMU_PHP 0x00000228 +#define SRST_ARESETN_MMU_BIU 0x00000229 + +// CRU_SOFTRST_CON35(Offset:0xA8C) +#define SRST_ARESETN_USB3OTG2 0x00000237 + +// CRU_SOFTRST_CON37(Offset:0xA94) +#define SRST_RESETN_PMALIVE0 0x00000254 +#define SRST_RESETN_PMALIVE1 0x00000255 +#define SRST_RESETN_PMALIVE2 0x00000256 +#define SRST_ARESETN_SATA0 0x00000257 +#define SRST_ARESETN_SATA1 0x00000258 +#define SRST_ARESETN_SATA2 0x00000259 +#define SRST_RESETN_RXOOB0 0x0000025A +#define SRST_RESETN_RXOOB1 0x0000025B +#define SRST_RESETN_RXOOB2 0x0000025C +#define SRST_RESETN_ASIC0 0x0000025D +#define SRST_RESETN_ASIC1 0x0000025E +#define SRST_RESETN_ASIC2 0x0000025F + +// CRU_SOFTRST_CON40(Offset:0xAA0) +#define SRST_ARESETN_RKVDEC_CCU 0x00000282 +#define SRST_HRESETN_RKVDEC0 0x00000283 +#define SRST_ARESETN_RKVDEC0 0x00000284 +#define SRST_HRESETN_RKVDEC0_BIU 0x00000285 +#define SRST_ARESETN_RKVDEC0_BIU 0x00000286 +#define SRST_RESETN_RKVDEC0_CA 0x00000287 +#define SRST_RESETN_RKVDEC0_HEVC_CA 0x00000288 +#define SRST_RESETN_RKVDEC0_CORE 0x00000289 + +// CRU_SOFTRST_CON41(Offset:0xAA4) +#define SRST_HRESETN_RKVDEC1 0x00000292 +#define SRST_ARESETN_RKVDEC1 0x00000293 +#define SRST_HRESETN_RKVDEC1_BIU 0x00000294 +#define SRST_ARESETN_RKVDEC1_BIU 0x00000295 +#define SRST_RESETN_RKVDEC1_CA 0x00000296 +#define SRST_RESETN_RKVDEC1_HEVC_CA 0x00000297 +#define SRST_RESETN_RKVDEC1_CORE 0x00000298 + +// CRU_SOFTRST_CON42(Offset:0xAA8) +#define SRST_ARESETN_USB_BIU 0x000002A2 +#define SRST_HRESETN_USB_BIU 0x000002A3 +#define SRST_ARESETN_USB3OTG0 0x000002A4 +#define SRST_ARESETN_USB3OTG1 0x000002A7 +#define SRST_HRESETN_HOST0 0x000002AA +#define SRST_HRESETN_HOST_ARB0 0x000002AB +#define SRST_HRESETN_HOST1 0x000002AC +#define SRST_HRESETN_HOST_ARB1 0x000002AD +#define SRST_ARESETN_USB_GRF 0x000002AE +#define SRST_CRESETN_USB2P0_HOST0 0x000002AF + +// CRU_SOFTRST_CON43(Offset:0xAAC) +#define SRST_CRESETN_USB2P0_HOST1 0x000002B0 +#define SRST_RESETN_HOST_UTMI0 0x000002B1 +#define SRST_RESETN_HOST_UTMI1 0x000002B2 + +// CRU_SOFTRST_CON44(Offset:0xAB0) +#define SRST_ARESETN_VDPU_BIU 0x000002C4 +#define SRST_ARESETN_VDPU_LOW_BIU 0x000002C5 +#define SRST_HRESETN_VDPU_BIU 0x000002C6 +#define SRST_ARESETN_JPEG_DECODER_BIU 0x000002C7 +#define SRST_ARESETN_VPU 0x000002C8 +#define SRST_HRESETN_VPU 0x000002C9 +#define SRST_ARESETN_JPEG_ENCODER0 0x000002CA +#define SRST_HRESETN_JPEG_ENCODER0 0x000002CB +#define SRST_ARESETN_JPEG_ENCODER1 0x000002CC +#define SRST_HRESETN_JPEG_ENCODER1 0x000002CD +#define SRST_ARESETN_JPEG_ENCODER2 0x000002CE +#define SRST_HRESETN_JPEG_ENCODER2 0x000002CF + +// CRU_SOFTRST_CON45(Offset:0xAB4) +#define SRST_ARESETN_JPEG_ENCODER3 0x000002D0 +#define SRST_HRESETN_JPEG_ENCODER3 0x000002D1 +#define SRST_ARESETN_JPEG_DECODER 0x000002D2 +#define SRST_HRESETN_JPEG_DECODER 0x000002D3 +#define SRST_HRESETN_IEP2P0 0x000002D4 +#define SRST_ARESETN_IEP2P0 0x000002D5 +#define SRST_RESETN_IEP2P0_CORE 0x000002D6 +#define SRST_HRESETN_RGA2 0x000002D7 +#define SRST_ARESETN_RGA2 0x000002D8 +#define SRST_RESETN_RGA2_CORE 0x000002D9 +#define SRST_HRESETN_RGA3_0 0x000002DA +#define SRST_ARESETN_RGA3_0 0x000002DB +#define SRST_RESETN_RGA3_0_CORE 0x000002DC + +// CRU_SOFTRST_CON47(Offset:0xABC) +#define SRST_HRESETN_RKVENC0_BIU 0x000002F2 +#define SRST_ARESETN_RKVENC0_BIU 0x000002F3 +#define SRST_HRESETN_RKVENC0 0x000002F4 +#define SRST_ARESETN_RKVENC0 0x000002F5 +#define SRST_RESETN_RKVENC0_CORE 0x000002F6 + +// CRU_SOFTRST_CON48(Offset:0xAC0) +#define SRST_HRESETN_RKVENC1_BIU 0x00000302 +#define SRST_ARESETN_RKVENC1_BIU 0x00000303 +#define SRST_HRESETN_RKVENC1 0x00000304 +#define SRST_ARESETN_RKVENC1 0x00000305 +#define SRST_RESETN_RKVENC1_CORE 0x00000306 + +// CRU_SOFTRST_CON49(Offset:0xAC4) +#define SRST_ARESETN_VI_BIU 0x00000313 +#define SRST_HRESETN_VI_BIU 0x00000314 +#define SRST_PRESETN_VI_BIU 0x00000315 +#define SRST_DRESETN_VICAP 0x00000316 +#define SRST_ARESETN_VICAP 0x00000317 +#define SRST_HRESETN_VICAP 0x00000318 +#define SRST_RESETN_ISP0 0x0000031A +#define SRST_RESETN_ISP0_VICAP 0x0000031B + +// CRU_SOFTRST_CON50(Offset:0xAC8) +#define SRST_RESETN_FISHEYE0 0x00000320 +#define SRST_RESETN_FISHEYE1 0x00000323 +#define SRST_PRESETN_CSI_HOST_0 0x00000324 +#define SRST_PRESETN_CSI_HOST_1 0x00000325 +#define SRST_PRESETN_CSI_HOST_2 0x00000326 +#define SRST_PRESETN_CSI_HOST_3 0x00000327 +#define SRST_PRESETN_CSI_HOST_4 0x00000328 +#define SRST_PRESETN_CSI_HOST_5 0x00000329 + +// CRU_SOFTRST_CON51(Offset:0xACC) +#define SRST_RESETN_CSIHOST0_VICAP 0x00000334 +#define SRST_RESETN_CSIHOST1_VICAP 0x00000335 +#define SRST_RESETN_CSIHOST2_VICAP 0x00000336 +#define SRST_RESETN_CSIHOST3_VICAP 0x00000337 +#define SRST_RESETN_CSIHOST4_VICAP 0x00000338 +#define SRST_RESETN_CSIHOST5_VICAP 0x00000339 +#define SRST_RESETN_CIFIN 0x0000033D + +// CRU_SOFTRST_CON52(Offset:0xAD0) +#define SRST_ARESETN_VOP_BIU 0x00000344 +#define SRST_ARESETN_VOP_LOW_BIU 0x00000345 +#define SRST_HRESETN_VOP_BIU 0x00000346 +#define SRST_PRESETN_VOP_BIU 0x00000347 +#define SRST_HRESETN_VOP 0x00000348 +#define SRST_ARESETN_VOP 0x00000349 +#define SRST_DRESETN_VOP0 0x0000034D +#define SRST_DRESETN_VOP2HDMI_BRIDGE0 0x0000034E +#define SRST_DRESETN_VOP2HDMI_BRIDGE1 0x0000034F + +// CRU_SOFTRST_CON53(Offset:0xAD4) +#define SRST_DRESETN_VOP1 0x00000350 +#define SRST_DRESETN_VOP2 0x00000351 +#define SRST_DRESETN_VOP3 0x00000352 +#define SRST_PRESETN_VOPGRF 0x00000353 +#define SRST_PRESETN_DSIHOST0 0x00000354 +#define SRST_PRESETN_DSIHOST1 0x00000355 +#define SRST_RESETN_DSIHOST0 0x00000356 +#define SRST_RESETN_DSIHOST1 0x00000357 +#define SRST_RESETN_VOP_PMU 0x00000358 +#define SRST_PRESETN_VOP_CHANNEL_BIU 0x00000359 + +// CRU_SOFTRST_CON55(Offset:0xADC) +#define SRST_HRESETN_VO0_BIU 0x00000375 +#define SRST_HRESETN_VO0_S_BIU 0x00000376 +#define SRST_PRESETN_VO0_BIU 0x00000377 +#define SRST_PRESETN_VO0_S_BIU 0x00000378 +#define SRST_ARESETN_HDCP0_BIU 0x00000379 +#define SRST_PRESETN_VO0GRF 0x0000037A +#define SRST_HRESETN_HDCP_KEY0 0x0000037B +#define SRST_ARESETN_HDCP0 0x0000037C +#define SRST_HRESETN_HDCP0 0x0000037D +#define SRST_RESETN_HDCP0 0x0000037F + +// CRU_SOFTRST_CON56(Offset:0xAE0) +#define SRST_PRESETN_TRNG0 0x00000381 +#define SRST_RESETN_DP0 0x00000388 +#define SRST_RESETN_DP1 0x00000389 +#define SRST_HRESETN_I2S4_8CH 0x0000038A +#define SRST_MRESETN_I2S4_8CH_TX 0x0000038D +#define SRST_HRESETN_I2S8_8CH 0x0000038E + +// CRU_SOFTRST_CON57(Offset:0xAE4) +#define SRST_MRESETN_I2S8_8CH_TX 0x00000391 +#define SRST_HRESETN_SPDIF2_DP0 0x00000392 +#define SRST_MRESETN_SPDIF2_DP0 0x00000396 +#define SRST_HRESETN_SPDIF5_DP1 0x00000397 +#define SRST_MRESETN_SPDIF5_DP1 0x0000039B + +// CRU_SOFTRST_CON59(Offset:0xAEC) +#define SRST_ARESETN_HDCP1_BIU 0x000003B6 +#define SRST_ARESETN_VO1_BIU 0x000003B8 +#define SRST_HRESETN_VOP1_BIU 0x000003B9 +#define SRST_HRESETN_VOP1_S_BIU 0x000003BA +#define SRST_PRESETN_VOP1_BIU 0x000003BB +#define SRST_PRESETN_VO1GRF 0x000003BC +#define SRST_PRESETN_VO1_S_BIU 0x000003BD + +// CRU_SOFTRST_CON60(Offset:0xAF0) +#define SRST_HRESETN_I2S7_8CH 0x000003C0 +#define SRST_MRESETN_I2S7_8CH_RX 0x000003C3 +#define SRST_HRESETN_HDCP_KEY1 0x000003C4 +#define SRST_ARESETN_HDCP1 0x000003C5 +#define SRST_HRESETN_HDCP1 0x000003C6 +#define SRST_RESETN_HDCP1 0x000003C8 +#define SRST_PRESETN_TRNG1 0x000003CA +#define SRST_PRESETN_HDMITX0 0x000003CB + +// CRU_SOFTRST_CON61(Offset:0xAF4) +#define SRST_RESETN_HDMITX0_REF 0x000003D0 +#define SRST_PRESETN_HDMITX1 0x000003D2 +#define SRST_RESETN_HDMITX1_REF 0x000003D7 +#define SRST_ARESETN_HDMIRX 0x000003D9 +#define SRST_PRESETN_HDMIRX 0x000003DA +#define SRST_RESETN_HDMIRX_REF 0x000003DB + +// CRU_SOFTRST_CON62(Offset:0xAF8) +#define SRST_PRESETN_EDP0 0x000003E0 +#define SRST_RESETN_EDP0_24M 0x000003E1 +#define SRST_PRESETN_EDP1 0x000003E3 +#define SRST_RESETN_EDP1_24M 0x000003E4 +#define SRST_MRESETN_I2S5_8CH_TX 0x000003E8 +#define SRST_HRESETN_I2S5_8CH 0x000003EC +#define SRST_MRESETN_I2S6_8CH_TX 0x000003EF + +// CRU_SOFTRST_CON63(Offset:0xAFC) +#define SRST_MRESETN_I2S6_8CH_RX 0x000003F2 +#define SRST_HRESETN_I2S6_8CH 0x000003F3 +#define SRST_HRESETN_SPDIF3 0x000003F4 +#define SRST_MRESETN_SPDIF3 0x000003F7 +#define SRST_HRESETN_SPDIF4 0x000003F8 +#define SRST_MRESETN_SPDIF4 0x000003FB +#define SRST_HRESETN_SPDIFRX0 0x000003FC +#define SRST_MRESETN_SPDIFRX0 0x000003FD +#define SRST_HRESETN_SPDIFRX1 0x000003FE +#define SRST_MRESETN_SPDIFRX1 0x000003FF + +// CRU_SOFTRST_CON64(Offset:0xB00) +#define SRST_HRESETN_SPDIFRX2 0x00000400 +#define SRST_MRESETN_SPDIFRX2 0x00000401 +#define SRST_RESETN_LINKSYM_HDMITXPHY0 0x0000040C +#define SRST_RESETN_LINKSYM_HDMITXPHY1 0x0000040D +#define SRST_RESETN_VO1_BRIDGE0 0x0000040E +#define SRST_RESETN_VO1_BRIDGE1 0x0000040F + +// CRU_SOFTRST_CON65(Offset:0xB04) +#define SRST_HRESETN_I2S9_8CH 0x00000410 +#define SRST_MRESETN_I2S9_8CH_RX 0x00000413 +#define SRST_HRESETN_I2S10_8CH 0x00000414 +#define SRST_MRESETN_I2S10_8CH_RX 0x00000417 +#define SRST_PRESETN_S_HDMIRX 0x00000418 + +// CRU_SOFTRST_CON66(Offset:0xB08) +#define SRST_RESETN_GPU 0x00000424 +#define SRST_SYSRESETN_GPU 0x00000425 +#define SRST_ARESETN_S_GPU_BIU 0x00000428 +#define SRST_ARESETN_M0_GPU_BIU 0x00000429 +#define SRST_ARESETN_M1_GPU_BIU 0x0000042A +#define SRST_ARESETN_M2_GPU_BIU 0x0000042B +#define SRST_ARESETN_M3_GPU_BIU 0x0000042C +#define SRST_PRESETN_GPU_BIU 0x0000042E +#define SRST_PRESETN_PVTM2 0x0000042F + +// CRU_SOFTRST_CON67(Offset:0xB0C) +#define SRST_RESETN_PVTM2 0x00000430 +#define SRST_PRESETN_GPU_GRF 0x00000432 +#define SRST_RESETN_GPU_PVTPLL 0x00000433 +#define SRST_PORESETN_GPU_JTAG 0x00000434 + +// CRU_SOFTRST_CON68(Offset:0xB10) +#define SRST_ARESETN_AV1_BIU 0x00000441 +#define SRST_ARESETN_AV1 0x00000442 +#define SRST_PRESETN_AV1_BIU 0x00000444 +#define SRST_PRESETN_AV1 0x00000445 + +// CRU_SOFTRST_CON69(Offset:0xB14) +#define SRST_ARESETN_DDR_BIU 0x00000454 +#define SRST_ARESETN_DMA2DDR 0x00000455 +#define SRST_ARESETN_DDR_SHAREMEM 0x00000456 +#define SRST_ARESETN_DDR_SHAREMEM_BIU 0x00000457 +#define SRST_ARESETN_CENTER_S200_BIU 0x0000045A +#define SRST_ARESETN_CENTER_S400_BIU 0x0000045B +#define SRST_HRESETN_AHB2APB 0x0000045C +#define SRST_HRESETN_CENTER_BIU 0x0000045D +#define SRST_FRESETN_DDR_CM0_CORE 0x0000045E + +// CRU_SOFTRST_CON70(Offset:0xB18) +#define SRST_RESETN_DDR_TIMER0 0x00000460 +#define SRST_RESETN_DDR_TIMER1 0x00000461 +#define SRST_TRESETN_WDT_DDR 0x00000462 +#define SRST_TRESETN_DDR_CM0_JTAG 0x00000463 +#define SRST_PRESETN_CENTER_GRF 0x00000465 +#define SRST_PRESETN_AHB2APB 0x00000466 +#define SRST_PRESETN_WDT 0x00000467 +#define SRST_PRESETN_TIMER 0x00000468 +#define SRST_PRESETN_DMA2DDR 0x00000469 +#define SRST_PRESETN_SHAREMEM 0x0000046A +#define SRST_PRESETN_CENTER_BIU 0x0000046B +#define SRST_PRESETN_CENTER_CHANNEL_BIU 0x0000046C + +// CRU_SOFTRST_CON72(Offset:0xB20) +#define SRST_PRESETN_USBDPGRF0 0x00000481 +#define SRST_PRESETN_USBDPPHY0 0x00000482 +#define SRST_PRESETN_USBDPGRF1 0x00000483 +#define SRST_PRESETN_USBDPPHY1 0x00000484 +#define SRST_PRESETN_HDPTX0 0x00000485 +#define SRST_PRESETN_HDPTX1 0x00000486 +#define SRST_PRESETN_APB2ASB_SLV_BOT_RIGHT 0x00000487 +#define SRST_PRESETN_USB2PHY_U3_0_GRF0 0x00000488 +#define SRST_PRESETN_USB2PHY_U3_1_GRF0 0x00000489 +#define SRST_PRESETN_USB2PHY_U2_0_GRF0 0x0000048A +#define SRST_PRESETN_USB2PHY_U2_1_GRF0 0x0000048B + +// CRU_SOFTRST_CON73(Offset:0xB24) +#define SRST_RESETN_HDMIHDP0 0x0000049C +#define SRST_RESETN_HDMIHDP1 0x0000049D + +// CRU_SOFTRST_CON74(Offset:0xB28) +#define SRST_ARESETN_VO1USB_TOP_BIU 0x000004A1 +#define SRST_HRESETN_VO1USB_TOP_BIU 0x000004A3 + +// CRU_SOFTRST_CON75(Offset:0xB2C) +#define SRST_HRESETN_SDIO_BIU 0x000004B1 +#define SRST_HRESETN_SDIO 0x000004B2 +#define SRST_RESETN_SDIO 0x000004B3 + +// CRU_SOFTRST_CON76(Offset:0xB30) +#define SRST_HRESETN_RGA3_BIU 0x000004C2 +#define SRST_ARESETN_RGA3_BIU 0x000004C3 +#define SRST_HRESETN_RGA3_1 0x000004C4 +#define SRST_ARESETN_RGA3_1 0x000004C5 +#define SRST_RESETN_RGA3_1_CORE 0x000004C6 + +// CRU_SOFTRST_CON77(Offset:0xB34) +#define SRST_RESETN_REF_PIPE_PHY0 0x000004D6 +#define SRST_RESETN_REF_PIPE_PHY1 0x000004D7 +#define SRST_RESETN_REF_PIPE_PHY2 0x000004D8 + +// CRU_GATE_CON00(Offset:0x800) +#define CLK_MATRIX_50M_SRC_GATE 0x00000000 +#define CLK_MATRIX_100M_SRC_GATE 0x00000001 +#define CLK_MATRIX_150M_SRC_GATE 0x00000002 +#define CLK_MATRIX_200M_SRC_GATE 0x00000003 +#define CLK_MATRIX_250M_SRC_GATE 0x00000004 +#define CLK_MATRIX_300M_SRC_GATE 0x00000005 +#define CLK_MATRIX_350M_SRC_GATE 0x00000006 +#define CLK_MATRIX_400M_SRC_GATE 0x00000007 +#define CLK_MATRIX_450M_SRC_GATE 0x00000008 +#define CLK_MATRIX_500M_SRC_GATE 0x00000009 +#define CLK_MATRIX_600M_SRC_GATE 0x0000000A +#define CLK_MATRIX_650M_SRC_GATE 0x0000000B +#define CLK_MATRIX_700M_SRC_GATE 0x0000000C +#define CLK_MATRIX_800M_SRC_GATE 0x0000000D +#define CLK_MATRIX_1000M_SRC_GATE 0x0000000E +#define CLK_MATRIX_1200M_SRC_GATE 0x0000000F + +// CRU_GATE_CON01(Offset:0x804) +#define ACLK_TOP_ROOT_GATE 0x00000010 +#define PCLK_TOP_ROOT_GATE 0x00000011 +#define ACLK_LOW_TOP_ROOT_GATE 0x00000012 +#define ACLK_TOP_BIU_GATE 0x00000013 +#define PCLK_TOP_BIU_GATE 0x00000014 +#define PCLK_CSIPHY0_GATE 0x00000016 +#define PCLK_CSIPHY1_GATE 0x00000018 +#define ACLK_TOP_M300_ROOT_GATE 0x0000001A +#define ACLK_TOP_M500_ROOT_GATE 0x0000001B +#define ACLK_TOP_M400_ROOT_GATE 0x0000001C +#define ACLK_TOP_S200_ROOT_GATE 0x0000001D +#define ACLK_TOP_S400_ROOT_GATE 0x0000001E +#define ACLK_TOP_M500_BIU_GATE 0x0000001F + +// CRU_GATE_CON02(Offset:0x808) +#define ACLK_TOP_M400_BIU_GATE 0x00000020 +#define ACLK_TOP_S200_BIU_GATE 0x00000021 +#define ACLK_TOP_S400_BIU_GATE 0x00000022 +#define ACLK_TOP_M300_BIU_GATE 0x00000023 +#define CLK_TESTOUT_TOP_GATE 0x00000024 +#define CLK_TESTOUT_GRP0_GATE 0x00000026 +#define CLK_USBDP_COMBO_PHY0_IMMORTAL_GATE 0x00000028 +#define CLK_USBDP_COMBO_PHY1_IMMORTAL_GATE 0x0000002F + +// CRU_GATE_CON03(Offset:0x80C) +#define PCLK_MIPI_DCPHY0_GATE 0x0000003E +#define PCLK_MIPI_DCPHY0_GRF_GATE 0x0000003F + +// CRU_GATE_CON04(Offset:0x810) +#define PCLK_MIPI_DCPHY1_GATE 0x00000043 +#define PCLK_MIPI_DCPHY1_GRF_GATE 0x00000044 +#define PCLK_APB2ASB_SLV_CDPHY_GATE 0x00000045 +#define PCLK_APB2ASB_SLV_CSIPHY_GATE 0x00000046 +#define PCLK_APB2ASB_SLV_VCCIO3_5_GATE 0x00000047 +#define PCLK_APB2ASB_SLV_VCCIO6_GATE 0x00000048 +#define PCLK_APB2ASB_SLV_EMMCIO_GATE 0x00000049 +#define PCLK_APB2ASB_SLV_IOC_TOP_GATE 0x0000004A +#define PCLK_APB2ASB_SLV_IOC_RIGHT_GATE 0x0000004B + +// CRU_GATE_CON05(Offset:0x814) +#define PCLK_CRU_GATE 0x00000050 +#define MCLK_GMAC0_OUT_GATE 0x00000053 +#define REFCLKO25M_ETH0_OUT_GATE 0x00000054 +#define REFCLKO25M_ETH1_OUT_GATE 0x00000055 +#define CLK_CIFOUT_OUT_GATE 0x00000056 +#define ACLK_CHANNEL_SECURE2VO1USB_GATE 0x00000057 +#define ACLK_CHANNEL_SECURE2CENTER_GATE 0x00000058 +#define CLK_MIPI_CAMERAOUT_M0_GATE 0x00000059 +#define CLK_MIPI_CAMERAOUT_M1_GATE 0x0000005A +#define CLK_MIPI_CAMERAOUT_M2_GATE 0x0000005B +#define CLK_MIPI_CAMERAOUT_M3_GATE 0x0000005C +#define CLK_MIPI_CAMERAOUT_M4_GATE 0x0000005D +#define HCLK_CHANNEL_SECURE2VO1USB_GATE 0x0000005E +#define HCLK_CHANNEL_SECURE2CENTER_GATE 0x0000005F + +// CRU_GATE_CON06(Offset:0x818) +#define PCLK_CHANNEL_SECURE2VO1USB_GATE 0x00000060 +#define PCLK_CHANNEL_SECURE2CENTER_GATE 0x00000061 + +// CRU_GATE_CON07(Offset:0x81C) +#define HCLK_AUDIO_ROOT_GATE 0x00000070 +#define PCLK_AUDIO_ROOT_GATE 0x00000071 +#define HCLK_AUDIO_BIU_GATE 0x00000072 +#define PCLK_AUDIO_BIU_GATE 0x00000073 +#define HCLK_I2S0_8CH_GATE 0x00000074 +#define CLK_I2S0_8CH_TX_GATE 0x00000075 +#define CLK_I2S0_8CH_FRAC_TX_GATE 0x00000076 +#define MCLK_I2S0_8CH_TX_GATE 0x00000077 +#define CLK_I2S0_8CH_RX_GATE 0x00000078 +#define CLK_I2S0_8CH_FRAC_RX_GATE 0x00000079 +#define MCLK_I2S0_8CH_RX_GATE 0x0000007A +#define PCLK_ACDCDIG_GATE 0x0000007B +#define HCLK_I2S2_2CH_GATE 0x0000007C +#define HCLK_I2S3_2CH_GATE 0x0000007D +#define CLK_I2S2_2CH_GATE 0x0000007E +#define CLK_I2S2_2CH_FRAC_GATE 0x0000007F + +// CRU_GATE_CON08(Offset:0x820) +#define MCLK_I2S2_2CH_GATE 0x00000080 +#define CLK_I2S3_2CH_GATE 0x00000081 +#define CLK_I2S3_2CH_FRAC_GATE 0x00000082 +#define MCLK_I2S3_2CH_GATE 0x00000083 +#define CLK_DAC_ACDCDIG_GATE 0x00000084 +#define HCLK_SPDIF0_GATE 0x0000008E +#define CLK_SPDIF0_GATE 0x0000008F + +// CRU_GATE_CON09(Offset:0x824) +#define CLK_SPDIF0_FRAC_GATE 0x00000090 +#define MCLK_SPDIF0_GATE 0x00000091 +#define HCLK_SPDIF1_GATE 0x00000092 +#define CLK_SPDIF1_GATE 0x00000093 +#define CLK_SPDIF1_FRAC_GATE 0x00000094 +#define MCLK_SPDIF1_GATE 0x00000095 +#define HCLK_PDM1_GATE 0x00000096 +#define MCLK_PDM1_GATE 0x00000097 + +// CRU_GATE_CON10(Offset:0x828) +#define ACLK_BUS_ROOT_GATE 0x000000A0 +#define ACLK_BUS_BIU_GATE 0x000000A1 +#define PCLK_BUS_BIU_GATE 0x000000A2 +#define ACLK_GIC_GATE 0x000000A3 +#define ACLK_DMAC0_GATE 0x000000A5 +#define ACLK_DMAC1_GATE 0x000000A6 +#define ACLK_DMAC2_GATE 0x000000A7 +#define PCLK_I2C1_GATE 0x000000A8 +#define PCLK_I2C2_GATE 0x000000A9 +#define PCLK_I2C3_GATE 0x000000AA +#define PCLK_I2C4_GATE 0x000000AB +#define PCLK_I2C5_GATE 0x000000AC +#define PCLK_I2C6_GATE 0x000000AD +#define PCLK_I2C7_GATE 0x000000AE +#define PCLK_I2C8_GATE 0x000000AF + +// CRU_GATE_CON11(Offset:0x82C) +#define CLK_I2C1_GATE 0x000000B0 +#define CLK_I2C2_GATE 0x000000B1 +#define CLK_I2C3_GATE 0x000000B2 +#define CLK_I2C4_GATE 0x000000B3 +#define CLK_I2C5_GATE 0x000000B4 +#define CLK_I2C6_GATE 0x000000B5 +#define CLK_I2C7_GATE 0x000000B6 +#define CLK_I2C8_GATE 0x000000B7 +#define PCLK_CAN0_GATE 0x000000B8 +#define CLK_CAN0_GATE 0x000000B9 +#define PCLK_CAN1_GATE 0x000000BA +#define CLK_CAN1_GATE 0x000000BB +#define PCLK_CAN2_GATE 0x000000BC +#define CLK_CAN2_GATE 0x000000BD +#define PCLK_SARADC_GATE 0x000000BE +#define CLK_SARADC_GATE 0x000000BF + +// CRU_GATE_CON12(Offset:0x830) +#define PCLK_TSADC_GATE 0x000000C0 +#define CLK_TSADC_GATE 0x000000C1 +#define PCLK_UART1_GATE 0x000000C2 +#define PCLK_UART2_GATE 0x000000C3 +#define PCLK_UART3_GATE 0x000000C4 +#define PCLK_UART4_GATE 0x000000C5 +#define PCLK_UART5_GATE 0x000000C6 +#define PCLK_UART6_GATE 0x000000C7 +#define PCLK_UART7_GATE 0x000000C8 +#define PCLK_UART8_GATE 0x000000C9 +#define PCLK_UART9_GATE 0x000000CA +#define CLK_UART1_GATE 0x000000CB +#define CLK_UART1_FRAC_GATE 0x000000CC +#define SCLK_UART1_GATE 0x000000CD +#define CLK_UART2_GATE 0x000000CE +#define CLK_UART2_FRAC_GATE 0x000000CF + +// CRU_GATE_CON13(Offset:0x834) +#define SCLK_UART2_GATE 0x000000D0 +#define CLK_UART3_GATE 0x000000D1 +#define CLK_UART3_FRAC_GATE 0x000000D2 +#define SCLK_UART3_GATE 0x000000D3 +#define CLK_UART4_GATE 0x000000D4 +#define CLK_UART4_FRAC_GATE 0x000000D5 +#define SCLK_UART4_GATE 0x000000D6 +#define CLK_UART5_GATE 0x000000D7 +#define CLK_UART5_FRAC_GATE 0x000000D8 +#define SCLK_UART5_GATE 0x000000D9 +#define CLK_UART6_GATE 0x000000DA +#define CLK_UART6_FRAC_GATE 0x000000DB +#define SCLK_UART6_GATE 0x000000DC +#define CLK_UART7_GATE 0x000000DD +#define CLK_UART7_FRAC_GATE 0x000000DE +#define SCLK_UART7_GATE 0x000000DF + +// CRU_GATE_CON14(Offset:0x838) +#define CLK_UART8_GATE 0x000000E0 +#define CLK_UART8_FRAC_GATE 0x000000E1 +#define SCLK_UART8_GATE 0x000000E2 +#define CLK_UART9_GATE 0x000000E3 +#define CLK_UART9_FRAC_GATE 0x000000E4 +#define SCLK_UART9_GATE 0x000000E5 +#define PCLK_SPI0_GATE 0x000000E6 +#define PCLK_SPI1_GATE 0x000000E7 +#define PCLK_SPI2_GATE 0x000000E8 +#define PCLK_SPI3_GATE 0x000000E9 +#define PCLK_SPI4_GATE 0x000000EA +#define CLK_SPI0_GATE 0x000000EB +#define CLK_SPI1_GATE 0x000000EC +#define CLK_SPI2_GATE 0x000000ED +#define CLK_SPI3_GATE 0x000000EE +#define CLK_SPI4_GATE 0x000000EF + +// CRU_GATE_CON15(Offset:0x83C) +#define PCLK_WDT0_GATE 0x000000F0 +#define TCLK_WDT0_GATE 0x000000F1 +#define PCLK_SYS_GRF_GATE 0x000000F2 +#define PCLK_PWM1_GATE 0x000000F3 +#define CLK_PWM1_GATE 0x000000F4 +#define CLK_PWM1_CAPTURE_GATE 0x000000F5 +#define PCLK_PWM2_GATE 0x000000F6 +#define CLK_PWM2_GATE 0x000000F7 +#define CLK_PWM2_CAPTURE_GATE 0x000000F8 +#define PCLK_PWM3_GATE 0x000000F9 +#define CLK_PWM3_GATE 0x000000FA +#define CLK_PWM3_CAPTURE_GATE 0x000000FB +#define PCLK_BUSTIMER0_GATE 0x000000FC +#define PCLK_BUSTIMER1_GATE 0x000000FD +#define CLK_BUSTIMER_ROOT_GATE 0x000000FE +#define CLK_BUSTIMER0_GATE 0x000000FF + +// CRU_GATE_CON16(Offset:0x840) +#define CLK_BUSTIMER1_GATE 0x00000100 +#define CLK_BUSTIMER2_GATE 0x00000101 +#define CLK_BUSTIMER3_GATE 0x00000102 +#define CLK_BUSTIMER4_GATE 0x00000103 +#define CLK_BUSTIMER5_GATE 0x00000104 +#define CLK_BUSTIMER6_GATE 0x00000105 +#define CLK_BUSTIMER7_GATE 0x00000106 +#define CLK_BUSTIMER8_GATE 0x00000107 +#define CLK_BUSTIMER9_GATE 0x00000108 +#define CLK_BUSTIMER10_GATE 0x00000109 +#define CLK_BUSTIMER11_GATE 0x0000010A +#define PCLK_MAILBOX0_GATE 0x0000010B +#define PCLK_MAILBOX1_GATE 0x0000010C +#define PCLK_MAILBOX2_GATE 0x0000010D +#define PCLK_GPIO1_GATE 0x0000010E +#define DBCLK_GPIO1_GATE 0x0000010F + +// CRU_GATE_CON17(Offset:0x844) +#define PCLK_GPIO2_GATE 0x00000110 +#define DBCLK_GPIO2_GATE 0x00000111 +#define PCLK_GPIO3_GATE 0x00000112 +#define DBCLK_GPIO3_GATE 0x00000113 +#define PCLK_GPIO4_GATE 0x00000114 +#define DBCLK_GPIO4_GATE 0x00000115 +#define ACLK_DECOM_GATE 0x00000116 +#define PCLK_DECOM_GATE 0x00000117 +#define DCLK_DECOM_GATE 0x00000118 +#define PCLK_TOP_GATE 0x00000119 +#define ACLK_GICADB_GIC2CORE_BUS_GATE 0x0000011B +#define PCLK_DFT2APB_GATE 0x0000011C +#define PCLK_APB2ASB_MST_TOP_GATE 0x0000011D +#define PCLK_APB2ASB_MST_CDPHY_GATE 0x0000011E +#define PCLK_APB2ASB_MST_BOT_RIGHT_GATE 0x0000011F + +// CRU_GATE_CON18(Offset:0x848) +#define PCLK_APB2ASB_MST_IOC_TOP_GATE 0x00000120 +#define PCLK_APB2ASB_MST_IOC_RIGHT_GATE 0x00000121 +#define PCLK_APB2ASB_MST_CSIPHY_GATE 0x00000122 +#define PCLK_APB2ASB_MST_VCCIO3_5_GATE 0x00000123 +#define PCLK_APB2ASB_MST_VCCIO6_GATE 0x00000124 +#define PCLK_APB2ASB_MST_EMMCIO_GATE 0x00000125 +#define ACLK_SPINLOCK_GATE 0x00000126 +#define PCLK_OTPC_NS_GATE 0x00000129 +#define CLK_OTPC_NS_GATE 0x0000012A +#define CLK_OTPC_ARB_GATE 0x0000012B +#define CLK_OTPC_AUTO_RD_GATE 0x0000012C +#define CLK_OTP_PHY_GATE 0x0000012D + +// CRU_GATE_CON19(Offset:0x84C) +#define PCLK_BUSIOC_GATE 0x00000130 +#define CLK_BISRINTF_PLLSRC_GATE 0x00000131 +#define CLK_BISRINTF_GATE 0x00000132 +#define PCLK_PMU2_GATE 0x00000133 +#define PCLK_PMUCM0_INTMUX_GATE 0x00000134 +#define PCLK_DDRCM0_INTMUX_GATE 0x00000135 + +// CRU_GATE_CON20(Offset:0x850) +#define PCLK_DDR_DFICTL_CH0_GATE 0x00000140 +#define PCLK_DDR_MON_CH0_GATE 0x00000141 +#define PCLK_DDR_STANDBY_CH0_GATE 0x00000142 +#define PCLK_DDR_UPCTL_CH0_GATE 0x00000143 +#define TMCLK_DDR_MON_CH0_GATE 0x00000144 +#define PCLK_DDR_GRF_CH01_GATE 0x00000145 +#define CLK_DFI_CH0_GATE 0x00000146 +#define CLK_SBR_CH0_GATE 0x00000147 +#define CLK_DDR_UPCTL_CH0_GATE 0x00000148 +#define CLK_DDR_DFICTL_CH0_GATE 0x00000149 +#define CLK_DDR_MON_CH0_GATE 0x0000014A +#define CLK_DDR_STANDBY_CH0_GATE 0x0000014B +#define ACLK_DDR_UPCTL_CH0_GATE 0x0000014C +#define PCLK_DDR_DFICTL_CH1_GATE 0x0000014D +#define PCLK_DDR_MON_CH1_GATE 0x0000014E +#define PCLK_DDR_STANDBY_CH1_GATE 0x0000014F + +// CRU_GATE_CON21(Offset:0x854) +#define PCLK_DDR_UPCTL_CH1_GATE 0x00000150 +#define TMCLK_DDR_MON_CH1_GATE 0x00000151 +#define CLK_DFI_CH1_GATE 0x00000152 +#define CLK_SBR_CH1_GATE 0x00000153 +#define CLK_DDR_UPCTL_CH1_GATE 0x00000154 +#define CLK_DDR_DFICTL_CH1_GATE 0x00000155 +#define CLK_DDR_MON_CH1_GATE 0x00000156 +#define CLK_DDR_STANDBY_CH1_GATE 0x00000157 +#define ACLK_DDR_UPCTL_CH1_GATE 0x00000158 +#define ACLK_DDR_DDRSCH0_GATE 0x0000015D +#define ACLK_DDR_RS_DDRSCH0_GATE 0x0000015E +#define ACLK_DDR_FRS_DDRSCH0_GATE 0x0000015F + +// CRU_GATE_CON22(Offset:0x858) +#define ACLK_DDR_SCRAMBLE0_GATE 0x00000160 +#define ACLK_DDR_FRS_SCRAMBLE0_GATE 0x00000161 +#define ACLK_DDR_DDRSCH1_GATE 0x00000162 +#define ACLK_DDR_RS_DDRSCH1_GATE 0x00000163 +#define ACLK_DDR_FRS_DDRSCH1_GATE 0x00000164 +#define ACLK_DDR_SCRAMBLE1_GATE 0x00000165 +#define ACLK_DDR_FRS_SCRAMBLE1_GATE 0x00000166 +#define PCLK_DDR_DDRSCH0_GATE 0x00000167 +#define PCLK_DDR_DDRSCH1_GATE 0x00000168 +#define CLK_TESTOUT_DDR01_GATE 0x00000169 + +// CRU_GATE_CON23(Offset:0x85C) +#define PCLK_DDR_DFICTL_CH2_GATE 0x00000170 +#define PCLK_DDR_MON_CH2_GATE 0x00000171 +#define PCLK_DDR_STANDBY_CH2_GATE 0x00000172 +#define PCLK_DDR_UPCTL_CH2_GATE 0x00000173 +#define TMCLK_DDR_MON_CH2_GATE 0x00000174 +#define PCLK_DDR_GRF_CH23_GATE 0x00000175 +#define CLK_DFI_CH2_GATE 0x00000176 +#define CLK_SBR_CH2_GATE 0x00000177 +#define CLK_DDR_UPCTL_CH2_GATE 0x00000178 +#define CLK_DDR_DFICTL_CH2_GATE 0x00000179 +#define CLK_DDR_MON_CH2_GATE 0x0000017A +#define CLK_DDR_STANDBY_CH2_GATE 0x0000017B +#define ACLK_DDR_UPCTL_CH2_GATE 0x0000017C +#define PCLK_DDR_DFICTL_CH3_GATE 0x0000017D +#define PCLK_DDR_MON_CH3_GATE 0x0000017E +#define PCLK_DDR_STANDBY_CH3_GATE 0x0000017F + +// CRU_GATE_CON24(Offset:0x860) +#define PCLK_DDR_UPCTL_CH3_GATE 0x00000180 +#define TMCLK_DDR_MON_CH3_GATE 0x00000181 +#define CLK_DFI_CH3_GATE 0x00000182 +#define CLK_SBR_CH3_GATE 0x00000183 +#define CLK_DDR_UPCTL_CH3_GATE 0x00000184 +#define CLK_DDR_DFICTL_CH3_GATE 0x00000185 +#define CLK_DDR_MON_CH3_GATE 0x00000186 +#define CLK_DDR_STANDBY_CH3_GATE 0x00000187 +#define ACLK_DDR_UPCTL_CH3_GATE 0x00000188 +#define ACLK_DDR_DDRSCH2_GATE 0x0000018D +#define ACLK_DDR_RS_DDRSCH2_GATE 0x0000018E +#define ACLK_DDR_FRS_DDRSCH2_GATE 0x0000018F + +// CRU_GATE_CON25(Offset:0x864) +#define ACLK_DDR_SCRAMBLE2_GATE 0x00000190 +#define ACLK_DDR_FRS_SCRAMBLE2_GATE 0x00000191 +#define ACLK_DDR_DDRSCH3_GATE 0x00000192 +#define ACLK_DDR_RS_DDRSCH3_GATE 0x00000193 +#define ACLK_DDR_FRS_DDRSCH3_GATE 0x00000194 +#define ACLK_DDR_SCRAMBLE3_GATE 0x00000195 +#define ACLK_DDR_FRS_SCRAMBLE3_GATE 0x00000196 +#define PCLK_DDR_DDRSCH2_GATE 0x00000197 +#define PCLK_DDR_DDRSCH3_GATE 0x00000198 +#define CLK_TESTOUT_DDR23_GATE 0x00000199 + +// CRU_GATE_CON26(Offset:0x868) +#define ACLK_ISP1_ROOT_GATE 0x000001A0 +#define HCLK_ISP1_ROOT_GATE 0x000001A1 +#define CLK_ISP1_CORE_GATE 0x000001A2 +#define CLK_ISP1_CORE_MARVIN_GATE 0x000001A3 +#define CLK_ISP1_CORE_VICAP_GATE 0x000001A4 +#define ACLK_ISP1_GATE 0x000001A5 +#define ACLK_ISP1_BIU_GATE 0x000001A6 +#define HCLK_ISP1_GATE 0x000001A7 +#define HCLK_ISP1_BIU_GATE 0x000001A8 + +// CRU_GATE_CON27(Offset:0x86C) +#define ACLK_RKNN1_GATE 0x000001B0 +#define ACLK_RKNN1_BIU_GATE 0x000001B1 +#define HCLK_RKNN1_GATE 0x000001B2 +#define HCLK_RKNN1_BIU_GATE 0x000001B3 + +// CRU_GATE_CON28(Offset:0x870) +#define ACLK_RKNN2_GATE 0x000001C0 +#define ACLK_RKNN2_BIU_GATE 0x000001C1 +#define HCLK_RKNN2_GATE 0x000001C2 +#define HCLK_RKNN2_BIU_GATE 0x000001C3 + +// CRU_GATE_CON29(Offset:0x874) +#define HCLK_RKNN_ROOT_GATE 0x000001D0 +#define CLK_RKNN_DSU0_DF_GATE 0x000001D1 +#define CLK_TESTOUT_NPU_GATE 0x000001D2 +#define CLK_RKNN_DSU0_GATE 0x000001D3 +#define PCLK_NPUTOP_ROOT_GATE 0x000001D4 +#define PCLK_NPUTOP_BIU_GATE 0x000001D5 +#define PCLK_NPU_TIMER_GATE 0x000001D6 +#define CLK_NPUTIMER_ROOT_GATE 0x000001D7 +#define CLK_NPUTIMER0_GATE 0x000001D8 +#define CLK_NPUTIMER1_GATE 0x000001D9 +#define PCLK_NPU_WDT_GATE 0x000001DA +#define TCLK_NPU_WDT_GATE 0x000001DB +#define PCLK_PVTM1_GATE 0x000001DC +#define PCLK_NPU_GRF_GATE 0x000001DD +#define CLK_PVTM1_GATE 0x000001DE +#define CLK_NPU_PVTM_GATE 0x000001DF + +// CRU_GATE_CON30(Offset:0x878) +#define CLK_NPU_PVTPLL_GATE 0x000001E0 +#define HCLK_NPU_CM0_ROOT_GATE 0x000001E1 +#define HCLK_NPU_CM0_BIU_GATE 0x000001E2 +#define FCLK_NPU_CM0_CORE_GATE 0x000001E3 +#define CLK_NPU_CM0_RTC_GATE 0x000001E5 +#define ACLK_RKNN0_GATE 0x000001E6 +#define ACLK_RKNN0_BIU_GATE 0x000001E7 +#define HCLK_RKNN0_GATE 0x000001E8 +#define HCLK_RKNN0_BIU_GATE 0x000001E9 + +// CRU_GATE_CON31(Offset:0x87C) +#define HCLK_NVM_ROOT_GATE 0x000001F0 +#define ACLK_NVM_ROOT_GATE 0x000001F1 +#define HCLK_NVM_BIU_GATE 0x000001F2 +#define ACLK_NVM_BIU_GATE 0x000001F3 +#define HCLK_EMMC_GATE 0x000001F4 +#define ACLK_EMMC_GATE 0x000001F5 +#define CCLK_EMMC_GATE 0x000001F6 +#define BCLK_EMMC_GATE 0x000001F7 +#define TMCLK_EMMC_GATE 0x000001F8 +#define SCLK_SFC_GATE 0x000001F9 +#define HCLK_SFC_GATE 0x000001FA +#define HCLK_SFC_XIP_GATE 0x000001FB + +// CRU_GATE_CON32(Offset:0x880) +#define PCLK_PHP_ROOT_GATE 0x00000200 +#define PCLK_GRF_GATE 0x00000201 +#define PCLK_DEC_BIU_GATE 0x00000202 +#define PCLK_GMAC0_GATE 0x00000203 +#define PCLK_GMAC1_GATE 0x00000204 +#define PCLK_PHP_BIU_GATE 0x00000205 +#define ACLK_PCIE_ROOT_GATE 0x00000206 +#define ACLK_PHP_ROOT_GATE 0x00000207 +#define ACLK_PCIE_BRIDGE_GATE 0x00000208 +#define ACLK_PHP_BIU_GATE 0x00000209 +#define ACLK_GMAC0_GATE 0x0000020A +#define ACLK_GMAC1_GATE 0x0000020B +#define ACLK_PCIE_BIU_GATE 0x0000020C +#define ACLK_PCIE_4L_DBI_GATE 0x0000020D +#define ACLK_PCIE_2L_DBI_GATE 0x0000020E +#define ACLK_PCIE_1L0_DBI_GATE 0x0000020F + +// CRU_GATE_CON33(Offset:0x884) +#define ACLK_PCIE_1L1_DBI_GATE 0x00000210 +#define ACLK_PCIE_1L2_DBI_GATE 0x00000211 +#define ACLK_PCIE_4L_MSTR_GATE 0x00000212 +#define ACLK_PCIE_2L_MSTR_GATE 0x00000213 +#define ACLK_PCIE_1L0_MSTR_GATE 0x00000214 +#define ACLK_PCIE_1L1_MSTR_GATE 0x00000215 +#define ACLK_PCIE_1L2_MSTR_GATE 0x00000216 +#define ACLK_PCIE_4L_SLV_GATE 0x00000217 +#define ACLK_PCIE_2L_SLV_GATE 0x00000218 +#define ACLK_PCIE_1L0_SLV_GATE 0x00000219 +#define ACLK_PCIE_1L1_SLV_GATE 0x0000021A +#define ACLK_PCIE_1L2_SLV_GATE 0x0000021B +#define PCLK_PCIE_4L_GATE 0x0000021C +#define PCLK_PCIE_2L_GATE 0x0000021D +#define PCLK_PCIE_1L0_GATE 0x0000021E +#define PCLK_PCIE_1L1_GATE 0x0000021F + +// CRU_GATE_CON34(Offset:0x888) +#define PCLK_PCIE_1L2_GATE 0x00000220 +#define CLK_PCIE_4L_AUX_GATE 0x00000221 +#define CLK_PCIE_2L_AUX_GATE 0x00000222 +#define CLK_PCIE_1L0_AUX_GATE 0x00000223 +#define CLK_PCIE_1L1_AUX_GATE 0x00000224 +#define CLK_PCIE_1L2_AUX_GATE 0x00000225 +#define ACLK_PHP_GIC_ITS_GATE 0x00000226 +#define ACLK_MMU_PCIE_GATE 0x00000227 +#define ACLK_MMU_PHP_GATE 0x00000228 +#define ACLK_MMU_BIU_GATE 0x00000229 +#define CLK_GMAC0_PTP_REF_GATE 0x0000022A +#define CLK_GMAC1_PTP_REF_GATE 0x0000022B + +// CRU_GATE_CON35(Offset:0x88C) +#define CLK_GMAC_125M_CRU_GATE 0x00000235 +#define CLK_GMAC_50M_CRU_GATE 0x00000236 +#define ACLK_USB3OTG2_GATE 0x00000237 +#define SUSPEND_CLK_USB3OTG2_GATE 0x00000238 +#define REF_CLK_USB3OTG2_GATE 0x00000239 +#define CLK_UTMI_OTG2_GATE 0x0000023A + +// CRU_GATE_CON37(Offset:0x894) +#define CLK_PIPEPHY0_REF_GATE 0x00000250 +#define CLK_PIPEPHY1_REF_GATE 0x00000251 +#define CLK_PIPEPHY2_REF_GATE 0x00000252 +#define CLK_PMALIVE0_GATE 0x00000254 +#define CLK_PMALIVE1_GATE 0x00000255 +#define CLK_PMALIVE2_GATE 0x00000256 +#define ACLK_SATA0_GATE 0x00000257 +#define ACLK_SATA1_GATE 0x00000258 +#define ACLK_SATA2_GATE 0x00000259 +#define CLK_RXOOB0_GATE 0x0000025A +#define CLK_RXOOB1_GATE 0x0000025B +#define CLK_RXOOB2_GATE 0x0000025C + +// CRU_GATE_CON38(Offset:0x898) +#define CLK_PIPEPHY0_PIPE_G_GATE 0x00000263 +#define CLK_PIPEPHY1_PIPE_G_GATE 0x00000264 +#define CLK_PIPEPHY2_PIPE_G_GATE 0x00000265 +#define CLK_PIPEPHY0_PIPE_ASIC_G_GATE 0x00000266 +#define CLK_PIPEPHY1_PIPE_ASIC_G_GATE 0x00000267 +#define CLK_PIPEPHY2_PIPE_ASIC_G_GATE 0x00000268 +#define CLK_PIPEPHY2_PIPE_U3_G_GATE 0x00000269 +#define CLK_PCIE_1L2_PIPE_GATE 0x0000026D +#define CLK_PCIE_1L0_PIPE_GATE 0x0000026E +#define CLK_PCIE_1L1_PIPE_GATE 0x0000026F + +// CRU_GATE_CON39(Offset:0x89C) +#define CLK_PCIE_4L_PIPE_GATE 0x00000270 +#define CLK_PCIE_2L_PIPE_GATE 0x00000271 + +// CRU_GATE_CON40(Offset:0x8A0) +#define HCLK_RKVDEC0_ROOT_GATE 0x00000280 +#define ACLK_RKVDEC0_ROOT_GATE 0x00000281 +#define ACLK_RKVDEC_CCU_GATE 0x00000282 +#define HCLK_RKVDEC0_GATE 0x00000283 +#define ACLK_RKVDEC0_GATE 0x00000284 +#define HCLK_RKVDEC0_BIU_GATE 0x00000285 +#define ACLK_RKVDEC0_BIU_GATE 0x00000286 +#define CLK_RKVDEC0_CA_GATE 0x00000287 +#define CLK_RKVDEC0_HEVC_CA_GATE 0x00000288 +#define CLK_RKVDEC0_CORE_GATE 0x00000289 + +// CRU_GATE_CON41(Offset:0x8A4) +#define HCLK_RKVDEC1_ROOT_GATE 0x00000290 +#define ACLK_RKVDEC1_ROOT_GATE 0x00000291 +#define HCLK_RKVDEC1_GATE 0x00000292 +#define ACLK_RKVDEC1_GATE 0x00000293 +#define HCLK_RKVDEC1_BIU_GATE 0x00000294 +#define ACLK_RKVDEC1_BIU_GATE 0x00000295 +#define CLK_RKVDEC1_CA_GATE 0x00000296 +#define CLK_RKVDEC1_HEVC_CA_GATE 0x00000297 +#define CLK_RKVDEC1_CORE_GATE 0x00000298 + +// CRU_GATE_CON42(Offset:0x8A8) +#define ACLK_USB_ROOT_GATE 0x000002A0 +#define HCLK_USB_ROOT_GATE 0x000002A1 +#define ACLK_USB_BIU_GATE 0x000002A2 +#define HCLK_USB_BIU_GATE 0x000002A3 +#define ACLK_USB3OTG0_GATE 0x000002A4 +#define SUSPEND_CLK_USB3OTG0_GATE 0x000002A5 +#define REF_CLK_USB3OTG0_GATE 0x000002A6 +#define ACLK_USB3OTG1_GATE 0x000002A7 +#define SUSPEND_CLK_USB3OTG1_GATE 0x000002A8 +#define REF_CLK_USB3OTG1_GATE 0x000002A9 +#define HCLK_HOST0_GATE 0x000002AA +#define HCLK_HOST_ARB0_GATE 0x000002AB +#define HCLK_HOST1_GATE 0x000002AC +#define HCLK_HOST_ARB1_GATE 0x000002AD +#define ACLK_USB_GRF_GATE 0x000002AE +#define UTMI_OHCI_CLK48_HOST0_GATE 0x000002AF + +// CRU_GATE_CON43(Offset:0x8AC) +#define UTMI_OHCI_CLK48_HOST1_GATE 0x000002B0 + +// CRU_GATE_CON44(Offset:0x8B0) +#define ACLK_VDPU_ROOT_GATE 0x000002C0 +#define ACLK_VDPU_LOW_ROOT_GATE 0x000002C1 +#define HCLK_VDPU_ROOT_GATE 0x000002C2 +#define ACLK_JPEG_DECODER_ROOT_GATE 0x000002C3 +#define ACLK_VDPU_BIU_GATE 0x000002C4 +#define ACLK_VDPU_LOW_BIU_GATE 0x000002C5 +#define HCLK_VDPU_BIU_GATE 0x000002C6 +#define ACLK_JPEG_DECODER_BIU_GATE 0x000002C7 +#define ACLK_VPU_GATE 0x000002C8 +#define HCLK_VPU_GATE 0x000002C9 +#define ACLK_JPEG_ENCODER0_GATE 0x000002CA +#define HCLK_JPEG_ENCODER0_GATE 0x000002CB +#define ACLK_JPEG_ENCODER1_GATE 0x000002CC +#define HCLK_JPEG_ENCODER1_GATE 0x000002CD +#define ACLK_JPEG_ENCODER2_GATE 0x000002CE +#define HCLK_JPEG_ENCODER2_GATE 0x000002CF + +// CRU_GATE_CON45(Offset:0x8B4) +#define ACLK_JPEG_ENCODER3_GATE 0x000002D0 +#define HCLK_JPEG_ENCODER3_GATE 0x000002D1 +#define ACLK_JPEG_DECODER_GATE 0x000002D2 +#define HCLK_JPEG_DECODER_GATE 0x000002D3 +#define HCLK_IEP2P0_GATE 0x000002D4 +#define ACLK_IEP2P0_GATE 0x000002D5 +#define CLK_IEP2P0_CORE_GATE 0x000002D6 +#define HCLK_RGA2_GATE 0x000002D7 +#define ACLK_RGA2_GATE 0x000002D8 +#define CLK_RGA2_CORE_GATE 0x000002D9 +#define HCLK_RGA3_0_GATE 0x000002DA +#define ACLK_RGA3_0_GATE 0x000002DB +#define CLK_RGA3_0_CORE_GATE 0x000002DC + +// CRU_GATE_CON47(Offset:0x8BC) +#define HCLK_RKVENC0_ROOT_GATE 0x000002F0 +#define ACLK_RKVENC0_ROOT_GATE 0x000002F1 +#define HCLK_RKVENC0_BIU_GATE 0x000002F2 +#define ACLK_RKVENC0_BIU_GATE 0x000002F3 +#define HCLK_RKVENC0_GATE 0x000002F4 +#define ACLK_RKVENC0_GATE 0x000002F5 +#define CLK_RKVENC0_CORE_GATE 0x000002F6 + +// CRU_GATE_CON48(Offset:0x8C0) +#define HCLK_RKVENC1_ROOT_GATE 0x00000300 +#define ACLK_RKVENC1_ROOT_GATE 0x00000301 +#define HCLK_RKVENC1_BIU_GATE 0x00000302 +#define ACLK_RKVENC1_BIU_GATE 0x00000303 +#define HCLK_RKVENC1_GATE 0x00000304 +#define ACLK_RKVENC1_GATE 0x00000305 +#define CLK_RKVENC1_CORE_GATE 0x00000306 + +// CRU_GATE_CON49(Offset:0x8C4) +#define ACLK_VI_ROOT_GATE 0x00000310 +#define HCLK_VI_ROOT_GATE 0x00000311 +#define PCLK_VI_ROOT_GATE 0x00000312 +#define ACLK_VI_BIU_GATE 0x00000313 +#define HCLK_VI_BIU_GATE 0x00000314 +#define PCLK_VI_BIU_GATE 0x00000315 +#define DCLK_VICAP_GATE 0x00000316 +#define ACLK_VICAP_GATE 0x00000317 +#define HCLK_VICAP_GATE 0x00000318 +#define CLK_ISP0_CORE_GATE 0x00000319 +#define CLK_ISP0_CORE_MARVIN_GATE 0x0000031A +#define CLK_ISP0_CORE_VICAP_GATE 0x0000031B +#define ACLK_ISP0_GATE 0x0000031C +#define HCLK_ISP0_GATE 0x0000031D +#define ACLK_FISHEYE0_GATE 0x0000031E +#define HCLK_FISHEYE0_GATE 0x0000031F + +// CRU_GATE_CON50(Offset:0x8C8) +#define CLK_FISHEYE0_CORE_GATE 0x00000320 +#define ACLK_FISHEYE1_GATE 0x00000321 +#define HCLK_FISHEYE1_GATE 0x00000322 +#define CLK_FISHEYE1_CORE_GATE 0x00000323 +#define PCLK_CSI_HOST_0_GATE 0x00000324 +#define PCLK_CSI_HOST_1_GATE 0x00000325 +#define PCLK_CSI_HOST_2_GATE 0x00000326 +#define PCLK_CSI_HOST_3_GATE 0x00000327 +#define PCLK_CSI_HOST_4_GATE 0x00000328 +#define PCLK_CSI_HOST_5_GATE 0x00000329 + +// CRU_GATE_CON51(Offset:0x8CC) +#define CLK_CSIHOST0_VICAP_GATE 0x00000334 +#define CLK_CSIHOST1_VICAP_GATE 0x00000335 +#define CLK_CSIHOST2_VICAP_GATE 0x00000336 +#define CLK_CSIHOST3_VICAP_GATE 0x00000337 +#define CLK_CSIHOST4_VICAP_GATE 0x00000338 +#define CLK_CSIHOST5_VICAP_GATE 0x00000339 +#define ICLK_CSIHOST01_GATE 0x0000033A +#define ICLK_CSIHOST0_GATE 0x0000033B +#define ICLK_CSIHOST1_GATE 0x0000033C + +// CRU_GATE_CON52(Offset:0x8D0) +#define ACLK_VOP_ROOT_GATE 0x00000340 +#define ACLK_VOP_LOW_ROOT_GATE 0x00000341 +#define HCLK_VOP_ROOT_GATE 0x00000342 +#define PCLK_VOP_ROOT_GATE 0x00000343 +#define ACLK_VOP_BIU_GATE 0x00000344 +#define ACLK_VOP_LOW_BIU_GATE 0x00000345 +#define HCLK_VOP_BIU_GATE 0x00000346 +#define PCLK_VOP_BIU_GATE 0x00000347 +#define HCLK_VOP_GATE 0x00000348 +#define ACLK_VOP_GATE 0x00000349 +#define DCLK_VOP0_SRC_GATE 0x0000034A +#define DCLK_VOP1_SRC_GATE 0x0000034B +#define DCLK_VOP2_SRC_GATE 0x0000034C +#define DCLK_VOP0_GATE 0x0000034D + +// CRU_GATE_CON53(Offset:0x8D4) +#define DCLK_VOP1_GATE 0x00000350 +#define DCLK_VOP2_GATE 0x00000351 +#define DCLK_VOP3_GATE 0x00000352 +#define PCLK_VOPGRF_GATE 0x00000353 +#define PCLK_DSIHOST0_GATE 0x00000354 +#define PCLK_DSIHOST1_GATE 0x00000355 +#define CLK_DSIHOST0_GATE 0x00000356 +#define CLK_DSIHOST1_GATE 0x00000357 +#define CLK_VOP_PMU_GATE 0x00000358 +#define PCLK_VOP_CHANNEL_BIU_GATE 0x00000359 +#define ACLK_VOP_DOBY_GATE 0x0000035A + +// CRU_GATE_CON55(Offset:0x8DC) +#define ACLK_VO0_ROOT_GATE 0x00000370 +#define HCLK_VO0_ROOT_GATE 0x00000371 +#define HCLK_VO0_S_ROOT_GATE 0x00000372 +#define PCLK_VO0_ROOT_GATE 0x00000373 +#define PCLK_VO0_S_ROOT_GATE 0x00000374 +#define HCLK_VO0_BIU_GATE 0x00000375 +#define HCLK_VO0_S_BIU_GATE 0x00000376 +#define PCLK_VO0_BIU_GATE 0x00000377 +#define PCLK_VO0_S_BIU_GATE 0x00000378 +#define ACLK_HDCP0_BIU_GATE 0x00000379 +#define PCLK_VO0GRF_GATE 0x0000037A +#define HCLK_HDCP_KEY0_GATE 0x0000037B +#define ACLK_HDCP0_GATE 0x0000037C +#define HCLK_HDCP0_GATE 0x0000037D +#define PCLK_HDCP0_GATE 0x0000037E + +// CRU_GATE_CON56(Offset:0x8E0) +#define ACLK_TRNG0_GATE 0x00000380 +#define PCLK_TRNG0_GATE 0x00000381 +#define CLK_AUX16MHZ_0_GATE 0x00000382 +#define CLK_AUX16MHZ_1_GATE 0x00000383 +#define PCLK_DP0_GATE 0x00000384 +#define PCLK_DP1_GATE 0x00000385 +#define PCLK_S_DP0_GATE 0x00000386 +#define PCLK_S_DP1_GATE 0x00000387 +#define CLK_DP0_GATE 0x00000388 +#define CLK_DP1_GATE 0x00000389 +#define HCLK_I2S4_8CH_GATE 0x0000038A +#define CLK_I2S4_8CH_TX_GATE 0x0000038B +#define CLK_I2S4_8CH_FRAC_TX_GATE 0x0000038C +#define MCLK_I2S4_8CH_TX_GATE 0x0000038D +#define HCLK_I2S8_8CH_GATE 0x0000038E +#define CLK_I2S8_8CH_TX_GATE 0x0000038F + +// CRU_GATE_CON57(Offset:0x8E4) +#define CLK_I2S8_8CH_FRAC_TX_GATE 0x00000390 +#define MCLK_I2S8_8CH_TX_GATE 0x00000391 +#define HCLK_SPDIF2_DP0_GATE 0x00000392 +#define CLK_SPDIF2_DP0_GATE 0x00000393 +#define CLK_SPDIF2_DP0_FRAC_GATE 0x00000394 +#define MCLK_SPDIF2_DP0_GATE 0x00000395 +#define MCLK_SPDIF2_GATE 0x00000396 +#define HCLK_SPDIF5_DP1_GATE 0x00000397 +#define CLK_SPDIF5_DP1_GATE 0x00000398 +#define CLK_SPDIF5_DP1_FRAC_GATE 0x00000399 +#define MCLK_SPDIF5_DP1_GATE 0x0000039A +#define MCLK_SPDIF5_GATE 0x0000039B + +// CRU_GATE_CON59(Offset:0x8EC) +#define ACLK_HDCP1_ROOT_GATE 0x000003B0 +#define ACLK_HDMIRX_ROOT_GATE 0x000003B1 +#define HCLK_VO1_ROOT_GATE 0x000003B2 +#define HCLK_VO1_S_ROOT_GATE 0x000003B3 +#define PCLK_VO1_ROOT_GATE 0x000003B4 +#define PCLK_VO1_S_ROOT_GATE 0x000003B5 +#define ACLK_HDCP1_BIU_GATE 0x000003B6 +#define ACLK_VO1_BIU_GATE 0x000003B8 +#define HCLK_VO1_BIU_GATE 0x000003B9 +#define HCLK_VO1_S_BIU_GATE 0x000003BA +#define PCLK_VO1_BIU_GATE 0x000003BB +#define PCLK_VO1GRF_GATE 0x000003BC +#define PCLK_VO1_S_BIU_GATE 0x000003BD +#define PCLK_S_EDP0_GATE 0x000003BE +#define PCLK_S_EDP1_GATE 0x000003BF + +// CRU_GATE_CON60(Offset:0x8F0) +#define HCLK_I2S7_8CH_GATE 0x000003C0 +#define CLK_I2S7_8CH_RX_GATE 0x000003C1 +#define CLK_I2S7_8CH_FRAC_RX_GATE 0x000003C2 +#define MCLK_I2S7_8CH_RX_GATE 0x000003C3 +#define HCLK_HDCP_KEY1_GATE 0x000003C4 +#define ACLK_HDCP1_GATE 0x000003C5 +#define HCLK_HDCP1_GATE 0x000003C6 +#define PCLK_HDCP1_GATE 0x000003C7 +#define ACLK_TRNG1_GATE 0x000003C9 +#define PCLK_TRNG1_GATE 0x000003CA +#define PCLK_HDMITX0_GATE 0x000003CB +#define CLK_HDMITX0_EARC_GATE 0x000003CF + +// CRU_GATE_CON61(Offset:0x8F4) +#define CLK_HDMITX0_REF_GATE 0x000003D0 +#define PCLK_HDMITX1_GATE 0x000003D2 +#define CLK_HDMITX1_EARC_GATE 0x000003D6 +#define CLK_HDMITX1_REF_GATE 0x000003D7 +#define ACLK_HDMIRX_GATE 0x000003D9 +#define PCLK_HDMIRX_GATE 0x000003DA +#define CLK_HDMIRX_REF_GATE 0x000003DB +#define CLK_HDMIRX_AUD_SRC_GATE 0x000003DC +#define CLK_HDMIRX_AUD_FRAC_GATE 0x000003DD +#define CLK_HDMIRX_AUD_GATE 0x000003DE +#define CLK_HDMIRX_TMDSQP_GATE 0x000003DF + +// CRU_GATE_CON62(Offset:0x8F8) +#define PCLK_EDP0_GATE 0x000003E0 +#define CLK_EDP0_24M_GATE 0x000003E1 +#define CLK_EDP0_200M_GATE 0x000003E2 +#define PCLK_EDP1_GATE 0x000003E3 +#define CLK_EDP1_24M_GATE 0x000003E4 +#define CLK_EDP1_200M_GATE 0x000003E5 +#define CLK_I2S5_8CH_TX_GATE 0x000003E6 +#define CLK_I2S5_8CH_FRAC_TX_GATE 0x000003E7 +#define MCLK_I2S5_8CH_TX_GATE 0x000003E8 +#define HCLK_I2S5_8CH_GATE 0x000003EC +#define CLK_I2S6_8CH_TX_GATE 0x000003ED +#define CLK_I2S6_8CH_FRAC_TX_GATE 0x000003EE +#define MCLK_I2S6_8CH_TX_GATE 0x000003EF + +// CRU_GATE_CON63(Offset:0x8FC) +#define CLK_I2S6_8CH_RX_GATE 0x000003F0 +#define CLK_I2S6_8CH_FRAC_RX_GATE 0x000003F1 +#define MCLK_I2S6_8CH_RX_GATE 0x000003F2 +#define HCLK_I2S6_8CH_GATE 0x000003F3 +#define HCLK_SPDIF3_GATE 0x000003F4 +#define CLK_SPDIF3_GATE 0x000003F5 +#define CLK_SPDIF3_FRAC_GATE 0x000003F6 +#define MCLK_SPDIF3_GATE 0x000003F7 +#define HCLK_SPDIF4_GATE 0x000003F8 +#define CLK_SPDIF4_GATE 0x000003F9 +#define CLK_SPDIF4_FRAC_GATE 0x000003FA +#define MCLK_SPDIF4_GATE 0x000003FB +#define HCLK_SPDIFRX0_GATE 0x000003FC +#define MCLK_SPDIFRX0_GATE 0x000003FD +#define HCLK_SPDIFRX1_GATE 0x000003FE +#define MCLK_SPDIFRX1_GATE 0x000003FF + +// CRU_GATE_CON64(Offset:0x900) +#define HCLK_SPDIFRX2_GATE 0x00000400 +#define MCLK_SPDIFRX2_GATE 0x00000401 +#define DCLK_VOP2HDMI_BRIDGE0_VO1_GATE 0x0000040E +#define DCLK_VOP2HDMI_BRIDGE1_VO1_GATE 0x0000040F + +// CRU_GATE_CON65(Offset:0x904) +#define HCLK_I2S9_8CH_GATE 0x00000410 +#define CLK_I2S9_8CH_RX_GATE 0x00000411 +#define CLK_I2S9_8CH_FRAC_RX_GATE 0x00000412 +#define MCLK_I2S9_8CH_RX_GATE 0x00000413 +#define HCLK_I2S10_8CH_GATE 0x00000414 +#define CLK_I2S10_8CH_RX_GATE 0x00000415 +#define CLK_I2S10_8CH_FRAC_RX_GATE 0x00000416 +#define MCLK_I2S10_8CH_RX_GATE 0x00000417 +#define PCLK_S_HDMIRX_GATE 0x00000418 +#define CLK_HDMITRX_REFSRC_GATE 0x00000419 + +// CRU_GATE_CON66(Offset:0x908) +#define CLK_GPU_SRC_DF_GATE 0x00000421 +#define CLK_TESTOUT_GPU_GATE 0x00000422 +#define CLK_GPU_SRC_GATE 0x00000423 +#define CLK_GPU_GATE 0x00000424 +#define CLK_GPU_COREGROUP_GATE 0x00000426 +#define CLK_GPU_STACKS_GATE 0x00000427 +#define ACLK_S_GPU_BIU_GATE 0x00000428 +#define ACLK_M0_GPU_BIU_GATE 0x00000429 +#define ACLK_M1_GPU_BIU_GATE 0x0000042A +#define ACLK_M2_GPU_BIU_GATE 0x0000042B +#define ACLK_M3_GPU_BIU_GATE 0x0000042C +#define PCLK_GPU_ROOT_GATE 0x0000042D +#define PCLK_GPU_BIU_GATE 0x0000042E +#define PCLK_PVTM2_GATE 0x0000042F + +// CRU_GATE_CON67(Offset:0x90C) +#define CLK_PVTM2_GATE 0x00000430 +#define CLK_GPU_PVTM_GATE 0x00000431 +#define PCLK_GPU_GRF_GATE 0x00000432 +#define CLK_GPU_PVTPLL_GATE 0x00000433 + +// CRU_GATE_CON68(Offset:0x910) +#define ACLK_AV1_ROOT_GATE 0x00000440 +#define ACLK_AV1_BIU_GATE 0x00000441 +#define ACLK_AV1_GATE 0x00000442 +#define PCLK_AV1_ROOT_GATE 0x00000443 +#define PCLK_AV1_BIU_GATE 0x00000444 +#define PCLK_AV1_GATE 0x00000445 + +// CRU_GATE_CON69(Offset:0x914) +#define ACLK_CENTER_ROOT_GATE 0x00000450 +#define ACLK_CENTER_LOW_ROOT_GATE 0x00000451 +#define HCLK_CENTER_ROOT_GATE 0x00000452 +#define PCLK_CENTER_ROOT_GATE 0x00000453 +#define ACLK_DDR_BIU_GATE 0x00000454 +#define ACLK_DMA2DDR_GATE 0x00000455 +#define ACLK_DDR_SHAREMEM_GATE 0x00000456 +#define ACLK_DDR_SHAREMEM_BIU_GATE 0x00000457 +#define ACLK_CENTER_S200_ROOT_GATE 0x00000458 +#define ACLK_CENTER_S400_ROOT_GATE 0x00000459 +#define ACLK_CENTER_S200_BIU_GATE 0x0000045A +#define ACLK_CENTER_S400_BIU_GATE 0x0000045B +#define HCLK_AHB2APB_GATE 0x0000045C +#define HCLK_CENTER_BIU_GATE 0x0000045D +#define FCLK_DDR_CM0_CORE_GATE 0x0000045E +#define CLK_DDR_TIMER_ROOT_GATE 0x0000045F + +// CRU_GATE_CON70(Offset:0x918) +#define CLK_DDR_TIMER0_GATE 0x00000460 +#define CLK_DDR_TIMER1_GATE 0x00000461 +#define TCLK_WDT_DDR_GATE 0x00000462 +#define CLK_DDR_CM0_RTC_GATE 0x00000464 +#define PCLK_CENTER_GRF_GATE 0x00000465 +#define PCLK_AHB2APB_GATE 0x00000466 +#define PCLK_WDT_GATE 0x00000467 +#define PCLK_TIMER_GATE 0x00000468 +#define PCLK_DMA2DDR_GATE 0x00000469 +#define PCLK_SHAREMEM_GATE 0x0000046A +#define PCLK_CENTER_BIU_GATE 0x0000046B +#define PCLK_CENTER_CHANNEL_BIU_GATE 0x0000046C + +// CRU_GATE_CON72(Offset:0x920) +#define PCLK_USBDPGRF0_GATE 0x00000481 +#define PCLK_USBDPPHY0_GATE 0x00000482 +#define PCLK_USBDPGRF1_GATE 0x00000483 +#define PCLK_USBDPPHY1_GATE 0x00000484 +#define PCLK_HDPTX0_GATE 0x00000485 +#define PCLK_HDPTX1_GATE 0x00000486 +#define PCLK_APB2ASB_SLV_BOT_RIGHT_GATE 0x00000487 +#define PCLK_USB2PHY_U3_0_GRF0_GATE 0x00000488 +#define PCLK_USB2PHY_U3_1_GRF0_GATE 0x00000489 +#define PCLK_USB2PHY_U2_0_GRF0_GATE 0x0000048A +#define PCLK_USB2PHY_U2_1_GRF0_GATE 0x0000048B + +// CRU_GATE_CON73(Offset:0x924) +#define CLK_HDMIHDP0_GATE 0x0000049C +#define CLK_HDMIHDP1_GATE 0x0000049D + +// CRU_GATE_CON74(Offset:0x928) +#define ACLK_VO1USB_TOP_ROOT_GATE 0x000004A0 +#define ACLK_VO1USB_TOP_BIU_GATE 0x000004A1 +#define HCLK_VO1USB_TOP_ROOT_GATE 0x000004A2 +#define HCLK_VO1USB_TOP_BIU_GATE 0x000004A3 + +// CRU_GATE_CON75(Offset:0x92C) +#define HCLK_SDIO_ROOT_GATE 0x000004B0 +#define HCLK_SDIO_BIU_GATE 0x000004B1 +#define HCLK_SDIO_GATE 0x000004B2 +#define CCLK_SRC_SDIO_GATE 0x000004B3 + +// CRU_GATE_CON76(Offset:0x930) +#define ACLK_RGA3_ROOT_GATE 0x000004C0 +#define HCLK_RGA3_ROOT_GATE 0x000004C1 +#define HCLK_RGA3_BIU_GATE 0x000004C2 +#define ACLK_RGA3_BIU_GATE 0x000004C3 +#define HCLK_RGA3_1_GATE 0x000004C4 +#define ACLK_RGA3_1_GATE 0x000004C5 +#define CLK_RGA3_1_CORE_GATE 0x000004C6 + +// CRU_GATE_CON77(Offset:0x934) +#define CLK_REF_PIPE_PHY0_OSC_SRC_GATE 0x000004D0 +#define CLK_REF_PIPE_PHY1_OSC_SRC_GATE 0x000004D1 +#define CLK_REF_PIPE_PHY2_OSC_SRC_GATE 0x000004D2 +#define CLK_REF_PIPE_PHY0_PLL_SRC_GATE 0x000004D3 +#define CLK_REF_PIPE_PHY1_PLL_SRC_GATE 0x000004D4 +#define CLK_REF_PIPE_PHY2_PLL_SRC_GATE 0x000004D5 + +// CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_MATRIX_50M_SRC_DIV 0x05000000 +#define CLK_MATRIX_100M_SRC_DIV 0x05060000 +#define CLK_MATRIX_50M_SRC_SEL 0x01050000 +#define CLK_MATRIX_50M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_50M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_100M_SRC_SEL 0x010B0000 +#define CLK_MATRIX_100M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_100M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON01(Offset:0x304) +#define CLK_MATRIX_150M_SRC_DIV 0x05000001 +#define CLK_MATRIX_200M_SRC_DIV 0x05060001 +#define CLK_MATRIX_150M_SRC_SEL 0x01050001 +#define CLK_MATRIX_150M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_150M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_200M_SRC_SEL 0x010B0001 +#define CLK_MATRIX_200M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_200M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON02(Offset:0x308) +#define CLK_MATRIX_250M_SRC_DIV 0x05000002 +#define CLK_MATRIX_300M_SRC_DIV 0x05060002 +#define CLK_MATRIX_250M_SRC_SEL 0x01050002 +#define CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_300M_SRC_SEL 0x010B0002 +#define CLK_MATRIX_300M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_300M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON03(Offset:0x30C) +#define CLK_MATRIX_350M_SRC_DIV 0x05000003 +#define CLK_MATRIX_400M_SRC_DIV 0x05060003 +#define CLK_MATRIX_350M_SRC_SEL 0x01050003 +#define CLK_MATRIX_350M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_350M_SRC_SEL_CLK_SPLL_MUX 1U +#define CLK_MATRIX_400M_SRC_SEL 0x010B0003 +#define CLK_MATRIX_400M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_400M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON04(Offset:0x310) +#define CLK_MATRIX_450M_SRC_DIV 0x05000004 +#define CLK_MATRIX_500M_SRC_DIV 0x05060004 +#define CLK_MATRIX_450M_SRC_SEL 0x01050004 +#define CLK_MATRIX_450M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_450M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_500M_SRC_SEL 0x010B0004 +#define CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON05(Offset:0x314) +#define CLK_MATRIX_600M_SRC_DIV 0x05000005 +#define CLK_MATRIX_650M_SRC_DIV 0x05060005 +#define CLK_MATRIX_600M_SRC_SEL 0x01050005 +#define CLK_MATRIX_600M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_600M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_650M_SRC_SEL 0x010B0005 +#define CLK_MATRIX_650M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_650M_SRC_SEL_CLK_LPLL_MUX 1U + +// CRU_CLKSEL_CON06(Offset:0x318) +#define CLK_MATRIX_700M_SRC_DIV 0x05000006 +#define CLK_MATRIX_800M_SRC_DIV 0x05060006 +#define CLK_MATRIX_700M_SRC_SEL 0x01050006 +#define CLK_MATRIX_700M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_700M_SRC_SEL_CLK_SPLL_MUX 1U +#define CLK_MATRIX_800M_SRC_SEL 0x010B0006 +#define CLK_MATRIX_800M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_800M_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON07(Offset:0x31C) +#define CLK_MATRIX_1000M_SRC_DIV 0x05000007 +#define CLK_MATRIX_1200M_SRC_DIV 0x05070007 +#define CLK_MATRIX_1000M_SRC_SEL 0x02050007 +#define CLK_MATRIX_1000M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_1000M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_MATRIX_1000M_SRC_SEL_CLK_NPLL_MUX 2U +#define CLK_MATRIX_1000M_SRC_SEL_CLK_V0PLL_MUX 3U +#define CLK_MATRIX_1200M_SRC_SEL 0x010C0007 +#define CLK_MATRIX_1200M_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_MATRIX_1200M_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON08(Offset:0x320) +#define ACLK_TOP_ROOT_DIV 0x05000008 +#define ACLK_LOW_TOP_ROOT_DIV 0x05090008 +#define ACLK_TOP_ROOT_SEL 0x02050008 +#define ACLK_TOP_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_TOP_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_TOP_ROOT_SEL_CLK_AUPLL_MUX 2U +#define PCLK_TOP_ROOT_SEL 0x02070008 +#define PCLK_TOP_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_TOP_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_TOP_ROOT_SEL_XIN_OSC0_FUNC 2U +#define ACLK_LOW_TOP_ROOT_SEL 0x010E0008 +#define ACLK_LOW_TOP_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_LOW_TOP_ROOT_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON09(Offset:0x324) +#define ACLK_TOP_M300_ROOT_SEL 0x02000009 +#define ACLK_TOP_M300_ROOT_SEL_CLK_MATRIX_300M_SRC 0U +#define ACLK_TOP_M300_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_TOP_M300_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_TOP_M300_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_TOP_M500_ROOT_SEL 0x02020009 +#define ACLK_TOP_M500_ROOT_SEL_CLK_MATRIX_500M_SRC 0U +#define ACLK_TOP_M500_ROOT_SEL_CLK_MATRIX_300M_SRC 1U +#define ACLK_TOP_M500_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_TOP_M500_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_TOP_M400_ROOT_SEL 0x02040009 +#define ACLK_TOP_M400_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define ACLK_TOP_M400_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_TOP_M400_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_TOP_M400_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_TOP_S200_ROOT_SEL 0x02060009 +#define ACLK_TOP_S200_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define ACLK_TOP_S200_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define ACLK_TOP_S200_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define ACLK_TOP_S200_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_TOP_S400_ROOT_SEL 0x02080009 +#define ACLK_TOP_S400_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define ACLK_TOP_S400_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_TOP_S400_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_TOP_S400_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON10(Offset:0x328) +#define CLK_TESTOUT_TOP_DIV 0x0600000A +#define CLK_TESTOUT_TOP_SEL 0x0306000A +#define CLK_TESTOUT_TOP_SEL_CLK_GPLL_MUX 0U +#define CLK_TESTOUT_TOP_SEL_CLK_CPLL_MUX 1U +#define CLK_TESTOUT_TOP_SEL_CLK_AUPLL_MUX 2U +#define CLK_TESTOUT_TOP_SEL_CLK_SPLL_MUX 3U +#define CLK_TESTOUT_TOP_SEL_CLK_V0PLL_MUX 4U +#define CLK_TESTOUT_TOP_SEL_CLK_DEEPSLOW 5U +#define CLK_TESTOUT_SEL 0x0309000A +#define CLK_TESTOUT_SEL_CLK_TESTOUT_GRP0 0U +#define CLK_TESTOUT_SEL_CLK_TESTOUT_B0 1U +#define CLK_TESTOUT_SEL_CLK_TESTOUT_B1 2U +#define CLK_TESTOUT_SEL_CLK_TESTOUT_L 3U +#define CLK_TESTOUT_SEL_CLK_TESTOUT_DDR01 4U +#define CLK_TESTOUT_SEL_CLK_TESTOUT_DDR23 5U +#define CLK_TESTOUT_GRP0_SEL 0x030C000A +#define CLK_TESTOUT_GRP0_SEL_CLK_REF_PIPE_PHY0 0U +#define CLK_TESTOUT_GRP0_SEL_CLK_REF_PIPE_PHY1 1U +#define CLK_TESTOUT_GRP0_SEL_CLK_REF_PIPE_PHY2 2U +#define CLK_TESTOUT_GRP0_SEL_CLK_TESTOUT_TOP 3U +#define CLK_TESTOUT_GRP0_SEL_CLK_TESTOUT_GPU 4U +#define CLK_TESTOUT_GRP0_SEL_CLK_TESTOUT_NPU 5U + +// CRU_CLKSEL_CON15(Offset:0x33C) +#define MCLK_GMAC0_OUT_DIV 0x0700000F +#define REFCLKO25M_ETH0_OUT_DIV 0x0708000F +#define MCLK_GMAC0_OUT_SEL 0x0107000F +#define MCLK_GMAC0_OUT_SEL_CLK_GPLL_MUX 0U +#define MCLK_GMAC0_OUT_SEL_CLK_CPLL_MUX 1U +#define REFCLKO25M_ETH0_OUT_SEL 0x010F000F +#define REFCLKO25M_ETH0_OUT_SEL_CLK_GPLL_MUX 0U +#define REFCLKO25M_ETH0_OUT_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON16(Offset:0x340) +#define REFCLKO25M_ETH1_OUT_DIV 0x07000010 +#define REFCLKO25M_ETH1_OUT_SEL 0x01070010 +#define REFCLKO25M_ETH1_OUT_SEL_CLK_GPLL_MUX 0U +#define REFCLKO25M_ETH1_OUT_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON17(Offset:0x344) +#define CLK_CIFOUT_OUT_DIV 0x08000011 +#define CLK_CIFOUT_OUT_SEL 0x02080011 +#define CLK_CIFOUT_OUT_SEL_CLK_GPLL_MUX 0U +#define CLK_CIFOUT_OUT_SEL_CLK_CPLL_MUX 1U +#define CLK_CIFOUT_OUT_SEL_XIN_OSC0_FUNC 2U +#define CLK_CIFOUT_OUT_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON18(Offset:0x348) +#define CLK_MIPI_CAMARAOUT_M0_DIV 0x08000012 +#define CLK_MIPI_CAMARAOUT_M0_SEL 0x02080012 +#define CLK_MIPI_CAMARAOUT_M0_SEL_XIN_OSC0_FUNC 0U +#define CLK_MIPI_CAMARAOUT_M0_SEL_CLK_SPLL_MUX 1U +#define CLK_MIPI_CAMARAOUT_M0_SEL_CLK_GPLL_MUX 2U +#define CLK_MIPI_CAMARAOUT_M0_SEL_CLK_CPLL_MUX 3U + +// CRU_CLKSEL_CON19(Offset:0x34C) +#define CLK_MIPI_CAMARAOUT_M1_DIV 0x08000013 +#define CLK_MIPI_CAMARAOUT_M1_SEL 0x02080013 +#define CLK_MIPI_CAMARAOUT_M1_SEL_XIN_OSC0_FUNC 0U +#define CLK_MIPI_CAMARAOUT_M1_SEL_CLK_SPLL_MUX 1U +#define CLK_MIPI_CAMARAOUT_M1_SEL_CLK_GPLL_MUX 2U +#define CLK_MIPI_CAMARAOUT_M1_SEL_CLK_CPLL_MUX 3U + +// CRU_CLKSEL_CON20(Offset:0x350) +#define CLK_MIPI_CAMARAOUT_M2_DIV 0x08000014 +#define CLK_MIPI_CAMARAOUT_M2_SEL 0x02080014 +#define CLK_MIPI_CAMARAOUT_M2_SEL_XIN_OSC0_FUNC 0U +#define CLK_MIPI_CAMARAOUT_M2_SEL_CLK_SPLL_MUX 1U +#define CLK_MIPI_CAMARAOUT_M2_SEL_CLK_GPLL_MUX 2U +#define CLK_MIPI_CAMARAOUT_M2_SEL_CLK_CPLL_MUX 3U + +// CRU_CLKSEL_CON21(Offset:0x354) +#define CLK_MIPI_CAMARAOUT_M3_DIV 0x08000015 +#define CLK_MIPI_CAMARAOUT_M3_SEL 0x02080015 +#define CLK_MIPI_CAMARAOUT_M3_SEL_XIN_OSC0_FUNC 0U +#define CLK_MIPI_CAMARAOUT_M3_SEL_CLK_SPLL_MUX 1U +#define CLK_MIPI_CAMARAOUT_M3_SEL_CLK_GPLL_MUX 2U +#define CLK_MIPI_CAMARAOUT_M3_SEL_CLK_CPLL_MUX 3U + +// CRU_CLKSEL_CON22(Offset:0x358) +#define CLK_MIPI_CAMARAOUT_M4_DIV 0x08000016 +#define CLK_MIPI_CAMARAOUT_M4_SEL 0x02080016 +#define CLK_MIPI_CAMARAOUT_M4_SEL_XIN_OSC0_FUNC 0U +#define CLK_MIPI_CAMARAOUT_M4_SEL_CLK_SPLL_MUX 1U +#define CLK_MIPI_CAMARAOUT_M4_SEL_CLK_GPLL_MUX 2U +#define CLK_MIPI_CAMARAOUT_M4_SEL_CLK_CPLL_MUX 3U + +// CRU_CLKSEL_CON24(Offset:0x360) +#define CLK_I2S0_8CH_TX_SRC_DIV 0x05040018 +#define HCLK_AUDIO_ROOT_SEL 0x02000018 +#define HCLK_AUDIO_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_AUDIO_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_AUDIO_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_AUDIO_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_AUDIO_ROOT_SEL 0x02020018 +#define PCLK_AUDIO_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_AUDIO_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_AUDIO_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_I2S0_8CH_TX_SRC_SEL 0x01090018 +#define CLK_I2S0_8CH_TX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S0_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON25(Offset:0x364) +#define CLK_I2S0_8CH_TX_FRAC_DIV 0x20000019 + +// CRU_CLKSEL_CON26(Offset:0x368) +#define CLK_I2S0_8CH_RX_SRC_DIV 0x0502001A +#define MCLK_I2S0_8CH_TX_SEL 0x0200001A +#define MCLK_I2S0_8CH_TX_SEL_CLK_I2S0_8CH_TX_SRC 0U +#define MCLK_I2S0_8CH_TX_SEL_CLK_I2S0_8CH_TX_FRAC 1U +#define MCLK_I2S0_8CH_TX_SEL_I2S0_MCLKIN 2U +#define MCLK_I2S0_8CH_TX_SEL_XIN_OSC0_HALF 3U +#define CLK_I2S0_8CH_RX_SRC_SEL 0x0107001A +#define CLK_I2S0_8CH_RX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S0_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON27(Offset:0x36C) +#define CLK_I2S0_8CH_RX_FRAC_DIV 0x2000001B + +// CRU_CLKSEL_CON28(Offset:0x370) +#define CLK_I2S2_2CH_SRC_DIV 0x0504001C +#define MCLK_I2S0_8CH_RX_SEL 0x0200001C +#define MCLK_I2S0_8CH_RX_SEL_CLK_I2S0_8CH_RX_SRC 0U +#define MCLK_I2S0_8CH_RX_SEL_CLK_I2S0_8CH_RX_FRAC 1U +#define MCLK_I2S0_8CH_RX_SEL_I2S0_MCLKIN 2U +#define MCLK_I2S0_8CH_RX_SEL_XIN_OSC0_HALF 3U +#define I2S0_8CH_MCLKOUT_SEL 0x0202001C +#define I2S0_8CH_MCLKOUT_SEL_MCLK_I2S0_8CH_TX 0U +#define I2S0_8CH_MCLKOUT_SEL_MCLK_I2S0_8CH_RX 1U +#define I2S0_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 2U +#define CLK_I2S2_2CH_SRC_SEL 0x0109001C +#define CLK_I2S2_2CH_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S2_2CH_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON29(Offset:0x374) +#define CLK_I2S2_2CH_FRAC_DIV 0x2000001D + +// CRU_CLKSEL_CON30(Offset:0x378) +#define CLK_I2S3_2CH_SRC_DIV 0x0503001E +#define MCLK_I2S2_2CH_SEL 0x0200001E +#define MCLK_I2S2_2CH_SEL_CLK_I2S2_2CH_SRC 0U +#define MCLK_I2S2_2CH_SEL_CLK_I2S2_2CH_FRAC 1U +#define MCLK_I2S2_2CH_SEL_I2S2_MCLKIN 2U +#define MCLK_I2S2_2CH_SEL_XIN_OSC0_HALF 3U +#define I2S2_2CH_MCLKOUT_SEL 0x0102001E +#define I2S2_2CH_MCLKOUT_SEL_MCLK_I2S2_2CH 0U +#define I2S2_2CH_MCLKOUT_SEL_XIN_OSC0_HALF 1U +#define CLK_I2S3_2CH_SRC_SEL 0x0108001E +#define CLK_I2S3_2CH_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S3_2CH_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON31(Offset:0x37C) +#define CLK_I2S3_2CH_FRAC_DIV 0x2000001F + +// CRU_CLKSEL_CON32(Offset:0x380) +#define CLK_SPDIF0_SRC_DIV 0x05030020 +#define MCLK_I2S3_2CH_SEL 0x02000020 +#define MCLK_I2S3_2CH_SEL_CLK_I2S3_2CH_SRC 0U +#define MCLK_I2S3_2CH_SEL_CLK_I2S3_2CH_FRAC 1U +#define MCLK_I2S3_2CH_SEL_I2S3_MCLKIN 2U +#define MCLK_I2S3_2CH_SEL_XIN_OSC0_HALF 3U +#define I2S3_2CH_MCLKOUT_SEL 0x01020020 +#define I2S3_2CH_MCLKOUT_SEL_MCLK_I2S3_2CH 0U +#define I2S3_2CH_MCLKOUT_SEL_XIN_OSC0_HALF 1U +#define CLK_SPDIF0_SRC_SEL 0x01080020 +#define CLK_SPDIF0_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF0_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON33(Offset:0x384) +#define CLK_SPDIF0_FRAC_DIV 0x20000021 + +// CRU_CLKSEL_CON34(Offset:0x388) +#define CLK_SPDIF1_SRC_DIV 0x05020022 +#define MCLK_SPDIF0_SEL 0x02000022 +#define MCLK_SPDIF0_SEL_CLK_SPDIF0_SRC 0U +#define MCLK_SPDIF0_SEL_CLK_SPDIF0_FRAC 1U +#define MCLK_SPDIF0_SEL_XIN_OSC0_HALF 2U +#define CLK_SPDIF1_SRC_SEL 0x01070022 +#define CLK_SPDIF1_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF1_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON35(Offset:0x38C) +#define CLK_SPDIF1_FRAC_DIV 0x20000023 + +// CRU_CLKSEL_CON36(Offset:0x390) +#define MCLK_PDM1_DIV 0x05020024 +#define MCLK_SPDIF1_SEL 0x02000024 +#define MCLK_SPDIF1_SEL_CLK_SPDIF1_SRC 0U +#define MCLK_SPDIF1_SEL_CLK_SPDIF1_FRAC 1U +#define MCLK_SPDIF1_SEL_XIN_OSC0_HALF 2U +#define MCLK_PDM1_SEL 0x02070024 +#define MCLK_PDM1_SEL_CLK_GPLL_MUX 0U +#define MCLK_PDM1_SEL_CLK_CPLL_MUX 1U +#define MCLK_PDM1_SEL_CLK_AUPLL_MUX 2U + +// CRU_CLKSEL_CON38(Offset:0x398) +#define ACLK_BUS_ROOT_DIV 0x05000026 +#define ACLK_BUS_ROOT_SEL 0x01050026 +#define ACLK_BUS_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_BUS_ROOT_SEL_CLK_CPLL_MUX 1U +#define CLK_I2C1_SEL 0x01060026 +#define CLK_I2C1_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C1_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C2_SEL 0x01070026 +#define CLK_I2C2_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C2_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C3_SEL 0x01080026 +#define CLK_I2C3_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C3_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C4_SEL 0x01090026 +#define CLK_I2C4_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C4_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C5_SEL 0x010A0026 +#define CLK_I2C5_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C5_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C6_SEL 0x010B0026 +#define CLK_I2C6_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C6_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C7_SEL 0x010C0026 +#define CLK_I2C7_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C7_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_I2C8_SEL 0x010D0026 +#define CLK_I2C8_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_I2C8_SEL_CLK_MATRIX_100M_SRC 1U + +// CRU_CLKSEL_CON39(Offset:0x39C) +#define CLK_CAN0_DIV 0x05000027 +#define CLK_CAN1_DIV 0x05060027 +#define CLK_CAN0_SEL 0x01050027 +#define CLK_CAN0_SEL_CLK_GPLL_MUX 0U +#define CLK_CAN0_SEL_CLK_CPLL_MUX 1U +#define CLK_CAN1_SEL 0x010B0027 +#define CLK_CAN1_SEL_CLK_GPLL_MUX 0U +#define CLK_CAN1_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON40(Offset:0x3A0) +#define CLK_CAN2_DIV 0x05000028 +#define CLK_SARADC_DIV 0x08060028 +#define CLK_CAN2_SEL 0x01050028 +#define CLK_CAN2_SEL_CLK_GPLL_MUX 0U +#define CLK_CAN2_SEL_CLK_CPLL_MUX 1U +#define CLK_SARADC_SEL 0x010E0028 +#define CLK_SARADC_SEL_CLK_GPLL_MUX 0U +#define CLK_SARADC_SEL_XIN_OSC0_FUNC 1U + +// CRU_CLKSEL_CON41(Offset:0x3A4) +#define CLK_TSADC_DIV 0x08000029 +#define CLK_UART1_SRC_DIV 0x05090029 +#define CLK_TSADC_SEL 0x01080029 +#define CLK_TSADC_SEL_CLK_GPLL_MUX 0U +#define CLK_TSADC_SEL_XIN_OSC0_FUNC 1U +#define CLK_UART1_SRC_SEL 0x010E0029 +#define CLK_UART1_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART1_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON42(Offset:0x3A8) +#define CLK_UART1_FRAC_DIV 0x2000002A + +// CRU_CLKSEL_CON43(Offset:0x3AC) +#define CLK_UART2_SRC_DIV 0x0502002B +#define SCLK_UART1_SEL 0x0200002B +#define SCLK_UART1_SEL_CLK_UART1_SRC 0U +#define SCLK_UART1_SEL_CLK_UART1_FRAC 1U +#define SCLK_UART1_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART2_SRC_SEL 0x0107002B +#define CLK_UART2_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART2_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON44(Offset:0x3B0) +#define CLK_UART2_FRAC_DIV 0x2000002C + +// CRU_CLKSEL_CON45(Offset:0x3B4) +#define CLK_UART3_SRC_DIV 0x0502002D +#define SCLK_UART2_SEL 0x0200002D +#define SCLK_UART2_SEL_CLK_UART2_SRC 0U +#define SCLK_UART2_SEL_CLK_UART2_FRAC 1U +#define SCLK_UART2_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART3_SRC_SEL 0x0107002D +#define CLK_UART3_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART3_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON46(Offset:0x3B8) +#define CLK_UART3_FRAC_DIV 0x2000002E + +// CRU_CLKSEL_CON47(Offset:0x3BC) +#define CLK_UART4_SRC_DIV 0x0502002F +#define SCLK_UART3_SEL 0x0200002F +#define SCLK_UART3_SEL_CLK_UART3_SRC 0U +#define SCLK_UART3_SEL_CLK_UART3_FRAC 1U +#define SCLK_UART3_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART4_SRC_SEL 0x0107002F +#define CLK_UART4_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART4_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON48(Offset:0x3C0) +#define CLK_UART4_FRAC_DIV 0x20000030 + +// CRU_CLKSEL_CON49(Offset:0x3C4) +#define CLK_UART5_SRC_DIV 0x05020031 +#define SCLK_UART4_SEL 0x02000031 +#define SCLK_UART4_SEL_CLK_UART4_SRC 0U +#define SCLK_UART4_SEL_CLK_UART4_FRAC 1U +#define SCLK_UART4_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART5_SRC_SEL 0x01070031 +#define CLK_UART5_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART5_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON50(Offset:0x3C8) +#define CLK_UART5_FRAC_DIV 0x20000032 + +// CRU_CLKSEL_CON51(Offset:0x3CC) +#define CLK_UART6_SRC_DIV 0x05020033 +#define SCLK_UART5_SEL 0x02000033 +#define SCLK_UART5_SEL_CLK_UART5_SRC 0U +#define SCLK_UART5_SEL_CLK_UART5_FRAC 1U +#define SCLK_UART5_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART6_SRC_SEL 0x01070033 +#define CLK_UART6_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART6_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON52(Offset:0x3D0) +#define CLK_UART6_FRAC_DIV 0x20000034 + +// CRU_CLKSEL_CON53(Offset:0x3D4) +#define CLK_UART7_SRC_DIV 0x05020035 +#define SCLK_UART6_SEL 0x02000035 +#define SCLK_UART6_SEL_CLK_UART6_SRC 0U +#define SCLK_UART6_SEL_CLK_UART6_FRAC 1U +#define SCLK_UART6_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART7_SRC_SEL 0x01070035 +#define CLK_UART7_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART7_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON54(Offset:0x3D8) +#define CLK_UART7_FRAC_DIV 0x20000036 + +// CRU_CLKSEL_CON55(Offset:0x3DC) +#define CLK_UART8_SRC_DIV 0x05020037 +#define SCLK_UART7_SEL 0x02000037 +#define SCLK_UART7_SEL_CLK_UART7_SRC 0U +#define SCLK_UART7_SEL_CLK_UART7_FRAC 1U +#define SCLK_UART7_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART8_SRC_SEL 0x01070037 +#define CLK_UART8_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART8_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON56(Offset:0x3E0) +#define CLK_UART8_FRAC_DIV 0x20000038 + +// CRU_CLKSEL_CON57(Offset:0x3E4) +#define CLK_UART9_SRC_DIV 0x05020039 +#define SCLK_UART8_SEL 0x02000039 +#define SCLK_UART8_SEL_CLK_UART8_SRC 0U +#define SCLK_UART8_SEL_CLK_UART8_FRAC 1U +#define SCLK_UART8_SEL_XIN_OSC0_FUNC 2U +#define CLK_UART9_SRC_SEL 0x01070039 +#define CLK_UART9_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_UART9_SRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON58(Offset:0x3E8) +#define CLK_UART9_FRAC_DIV 0x2000003A + +// CRU_CLKSEL_CON59(Offset:0x3EC) +#define SCLK_UART9_SEL 0x0200003B +#define SCLK_UART9_SEL_CLK_UART9_SRC 0U +#define SCLK_UART9_SEL_CLK_UART9_FRAC 1U +#define SCLK_UART9_SEL_XIN_OSC0_FUNC 2U +#define CLK_SPI0_SEL 0x0202003B +#define CLK_SPI0_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_SPI0_SEL_CLK_MATRIX_150M_SRC 1U +#define CLK_SPI0_SEL_XIN_OSC0_FUNC 2U +#define CLK_SPI1_SEL 0x0204003B +#define CLK_SPI1_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_SPI1_SEL_CLK_MATRIX_150M_SRC 1U +#define CLK_SPI1_SEL_XIN_OSC0_FUNC 2U +#define CLK_SPI2_SEL 0x0206003B +#define CLK_SPI2_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_SPI2_SEL_CLK_MATRIX_150M_SRC 1U +#define CLK_SPI2_SEL_XIN_OSC0_FUNC 2U +#define CLK_SPI3_SEL 0x0208003B +#define CLK_SPI3_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_SPI3_SEL_CLK_MATRIX_150M_SRC 1U +#define CLK_SPI3_SEL_XIN_OSC0_FUNC 2U +#define CLK_SPI4_SEL 0x020A003B +#define CLK_SPI4_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_SPI4_SEL_CLK_MATRIX_150M_SRC 1U +#define CLK_SPI4_SEL_XIN_OSC0_FUNC 2U +#define CLK_PWM1_SEL 0x020C003B +#define CLK_PWM1_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_PWM1_SEL_CLK_MATRIX_50M_SRC 1U +#define CLK_PWM1_SEL_XIN_OSC0_FUNC 2U +#define CLK_PWM2_SEL 0x020E003B +#define CLK_PWM2_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_PWM2_SEL_CLK_MATRIX_50M_SRC 1U +#define CLK_PWM2_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON60(Offset:0x3F0) +#define DBCLK_GPIO1_DIV 0x0503003C +#define DBCLK_GPIO2_DIV 0x0509003C +#define CLK_PWM3_SEL 0x0200003C +#define CLK_PWM3_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_PWM3_SEL_CLK_MATRIX_50M_SRC 1U +#define CLK_PWM3_SEL_XIN_OSC0_FUNC 2U +#define CLK_BUS_TIMER_ROOT_SEL 0x0102003C +#define CLK_BUS_TIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_BUS_TIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define DBCLK_GPIO1_SEL 0x0108003C +#define DBCLK_GPIO1_SEL_XIN_OSC0_FUNC 0U +#define DBCLK_GPIO1_SEL_CLK_DEEPSLOW 1U +#define DBCLK_GPIO2_SEL 0x010E003C +#define DBCLK_GPIO2_SEL_XIN_OSC0_FUNC 0U +#define DBCLK_GPIO2_SEL_CLK_DEEPSLOW 1U + +// CRU_CLKSEL_CON61(Offset:0x3F4) +#define DBCLK_GPIO3_DIV 0x0500003D +#define DBCLK_GPIO4_DIV 0x0506003D +#define DBCLK_GPIO3_SEL 0x0105003D +#define DBCLK_GPIO3_SEL_XIN_OSC0_FUNC 0U +#define DBCLK_GPIO3_SEL_CLK_DEEPSLOW 1U +#define DBCLK_GPIO4_SEL 0x010B003D +#define DBCLK_GPIO4_SEL_XIN_OSC0_FUNC 0U +#define DBCLK_GPIO4_SEL_CLK_DEEPSLOW 1U + +// CRU_CLKSEL_CON62(Offset:0x3F8) +#define DCLK_DECOM_DIV 0x0500003E +#define CLK_BISRINTF_PLLSRC_DIV 0x0506003E +#define DCLK_DECOM_SEL 0x0105003E +#define DCLK_DECOM_SEL_CLK_GPLL_MUX 0U +#define DCLK_DECOM_SEL_CLK_SPLL_MUX 1U + +// CRU_CLKSEL_CON63(Offset:0x3FC) +#define CLK_TESTOUT_DDR01_DIV 0x0600003F +#define CLK_TESTOUT_DDR01_SEL 0x0106003F +#define CLK_TESTOUT_DDR01_SEL_CLK_DFI_CH0 0U +#define CLK_TESTOUT_DDR01_SEL_CLK_DFI_CH1 1U + +// CRU_CLKSEL_CON65(Offset:0x404) +#define CLK_TESTOUT_DDR23_DIV 0x06000041 +#define CLK_TESTOUT_DDR23_SEL 0x01060041 +#define CLK_TESTOUT_DDR23_SEL_CLK_DFI_CH2 0U +#define CLK_TESTOUT_DDR23_SEL_CLK_DFI_CH3 1U + +// CRU_CLKSEL_CON67(Offset:0x40C) +#define ACLK_ISP1_ROOT_DIV 0x05000043 +#define CLK_ISP1_CORE_DIV 0x05090043 +#define ACLK_ISP1_ROOT_SEL 0x02050043 +#define ACLK_ISP1_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_ISP1_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_ISP1_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_ISP1_ROOT_SEL_CLK_SPLL_MUX 3U +#define HCLK_ISP1_ROOT_SEL 0x02070043 +#define HCLK_ISP1_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_ISP1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_ISP1_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_ISP1_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CLK_ISP1_CORE_SEL 0x020E0043 +#define CLK_ISP1_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_ISP1_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_ISP1_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_ISP1_CORE_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON73(Offset:0x424) +#define CLK_RKNN_DSU0_SRC_T_DIV 0x05020049 +#define CLK_TESTOUT_NPU_DIV 0x050A0049 +#define HCLK_RKNN_ROOT_SEL 0x02000049 +#define HCLK_RKNN_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RKNN_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RKNN_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RKNN_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CLK_RKNN_DSU0_SRC_T_SEL 0x03070049 +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_GPLL_MUX 0U +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_CPLL_MUX 1U +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_AUPLL_MUX 2U +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_NPLL_MUX 3U +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_SPLL_MUX 4U +#define CLK_TESTOUT_NPU_SEL 0x010F0049 +#define CLK_TESTOUT_NPU_SEL_CLK_RKNN_DSU0_SRC_T 0U +#define CLK_TESTOUT_NPU_SEL_CLK_NPU_PVTPLL 1U + +// CRU_CLKSEL_CON74(Offset:0x428) +#define CLK_NPU_CM0_RTC_DIV 0x0507004A +#define CLK_RKNN_DSU0_SEL 0x0100004A +#define CLK_RKNN_DSU0_SEL_CLK_RKNN_DSU0_SRC_T 0U +#define CLK_RKNN_DSU0_SEL_CLK_NPU_PVTPLL 1U +#define PCLK_NPUTOP_ROOT_SEL 0x0201004A +#define PCLK_NPUTOP_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_NPUTOP_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_NPUTOP_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_NPUTIMER_ROOT_SEL 0x0103004A +#define CLK_NPUTIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_NPUTIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_NPU_PVTPLL_SEL 0x0104004A +#define CLK_NPU_PVTPLL_SEL_CLK_RKNN_DSU0_SRC_T 0U +#define CLK_NPU_PVTPLL_SEL_XIN_OSC0_FUNC 1U +#define HCLK_NPU_CM0_ROOT_SEL 0x0205004A +#define HCLK_NPU_CM0_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define HCLK_NPU_CM0_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define HCLK_NPU_CM0_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define HCLK_NPU_CM0_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CLK_NPU_CM0_RTC_SEL 0x010C004A +#define CLK_NPU_CM0_RTC_SEL_XIN_OSC0_FUNC 0U +#define CLK_NPU_CM0_RTC_SEL_CLK_DEEPSLOW 1U + +// CRU_CLKSEL_CON77(Offset:0x434) +#define ACLK_NVM_ROOT_DIV 0x0502004D +#define CCLK_EMMC_DIV 0x0608004D +#define HCLK_NVM_ROOT_SEL 0x0200004D +#define HCLK_NVM_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_NVM_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_NVM_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_NVM_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_NVM_ROOT_SEL 0x0107004D +#define ACLK_NVM_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_NVM_ROOT_SEL_CLK_CPLL_MUX 1U +#define CCLK_EMMC_SEL 0x020E004D +#define CCLK_EMMC_SEL_CLK_GPLL_MUX 0U +#define CCLK_EMMC_SEL_CLK_CPLL_MUX 1U +#define CCLK_EMMC_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON78(Offset:0x438) +#define BCLK_EMMC_DIV 0x0500004E +#define SCLK_SFC_DIV 0x0606004E +#define BCLK_EMMC_SEL 0x0105004E +#define BCLK_EMMC_SEL_CLK_GPLL_MUX 0U +#define BCLK_EMMC_SEL_CLK_CPLL_MUX 1U +#define SCLK_SFC_SEL 0x020C004E +#define SCLK_SFC_SEL_CLK_GPLL_MUX 0U +#define SCLK_SFC_SEL_CLK_CPLL_MUX 1U +#define SCLK_SFC_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON80(Offset:0x440) +#define ACLK_PCIE_ROOT_DIV 0x05020050 +#define ACLK_PHP_ROOT_DIV 0x05080050 +#define PCLK_PHP_ROOT_SEL 0x02000050 +#define PCLK_PHP_ROOT_SEL_CLK_MATRIX_150M_SRC 0U +#define PCLK_PHP_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_PHP_ROOT_SEL_XIN_OSC0_FUNC 2U +#define ACLK_PCIE_ROOT_SEL 0x01070050 +#define ACLK_PCIE_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_PCIE_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_PHP_ROOT_SEL 0x010D0050 +#define ACLK_PHP_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_PHP_ROOT_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON81(Offset:0x444) +#define CLK_GMAC0_PTP_REF_DIV 0x06000051 +#define CLK_GMAC1_PTP_REF_DIV 0x06070051 +#define CLK_GMAC0_PTP_REF_SEL 0x01060051 +#define CLK_GMAC0_PTP_REF_SEL_CLK_CPLL_MUX 0U +#define CLK_GMAC0_PTP_REF_SEL_CLK_GMAC0_PTPREFO 1U +#define CLK_GMAC1_PTP_REF_SEL 0x010D0051 +#define CLK_GMAC1_PTP_REF_SEL_CLK_CPLL_MUX 0U +#define CLK_GMAC1_PTP_REF_SEL_CLK_GMAC1_PTPREFO 1U + +// CRU_CLKSEL_CON82(Offset:0x448) +#define CLK_RXOOB0_DIV 0x07000052 +#define CLK_RXOOB1_DIV 0x07080052 +#define CLK_RXOOB0_SEL 0x01070052 +#define CLK_RXOOB0_SEL_CLK_GPLL_MUX 0U +#define CLK_RXOOB0_SEL_CLK_CPLL_MUX 1U +#define CLK_RXOOB1_SEL 0x010F0052 +#define CLK_RXOOB1_SEL_CLK_GPLL_MUX 0U +#define CLK_RXOOB1_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON83(Offset:0x44C) +#define CLK_RXOOB2_DIV 0x07000053 +#define CLK_GMAC_125M_CRU_I_DIV 0x07080053 +#define CLK_RXOOB2_SEL 0x01070053 +#define CLK_RXOOB2_SEL_CLK_GPLL_MUX 0U +#define CLK_RXOOB2_SEL_CLK_CPLL_MUX 1U +#define CLK_GMAC_125M_CRU_I_SEL 0x010F0053 +#define CLK_GMAC_125M_CRU_I_SEL_CLK_GPLL_MUX 0U +#define CLK_GMAC_125M_CRU_I_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON84(Offset:0x450) +#define CLK_GMAC_50M_CRU_I_DIV 0x07000054 +#define CLK_UTMI_OTG2_DIV 0x04080054 +#define CLK_GMAC_50M_CRU_I_SEL 0x01070054 +#define CLK_GMAC_50M_CRU_I_SEL_CLK_GPLL_MUX 0U +#define CLK_GMAC_50M_CRU_I_SEL_CLK_CPLL_MUX 1U +#define CLK_UTMI_OTG2_SEL 0x020C0054 +#define CLK_UTMI_OTG2_SEL_CLK_MATRIX_150M_SRC 0U +#define CLK_UTMI_OTG2_SEL_CLK_MATRIX_50M_SRC 1U +#define CLK_UTMI_OTG2_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON85(Offset:0x454) +#define CLK_GMAC0_TX_125M_O_DIV 0x06000055 +#define CLK_GMAC1_TX_125M_O_DIV 0x06060055 + +// CRU_CLKSEL_CON89(Offset:0x464) +#define ACLK_RKVDEC0_ROOT_DIV 0x05020059 +#define ACLK_RKVDEC_CCU_DIV 0x05090059 +#define HCLK_RKVDEC0_ROOT_SEL 0x02000059 +#define HCLK_RKVDEC0_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RKVDEC0_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RKVDEC0_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RKVDEC0_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_RKVDEC0_ROOT_SEL 0x02070059 +#define ACLK_RKVDEC0_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_RKVDEC0_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_RKVDEC0_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_RKVDEC0_ROOT_SEL_CLK_SPLL_MUX 3U +#define ACLK_RKVDEC_CCU_SEL 0x020E0059 +#define ACLK_RKVDEC_CCU_SEL_CLK_GPLL_MUX 0U +#define ACLK_RKVDEC_CCU_SEL_CLK_CPLL_MUX 1U +#define ACLK_RKVDEC_CCU_SEL_CLK_AUPLL_MUX 2U +#define ACLK_RKVDEC_CCU_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON90(Offset:0x468) +#define CLK_RKVDEC0_CA_DIV 0x0500005A +#define CLK_RKVDEC0_HEVC_CA_DIV 0x0506005A +#define CLK_RKVDEC0_CA_SEL 0x0105005A +#define CLK_RKVDEC0_CA_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC0_CA_SEL_CLK_CPLL_MUX 1U +#define CLK_RKVDEC0_HEVC_CA_SEL 0x020B005A +#define CLK_RKVDEC0_HEVC_CA_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC0_HEVC_CA_SEL_CLK_CPLL_MUX 1U +#define CLK_RKVDEC0_HEVC_CA_SEL_CLK_NPLL_MUX 2U +#define CLK_RKVDEC0_HEVC_CA_SEL_CLK_MATRIX_1000M_SRC 3U + +// CRU_CLKSEL_CON91(Offset:0x46C) +#define CLK_RKVDEC0_CORE_DIV 0x0500005B +#define CLK_RKVDEC0_CORE_SEL 0x0105005B +#define CLK_RKVDEC0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC0_CORE_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON93(Offset:0x474) +#define ACLK_RKVDEC1_ROOT_DIV 0x0502005D +#define CLK_RKVDEC1_CA_DIV 0x0509005D +#define HCLK_RKVDEC1_ROOT_SEL 0x0200005D +#define HCLK_RKVDEC1_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RKVDEC1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RKVDEC1_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RKVDEC1_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_RKVDEC1_ROOT_SEL 0x0207005D +#define ACLK_RKVDEC1_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_RKVDEC1_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_RKVDEC1_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_RKVDEC1_ROOT_SEL_CLK_NPLL_MUX 3U +#define CLK_RKVDEC1_CA_SEL 0x010E005D +#define CLK_RKVDEC1_CA_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC1_CA_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON94(Offset:0x478) +#define CLK_RKVDEC1_HEVC_CA_DIV 0x0500005E +#define CLK_RKVDEC1_CORE_DIV 0x0507005E +#define CLK_RKVDEC1_HEVC_CA_SEL 0x0205005E +#define CLK_RKVDEC1_HEVC_CA_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC1_HEVC_CA_SEL_CLK_CPLL_MUX 1U +#define CLK_RKVDEC1_HEVC_CA_SEL_CLK_NPLL_MUX 2U +#define CLK_RKVDEC1_HEVC_CA_SEL_CLK_MATRIX_1000M_SRC 3U +#define CLK_RKVDEC1_CORE_SEL 0x010C005E +#define CLK_RKVDEC1_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVDEC1_CORE_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON96(Offset:0x480) +#define ACLK_USB_ROOT_DIV 0x05000060 +#define ACLK_USB_ROOT_SEL 0x01050060 +#define ACLK_USB_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_USB_ROOT_SEL_CLK_CPLL_MUX 1U +#define HCLK_USB_ROOT_SEL 0x02060060 +#define HCLK_USB_ROOT_SEL_CLK_MATRIX_150M_SRC 0U +#define HCLK_USB_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_USB_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_USB_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON98(Offset:0x488) +#define ACLK_VDPU_ROOT_DIV 0x05000062 +#define ACLK_VDPU_ROOT_SEL 0x02050062 +#define ACLK_VDPU_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_VDPU_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_VDPU_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_VDPU_LOW_ROOT_SEL 0x02070062 +#define ACLK_VDPU_LOW_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define ACLK_VDPU_LOW_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_VDPU_LOW_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_VDPU_LOW_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_VDPU_ROOT_SEL 0x02090062 +#define HCLK_VDPU_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VDPU_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VDPU_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VDPU_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON99(Offset:0x48C) +#define ACLK_JPEG_DECODER_ROOT_DIV 0x05000063 +#define CLK_IEP2P0_CORE_DIV 0x05070063 +#define ACLK_JPEG_DECODER_ROOT_SEL 0x02050063 +#define ACLK_JPEG_DECODER_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_JPEG_DECODER_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_JPEG_DECODER_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_JPEG_DECODER_ROOT_SEL_CLK_SPLL_MUX 3U +#define CLK_IEP2P0_CORE_SEL 0x010C0063 +#define CLK_IEP2P0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_IEP2P0_CORE_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON100(Offset:0x490) +#define CLK_RGA2_CORE_DIV 0x05000064 +#define CLK_RGA3_0_CORE_DIV 0x05080064 +#define CLK_RGA2_CORE_SEL 0x03050064 +#define CLK_RGA2_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RGA2_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_RGA2_CORE_SEL_CLK_NPLL_MUX 2U +#define CLK_RGA2_CORE_SEL_CLK_AUPLL_MUX 3U +#define CLK_RGA2_CORE_SEL_CLK_SPLL_MUX 4U +#define CLK_RGA3_0_CORE_SEL 0x030D0064 +#define CLK_RGA3_0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RGA3_0_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_RGA3_0_CORE_SEL_CLK_NPLL_MUX 2U +#define CLK_RGA3_0_CORE_SEL_CLK_AUPLL_MUX 3U +#define CLK_RGA3_0_CORE_SEL_CLK_SPLL_MUX 4U + +// CRU_CLKSEL_CON102(Offset:0x498) +#define ACLK_RKVENC0_ROOT_DIV 0x05020066 +#define CLK_RKVENC0_CORE_DIV 0x05090066 +#define HCLK_RKVENC0_ROOT_SEL 0x02000066 +#define HCLK_RKVENC0_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RKVENC0_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RKVENC0_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RKVENC0_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_RKVENC0_ROOT_SEL 0x02070066 +#define ACLK_RKVENC0_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_RKVENC0_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_RKVENC0_ROOT_SEL_CLK_NPLL_MUX 2U +#define CLK_RKVENC0_CORE_SEL 0x020E0066 +#define CLK_RKVENC0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVENC0_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_RKVENC0_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_RKVENC0_CORE_SEL_CLK_NPLL_MUX 3U + +// CRU_CLKSEL_CON104(Offset:0x4A0) +#define ACLK_RKVENC1_ROOT_DIV 0x05020068 +#define CLK_RKVENC1_CORE_DIV 0x05090068 +#define HCLK_RKVENC1_ROOT_SEL 0x02000068 +#define HCLK_RKVENC1_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RKVENC1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RKVENC1_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RKVENC1_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_RKVENC1_ROOT_SEL 0x02070068 +#define ACLK_RKVENC1_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_RKVENC1_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_RKVENC1_ROOT_SEL_CLK_NPLL_MUX 2U +#define CLK_RKVENC1_CORE_SEL 0x020E0068 +#define CLK_RKVENC1_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RKVENC1_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_RKVENC1_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_RKVENC1_CORE_SEL_CLK_NPLL_MUX 3U + +// CRU_CLKSEL_CON106(Offset:0x4A8) +#define ACLK_VI_ROOT_DIV 0x0500006A +#define ACLK_VI_ROOT_SEL 0x0305006A +#define ACLK_VI_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_VI_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_VI_ROOT_SEL_CLK_NPLL_MUX 2U +#define ACLK_VI_ROOT_SEL_CLK_AUPLL_MUX 3U +#define ACLK_VI_ROOT_SEL_CLK_SPLL_MUX 4U +#define HCLK_VI_ROOT_SEL 0x0208006A +#define HCLK_VI_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VI_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VI_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VI_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_VI_ROOT_SEL 0x020A006A +#define PCLK_VI_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_VI_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_VI_ROOT_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON107(Offset:0x4AC) +#define DCLK_VICAP_DIV 0x0500006B +#define CLK_ISP0_CORE_DIV 0x0506006B +#define DCLK_VICAP_SEL 0x0105006B +#define DCLK_VICAP_SEL_CLK_GPLL_MUX 0U +#define DCLK_VICAP_SEL_CLK_CPLL_MUX 1U +#define CLK_ISP0_CORE_SEL 0x020B006B +#define CLK_ISP0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_ISP0_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_ISP0_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_ISP0_CORE_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON108(Offset:0x4B0) +#define CLK_FISHEYE0_CORE_DIV 0x0500006C +#define CLK_FISHEYE1_CORE_DIV 0x0507006C +#define CLK_FISHEYE0_CORE_SEL 0x0205006C +#define CLK_FISHEYE0_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_FISHEYE0_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_FISHEYE0_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_FISHEYE0_CORE_SEL_CLK_SPLL_MUX 3U +#define CLK_FISHEYE1_CORE_SEL 0x020C006C +#define CLK_FISHEYE1_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_FISHEYE1_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_FISHEYE1_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_FISHEYE1_CORE_SEL_CLK_SPLL_MUX 3U +#define ICLK_CSIHOST01_SEL 0x020E006C +#define ICLK_CSIHOST01_SEL_CLK_MATRIX_400M_SRC 0U +#define ICLK_CSIHOST01_SEL_CLK_MATRIX_200M_SRC 1U +#define ICLK_CSIHOST01_SEL_CLK_MATRIX_100M_SRC 2U +#define ICLK_CSIHOST01_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON110(Offset:0x4B8) +#define ACLK_VOP_ROOT_DIV 0x0500006E +#define ACLK_VOP_ROOT_SEL 0x0305006E +#define ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_VOP_ROOT_SEL_CLK_AUPLL_MUX 2U +#define ACLK_VOP_ROOT_SEL_CLK_NPLL_MUX 3U +#define ACLK_VOP_ROOT_SEL_CLK_SPLL_MUX 4U +#define ACLK_VOP_LOW_ROOT_SEL 0x0208006E +#define ACLK_VOP_LOW_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define ACLK_VOP_LOW_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_VOP_LOW_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_VOP_LOW_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_VOP_ROOT_SEL 0x020A006E +#define HCLK_VOP_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VOP_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VOP_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VOP_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_VOP_ROOT_SEL 0x020C006E +#define PCLK_VOP_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_VOP_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_VOP_ROOT_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON111(Offset:0x4BC) +#define DCLK_VOP0_SRC_DIV 0x0700006F +#define DCLK_VOP1_SRC_DIV 0x0509006F +#define DCLK_VOP0_SRC_SEL 0x0207006F +#define DCLK_VOP0_SRC_SEL_CLK_GPLL_MUX 0U +#define DCLK_VOP0_SRC_SEL_CLK_CPLL_MUX 1U +#define DCLK_VOP0_SRC_SEL_CLK_V0PLL_MUX 2U +#define DCLK_VOP0_SRC_SEL_CLK_AUPLL_MUX 3U +#define DCLK_VOP1_SRC_SEL 0x020E006F +#define DCLK_VOP1_SRC_SEL_CLK_GPLL_MUX 0U +#define DCLK_VOP1_SRC_SEL_CLK_CPLL_MUX 1U +#define DCLK_VOP1_SRC_SEL_CLK_V0PLL_MUX 2U +#define DCLK_VOP1_SRC_SEL_CLK_AUPLL_MUX 3U + +// CRU_CLKSEL_CON112(Offset:0x4C0) +#define DCLK_VOP2_SRC_DIV 0x05000070 +#define DCLK_VOP2_SRC_SEL 0x02050070 +#define DCLK_VOP2_SRC_SEL_CLK_GPLL_MUX 0U +#define DCLK_VOP2_SRC_SEL_CLK_CPLL_MUX 1U +#define DCLK_VOP2_SRC_SEL_CLK_V0PLL_MUX 2U +#define DCLK_VOP2_SRC_SEL_CLK_AUPLL_MUX 3U +#define DCLK_VOP0_SEL 0x02070070 +#define DCLK_VOP0_SEL_DCLK_VOP0_SRC 0U +#define DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL0_O 1U +#define DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL1_O 2U +#define DCLK_VOP1_SEL 0x02090070 +#define DCLK_VOP1_SEL_DCLK_VOP1_SRC 0U +#define DCLK_VOP1_SEL_CLK_HDMIPHY_PIXEL0_O 1U +#define DCLK_VOP1_SEL_CLK_HDMIPHY_PIXEL1_O 2U +#define DCLK_VOP2_SEL 0x020B0070 +#define DCLK_VOP2_SEL_DCLK_VOP2_SRC 0U +#define DCLK_VOP2_SEL_CLK_HDMIPHY_PIXEL0_O 1U +#define DCLK_VOP2_SEL_CLK_HDMIPHY_PIXEL1_O 2U + +// CRU_CLKSEL_CON113(Offset:0x4C4) +#define DCLK_VOP3_DIV 0x07000071 +#define DCLK_VOP3_SEL 0x02070071 +#define DCLK_VOP3_SEL_CLK_GPLL_MUX 0U +#define DCLK_VOP3_SEL_CLK_CPLL_MUX 1U +#define DCLK_VOP3_SEL_CLK_V0PLL_MUX 2U +#define DCLK_VOP3_SEL_CLK_AUPLL_MUX 3U + +// CRU_CLKSEL_CON114(Offset:0x4C8) +#define CLK_DSIHOST0_DIV 0x07000072 +#define CLK_DSIHOST0_SEL 0x02070072 +#define CLK_DSIHOST0_SEL_CLK_GPLL_MUX 0U +#define CLK_DSIHOST0_SEL_CLK_CPLL_MUX 1U +#define CLK_DSIHOST0_SEL_CLK_V0PLL_MUX 2U +#define CLK_DSIHOST0_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON115(Offset:0x4CC) +#define CLK_DSIHOST1_DIV 0x07000073 +#define CLK_DSIHOST1_SEL 0x02070073 +#define CLK_DSIHOST1_SEL_CLK_GPLL_MUX 0U +#define CLK_DSIHOST1_SEL_CLK_CPLL_MUX 1U +#define CLK_DSIHOST1_SEL_CLK_V0PLL_MUX 2U +#define CLK_DSIHOST1_SEL_CLK_SPLL_MUX 3U +#define ACLK_VOP_SUB_SRC_SEL 0x01090073 +#define ACLK_VOP_SUB_SRC_SEL_ACLK_VOP_ROOT 0U +#define ACLK_VOP_SUB_SRC_SEL_ACLK_VOP_DIV2_SRC 1U + +// CRU_CLKSEL_CON116(Offset:0x4D0) +#define ACLK_VO0_ROOT_DIV 0x05000074 +#define ACLK_VO0_ROOT_SEL 0x01050074 +#define ACLK_VO0_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_VO0_ROOT_SEL_CLK_CPLL_MUX 1U +#define HCLK_VO0_ROOT_SEL 0x02060074 +#define HCLK_VO0_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VO0_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VO0_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VO0_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_VO0_S_ROOT_SEL 0x02080074 +#define HCLK_VO0_S_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VO0_S_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VO0_S_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VO0_S_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_VO0_ROOT_SEL 0x020A0074 +#define PCLK_VO0_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_VO0_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_VO0_ROOT_SEL_XIN_OSC0_FUNC 2U +#define PCLK_VO0_S_ROOT_SEL 0x020C0074 +#define PCLK_VO0_S_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_VO0_S_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_VO0_S_ROOT_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON117(Offset:0x4D4) +#define CLK_AUX16MHZ_0_DIV 0x08000075 +#define CLK_AUX16MHZ_1_DIV 0x08080075 + +// CRU_CLKSEL_CON118(Offset:0x4D8) +#define CLK_I2S4_8CH_TX_SRC_DIV 0x05000076 +#define CLK_I2S4_8CH_TX_SRC_SEL 0x01050076 +#define CLK_I2S4_8CH_TX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S4_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON119(Offset:0x4DC) +#define CLK_I2S4_8CH_TX_FRAC_DIV 0x20000077 + +// CRU_CLKSEL_CON120(Offset:0x4E0) +#define CLK_I2S8_8CH_TX_SRC_DIV 0x05030078 +#define MCLK_I2S4_8CH_TX_SEL 0x02000078 +#define MCLK_I2S4_8CH_TX_SEL_CLK_I2S4_8CH_TX_SRC 0U +#define MCLK_I2S4_8CH_TX_SEL_CLK_I2S4_8CH_TX_FRAC 1U +#define MCLK_I2S4_8CH_TX_SEL_I2S4_MCLKIN 2U +#define MCLK_I2S4_8CH_TX_SEL_XIN_OSC0_HALF 3U +#define CLK_I2S8_8CH_TX_SRC_SEL 0x01080078 +#define CLK_I2S8_8CH_TX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S8_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON121(Offset:0x4E4) +#define CLK_I2S8_8CH_TX_FRAC_DIV 0x20000079 + +// CRU_CLKSEL_CON122(Offset:0x4E8) +#define CLK_SPDIF2_DP0_SRC_DIV 0x0503007A +#define MCLK_I2S8_8CH_TX_SEL 0x0200007A +#define MCLK_I2S8_8CH_TX_SEL_CLK_I2S8_8CH_TX_SRC 0U +#define MCLK_I2S8_8CH_TX_SEL_CLK_I2S8_8CH_TX_FRAC 1U +#define MCLK_I2S8_8CH_TX_SEL_I2S8_MCLKIN 2U +#define MCLK_I2S8_8CH_TX_SEL_XIN_OSC0_HALF 3U +#define CLK_SPDIF2_DP0_SRC_SEL 0x0108007A +#define CLK_SPDIF2_DP0_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF2_DP0_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON123(Offset:0x4EC) +#define CLK_SPDIF2_DP0_FRAC_DIV 0x2000007B + +// CRU_CLKSEL_CON124(Offset:0x4F0) +#define CLK_SPDIF5_DP1_SRC_DIV 0x0502007C +#define MCLK_4X_SPDIF2_DP0_SEL 0x0200007C +#define MCLK_4X_SPDIF2_DP0_SEL_CLK_SPDIF2_DP0_SRC 0U +#define MCLK_4X_SPDIF2_DP0_SEL_CLK_SPDIF2_DP0_FRAC 1U +#define MCLK_4X_SPDIF2_DP0_SEL_XIN_OSC0_HALF 2U +#define CLK_SPDIF5_DP1_SRC_SEL 0x0107007C +#define CLK_SPDIF5_DP1_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF5_DP1_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON125(Offset:0x4F4) +#define CLK_SPDIF5_DP1_FRAC_DIV 0x2000007D + +// CRU_CLKSEL_CON126(Offset:0x4F8) +#define MCLK_4X_SPDIF5_DP1_SEL 0x0200007E +#define MCLK_4X_SPDIF5_DP1_SEL_CLK_SPDIF5_DP1_SRC 0U +#define MCLK_4X_SPDIF5_DP1_SEL_CLK_SPDIF5_DP1_FRAC 1U +#define MCLK_4X_SPDIF5_DP1_SEL_XIN_OSC0_HALF 2U + +// CRU_CLKSEL_CON128(Offset:0x500) +#define ACLK_HDCP1_ROOT_DIV 0x05000080 +#define ACLK_HDMIRX_ROOT_DIV 0x05070080 +#define ACLK_HDCP1_ROOT_SEL 0x02050080 +#define ACLK_HDCP1_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_HDCP1_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_HDCP1_ROOT_SEL_CLK_HDMITRX_REFSRC 2U +#define ACLK_HDMIRX_ROOT_SEL 0x010C0080 +#define ACLK_HDMIRX_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_HDMIRX_ROOT_SEL_CLK_CPLL_MUX 1U +#define HCLK_VO1_ROOT_SEL 0x020D0080 +#define HCLK_VO1_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VO1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VO1_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VO1_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON129(Offset:0x504) +#define CLK_I2S7_8CH_RX_SRC_DIV 0x05060081 +#define HCLK_VO1_S_ROOT_SEL 0x02000081 +#define HCLK_VO1_S_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VO1_S_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VO1_S_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VO1_S_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_VO1_ROOT_SEL 0x02020081 +#define PCLK_VO1_ROOT_SEL_CLK_MATRIX_150M_SRC 0U +#define PCLK_VO1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define PCLK_VO1_ROOT_SEL_XIN_OSC0_FUNC 2U +#define PCLK_VO1_S_ROOT_SEL 0x02040081 +#define PCLK_VO1_S_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_VO1_S_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_VO1_S_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_I2S7_8CH_RX_SRC_SEL 0x010B0081 +#define CLK_I2S7_8CH_RX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S7_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON130(Offset:0x508) +#define CLK_I2S7_8CH_RX_FRAC_DIV 0x20000082 + +// CRU_CLKSEL_CON131(Offset:0x50C) +#define MCLK_I2S7_8CH_RX_SEL 0x02000083 +#define MCLK_I2S7_8CH_RX_SEL_CLK_I2S7_8CH_RX_SRC 0U +#define MCLK_I2S7_8CH_RX_SEL_CLK_I2S7_8CH_RX_FRAC 1U +#define MCLK_I2S7_8CH_RX_SEL_I2S7_MCLKIN 2U +#define MCLK_I2S7_8CH_RX_SEL_XIN_OSC0_HALF 3U + +// CRU_CLKSEL_CON133(Offset:0x514) +#define CLK_HDMITX0_EARC_DIV 0x05010085 +#define CLK_HDMITX0_EARC_SEL 0x01060085 +#define CLK_HDMITX0_EARC_SEL_CLK_GPLL_MUX 0U +#define CLK_HDMITX0_EARC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON136(Offset:0x520) +#define CLK_HDMITX1_EARC_DIV 0x05010088 +#define CLK_HDMITX1_EARC_SEL 0x01060088 +#define CLK_HDMITX1_EARC_SEL_CLK_GPLL_MUX 0U +#define CLK_HDMITX1_EARC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON138(Offset:0x528) +#define CLK_HDMIRX_AUD_SRC_DIV 0x0800008A +#define CLK_HDMIRX_AUD_SRC_SEL 0x0108008A +#define CLK_HDMIRX_AUD_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_HDMIRX_AUD_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON139(Offset:0x52C) +#define CLK_HDMIRX_AUD_FRAC_DIV 0x2000008B + +// CRU_CLKSEL_CON140(Offset:0x530) +#define CLK_I2S5_8CH_TX_SRC_DIV 0x0505008C +#define CLK_HDMIRX_AUD_SEL 0x0100008C +#define CLK_HDMIRX_AUD_SEL_CLK_HDMIRX_AUD_SRC 0U +#define CLK_HDMIRX_AUD_SEL_CLK_HDMIRX_AUD_FRAC 1U +#define CLK_EDP0_200M_SEL 0x0201008C +#define CLK_EDP0_200M_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_EDP0_200M_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_EDP0_200M_SEL_CLK_MATRIX_50M_SRC 2U +#define CLK_EDP0_200M_SEL_XIN_OSC0_FUNC 3U +#define CLK_EDP1_200M_SEL 0x0203008C +#define CLK_EDP1_200M_SEL_CLK_MATRIX_200M_SRC 0U +#define CLK_EDP1_200M_SEL_CLK_MATRIX_100M_SRC 1U +#define CLK_EDP1_200M_SEL_CLK_MATRIX_50M_SRC 2U +#define CLK_EDP1_200M_SEL_XIN_OSC0_FUNC 3U +#define CLK_I2S5_8CH_TX_SRC_SEL 0x010A008C +#define CLK_I2S5_8CH_TX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S5_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON141(Offset:0x534) +#define CLK_I2S5_8CH_TX_FRAC_DIV 0x2000008D + +// CRU_CLKSEL_CON142(Offset:0x538) +#define MCLK_I2S5_8CH_TX_SEL 0x0200008E +#define MCLK_I2S5_8CH_TX_SEL_CLK_I2S5_8CH_TX_SRC 0U +#define MCLK_I2S5_8CH_TX_SEL_CLK_I2S5_8CH_TX_FRAC 1U +#define MCLK_I2S5_8CH_TX_SEL_I2S5_MCLKIN 2U +#define MCLK_I2S5_8CH_TX_SEL_XIN_OSC0_HALF 3U + +// CRU_CLKSEL_CON144(Offset:0x540) +#define CLK_I2S6_8CH_TX_SRC_DIV 0x05030090 +#define CLK_I2S6_8CH_TX_SRC_SEL 0x01080090 +#define CLK_I2S6_8CH_TX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S6_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON145(Offset:0x544) +#define CLK_I2S6_8CH_TX_FRAC_DIV 0x20000091 + +// CRU_CLKSEL_CON146(Offset:0x548) +#define CLK_I2S6_8CH_RX_SRC_DIV 0x05020092 +#define MCLK_I2S6_8CH_TX_SEL 0x02000092 +#define MCLK_I2S6_8CH_TX_SEL_CLK_I2S6_8CH_TX_SRC 0U +#define MCLK_I2S6_8CH_TX_SEL_CLK_I2S6_8CH_TX_FRAC 1U +#define MCLK_I2S6_8CH_TX_SEL_I2S6_MCLKIN 2U +#define MCLK_I2S6_8CH_TX_SEL_XIN_OSC0_HALF 3U +#define CLK_I2S6_8CH_RX_SRC_SEL 0x01070092 +#define CLK_I2S6_8CH_RX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S6_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON147(Offset:0x54C) +#define CLK_I2S6_8CH_RX_FRAC_DIV 0x20000093 + +// CRU_CLKSEL_CON148(Offset:0x550) +#define CLK_SPDIF3_SRC_DIV 0x05040094 +#define MCLK_I2S6_8CH_RX_SEL 0x02000094 +#define MCLK_I2S6_8CH_RX_SEL_CLK_I2S6_8CH_RX_SRC 0U +#define MCLK_I2S6_8CH_RX_SEL_CLK_I2S6_8CH_RX_FRAC 1U +#define MCLK_I2S6_8CH_RX_SEL_I2S6_MCLKIN 2U +#define MCLK_I2S6_8CH_RX_SEL_XIN_OSC0_HALF 3U +#define I2S6_8CH_MCLKOUT_SEL 0x02020094 +#define I2S6_8CH_MCLKOUT_SEL_MCLK_I2S6_8CH_TX 0U +#define I2S6_8CH_MCLKOUT_SEL_MCLK_I2S6_8CH_RX 1U +#define I2S6_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 2U +#define CLK_SPDIF3_SRC_SEL 0x01090094 +#define CLK_SPDIF3_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF3_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON149(Offset:0x554) +#define CLK_SPDIF3_FRAC_DIV 0x20000095 + +// CRU_CLKSEL_CON150(Offset:0x558) +#define CLK_SPDIF4_SRC_DIV 0x05020096 +#define MCLK_SPDIF3_SEL 0x02000096 +#define MCLK_SPDIF3_SEL_CLK_SPDIF3_SRC 0U +#define MCLK_SPDIF3_SEL_CLK_SPDIF3_FRAC 1U +#define MCLK_SPDIF3_SEL_XIN_OSC0_HALF 2U +#define CLK_SPDIF4_SRC_SEL 0x01070096 +#define CLK_SPDIF4_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_SPDIF4_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON151(Offset:0x55C) +#define CLK_SPDIF4_FRAC_DIV 0x20000097 + +// CRU_CLKSEL_CON152(Offset:0x560) +#define MCLK_SPDIFRX0_DIV 0x05020098 +#define MCLK_SPDIFRX1_DIV 0x05090098 +#define MCLK_SPDIF4_SEL 0x02000098 +#define MCLK_SPDIF4_SEL_CLK_SPDIF4_SRC 0U +#define MCLK_SPDIF4_SEL_CLK_SPDIF4_FRAC 1U +#define MCLK_SPDIF4_SEL_XIN_OSC0_HALF 2U +#define MCLK_SPDIFRX0_SEL 0x02070098 +#define MCLK_SPDIFRX0_SEL_CLK_GPLL_MUX 0U +#define MCLK_SPDIFRX0_SEL_CLK_CPLL_MUX 1U +#define MCLK_SPDIFRX0_SEL_CLK_AUPLL_MUX 2U +#define MCLK_SPDIFRX1_SEL 0x020E0098 +#define MCLK_SPDIFRX1_SEL_CLK_GPLL_MUX 0U +#define MCLK_SPDIFRX1_SEL_CLK_CPLL_MUX 1U +#define MCLK_SPDIFRX1_SEL_CLK_AUPLL_MUX 2U + +// CRU_CLKSEL_CON153(Offset:0x564) +#define MCLK_SPDIFRX2_DIV 0x05000099 +#define CLK_I2S9_8CH_RX_SRC_DIV 0x05070099 +#define MCLK_SPDIFRX2_SEL 0x02050099 +#define MCLK_SPDIFRX2_SEL_CLK_GPLL_MUX 0U +#define MCLK_SPDIFRX2_SEL_CLK_CPLL_MUX 1U +#define MCLK_SPDIFRX2_SEL_CLK_AUPLL_MUX 2U +#define CLK_I2S9_8CH_RX_SRC_SEL 0x010C0099 +#define CLK_I2S9_8CH_RX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S9_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON154(Offset:0x568) +#define CLK_I2S9_8CH_RX_FRAC_DIV 0x2000009A + +// CRU_CLKSEL_CON155(Offset:0x56C) +#define CLK_I2S10_8CH_RX_SRC_DIV 0x0503009B +#define MCLK_I2S9_8CH_RX_SEL 0x0200009B +#define MCLK_I2S9_8CH_RX_SEL_CLK_I2S9_8CH_RX_SRC 0U +#define MCLK_I2S9_8CH_RX_SEL_CLK_I2S9_8CH_RX_FRAC 1U +#define MCLK_I2S9_8CH_RX_SEL_I2S9_MCLKIN 2U +#define MCLK_I2S9_8CH_RX_SEL_XIN_OSC0_HALF 3U +#define CLK_I2S10_8CH_RX_SRC_SEL 0x0108009B +#define CLK_I2S10_8CH_RX_SRC_SEL_CLK_GPLL_MUX 0U +#define CLK_I2S10_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 1U + +// CRU_CLKSEL_CON156(Offset:0x570) +#define CLK_I2S10_8CH_RX_FRAC_DIV 0x2000009C + +// CRU_CLKSEL_CON157(Offset:0x574) +#define CLK_HDMITRX_REFSRC_DIV 0x0502009D +#define MCLK_I2S10_8CH_RX_SEL 0x0200009D +#define MCLK_I2S10_8CH_RX_SEL_CLK_I2S10_8CH_RX_SRC 0U +#define MCLK_I2S10_8CH_RX_SEL_CLK_I2S10_8CH_RX_FRAC 1U +#define MCLK_I2S10_8CH_RX_SEL_I2S10_MCLKIN 2U +#define MCLK_I2S10_8CH_RX_SEL_XIN_OSC0_HALF 3U +#define CLK_HDMITRX_REFSRC_SEL 0x0107009D +#define CLK_HDMITRX_REFSRC_SEL_CLK_GPLL_MUX 0U +#define CLK_HDMITRX_REFSRC_SEL_CLK_CPLL_MUX 1U + +// CRU_CLKSEL_CON158(Offset:0x578) +#define CLK_GPU_SRC_T_DIV 0x0500009E +#define CLK_TESTOUT_GPU_DIV 0x0508009E +#define CLK_GPU_SRC_T_SEL 0x0305009E +#define CLK_GPU_SRC_T_SEL_CLK_GPLL_MUX 0U +#define CLK_GPU_SRC_T_SEL_CLK_CPLL_MUX 1U +#define CLK_GPU_SRC_T_SEL_CLK_AUPLL_MUX 2U +#define CLK_GPU_SRC_T_SEL_CLK_NPLL_MUX 3U +#define CLK_GPU_SRC_T_SEL_CLK_SPLL_MUX 4U +#define CLK_TESTOUT_GPU_SEL 0x010D009E +#define CLK_TESTOUT_GPU_SEL_CLK_GPU_SRC_T 0U +#define CLK_TESTOUT_GPU_SEL_CLK_GPU_PVTPLL 1U +#define CLK_GPU_SRC_SEL 0x010E009E +#define CLK_GPU_SRC_SEL_CLK_GPU_SRC_T 0U +#define CLK_GPU_SRC_SEL_CLK_GPU_PVTPLL 1U + +// CRU_CLKSEL_CON159(Offset:0x57C) +#define CLK_GPU_STACKS_DIV 0x0500009F +#define ACLK_S_GPU_BIU_DIV 0x0505009F +#define ACLK_M0_GPU_BIU_DIV 0x050A009F + +// CRU_CLKSEL_CON160(Offset:0x580) +#define ACLK_M1_GPU_BIU_DIV 0x050000A0 +#define ACLK_M2_GPU_BIU_DIV 0x050500A0 +#define ACLK_M3_GPU_BIU_DIV 0x050A00A0 + +// CRU_CLKSEL_CON161(Offset:0x584) +#define PCLK_GPU_ROOT_SEL 0x020000A1 +#define PCLK_GPU_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_GPU_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_GPU_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_GPU_PVTPLL_SEL 0x010200A1 +#define CLK_GPU_PVTPLL_SEL_CLK_GPU_SRC_T 0U +#define CLK_GPU_PVTPLL_SEL_XIN_OSC0_FUNC 1U + +// CRU_CLKSEL_CON163(Offset:0x58C) +#define ACLK_AV1_ROOT_DIV 0x050000A3 +#define ACLK_AV1_ROOT_SEL 0x020500A3 +#define ACLK_AV1_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_AV1_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_AV1_ROOT_SEL_CLK_AUPLL_MUX 2U +#define PCLK_AV1_ROOT_SEL 0x020700A3 +#define PCLK_AV1_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define PCLK_AV1_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define PCLK_AV1_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define PCLK_AV1_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON165(Offset:0x594) +#define ACLK_CENTER_ROOT_SEL 0x020000A5 +#define ACLK_CENTER_ROOT_SEL_CLK_MATRIX_700M_SRC 0U +#define ACLK_CENTER_ROOT_SEL_CLK_MATRIX_400M_SRC 1U +#define ACLK_CENTER_ROOT_SEL_CLK_MATRIX_200M_SRC 2U +#define ACLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_CENTER_LOW_ROOT_SEL 0x020200A5 +#define ACLK_CENTER_LOW_ROOT_SEL_CLK_MATRIX_500M_SRC 0U +#define ACLK_CENTER_LOW_ROOT_SEL_CLK_MATRIX_250M_SRC 1U +#define ACLK_CENTER_LOW_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_CENTER_LOW_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_CENTER_ROOT_SEL 0x020400A5 +#define HCLK_CENTER_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define HCLK_CENTER_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define HCLK_CENTER_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define HCLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_CENTER_ROOT_SEL 0x020600A5 +#define PCLK_CENTER_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define PCLK_CENTER_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define PCLK_CENTER_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define PCLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_CENTER_S200_ROOT_SEL 0x020800A5 +#define ACLK_CENTER_S200_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define ACLK_CENTER_S200_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define ACLK_CENTER_S200_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define ACLK_CENTER_S200_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_CENTER_S400_ROOT_SEL 0x020A00A5 +#define ACLK_CENTER_S400_ROOT_SEL_CLK_MATRIX_400M_SRC 0U +#define ACLK_CENTER_S400_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_CENTER_S400_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_CENTER_S400_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CLK_DDR_TIMER_ROOT_SEL 0x010C00A5 +#define CLK_DDR_TIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_DDR_TIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 1U + +// CRU_CLKSEL_CON166(Offset:0x598) +#define CLK_DDR_CM0_RTC_DIV 0x050000A6 +#define CLK_DDR_CM0_RTC_SEL 0x010500A6 +#define CLK_DDR_CM0_RTC_SEL_XIN_OSC0_FUNC 0U +#define CLK_DDR_CM0_RTC_SEL_CLK_DEEPSLOW 1U + +// CRU_CLKSEL_CON170(Offset:0x5A8) +#define ACLK_VO1USB_TOP_ROOT_DIV 0x050000AA +#define ACLK_VO1USB_TOP_ROOT_SEL 0x010500AA +#define ACLK_VO1USB_TOP_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_VO1USB_TOP_ROOT_SEL_CLK_CPLL_MUX 1U +#define HCLK_VO1USB_TOP_ROOT_SEL 0x020600AA +#define HCLK_VO1USB_TOP_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_VO1USB_TOP_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_VO1USB_TOP_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_VO1USB_TOP_ROOT_SEL_XIN_OSC0_FUNC 3U + +// CRU_CLKSEL_CON172(Offset:0x5B0) +#define CCLK_SRC_SDIO_DIV 0x060200AC +#define HCLK_SDIO_ROOT_SEL 0x020000AC +#define HCLK_SDIO_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_SDIO_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_SDIO_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_SDIO_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CCLK_SRC_SDIO_SEL 0x020800AC +#define CCLK_SRC_SDIO_SEL_CLK_GPLL_MUX 0U +#define CCLK_SRC_SDIO_SEL_CLK_CPLL_MUX 1U +#define CCLK_SRC_SDIO_SEL_XIN_OSC0_FUNC 2U + +// CRU_CLKSEL_CON174(Offset:0x5B8) +#define ACLK_RGA3_ROOT_DIV 0x050000AE +#define CLK_RGA3_1_CORE_DIV 0x050900AE +#define ACLK_RGA3_ROOT_SEL 0x020500AE +#define ACLK_RGA3_ROOT_SEL_CLK_GPLL_MUX 0U +#define ACLK_RGA3_ROOT_SEL_CLK_CPLL_MUX 1U +#define ACLK_RGA3_ROOT_SEL_CLK_AUPLL_MUX 2U +#define HCLK_RGA3_ROOT_SEL 0x020700AE +#define HCLK_RGA3_ROOT_SEL_CLK_MATRIX_200M_SRC 0U +#define HCLK_RGA3_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_RGA3_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_RGA3_ROOT_SEL_XIN_OSC0_FUNC 3U +#define CLK_RGA3_1_CORE_SEL 0x020E00AE +#define CLK_RGA3_1_CORE_SEL_CLK_GPLL_MUX 0U +#define CLK_RGA3_1_CORE_SEL_CLK_CPLL_MUX 1U +#define CLK_RGA3_1_CORE_SEL_CLK_AUPLL_MUX 2U +#define CLK_RGA3_1_CORE_SEL_CLK_SPLL_MUX 3U + +// CRU_CLKSEL_CON176(Offset:0x5C0) +#define CLK_REF_PIPE_PHY0_PLL_SRC_DIV 0x060000B0 +#define CLK_REF_PIPE_PHY1_PLL_SRC_DIV 0x060600B0 + +// CRU_CLKSEL_CON177(Offset:0x5C4) +#define CLK_REF_PIPE_PHY2_PLL_SRC_DIV 0x060000B1 +#define CLK_REF_PIPE_PHY0_SEL 0x010600B1 +#define CLK_REF_PIPE_PHY0_SEL_CLK_REF_PIPE_PHY0_OSC_SRC 0U +#define CLK_REF_PIPE_PHY0_SEL_CLK_REF_PIPE_PHY0_PLL_SRC 1U +#define CLK_REF_PIPE_PHY1_SEL 0x010700B1 +#define CLK_REF_PIPE_PHY1_SEL_CLK_REF_PIPE_PHY1_OSC_SRC 0U +#define CLK_REF_PIPE_PHY1_SEL_CLK_REF_PIPE_PHY1_PLL_SRC 1U +#define CLK_REF_PIPE_PHY2_SEL 0x010800B1 +#define CLK_REF_PIPE_PHY2_SEL_CLK_REF_PIPE_PHY2_OSC_SRC 0U +#define CLK_REF_PIPE_PHY2_SEL_CLK_REF_PIPE_PHY2_PLL_SRC 1U + +// ====================== PHPTOPCRU module definition bank=1 ====================== +// PHPTOPCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_PHPTOP_CRU 0x00001001 +#define SRST_PRESETN_PCIE_COMBO_PIPE_GRF0 0x00001002 +#define SRST_PRESETN_PCIE_COMBO_PIPE_GRF1 0x00001003 +#define SRST_PRESETN_PCIE_COMBO_PIPE_GRF2 0x00001004 +#define SRST_PRESETN_PCIE_COMBO_PIPE_PHY0 0x00001005 +#define SRST_PRESETN_PCIE_COMBO_PIPE_PHY1 0x00001006 +#define SRST_PRESETN_PCIE_COMBO_PIPE_PHY2 0x00001007 +#define SRST_PRESETN_PCIE3_PHY 0x00001008 +#define SRST_PRESETN_APB2ASB_SLV_CHIP_TOP 0x00001009 +#define SRST_RESETN_PCIE3_PHY 0x0000100A + +// PHPTOPCRU_GATE_CON00(Offset:0x800) +#define PCLK_PHPTOP_CRU_GATE 0x00001001 +#define PCLK_PCIE_COMBO_PIPE_GRF0_GATE 0x00001002 +#define PCLK_PCIE_COMBO_PIPE_GRF1_GATE 0x00001003 +#define PCLK_PCIE_COMBO_PIPE_GRF2_GATE 0x00001004 +#define PCLK_PCIE_COMBO_PIPE_PHY0_GATE 0x00001005 +#define PCLK_PCIE_COMBO_PIPE_PHY1_GATE 0x00001006 +#define PCLK_PCIE_COMBO_PIPE_PHY2_GATE 0x00001007 +#define PCLK_PCIE3_PHY_GATE 0x00001008 +#define PCLK_APB2ASB_SLV_CHIP_TOP_GATE 0x00001009 + +// ====================== SECURECRU module definition bank=2 ====================== +// SECURECRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_ARESETN_SECURE_NS_BIU 0x0000200A +#define SRST_HRESETN_SECURE_NS_BIU 0x0000200B +#define SRST_ARESETN_SECURE_S_BIU 0x0000200C +#define SRST_HRESETN_SECURE_S_BIU 0x0000200D +#define SRST_PRESETN_SECURE_S_BIU 0x0000200E +#define SRST_RESETN_CRYPTO_CORE 0x0000200F + +// SECURECRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_RESETN_CRYPTO_PKA 0x00002010 +#define SRST_RESETN_CRYPTO_RNG 0x00002011 +#define SRST_ARESETN_CRYPTO 0x00002012 +#define SRST_HRESETN_CRYPTO 0x00002013 +#define SRST_RESETN_SCRYPTO_CORE 0x00002014 +#define SRST_RESETN_SCRYPTO_PKA 0x00002015 +#define SRST_RESETN_SCRYPTO_RNG 0x00002016 +#define SRST_ARESETN_SCRYPTO 0x00002017 +#define SRST_HRESETN_SCRYPTO 0x00002018 +#define SRST_RESETN_KEYLADDER_CORE 0x00002019 +#define SRST_RESETN_KEYLADDER_RNG 0x0000201A +#define SRST_ARESETN_KEYLADDER 0x0000201B +#define SRST_HRESETN_KEYLADDER 0x0000201C +#define SRST_PRESETN_OTPC_S 0x0000201D +#define SRST_RESETN_OTPC_S 0x0000201E +#define SRST_PRESETN_WDT_S 0x0000201F + +// SECURECRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_TRESETN_WDT_S 0x00002020 +#define SRST_HRESETN_BOOTROM 0x00002021 +#define SRST_ARESETN_DCF 0x00002022 +#define SRST_PRESETN_DCF 0x00002023 +#define SRST_PRESETN_STIMER0 0x00002024 +#define SRST_HRESETN_BOOTROM_NS 0x00002025 +#define SRST_RESETN_STIMER0 0x00002027 +#define SRST_RESETN_STIMER1 0x00002028 +#define SRST_RESETN_STIMER2 0x00002029 +#define SRST_RESETN_STIMER3 0x0000202A +#define SRST_RESETN_STIMER4 0x0000202B +#define SRST_RESETN_STIMER5 0x0000202C +#define SRST_PRESETN_SCRYPTO 0x0000202D +#define SRST_PRESETN_KEYLAD 0x0000202E +#define SRST_HRESETN_TRNG_S 0x0000202F + +// SECURECRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_HRESETN_TRNG_NS 0x00002030 +#define SRST_DRESETN_SDMMC_BUFFER 0x00002031 +#define SRST_HRESETN_SDMMC 0x00002032 +#define SRST_HRESETN_SDMMC_BUFFER 0x00002033 +#define SRST_RESETN_SDMMC 0x00002034 +#define SRST_PRESETN_TRNG_CHK 0x00002035 +#define SRST_RESETN_TRNG_S 0x00002036 +#define SRST_PRESETN_SECURE_CRU 0x00002037 + +// SECURECRU_GATE_CON00(Offset:0x800) +#define CLK_MATRIX_SEC_50M_SRC_GATE 0x00002000 +#define CLK_MATRIX_SEC_100M_SRC_GATE 0x00002001 +#define CLK_MATRIX_SEC_175M_SRC_GATE 0x00002002 +#define CLK_MATRIX_SEC_200M_SRC_GATE 0x00002003 +#define CLK_MATRIX_SEC_333M_SRC_GATE 0x00002004 +#define ACLK_SECURE_NS_ROOT_GATE 0x00002005 +#define HCLK_SECURE_NS_ROOT_GATE 0x00002006 +#define ACLK_SECURE_S_ROOT_GATE 0x00002007 +#define HCLK_SECURE_S_ROOT_GATE 0x00002008 +#define PCLK_SECURE_S_ROOT_GATE 0x00002009 +#define ACLK_SECURE_NS_BIU_GATE 0x0000200A +#define HCLK_SECURE_NS_BIU_GATE 0x0000200B +#define ACLK_SECURE_S_BIU_GATE 0x0000200C +#define HCLK_SECURE_S_BIU_GATE 0x0000200D +#define PCLK_SECURE_S_BIU_GATE 0x0000200E +#define CLK_CRYPTO_CORE_GATE 0x0000200F + +// SECURECRU_GATE_CON01(Offset:0x804) +#define CLK_CRYPTO_PKA_GATE 0x00002010 +#define CLK_CRYPTO_RNG_GATE 0x00002011 +#define ACLK_CRYPTO_GATE 0x00002012 +#define HCLK_CRYPTO_GATE 0x00002013 +#define CLK_SCRYPTO_CORE_GATE 0x00002014 +#define CLK_SCRYPTO_PKA_GATE 0x00002015 +#define CLK_SCRYPTO_RNG_GATE 0x00002016 +#define ACLK_SCRYPTO_GATE 0x00002017 +#define HCLK_SCRYPTO_GATE 0x00002018 +#define CLK_KEYLADDER_CORE_GATE 0x00002019 +#define CLK_KEYLADDER_RNG_GATE 0x0000201A +#define ACLK_KEYLADDER_GATE 0x0000201B +#define HCLK_KEYLADDER_GATE 0x0000201C +#define PCLK_OTPC_S_GATE 0x0000201D +#define CLK_OTPC_S_GATE 0x0000201E +#define PCLK_WDT_S_GATE 0x0000201F + +// SECURECRU_GATE_CON02(Offset:0x808) +#define TCLK_WDT_S_GATE 0x00002020 +#define HCLK_BOOTROM_GATE 0x00002021 +#define ACLK_DCF_GATE 0x00002022 +#define PCLK_DCF_GATE 0x00002023 +#define PCLK_STIMER0_GATE 0x00002024 +#define HCLK_BOOTROM_NS_GATE 0x00002025 +#define CLK_STIMER_ROOT_GATE 0x00002026 +#define CLK_STIMER0_GATE 0x00002027 +#define CLK_STIMER1_GATE 0x00002028 +#define CLK_STIMER2_GATE 0x00002029 +#define CLK_STIMER3_GATE 0x0000202A +#define CLK_STIMER4_GATE 0x0000202B +#define CLK_STIMER5_GATE 0x0000202C +#define PCLK_SCRYPTO_GATE 0x0000202D +#define PCLK_KEYLAD_GATE 0x0000202E +#define HCLK_TRNG_S_GATE 0x0000202F + +// SECURECRU_GATE_CON03(Offset:0x80C) +#define HCLK_TRNG_NS_GATE 0x00002030 +#define DCLK_SDMMC_BUFFER_GATE 0x00002031 +#define HCLK_SDMMC_GATE 0x00002032 +#define HCLK_SDMMC_BUFFER_GATE 0x00002033 +#define CCLK_SRC_SDMMC_GATE 0x00002034 +#define PCLK_TRNG_CHK_GATE 0x00002035 +#define CLK_TRNG_S_GATE 0x00002036 +#define PCLK_SECURE_CRU_GATE 0x00002037 + +// SECURECRU_CLKSEL_CON00(Offset:0x300) +#define CLK_MATRIX_SEC_58M_SRC_DIV 0x03000200 +#define CLK_MATRIX_SEC_116M_SRC_DIV 0x03030200 +#define CLK_MATRIX_SEC_175M_SRC_DIV 0x03060200 +#define CLK_MATRIX_SEC_233M_SRC_DIV 0x03090200 +#define CLK_MATRIX_SEC_350M_SRC_DIV 0x030C0200 + +// SECURECRU_CLKSEL_CON01(Offset:0x304) +#define ACLK_SECURE_NS_ROOT_SEL 0x02000201 +#define ACLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_350M_SRC 0U +#define ACLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_200M_SRC 1U +#define ACLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_100M_SRC 2U +#define ACLK_SECURE_NS_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_SECURE_NS_ROOT_SEL 0x02020201 +#define HCLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_150M_SRC 0U +#define HCLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_100M_SRC 1U +#define HCLK_SECURE_NS_ROOT_SEL_CLK_MATRIX_50M_SRC 2U +#define HCLK_SECURE_NS_ROOT_SEL_XIN_OSC0_FUNC 3U +#define ACLK_SECURE_S_ROOT_SEL 0x02040201 +#define ACLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define ACLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define ACLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define ACLK_SECURE_S_ROOT_SEL_XIN_OSC0_FUNC 3U +#define HCLK_SECURE_S_ROOT_SEL 0x02060201 +#define HCLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_175M_SRC 0U +#define HCLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_116M_SRC 1U +#define HCLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_58M_SRC 2U +#define HCLK_SECURE_S_ROOT_SEL_XIN_OSC0_FUNC 3U +#define PCLK_SECURE_S_ROOT_SEL 0x02080201 +#define PCLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_116M_SRC 0U +#define PCLK_SECURE_S_ROOT_SEL_CLK_MATRIX_SEC_58M_SRC 1U +#define PCLK_SECURE_S_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_CRYPTO_CORE_SEL 0x020A0201 +#define CLK_CRYPTO_CORE_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define CLK_CRYPTO_CORE_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define CLK_CRYPTO_CORE_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define CLK_CRYPTO_CORE_SEL_XIN_OSC0_FUNC 3U +#define CLK_CRYPTO_PKA_SEL 0x020C0201 +#define CLK_CRYPTO_PKA_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define CLK_CRYPTO_PKA_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define CLK_CRYPTO_PKA_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define CLK_CRYPTO_PKA_SEL_XIN_OSC0_FUNC 3U +#define CLK_CRYPTO_RNG_SEL 0x020E0201 +#define CLK_CRYPTO_RNG_SEL_CLK_MATRIX_SEC_175M_SRC 0U +#define CLK_CRYPTO_RNG_SEL_CLK_MATRIX_SEC_116M_SRC 1U +#define CLK_CRYPTO_RNG_SEL_CLK_MATRIX_SEC_58M_SRC 2U +#define CLK_CRYPTO_RNG_SEL_XIN_OSC0_FUNC 3U + +// SECURECRU_CLKSEL_CON02(Offset:0x308) +#define CLK_SCRYPTO_CORE_SEL 0x02000202 +#define CLK_SCRYPTO_CORE_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define CLK_SCRYPTO_CORE_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define CLK_SCRYPTO_CORE_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define CLK_SCRYPTO_CORE_SEL_XIN_OSC0_FUNC 3U +#define CLK_SCRYPTO_PKA_SEL 0x02020202 +#define CLK_SCRYPTO_PKA_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define CLK_SCRYPTO_PKA_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define CLK_SCRYPTO_PKA_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define CLK_SCRYPTO_PKA_SEL_XIN_OSC0_FUNC 3U +#define CLK_SCRYPTO_RNG_SEL 0x02040202 +#define CLK_SCRYPTO_RNG_SEL_CLK_MATRIX_SEC_175M_SRC 0U +#define CLK_SCRYPTO_RNG_SEL_CLK_MATRIX_SEC_116M_SRC 1U +#define CLK_SCRYPTO_RNG_SEL_CLK_MATRIX_SEC_58M_SRC 2U +#define CLK_SCRYPTO_RNG_SEL_XIN_OSC0_FUNC 3U +#define CLK_KEYLADDER_CORE_SEL 0x02060202 +#define CLK_KEYLADDER_CORE_SEL_CLK_MATRIX_SEC_350M_SRC 0U +#define CLK_KEYLADDER_CORE_SEL_CLK_MATRIX_SEC_233M_SRC 1U +#define CLK_KEYLADDER_CORE_SEL_CLK_MATRIX_SEC_116M_SRC 2U +#define CLK_KEYLADDER_CORE_SEL_XIN_OSC0_FUNC 3U +#define CLK_KEYLADDER_RNG_SEL 0x02080202 +#define CLK_KEYLADDER_RNG_SEL_CLK_MATRIX_SEC_175M_SRC 0U +#define CLK_KEYLADDER_RNG_SEL_CLK_MATRIX_SEC_116M_SRC 1U +#define CLK_KEYLADDER_RNG_SEL_CLK_MATRIX_SEC_58M_SRC 2U +#define CLK_KEYLADDER_RNG_SEL_XIN_OSC0_FUNC 3U +#define CLK_STIMER_ROOT_SEL 0x010A0202 +#define CLK_STIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_STIMER_ROOT_SEL_CLK_MATRIX_SEC_116M_SRC 1U + +// SECURECRU_CLKSEL_CON03(Offset:0x30C) +#define DCLK_SDMMC_BUFFER_DIV 0x05000203 +#define CCLK_SRC_SDMMC_DIV 0x06060203 +#define DCLK_SDMMC_BUFFER_SEL 0x01050203 +#define DCLK_SDMMC_BUFFER_SEL_CLK_GPLL_MUX 0U +#define DCLK_SDMMC_BUFFER_SEL_CLK_SPLL_MUX 1U +#define CCLK_SRC_SDMMC_SEL 0x020C0203 +#define CCLK_SRC_SDMMC_SEL_CLK_GPLL_MUX 0U +#define CCLK_SRC_SDMMC_SEL_CLK_SPLL_MUX 1U +#define CCLK_SRC_SDMMC_SEL_XIN_OSC0_FUNC 2U + +// ======================= SBUSCRU module definition bank=3 ======================= +// SBUSCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_PRESETN_SBUS_BIU 0x00003001 +#define SRST_PRESETN_SBUS_CRU 0x00003002 +#define SRST_PRESETN_SBUS_SGRF 0x00003003 +#define SRST_PRESETN_JDBCK_DAP 0x00003004 +#define SRST_RESETN_JDBCK_DAP 0x00003005 +#define SRST_PRESETN_STIMER1 0x00003007 +#define SRST_RESETN_STIMER6 0x00003009 +#define SRST_RESETN_STIMER7 0x0000300A +#define SRST_RESETN_STIMER8 0x0000300B +#define SRST_RESETN_STIMER9 0x0000300C +#define SRST_RESETN_STIMER10 0x0000300D +#define SRST_RESETN_STIMER11 0x0000300E + +// SBUSCRU_GATE_CON00(Offset:0x800) +#define PCLK_SBUS_ROOT_GATE 0x00003000 +#define PCLK_SBUS_BIU_GATE 0x00003001 +#define PCLK_SBUS_CRU_GATE 0x00003002 +#define PCLK_SBUS_SGRF_GATE 0x00003003 +#define PCLK_JDBCK_DAP_GATE 0x00003004 +#define CLK_JDBCK_DAP_GATE 0x00003005 +#define CLK_MATRIX_SBUS_100M_SRC_GATE 0x00003006 +#define PCLK_STIMER1_GATE 0x00003007 +#define CLK_SBUS_TIMER_GATE 0x00003008 +#define CLK_STIMER6_GATE 0x00003009 +#define CLK_STIMER7_GATE 0x0000300A +#define CLK_STIMER8_GATE 0x0000300B +#define CLK_STIMER9_GATE 0x0000300C +#define CLK_STIMER10_GATE 0x0000300D +#define CLK_STIMER11_GATE 0x0000300E + +// SBUSCRU_CLKSEL_CON00(Offset:0x300) +#define PCLK_SBUS_ROOT_DIV 0x05000300 +#define CLK_MATRIX_SBUS_100M_SRC_DIV 0x05050300 +#define CLK_MATRIX_SBUS_100M_SRC_SEL 0x010A0300 +#define CLK_MATRIX_SBUS_100M_SRC_SEL_CLK_SPLL_MUX 0U +#define CLK_MATRIX_SBUS_100M_SRC_SEL_CLK_CPLL_MUX 1U +#define CLK_SBUS_TIMER_ROOT_SEL 0x010B0300 +#define CLK_SBUS_TIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_SBUS_TIMER_ROOT_SEL_CLK_MATRIX_SBUS_100M_SRC 1U + +// ====================== PMU1SCRU module definition bank=4 ======================= +// PMU1SCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_HRESETN_PMU1_S_BIU 0x00004004 +#define SRST_PRESETN_PMU1_S_BIU 0x00004005 +#define SRST_PRESETN_PMU1_OSC_CHK 0x00004006 +#define SRST_HRESETN_PMU1_MEM 0x00004007 +#define SRST_PRESETN_PMU1_SGRF 0x00004008 +#define SRST_PRESETN_PMU1_CRU_S 0x00004009 + +// PMU1SCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_RESETN_PMU0PVTM 0x00004012 +#define SRST_PRESETN_PMU0PVTM 0x00004013 +#define SRST_PRESETN_PMU0_SGRF 0x00004014 +#define SRST_PRESETN_PMU0_SGRF_REMAP 0x00004015 +#define SRST_PRESETN_PMU0_HP_TIMER 0x00004017 +#define SRST_RESETN_PMU0_HP_TIMER 0x00004018 +#define SRST_RESETN_PMU0_32K_HP_TIMER 0x00004019 + +// PMU1SCRU_GATE_CON00(Offset:0x800) +#define HCLK_PMU1_S_ROOT_I_GATE 0x00004001 +#define HCLK_PMU1_S_ROOT_GATE 0x00004002 +#define PCLK_PMU1_S_ROOT_GATE 0x00004003 +#define HCLK_PMU1_S_BIU_GATE 0x00004004 +#define PCLK_PMU1_S_BIU_GATE 0x00004005 +#define PCLK_PMU1_OSC_CHK_GATE 0x00004006 +#define HCLK_PMU1_MEM_GATE 0x00004007 +#define PCLK_PMU1_SGRF_GATE 0x00004008 +#define PCLK_PMU1_CRU_S_GATE 0x00004009 + +// PMU1SCRU_GATE_CON01(Offset:0x804) +#define XIN_OSC0_DIV_GATE 0x00004010 +#define PCLK_PMU0_S_ROOT_GATE 0x00004011 +#define CLK_PMU0PVTM_GATE 0x00004012 +#define PCLK_PMU0PVTM_GATE 0x00004013 +#define PCLK_PMU0_SGRF_GATE 0x00004014 +#define PCLK_PMU0_SCRKEYGEN_GATE 0x00004016 +#define PCLK_PMU0_HP_TIMER_GATE 0x00004017 +#define CLK_PMU0_HP_TIMER_GATE 0x00004018 +#define CLK_PMU0_32K_HP_TIMER_GATE 0x00004019 + +// PMU1SCRU_CLKSEL_CON00(Offset:0x300) +#define HCLK_PMU1_S_ROOT_I_SEL 0x02000400 +#define HCLK_PMU1_S_ROOT_I_SEL_CLK_MATRIX_PMU1_200M_SRC 0U +#define HCLK_PMU1_S_ROOT_I_SEL_CLK_MATRIX_PMU1_100M_SRC 1U +#define HCLK_PMU1_S_ROOT_I_SEL_CLK_MATRIX_PMU1_50M_SRC 2U +#define HCLK_PMU1_S_ROOT_I_SEL_XIN_OSC0_FUNC 3U +#define PCLK_PMU1_S_ROOT_I_SEL 0x02020400 +#define PCLK_PMU1_S_ROOT_I_SEL_CLK_MATRIX_PMU1_100M_SRC 0U +#define PCLK_PMU1_S_ROOT_I_SEL_CLK_MATRIX_PMU1_50M_SRC 1U +#define PCLK_PMU1_S_ROOT_I_SEL_XIN_OSC0_FUNC 2U + +// PMU1SCRU_CLKSEL_CON02(Offset:0x308) +#define XIN_OSC0_DIV_DIV 0x20000402 + +// ======================= PMU1CRU module definition bank=5 ======================= +// PMU1CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_HRESETN_PMU1_BIU 0x0000500A +#define SRST_PRESETN_PMU1_BIU 0x0000500B +#define SRST_HRESETN_PMU_CM0_BIU 0x0000500C +#define SRST_FRESETN_PMU_CM0_CORE 0x0000500D +#define SRST_TRESETN_PMU1_CM0_JTAG 0x0000500E + +// PMU1CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_RESETN_DDR_FAIL_SAFE 0x00005011 +#define SRST_PRESETN_CRU_PMU1 0x00005012 +#define SRST_PRESETN_PMU1_GRF 0x00005014 +#define SRST_PRESETN_PMU1_IOC 0x00005015 +#define SRST_PRESETN_PMU1WDT 0x00005016 +#define SRST_TRESETN_PMU1WDT 0x00005017 +#define SRST_PRESETN_PMU1TIMER 0x00005018 +#define SRST_RESETN_PMU1TIMER0 0x0000501A +#define SRST_RESETN_PMU1TIMER1 0x0000501B +#define SRST_PRESETN_PMU1PWM 0x0000501C +#define SRST_RESETN_PMU1PWM 0x0000501D + +// PMU1CRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_PRESETN_I2C0 0x00005021 +#define SRST_RESETN_I2C0 0x00005022 +#define SRST_SRESETN_UART0 0x00005025 +#define SRST_PRESETN_UART0 0x00005026 +#define SRST_HRESETN_I2S1_8CH 0x00005027 +#define SRST_MRESETN_I2S1_8CH_TX 0x0000502A +#define SRST_MRESETN_I2S1_8CH_RX 0x0000502D +#define SRST_HRESETN_PDM0 0x0000502E +#define SRST_RESETN_PDM0 0x0000502F + +// PMU1CRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_HRESETN_VAD 0x00005030 +#define SRST_RESETN_HDPTX0_INIT 0x0000503B +#define SRST_RESETN_HDPTX0_CMN 0x0000503C +#define SRST_RESETN_HDPTX0_LANE 0x0000503D +#define SRST_RESETN_HDPTX1_INIT 0x0000503F + +// PMU1CRU_SOFTRST_CON04(Offset:0xA10) +#define SRST_RESETN_HDPTX1_CMN 0x00005040 +#define SRST_RESETN_HDPTX1_LANE 0x00005041 +#define SRST_MRESETN_MIPI_DCPHY0 0x00005043 +#define SRST_SRESETN_MIPI_DCPHY0 0x00005044 +#define SRST_MRESETN_MIPI_DCPHY1 0x00005045 +#define SRST_SRESETN_MIPI_DCPHY1 0x00005046 +#define SRST_RESETN_OTGPHY_U3_0 0x00005047 +#define SRST_RESETN_OTGPHY_U3_1 0x00005048 +#define SRST_RESETN_OTGPHY_U2_0 0x00005049 +#define SRST_RESETN_OTGPHY_U2_1 0x0000504A + +// PMU1CRU_SOFTRST_CON05(Offset:0xA14) +#define SRST_PRESETN_PMU0GRF 0x00005053 +#define SRST_PRESETN_PMU0IOC 0x00005054 +#define SRST_PRESETN_GPIO0 0x00005055 +#define SRST_DBRESETN_GPIO0 0x00005056 + +// PMU1CRU_GATE_CON00(Offset:0x800) +#define CLK_MATRIX_PMU1_50M_SRC_GATE 0x00005000 +#define CLK_MATRIX_PMU1_100M_SRC_GATE 0x00005001 +#define CLK_MATRIX_PMU1_200M_SRC_GATE 0x00005002 +#define CLK_MATRIX_PMU1_300M_SRC_GATE 0x00005003 +#define CLK_MATRIX_PMU1_400M_SRC_GATE 0x00005004 +#define HCLK_PMU1_ROOT_I_GATE 0x00005005 +#define HCLK_PMU1_ROOT_GATE 0x00005006 +#define PCLK_PMU1_ROOT_I_GATE 0x00005007 +#define HCLK_PMU_CM0_ROOT_I_GATE 0x00005008 +#define HCLK_PMU_CM0_ROOT_GATE 0x00005009 +#define HCLK_PMU1_BIU_GATE 0x0000500A +#define PCLK_PMU1_BIU_GATE 0x0000500B +#define HCLK_PMU_CM0_BIU_GATE 0x0000500C +#define FCLK_PMU_CM0_CORE_GATE 0x0000500D +#define CLK_PMU_CM0_RTC_GATE 0x0000500F + +// PMU1CRU_GATE_CON01(Offset:0x804) +#define PCLK_PMU1_GATE 0x00005010 +#define CLK_DDR_FAIL_SAFE_GATE 0x00005011 +#define PCLK_PMU1_CRU_GATE 0x00005012 +#define CLK_PMU1_GATE 0x00005013 +#define PCLK_PMU1_GRF_GATE 0x00005014 +#define PCLK_PMU1_IOC_GATE 0x00005015 +#define PCLK_PMU1WDT_GATE 0x00005016 +#define TCLK_PMU1WDT_GATE 0x00005017 +#define PCLK_PMU1TIMER_GATE 0x00005018 +#define CLK_PMU1TIMER_ROOT_GATE 0x00005019 +#define CLK_PMU1TIMER0_GATE 0x0000501A +#define CLK_PMU1TIMER1_GATE 0x0000501B +#define PCLK_PMU1PWM_GATE 0x0000501C +#define CLK_PMU1PWM_GATE 0x0000501D +#define CLK_PMU1PWM_CAPTURE_GATE 0x0000501E + +// PMU1CRU_GATE_CON02(Offset:0x808) +#define PCLK_I2C0_GATE 0x00005021 +#define CLK_I2C0_GATE 0x00005022 +#define CLK_UART0_GATE 0x00005023 +#define CLK_UART0_FRAC_GATE 0x00005024 +#define SCLK_UART0_GATE 0x00005025 +#define PCLK_UART0_GATE 0x00005026 +#define HCLK_I2S1_8CH_GATE 0x00005027 +#define CLK_I2S1_8CH_TX_GATE 0x00005028 +#define CLK_I2S1_8CH_FRAC_TX_GATE 0x00005029 +#define MCLK_I2S1_8CH_TX_GATE 0x0000502A +#define CLK_I2S1_8CH_RX_GATE 0x0000502B +#define CLK_I2S1_8CH_FRAC_RX_GATE 0x0000502C +#define MCLK_I2S1_8CH_RX_GATE 0x0000502D +#define HCLK_PDM0_GATE 0x0000502E +#define MCLK_PDM0_GATE 0x0000502F + +// PMU1CRU_GATE_CON03(Offset:0x80C) +#define HCLK_VAD_GATE 0x00005030 +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_GATE 0x00005035 +#define CLK_HDPTX0_REF_XTAL_GATE 0x0000503B + +// PMU1CRU_GATE_CON04(Offset:0x810) +#define CLK_REF_MIPI_DCPHY0_GATE 0x00005043 +#define CLK_OTGPHY_U3_0_GATE 0x00005047 +#define CLK_CR_PARA_GATE 0x0000504B + +// PMU1CRU_GATE_CON05(Offset:0x814) +#define PCLK_PMU0_ROOT_GATE 0x00005050 +#define CLK_PMU0_GATE 0x00005051 +#define PCLK_PMU0_GATE 0x00005052 +#define PCLK_PMU0GRF_GATE 0x00005053 +#define PCLK_PMU0IOC_GATE 0x00005054 +#define PCLK_GPIO0_GATE 0x00005055 +#define DBCLK_GPIO0_GATE 0x00005056 + +// PMU1CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_MATRIX_PMU1_50M_SRC_DIV 0x04000500 +#define CLK_MATRIX_PMU1_100M_SRC_DIV 0x03040500 +#define CLK_MATRIX_PMU1_200M_SRC_DIV 0x03070500 +#define CLK_MATRIX_PMU1_300M_SRC_DIV 0x050A0500 +#define CLK_MATRIX_PMU1_300M_SRC_SEL 0x010F0500 +#define CLK_MATRIX_PMU1_300M_SRC_SEL_CLK_MATRIX_300M_SRC 0U +#define CLK_MATRIX_PMU1_300M_SRC_SEL_XIN_OSC0_FUNC 1U + +// PMU1CRU_CLKSEL_CON01(Offset:0x304) +#define CLK_MATRIX_PMU1_400M_SRC_DIV 0x05000501 +#define CLK_MATRIX_PMU1_400M_SRC_SEL 0x01050501 +#define CLK_MATRIX_PMU1_400M_SRC_SEL_CLK_MATRIX_400M_SRC 0U +#define CLK_MATRIX_PMU1_400M_SRC_SEL_XIN_OSC0_FUNC 1U +#define HCLK_PMU1_ROOT_I_SEL 0x02060501 +#define HCLK_PMU1_ROOT_I_SEL_CLK_MATRIX_PMU1_200M_SRC 0U +#define HCLK_PMU1_ROOT_I_SEL_CLK_MATRIX_PMU1_100M_SRC 1U +#define HCLK_PMU1_ROOT_I_SEL_CLK_MATRIX_PMU1_50M_SRC 2U +#define HCLK_PMU1_ROOT_I_SEL_XIN_OSC0_FUNC 3U +#define PCLK_PMU1_ROOT_I_SEL 0x02080501 +#define PCLK_PMU1_ROOT_I_SEL_CLK_MATRIX_PMU1_100M_SRC 0U +#define PCLK_PMU1_ROOT_I_SEL_CLK_MATRIX_PMU1_50M_SRC 1U +#define PCLK_PMU1_ROOT_I_SEL_XIN_OSC0_FUNC 2U +#define HCLK_PMU_CM0_ROOT_I_SEL 0x020A0501 +#define HCLK_PMU_CM0_ROOT_I_SEL_CLK_MATRIX_PMU1_400M_SRC 0U +#define HCLK_PMU_CM0_ROOT_I_SEL_CLK_MATRIX_PMU1_200M_SRC 1U +#define HCLK_PMU_CM0_ROOT_I_SEL_CLK_MATRIX_PMU1_100M_SRC 2U +#define HCLK_PMU_CM0_ROOT_I_SEL_XIN_OSC0_FUNC 3U + +// PMU1CRU_CLKSEL_CON02(Offset:0x308) +#define CLK_PMU_CM0_RTC_DIV 0x05000502 +#define CLK_PMU_CM0_RTC_SEL 0x01050502 +#define CLK_PMU_CM0_RTC_SEL_XIN_OSC0_FUNC 0U +#define CLK_PMU_CM0_RTC_SEL_CLK_DEEPSLOW 1U +#define TCLK_PMU1WDT_SEL 0x01060502 +#define TCLK_PMU1WDT_SEL_XIN_OSC0_FUNC 0U +#define TCLK_PMU1WDT_SEL_CLK_DEEPSLOW 1U +#define CLK_PMU1TIMER_ROOT_SEL 0x02070502 +#define CLK_PMU1TIMER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_PMU1TIMER_ROOT_SEL_CLK_DEEPSLOW 1U +#define CLK_PMU1TIMER_ROOT_SEL_CLK_MATRIX_PMU1_100M_SRC 2U +#define CLK_PMU1PWM_SEL 0x02090502 +#define CLK_PMU1PWM_SEL_CLK_MATRIX_PMU1_100M_SRC 0U +#define CLK_PMU1PWM_SEL_CLK_MATRIX_PMU1_50M_SRC 1U +#define CLK_PMU1PWM_SEL_XIN_OSC0_FUNC 2U + +// PMU1CRU_CLKSEL_CON03(Offset:0x30C) +#define CLK_UART0_SRC_DIV 0x05070503 +#define CLK_I2C0_SEL 0x01060503 +#define CLK_I2C0_SEL_CLK_MATRIX_PMU1_200M_SRC 0U +#define CLK_I2C0_SEL_CLK_MATRIX_PMU1_100M_SRC 1U + +// PMU1CRU_CLKSEL_CON04(Offset:0x310) +#define CLK_UART0_FRAC_DIV 0x20000504 + +// PMU1CRU_CLKSEL_CON05(Offset:0x314) +#define CLK_I2S1_8CH_TX_SRC_DIV 0x05020505 +#define SCLK_UART0_SEL 0x02000505 +#define SCLK_UART0_SEL_CLK_UART0_SRC 0U +#define SCLK_UART0_SEL_CLK_UART0_FRAC 1U +#define SCLK_UART0_SEL_XIN_OSC0_FUNC 2U + +// PMU1CRU_CLKSEL_CON06(Offset:0x318) +#define CLK_I2S1_8CH_TX_FRAC_DIV 0x20000506 + +// PMU1CRU_CLKSEL_CON07(Offset:0x31C) +#define CLK_I2S1_8CH_RX_SRC_DIV 0x05020507 +#define MCLK_I2S1_8CH_TX_SEL 0x02000507 +#define MCLK_I2S1_8CH_TX_SEL_CLK_I2S1_8CH_TX_SRC 0U +#define MCLK_I2S1_8CH_TX_SEL_CLK_I2S1_8CH_TX_FRAC 1U +#define MCLK_I2S1_8CH_TX_SEL_I2S1_MCLKIN 2U +#define MCLK_I2S1_8CH_TX_SEL_XIN_OSC0_HALF 3U + +// PMU1CRU_CLKSEL_CON08(Offset:0x320) +#define CLK_I2S1_8CH_RX_FRAC_DIV 0x20000508 + +// PMU1CRU_CLKSEL_CON09(Offset:0x324) +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_DIV 0x05050509 +#define MCLK_I2S1_8CH_RX_SEL 0x02000509 +#define MCLK_I2S1_8CH_RX_SEL_CLK_I2S1_8CH_RX_SRC 0U +#define MCLK_I2S1_8CH_RX_SEL_CLK_I2S1_8CH_RX_FRAC 1U +#define MCLK_I2S1_8CH_RX_SEL_I2S1_MCLKIN 2U +#define MCLK_I2S1_8CH_RX_SEL_XIN_OSC0_HALF 3U +#define I2S1_8CH_MCLKOUT_SEL 0x02020509 +#define I2S1_8CH_MCLKOUT_SEL_MCLK_I2S1_8CH_TX 0U +#define I2S1_8CH_MCLKOUT_SEL_MCLK_I2S1_8CH_RX 1U +#define I2S1_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 2U +#define MCLK_PDM0_SEL 0x01040509 +#define MCLK_PDM0_SEL_CLK_MATRIX_PMU1_300M_SRC 0U +#define MCLK_PDM0_SEL_CLK_MATRIX_PMU1_200M_SRC 1U +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL 0x010A0509 +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_XIN_OSC0_FUNC 0U +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_CLK_PPLL 1U + +// PMU1CRU_CLKSEL_CON12(Offset:0x330) +#define CLK_HDPTX0_REF_XTAL_DIV 0x0506050C +#define CLK_HDPTX0_REF_XTAL_SEL 0x010B050C +#define CLK_HDPTX0_REF_XTAL_SEL_XIN_OSC0_FUNC 0U +#define CLK_HDPTX0_REF_XTAL_SEL_CLK_PPLL 1U + +// PMU1CRU_CLKSEL_CON14(Offset:0x338) +#define CLK_REF_MIPI_DCPHY0_DIV 0x0700050E +#define CLK_OTGPHY_U3_0_DIV 0x0509050E +#define CLK_REF_MIPI_DCPHY0_SEL 0x0207050E +#define CLK_REF_MIPI_DCPHY0_SEL_XIN_OSC0_FUNC 0U +#define CLK_REF_MIPI_DCPHY0_SEL_CLK_PPLL 1U +#define CLK_REF_MIPI_DCPHY0_SEL_CLK_SPLL_MUX 2U +#define CLK_OTGPHY_U3_0_SEL 0x010E050E +#define CLK_OTGPHY_U3_0_SEL_XIN_OSC0_FUNC 0U +#define CLK_OTGPHY_U3_0_SEL_CLK_PPLL 1U + +// PMU1CRU_CLKSEL_CON15(Offset:0x33C) +#define CLK_CR_PARA_DIV 0x0500050F +#define CLK_CR_PARA_SEL 0x0205050F +#define CLK_CR_PARA_SEL_XIN_OSC0_FUNC 0U +#define CLK_CR_PARA_SEL_CLK_PPLL 1U +#define CLK_CR_PARA_SEL_CLK_SPLL_MUX 2U + +// PMU1CRU_CLKSEL_CON17(Offset:0x344) +#define DBCLK_GPIO0_SEL 0x01000511 +#define DBCLK_GPIO0_SEL_XIN_OSC0_FUNC 0U +#define DBCLK_GPIO0_SEL_CLK_DEEPSLOW 1U + +// ======================= DDR0CRU module definition bank=6 ======================= +// DDR0CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_DDRPHY2XDIV_CH0 0x00006001 +#define SRST_RESETN_DDRPHY2X_CH0 0x00006002 +#define SRST_PRESETN_DDR_CRU_CH0 0x00006003 +#define SRST_PRESETN_DDRPHY_CH0 0x00006004 + +// DDR0CRU_GATE_CON00(Offset:0x800) +#define PCLK_DDR_CRU_CH0_GATE 0x00006003 +#define PCLK_DDRPHY_CH0_GATE 0x00006004 +#define CLK_OSC_DDRPHY_CH0_GATE 0x00006005 + +// DDR0CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_DDRPHY2X_CH0_SEL 0x01000600 +#define CLK_DDRPHY2X_CH0_SEL_CLK_D0APLL_T 0U +#define CLK_DDRPHY2X_CH0_SEL_CLK_D0BPLL 1U + +// ======================= DDR1CRU module definition bank=7 ======================= +// DDR1CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_DDRPHY2XDIV_CH1 0x00007001 +#define SRST_RESETN_DDRPHY2X_CH1 0x00007002 +#define SRST_PRESETN_DDR_CRU_CH1 0x00007003 +#define SRST_PRESETN_DDRPHY_CH1 0x00007004 + +// DDR1CRU_GATE_CON00(Offset:0x800) +#define PCLK_DDR_CRU_CH1_GATE 0x00007003 +#define PCLK_DDRPHY_CH1_GATE 0x00007004 +#define CLK_OSC_DDRPHY_CH1_GATE 0x00007005 + +// DDR1CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_DDRPHY2X_CH1_SEL 0x01000700 +#define CLK_DDRPHY2X_CH1_SEL_CLK_D1APLL_T 0U +#define CLK_DDRPHY2X_CH1_SEL_CLK_D1BPLL 1U + +// ======================= DDR2CRU module definition bank=8 ======================= +// DDR2CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_DDRPHY2XDIV_CH2 0x00008001 +#define SRST_RESETN_DDRPHY2X_CH2 0x00008002 +#define SRST_PRESETN_DDR_CRU_CH2 0x00008003 +#define SRST_PRESETN_DDRPHY_CH2 0x00008004 + +// DDR2CRU_GATE_CON00(Offset:0x800) +#define PCLK_DDR_CRU_CH2_GATE 0x00008003 +#define PCLK_DDRPHY_CH2_GATE 0x00008004 +#define CLK_OSC_DDRPHY_CH2_GATE 0x00008005 + +// DDR2CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_DDRPHY2X_CH2_SEL 0x01000800 +#define CLK_DDRPHY2X_CH2_SEL_CLK_D2APLL_T 0U +#define CLK_DDRPHY2X_CH2_SEL_CLK_D2BPLL 1U + +// ======================= DDR3CRU module definition bank=9 ======================= +// DDR3CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_RESETN_DDRPHY2XDIV_CH3 0x00009001 +#define SRST_RESETN_DDRPHY2X_CH3 0x00009002 +#define SRST_PRESETN_DDR_CRU_CH3 0x00009003 +#define SRST_PRESETN_DDRPHY_CH3 0x00009004 + +// DDR3CRU_GATE_CON00(Offset:0x800) +#define PCLK_DDR_CRU_CH3_GATE 0x00009003 +#define PCLK_DDRPHY_CH3_GATE 0x00009004 +#define CLK_OSC_DDRPHY_CH3_GATE 0x00009005 + +// DDR3CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_DDRPHY2X_CH3_SEL 0x01000900 +#define CLK_DDRPHY2X_CH3_SEL_CLK_D3APLL_T 0U +#define CLK_DDRPHY2X_CH3_SEL_CLK_D3BPLL 1U + +// ==================== BIGCORE0CRU module definition bank=10 ===================== +// BIGCORE0CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_NCPUPORESET_B0 0x0000A004 +#define SRST_NCORERESET_B0 0x0000A005 +#define SRST_NCPUPORESET_B1 0x0000A008 +#define SRST_NCORERESET_B1 0x0000A009 +#define SRST_RESETN_BIGCORE0_PVTPLL 0x0000A00B +#define SRST_RESETN_BIGCORE0_PVTM 0x0000A00C +#define SRST_PRESETN_BIGCORE0_BIU 0x0000A00F + +// BIGCORE0CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_BIGCORE0_PVTM 0x0000A010 +#define SRST_PRESETN_BIGCORE0_GRF 0x0000A011 +#define SRST_PRESETN_BIGCORE0_CRU 0x0000A012 +#define SRST_PRESETN_BIGCORE0_CPUBOOST 0x0000A013 +#define SRST_RESETN_24M_BIGCORE0_CPUBOOST 0x0000A014 + +// BIGCORE0CRU_GATE_CON00(Offset:0x800) +#define CLK_CORE_B01_I_GATE 0x0000A001 +#define CLK_CORE_B0_CLEAN_GATE 0x0000A002 +#define CLK_CORE_B0_UC_GATE 0x0000A003 +#define CLK_CORE_B1_CLEAN_GATE 0x0000A006 +#define CLK_CORE_B1_UC_GATE 0x0000A007 +#define CLK_TESTOUT_B0_GATE 0x0000A00A +#define REFCLK_BIGCORE0_PVTPLL_GATE 0x0000A00B +#define CLK_BIGCORE0_PVTM_GATE 0x0000A00C +#define CLK_CORE_BIGCORE0_PVTM_GATE 0x0000A00D +#define PCLK_BIGCORE0_ROOT_GATE 0x0000A00E +#define PCLK_BIGCORE0_BIU_GATE 0x0000A00F + +// BIGCORE0CRU_GATE_CON01(Offset:0x804) +#define PCLK_BIGCORE0_PVTM_GATE 0x0000A010 +#define PCLK_BIGCORE0_GRF_GATE 0x0000A011 +#define PCLK_BIGCORE0_CRU_GATE 0x0000A012 +#define PCLK_BIGCORE0_CPUBOOST_GATE 0x0000A013 +#define CLK_24M_BIGCORE0_CPUBOOST_GATE 0x0000A014 + +// BIGCORE0CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_CORE_B01_GPLL_SRC_DIV 0x05010A00 +#define CLK_CORE_B0_UC_DIV 0x05080A00 +#define CLK_CORE_B01_SLOW_SRC_SEL 0x01000A00 +#define CLK_CORE_B01_SLOW_SRC_SEL_XIN_OSC0_FUNC 0U +#define CLK_CORE_B01_SLOW_SRC_SEL_CLK_DEEPSLOW 1U +#define CLK_CORE_B01_SRC_SEL 0x02060A00 +#define CLK_CORE_B01_SRC_SEL_CLK_CORE_B01_SLOW_SRC 0U +#define CLK_CORE_B01_SRC_SEL_CLK_CORE_B01_GPLL_SRC 1U +#define CLK_CORE_B01_SRC_SEL_CLK_B0PLL 2U +#define CLK_CORE_B0_SEL 0x020D0A00 +#define CLK_CORE_B0_SEL_CLK_CORE_B0_UC 0U +#define CLK_CORE_B0_SEL_CLK_CORE_B0_CLEAN 1U +#define CLK_CORE_B0_SEL_CLK_CORE_B01_PVTPLL_T 2U + +// BIGCORE0CRU_CLKSEL_CON01(Offset:0x304) +#define CLK_CORE_B1_UC_DIV 0x05000A01 +#define CLK_TESTOUT_B0_DIV 0x06070A01 +#define CLK_CORE_B1_SEL 0x02050A01 +#define CLK_CORE_B1_SEL_CLK_CORE_B1_UC 0U +#define CLK_CORE_B1_SEL_CLK_CORE_B1_CLEAN 1U +#define CLK_CORE_B1_SEL_CLK_CORE_B01_PVTPLL_T 2U +#define CLK_TESTOUT_B0_SEL 0x010D0A01 +#define CLK_TESTOUT_B0_SEL_CLK_B0PLL 0U +#define CLK_TESTOUT_B0_SEL_CLK_CORE_B01_PVTPLL 1U +#define REFCLK_BIGCORE0_PVTPLL_SEL 0x010E0A01 +#define REFCLK_BIGCORE0_PVTPLL_SEL_CLK_CORE_B01 0U +#define REFCLK_BIGCORE0_PVTPLL_SEL_XIN_OSC0_FUNC 1U + +// BIGCORE0CRU_CLKSEL_CON02(Offset:0x308) +#define PCLK_BIGCORE0_ROOT_SEL 0x02000A02 +#define PCLK_BIGCORE0_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_BIGCORE0_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_BIGCORE0_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_CORE_B01_PVTPLL_T_SEL 0x01020A02 +#define CLK_CORE_B01_PVTPLL_T_SEL_CLK_DEEPSLOW 0U +#define CLK_CORE_B01_PVTPLL_T_SEL_CLK_CORE_B01_PVTPLL 1U + +// ==================== BIGCORE1CRU module definition bank=11 ===================== +// BIGCORE1CRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_NCPUPORESET_B2 0x0000B004 +#define SRST_NCORERESET_B2 0x0000B005 +#define SRST_NCPUPORESET_B3 0x0000B008 +#define SRST_NCORERESET_B3 0x0000B009 +#define SRST_RESETN_BIGCORE1_PVTPLL 0x0000B00B +#define SRST_RESETN_BIGCORE1_PVTM 0x0000B00C +#define SRST_PRESETN_BIGCORE1_BIU 0x0000B00F + +// BIGCORE1CRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_PRESETN_BIGCORE1_PVTM 0x0000B010 +#define SRST_PRESETN_BIGCORE1_GRF 0x0000B011 +#define SRST_PRESETN_BIGCORE1_CRU 0x0000B012 +#define SRST_PRESETN_BIGCORE1_CPUBOOST 0x0000B013 +#define SRST_RESETN_24M_BIGCORE1_CPUBOOST 0x0000B014 + +// BIGCORE1CRU_GATE_CON00(Offset:0x800) +#define CLK_CORE_B23_I_GATE 0x0000B001 +#define CLK_CORE_B2_CLEAN_GATE 0x0000B002 +#define CLK_CORE_B2_UC_GATE 0x0000B003 +#define CLK_CORE_B3_CLEAN_GATE 0x0000B006 +#define CLK_CORE_B3_UC_GATE 0x0000B007 +#define CLK_TESTOUT_B1_GATE 0x0000B00A +#define REFCLK_BIGCORE1_PVTPLL_GATE 0x0000B00B +#define CLK_BIGCORE1_PVTM_GATE 0x0000B00C +#define CLK_CORE_BIGCORE1_PVTM_GATE 0x0000B00D +#define PCLK_BIGCORE1_ROOT_GATE 0x0000B00E +#define PCLK_BIGCORE1_BIU_GATE 0x0000B00F + +// BIGCORE1CRU_GATE_CON01(Offset:0x804) +#define PCLK_BIGCORE1_PVTM_GATE 0x0000B010 +#define PCLK_BIGCORE1_GRF_GATE 0x0000B011 +#define PCLK_BIGCORE1_CRU_GATE 0x0000B012 +#define PCLK_BIGCORE1_CPUBOOST_GATE 0x0000B013 +#define CLK_24M_BIGCORE1_CPUBOOST_GATE 0x0000B014 + +// BIGCORE1CRU_CLKSEL_CON00(Offset:0x300) +#define CLK_CORE_B23_GPLL_SRC_DIV 0x05010B00 +#define CLK_CORE_B2_UC_DIV 0x05080B00 +#define CLK_CORE_B23_SLOW_SRC_SEL 0x01000B00 +#define CLK_CORE_B23_SLOW_SRC_SEL_XIN_OSC0_FUNC 0U +#define CLK_CORE_B23_SLOW_SRC_SEL_CLK_DEEPSLOW 1U +#define CLK_CORE_B23_SRC_SEL 0x02060B00 +#define CLK_CORE_B23_SRC_SEL_CLK_CORE_B23_SLOW_SRC 0U +#define CLK_CORE_B23_SRC_SEL_CLK_CORE_B23_GPLL_SRC 1U +#define CLK_CORE_B23_SRC_SEL_CLK_B1PLL 2U +#define CLK_CORE_B2_SEL 0x020D0B00 +#define CLK_CORE_B2_SEL_CLK_CORE_B2_UC 0U +#define CLK_CORE_B2_SEL_CLK_CORE_B2_CLEAN 1U +#define CLK_CORE_B2_SEL_CLK_CORE_B23_PVTPLL_T 2U + +// BIGCORE1CRU_CLKSEL_CON01(Offset:0x304) +#define CLK_CORE_B3_UC_DIV 0x05000B01 +#define CLK_TESTOUT_B1_DIV 0x06070B01 +#define CLK_CORE_B3_SEL 0x02050B01 +#define CLK_CORE_B3_SEL_CLK_CORE_B3_UC 0U +#define CLK_CORE_B3_SEL_CLK_CORE_B3_CLEAN 1U +#define CLK_CORE_B3_SEL_CLK_CORE_B23_PVTPLL_T 2U +#define CLK_TESTOUT_B1_SEL 0x010D0B01 +#define CLK_TESTOUT_B1_SEL_CLK_B1PLL 0U +#define CLK_TESTOUT_B1_SEL_CLK_CORE_B23_PVTPLL 1U +#define REFCLK_BIGCORE1_PVTPLL_SEL 0x010E0B01 +#define REFCLK_BIGCORE1_PVTPLL_SEL_CLK_CORE_B23 0U +#define REFCLK_BIGCORE1_PVTPLL_SEL_XIN_OSC0_FUNC 1U + +// BIGCORE1CRU_CLKSEL_CON02(Offset:0x308) +#define PCLK_BIGCORE1_ROOT_SEL 0x02000B02 +#define PCLK_BIGCORE1_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_BIGCORE1_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_BIGCORE1_ROOT_SEL_XIN_OSC0_FUNC 2U +#define CLK_CORE_B23PVTPLL_T_SEL 0x01020B02 +#define CLK_CORE_B23PVTPLL_T_SEL_CLK_DEEPSLOW 0U +#define CLK_CORE_B23PVTPLL_T_SEL_CLK_CORE_B23PVTPLL 1U + +// ======================= DSUCRU module definition bank=12 ======================= +// DSUCRU_SOFTRST_CON00(Offset:0xA00) +#define SRST_NSPORESET_DSU 0x0000C006 +#define SRST_NSRESET_DSU 0x0000C007 +#define SRST_ARESETN_M_DSU_BIU 0x0000C00A +#define SRST_ARESETN_S_DSU_BIU 0x0000C00B +#define SRST_NPERIPHRESET_DSU 0x0000C00D + +// DSUCRU_SOFTRST_CON01(Offset:0xA04) +#define SRST_NATRESET_DSU 0x0000C010 +#define SRST_ARESETN_ADB_DSU 0x0000C012 +#define SRST_PRESETN_DSU_BIU 0x0000C015 +#define SRST_NPRESET_DSU 0x0000C016 +#define SRST_PRESETN_DBG 0x0000C017 +#define SRST_PRESETN_S_DAPLITE 0x0000C018 +#define SRST_PRESETN_M_DAPLITE 0x0000C019 +#define SRST_PRESETN_M_DAPLITE_BIU 0x0000C01A +#define SRST_PRESETN_DSU_GRF 0x0000C01B +#define SRST_PORESETN_JTAG 0x0000C01C +#define SRST_NTRESET_JTAG 0x0000C01D +#define SRST_RESETN_LITCORE_PVTPLL 0x0000C01E +#define SRST_RESETN_DSU_PVTPLL 0x0000C01F + +// DSUCRU_SOFTRST_CON02(Offset:0xA08) +#define SRST_RESETN_LITCORE_PVTM 0x0000C020 +#define SRST_PRESETN_DSU_S_BIU 0x0000C023 +#define SRST_PRESETN_DSU_SGRF 0x0000C024 +#define SRST_PRESETN_LITCORE_PVTM 0x0000C026 +#define SRST_PRESETN_LITCORE_GRF 0x0000C027 +#define SRST_PRESETN_DSU_CRU 0x0000C028 +#define SRST_PRESETN_LITCORE_CPUBOOST 0x0000C029 +#define SRST_RESETN_24M_LITCORE_CPUBOOST 0x0000C02A + +// DSUCRU_SOFTRST_CON03(Offset:0xA0C) +#define SRST_NCPUPORESET_L0 0x0000C032 +#define SRST_NCORERESET_L0 0x0000C033 +#define SRST_NCPUPORESET_L1 0x0000C035 +#define SRST_NCORERESET_L1 0x0000C036 +#define SRST_NCPUPORESET_L2 0x0000C038 +#define SRST_NCORERESET_L2 0x0000C039 +#define SRST_NCPUPORESET_L3 0x0000C03B +#define SRST_NCORERESET_L3 0x0000C03C +#define SRST_ARESETN_MP_DSU_BIU 0x0000C03D +#define SRST_NGICRESET_DSU 0x0000C03E + +// DSUCRU_GATE_CON00(Offset:0x800) +#define SCLK_DSU_DF_SRC_GATE 0x0000C000 +#define SCLK_DSU_DF_DIV2_SRC_GATE 0x0000C001 +#define SCLK_DSU_NP5_SRC_GATE 0x0000C002 +#define SCLK_DSU_NP5_DIV2_SRC_GATE 0x0000C003 +#define SCLK_DSU_SRC_GATE 0x0000C004 +#define SCLK_DSU_SRC_T_GATE 0x0000C005 +#define SCLK_DSU_GATE 0x0000C006 +#define ACLKM_DSU_GATE 0x0000C008 +#define ACLKS_DSU_GATE 0x0000C009 +#define ACLK_M_DSU_BIU_GATE 0x0000C00A +#define ACLK_S_DSU_BIU_GATE 0x0000C00B +#define ACLK_MP_DSU_GATE 0x0000C00C +#define PERIPHCLK_DSU_GATE 0x0000C00D +#define CNTCLK_DSU_GATE 0x0000C00E +#define TSCLK_DSU_GATE 0x0000C00F + +// DSUCRU_GATE_CON01(Offset:0x804) +#define ATCLK_DSU_GATE 0x0000C010 +#define GICCLK_DSU_T_GATE 0x0000C011 +#define ACLK_ADB_DSU_GATE 0x0000C012 +#define PCLK_DSU_ROOT_GATE 0x0000C013 +#define PCLK_DSU_NS_ROOT_GATE 0x0000C014 +#define PCLK_DSU_BIU_GATE 0x0000C015 +#define PCLK_DSU_GATE 0x0000C016 +#define PCLK_DBG_GATE 0x0000C017 +#define PCLK_S_DAPLITE_GATE 0x0000C018 +#define PCLK_M_DAPLITE_GATE 0x0000C019 +#define PCLK_M_DAPLITE_BIU_GATE 0x0000C01A +#define PCLK_DSU_GRF_GATE 0x0000C01B +#define REFCLK_LITCORE_PVTPLL_GATE 0x0000C01E +#define REFCLK_DSU_PVTPLL_GATE 0x0000C01F + +// DSUCRU_GATE_CON02(Offset:0x808) +#define CLK_LITCORE_PVTM_GATE 0x0000C020 +#define CLK_CORE_LITCORE_PVTM_GATE 0x0000C021 +#define PCLK_DSU_S_ROOT_GATE 0x0000C022 +#define PCLK_DSU_S_BIU_GATE 0x0000C023 +#define PCLK_DSU_SGRF_GATE 0x0000C024 +#define CLK_TESTOUT_L_GATE 0x0000C025 +#define PCLK_LITCORE_PVTM_GATE 0x0000C026 +#define PCLK_LITCORE_GRF_GATE 0x0000C027 +#define PCLK_DSU_CRU_GATE 0x0000C028 +#define PCLK_LITCORE_CPUBOOST_GATE 0x0000C029 +#define CLK_24M_LITCORE_CPUBOOST_GATE 0x0000C02A +#define CLK_CORE_L0_CLEAN_GATE 0x0000C02B +#define CLK_CORE_L1_CLEAN_GATE 0x0000C02C +#define CLK_CORE_L2_CLEAN_GATE 0x0000C02D +#define CLK_CORE_L3_CLEAN_GATE 0x0000C02E +#define CLK_CORE_L_DIV2_SRC_GATE 0x0000C02F + +// DSUCRU_GATE_CON03(Offset:0x80C) +#define CLK_CORE_L_GATE 0x0000C030 +#define CLK_CORE_L0_UC_GATE 0x0000C031 +#define CLK_CORE_L1_UC_GATE 0x0000C034 +#define CLK_CORE_L2_UC_GATE 0x0000C037 +#define CLK_CORE_L3_UC_GATE 0x0000C03A +#define ACLK_MP_DSU_BIU_GATE 0x0000C03D +#define GICCLK_DSU_GATE 0x0000C03E + +// DSUCRU_CLKSEL_CON00(Offset:0x300) +#define SCLK_DSU_DF_SRC_DIV 0x05070C00 +#define SCLK_DSU_DF_SRC_SEL 0x020C0C00 +#define SCLK_DSU_DF_SRC_SEL_CLK_B0PLL_MUX 0U +#define SCLK_DSU_DF_SRC_SEL_CLK_B1PLL_MUX 1U +#define SCLK_DSU_DF_SRC_SEL_CLK_LPLL_MUX 2U +#define SCLK_DSU_DF_SRC_SEL_CLK_GPLL_MUX 3U + +// DSUCRU_CLKSEL_CON01(Offset:0x304) +#define ACLKM_DSU_DIV 0x05010C01 +#define ACLKS_DSU_DIV 0x05060C01 +#define ACLK_MP_DSU_DIV 0x050B0C01 +#define SCLK_DSU_SRC_T_SEL 0x01000C01 +#define SCLK_DSU_SRC_T_SEL_SCLK_DSU_SRC 0U +#define SCLK_DSU_SRC_T_SEL_CLK_DSU_PVTPLL_T 1U + +// DSUCRU_CLKSEL_CON02(Offset:0x308) +#define PERIPHCLK_DSU_DIV 0x05000C02 +#define CNTCLK_DSU_DIV 0x05050C02 +#define TSCLK_DSU_DIV 0x050A0C02 + +// DSUCRU_CLKSEL_CON03(Offset:0x30C) +#define ATCLK_DSU_DIV 0x05000C03 +#define GICCLK_DSU_T_DIV 0x05050C03 + +// DSUCRU_CLKSEL_CON04(Offset:0x310) +#define PCLK_DSU_ROOT_DIV 0x05000C04 +#define PCLK_DSU_ROOT_SEL 0x02050C04 +#define PCLK_DSU_ROOT_SEL_CLK_B0PLL_MUX 0U +#define PCLK_DSU_ROOT_SEL_CLK_B1PLL_MUX 1U +#define PCLK_DSU_ROOT_SEL_CLK_LPLL_MUX 2U +#define PCLK_DSU_ROOT_SEL_CLK_GPLL_MUX 3U +#define PCLK_DSU_NS_ROOT_SEL 0x02070C04 +#define PCLK_DSU_NS_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_DSU_NS_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_DSU_NS_ROOT_SEL_XIN_OSC0_FUNC 2U +#define REFCLK_LITCORE_PVTPLL_SEL 0x01090C04 +#define REFCLK_LITCORE_PVTPLL_SEL_CLK_CORE_L 0U +#define REFCLK_LITCORE_PVTPLL_SEL_XIN_OSC0_FUNC 1U +#define REFCLK_DSU_PVTPLL_SEL 0x010A0C04 +#define REFCLK_DSU_PVTPLL_SEL_SCLK_DSU_SRC 0U +#define REFCLK_DSU_PVTPLL_SEL_XIN_OSC0_FUNC 1U +#define PCLK_DSU_S_ROOT_SEL 0x020B0C04 +#define PCLK_DSU_S_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define PCLK_DSU_S_ROOT_SEL_CLK_MATRIX_50M_SRC 1U +#define PCLK_DSU_S_ROOT_SEL_XIN_OSC0_FUNC 2U + +// DSUCRU_CLKSEL_CON05(Offset:0x314) +#define CLK_TESTOUT_L_DIV 0x06000C05 +#define CLK_CORE_L_GPLL_SRC_DIV 0x05090C05 +#define CLK_TESTOUT_L_SEL 0x02060C05 +#define CLK_TESTOUT_L_SEL_CLK_LPLL 0U +#define CLK_TESTOUT_L_SEL_CLK_CORE_L_PVTPLL 1U +#define CLK_TESTOUT_L_SEL_SCLK_DSU_SRC 2U +#define CLK_TESTOUT_L_SEL_CLK_DSU_PVTPLL 3U +#define CLK_CORE_L_SLOW_SRC_SEL 0x01080C05 +#define CLK_CORE_L_SLOW_SRC_SEL_XIN_OSC0_FUNC 0U +#define CLK_CORE_L_SLOW_SRC_SEL_CLK_DEEPSLOW 1U +#define CLK_CORE_L_SRC_SEL 0x020E0C05 +#define CLK_CORE_L_SRC_SEL_CLK_CORE_L_SLOW_SRC 0U +#define CLK_CORE_L_SRC_SEL_CLK_CORE_L_GPLL_SRC 1U +#define CLK_CORE_L_SRC_SEL_CLK_LPLL 2U + +// DSUCRU_CLKSEL_CON06(Offset:0x318) +#define CLK_CORE_L0_UC_DIV 0x05000C06 +#define CLK_CORE_L1_UC_DIV 0x05070C06 +#define CLK_CORE_L0_SEL 0x02050C06 +#define CLK_CORE_L0_SEL_CLK_CORE_L0_UC 0U +#define CLK_CORE_L0_SEL_CLK_CORE_L0_CLEAN 1U +#define CLK_CORE_L0_SEL_CLK_CORE_L_PVTPLL_T 2U +#define CLK_CORE_L1_SEL 0x020C0C06 +#define CLK_CORE_L1_SEL_CLK_CORE_L1_UC 0U +#define CLK_CORE_L1_SEL_CLK_CORE_L1_CLEAN 1U +#define CLK_CORE_L1_SEL_CLK_CORE_L_PVTPLL_T 2U + +// DSUCRU_CLKSEL_CON07(Offset:0x31C) +#define CLK_CORE_L2_UC_DIV 0x05000C07 +#define CLK_CORE_L3_UC_DIV 0x05070C07 +#define CLK_CORE_L2_SEL 0x02050C07 +#define CLK_CORE_L2_SEL_CLK_CORE_L2_UC 0U +#define CLK_CORE_L2_SEL_CLK_CORE_L2_CLEAN 1U +#define CLK_CORE_L2_SEL_CLK_CORE_L_PVTPLL_T 2U +#define CLK_CORE_L3_SEL 0x020C0C07 +#define CLK_CORE_L3_SEL_CLK_CORE_L3_UC 0U +#define CLK_CORE_L3_SEL_CLK_CORE_L3_CLEAN 1U +#define CLK_CORE_L3_SEL_CLK_CORE_L_PVTPLL_T 2U +#define CLK_CORE_L_PVTPLL_T_SEL 0x010E0C07 +#define CLK_CORE_L_PVTPLL_T_SEL_CLK_DEEPSLOW 0U +#define CLK_CORE_L_PVTPLL_T_SEL_CLK_CORE_L_PVTPLL 1U +#define CLK_DSU_PVTPLL_T_SEL 0x010F0C07 +#define CLK_DSU_PVTPLL_T_SEL_CLK_DEEPSLOW 0U +#define CLK_DSU_PVTPLL_T_SEL_CLK_DSU_PVTPLL 1U + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __RK3588_H */ diff --git a/demos/rk3588/bsp/hal/soc.h b/demos/rk3588/bsp/hal/soc.h new file mode 100755 index 00000000..ffa71d12 --- /dev/null +++ b/demos/rk3588/bsp/hal/soc.h @@ -0,0 +1,732 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __SOC_H +#define __SOC_H +#ifdef __cplusplus + extern "C" { +#endif + +#include "hal_conf.h" + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< brief Defines 'write only' permissions */ +#define __IO volatile /*!< brief Defines 'read / write' permissions */ + +/* ================================================================================ */ +/* ================ DMA REQ =============== */ +/* ================================================================================ */ +typedef enum { + DMA_REQ_I2S0_8CH_TX = 0, + DMA_REQ_I2S2_2CH_TX = 0, + DMA_REQ_I2S4_8CH_TX = 0, + DMA_REQ_I2S0_8CH_RX = 1, + DMA_REQ_I2S2_2CH_RX = 1, + DMA_REQ_I2S1_8CH_TX = 2, + DMA_REQ_I2S3_2CH_TX = 2, + DMA_REQ_I2S5_8CH_TX = 2, + DMA_REQ_I2S1_8CH_RX = 3, + DMA_REQ_I2S3_2CH_RX = 3, + DMA_REQ_PDM0 = 4, + DMA_REQ_PDM1 = 4, + DMA_REQ_I2S6_8CH_TX = 4, + DMA_REQ_SPDIF0_TX = 5, + DMA_REQ_SPDIF1_TX = 5, + DMA_REQ_UART0_TX = 6, + DMA_REQ_SPDIF2_TX = 6, + DMA_REQ_UART0_RX = 7, + DMA_REQ_SPDIF3_TX = 7, + DMA_REQ_UART7_TX = 7, + DMA_REQ_UART1_TX = 8, + DMA_REQ_SPDIF4_TX = 8, + DMA_REQ_UART7_RX = 8, + DMA_REQ_UART1_RX = 9, + DMA_REQ_UART4_TX = 9, + DMA_REQ_UART8_TX = 9, + DMA_REQ_UART2_TX = 10, + DMA_REQ_UART4_RX = 10, + DMA_REQ_UART8_RX = 10, + DMA_REQ_UART2_RX = 11, + DMA_REQ_UART5_TX = 11, + DMA_REQ_UART9_TX = 11, + DMA_REQ_UART3_TX = 12, + DMA_REQ_UART5_RX = 12, + DMA_REQ_UART9_RX = 12, + DMA_REQ_UART3_RX = 13, + DMA_REQ_UART6_TX = 13, + DMA_REQ_SPI4_TX = 13, + DMA_REQ_SPI0_TX = 14, + DMA_REQ_UART6_RX = 14, + DMA_REQ_SPI4_RX = 14, + DMA_REQ_SPI0_RX = 15, + DMA_REQ_SPI2_TX = 15, + DMA_REQ_PWM2 = 15, + DMA_REQ_SPI1_TX = 16, + DMA_REQ_SPI2_RX = 16, + DMA_REQ_PWM3 = 16, + DMA_REQ_SPI1_RX = 17, + DMA_REQ_SPI3_TX = 17, + DMA_REQ_CAN2_TX = 17, + DMA_REQ_PWM0 = 18, + DMA_REQ_SPI3_RX = 18, + DMA_REQ_CAN2_RX = 18, + DMA_REQ_CAN0_TX = 19, + DMA_REQ_PWM1 = 19, + DMA_REQ_SDMMC = 19, + DMA_REQ_CAN0_RX = 20, + DMA_REQ_CAN1_TX = 20, + DMA_REQ_SPDIF0_RX = 21, + DMA_REQ_CAN1_RX = 21, + DMA_REQ_I2S7_8CH_RX = 21, + DMA_REQ_SPDIF1_RX = 22, + DMA_REQ_SPDIF5_TX = 22, + DMA_REQ_I2S8_8CH_TX = 22, + DMA_REQ_SPDIF2_RX = 23, + DMA_REQ_I29_8CH_RX = 23, + DMA_REQ_I210_8CH_RX = 24, +} DMA_REQ_Type; + +/* ================================================================================ */ +/* ================ IRQ ================ */ +/* ================================================================================ */ +#define NUM_INT_PER_CON 256 +#define NUM_INT_PER_GROUP 64 +#define NUM_EXT_INTERRUPTS 512 + +#if defined(HAL_MCU_CORE) +#if defined(RKMCU_RK3588_PMU) +typedef enum { +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** Platform Exceptions Numbers ***************************************************/ + PMIC_IRQn = 0, /*!< PMIC Interrupt */ + SDMMC_DETECTN_IRQn = 1, /*!< SDMMC Interrupt */ + UART0_IRQn = 2, /*!< UART0 Interrupt */ + GPIO0_IRQn = 3, /*!< GPIO0 Interrupt */ + GPIO0_EXP_IRQn = 4, /*!< GPIO0 EXP Interrupt */ + I2C0_IRQn = 5, /*!< I2C0 Interrupt */ + VAD_IRQn = 6, /*!< VAD Interrupt */ + PDM0_IRQn = 7, /*!< PDM0 Interrupt */ + I2S1_IRQn = 8, /*!< I2S1 Interrupt */ + PVTM_IRQn = 9, /*!< PVTM Interrupt */ + PWM0_PWR_IRQn = 10, /*!< PWM0 PWR Interrupt */ + PWM0_IRQn = 11, /*!< PWM0 Interrupt */ + WDT0_IRQn = 12, /*!< WDT Interrupt */ + TIMER0_IRQn = 14, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 13, /*!< TIMER1 Interrupt */ + CRC_CHK_RST_IRQn = 15, /*!< CRC_CHK_RST Interrupt */ + INTMUX_OUT_START_IRQn = 16, /*!< INTMUX_OUT_START Interrupt */ + INTMUX_OUT_END_IRQn = 23, /*!< INTMUX_OUT_END Interrupt */ + HPTIMER_PMU0_IRQn = 24, /*!< HPTIMER_PMU0 Interrupt */ + OSC_CHK_RST_IRQn = 25, /*!< OSC_CHK_RST Interrupt */ + CACHE_IRQn = 26, /*!< CACHE Interrupt */ + NUM_INTERRUPTS = 27, /*!< Number of internal IRQ */ + MBOX0_CH0_AP_IRQn = 93 + NUM_INTERRUPTS, /*!< MAILBOX_CH0_AP Interrupt */ + MBOX0_CH1_AP_IRQn = 94 + NUM_INTERRUPTS, /*!< MAILBOX_CH1_AP Interrupt */ + MBOX0_CH2_AP_IRQn = 95 + NUM_INTERRUPTS, /*!< MAILBOX_CH2_AP Interrupt */ + MBOX0_CH3_AP_IRQn = 96 + NUM_INTERRUPTS, /*!< MAILBOX_CH3_AP Interrupt */ + MBOX0_CH0_BB_IRQn = 97 + NUM_INTERRUPTS, /*!< MAILBOX_CH0_BB Interrupt */ + MBOX0_CH1_BB_IRQn = 98 + NUM_INTERRUPTS, /*!< MAILBOX_CH1_BB Interrupt */ + MBOX0_CH2_BB_IRQn = 99 + NUM_INTERRUPTS, /*!< MAILBOX_CH2_BB Interrupt */ + MBOX0_CH3_BB_IRQn = 100 + NUM_INTERRUPTS, /*!< MAILBOX_CH3_BB Interrupt */ + GPIO1_IRQn = 310 + NUM_INTERRUPTS, /*!< GPIO1 Interrupt */ + GPIO2_IRQn = 311 + NUM_INTERRUPTS, /*!< GPIO2 Interrupt */ + GPIO3_IRQn = 312 + NUM_INTERRUPTS, /*!< GPIO3 Interrupt */ + GPIO4_IRQn = 313 + NUM_INTERRUPTS, /*!< GPIO4 Interrupt */ + TOTAL_INTERRUPTS = (NUM_INTERRUPTS + NUM_EXT_INTERRUPTS), /*!< For external interrupt from intmux */ +} IRQn_Type; +#elif defined(RKMCU_RK3588_NPU) +typedef enum { +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** Platform Exceptions Numbers ***************************************************/ + TIMER0_IRQn = 0, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 1, /*!< TIMER1 Interrupt */ + PVTM_IRQn = 2, /*!< PVTM Interrupt */ + WDT0_IRQn = 3, /*!< WDT Interrupt */ + C0_RKNN_IRQn = 4, /*!< C0_RKNN Interrupt */ + C1_RKNN_IRQn = 5, /*!< C1_RKNN Interrupt */ + C2_RKNN_IRQn = 6, /*!< C2_RKNN Interrupt */ + CACHE_IRQn = 7, /*!< CACHE Interrupt */ + MBOX0_CH0_AP_IRQn = 8, /*!< MAILBOX_CH0_AP Interrupt */ + MBOX0_CH1_AP_IRQn = 9, /*!< MAILBOX_CH1_AP Interrupt */ + MBOX0_CH2_AP_IRQn = 10, /*!< MAILBOX_CH2_AP Interrupt */ + MBOX0_CH3_AP_IRQn = 11, /*!< MAILBOX_CH3_AP Interrupt */ + MBOX0_CH0_BB_IRQn = 12, /*!< MAILBOX_CH0_BB Interrupt */ + MBOX0_CH1_BB_IRQn = 13, /*!< MAILBOX_CH1_BB Interrupt */ + MBOX0_CH2_BB_IRQn = 14, /*!< MAILBOX_CH2_BB Interrupt */ + MBOX0_CH3_BB_IRQn = 15, /*!< MAILBOX_CH3_BB Interrupt */ + NUM_INTERRUPTS = 16, /*!< Number of internal IRQ */ + DUMMY_IRQn = 256, /*!< Avoid compile warning: overflow in conversion */ +} IRQn_Type; +#elif defined(RKMCU_RK3588_DDR) +typedef enum +{ +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/****** Platform Exceptions Numbers ***************************************************/ + INTMUX_OUT_START_IRQn = 0, /*!< INTMUX_OUT_START Interrupt */ + INTMUX_OUT_END_IRQn = 7, /*!< INTMUX_OUT_END Interrupt */ + NUM_INTERRUPTS = 27, /*!< Number of internal IRQ */ + MBOX0_CH0_AP_IRQn = 101 + NUM_INTERRUPTS, /*!< MAILBOX_CH0_AP Interrupt */ + MBOX0_CH1_AP_IRQn = 102 + NUM_INTERRUPTS, /*!< MAILBOX_CH1_AP Interrupt */ + MBOX0_CH2_AP_IRQn = 103 + NUM_INTERRUPTS, /*!< MAILBOX_CH2_AP Interrupt */ + MBOX0_CH3_AP_IRQn = 104 + NUM_INTERRUPTS, /*!< MAILBOX_CH3_AP Interrupt */ + MBOX0_CH0_BB_IRQn = 105 + NUM_INTERRUPTS, /*!< MAILBOX_CH0_BB Interrupt */ + MBOX0_CH1_BB_IRQn = 106 + NUM_INTERRUPTS, /*!< MAILBOX_CH1_BB Interrupt */ + MBOX0_CH2_BB_IRQn = 107 + NUM_INTERRUPTS, /*!< MAILBOX_CH2_BB Interrupt */ + MBOX0_CH3_BB_IRQn = 108 + NUM_INTERRUPTS, /*!< MAILBOX_CH3_BB Interrupt */ + WDT0_IRQn = 433 + NUM_INTERRUPTS, /*!< WDT Interrupt */ + TIMER0_IRQn = 434 + NUM_INTERRUPTS, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 435 + NUM_INTERRUPTS, /*!< TIMER1 Interrupt */ + TOTAL_INTERRUPTS = (NUM_INTERRUPTS + NUM_EXT_INTERRUPTS), /*!< For external interrupt from intmux */ +} IRQn_Type; +#else +#error missing IRQn_Type define for interrupt +#endif + +#if defined(RKMCU_RK3588_PMU) || defined(RKMCU_RK3588_DDR) +#define HAS_CUSTOME_INTC +#endif +#endif /* HAL_MCU_CORE */ + +#if defined(HAL_AP_CORE) +typedef enum +{ +/* When IPI_SGIs are used in AMP mode, you need to pay attention to whether it conflicts + * with SMP mode. Especially in the case of Linux OS as The Master Core. + * IPI_SGI 0~7 for non-secure and IPI_SGI 8~15 for secure. + */ + IPI_SGI0 = 0, + IPI_SGI1 = 1, + IPI_SGI2 = 2, + IPI_SGI3 = 3, + IPI_SGI4 = 4, + IPI_SGI5 = 5, + IPI_SGI6 = 6, + IPI_SGI7 = 7, + IPI_SGI8 = 8, + IPI_SGI9 = 9, + IPI_SGI10 = 10, + IPI_SGI11 = 11, + IPI_SGI12 = 12, + IPI_SGI13 = 13, + IPI_SGI14 = 14, + IPI_SGI15 = 15, + + CNTHP_IRQn = 26, + CNTV_IRQn = 27, + CNTPS_IRQn = 29, + CNTPNS_IRQn = 30, + +/****** Platform Exceptions Numbers ***************************************************/ + MBOX0_CH0_B2A_IRQn = 93, /*!< MBOX0 CH0 B2A Interrupt */ + MBOX0_CH1_B2A_IRQn = 94, /*!< MBOX0 CH1 B2A Interrupt */ + MBOX0_CH2_B2A_IRQn = 95, /*!< MBOX0 CH2 B2A Interrupt */ + MBOX0_CH3_B2A_IRQn = 96, /*!< MBOX0 CH3 B2A Interrupt */ + MBOX0_CH0_A2B_IRQn = 97, /*!< MBOX0 CH0 A2B Interrupt */ + MBOX0_CH1_A2B_IRQn = 98, /*!< MBOX0 CH1 A2B Interrupt */ + MBOX0_CH2_A2B_IRQn = 99, /*!< MBOX0 CH2 A2B Interrupt */ + MBOX0_CH3_A2B_IRQn = 100, /*!< MBOX0 CH3 A2B Interrupt */ + MBOX1_CH0_B2A_IRQn = 101, /*!< MBOX1 CH0 B2A Interrupt */ + MBOX1_CH1_B2A_IRQn = 102, /*!< MBOX1 CH1 B2A Interrupt */ + MBOX1_CH2_B2A_IRQn = 103, /*!< MBOX1 CH2 B2A Interrupt */ + MBOX1_CH3_B2A_IRQn = 104, /*!< MBOX1 CH3 B2A Interrupt */ + MBOX1_CH0_A2B_IRQn = 105, /*!< MBOX1 CH0 A2B Interrupt */ + MBOX1_CH1_A2B_IRQn = 106, /*!< MBOX1 CH1 A2B Interrupt */ + MBOX1_CH2_A2B_IRQn = 107, /*!< MBOX1 CH2 A2B Interrupt */ + MBOX1_CH3_A2B_IRQn = 108, /*!< MBOX1 CH3 A2B Interrupt */ + MBOX2_CH0_B2A_IRQn = 109, /*!< MBOX2 CH0 B2A Interrupt */ + MBOX2_CH1_B2A_IRQn = 110, /*!< MBOX2 CH1 B2A Interrupt */ + MBOX2_CH2_B2A_IRQn = 111, /*!< MBOX2 CH2 B2A Interrupt */ + MBOX2_CH3_B2A_IRQn = 112, /*!< MBOX2 CH3 B2A Interrupt */ + MBOX2_CH0_A2B_IRQn = 113, /*!< MBOX2 CH0 A2B Interrupt */ + MBOX2_CH1_A2B_IRQn = 114, /*!< MBOX2 CH1 A2B Interrupt */ + MBOX2_CH2_A2B_IRQn = 115, /*!< MBOX2 CH2 A2B Interrupt */ + MBOX2_CH3_A2B_IRQn = 116, /*!< MBOX2 CH3 A2B Interrupt */ + GPIO0_IRQn = 309, /*!< GPIO0 Interrupt */ + GPIO1_IRQn = 310, /*!< GPIO1 Interrupt */ + GPIO2_IRQn = 311, /*!< GPIO2 Interrupt */ + GPIO3_IRQn = 312, /*!< GPIO3 Interrupt */ + GPIO4_IRQn = 313, /*!< GPIO4 Interrupt */ + GPIO0_EXP_IRQn = 314, /*!< GPIO0 EXP Interrupt */ + GPIO1_EXP_IRQn = 315, /*!< GPIO1 EXP Interrupt */ + GPIO2_EXP_IRQn = 316, /*!< GPIO2 EXP Interrupt */ + GPIO3_EXP_IRQn = 317, /*!< GPIO3 EXP Interrupt */ + GPIO4_EXP_IRQn = 318, /*!< GPIO4 EXP Interrupt */ + TIMER0_IRQn = 321, /*!< TIMER0 Interrupt */ + TIMER1_IRQn = 322, /*!< TIMER1 Interrupt */ + TIMER2_IRQn = 323, /*!< TIMER2 Interrupt */ + TIMER3_IRQn = 324, /*!< TIMER3 Interrupt */ + TIMER4_IRQn = 325, /*!< TIMER4 Interrupt */ + TIMER5_IRQn = 326, /*!< TIMER5 Interrupt */ + TIMER6_IRQn = 327, /*!< TIMER6 Interrupt */ + TIMER7_IRQn = 328, /*!< TIMER7 Interrupt */ + TIMER8_IRQn = 329, /*!< TIMER8 Interrupt */ + TIMER9_IRQn = 330, /*!< TIMER9 Interrupt */ + TIMER10_IRQn = 331, /*!< TIMER10 Interrupt */ + TIMER11_IRQn = 332, /*!< TIMER11 Interrupt */ + UART0_IRQn = 363, /*!< UART0 Interrupt */ + UART1_IRQn = 364, /*!< UART1 Interrupt */ + UART2_IRQn = 365, /*!< UART2 Interrupt */ + UART3_IRQn = 366, /*!< UART3 Interrupt */ + UART4_IRQn = 367, /*!< UART4 Interrupt */ + UART5_IRQn = 368, /*!< UART5 Interrupt */ + UART6_IRQn = 369, /*!< UART6 Interrupt */ + UART7_IRQn = 370, /*!< UART7 Interrupt */ + UART8_IRQn = 371, /*!< UART8 Interrupt */ + UART9_IRQn = 372, /*!< UART9 Interrupt */ + RSVD0_IRQn = 454, /*!< RSVD0 Interrupt */ + NUM_INTERRUPTS = 512, +} IRQn_Type; + +#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N)) + +#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(15 + (cpu)) /* gic irq: 469 */ + +#define GPIO_IRQ_GROUP_DIRQ_BASE 480 +#define GPIO_IRQ_GROUP_DIRQ_NUM 32 + +#define GPIO_IRQ_GROUP_GPIO0_HWIRQ GPIO0_IRQn +#define GPIO_IRQ_GROUP_GPION_HWIRQ GPIO4_IRQn + +#endif /* HAL_AP_CORE */ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000) + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#if defined(HAL_AP_CORE) && defined(HAL_MCU_CORE) +#error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled" +#endif + +#if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE) +#error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h" +#endif + +#ifdef HAL_AP_CORE +#define __CORTEX_A 55U +#define __CORTEX_A_BIG 76U /* Cortex-A76 Core */ +#define __CORTEX_A_LIT 55U /* Cortex-A55 Core */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __TIM_PRESENT 1U /* Generic Timer */ + +#define CACHE_LINE_SHIFT (6U) +#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) + +#else +#define __CM0_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 0U /* no MPU present */ +#define __VTOR_PRESENT 0U /* no VTOR present */ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ + +#define NVIC_PERIPH_IRQ_OFFSET 16U +#define MAX_INTERRUPT_VECTOR 64U + +#endif + +#ifndef __ASSEMBLY__ +#include "cmsis_compiler.h" +#ifdef __CORTEX_A +#include "core_ca.h" +#else +#include "core_cm0.h" +#endif +// #include "system_rk3588.h" +#endif /* __ASSEMBLY__ */ +#include "rk3588.h" + +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define GIC_DISTRIBUTOR_BASE 0xFE600000 /* GICD base address */ +#define GIC_REDISTRIBUTOR_BASE 0xFE660000 /* GICR base address */ + +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +#if defined(HAL_AP_CORE) +/********************************** CPU Topology ****************************************/ +#define MPIDR_MT_MASK ((1U) << 24) +#define MPIDR_AFFLVL_MASK (0xFFU) +#define MPIDR_AFF0_SHIFT (0U) +#define MPIDR_AFF1_SHIFT (8U) +#define MPIDR_AFF2_SHIFT (16U) +#define MPIDR_AFF3_SHIFT (32U) +#define MPIDR_AFFINITY_MASK (0xFFFFFFU) +#define PLATFORM_CLUSTER0_CORE_COUNT (8) +#define PLATFORM_CORE_COUNT (8) +#define CPU_GET_AFFINITY(cpuId, clusterId) ((cpuId) << MPIDR_AFF1_SHIFT) + +#endif /* HAL_AP_CORE */ + +#if defined(HAL_MCU_CORE) +/**************************************** CACHE ****************************************/ +/* CACHE LINE SIZE */ +#define CACHE_LINE_SHIFT (5U) +#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) +#define CACHE_LINE_ADDR_MASK (0xFFFFFFFFU << CACHE_LINE_SHIFT) +#define CACHE_M_CLEAN 0x0U +#define CACHE_M_INVALID 0x2U +#define CACHE_M_CLEAN_INVALID 0x4U +#define CACHE_M_INVALID_ALL 0x6U +#define CACHE_REVISION (0x00000100U) + +#ifndef HAL_CACHE_DECODED_ADDR_BASE +#error "Please define HAL_CACHE_DECODED_ADDR_BASE on hal_conf.h" +#endif + +#endif /* HAL_MCU_CORE */ + +/******************************************CRU*******************************************/ +#define CRU_CLK_USE_CON_BANK +#define CLK64(mux, div) ((((mux) & 0xffffffffULL) << 32) | ((div) & 0xffffffffULL)) + +#ifndef __ASSEMBLY__ +typedef enum CLOCK_Name { + CLK_INVALID = 0U, + PLL_AUPLL, + PLL_B0PLL, + PLL_B1PLL, + PLL_CPLL, + PLL_GPLL, + PLL_LPLL, + PLL_NPLL, + PLL_PPLL, + PLL_V0PLL, + + /* storage */ + BCLK_EMMC = CLK64(BCLK_EMMC_SEL, BCLK_EMMC_DIV), + CCLK_EMMC = CLK64(CCLK_EMMC_SEL, CCLK_EMMC_DIV), + SCLK_SFC = CLK64(SCLK_SFC_SEL, SCLK_SFC_DIV), + CCLK_SRC_SDIO = CLK64(CCLK_SRC_SDIO_SEL, CCLK_SRC_SDIO_DIV), + CLK_REF_PIPE_PHY0 = CLK64(CLK_REF_PIPE_PHY0_SEL, CLK_REF_PIPE_PHY0_PLL_SRC_DIV), + CLK_REF_PIPE_PHY1 = CLK64(CLK_REF_PIPE_PHY1_SEL, CLK_REF_PIPE_PHY1_PLL_SRC_DIV), + CLK_REF_PIPE_PHY2 = CLK64(CLK_REF_PIPE_PHY2_SEL, CLK_REF_PIPE_PHY2_PLL_SRC_DIV), + + /* audio */ + HCLK_VAD = CLK64(HCLK_PMU1_ROOT_I_SEL, 0U), + MCLK_PDM0 = CLK64(MCLK_PDM0_SEL, 0U), + CLK_I2S0_8CH_TX_SRC = CLK64(CLK_I2S0_8CH_TX_SRC_SEL, CLK_I2S0_8CH_TX_SRC_DIV), + CLK_I2S0_8CH_TX_FRAC = CLK64(0U, CLK_I2S0_8CH_TX_FRAC_DIV), + CLK_I2S0_8CH_TX = CLK64(MCLK_I2S0_8CH_TX_SEL, 0U), + CLK_I2S0_8CH_RX_SRC = CLK64(CLK_I2S0_8CH_RX_SRC_SEL, CLK_I2S0_8CH_RX_SRC_DIV), + CLK_I2S0_8CH_RX_FRAC = CLK64(0U, CLK_I2S0_8CH_RX_FRAC_DIV), + CLK_I2S0_8CH_RX = CLK64(MCLK_I2S0_8CH_RX_SEL, 0U), + CLK_I2S1_8CH_TX_SRC = CLK64(0U, CLK_I2S1_8CH_TX_SRC_DIV), + CLK_I2S1_8CH_TX_FRAC = CLK64(0U, CLK_I2S1_8CH_TX_FRAC_DIV), + CLK_I2S1_8CH_TX = CLK64(MCLK_I2S1_8CH_TX_SEL, 0U), + CLK_I2S1_8CH_RX_SRC = CLK64(0U, CLK_I2S1_8CH_RX_SRC_DIV), + CLK_I2S1_8CH_RX_FRAC = CLK64(0U, CLK_I2S1_8CH_RX_FRAC_DIV), + CLK_I2S1_8CH_RX = CLK64(MCLK_I2S1_8CH_RX_SEL, 0U), + CLK_I2S2_2CH = CLK64(MCLK_I2S2_2CH_SEL, 0U), + CLK_I2S2_2CH_SRC = CLK64(CLK_I2S2_2CH_SRC_SEL, CLK_I2S2_2CH_SRC_DIV), + CLK_I2S2_2CH_FRAC = CLK64(0U, CLK_I2S2_2CH_FRAC_DIV), + CLK_I2S3_2CH = CLK64(MCLK_I2S3_2CH_SEL, 0U), + CLK_I2S3_2CH_SRC = CLK64(CLK_I2S3_2CH_SRC_SEL, CLK_I2S3_2CH_SRC_DIV), + CLK_I2S3_2CH_FRAC = CLK64(0U, CLK_I2S3_2CH_FRAC_DIV), + CLK_I2S4_8CH_TX_SRC = CLK64(0U, CLK_I2S4_8CH_TX_SRC_DIV), + CLK_I2S4_8CH_TX_FRAC = CLK64(0U, CLK_I2S4_8CH_TX_FRAC_DIV), + CLK_I2S4_8CH_TX = CLK64(MCLK_I2S4_8CH_TX_SEL, 0U), + CLK_I2S5_8CH_TX_SRC = CLK64(0U, CLK_I2S5_8CH_TX_SRC_DIV), + CLK_I2S5_8CH_TX_FRAC = CLK64(0U, CLK_I2S5_8CH_TX_FRAC_DIV), + CLK_I2S5_8CH_TX = CLK64(MCLK_I2S5_8CH_TX_SEL, 0U), + CLK_I2S6_8CH_TX_SRC = CLK64(CLK_I2S6_8CH_TX_SRC_SEL, CLK_I2S6_8CH_TX_SRC_DIV), + CLK_I2S6_8CH_TX_FRAC = CLK64(0U, CLK_I2S6_8CH_TX_FRAC_DIV), + CLK_I2S6_8CH_TX = CLK64(MCLK_I2S6_8CH_TX_SEL, 0U), + CLK_I2S6_8CH_RX_SRC = CLK64(CLK_I2S6_8CH_RX_SRC_SEL, CLK_I2S6_8CH_RX_SRC_DIV), + CLK_I2S6_8CH_RX_FRAC = CLK64(0U, CLK_I2S6_8CH_RX_FRAC_DIV), + CLK_I2S6_8CH_RX = CLK64(MCLK_I2S6_8CH_RX_SEL, 0U), + CLK_I2S7_8CH_RX_SRC = CLK64(CLK_I2S7_8CH_RX_SRC_SEL, CLK_I2S7_8CH_RX_SRC_DIV), + CLK_I2S7_8CH_RX_FRAC = CLK64(0U, CLK_I2S7_8CH_RX_FRAC_DIV), + CLK_I2S7_8CH_RX = CLK64(MCLK_I2S7_8CH_RX_SEL, 0U), + CLK_I2S8_8CH_TX_SRC = CLK64(CLK_I2S8_8CH_TX_SRC_SEL, CLK_I2S8_8CH_TX_SRC_DIV), + CLK_I2S8_8CH_TX_FRAC = CLK64(0U, CLK_I2S8_8CH_TX_FRAC_DIV), + CLK_I2S8_8CH_TX = CLK64(MCLK_I2S8_8CH_TX_SEL, 0U), + CLK_I2S9_8CH_RX_SRC = CLK64(CLK_I2S9_8CH_RX_SRC_SEL, CLK_I2S9_8CH_RX_SRC_DIV), + CLK_I2S9_8CH_RX_FRAC = CLK64(0U, CLK_I2S9_8CH_RX_FRAC_DIV), + CLK_I2S9_8CH_RX = CLK64(MCLK_I2S9_8CH_RX_SEL, 0U), + CLK_I2S10_8CH_RX_SRC = CLK64(CLK_I2S10_8CH_RX_SRC_SEL, CLK_I2S10_8CH_RX_SRC_DIV), + CLK_I2S10_8CH_RX_FRAC = CLK64(0U, CLK_I2S10_8CH_RX_FRAC_DIV), + CLK_I2S10_8CH_RX = CLK64(MCLK_I2S10_8CH_RX_SEL, 0U), + + CLK_SPDIF0 = CLK64(MCLK_SPDIF0_SEL, 0U), + CLK_SPDIF0_SRC = CLK64(CLK_SPDIF0_SRC_SEL, CLK_SPDIF0_SRC_DIV), + CLK_SPDIF0_FRAC = CLK64(0U, CLK_SPDIF0_FRAC_DIV), + CLK_SPDIF1 = CLK64(MCLK_SPDIF1_SEL, 0U), + CLK_SPDIF1_SRC = CLK64(CLK_SPDIF1_SRC_SEL, CLK_SPDIF1_SRC_DIV), + CLK_SPDIF1_FRAC = CLK64(0U, CLK_SPDIF1_FRAC_DIV), + CLK_SPDIF2_DP0 = CLK64(MCLK_4X_SPDIF2_DP0_SEL, 0U), + CLK_SPDIF2_DP0_SRC = CLK64(CLK_SPDIF2_DP0_SRC_SEL, CLK_SPDIF2_DP0_SRC_DIV), + CLK_SPDIF2_DP0_FRAC = CLK64(0U, CLK_SPDIF2_DP0_FRAC_DIV), + CLK_SPDIF3 = CLK64(MCLK_SPDIF3_SEL, 0U), + CLK_SPDIF3_SRC = CLK64(CLK_SPDIF3_SRC_SEL, CLK_SPDIF3_SRC_DIV), + CLK_SPDIF3_FRAC = CLK64(0U, CLK_SPDIF3_FRAC_DIV), + CLK_SPDIF4 = CLK64(MCLK_SPDIF4_SEL, 0U), + CLK_SPDIF4_SRC = CLK64(CLK_SPDIF4_SRC_SEL, CLK_SPDIF4_SRC_DIV), + CLK_SPDIF4_FRAC = CLK64(0U, CLK_SPDIF4_FRAC_DIV), + CLK_SPDIF5_DP1 = CLK64(MCLK_4X_SPDIF5_DP1_SEL, 0U), + CLK_SPDIF5_DP1_SRC = CLK64(CLK_SPDIF5_DP1_SRC_SEL, CLK_SPDIF5_DP1_SRC_DIV), + CLK_SPDIF5_DP1_FRAC = CLK64(0U, CLK_SPDIF5_DP1_FRAC_DIV), + + /* net */ + CLK_GMAC_125M = CLK64(CLK_GMAC_125M_CRU_I_SEL, CLK_GMAC_125M_CRU_I_DIV), + CLK_GMAC_50M = CLK64(CLK_GMAC_50M_CRU_I_SEL, CLK_GMAC_50M_CRU_I_DIV), + REFCLKO25M_ETH0_OUT = CLK64(REFCLKO25M_ETH0_OUT_SEL, REFCLKO25M_ETH0_OUT_DIV), + REFCLKO25M_ETH1_OUT = CLK64(REFCLKO25M_ETH1_OUT_SEL, REFCLKO25M_ETH1_OUT_DIV), + + /* display */ + DCLK_VOP0_SRC = CLK64(DCLK_VOP0_SRC_SEL, DCLK_VOP0_SRC_DIV), + DCLK_VOP1_SRC = CLK64(DCLK_VOP1_SRC_SEL, DCLK_VOP1_SRC_DIV), + DCLK_VOP2_SRC = CLK64(DCLK_VOP2_SRC_SEL, DCLK_VOP2_SRC_DIV), + DCLK_VOP0 = CLK64(DCLK_VOP0_SEL, 0U), + DCLK_VOP1 = CLK64(DCLK_VOP1_SEL, 0U), + DCLK_VOP2 = CLK64(DCLK_VOP2_SEL, 0U), + DCLK_VOP3 = CLK64(DCLK_VOP3_SEL, DCLK_VOP3_DIV), + + /* other interface */ + CLK_UART0_SRC = CLK64(0U, CLK_UART0_SRC_DIV), + CLK_UART0_FRAC = CLK64(0U, CLK_UART0_FRAC_DIV), + CLK_UART0 = CLK64(SCLK_UART0_SEL, 0U), + CLK_UART1_SRC = CLK64(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV), + CLK_UART1_FRAC = CLK64(0U, CLK_UART1_FRAC_DIV), + CLK_UART1 = CLK64(SCLK_UART1_SEL, 0U), + CLK_UART2_SRC = CLK64(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV), + CLK_UART2_FRAC = CLK64(0U, CLK_UART2_FRAC_DIV), + CLK_UART2 = CLK64(SCLK_UART2_SEL, 0U), + CLK_UART3_SRC = CLK64(CLK_UART3_SRC_SEL, CLK_UART3_SRC_DIV), + CLK_UART3_FRAC = CLK64(0U, CLK_UART3_FRAC_DIV), + CLK_UART3 = CLK64(SCLK_UART3_SEL, 0U), + CLK_UART4_SRC = CLK64(CLK_UART4_SRC_SEL, CLK_UART4_SRC_DIV), + CLK_UART4_FRAC = CLK64(0U, CLK_UART4_FRAC_DIV), + CLK_UART4 = CLK64(SCLK_UART4_SEL, 0U), + CLK_UART5_SRC = CLK64(CLK_UART5_SRC_SEL, CLK_UART5_SRC_DIV), + CLK_UART5_FRAC = CLK64(0U, CLK_UART5_FRAC_DIV), + CLK_UART5 = CLK64(SCLK_UART5_SEL, 0U), + CLK_UART6_SRC = CLK64(CLK_UART6_SRC_SEL, CLK_UART6_SRC_DIV), + CLK_UART6_FRAC = CLK64(0U, CLK_UART6_FRAC_DIV), + CLK_UART6 = CLK64(SCLK_UART6_SEL, 0U), + CLK_UART7_SRC = CLK64(CLK_UART7_SRC_SEL, CLK_UART7_SRC_DIV), + CLK_UART7_FRAC = CLK64(0U, CLK_UART7_FRAC_DIV), + CLK_UART7 = CLK64(SCLK_UART7_SEL, 0U), + CLK_UART8_SRC = CLK64(CLK_UART8_SRC_SEL, CLK_UART8_SRC_DIV), + CLK_UART8_FRAC = CLK64(0U, CLK_UART8_FRAC_DIV), + CLK_UART8 = CLK64(SCLK_UART8_SEL, 0U), + CLK_UART9_SRC = CLK64(CLK_UART9_SRC_SEL, CLK_UART9_SRC_DIV), + CLK_UART9_FRAC = CLK64(0U, CLK_UART9_FRAC_DIV), + CLK_UART9 = CLK64(SCLK_UART9_SEL, 0U), + + CLK_I2C0 = CLK64(CLK_I2C0_SEL, 0U), + CLK_I2C1 = CLK64(CLK_I2C1_SEL, 0U), + CLK_I2C2 = CLK64(CLK_I2C2_SEL, 0U), + CLK_I2C3 = CLK64(CLK_I2C3_SEL, 0U), + CLK_I2C4 = CLK64(CLK_I2C4_SEL, 0U), + CLK_I2C5 = CLK64(CLK_I2C5_SEL, 0U), + CLK_I2C6 = CLK64(CLK_I2C6_SEL, 0U), + CLK_I2C7 = CLK64(CLK_I2C7_SEL, 0U), + CLK_I2C8 = CLK64(CLK_I2C8_SEL, 0U), + + CLK_PWM1 = CLK64(CLK_PWM1_SEL, 0U), + CLK_PWM2 = CLK64(CLK_PWM2_SEL, 0U), + CLK_PWM3 = CLK64(CLK_PWM3_SEL, 0U), + + CLK_SPI0 = CLK64(CLK_SPI0_SEL, 0U), + CLK_SPI1 = CLK64(CLK_SPI1_SEL, 0U), + CLK_SPI2 = CLK64(CLK_SPI2_SEL, 0U), + CLK_SPI3 = CLK64(CLK_SPI3_SEL, 0U), + CLK_SPI4 = CLK64(CLK_SPI4_SEL, 0U), + + HCLK_PMU_CM0 = CLK64(HCLK_PMU_CM0_ROOT_I_SEL, 0U), +} eCLOCK_Name; +#endif /* __ASSEMBLY__ */ +/****************************************MBOX********************************************/ +#define MBOX_CNT 2 +#define MBOX_CHAN_CNT 4 + +/***************************************INTMUX*******************************************/ +#define INTMUX0_PMU_BASE 0xFECF0000U /* INTMUX0_PMU base address */ +#define INTMUX1_PMU_BASE 0xFECF4000U /* INTMUX1_PMU base address */ +#define INTMUX0_DDR_BASE 0xFECF8000U /* INTMUX0_DDR base address */ +#define INTMUX1_DDR_BASE 0xFECFC000U /* INTMUX1_DDR base address */ + +/* INTMUX Register Structure Define */ +struct INTMUX_REG { + __IO uint32_t INT_ENABLE_GROUP[32]; /* Address Offset: 0x0000 */ + __IO uint32_t INT_FLAG_GROUP[32]; /* Address Offset: 0x0080 */ +}; + +#if defined(RKMCU_RK3588_PMU) +#define INTMUX0 ((struct INTMUX_REG *) INTMUX0_PMU_BASE) +#define INTMUX1 ((struct INTMUX_REG *) INTMUX1_PMU_BASE) +#elif defined(RKMCU_RK3588_DDR) +#define INTMUX0 ((struct INTMUX_REG *) INTMUX0_DDR_BASE) +#define INTMUX1 ((struct INTMUX_REG *) INTMUX1_DDR_BASE) +#endif + +#define IS_INTMUX0_INSTANCE(instance) ((instance) == INTMUX0) +#define IS_INTMUX1_INSTANCE(instance) ((instance) == INTMUX1) + +/****************************************************************************************/ +/* */ +/* Platform Differences Section */ +/* */ +/****************************************************************************************/ +#if defined(HAL_AP_CORE) + +#undef DCACHE +#undef ICACHE + +#endif + +#if defined(HAL_MCU_CORE) + +#if defined(RKMCU_RK3588_PMU) +#undef TIMER0_BASE +#undef TIMER1_BASE +#define TIMER0_BASE 0xFD8F0000U /* TIMER0 base address */ +#define TIMER1_BASE 0xFD8F0020U /* TIMER1 base address */ +#elif defined(RKMCU_RK3588_DDR) +#undef DCACHE +#undef ICACHE +#undef MBOX0_BASE +#define MBOX0_BASE 0xFEC70000U /* MBOX0 base address */ +#undef WDT_BASE +#define WDT_BASE 0xFE110000U /* WDT base address*/ +#undef TIMER0_BASE +#undef TIMER1_BASE +#define TIMER0_BASE 0xFE118000U /* TIMER0_BASE*/ +#define TIMER1_BASE 0xFE118020U /* TIMER1_BASE*/ +#elif defined(RKMCU_RK3588_NPU) +#undef MBOX0_BASE +#define MBOX0_BASE 0xFECE0000U /* MBOX0 base address */ +#undef WDT_BASE +#define WDT_BASE 0xFDAF8000U /* WDT base address*/ +#undef TIMER0_BASE +#undef TIMER1_BASE +#define TIMER0_BASE 0xFDB00000U /* TIMER0_BASE*/ +#define TIMER1_BASE 0xFDB00020U /* TIMER1_BASE*/ +#endif + +#endif + +/****************************************GPIO********************************************/ +#ifdef GPIO_VER_ID +#undef GPIO_VER_ID +#define GPIO_VER_ID (0x01000C2BU) +#endif + +/****************************************PMU*********************************************/ +#define RK3588_PD_GPU 0 +#define RK3588_PD_NPU 1 +#define RK3588_PD_VCODEC 2 +#define RK3588_PD_NPUTOP 3 +#define RK3588_PD_NPU1 4 +#define RK3588_PD_NPU2 5 +#define RK3588_PD_VENC0 6 +#define RK3588_PD_VENC1 7 +#define RK3588_PD_RKVDEC0 8 +#define RK3588_PD_RKVDEC1 9 +#define RK3588_PD_VDPU 10 +#define RK3588_PD_RGA30 11 +#define RK3588_PD_AV1 12 +#define RK3588_PD_VI 13 +#define RK3588_PD_FEC 14 +#define RK3588_PD_ISP1 15 +#define RK3588_PD_RGA31 16 +#define RK3588_PD_VOP 17 +#define RK3588_PD_VO0 18 +#define RK3588_PD_VO1 19 +#define RK3588_PD_AUDIO 20 +#define RK3588_PD_PHP 21 +#define RK3588_PD_GMAC 22 +#define RK3588_PD_PCIE 23 +#define RK3588_PD_NVM 24 +#define RK3588_PD_NVM0 25 +#define RK3588_PD_SDIO 26 +#define RK3588_PD_USB 27 +#define RK3588_PD_SDMMC 28 + +#define PD_RK3588(id) (id | 0x80000000U) + +#ifndef __ASSEMBLY__ +typedef enum PD_Id { + PD_INVALID = 0U, + PD_GPU = PD_RK3588(RK3588_PD_GPU), + PD_NPU = PD_RK3588(RK3588_PD_NPU), + PD_VCODEC = PD_RK3588(RK3588_PD_VCODEC), + PD_NPUTOP = PD_RK3588(RK3588_PD_NPUTOP), + PD_NPU1 = PD_RK3588(RK3588_PD_NPU1), + PD_NPU2 = PD_RK3588(RK3588_PD_NPU2), + PD_VENC0 = PD_RK3588(RK3588_PD_VENC0), + PD_VENC1 = PD_RK3588(RK3588_PD_VENC1), + PD_RKVDEC0 = PD_RK3588(RK3588_PD_RKVDEC0), + PD_RKVDEC1 = PD_RK3588(RK3588_PD_RKVDEC1), + PD_VDPU = PD_RK3588(RK3588_PD_VDPU), + PD_RGA30 = PD_RK3588(RK3588_PD_RGA30), + PD_AV1 = PD_RK3588(RK3588_PD_AV1), + PD_VI = PD_RK3588(RK3588_PD_VI), + PD_FEC = PD_RK3588(RK3588_PD_FEC), + PD_ISP1 = PD_RK3588(RK3588_PD_ISP1), + PD_RGA31 = PD_RK3588(RK3588_PD_RGA31), + PD_VOP = PD_RK3588(RK3588_PD_VOP), + PD_VO0 = PD_RK3588(RK3588_PD_VO0), + PD_VO1 = PD_RK3588(RK3588_PD_VO1), + PD_AUDIO = PD_RK3588(RK3588_PD_AUDIO), + PD_PHP = PD_RK3588(RK3588_PD_PHP), + PD_GMAC = PD_RK3588(RK3588_PD_GMAC), + PD_PCIE = PD_RK3588(RK3588_PD_PCIE), + PD_NVM = PD_RK3588(RK3588_PD_NVM), + PD_NVM0 = PD_RK3588(RK3588_PD_NVM0), + PD_SDIO = PD_RK3588(RK3588_PD_SDIO), + PD_USB = PD_RK3588(RK3588_PD_USB), + PD_SDMMC = PD_RK3588(RK3588_PD_SDMMC), +} ePD_Id; +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __SOC_H */ diff --git a/demos/rk3588/bsp/print.c b/demos/rk3588/bsp/print.c index 8371dff6..a42809aa 100755 --- a/demos/rk3588/bsp/print.c +++ b/demos/rk3588/bsp/print.c @@ -2,6 +2,7 @@ #include "prt_typedef.h" #include "cpu_config.h" #include "securec.h" +#include "hal_base.h" #define OS_MAX_SHOW_LEN 0x200 @@ -10,12 +11,9 @@ U32 PRT_UartInit(void) return OS_FAIL; } -void uart_poll_send(unsigned char ch) +static inline void uart_poll_send(unsigned char ch) { - /* 暂不使用uart，先直接写串口寄存器地址，启用MMU后速度加快，延时相应的增加 */ - volatile int time = 25000; - *(unsigned int *)UART_BASE_ADDR = ch; - while (time--); + HAL_UART_SerialOutChar(UART2, ch); } void TestPutc(unsigned char ch) -- Gitee