From b5a8165079a8e9b14e1c92505ee61478fe8abdfa Mon Sep 17 00:00:00 2001 From: guo-uni Date: Thu, 12 Jun 2025 02:33:01 +0000 Subject: [PATCH] demos: support UniProton started on hi3095 FusionDock support UniProton started on hi3095 FusionDock Signed-off-by: guoliwei --- .../config_armv8_hi3095/defconfig | 5 +++ demos/hi3095/bsp/hi3095/cpu_config.h | 4 +++ demos/hi3095/bsp/start.S | 5 +++ demos/hi3095/bsp/timer.c | 32 +++++++++++++++++++ demos/hi3095/config/prt_config.h | 8 +++++ 5 files changed, 54 insertions(+) diff --git a/build/uniproton_config/config_armv8_hi3095/defconfig b/build/uniproton_config/config_armv8_hi3095/defconfig index 7df41abe..4d780437 100644 --- a/build/uniproton_config/config_armv8_hi3095/defconfig +++ b/build/uniproton_config/config_armv8_hi3095/defconfig @@ -149,6 +149,11 @@ CONFIG_OS_OPTION_LOCALE=y CONFIG_OS_OPTION_OPENAMP=y CONFIG_OS_OPTION_PROXY=y +# +# Guest Modules Configuration, mutually exclusive with Openamp +# +# CONFIG_GUEST_OS is not set + # # enable CXX # diff --git a/demos/hi3095/bsp/hi3095/cpu_config.h b/demos/hi3095/bsp/hi3095/cpu_config.h index 76c4a759..536b4cfc 100644 --- a/demos/hi3095/bsp/hi3095/cpu_config.h +++ b/demos/hi3095/bsp/hi3095/cpu_config.h @@ -14,7 +14,11 @@ #define UART_BASE_ADDR MMU_UART_ADDR +#if defined(GUEST_OS) +#define TEST_CLK_INT 27 +#else #define TEST_CLK_INT 30 +#endif #define OS_GIC_VER 3 #define SICR_ADDR_OFFSET_PER_CORE 0x20000U diff --git a/demos/hi3095/bsp/start.S b/demos/hi3095/bsp/start.S index c349dad9..3485b940 100644 --- a/demos/hi3095/bsp/start.S +++ b/demos/hi3095/bsp/start.S @@ -96,6 +96,11 @@ OsEl2SwitchToEl1: ERET Start: +#if defined(GUEST_OS) + MOV x4, #3 << 20 + MSR CPACR_EL1, x4 +#endif + #if defined(OS_OPTION_SMP) OsAsmGetCoreId x0 // 读取核号 LDR x4, =g_cfgPrimaryCore diff --git a/demos/hi3095/bsp/timer.c b/demos/hi3095/bsp/timer.c index 0c5c616a..6c21b6f9 100644 --- a/demos/hi3095/bsp/timer.c +++ b/demos/hi3095/bsp/timer.c @@ -18,6 +18,37 @@ U64 GetGenericTimerFreq(void) return freq; } +#if defined(GUEST_OS) +void TimerIsr(uintptr_t para) +{ + (void)para; + U32 cfgMask = 0x0; + U64 cycle = PMU_TIMER_FREQUENCY / OS_TICK_PER_SECOND; + + OS_EMBED_ASM("MSR CNTV_CTL_EL0, %0" : : "r"(cfgMask) : "memory"); + PRT_ISB(); + OS_EMBED_ASM("MSR CNTV_TVAL_EL0, %0" : : "r"(cycle) : "memory", "cc"); + + cfgMask = 0x1; + OS_EMBED_ASM("MSR CNTV_CTL_EL0, %0" : : "r"(cfgMask) : "memory"); + + PRT_TickISR(); + PRT_ISB(); +} + +void CoreTimerInit(void) +{ + U32 cfgMask = 0x0; + U64 cycle = PMU_TIMER_FREQUENCY / OS_TICK_PER_SECOND; + + OS_EMBED_ASM("MSR CNTV_CTL_EL0, %0" : : "r"(cfgMask) : "memory"); + PRT_ISB(); + OS_EMBED_ASM("MSR CNTV_TVAL_EL0, %0" : : "r"(cycle) : "memory", "cc"); + + cfgMask = 0x1; + OS_EMBED_ASM("MSR CNTV_CTL_EL0, %0" : : "r"(cfgMask) : "memory"); +} +#else void TimerIsr(uintptr_t para) { (void)para; @@ -47,6 +78,7 @@ void CoreTimerInit(void) cfgMask = 0x1; OS_EMBED_ASM("MSR CNTP_CTL_EL0, %0" : : "r"(cfgMask) : "memory"); } +#endif U32 CoreTimerStart(void) { diff --git a/demos/hi3095/config/prt_config.h b/demos/hi3095/config/prt_config.h index a24ef9a4..8675127f 100644 --- a/demos/hi3095/config/prt_config.h +++ b/demos/hi3095/config/prt_config.h @@ -34,7 +34,11 @@ extern "C" { /* 最大可支持的核数，单位：个 */ #define OS_SYS_CORE_MAX_NUM 4 /* 主核ID */ +#if defined(GUEST_OS) +#define OS_SYS_CORE_PRIMARY 0 +#else #define OS_SYS_CORE_PRIMARY 3 +#endif /* ***************************** 中断模块配置 ************************** */ /* 硬中断最大支持个数 */ @@ -88,7 +92,11 @@ extern "C" { /* 私有FSC内存分区起始地址 */ #define OS_MEM_FSC_PT_ADDR (uintptr_t)&g_memRegion00[0] /* 私有FSC内存分区大小 */ +#if defined(GUEST_OS) +#define OS_MEM_FSC_PT_SIZE 0x80000 +#else #define OS_MEM_FSC_PT_SIZE 0x1d000000 +#endif /* ***************************** 配置信号量管理模块 ************************* */ /* 信号量模块裁剪开关 */ -- Gitee