diff --git a/build.py b/build.py
index 37e34304c149a9c7ec9c68b9cbd10f85f86ab01e..061eedb4e74c2dc88f63ed824e408e9b41ccaaee 100644
--- a/build.py
+++ b/build.py
@@ -80,6 +80,8 @@ class Compile:
             self.build_machine_platform = 'arm64'
         elif platform.uname()[-1] == 'x86_64':
             self.build_machine_platform = 'x86'
+        elif platform.uname()[-1] == 'arm':
+            self.build_machine_platform = 'arm'
         else:
             self.build_machine_platform = 'riscv64'
             self.cmake_env_path = os.path.dirname(
diff --git a/build/uniproton_ci_lib/globle.py b/build/uniproton_ci_lib/globle.py
index 11b609d137a999e8dfc491fdf214fb6f1d44c33d..2d7cf4e676e0ded2a038b813c09064690d0d1976 100755
--- a/build/uniproton_ci_lib/globle.py
+++ b/build/uniproton_ci_lib/globle.py
@@ -10,7 +10,7 @@ home_path = os.path.dirname(build_dir)
 config_dir = os.path.join(home_path,'config.xml')
 kbuild_path = '%s/cmake/common/build_auxiliary_script' % home_path
 
-cpus_ = {'all': ['clean', 'm4', 'raspi4', 'hi3093', 'hi3095', 'atlasa1', 'kp920', 'kp920_lite', 'x86_64', 'rk3568_jailhouse', 'rk3588', 'ascend310b', 'uvp', 'rv64virt', 'ds-d1s', 'e2000q','visionfive2'],
+cpus_ = {'all': ['clean', 'm4', 'raspi4', 'hi3093', 'hi3095', 'atlasa1', 'kp920', 'kp920_lite', 'x86_64', 'rk3568_jailhouse', 'rk3588', 'ascend310b', 'uvp', 'rv64virt', 'ds-d1s', 'e2000q','visionfive2', 'd9_secure'],
          'clean': ['clean'],
          'm4': ['m4'],
          'raspi4': ['raspi4'],
@@ -28,7 +28,8 @@ cpus_ = {'all': ['clean', 'm4', 'raspi4', 'hi3093', 'hi3095', 'atlasa1', 'kp920'
          'ds-d1s': ['ds-d1s'],
          'e2000q': ['e2000q'],
 	     'milkvduol' : ['milkvduol'],
-         'visionfive2' : ['visionfive2']
+         'visionfive2' : ['visionfive2'],
+	     'd9_secure': ['d9_secure']
          }
 
 cpu_plat = {'m4': ['cortex'],
@@ -47,5 +48,6 @@ cpu_plat = {'m4': ['cortex'],
             'ds-d1s': ['riscv64'],
             'e2000q': ['armv8'],
 	        'milkvduol' : ['riscv64'],
-            'visionfive2': ['riscv64']
+            'visionfive2': ['riscv64'],
+            'd9_secure': ['cortex_r5']
            }
diff --git a/build/uniproton_config/config_cortex_r5_d9_secure/defconfig b/build/uniproton_config/config_cortex_r5_d9_secure/defconfig
new file mode 100755
index 0000000000000000000000000000000000000000..302e367c7a4537a078e83c7b4b46f50cb2cf58a4
--- /dev/null
+++ b/build/uniproton_config/config_cortex_r5_d9_secure/defconfig
@@ -0,0 +1,154 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# UniProton Configuration
+#
+
+#
+# Arch Modules Configuration
+#
+CONFIG_OS_ARCH_ARMV7_R=y
+# CONFIG_OS_OPTION_GUARD_STACK=y
+CONFIG_OS_ARCH_ABT_STACK_SIZE=128
+CONFIG_OS_ARCH_IRQ_STACK_SIZE=512
+CONFIG_OS_ARCH_FIQ_STACK_SIZE=256
+CONFIG_OS_ARCH_SYS_STACK_SIZE=2048
+CONFIG_OS_ARCH_UND_STACK_SIZE=128
+CONFIG_OS_ARCH_SVC_STACK_SIZE=4096
+
+#
+# ARM7-R Sepecfic Configuration
+#
+CONFIG_INTERNAL_OS_D9_SECURE=y
+CONFIG_INTERNAL_OS_PLATFORM_CORTEX_R5=y
+
+#
+# Generic Configuration
+#
+CONFIG_OS_HARDWARE_PLATFORM="OS_CORTEX_R5"
+CONFIG_OS_CPU_TYPE="OS_D9_SECURE"
+CONFIG_OS_MAX_CORE_NUM=1
+CONFIG_OS_THIS_CORE=0
+CONFIG_INTERNAL_OS_BYTE_ORDER_LE=y
+CONFIG_OS_BYTE_ORDER="OS_LITTLE_ENDIAN"
+CONFIG_OS_CACHE_LINE_SIZE=32
+
+#
+# Core Modules Configuration
+#
+
+#
+# IPC Modules Configuration
+#
+
+#
+# Event feature configuration
+#
+CONFIG_OS_OPTION_EVENT=y
+CONFIG_OS_OPTION_QUEUE=y
+
+#
+# Semaphore feature configuration
+#
+CONFIG_OS_OPTION_BIN_SEM=y
+CONFIG_OS_OPTION_SEM_RECUR_PV=y
+CONFIG_OS_OPTION_SEM_PRIOR=y
+
+#
+# Kernel Modules Configuration
+#
+
+#
+# IRQ Modules Configuration
+#
+# CONFIG_OS_OPTION_HWI_COMBINE is not set
+CONFIG_INTERNAL_OS_GIC_VER="gicv600"
+CONFIG_OS_GIC_VER=2
+CONFIG_GIC_DIST_BASE=0xf5411000U
+
+CONFIG_OS_OPTION_HWI_PRIORITY=y
+CONFIG_OS_OPTION_HWI_ATTRIBUTE=y
+# CONFIG_OS_OPTION_HWI_MAX_NUM_CONFIG is not set
+
+#
+# Exc Modules Configuration
+CONFIG_INTERNAL_OS_SCHEDULE_SINGLE_CORE_BY_CCODE=y
+# CONFIG_OS_OPTION_SYS_TIME_USR=y
+#
+
+#
+# Task module Configuration
+#
+CONFIG_OS_OPTION_TASK=y
+
+#
+# TASK features configuration
+#
+CONFIG_OS_OPTION_TASK_DELETE=y
+CONFIG_OS_OPTION_TASK_SUSPEND=y
+CONFIG_OS_OPTION_TASK_INFO=y
+CONFIG_OS_OPTION_TASK_YIELD=y
+CONFIG_OS_TSK_PRIORITY_HIGHEST=0
+CONFIG_OS_TSK_PRIORITY_LOWEST=31
+CONFIG_OS_TSK_NUM_OF_PRIORITIES=32
+CONFIG_OS_TSK_CORE_BYTES_IN_PID=2
+
+#
+# Timer Modules Configuration
+#
+CONFIG_INTERNAL_OS_SWTMR=y
+
+#
+# MM Modules Configuration
+#
+
+#
+# OM Modules Configuration
+#
+CONFIG_OS_OPTION_CPUP=y
+
+#
+# CPUP features configuration
+#
+CONFIG_INTERNAL_OS_CPUP_THREAD=y
+CONFIG_OS_OPTION_CPUP_WARN=y
+
+#
+# Error Report Module Configuration
+#
+
+#
+# Hook feature configuration
+#
+
+#
+# Debug configuration
+#
+# CONFIG_OS_GDB_STUB=y
+# CONFIG_OS_GDB_STUB_UART=y
+# CONFIG_OS_OPTION_COREDUMP=y
+
+#
+# security Modules Configuration
+#
+CONFIG_OS_OPTION_RND=y
+
+CONFIG_OS_OPTION_POSIX=y
+CONFIG_OS_OPTION_POSIX_SIGNAL=y
+CONFIG_OS_POSIX_TYPE_NEWLIB=y
+CONFIG_OS_POSIX_SET_TZDST=y
+CONFIG_OS_OPTION_LOCALE=y
+
+# CONFIG_OS_OPTION_RR_SCHED=y
+# CONFIG_OS_OPTION_RR_SCHED_IRQ_TIME_DISCOUNT=y
+
+#
+# Openamp Modules Configuration
+#
+# CONFIG_OS_OPTION_OPENAMP=y
+# CONFIG_OS_OPTION_RSC_TABLE=y
+#
+
+#
+# Utility Modules Configuration
+#
+
diff --git a/cmake/common/build_auxiliary_script/make_lib_rename_file_type.sh b/cmake/common/build_auxiliary_script/make_lib_rename_file_type.sh
index 534a122979d7f498aa528e42913e7dfd9c6d4f73..33f27f3ab522744141bf4087ee9975df40f0b177 100755
--- a/cmake/common/build_auxiliary_script/make_lib_rename_file_type.sh
+++ b/cmake/common/build_auxiliary_script/make_lib_rename_file_type.sh
@@ -14,7 +14,7 @@ CK_LIB_SUFFIX="$3"
 file=lib"${CK_LIB_SUFFIX}"
 
 
-if [ "${CPU_TYPE}" = "m4" ] ; then
+if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "d9_secure" ] ; then
     ARNAME=arm-none-eabi-ar ; OBJCOPYNAME=arm-none-eabi-objcopy;
 elif [ "${CPU_TYPE}" = "raspi4" ] || [ "${CPU_TYPE}" = "hi3093" ] || [ "${CPU_TYPE}" = "hi3095" ] || [ "${CPU_TYPE}" = "atlasa1" ] || [ "${CPU_TYPE}" = "kp920" ] || [ "${CPU_TYPE}" = "kp920_lite" ] || [ "${CPU_TYPE}" = "rk3568_jailhouse" ] || [ "${CPU_TYPE}" = "rk3588" ] || [ "${CPU_TYPE}" = "ascend310b" ] || [ "${CPU_TYPE}" = "e2000q" ];
     then ARNAME=aarch64-none-elf-ar; OBJCOPYNAME=aarch64-none-elf-objcopy;
@@ -29,7 +29,7 @@ fi
 sleep 2
 pushd "$CK_LIB_PATH"
 ##为什么不加这一行要报错
-if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "raspi4" ] || [ "${CPU_TYPE}" = "hi3093" ] || [ "${CPU_TYPE}" = "hi3095" ] || [ "${CPU_TYPE}" = "atlasa1" ] || [ "${CPU_TYPE}" = "kp920" ] || [ "${CPU_TYPE}" = "kp920_lite" ] || [ "${CPU_TYPE}" = "x86_64" ] || [ "${CPU_TYPE}" = "rk3568_jailhouse" ] || [ "${CPU_TYPE}" = "rk3588" ] || [ "${CPU_TYPE}" = "ascend310b" ] || [ "${CPU_TYPE}" = "rv64virt" ] || [ "${CPU_TYPE}" = "ds-d1s" ] || [ "${CPU_TYPE}" = "e2000q" ] || [ "${CPU_TYPE}" = "milkvduol" ]; then
+if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "raspi4" ] || [ "${CPU_TYPE}" = "hi3093" ] || [ "${CPU_TYPE}" = "hi3095" ] || [ "${CPU_TYPE}" = "atlasa1" ] || [ "${CPU_TYPE}" = "kp920" ] || [ "${CPU_TYPE}" = "kp920_lite" ] || [ "${CPU_TYPE}" = "x86_64" ] || [ "${CPU_TYPE}" = "rk3568_jailhouse" ] || [ "${CPU_TYPE}" = "rk3588" ] || [ "${CPU_TYPE}" = "ascend310b" ] || [ "${CPU_TYPE}" = "rv64virt" ] || [ "${CPU_TYPE}" = "ds-d1s" ] || [ "${CPU_TYPE}" = "e2000q" ] || [ "${CPU_TYPE}" = "milkvduol" ] || [ "${CPU_TYPE}" = "d9_secure" ]; then
     [ -n tmp_"${file}" ] && rm -rf tmp_"${file}" 
 fi
 mkdir tmp_"${file}"
@@ -40,13 +40,13 @@ pushd tmp_"${file}"
 # 删除某变量指定的目录下所有文件。
 # 通过对变量${FILE_PATH}进行判断，当${FILE_PATH}为空时，不会错误删除根目录下的文件。
 [ -n "${file}" ] && rm -rf "${file}"
-if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "raspi4" ] || [ "${CPU_TYPE}" = "hi3093" ] || [ "${CPU_TYPE}" = "hi3095" ] || [ "${CPU_TYPE}" = "kp920" ] || [ "${CPU_TYPE}" = "kp920_lite" ] || [ "${CPU_TYPE}" = "atlasa1" ]|| [ "${CPU_TYPE}" = "rk3568_jailhouse" ] || [ "${CPU_TYPE}" = "rk3588" ] || [ "${CPU_TYPE}" = "ascend310b" ] || [ "${CPU_TYPE}" = "rv64virt" ] || [ "${CPU_TYPE}" = "ds-d1s" ] || [ "${CPU_TYPE}" = "e2000q" ] || [ "${CPU_TYPE}" = "milkvduol" ]; then  
+if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "raspi4" ] || [ "${CPU_TYPE}" = "hi3093" ] || [ "${CPU_TYPE}" = "hi3095" ] || [ "${CPU_TYPE}" = "kp920" ] || [ "${CPU_TYPE}" = "kp920_lite" ] || [ "${CPU_TYPE}" = "atlasa1" ]|| [ "${CPU_TYPE}" = "rk3568_jailhouse" ] || [ "${CPU_TYPE}" = "rk3588" ] || [ "${CPU_TYPE}" = "ascend310b" ] || [ "${CPU_TYPE}" = "rv64virt" ] || [ "${CPU_TYPE}" = "ds-d1s" ] || [ "${CPU_TYPE}" = "e2000q" ] || [ "${CPU_TYPE}" = "milkvduol" ] || [ "${CPU_TYPE}" = "d9_secure" ]; then  
     find . -name '*.s.o'| awk -F "." '{print $2}'|xargs -I'{}' mv ./{}.s.o ./{}.o
     find . -name '*.S.o'| awk -F "." '{print $2}'|xargs -I'{}' mv ./{}.S.o ./{}.o
     find . -name '*.c.o'| awk -F "." '{print $2}'|xargs -I'{}' mv ./{}.c.o ./{}.o
 fi
 
-if [ "${CPU_TYPE}" = "m4" ] ; then
+if [ "${CPU_TYPE}" = "m4" ] || [ "${CPU_TYPE}" = "d9_secure" ] ; then
     for i in $(ls *.o);
     do
         if [ -f "${i}" ]  ; then
diff --git a/cmake/tool_chain/d9_secure-cortex_r5-config.cmake.in b/cmake/tool_chain/d9_secure-cortex_r5-config.cmake.in
new file mode 100755
index 0000000000000000000000000000000000000000..c9f4e6c99ac2c94c22c18b630775ed1629f5d488
--- /dev/null
+++ b/cmake/tool_chain/d9_secure-cortex_r5-config.cmake.in
@@ -0,0 +1,14 @@
+@PACKAGE_INIT@
+include(${CMAKE_CURRENT_LIST_DIR}/UniProton-d9_secure-cortex_r5-targets.cmake)
+
+
+
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_BASE_DIR               "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_BASE_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR            "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_SEC_DIR        "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_SEC_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_DIR            "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR        "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR     "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR@")
+set_and_check(INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR             "@PACKAGE_INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR@")
+
+check_required_components(UniProton-d9_secure-cortex_r5)
\ No newline at end of file
diff --git a/cmake/tool_chain/d9_secure_cortex_r5.cmake b/cmake/tool_chain/d9_secure_cortex_r5.cmake
new file mode 100755
index 0000000000000000000000000000000000000000..fc0e4c9a0a75003284ea12e28c6d3257f7aafcf2
--- /dev/null
+++ b/cmake/tool_chain/d9_secure_cortex_r5.cmake
@@ -0,0 +1,137 @@
+set(BUILD_DIR "$ENV{BUILD_TMP_DIR}" ) #version id
+set(OBJCOPY_PATH "$ENV{OBJCOPY_PATH}" ) #OBJCOPY_PATH
+
+#将所有对象库添加到列表中
+foreach(FILE_NAME ${ALL_OBJECT_LIBRARYS})
+    list(APPEND CORTEX_R5_D9_SECURE_SRCS
+        $<TARGET_OBJECTS:${FILE_NAME}>
+    )
+endforeach()
+
+#编译结果
+string(TOUPPER ${PLAM_TYPE} PLAM_TYPE_UP)
+string(TOUPPER ${CPU_TYPE} CPU_TYPE_UP)
+#编译.a库
+add_library(D9_SECURE  STATIC "${CORTEX_R5_D9_SECURE_SRCS}")
+set_target_properties(D9_SECURE PROPERTIES SUFFIX ".a")
+
+add_custom_target(cleanobj)
+add_custom_command(TARGET cleanobj POST_BUILD
+                   COMMAND echo "Finish Building!"
+                   )
+
+if (${COMPILE_MODE} STREQUAL "debug")
+    message("=============== COMPILE_MODE is ${COMPILE_MODE} ===============")
+endif()
+####以下为d9_secure make install打包脚本#####
+set(d9_secure_cortex_r5_export modules)
+
+# 下面的变量分别定义了安装根目录、头文件安装目录、动态库安装目录、静态库安装目录、OBJECT文件安装目录、可执行程序安装目录、配置文件安装目录。
+# 注意：所有安装路径必须是相对CMAKE_INSTALL_PREFIX的相对路径，不可以使用绝对路径!!!
+# 否则安装目录下的配置文件(foo-config.cmake, foo-tragets.cmake等)拷贝到其它目录时无法工作。
+set(INSTALL_D9_SECURE_CORTEX_R5_BASE_DIR               .)
+set(INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR            UniProton/include)
+set(INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_SEC_DIR        libboundscheck/include)
+set(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_DIR            UniProton/lib/d9_secure)
+set(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR        libboundscheck/lib/d9_secure)
+set(INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR     UniProton/config)
+set(INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR             cmake/d9_secure)
+
+
+
+
+include(CMakePackageConfigHelpers)
+configure_package_config_file(${PROJECT_SOURCE_DIR}/cmake/tool_chain/d9_secure-cortex_r5-config.cmake.in
+    ${CMAKE_CURRENT_BINARY_DIR}/UniProton-d9_secure-cortex_r5-config.cmake
+    INSTALL_DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR}
+    PATH_VARS
+    INSTALL_D9_SECURE_CORTEX_R5_BASE_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_SEC_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR
+    INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR
+    INSTALL_PREFIX ${CMAKE_INSTALL_PREFIX}
+)
+install(EXPORT ${d9_secure_cortex_r5_export}
+        NAMESPACE UniProton::
+        FILE UniProton-d9_secure-cortex_r5-targets.cmake
+        DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR}
+)
+install(FILES
+    ${CMAKE_CURRENT_BINARY_DIR}/UniProton-d9_secure-cortex_r5-config.cmake
+    DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_CONFIG_DIR}
+)
+
+install(TARGETS
+    D9_SECURE
+    EXPORT ${d9_secure_cortex_r5_export}
+    ARCHIVE DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_DIR}/
+)
+
+if (${COMPILE_OPTION} STREQUAL "coverity" OR ${COMPILE_OPTION} STREQUAL "fortify" OR ${COMPILE_OPTION} STREQUAL "UniProton")
+    message("Don't Install Sec Lib In ${COMPILE_OPTION}")
+else()
+    install(TARGETS
+        CortexMXsec_c
+        EXPORT ${d9_secure_cortex_r5_export}
+        ARCHIVE DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR}
+    )
+
+    if (NOT "${RPROTON_INSTALL_FILE_OPTION}" STREQUAL "SUPER_BUILD")
+        ##{GLOB 所有文件 | GLOB_RECURSE 递归查找文件&文件夹}
+        file(GLOB glob_sec_files  ${PROJECT_SOURCE_DIR}/platform/libboundscheck/include/*.h)
+        install(FILES
+            ${glob_sec_files}
+            DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_SEC_DIR}
+        )
+    endif()
+endif()
+
+install(FILES
+    ${PROJECT_SOURCE_DIR}/build/uniproton_config/config_cortex_r5_d9_secure/prt_buildef.h
+    DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR}/d9_secure/
+)
+if (NOT "${RPROTON_INSTALL_FILE_OPTION}" STREQUAL "SUPER_BUILD")
+    ##{GLOB 所有文件 | GLOB_RECURSE 递归查找文件&文件夹}
+
+    install(FILES
+        ${PROJECT_SOURCE_DIR}/src/config/prt_config.c
+        ${PROJECT_SOURCE_DIR}/src/config/prt_config_internal.h
+        ${PROJECT_SOURCE_DIR}/src/config/config/prt_config.h
+        DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_ARCHIVE_CONFIG_DIR}
+    )
+
+    ##{GLOB 所有文件 | GLOB_RECURSE 递归查找文件&文件夹}
+    file(GLOB hw_drv_include_files  ${PROJECT_SOURCE_DIR}/src/include/uapi/hw/armv7-r/*)
+    install(FILES
+        ${hw_drv_include_files}
+        DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR}/hw/armv7-r
+    )
+
+
+    install(FILES
+
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_clk.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_cpup.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_err.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_errno.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_event.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_exc.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_hook.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_hwi.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_idle.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_mem.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_module.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_queue.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_sem.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_sys.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_task.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_tick.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_timer.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_typedef.h
+        ${PROJECT_SOURCE_DIR}/src/include/uapi/prt_signal.h
+        DESTINATION ${INSTALL_D9_SECURE_CORTEX_R5_INCLUDE_DIR}/
+    )
+endif()
diff --git a/cmake/tool_chain/uniproton_tool_chain.cmake b/cmake/tool_chain/uniproton_tool_chain.cmake
index 07475ad5bf0c835e8aa83233b4ee360fa062107a..ac117140b31c0884ece14c2cb5a86fee340f06eb 100755
--- a/cmake/tool_chain/uniproton_tool_chain.cmake
+++ b/cmake/tool_chain/uniproton_tool_chain.cmake
@@ -13,7 +13,7 @@ set(COMPILE_OPTION "$ENV{COMPILE_OPTION}" )
 set(RPROTON_INSTALL_FILE_OPTION "$ENV{RPROTON_INSTALL_FILE_OPTION}" )##RPROTON_INSTALL_FILE_OPTION="SUPER_BUILD";
 
 
-if (${CPU_TYPE} STREQUAL "m4")
+if (${CPU_TYPE} STREQUAL "m4" OR ${CPU_TYPE} STREQUAL "d9_secure")
 #### 统一告警选项,请审慎增删
 set(STRONG_COMPILE_WARING_FLAG "-Wunused -Wredundant-decls -Wfloat-conversion -Wwrite-strings -Wunused-macros -Wswitch-default -Wshift-overflow=2 -Wnested-externs -Wmissing-include-dirs -Wlogical-op -Wjump-misses-init -Wformat-security -Wvla -Wframe-larger-than=4096 -Wduplicated-cond  -Wdisabled-optimization -Wignored-qualifiers -Wimplicit-fallthrough=3 -Wpointer-arith -Wshift-negative-value -Wsign-compare -Wtype-limits -Wcast-qual -Wundef -Wbad-function-cast -Wold-style-definition -Wpacked -Wstrict-prototypes -Wstack-usage=2048")
 set(COMPILE_WARING_FLAG " -Wall -Werror  -Wextra -Wformat=2 -Wfloat-equal -Wshadow -Wtrampolines -Wdate-time ")## -Wall -Werror  -Wextra -Wformat=2 -Wfloat-equal 
diff --git a/cmake/tool_chain/uniproton_tool_chain_gcc.cmake b/cmake/tool_chain/uniproton_tool_chain_gcc.cmake
index 84cd3a090cab5332da5a8190884f3122f81966b9..a358bcf82dff0a7db379031eeb2f992d5dc6913d 100644
--- a/cmake/tool_chain/uniproton_tool_chain_gcc.cmake
+++ b/cmake/tool_chain/uniproton_tool_chain_gcc.cmake
@@ -38,6 +38,19 @@ if(${CPU_TYPE} STREQUAL "m4")
         set(CMAKE_C_COMPILE_OBJECT "${CMAKE_C_COMPILE_OBJECT} ${STRONG_COMPILE_WARING_FLAG} ${COMPILE_WARING_FLAG} -std=gnu11 -fno-common -fomit-frame-pointer -mcpu=cortex-m4 -mthumb -mfloat-abi=softfp -mfpu=fpv4-sp-d16   -fstack-protector-strong  -fdata-sections  -ffunction-sections -fshort-enums  -funsigned-char -DSECUREC_BUFFER_SIZE=32 <FLAGS> <INCLUDES> -c <SOURCE> -o <OBJECT>")
 endif()
 
+if(${CPU_TYPE} STREQUAL "d9_secure")
+        set(CMAKE_ASM_FLAGS "--specs=nosys.specs")
+        set(CMAKE_C_FLAGS "--specs=nosys.specs") #原ID形式\"888888\"
+        set(CMAKE_C_COMPILE_OBJECT "<CMAKE_C_COMPILER> -O2 -pipe ")
+
+        file(STRINGS "$ENV{CONFIG_FILE_PATH}/defconfig" config_options REGEX "^CONFIG_OS_OPTION_POSIX" ENCODING "UTF-8")
+        foreach(config_option ${config_options})
+                set(CMAKE_C_COMPILE_OBJECT "${CMAKE_C_COMPILE_OBJECT} -D_GNU_SOURCE -D_POSIX_THREADS -D_POSIX_THREAD_PRIORITY_SCHEDULING -D_POSIX_PRIORITY_SCHEDULING -D_POSIX_TIMERS -D_POSIX_CPUTIME -D_POSIX_THREAD_CPUTIME -D_POSIX_MONOTONIC_CLOCK -D_POSIX_TIMEOUTS -D_POSIX_CLOCK_SELECTION -D_POSIX_THREAD_PRIO_PROTECT -D_UNIX98_THREAD_MUTEX_ATTRIBUTES -D_POSIX_READER_WRITER_LOCKS")
+        endforeach()
+
+        set(CMAKE_C_COMPILE_OBJECT "${CMAKE_C_COMPILE_OBJECT} ${STRONG_COMPILE_WARING_FLAG} ${COMPILE_WARING_FLAG} -std=gnu11 -fno-common -fomit-frame-pointer -mcpu=cortex-r5 -mthumb  -D__thumb__ -mfloat-abi=soft -mfpu=fpv4-sp-d16    -fstack-protector-strong  -fdata-sections  -ffunction-sections -fshort-enums  -funsigned-char -DSECUREC_BUFFER_SIZE=32 <FLAGS> <INCLUDES> -c <SOURCE> -o <OBJECT>")
+        set(CMAKE_ASM_COMPILE_OBJECT "<CMAKE_ASM_COMPILER>  -O2  -pipe ${STRONG_COMPILE_WARING_FLAG} ${COMPILE_WARING_FLAG} -std=gnu11 -fno-common -fomit-frame-pointer -mthumb -D__thumb__ -mcpu=cortex-r5 -mfloat-abi=soft -mfpu=fpv4-sp-d16  -Wa,-mimplicit-it=thumb  -fstack-protector-strong  -funsigned-char  <FLAGS> <INCLUDES> -c <SOURCE> -o <OBJECT>")
+endif()
 
 set(CMAKE_LINKER "${TOOLCHAIN_DIR}/arm-none-eabi-ld" CACHE STRING "" FORCE) 
 set(CMAKE_AR "${TOOLCHAIN_DIR}/arm-none-eabi-ar" CACHE STRING "" FORCE) 
diff --git a/config.xml b/config.xml
index 4bc643fa58bf3e1323299847060e7ff6ddf2377a..9f2ab9e49f1ba89585db8bf63a624ef390bbc400 100644
--- a/config.xml
+++ b/config.xml
@@ -197,4 +197,15 @@
             </platform>
         </project>
     </projects>
+    <projects>
+        <project cpu_type="d9_secure">
+            <lib_type>SRE</lib_type>
+            <platform plat_name="cortex_r5">
+                <name>cortex_r5</name>
+                <compile_path_x86>/opt/buildtools/gcc-arm-none-eabi-10-2020-q4-major/bin</compile_path_x86>
+                <compile_path_arm64>/opt/buildtools/gcc-arm-none-eabi-10-2020-q4-major/bin</compile_path_arm64>
+                <kconf_dir>cortex_r5_d9_secure</kconf_dir>
+            </platform>
+        </project>
+    </projects>
 </config>
\ No newline at end of file
diff --git a/demos/d9_secure/CMakeLists.txt b/demos/d9_secure/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..c10cd420365576b48e4f3ab95fa6f660192ad9b7
--- /dev/null
+++ b/demos/d9_secure/CMakeLists.txt
@@ -0,0 +1,54 @@
+cmake_minimum_required(VERSION 3.12)
+project(${APP} LANGUAGES C ASM)
+
+set(HOME_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../..)
+
+set(CMAKE_C_COMPILER ${TOOLCHAIN_PATH}/bin/${TOOLCHAIN_PREFIX}-gcc)
+set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PATH}/bin/${TOOLCHAIN_PREFIX}-g++)
+set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PATH}/bin/${TOOLCHAIN_PREFIX}-gcc)
+set(CMAKE_LINKER ${TOOLCHAIN_PATH}/bin/${TOOLCHAIN_PREFIX}-ld)
+
+set(CMAKE_C_FLAGS "-g -O0 -mthumb -D__thumb__ -mcpu=cortex-r5 -std=gnu11 -fno-common -fomit-frame-pointer -mthumb -mfloat-abi=soft -mfpu=fpv4-sp-d16  -Wa,-mimplicit-it=thumb  -fstack-protector-strong  -funsigned-char -fdata-sections -ffunction-sections -fshort-enums")
+set(CMAKE_CXX_FLAGS "-mthumb -D__thumb__ -mcpu=cortex-r5 -mfloat-abi=soft -mfpu=fpv4-sp-d16  -fno-threadsafe-statics -fno-builtin -DEIGEN_NO_IO=1")
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
+set(CMAKE_ASM_FLAGS ${CMAKE_C_FLAGS})
+set(ldfile "${CMAKE_CURRENT_SOURCE_DIR}/build/d9_secure.ld")
+set(CMAKE_EXE_LINKER_FLAGS "-nostdlib -Wl,-EL -Wl,-d -Wl,-no-enum-size-warning  -u _printf_float -nostartfiles -static -T ${ldfile}")
+
+add_compile_options(
+    -Wno-parentheses
+)
+
+include(${HOME_PATH}/cmake/functions/uniproton_functions.cmake)
+import_kconfig(${HOME_PATH}/build/uniproton_config/config_cortex_r5_${CPU_TYPE}/defconfig)
+
+include_directories(
+    ${CMAKE_CURRENT_SOURCE_DIR}/include
+    ${CMAKE_CURRENT_SOURCE_DIR}/include/arch
+    ${CMAKE_CURRENT_SOURCE_DIR}/include/net
+    ${CMAKE_CURRENT_SOURCE_DIR}/include/utility
+    ${CMAKE_CURRENT_SOURCE_DIR}/config
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    ${CMAKE_CURRENT_SOURCE_DIR}/src/d9_secure
+    ${CMAKE_CURRENT_SOURCE_DIR}/apps
+)
+
+link_directories(${CMAKE_CURRENT_SOURCE_DIR}/libs)
+link_libraries(
+    -Wl,--start-group
+    "${CMAKE_CURRENT_SOURCE_DIR}/libs/libCortexMXsec_c.lib"
+    "${CMAKE_CURRENT_SOURCE_DIR}/libs/libD9_SECURE.a"
+    -Wl,--end-group
+    -lgcc
+)
+
+add_subdirectory(config)
+add_subdirectory(src)
+add_subdirectory(apps)
+
+list(APPEND OBJS $<TARGET_OBJECTS:config>)
+list(APPEND OBJS $<TARGET_OBJECTS:src>)
+list(APPEND OBJS $<TARGET_OBJECTS:apps>)
+
+add_executable(${APP} ${OBJS})
diff --git a/demos/d9_secure/apps/CMakeLists.txt b/demos/d9_secure/apps/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..eb97751f017a56bd0a2ec70613a4ed6c29d73075
--- /dev/null
+++ b/demos/d9_secure/apps/CMakeLists.txt
@@ -0,0 +1,2 @@
+set(SRC main.c)
+add_library(apps OBJECT ${SRC})
\ No newline at end of file
diff --git a/demos/d9_secure/apps/main.c b/demos/d9_secure/apps/main.c
new file mode 100755
index 0000000000000000000000000000000000000000..036e5c90328f53efa1807863531f73a5515282c1
--- /dev/null
+++ b/demos/d9_secure/apps/main.c
@@ -0,0 +1,124 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include <securec.h>
+#include <prt_config.h>
+#include <prt_config_internal.h>
+#include <prt_task.h>
+#include <prt_clk.h>
+#include <prt_hwi.h>
+#include <prt_sys.h>
+#include <prt_tick.h>
+#include <cpu_config.h>
+#include <print.h>
+
+TskHandle g_testTskHandle;
+U8 g_memRegion00[OS_MEM_FSC_PT_SIZE];
+
+void TestTaskEntry()
+{
+    PRT_Printf("Hello, UniProton d9340_secure start!\n");
+    U32 a = 20;
+
+    while (a--)
+    {
+        PRT_ClkDelayMs(500);
+        PRT_Printf("cycle=%llu, tick=%llu\n", PRT_ClkGetCycleCount64(), PRT_TickGetCount());
+    }
+
+    return;
+}
+
+
+U32 OsTestInit(void)
+{
+    U32 ret;
+    U8 ptNo = OS_MEM_DEFAULT_FSC_PT;
+    struct TskInitParam param = {0};
+
+    // create task
+    param.stackAddr = PRT_MemAllocAlign(0, ptNo, 0x2000, MEM_ADDR_ALIGN_016);
+    param.taskEntry = (TskEntryFunc)TestTaskEntry;
+    param.taskPrio = 30;
+    param.name = "TestTask";
+    param.stackSize = 0x2000;
+
+    ret = PRT_TaskCreate(&g_testTskHandle, &param);
+    if (ret)
+    {
+        return ret;
+    }
+
+    ret = PRT_TaskResume(g_testTskHandle);
+    if (ret)
+    {
+        return ret;
+    }
+
+    return OS_OK;
+}
+
+U32 PRT_AppInit(void)
+{
+    U32 ret;
+
+    ret = OsTestInit();
+    if (ret)
+    {
+        return ret;
+    }
+    ret = TestClkStart();
+    if (ret)
+    {
+        return ret;
+    }
+
+    return OS_OK;
+}
+
+U32 PRT_HardDrvInit(void)
+{
+    U32 ret;
+
+    ret = OsHwiInit();
+    if (ret)
+    {
+        return ret;
+    }
+
+    return OS_OK;
+}
+
+void PRT_HardBootInit(void)
+{
+}
+
+S32 main(void)
+{
+    return OsConfigStart();
+}
+
+extern void *__wrap_memset(void *dest, int set, size_t len)
+{
+    if (dest == NULL || len == 0)
+    {
+        return NULL;
+    }
+
+    char *ret = (char *)dest;
+    for (int i = 0; i < len; ++i)
+    {
+        ret[i] = set;
+    }
+    return dest;
+}
+
+extern void *__wrap_memcpy(void *dest, const void *src, size_t size)
+{
+    for (size_t i = 0; i < size; ++i)
+    {
+        *(char *)(dest + i) = *(char *)(src + i);
+    }
+    return dest;
+}
diff --git a/demos/d9_secure/build/build_app.sh b/demos/d9_secure/build/build_app.sh
new file mode 100755
index 0000000000000000000000000000000000000000..8ff68f67bc891e5fa128082265d54e3c54d02408
--- /dev/null
+++ b/demos/d9_secure/build/build_app.sh
@@ -0,0 +1,33 @@
+###################### build boards ######################
+export TOOLCHAIN_PATH=/opt/buildtools/gcc-arm-none-eabi-10-2020-q4-major
+export TOOLCHAIN_PREFIX=arm-none-eabi
+
+SCRIPT_DIR=$(dirname $(realpath $0))
+BOARD_PATH=$(basename $(dirname $SCRIPT_DIR))
+BOARD_PATH=$(basename $(dirname $(dirname $SCRIPT_DIR)))/$BOARD_PATH
+export BOARD_PATH
+
+export CPU_TYPE=d9_secure
+export APP_NAME=uniproton
+
+# export ALL="task-switch task-preempt semaphore-shuffle interrupt-latency deadlock-break message-latency"
+export ALL=$APP_NAME
+
+cp ../config/defconfig ../../../build/uniproton_config/config_cortex_r5_$CPU_TYPE
+sh ./build_static.sh $CPU_TYPE $BOARD_PATH
+
+cmake -S .. -B $APP_NAME \
+        -DAPP:STRING=$APP_NAME \
+        -DTOOLCHAIN_PATH:STRING=$TOOLCHAIN_PATH \
+        -DCPU_TYPE:STRING=$CPU_TYPE \
+        -DTOOLCHAIN_PREFIX:STRING=$TOOLCHAIN_PREFIX \
+
+pushd $APP_NAME && {
+    make $APP_NAME || exit 1
+} && popd
+
+if [ -f $APP_NAME/$APP_NAME ]; then
+    cp "$APP_NAME/$APP_NAME" "$SCRIPT_DIR/$APP_NAME.elf"
+    $TOOLCHAIN_PATH/bin/$TOOLCHAIN_PREFIX-objcopy -O binary "$SCRIPT_DIR/$APP_NAME.elf" "$SCRIPT_DIR/$APP_NAME.bin"
+    $TOOLCHAIN_PATH/bin/$TOOLCHAIN_PREFIX-objdump -D "$SCRIPT_DIR/$APP_NAME.elf" > "$SCRIPT_DIR/$APP_NAME.asm"
+fi
diff --git a/demos/d9_secure/build/build_static.sh b/demos/d9_secure/build/build_static.sh
new file mode 100755
index 0000000000000000000000000000000000000000..77bf6836d82ac0d547d2d9c10b71b1711c892cc1
--- /dev/null
+++ b/demos/d9_secure/build/build_static.sh
@@ -0,0 +1,25 @@
+git clone https://gitee.com/openeuler/libboundscheck.git
+
+cp libboundscheck/include/* ../../../platform/libboundscheck/include
+cp libboundscheck/src/* ../../../platform/libboundscheck/src
+rm -rf libboundscheck
+
+CPU_TYPE=$1
+BOARD_PATH=$2
+
+pushd ./../../../
+python build.py $CPU_TYPE
+
+INC_DIR=$BOARD_PATH/include
+LIB_DIR=$BOARD_PATH/libs
+
+[ -d $LIB_DIR ] || mkdir $LIB_DIR
+cp output/UniProton/lib/$CPU_TYPE/*.a $LIB_DIR
+cp output/libboundscheck/lib/$CPU_TYPE/*.lib $LIB_DIR
+
+[ -d $INC_DIR ] || mkdir $INC_DIR
+cp output/libboundscheck/lib/$CPU_TYPE/*.h $INC_DIR
+cp -r src/include/uapi/* $INC_DIR
+cp build/uniproton_config/config_cortex_r5_$CPU_TYPE/prt_buildef.h $INC_DIR/
+
+popd
diff --git a/demos/d9_secure/build/clean.sh b/demos/d9_secure/build/clean.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3dd95986d6c62297a9f899a268c7d58676bc9ce7
--- /dev/null
+++ b/demos/d9_secure/build/clean.sh
@@ -0,0 +1,29 @@
+BUILD_PATH=$(pwd)
+HOME_PATH=$(pwd)/../../..
+
+echo "Delete all files (*.asm *.bin *.elf) in "$BUILD_PATH" ..."
+rm -f "$BUILD_PATH"/*.asm
+rm -f "$BUILD_PATH"/*.bin
+rm -f "$BUILD_PATH"/*.elf
+rm -rf "$BUILD_PATH"/uniproton/
+
+echo "Delete the build directories ..."
+rm -rf "$BUILD_PATH"/bsp
+rm -rf "$BUILD_PATH"/apps
+rm -rf "$BUILD_PATH"/components
+
+echo "Delete "$BUILD_PATH"/libs/ file ..."
+rm -f "$BUILD_PATH"/../libs/*
+
+echo "Delete "$BUILD_PATH"/include directories ..."
+rm -f "$BUILD_PATH"/../include/* -rf
+
+echo "Delete "$HOME_PATH"/build directories ..."
+rm -rf "$HOME_PATH"/build/logs
+rm -rf "$HOME_PATH"/build/output
+rm -rf "$HOME_PATH"/build/uniproton_config/*/prt_buildef.h
+
+echo "Delete "$HOME_PATH"/output directories ..."
+rm -rf "$HOME_PATH"/output
+
+echo "Cleanup is complete!"
diff --git a/demos/d9_secure/build/d9_secure.ld b/demos/d9_secure/build/d9_secure.ld
new file mode 100755
index 0000000000000000000000000000000000000000..48a4b7fbf2d8fcdc0d8cb615213f54ac98d72c01
--- /dev/null
+++ b/demos/d9_secure/build/d9_secure.ld
@@ -0,0 +1,154 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x140000;
+
+    _start = .;
+
+    /* text/read-only data */
+    .text : {
+        __text_start = .;
+        KEEP(*(.text.boot.vectab1))
+        KEEP(*(.text.boot.vectab2))
+        KEEP(*(.text.boot))
+        *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
+    }
+
+    .interp : { *(.interp) }
+    .hash : { *(.hash) }
+    .dynsym : { *(.dynsym) }
+    .dynstr : { *(.dynstr) }
+    .rel.text : { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+    .rela.text : { *(.rela.text) *(.rela.gnu.linkonce.t*) }
+    .rel.data : { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+    .rela.data : { *(.rela.data) *(.rela.gnu.linkonce.d*) }
+    .rel.rodata : { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
+    .rela.rodata : { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
+    .rel.got : { *(.rel.got) }
+    .rela.got : { *(.rela.got) }
+    .rel.ctors : { *(.rel.ctors) }
+    .rela.ctors : { *(.rela.ctors) }
+    .rel.dtors : { *(.rel.dtors) }
+    .rela.dtors : { *(.rela.dtors) }
+    .rel.init : { *(.rel.init) }
+    .rela.init : { *(.rela.init) }
+    .rel.fini : { *(.rel.fini) }
+    .rela.fini : { *(.rela.fini) }
+    .rel.bss : { *(.rel.bss) }
+    .rela.bss : { *(.rela.bss) }
+    .rel.plt : { *(.rel.plt) }
+    .rela.plt : { *(.rela.plt) }
+    .init : { *(.init) } =0x9090
+    .plt : { *(.plt) }
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+    __exidx_end = .;
+
+    .dummy_post_text : {
+        __text_end = .;
+    }
+
+    .rodata : ALIGN(4) {
+        __rodata_start = .;
+        __fault_handler_table_start = .;
+        KEEP(*(.rodata.fault_handler_table))
+        __fault_handler_table_end = .;
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+    }
+
+    /*
+     * extra linker scripts tend to insert sections just after .rodata,
+     * so we want to make sure this symbol comes after anything inserted above,
+     * but not aligned to the next section necessarily.
+     */
+    .dummy_post_rodata : {
+        __rodata_end = .;
+    }
+
+    .data : ALIGN(4) {
+        /* writable data  */
+        __data_start_rom = .;
+        /* in one segment binaries, the rom data address is on top of the ram data address */
+        __data_start = .;
+        *(.data .data.* .gnu.linkonce.d.*)
+    }
+
+    .ctors : ALIGN(4) {
+        __ctor_list = .;
+        KEEP(*(.ctors .init_array))
+        __ctor_end = .;
+    }
+    .dtors : ALIGN(4) {
+        __dtor_list = .;
+        KEEP(*(.dtors .fini_array))
+        __dtor_end = .;
+    }
+    .got : { *(.got.plt) *(.got) }
+    .dynamic : { *(.dynamic) }
+
+    /*
+     * extra linker scripts tend to insert sections just after .data,
+     * so we want to make sure this symbol comes after anything inserted above,
+     * but not aligned to the next section necessarily.
+     */
+    .dummy_post_data : {
+        __data_end = .;
+    }
+
+    .nocache : ALIGN(1024) {
+        _nocacheable_start = .;
+        *(.nocache)
+        . = ALIGN(1024);
+        _nocacheable_end = .;
+    }
+
+    /* uninitialized data (in same segment as writable data) */
+    .bss : ALIGN(4) {
+        KEEP(*(.bss.prebss.*))
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    }
+
+    /* os data stack */
+    .os.data : ALIGN(4) {
+        *(.os.data)
+    }
+
+    _end = .;
+
+    .heap : ALIGN(4) {
+        _heap_start = .;
+        *(.heap)
+    }
+
+    . = 0x140000 + 0x80000;
+
+    _heap_end = .;
+
+    _end_of_ram = .;
+
+    /* Add a labelize section of ext memory start addr, which could
+     * be locate to extra linker script */
+    .ext.mem (NOLOAD) : {
+        . = ALIGN(4);
+        __ext_mem_start = .;
+        *(.ext.mem .ext.mem.*)
+        . = ALIGN(4);
+        __ext_mem_end = .;
+
+    }
+
+    /* Strip unnecessary stuff */
+    /DISCARD/ : { *(.comment .note .eh_frame) }
+}
+
diff --git a/demos/d9_secure/config/CMakeLists.txt b/demos/d9_secure/config/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..ab9f478fa5d22fec77aacc0ca17322566086ef75
--- /dev/null
+++ b/demos/d9_secure/config/CMakeLists.txt
@@ -0,0 +1,2 @@
+set(SRCS prt_config.c)
+add_library(config OBJECT ${SRCS})
diff --git a/demos/d9_secure/config/defconfig b/demos/d9_secure/config/defconfig
new file mode 100755
index 0000000000000000000000000000000000000000..302e367c7a4537a078e83c7b4b46f50cb2cf58a4
--- /dev/null
+++ b/demos/d9_secure/config/defconfig
@@ -0,0 +1,154 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# UniProton Configuration
+#
+
+#
+# Arch Modules Configuration
+#
+CONFIG_OS_ARCH_ARMV7_R=y
+# CONFIG_OS_OPTION_GUARD_STACK=y
+CONFIG_OS_ARCH_ABT_STACK_SIZE=128
+CONFIG_OS_ARCH_IRQ_STACK_SIZE=512
+CONFIG_OS_ARCH_FIQ_STACK_SIZE=256
+CONFIG_OS_ARCH_SYS_STACK_SIZE=2048
+CONFIG_OS_ARCH_UND_STACK_SIZE=128
+CONFIG_OS_ARCH_SVC_STACK_SIZE=4096
+
+#
+# ARM7-R Sepecfic Configuration
+#
+CONFIG_INTERNAL_OS_D9_SECURE=y
+CONFIG_INTERNAL_OS_PLATFORM_CORTEX_R5=y
+
+#
+# Generic Configuration
+#
+CONFIG_OS_HARDWARE_PLATFORM="OS_CORTEX_R5"
+CONFIG_OS_CPU_TYPE="OS_D9_SECURE"
+CONFIG_OS_MAX_CORE_NUM=1
+CONFIG_OS_THIS_CORE=0
+CONFIG_INTERNAL_OS_BYTE_ORDER_LE=y
+CONFIG_OS_BYTE_ORDER="OS_LITTLE_ENDIAN"
+CONFIG_OS_CACHE_LINE_SIZE=32
+
+#
+# Core Modules Configuration
+#
+
+#
+# IPC Modules Configuration
+#
+
+#
+# Event feature configuration
+#
+CONFIG_OS_OPTION_EVENT=y
+CONFIG_OS_OPTION_QUEUE=y
+
+#
+# Semaphore feature configuration
+#
+CONFIG_OS_OPTION_BIN_SEM=y
+CONFIG_OS_OPTION_SEM_RECUR_PV=y
+CONFIG_OS_OPTION_SEM_PRIOR=y
+
+#
+# Kernel Modules Configuration
+#
+
+#
+# IRQ Modules Configuration
+#
+# CONFIG_OS_OPTION_HWI_COMBINE is not set
+CONFIG_INTERNAL_OS_GIC_VER="gicv600"
+CONFIG_OS_GIC_VER=2
+CONFIG_GIC_DIST_BASE=0xf5411000U
+
+CONFIG_OS_OPTION_HWI_PRIORITY=y
+CONFIG_OS_OPTION_HWI_ATTRIBUTE=y
+# CONFIG_OS_OPTION_HWI_MAX_NUM_CONFIG is not set
+
+#
+# Exc Modules Configuration
+CONFIG_INTERNAL_OS_SCHEDULE_SINGLE_CORE_BY_CCODE=y
+# CONFIG_OS_OPTION_SYS_TIME_USR=y
+#
+
+#
+# Task module Configuration
+#
+CONFIG_OS_OPTION_TASK=y
+
+#
+# TASK features configuration
+#
+CONFIG_OS_OPTION_TASK_DELETE=y
+CONFIG_OS_OPTION_TASK_SUSPEND=y
+CONFIG_OS_OPTION_TASK_INFO=y
+CONFIG_OS_OPTION_TASK_YIELD=y
+CONFIG_OS_TSK_PRIORITY_HIGHEST=0
+CONFIG_OS_TSK_PRIORITY_LOWEST=31
+CONFIG_OS_TSK_NUM_OF_PRIORITIES=32
+CONFIG_OS_TSK_CORE_BYTES_IN_PID=2
+
+#
+# Timer Modules Configuration
+#
+CONFIG_INTERNAL_OS_SWTMR=y
+
+#
+# MM Modules Configuration
+#
+
+#
+# OM Modules Configuration
+#
+CONFIG_OS_OPTION_CPUP=y
+
+#
+# CPUP features configuration
+#
+CONFIG_INTERNAL_OS_CPUP_THREAD=y
+CONFIG_OS_OPTION_CPUP_WARN=y
+
+#
+# Error Report Module Configuration
+#
+
+#
+# Hook feature configuration
+#
+
+#
+# Debug configuration
+#
+# CONFIG_OS_GDB_STUB=y
+# CONFIG_OS_GDB_STUB_UART=y
+# CONFIG_OS_OPTION_COREDUMP=y
+
+#
+# security Modules Configuration
+#
+CONFIG_OS_OPTION_RND=y
+
+CONFIG_OS_OPTION_POSIX=y
+CONFIG_OS_OPTION_POSIX_SIGNAL=y
+CONFIG_OS_POSIX_TYPE_NEWLIB=y
+CONFIG_OS_POSIX_SET_TZDST=y
+CONFIG_OS_OPTION_LOCALE=y
+
+# CONFIG_OS_OPTION_RR_SCHED=y
+# CONFIG_OS_OPTION_RR_SCHED_IRQ_TIME_DISCOUNT=y
+
+#
+# Openamp Modules Configuration
+#
+# CONFIG_OS_OPTION_OPENAMP=y
+# CONFIG_OS_OPTION_RSC_TABLE=y
+#
+
+#
+# Utility Modules Configuration
+#
+
diff --git a/demos/d9_secure/config/prt_config.c b/demos/d9_secure/config/prt_config.c
new file mode 100755
index 0000000000000000000000000000000000000000..52be6de0017282387e72b7e5ac7c8d060d7c14e4
--- /dev/null
+++ b/demos/d9_secure/config/prt_config.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-12-22
+ * Description: UniProton的初始化C文件。
+ */
+#include "prt_config_internal.h"
+#include "cpu_config.h"
+
+#if (defined(OS_OPTION_SMP) || defined(OS_ARMV8))
+RESET_SEC_DATA U32 g_cfgPrimaryCore = OS_SYS_CORE_PRIMARY;
+#endif
+
+OS_SEC_ALW_INLINE INLINE void OsConfigAddrSizeGet(uintptr_t addr, uintptr_t size,
+                                                  uintptr_t *destAddr, uintptr_t *destSize)
+{
+    *destAddr = addr;
+    *destSize = size;
+}
+
+U32 OsMemConfigReg(void)
+{
+    U32 ret;
+
+    ret = OsFscMemInit(OS_MEM_FSC_PT_ADDR, OS_MEM_FSC_PT_SIZE);
+    if (ret != OS_OK) {
+        return ret;
+    }
+
+    return OS_OK;
+}
+
+U32 OsMemDefPtInit(void)
+{
+    return OS_OK;
+}
+
+U32 OsMemConfigInit(void)
+{
+    /* 系统默认FSC内存分区初始化 */
+    return OsMemDefPtInit();
+}
+
+U32 OsSystemReg(void)
+{
+    struct SysModInfo sysModInfo;
+
+    sysModInfo.systemClock = OS_SYS_CLOCK;
+    sysModInfo.cpuType = OS_CPU_TYPE;
+    sysModInfo.sysTimeHook = OS_SYS_TIME_HOOK;
+#if defined(OS_OPTION_SMP)
+    sysModInfo.coreRunNum = OS_SYS_CORE_RUN_NUM;
+    sysModInfo.coreMaxNum = OS_SYS_CORE_MAX_NUM;
+    sysModInfo.corePrimary = OS_SYS_CORE_PRIMARY;
+#endif
+#if defined(OS_OPTION_HWI_MAX_NUM_CONFIG)
+    sysModInfo.hwiMaxNum = OS_HWI_MAX_NUM_CONFIG;
+#endif
+
+    return OsSysRegister(&sysModInfo);
+}
+
+#if (OS_INCLUDE_SEM == YES)
+U32 OsSemConfigReg(void)
+{
+    struct SemModInfo semModInfo;
+
+    semModInfo.maxNum = OS_SEM_MAX_SUPPORT_NUM;
+    return OsSemRegister(&semModInfo);
+
+}
+#endif
+
+#if (OS_INCLUDE_TASK == YES)
+void OsTaskInfoSet(struct TskModInfo *taskModInfo)
+{
+    taskModInfo->maxNum = OS_TSK_MAX_SUPPORT_NUM;
+    taskModInfo->defaultSize = OS_TSK_DEFAULT_STACK_SIZE;
+    taskModInfo->idleStackSize = OS_TSK_IDLE_STACK_SIZE;
+    taskModInfo->magicWord = WORD_PACK((U32)OS_TSK_STACK_MAGIC_WORD);
+}
+#else
+#error "OS_INCLUDE_TASK MUST BE YES! The SWI has been cut out，the task can not cut out."
+#endif
+
+U32 OsHookConfigReg(void)
+{
+    struct HookModInfo hookModInfo;
+
+    hookModInfo.maxNum[OS_HOOK_HWI_ENTRY] = OS_HOOK_HWI_ENTRY_NUM;
+    hookModInfo.maxNum[OS_HOOK_HWI_EXIT] = OS_HOOK_HWI_EXIT_NUM;
+    hookModInfo.maxNum[OS_HOOK_TSK_CREATE] = OS_HOOK_TSK_CREATE_NUM;
+    hookModInfo.maxNum[OS_HOOK_TSK_DELETE] = OS_HOOK_TSK_DELETE_NUM;
+    hookModInfo.maxNum[OS_HOOK_TSK_SWITCH] = OS_HOOK_TSK_SWITCH_NUM;
+    hookModInfo.maxNum[OS_HOOK_IDLE_PERIOD] = OS_HOOK_IDLE_NUM;
+
+    return OsHookRegister(&hookModInfo);
+}
+
+U32 OsSysConfigReg(void)
+{
+    U32 ret;
+
+    ret = OsSystemReg();
+    if (ret != OS_OK) {
+        return ret;
+    }
+    return OS_OK;
+}
+
+#if (OS_INCLUDE_TICK == YES)
+U32 OsTickConfigReg(void)
+{
+    struct TickModInfo tickModInfo;
+
+    tickModInfo.tickPerSecond = OS_TICK_PER_SECOND;
+    tickModInfo.tickPriority = 0;
+
+    return OsTickRegister(&tickModInfo);
+}
+#endif
+
+#if (OS_INCLUDE_TASK == YES)
+U32 OsTskConfigReg(void)
+{
+    struct TskModInfo taskModInfo;
+    OsTaskInfoSet(&taskModInfo);
+    return OsTskRegister(&taskModInfo);
+}
+#endif
+
+#if (OS_INCLUDE_QUEUE == YES)
+U32 OsQueueConfigReg(void)
+{
+    return OsQueueRegister(OS_QUEUE_MAX_SUPPORT_NUM);
+}
+#endif
+
+#if (OS_INCLUDE_CPUP == YES)
+U32 OsCpupConfigReg(void)
+{
+    struct CpupModInfo cpupModInfo;
+
+    cpupModInfo.cpupWarnFlag = (bool)OS_CONFIG_CPUP_WARN;
+    cpupModInfo.sampleTime = OS_CPUP_SAMPLE_INTERVAL;
+    cpupModInfo.warn = OS_CPUP_SHORT_WARN;
+    cpupModInfo.resume = OS_CPUP_SHORT_RESUME;
+
+    return OsCpupRegister(&cpupModInfo);
+}
+#endif
+
+#if (OS_INCLUDE_TICK_SWTMER == YES)
+U32 OsSwTmrConfigInit(void)
+{
+    return OsSwTmrInit(OS_TICK_SWITIMER_MAX_NUM);
+}
+#endif
+
+#if (OS_INCLUDE_CPUP == YES)
+#if (OS_INCLUDE_TICK == NO)
+#error "OS_INCLUDE_CPUP depend on OS_INCLUDE_TICK!"
+#endif
+U32 OsCpupConfigInit(void)
+{
+    U32 ret;
+
+    ret = OsCpupInit();
+    if (ret != OS_OK) {
+        return ret;
+    }
+
+    if (OS_CONFIG_CPUP_WARN == YES) {
+#if defined(OS_OPTION_CPUP_WARN)
+        OsCpupWarnInit();
+#else
+        return OS_ERRNO_SYS_NO_CPUP_WARN;
+#endif
+    }
+    return OS_OK;
+}
+#endif
+
+#if (OS_INCLUDE_SEM == YES)
+U32 OsSemConfigInit(void)
+{
+    return OsSemInit();
+}
+#endif
+
+#if (OS_INCLUDE_TASK == YES)
+U32 OsTskConfigInit(void)
+{
+    return OsTskInit();
+}
+#endif
+
+#if defined(OS_OPTION_SMP)
+INIT_SEC_L4_TEXT U32 OsSchedRunQueConfigInit(void)
+{
+    OsSchedRunQueInit();
+    return OS_OK;
+}
+#endif
+
+static U32 OsHwiConfigReg(void)
+{
+#if (OS_INCLUDE_GIC_BASE_ADDR_CONFIG == YES)
+    U32 ret;
+    ret = OsGicConfigRegister((uintptr_t)OS_GIC_BASE_ADDR, (uintptr_t)OS_GICR_OFFSET, (uintptr_t)OS_GICR_STRIDE);
+    if (ret != OS_OK) {
+        return ret;
+    }
+#endif
+    return OS_OK;
+}
+
+/* 系统初始化注册表 */
+struct OsModuleConfigInfo g_moduleConfigTab[] = {
+    /* {模块号， 模块注册函数， 模块初始化函数} */
+    {OS_MID_SYS, {OsSysConfigReg, NULL}},
+    {OS_MID_MEM, {OsMemConfigReg, OsMemConfigInit}},
+    {OS_MID_HWI, {OsHwiConfigReg, OsHwiConfigInit}},
+    {OS_MID_HARDDRV, {NULL, PRT_HardDrvInit}},
+    {OS_MID_HOOK, {OsHookConfigReg, OsHookConfigInit}},
+    {OS_MID_EXC, {NULL, OsExcConfigInit}},
+#if defined(OS_OPTION_SMP)
+    {OS_MID_SCHED, {NULL, OsSchedRunQueConfigInit}},
+#endif
+#if (OS_INCLUDE_TASK == YES)
+    {OS_MID_TSK, {OsTskConfigReg, OsTskConfigInit}},
+#endif
+#if (OS_INCLUDE_TICK == YES)
+    {OS_MID_TICK, {OsTickConfigReg, OsTickConfigInit}},
+#endif
+
+#if (OS_INCLUDE_TICK_SWTMER == YES)
+    {OS_MID_SWTMR, {NULL, OsSwTmrConfigInit}},
+#endif
+
+#if (OS_INCLUDE_CPUP == YES)
+    {OS_MID_CPUP, {OsCpupConfigReg, OsCpupConfigInit}},
+#endif
+#if (OS_INCLUDE_SEM == YES)
+    {OS_MID_SEM, {OsSemConfigReg, OsSemConfigInit}},
+#endif
+#if (OS_INCLUDE_QUEUE == YES)
+    {OS_MID_QUEUE, {OsQueueConfigReg, OsQueueConfigInit}},
+#endif
+    {OS_MID_APP, {NULL, PRT_AppInit}},
+
+    {OS_MID_BUTT, {NULL, NULL}},
+};
+
+/*
+ * 描述：OS模块注册、初始化运行函数
+ */
+U32 OsModuleConfigRun(enum OsinitPhaseId initPhaseId, U32 initPhase)
+{
+    U32 idx = 0;
+    U32 ret = OS_OK;
+    while (g_moduleConfigTab[idx].moudleId != OS_MID_BUTT) {
+        if (g_moduleConfigTab[idx].moudleConfigFunc[initPhaseId] == NULL) {
+            idx++;
+            continue;
+        }
+        ret = g_moduleConfigTab[idx].moudleConfigFunc[initPhaseId]();
+        if (ret != OS_OK) {
+            break;
+        }
+        idx++;
+    }
+    return ret;
+}
+U32 OsRegister(void)
+{
+    return OsModuleConfigRun(OS_REGISTER_ID, OS_REGISTER_PHASE);
+}
+
+/*
+ * 描述：OsInitialize阶段
+ */
+U32 OsInitialize(void)
+{
+    return OsModuleConfigRun(OS_INIT_ID, OS_INITIALIZE_PHASE);
+}
+
+/*
+ * 描述：OsStart阶段
+ */
+U32 OsStart(void)
+{
+    U32 ret;
+
+#if (OS_INCLUDE_TICK == YES)
+    /* 表示系统在进行启动阶段，匹配MOUDLE_ID之后，标记进入TICK模块的启动 */
+    ret = OsTickStart();
+    if (ret != OS_OK) {
+        return ret;
+    }
+#endif
+
+#if (OS_INCLUDE_TASK == YES)
+    /* 表示系统在进行启动阶段，匹配MOUDLE_ID之后，标记进入任务模块的启动 */
+    ret = OsActivate();
+#else
+    ret = OS_OK;
+#endif
+
+    return ret;
+}
+
+#if defined(OS_OPTION_SMP)
+INIT_SEC_L4_TEXT U32 OsSlaveTskRecycleIPCInit(void)
+{
+    U32 ret;
+    ret = PRT_HwiEnable(OS_SMP_MC_CORE_IPC_SGI);
+    if (ret != OS_OK) {
+        return ret;
+    }
+    return ret;
+}
+
+INIT_SEC_L4_TEXT U32 OsSmpPreInit(void)
+{
+    U32 ret;
+    if(OsGetCoreID() != OS_SYS_CORE_PRIMARY) {
+        ret = OsModuleInit();
+        if(ret != OS_OK) {
+            return ret;
+        }
+
+        ret = OsCoreTimerSecondaryInit();
+        if (ret != OS_OK) {
+            return ret;
+        }
+
+        ret = OsSlaveTskRecycleIPCInit();
+        if (ret != OS_OK) {
+            return ret;
+        }
+
+        ret = OsStart();
+        if(ret != OS_OK) {
+            return ret;
+        }
+
+        /* 正常情况执行不应该到达这 */
+        return OS_FAIL;
+    }
+    return OS_OK;
+
+}
+#endif
+
+S32 OsConfigStart(void)
+{
+    U32 ret;
+
+    #if defined(OS_OPTION_SMP)
+        ret = OsSmpPreInit();
+        if(ret != OS_OK) {
+            return (S32)ret;
+        }
+    #endif
+
+    OsHwInit();
+
+    /* OS模块注册 */
+    ret = OsRegister();
+    if (ret != OS_OK) {
+        return (S32)ret;
+    }
+
+    /* OS模块初始化 */
+    ret = OsInitialize();
+    if (ret != OS_OK) {
+        return (S32)ret;
+    }
+
+    /* OS启动调度 */
+    ret = OsStart();
+    if (ret != OS_OK) {
+        return (S32)ret;
+    }
+
+    /* Execution should not reach this point */
+    return (S32)OS_ERROR;
+}
diff --git a/demos/d9_secure/config/prt_config.h b/demos/d9_secure/config/prt_config.h
new file mode 100755
index 0000000000000000000000000000000000000000..afd18394e156229d8584ce38bc8e10cec2de076f
--- /dev/null
+++ b/demos/d9_secure/config/prt_config.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-12-22
+ * Description: UniProton配置头文件，裁剪开关和配置项。
+ */
+#ifndef PRT_CONFIG_H
+#define PRT_CONFIG_H
+
+#include "prt_buildef.h"
+#include "prt_typedef.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif
+#endif
+
+/* ***************************** 配置系统基本信息 ******************************* */
+/* 芯片主频 */
+#define OS_SYS_CLOCK                                    24000000
+/* 用户注册的获取系统时间的函数*/
+#define OS_SYS_TIME_HOOK                                NULL
+/* 实际运行的核数，单位：个 */
+#define OS_SYS_CORE_RUN_NUM                             1
+/* 最大可支持的核数，单位：个 */
+#define OS_SYS_CORE_MAX_NUM                             1
+/* 主核ID */
+#define OS_SYS_CORE_PRIMARY                             0
+
+/* ***************************** 中断模块配置 ************************** */
+/* 硬中断最大支持个数 */
+#define OS_HWI_MAX_NUM_CONFIG                           275
+
+/* ***************************** 配置Tick中断模块 *************************** */
+/* Tick中断模块裁剪开关 */
+#define OS_INCLUDE_TICK                                 YES
+/* Tick中断时间间隔，tick处理时间不能超过1/OS_TICK_PER_SECOND(s) */
+#define OS_TICK_PER_SECOND                              1000
+
+/* ***************************** 配置定时器模块 ***************************** */
+/* 基于TICK的软件定时器裁剪开关 */
+#define OS_INCLUDE_TICK_SWTMER                          YES
+/* 基于TICK的软件定时器最大个数 */
+#define OS_TICK_SWITIMER_MAX_NUM                        32
+
+/* ***************************** 配置任务模块 ******************************* */
+/* 任务模块裁剪开关 */
+#define OS_INCLUDE_TASK                                 YES
+/* 最大支持的任务数,最大共支持254个 */
+#define OS_TSK_MAX_SUPPORT_NUM                          64
+/* 缺省的任务栈大小 */
+#define OS_TSK_DEFAULT_STACK_SIZE                       0x1000
+/* IDLE任务栈的大小 */
+#define OS_TSK_IDLE_STACK_SIZE                          0x1000
+/* 任务栈初始化魔术字，默认是0xCA，只支持配置一个字节 */
+#define OS_TSK_STACK_MAGIC_WORD                         0xCA
+
+/* ***************************** 配置CPU占用率及CPU告警模块 **************** */
+/* CPU占用率模块裁剪开关 */
+#define OS_INCLUDE_CPUP                                 NO
+/* 采样时间间隔(单位tick)，若其值大于0，则作为采样周期，否则两次调用PRT_CpupNow或PRT_CpupThread间隔作为周期 */
+#define OS_CPUP_SAMPLE_INTERVAL                         10
+/* CPU占用率告警动态配置项 */
+#define OS_CONFIG_CPUP_WARN                             NO
+/* CPU占用率告警阈值(精度为万分比) */
+#define OS_CPUP_SHORT_WARN                              8500
+/* CPU占用率告警恢复阈值(精度为万分比) */
+#define OS_CPUP_SHORT_RESUME                            7500
+
+/* ***************************** 配置内存管理模块 ************************** */
+/* 用户可以创建的最大分区数，取值范围[0,253] */
+#define OS_MEM_MAX_PT_NUM                               200
+/* 私有FSC内存分区起始地址 */
+#define OS_MEM_FSC_PT_ADDR                              (uintptr_t)&g_memRegion00[0]
+/* 私有FSC内存分区大小 */
+#define OS_MEM_FSC_PT_SIZE                              0x40000
+
+/* ***************************** 配置信号量管理模块 ************************* */
+/* 信号量模块裁剪开关 */
+#define OS_INCLUDE_SEM                                  YES
+
+/* 最大支持的信号量数 */
+#define OS_SEM_MAX_SUPPORT_NUM                          20
+
+/* ***************************** 配置队列模块 ******************************* */
+/* 队列模块裁剪开关 */
+#define OS_INCLUDE_QUEUE                                YES
+/* 最大支持的队列数,范围(0,0xFFFF] */
+#define OS_QUEUE_MAX_SUPPORT_NUM                        10
+
+/* ************************* 钩子模块配置 *********************************** */
+/* 硬中断进入钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_HWI_ENTRY_NUM                           5
+/* 硬中断退出钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_HWI_EXIT_NUM                            5
+/* 任务创建钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_TSK_CREATE_NUM                          1
+/* 任务删除钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_TSK_DELETE_NUM                          1
+/* 任务切换钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_TSK_SWITCH_NUM                          8
+/* IDLE钩子最大支持个数, 范围[0, 255] */
+#define OS_HOOK_IDLE_NUM                                4
+
+/* ************************* GIC模块配置 *********************************** */
+/* GIC地址可配置开关 */
+#define OS_INCLUDE_GIC_BASE_ADDR_CONFIG                 YES
+/* GIC基地址配置 */
+#define OS_GIC_BASE_ADDR                                0xF5411000U
+/* GICR相对于GIC基地址偏移量配置 这个D9 secure核用不到*/
+#define OS_GICR_OFFSET                                  0x20000U
+/* GICR核间偏移量配置  这个D9 secure核用不到 */
+#define OS_GICR_STRIDE                                  0x20000U
+
+extern U8 g_memRegion00[];
+
+#if defined(OS_OPTION_SMP)
+#error "目前不支持多核"
+#endif
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+#endif /* PRT_CONFIG_H */
diff --git a/demos/d9_secure/config/prt_config_internal.h b/demos/d9_secure/config/prt_config_internal.h
new file mode 100755
index 0000000000000000000000000000000000000000..4cd8c72979cca115a50a3f5aee35fdfec6e661a1
--- /dev/null
+++ b/demos/d9_secure/config/prt_config_internal.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-12-22
+ * Description: UniProton配置私有文件。
+ */
+#ifndef PRT_CONFIG_INTERNAL_H
+#define PRT_CONFIG_INTERNAL_H
+
+#include <stdint.h>
+#include "prt_config.h"
+#include "prt_sys.h"
+#include "prt_task.h"
+#include "prt_sem.h"
+#include "prt_tick.h"
+#include "prt_exc.h"
+#include "prt_cpup.h"
+#include "prt_mem.h"
+#include "prt_hook.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+#define WORD_PACK(val) (((val) << 24) | ((val) << 16) | ((val) << 8) | (val))
+
+/* UniProton模块注册函数的声明 */
+extern U32 OsFscMemInit(uintptr_t addr, U32 size);
+extern U32 OsSysRegister(struct SysModInfo *modInfo);
+extern U32 OsTickRegister(struct TickModInfo *modInfo);
+extern U32 OsTskRegister(struct TskModInfo *modInfo);
+extern U32 OsCpupRegister(struct CpupModInfo *modInfo);
+extern U32 OsSemRegister(const struct SemModInfo *modInfo);
+extern U32 OsHookRegister(struct HookModInfo *modInfo);
+
+extern U32 OsHwiConfigInit(void);
+extern U32 OsTickConfigInit(void);
+extern U32 OsTskInit(void);
+extern U32 OsCpupInit(void);
+extern void OsCpupWarnInit(void);
+extern U32 OsExcConfigInit(void);
+extern U32 OsSemInit(void);
+extern U32 OsHookConfigInit(void);
+
+/* UniProton系统启动相关函数的声明 */
+extern void OsHwInit(void);
+extern U32 OsActivate(void);
+extern U32 OsTickStart(void);
+extern U32 PRT_HardDrvInit(void);
+extern void PRT_HardBootInit(void);
+extern U32 PRT_AppInit(void);
+
+extern U32 OsQueueRegister(U16 maxQueue);
+extern U32 OsQueueConfigInit(void);
+extern U32 OsGicConfigRegister(uintptr_t gicdBase, uintptr_t gicrOffset, uintptr_t gicrStride);
+
+S32 OsConfigStart(void);
+
+#if (OS_INCLUDE_TICK_SWTMER == YES)
+extern U32 OsSwTmrInit(U32 maxTimerNum);
+#endif
+
+enum OsinitPhaseId {
+    OS_REGISTER_ID = 0,
+    OS_INIT_ID,
+    OS_MOUDLE_CONFIG
+};
+typedef U32 (*ConfigInitFunc)(void);
+struct OsModuleConfigInfo {
+    enum MoudleId moudleId;
+    ConfigInitFunc moudleConfigFunc[OS_MOUDLE_CONFIG];
+};
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+#endif /* PRT_CONFIG_INTERNAL_H */
diff --git a/demos/d9_secure/libs/.keep b/demos/d9_secure/libs/.keep
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/demos/d9_secure/readme.txt b/demos/d9_secure/readme.txt
new file mode 100755
index 0000000000000000000000000000000000000000..8695b7f4f6632f96a2aba2d99c02bd95aa7e9764
--- /dev/null
+++ b/demos/d9_secure/readme.txt
@@ -0,0 +1,7 @@
+本目录下放置的是UniProton实时部分版本。
+
+├─bsp             # 提供的板级驱动与OS对接；
+├─build           # 提供编译脚本编译出最终镜像；
+├─config          # 配置选项，供用户调整运行时参数；
+├─include         # UniProton实时部分提供的编程接口API；
+└─libs            # UniProton实时部分的静态库，build目录中的makefile示例已经将头文件和静态库的引用准备好，应用可直接使用；
diff --git a/demos/d9_secure/src/CMakeLists.txt b/demos/d9_secure/src/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..51e1df538d1185dc799bbea08a046b777a0497f4
--- /dev/null
+++ b/demos/d9_secure/src/CMakeLists.txt
@@ -0,0 +1,5 @@
+file(GLOB C_SRCS    "*.c"
+                    "*.S")
+
+set(SRCS ${C_SRCS})
+add_library(src OBJECT ${SRCS})
\ No newline at end of file
diff --git a/demos/d9_secure/src/armv7_r.h b/demos/d9_secure/src/armv7_r.h
new file mode 100755
index 0000000000000000000000000000000000000000..db3a5a984a14386add1ae2303a93a210e73ea6ba
--- /dev/null
+++ b/demos/d9_secure/src/armv7_r.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version：armv7-a/r定义
+ */
+
+#ifndef ARMV7_R_H
+#define ARMV7_R_H
+
+#include <prt_buildef.h>
+
+/* PSR */
+#define PSR_USR_MODE           0x00000010u
+#define PSR_FIQ_MODE           0x00000011u
+#define PSR_IRQ_MODE           0x00000012u
+#define PSR_SVC_MODE           0x00000013u
+#define PSR_ABT_MODE           0x00000017u
+#define PSR_UNDEF_MODE         0x0000001Bu
+#define PSR_HYP_MODE           0x0000001Au
+#define PSR_SYS_MODE           0x0000001Fu
+#define PSR_MODE_MASK          0x0000001Fu
+
+#define PSR_F_BIT               0x00000040u
+#define PSR_I_BIT               0x00000080u
+#define PSR_A_BIT               0x00000100u
+
+#define PSR_T_ARM           0x00000000u
+#define PSR_T_THUMB         0x00000020u
+
+#define PSR_INT_DISABLE     (PSR_I_BIT | PSR_F_BIT)
+
+/* MPIDR field defines */
+#define MPIDR_CPUID_MASK    0x000000FFu
+
+#define ICACHE              2               //The old value is 1
+#define DCACHE              1               //The old value is 2
+#define UCACHE              (ICACHE|DCACHE)
+
+#define __ALIGNED(x)        __attribute__((aligned(x)))
+#define __CACHE_ALIGN       __ALIGNED(OS_CACHE_LINE_SIZE)
+
+
+#endif
diff --git a/demos/d9_secure/src/d9_secure/cpu_config.h b/demos/d9_secure/src/d9_secure/cpu_config.h
new file mode 100755
index 0000000000000000000000000000000000000000..6bf24b2fb4f1a21883157a74e7f453e67054d3e5
--- /dev/null
+++ b/demos/d9_secure/src/d9_secure/cpu_config.h
@@ -0,0 +1,57 @@
+#ifndef CPU_CONFIG_H
+#define CPU_CONFIG_H
+#include <prt_buildef.h>
+
+#define MMU_IMAGE_ADDR             0x1400000U
+#define MMU_GIC_ADDR               0xF5411000U
+#define MMU_UART_ADDR              0xF04D0000U
+#define MMU_OPENAMP_ADDR           0x70000000U
+#ifdef OS_GDB_STUB
+#define MMU_GDB_STUB_ADDR          0x70040000U
+#endif
+
+#define OS_GIC_VER                 2
+#define SICR_ADDR_OFFSET_PER_CORE  0x200U
+
+#define GIC_CPU_BASE               (GIC_DIST_BASE + 0x1000U)
+
+#define GICD_CTLR                  (GIC_DIST_BASE + 0x0000U)
+#define GICD_TYPER                 (GIC_DIST_BASE + 0x0004U)
+#define GICD_IIDR                  (GIC_DIST_BASE + 0x0008U)
+#define GICD_IGROUPRn              (GIC_DIST_BASE + 0x0080U)
+#define GICD_ISENABLERn            (GIC_DIST_BASE + 0x0100U)
+#define GICD_ICENABLERn            (GIC_DIST_BASE + 0x0180U)
+#define GICD_ISPENDRn              (GIC_DIST_BASE + 0x0200U)
+#define GICD_ICPENDRn              (GIC_DIST_BASE + 0x0280U)
+#define GICD_ISACTIVERn            (GIC_DIST_BASE + 0x0300U)
+#define GICD_ICACTIVERn            (GIC_DIST_BASE + 0x0380U)
+#define GICD_IPRIORITYn            (GIC_DIST_BASE + 0x0400U)
+#define GICD_ITARGETSRn            (GIC_DIST_BASE + 0x0800U)
+
+#define GICC_CTLR                  (GIC_CPU_BASE  + 0x0000U)
+#define GICC_PMR                   (GIC_CPU_BASE  + 0x0004U)
+
+#define BIT(n)                     (1 << (n))
+
+#define GICC_CTLR_ENABLEGRP0       BIT(0)
+#define GICC_CTLR_ENABLEGRP1       BIT(1)
+#define GICC_CTLR_FIQBYPDISGRP0    BIT(5)
+#define GICC_CTLR_IRQBYPDISGRP0    BIT(6)
+#define GICC_CTLR_FIQBYPDISGRP1    BIT(7)
+#define GICC_CTLR_IRQBYPDISGRP1    BIT(8)
+
+#define GICC_CTLR_ENABLE_MASK      (GICC_CTLR_ENABLEGRP0 | \
+                                    GICC_CTLR_ENABLEGRP1)
+
+#define GICC_CTLR_BYPASS_MASK      (GICC_CTLR_FIQBYPDISGRP0 | \
+                                    GICC_CTLR_IRQBYPDISGRP0 | \
+                                    GICC_CTLR_FIQBYPDISGRP1 | \
+                                    GICC_CTLR_IRQBYPDISGRP1)
+
+#define GIC_REG_READ(addr)         (*(volatile U32 *)((uintptr_t)(addr)))
+#define GIC_REG_WRITE(addr, data)  (*(volatile U32 *)((uintptr_t)(addr)) = (U32)(data))
+
+#define REG_READ(addr)         (*(volatile U32 *)((uintptr_t)(addr)))
+#define REG_WRITE(addr, data)  (*(volatile U32 *)((uintptr_t)(addr)) = (U32)(data))
+
+#endif
diff --git a/demos/d9_secure/src/hwi_init.c b/demos/d9_secure/src/hwi_init.c
new file mode 100755
index 0000000000000000000000000000000000000000..27df71eeff7d76db9410c00ce1039e1c20842df9
--- /dev/null
+++ b/demos/d9_secure/src/hwi_init.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version：armv7-a/r定义
+ */
+
+#include <prt_hwi.h>
+#include <cpu_config.h>
+
+#define MAX_SPI_ID 274
+
+void OsGicInitCpuInterface(void)
+{
+    int i;
+    U32 val;
+
+    GIC_REG_WRITE(GICD_CTLR, 1);
+    /* disable int */
+    for (i = 0; i < MAX_SPI_ID; i += 32) {
+        GIC_REG_WRITE(GICD_ICENABLERn + (i/8), 0xFFFFFFFF);
+        GIC_REG_WRITE(GICD_ICPENDRn + (i/8), 0xFFFFFFFF);
+    }
+
+    /* set SPI cpu to cpu 0 and Non-secure view */
+    for (i = 32; i < MAX_SPI_ID; i += 4) {
+        GIC_REG_WRITE(GICD_IPRIORITYn + i, 0x80808080);
+        GIC_REG_WRITE(GICD_ITARGETSRn + i, 0x01010101);
+    }
+
+    GIC_REG_WRITE(GICC_PMR, 0xFF);
+
+    GIC_REG_WRITE(GICC_CTLR, 1);
+}
+
+U32 OsHwiInit(void)
+{
+    OsGicInitCpuInterface();
+    PRT_HwiUnLock();
+    return OS_OK;
+}
diff --git a/demos/d9_secure/src/print.c b/demos/d9_secure/src/print.c
new file mode 100755
index 0000000000000000000000000000000000000000..20c12d3bd766cd47bb6ed41e1dfcfd0cd3aa4ef3
--- /dev/null
+++ b/demos/d9_secure/src/print.c
@@ -0,0 +1,65 @@
+#include <stdarg.h>
+#include "prt_typedef.h"
+#include "cpu_config.h"
+#include "securec.h"
+
+typedef U32 (*PrintFunc)(const char *format, va_list vaList);
+#define OS_MAX_SHOW_LEN 0x200
+
+void uart_poll_send(unsigned char ch)
+{
+    volatile int time = 100000;
+    *(unsigned int *)MMU_UART_ADDR = ch;
+    while (time--);
+}
+
+void TestPutc(unsigned char ch)
+{
+    uart_poll_send(ch);
+    if (ch == '\n') {
+        uart_poll_send('\r');
+    }
+}
+
+int TestPrintf(const char *format, va_list vaList)
+{
+    int len;
+    char buff[OS_MAX_SHOW_LEN] = {0};
+    char *str = buff;
+
+    len = vsnprintf_s(buff, OS_MAX_SHOW_LEN, OS_MAX_SHOW_LEN, format, vaList);
+    if (len == -1) {
+        return len;
+    }
+
+    while (*str != '\0') {
+        TestPutc(*str);
+        str++;
+    }
+
+    return OS_OK;
+}
+
+U32 PRT_Printf(const char *format, ...)
+{
+    va_list vaList;
+    S32 count;
+
+    va_start(vaList, format);
+    count = TestPrintf(format, vaList);
+    va_end(vaList);
+
+    return count;
+}
+
+int printf(const char *format, ...)
+{
+    va_list vaList;
+    S32 count;
+
+    va_start(vaList, format);
+    count = TestPrintf(format, vaList);
+    va_end(vaList);
+
+    return (int)count;
+}
\ No newline at end of file
diff --git a/demos/d9_secure/src/print.h b/demos/d9_secure/src/print.h
new file mode 100755
index 0000000000000000000000000000000000000000..2d39b8ac01c3d4af019e9e247875109fa8cdf546
--- /dev/null
+++ b/demos/d9_secure/src/print.h
@@ -0,0 +1,7 @@
+#ifndef __PRINT_H__
+#define __PRINT_H__
+#include <prt_typedef.h>
+
+extern U32 PRT_Printf(const char *format, ...);
+
+#endif
diff --git a/demos/d9_secure/src/start.S b/demos/d9_secure/src/start.S
new file mode 100755
index 0000000000000000000000000000000000000000..b0c7104758f2624a1449f547adb72e30fd87e5e2
--- /dev/null
+++ b/demos/d9_secure/src/start.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-06-14     WuPeifeng    the first version
+ */
+
+#include "armv7_r.h"
+
+#define FUNCTION(x)             .global x; .type x,STT_FUNC; x:
+
+.globl _start
+
+.section ".text.boot"
+
+_start:
+    B   arm_reset
+    B   _osUnHandleed
+    B   _osUnHandleed
+    B   _osUnHandleed
+    B   _osUnHandleed
+    B   _osUnHandleed
+    B   OsHwiDispatcher
+    B   _osUnHandleed
+
+FUNCTION(arm_reset)
+OsStackBssInit:
+    /* 初始化通用寄存器 */
+    MOV R0, #0
+    MOV R1, #0
+    MOV R2, #0
+    MOV R3, #0
+    MOV R4, #0
+    MOV R5, #0
+    MOV R6, #0
+    MOV R7, #0
+    MOV R8, #0
+    MOV R9, #0
+    MOV R10, #0
+    MOV R11, #0
+    MOV R12, #0
+
+    /* 进入svc模式，关闭IRQ,FIQ*/
+    MOV     R0, #(PSR_SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+    MSR     cpsr_c, R0
+
+    MRC     p15, 0, R12, c1, c0, 0
+    BIC     R12, R12, #((1 << 0) | (1 << 1) | (1 << 2))
+    BIC     R12, R12, #((1 << 10) | (1 << 12) | (1 << 14))
+    BIC     R12, R12, #((1 << 25) | (1 << 30))
+    ORR     R12, R12, #((1 << 11))
+    BIC     R12, R12, #((1 << 13))
+    MCR     p15, 0, R12, c1, c0, 0
+
+    MRC     p15, 0, R0, c15, c0, 1
+    TST     R0, #(0x1F << 2)
+    BEQ     .Lno_normal_axi_pp
+
+    ORR     R0, R0, #1
+    MCR     p15, 0, R0, c15, c0, 1
+.Lno_normal_axi_pp:
+    MRC     p15, 0, R0, c15, c0, 2
+    TST     R0, #(0x1F << 2)
+    BEQ     .Lno_virtual_axi_pp
+
+    ORR     R0, R0, #1
+    MCR     p15, 0, R0, c15, c0, 2
+.Lno_virtual_axi_pp:
+    MRC     p15, 0, R0, c15, c0, 3
+    TST     R0, #(0x1F << 2)
+    BEQ     .Lno_ahb_pp
+
+    ORR     R0, R0, #1
+    MCR     p15, 0, R0, c15, c0, 3
+.Lno_ahb_pp:
+
+/* 初始化各个模式对应的私有寄存器和栈空间 */
+.Lstack_setup:
+    /* IRQ */
+    CPSID   i, #PSR_IRQ_MODE
+    MOV     LR, #0
+    LDR     R12, =irq_stack
+    ADD     R12, #OS_ARCH_IRQ_STACK_SIZE
+    MOV     SP, R12
+
+    /* FIQ */
+    CPSID   i, #PSR_FIQ_MODE
+    MOV     R8, #0
+    MOV     R9, #0
+    MOV     R10, #0
+    MOV     R11, #0
+    MOV     R12, #0
+    MOV     SP, R0
+    MOV     LR, #0
+    LDR     R12, =fiq_stack
+    ADD     R12, #OS_ARCH_FIQ_STACK_SIZE
+    MOV     SP, R12
+
+    /* data abort */
+    CPSID   i, #PSR_ABT_MODE
+    MOV     LR, #0
+    LDR     R12, =abt_stack
+    ADD     R12, #OS_ARCH_ABT_STACK_SIZE
+    MOV     SP, R12
+
+    /* undefined instruction */
+    CPSID   i, #PSR_UNDEF_MODE
+    MOV     LR, #0
+    LDR     R12, =und_stack
+    ADD     R12, #OS_ARCH_UND_STACK_SIZE
+    MOV     SP, R12
+
+    /* system/user 共用一个栈*/
+    CPSID   i, #PSR_SYS_MODE
+    MOV     LR, #0
+    LDR     R12, =sys_stack
+    ADD     R12, #OS_ARCH_SYS_STACK_SIZE
+    MOV     SP, R12
+
+    /* supervisor */
+    CPSID   i, #PSR_SVC_MODE
+    MOV     LR, #0
+    LDR     R12, =svc_stack
+    ADD     R12, #OS_ARCH_SVC_STACK_SIZE
+    MOV     SP, R12
+
+
+    /* 使能cache*/
+    LDR     R0, =ICACHE
+    BL      arch_enable_cache
+
+    LDR     R0, =DCACHE
+    BL      arch_enable_cache
+
+.Lbss_init:
+    LDR     R4, =__bss_start__
+    LDR     R5, =__bss_end__
+    MOV     R6, #0
+.Lbss_loop:
+    CMP     R4, R5
+    STRLT   R6, [R4], #4
+    BLT     .Lbss_loop
+
+OsPrimaryMain: /* OsPrimaryMain函数主核调用 */
+    BL PRT_HardBootInit /* 用户调用的第一个函数钩子，用户在此处完成Seed随机数生成 */
+    LDR     R0, =main
+    BLX     R0
+    B       .
diff --git a/demos/d9_secure/src/timer.c b/demos/d9_secure/src/timer.c
new file mode 100755
index 0000000000000000000000000000000000000000..14bb5056d4d245aac88e1669f606373204ca5e4b
--- /dev/null
+++ b/demos/d9_secure/src/timer.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-14     WuPeifeng    the first version：armv7-a/r定义
+ */
+
+#include "prt_sys.h"
+#include "prt_tick.h"
+#include "prt_config.h"
+#include "prt_task.h"
+#include "prt_hwi.h"
+#include "cpu_config.h"
+#include "securec.h"
+#include <stdio.h>
+
+#define TIMER3_BASE_REG         0xF08B0000
+#define TIMER3_IRQ_NUM          229
+
+#define REG_TMR_STA             0x00
+#define REG_TMR_STA_EN          0x4
+#define REG_TMR_SIG_EN          0x8
+#define REG_TMR_CLK_CFG         0x20
+#define REG_TMR_CNT_CFG         0x24
+#define REG_CNT_G0_OVF          0x28
+#define REG_CNT_G1_OVF          0x2C
+#define REG_LOCAL_A_OVF         0x30
+#define REG_CNT_G0              0x40
+#define REG_CNT_G1              0x44
+#
+
+uint64_t PRT_ClkGetCycleCount64(void)
+{
+    U32 countLow, countTmp, countHigh;
+
+    countLow = REG_READ(TIMER3_BASE_REG + REG_CNT_G0);
+    do {
+        countTmp = countLow;
+        countHigh = REG_READ(TIMER3_BASE_REG + REG_CNT_G1);
+        countLow = REG_READ(TIMER3_BASE_REG + REG_CNT_G0);
+    } while (countTmp > countLow);
+
+    return (((uint64_t)countHigh) << 32) + countLow;
+}
+
+static void TimerIsr(uintptr_t para)
+{
+    // 重置一个tick中断
+    U32 status = REG_READ(TIMER3_BASE_REG + REG_TMR_STA);
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_STA, status);
+
+    PRT_TickISR();
+    PRT_ISB();
+}
+
+static uint32_t CoreTimerStart(void)
+{
+    U32 reg_value;
+
+    // 设置LOCAL_A计时器超时值为一个tick周期的cycle值-1
+    REG_WRITE(TIMER3_BASE_REG + REG_LOCAL_A_OVF, ((OS_SYS_CLOCK / OS_TICK_PER_SECOND)- 1));
+
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_CNT_CFG);
+    reg_value |= (0x1 << 2); // reload CNT_LOCAL_A
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_CNT_CFG, reg_value);
+
+    // sdrv_tmr_lld_int_enable(TIMER3_BASE_REG, SDRV_TMR_STA_CNT_OVF_SHIFT(id));
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_STA_EN);
+    reg_value |= (0x1 << 10);
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_STA_EN, reg_value);
+
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_SIG_EN);
+    reg_value |= (0x1 << 10);
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_SIG_EN, reg_value);
+    return OS_OK;
+}
+
+
+uint32_t TestClkStart(void)
+{
+    uint32_t ret;
+    uint32_t reg_value;
+
+    /* 初始化寄存器 */
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_CLK_CFG);
+    reg_value &= 0xfffc0000;
+    /* 设置时钟24Mhz，不分频*/
+    reg_value |= (0x2 << 16);
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_CLK_CFG, reg_value);
+
+    // 设置 CASCADE_MODE
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_CNT_CFG);
+    reg_value |= (1 << 6);
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_CNT_CFG, reg_value);
+
+    /* 设置0xffffffff，G0和G1一起实现64位count计时 */
+    REG_WRITE(TIMER3_BASE_REG + REG_CNT_G0_OVF, 0xffffffff);
+    REG_WRITE(TIMER3_BASE_REG + REG_CNT_G1_OVF, 0xffffffff);
+    reg_value = REG_READ(TIMER3_BASE_REG + REG_TMR_CNT_CFG);
+    reg_value |= (0x1 << 0); // reload CNT_G0
+    reg_value |= (0x1 << 1); // reload CNT_G1
+    REG_WRITE(TIMER3_BASE_REG + REG_TMR_CNT_CFG, reg_value);
+
+    ret = PRT_HwiSetAttr(TIMER3_IRQ_NUM, 2, OS_HWI_MODE_ENGROSS);
+    if (ret != OS_OK) {
+        return ret;
+    }
+
+    ret = PRT_HwiCreate(TIMER3_IRQ_NUM, (HwiProcFunc)TimerIsr, 0);
+    if (ret != OS_OK) {
+        return ret;
+    }
+
+    PRT_HwiEnable(TIMER3_IRQ_NUM);
+
+    ret = CoreTimerStart();
+    if (ret != OS_OK) {
+        return ret;
+    }
+
+    return OS_OK;
+}
+
+
diff --git a/src/arch/CMakeLists.txt b/src/arch/CMakeLists.txt
index 784f5e71ab4697dfb507ac656c428763d1ced784..58928ea8fc4f954cfc08638e24853e9729fcdd9c 100644
--- a/src/arch/CMakeLists.txt
+++ b/src/arch/CMakeLists.txt
@@ -1,5 +1,5 @@
 add_subdirectory(cpu)
-if(${CONFIG_OS_ARCH_ARMV8})
+if((${CONFIG_OS_ARCH_ARMV8}) OR (${CONFIG_OS_ARCH_ARMV7_R}))
     add_subdirectory(drv)
 endif()
 
diff --git a/src/arch/cpu/CMakeLists.txt b/src/arch/cpu/CMakeLists.txt
index 7529e883be1fbe9c51935baa13fd3c531b949a5c..0b2a7956018ffbd51d2cc901cbdcfd7dacefaa35 100644
--- a/src/arch/cpu/CMakeLists.txt
+++ b/src/arch/cpu/CMakeLists.txt
@@ -11,3 +11,6 @@ endif()
 if(${CONFIG_OS_ARCH_RISCV64})
     add_subdirectory(riscv64)
 endif()
+if(${CONFIG_OS_ARCH_ARMV7_R})
+    add_subdirectory(armv7-r)
+endif()
\ No newline at end of file
diff --git a/src/arch/cpu/Kconfig b/src/arch/cpu/Kconfig
index 5cfbaa4c2a273bcde0037b0f08fe3028679612a0..868a0a0091c531c1314ce9ddef01d0b58b657c71 100644
--- a/src/arch/cpu/Kconfig
+++ b/src/arch/cpu/Kconfig
@@ -6,8 +6,11 @@ config OS_ARCH_X86_64
 	bool "X86_64"
 config OS_ARCH_RISCV64
 	bool "RISCV64"
+config OS_ARCH_ARMV7_R
+	bool "ARMV7_R"
 endchoice
 
 source "arch/cpu/riscv64/Kconfig"
 source "arch/cpu/armv7-m/Kconfig"
 source "arch/cpu/x86_64/Kconfig"
+source "arch/cpu/armv7-r/Kconfig"
diff --git a/src/arch/cpu/armv7-r/CMakeLists.txt b/src/arch/cpu/armv7-r/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..09446901075d48a43e3378ed1d3916b3ec2de9a0
--- /dev/null
+++ b/src/arch/cpu/armv7-r/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory(common)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/Kconfig b/src/arch/cpu/armv7-r/Kconfig
new file mode 100755
index 0000000000000000000000000000000000000000..fae2d21ac55e1a4e20c7aebeebd1b12267628dba
--- /dev/null
+++ b/src/arch/cpu/armv7-r/Kconfig
@@ -0,0 +1,18 @@
+menu "ARM7-M Sepecfic Configuration"
+
+depends on OS_ARCH_ARMV7_R
+
+config INTERNAL_OS_D9_SECURE
+	bool
+	select INTERNAL_OS_BYTE_ORDER_LE
+
+choice
+	prompt "Cpu Type"
+
+config INTERNAL_OS_PLATFORM_CORTEX_R5
+	bool "CORTEX_R5"
+	select INTERNAL_OS_D9_SECURE
+
+endchoice
+
+endmenu
diff --git a/src/arch/cpu/armv7-r/common/CMakeLists.txt b/src/arch/cpu/armv7-r/common/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..5e4c8744e58272baf672a00b57279c3657b5afb2
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/CMakeLists.txt
@@ -0,0 +1,6 @@
+add_subdirectory(boot)
+add_subdirectory(cache)
+add_subdirectory(exc)
+add_subdirectory(hwi)
+add_library_ex(prt_port.c)
+add_library_ex(prt_div64.c)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/armv7_r.h b/src/arch/cpu/armv7-r/common/armv7_r.h
new file mode 100755
index 0000000000000000000000000000000000000000..db3a5a984a14386add1ae2303a93a210e73ea6ba
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/armv7_r.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version：armv7-a/r定义
+ */
+
+#ifndef ARMV7_R_H
+#define ARMV7_R_H
+
+#include <prt_buildef.h>
+
+/* PSR */
+#define PSR_USR_MODE           0x00000010u
+#define PSR_FIQ_MODE           0x00000011u
+#define PSR_IRQ_MODE           0x00000012u
+#define PSR_SVC_MODE           0x00000013u
+#define PSR_ABT_MODE           0x00000017u
+#define PSR_UNDEF_MODE         0x0000001Bu
+#define PSR_HYP_MODE           0x0000001Au
+#define PSR_SYS_MODE           0x0000001Fu
+#define PSR_MODE_MASK          0x0000001Fu
+
+#define PSR_F_BIT               0x00000040u
+#define PSR_I_BIT               0x00000080u
+#define PSR_A_BIT               0x00000100u
+
+#define PSR_T_ARM           0x00000000u
+#define PSR_T_THUMB         0x00000020u
+
+#define PSR_INT_DISABLE     (PSR_I_BIT | PSR_F_BIT)
+
+/* MPIDR field defines */
+#define MPIDR_CPUID_MASK    0x000000FFu
+
+#define ICACHE              2               //The old value is 1
+#define DCACHE              1               //The old value is 2
+#define UCACHE              (ICACHE|DCACHE)
+
+#define __ALIGNED(x)        __attribute__((aligned(x)))
+#define __CACHE_ALIGN       __ALIGNED(OS_CACHE_LINE_SIZE)
+
+
+#endif
diff --git a/src/arch/cpu/armv7-r/common/boot/CMakeLists.txt b/src/arch/cpu/armv7-r/common/boot/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..7af904790410daeeb0a89d54b5cb0942139a381d
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/boot/CMakeLists.txt
@@ -0,0 +1 @@
+add_library_ex(prt_hw_boot.c)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/boot/prt_hw_boot.c b/src/arch/cpu/armv7-r/common/boot/prt_hw_boot.c
new file mode 100755
index 0000000000000000000000000000000000000000..64d75007a2a3c6b27f503913c1e78c83571c24e3
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/boot/prt_hw_boot.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-12-22
+ * Description: Hardware interrupt implementation
+ */
+#include "prt_attr_external.h"
+
+OS_SEC_L4_TEXT void OsHwInit(void)
+{
+}
diff --git a/src/arch/cpu/armv7-r/common/cache/CMakeLists.txt b/src/arch/cpu/armv7-r/common/cache/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..89481e0e5838da95d7c0c6b110da832a899031f1
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/cache/CMakeLists.txt
@@ -0,0 +1 @@
+add_library_ex(arm_cache.S)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/cache/arm_cache.S b/src/arch/cpu/armv7-r/common/cache/arm_cache.S
new file mode 100755
index 0000000000000000000000000000000000000000..0311180a4504d4ed42404f01a2fc64d9b74fb573
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/cache/arm_cache.S
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2008-2012 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <prt_buildef.h>
+#include "prt_asm_arm_external.h"
+
+.text
+
+/* void arch_disable_cache(uint flags) */
+FUNCTION(arch_disable_cache)
+    stmfd   sp!, {r4-r11, lr}
+
+    mov     r7, r0                      // save flags
+
+    mrs     r8, cpsr                    // save the old interrupt state
+    cpsid   iaf                         // interrupts disabled
+
+.Ldcache_disable:
+    tst     r7, #DCACHE
+    beq     .Licache_disable
+    mrc     p15, 0, r0, c1, c0, 0       // cr1
+    tst     r0, #(1<<2)                 // is the dcache already disabled?
+    beq     .Ldcache_already_disabled
+
+    bic     r0, #(1<<2)
+    mcr     p15, 0, r0, c1, c0, 0       // disable dcache
+
+    // flush and invalidate the dcache
+    // NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
+    bl      flush_invalidate_cache_v7
+
+    b       .Ldcache_disable_L2
+
+.Ldcache_already_disabled:
+    // make sure all of the caches are invalidated
+    // NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
+    bl      invalidate_cache_v7
+
+.Ldcache_disable_L2:
+
+#ifdef CONFIG_ARCH_L2CACHE
+    // disable the L2, if present
+    mrc     p15, 0, r0, c1, c0, 1       // aux cr1
+    bic     r0, #(1<<1)
+    mcr     p15, 0, r0, c1, c0, 1       // disable L2 dcache
+#endif
+
+.Licache_disable:
+    tst     r7, #ICACHE
+    beq     .Ldone_disable
+
+    mrc     p15, 0, r0, c1, c0, 0       // cr1
+    bic     r0, #(1<<12)
+    mcr     p15, 0, r0, c1, c0, 0       // disable icache
+
+.Ldone_disable:
+    // make sure the icache is always invalidated
+    mov     r0, #0
+    mcr     p15, 0, r0, c7, c5, 0       // invalidate icache to PoU
+
+    msr     cpsr, r8
+    ldmfd   sp!, {r4-r11, pc}
+
+/* void arch_enable_cache(uint flags) */
+FUNCTION(arch_enable_cache)
+    stmfd   sp!, {r4-r12, lr}
+
+    mov     r7, r0                      // save flags
+
+    mrs     r8, cpsr                    // save the old interrupt state
+    cpsid   iaf                         // interrupts disabled
+
+.Ldcache_enable:
+    tst     r7, #DCACHE
+    beq     .Licache_enable
+    mrc     p15, 0, r0, c1, c0, 0       // cr1
+    tst     r0, #(1<<2)                 // is the dcache already enabled?
+    bne     .Licache_enable
+
+    // invalidate L1 and L2
+    // NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
+    bl      invalidate_cache_v7
+
+#ifdef CONFIG_ARCH_L2CACHE
+    // enable the L2, if present
+    mrc     p15, 0, r0, c1, c0, 1       // aux cr1
+    orr     r0, #(1<<1)
+    mcr     p15, 0, r0, c1, c0, 1       // enable L2 dcache
+#endif
+
+    mrc     p15, 0, r0, c1, c0, 0       // cr1
+    orr     r0, #(1<<2)
+    mcr     p15, 0, r0, c1, c0, 0       // enable dcache
+
+.Licache_enable:
+    tst     r7, #ICACHE
+    beq     .Ldone_enable
+
+    mov     r0, #0
+    mcr     p15, 0, r0, c7, c5, 0       // invalidate icache to PoU
+
+    mrc     p15, 0, r0, c1, c0, 0       // cr1
+    orr     r0, #(1<<12)
+    mcr     p15, 0, r0, c1, c0, 0       // enable icache
+
+.Ldone_enable:
+    isb
+    msr     cpsr, r8
+    ldmfd   sp!, {r4-r12, pc}
+
+// flush & invalidate cache routine, trashes r0-r6, r9-r11
+flush_invalidate_cache_v7:
+    /* from ARMv7 manual, B2-17 */
+    dmb
+    MRC     p15, 1, R0, c0, c0, 1       // Read CLIDR
+    ANDS    R3, R0, #0x7000000
+    MOV     R3, R3, LSR #23             // Cache level value (naturally aligned)
+    BEQ     .Lfinished
+    MOV     R10, #0
+.Loop1:
+    ADD     R2, R10, R10, LSR #1        // Work out 3xcachelevel
+    MOV     R1, R0, LSR R2              // bottom 3 bits are the Cache type for this level
+    AND     R1, R1, #7                  // get those 3 bits alone
+    CMP     R1, #2
+    BLT     .Lskip                      // no cache or only instruction cache at this level
+    MCR     p15, 2, R10, c0, c0, 0      // write the Cache Size selection register
+    isb                                 // ISB to sync the change to the CacheSizeID reg
+    MRC     p15, 1, R1, c0, c0, 0       // reads current Cache Size ID register
+    AND     R2, R1, #0x7                // extract the line length field
+    ADD     R2, R2, #4                  // add 4 for the line length offset (log2 16 bytes)
+    LDR     R4, =0x3FF
+    ANDS    R4, R4, R1, LSR #3          // R4 is the max number on the way size (right aligned)
+    CLZ     R5, R4                      // R5 is the bit position of the way size increment
+    LDR     R6, =0x00007FFF
+    ANDS    R6, R6, R1, LSR #13         // R6 is the max number of the index size (right aligned)
+.Loop2:
+    MOV     R9, R4                      // R9 working copy of the max way size (right aligned)
+.Loop3:
+    ORR     R11, R10, R9, LSL R5        // factor in the way number and cache number into R11
+    ORR     R11, R11, R6, LSL R2        // factor in the index number
+    MCR     p15, 0, R11, c7, c14, 2     // clean & invalidate by set/way
+    SUBS    R9, R9, #1                  // decrement the way number
+    BGE     .Loop3
+    SUBS    R6, R6, #1                  // decrement the index
+    BGE     .Loop2
+.Lskip:
+    ADD     R10, R10, #2                // increment the cache number
+    CMP     R3, R10
+    BGT     .Loop1
+
+.Lfinished:
+    mov     r10, #0
+    mcr     p15, 2, r10, c0, c0, 0      // select cache level 0
+    dsb
+    isb
+
+    bx      lr
+
+// invalidate cache routine, trashes r0-r6, r9-r11
+invalidate_cache_v7:
+    /* from ARMv7 manual, B2-17 */
+    dmb
+    MRC     p15, 1, R0, c0, c0, 1       // Read CLIDR
+    ANDS    R3, R0, #0x7000000
+    MOV     R3, R3, LSR #23             // Cache level value (naturally aligned)
+    BEQ     .Lfinished_invalidate
+    MOV     R10, #0
+.Loop1_invalidate:
+    ADD     R2, R10, R10, LSR #1        // Work out 3xcachelevel
+    MOV     R1, R0, LSR R2              // bottom 3 bits are the Cache type for this level
+    AND     R1, R1, #7                  // get those 3 bits alone
+    CMP     R1, #2
+    BLT     .Lskip_invalidate           // no cache or only instruction cache at this level
+    MCR     p15, 2, R10, c0, c0, 0      // write the Cache Size selection register
+    isb                                 // ISB to sync the change to the CacheSizeID reg
+    MRC     p15, 1, R1, c0, c0, 0       // reads current Cache Size ID register
+    AND     R2, R1, #0x7                // extract the line length field
+    ADD     R2, R2, #4                  // add 4 for the line length offset (log2 16 bytes)
+    LDR     R4, =0x3FF
+    ANDS    R4, R4, R1, LSR #3          // R4 is the max number on the way size (right aligned)
+    CLZ     R5, R4                      // R5 is the bit position of the way size increment
+    LDR     R6, =0x00007FFF
+    ANDS    R6, R6, R1, LSR #13         // R6 is the max number of the index size (right aligned)
+.Loop2_invalidate:
+    MOV     R9, R4                      // R9 working copy of the max way size (right aligned)
+.Loop3_invalidate:
+    ORR     R11, R10, R9, LSL R5        // factor in the way number and cache number into R11
+    ORR     R11, R11, R6, LSL R2        // factor in the index number
+    MCR     p15, 0, R11, c7, c6, 2      // invalidate by set/way
+    SUBS    R9, R9, #1                  // decrement the way number
+    BGE     .Loop3_invalidate
+    SUBS    R6, R6, #1                  // decrement the index
+    BGE     .Loop2_invalidate
+.Lskip_invalidate:
+    ADD     R10, R10, #2                // increment the cache number
+    CMP     R3, R10
+    BGT     .Loop1_invalidate
+
+.Lfinished_invalidate:
+    dsb
+    mov     r10, #0
+    mcr     p15, 2, r10, c0, c0, 0      // select cache level 0
+    isb
+
+    bx      lr
+
+    /* void arch_flush_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_clean_cache_range)
+#ifdef CONFIG_ARM_WITH_CP15
+    mov     r3, r0                      // save the start address
+    add     r2, r0, r1                  // calculate the end address
+    bic     r0, #(OS_CACHE_LINE_SIZE-1)     // align the start with a cache line
+0:
+    mcr     p15, 0, r0, c7, c10, 1      // clean cache to PoC by MVA
+    add     r0, #OS_CACHE_LINE_SIZE
+    cmp     r0, r2
+    blo     0b
+
+    dsb
+#endif
+    bx      lr
+
+    /* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_clean_invalidate_cache_range)
+#ifdef CONFIG_ARM_WITH_CP15
+    mov     r3, r0                      // save the start address
+    add     r2, r0, r1                  // calculate the end address
+    bic     r0, #(OS_CACHE_LINE_SIZE-1)     // align the start with a cache line
+0:
+    mcr     p15, 0, r0, c7, c14, 1      // clean & invalidate dcache to PoC by MVA
+    add     r0, r0, #OS_CACHE_LINE_SIZE
+    cmp     r0, r2
+    blo     0b
+
+    dsb
+#endif
+    bx      lr
+
+    /* void arch_clean_invalidate_dcache_all(void); */
+FUNCTION(arch_clean_invalidate_dcache_all)
+#ifdef CONFIG_ARM_WITH_CP15
+	mrc		p15, 1, r0, c0, c0, 0   /* Read the Cache Size Identification Register */
+	ldr		r3, =0xffff			/* Isolate the NumSets field (bits 13-27) */
+	and		r0, r3, r0, lsr #13		/* r0=NumSets (number of sets - 1) */
+
+	mov		r1, #0				/* r1 = way loop counter */
+way_loop:
+
+	mov		r3, #0				/* r3 = set loop counter */
+set_loop:
+	mov		r2, r1, lsl #30			/* r2 = way loop counter << 30 */
+	orr		r2, r3, lsl #5			/* r2 = set/way cache operation format */
+	mcr		p15, 0, r2, c7, c14, 2  /* Data Cache Clean Invalidate by Set/Way */
+	add		r3, r3, #1			/* Increment set counter */
+	cmp		r0, r3				/* Last set? */
+	bne		set_loop			/* Keep looping if not */
+
+	add		r1, r1, #1			/* Increment the way counter */
+	cmp		r1, #4				/* Last way? (four ways assumed) */
+	bne		way_loop			/* Keep looping if not */
+
+	dsb
+#endif
+    bx      lr
+
+    /* void arch_invalidate_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_invalidate_cache_range)
+#ifdef CONFIG_ARM_WITH_CP15
+    mov     r3, r0                      // save the start address
+    add     r2, r0, r1                  // calculate the end address
+    bic     r0, #(OS_CACHE_LINE_SIZE-1)     // align the start with a cache line
+0:
+    mcr     p15, 0, r0, c7, c6, 1       // invalidate dcache to PoC by MVA
+    add     r0, r0, #OS_CACHE_LINE_SIZE
+    cmp     r0, r2
+    blo     0b
+
+    dsb
+#endif
+    bx      lr
+
+    /* void arch_sync_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_sync_cache_range)
+    push    { r14 }
+    bl      arch_clean_cache_range
+
+    mov     r0, #0
+    mcr     p15, 0, r0, c7, c5, 0       // invalidate icache to PoU
+
+    pop     { pc }
diff --git a/src/arch/cpu/armv7-r/common/exc/CMakeLists.txt b/src/arch/cpu/armv7-r/common/exc/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..905ff5df95d0eaf6c4966713f2678a84426624a6
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/exc/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library_ex(prt_exc.c)
+add_library_ex(exception.S)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/exc/exception.S b/src/arch/cpu/armv7-r/common/exc/exception.S
new file mode 100755
index 0000000000000000000000000000000000000000..aae2263734775430bd2cab5b89407850be5275f9
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/exc/exception.S
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------------
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013-2020. All rights reserved.
+ * Description: ARMv7 Hw Exc Implementation
+ * Author: Huawei LiteOS Team
+ * Create: 2013-01-01
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --------------------------------------------------------------------------- */
+
+#include "prt_exc_internal.h"
+
+    .extern   OsExcHandleEntry
+
+    .global   _osUnHandleed
+
+    .fpu vfpv4
+
+
+
+@ Description: Software interrupt exception handler
+_osUnHandleed:
+    STMFD   SP!, {LR}                                         @ Store PC
+    STMFD   SP!, {LR}
+    STMFD   SP!, {SP}
+    STMFD   SP!, {R0-R12}                                     @ Store SP,LR,R0-R12
+
+    MRS     R1, SPSR                                          @ Save exception`s CPSR.
+    STMFD   SP!, {R1}                                         @ Push task`s CPSR (i.e. exception SPSR).
+
+    MOV     R0, #0                                @ Set exception ID to OS_EXCEPT_SWI.
+    MOV     R5, SP
+
+    B       OsExcHandleEntry                                   @ Branch to global exception handler.
+
+    .end
diff --git a/src/arch/cpu/armv7-r/common/exc/prt_exc.c b/src/arch/cpu/armv7-r/common/exc/prt_exc.c
new file mode 100755
index 0000000000000000000000000000000000000000..d8b1a428822f6d284662552f807957b6b83f759d
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/exc/prt_exc.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2022-11-22
+ * Description: 异常处理。
+ */
+
+#include "prt_exc_internal.h"
+
+OS_SEC_BSS ExcTaskInfoFunc g_excTaskInfoGet;
+extern uintptr_t __exc_stack_top;
+
+/*
+ * 描述: EXC钩子处理函数
+ */
+INIT_SEC_L4_TEXT void OsExcHookHandle(void)
+{
+    struct ExcInfo *excInfo = OS_EXC_INFO_ADDR;
+
+    if (g_excModInfo.excepHook != NULL) {
+        (void)g_excModInfo.excepHook(excInfo); // 目前不支持异常返回
+    }
+
+    PRT_SysReboot();
+}
+/*
+ * 描述: FIQ异常处理
+ */
+OS_SEC_ALW_INLINE INLINE void OsExcFiqProc(U32 excType)
+{
+    struct ExcInfo excInfo = {0};
+    excInfo.excCause = excType;
+
+    if (g_excModInfo.excepHook != NULL) {
+        (void)g_excModInfo.excepHook(&excInfo);
+    }
+
+    PRT_SysReboot();
+}
+
+/*
+ * 描述: 获取异常前的线程信息
+ */
+OS_SEC_ALW_INLINE INLINE void OsExcSetThreadInfo(struct ExcInfo *excInfo)
+{
+    U32 threadId = INVALIDPID;
+    struct TskInfo taskInfo = {0};
+
+    if (g_excTaskInfoGet != NULL) {
+        g_excTaskInfoGet(&threadId, &taskInfo);
+    }
+
+    /* 记录发生异常时的线程ID，发生在任务和软中断中，此项具有意义，其他线程中，此项无意义 */
+    excInfo->threadId = INVALIDPID;
+
+    /* 设置异常前的线程类型 */
+    if (OS_INT_COUNT > 0) {
+        excInfo->threadType = EXC_IN_HWI;
+    } else if ((UNI_FLAG & OS_FLG_TICK_ACTIVE) != 0) {
+        excInfo->threadType = EXC_IN_TICK;
+    } else if ((UNI_FLAG & OS_FLG_SYS_ACTIVE) != 0) {
+        excInfo->threadType = EXC_IN_SYS;
+    } else if ((UNI_FLAG & OS_FLG_BGD_ACTIVE) != 0) {
+        excInfo->threadType = EXC_IN_TASK;
+        if (OsTskMaxNumGet() > 0) { /* 任务存在时 */
+            excInfo->threadId = threadId;
+        }
+    } else { /* OS_FLG_BGD_ACTIVE没有置位，代表此时还在系统进程中，没有进入业务线程 */
+        excInfo->threadType = EXC_IN_SYS_BOOT;
+    }
+
+    /* 任务栈栈底 */
+    if (excInfo->threadType == EXC_IN_TASK) {
+        excInfo->stackBottom = TRUNCATE((taskInfo.topOfStack + taskInfo.stackSize), OS_EXC_STACK_ALIGN);
+    }
+}
+/*
+ * 描述: 记录异常信息
+ */
+INIT_SEC_L4_TEXT void OsExcSaveInfo(struct ExcInfo *excInfo, struct ExcRegInfo *regs)
+{
+    U64 cycle;
+
+    /* 记录异常嵌套计数 */
+    excInfo->nestCnt = CUR_NEST_COUNT;
+
+    /* 记录os版本号 */
+    if (strncpy_s(excInfo->osVer, sizeof(excInfo->osVer), PRT_SysGetOsVersion(), (sizeof(excInfo->osVer) - 1)) != EOK) {
+        OS_GOTO_SYS_ERROR();
+    }
+    excInfo->osVer[OS_SYS_OS_VER_LEN - 1] = '\0';
+
+    /* 记录CPU ID */
+    excInfo->coreId = 0x0U;
+
+    /* 设置字节序 */
+    /* 魔术字 */
+    excInfo->byteOrder = OS_BYTE_ORDER;
+
+    /* 记录CPU类型 */
+    excInfo->cpuType = OsGetCpuType();
+
+    /* 记录CPU TICK值 */
+    cycle = OsCurCycleGet64();
+    excInfo->cpuTick.cntHi = OS_GET_64BIT_HIGH_32BIT(cycle);
+    excInfo->cpuTick.cntLo = (U32)cycle;
+
+    /* 记录寄存器信息 */
+    excInfo->regInfo = *regs;
+
+    /* 记录异常前栈指针 */
+    excInfo->sp = regs->SP;
+
+    /* 记录异常前栈底,系统栈栈底 */
+    excInfo->stackBottom = (uintptr_t)&__exc_stack_top;
+
+    OsExcSetThreadInfo(excInfo);
+}
+
+/*
+ * 描述: EXC模块的处理分发函数
+ */
+INIT_SEC_L4_TEXT void OsExcHandleEntry(U32 excType, struct ExcRegInfo *excRegs)
+{
+    struct ExcInfo *excInfo = OS_EXC_INFO_ADDR;
+
+    UNI_FLAG |= (OS_FLG_HWI_ACTIVE | OS_FLG_EXC_ACTIVE);
+    if (excType == OS_EXCEPT_FIQ) {
+        OsExcFiqProc(excType);
+        return;
+    }
+
+    /* 记录异常类型 */
+    excInfo->excCause = excType;
+    excInfo->fatalErrNo = OsFatalErrClr();
+
+    CUR_NEST_COUNT++;
+
+    /* 记录异常信息 */
+    OsExcSaveInfo(excInfo, excRegs);
+
+    /* 回调异常钩子函数 */
+    OsExcHookHandle();
+}
+
+/*
+ * 描述: EXC模块的初始化
+ */
+OS_SEC_L4_TEXT U32 OsExcConfigInit(void)
+{
+    return OS_OK;
+}
diff --git a/src/arch/cpu/armv7-r/common/exc/prt_exc_internal.h b/src/arch/cpu/armv7-r/common/exc/prt_exc_internal.h
new file mode 100755
index 0000000000000000000000000000000000000000..6653d9b7f6462ec61eb8396be464f55f7e302194
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/exc/prt_exc_internal.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2022-11-22
+ * Description: 异常模块内部头文件。
+ */
+#ifndef PRT_EXC_INTERNAL_H
+#define PRT_EXC_INTERNAL_H
+
+#ifndef __ASSEMBLER__
+#include "prt_attr_external.h"
+#include "prt_err_external.h"
+#include "prt_sys_external.h"
+#include "prt_cpu_external.h"
+#include "prt_exc_external.h"
+#include "prt_irq_external.h"
+#include "prt_task_external.h"
+#include "prt_hook_external.h"
+#include "prt_mem_external.h"
+#include "prt_sem_external.h"
+#include "prt_task_external.h"
+#include "prt_queue_external.h"
+#include "prt_swtmr_external.h"
+#include "prt_timer_external.h"
+#include "prt_raw_spinlock_external.h"
+
+/*
+ * 模块内宏定义
+ */
+#define OS_EXC_DEFAULT_EXC_TYPE 0
+
+#define OS_EXC_STACK_ALIGN     0x10U
+
+#define OS_EXC_ESR_UNDEF_INSTR  0x20U
+#define OS_EXC_ESR_PC_NOT_ALIGN 0x22U
+#define OS_EXC_ESR_DATA_ABORT   0x24U
+#define OS_EXC_ESR_SP_INSTR     0x26U
+
+#define INVALIDPID         0xFFFFFFFFUL
+#define INVALIDSTACKBOTTOM 0xFFFFFFFFUL
+
+/**
+ * system sections start and end address
+ */
+extern char __int_stack_start;
+extern char __int_stack_end;
+extern char __rodata_start;
+extern char __rodata_end;
+extern char __bss_start;
+extern char __bss_end;
+extern char __text_start;
+extern char __text_end;
+extern char __ram_data_start;
+extern char __ram_data_end;
+extern char __exc_heap_start;
+extern char __exc_heap_end;
+extern char __heap_start;
+extern char __init_array_start__;
+extern char __init_array_end__;
+
+#else
+#include <prt_asm_arm_external.h>
+#endif
+
+/* Define exception type ID */
+#define OS_EXCEPT_RESET          0x00
+#define OS_EXCEPT_UNDEF_INSTR    0x01
+#define OS_EXCEPT_SWI            0x02
+#define OS_EXCEPT_PREFETCH_ABORT 0x03
+#define OS_EXCEPT_DATA_ABORT     0x04
+#define OS_EXCEPT_FIQ            0x05
+#define OS_EXCEPT_ADDR_ABORT     0x06
+#define OS_EXCEPT_IRQ            0x07
+
+#endif /* PRT_EXC_INTERNAL_H */
diff --git a/src/arch/cpu/armv7-r/common/hwi/CMakeLists.txt b/src/arch/cpu/armv7-r/common/hwi/CMakeLists.txt
new file mode 100755
index 0000000000000000000000000000000000000000..c81aef908941a75917ad541707d4298d0bab5344
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/hwi/CMakeLists.txt
@@ -0,0 +1,2 @@
+add_library_ex(prt_dispatch.S)
+add_library_ex(prt_hwi.c)
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/hwi/prt_dispatch.S b/src/arch/cpu/armv7-r/common/hwi/prt_dispatch.S
new file mode 100755
index 0000000000000000000000000000000000000000..fdd731c7a6c0355c8efd4b0766819ff580480730
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/hwi/prt_dispatch.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version
+ */
+
+#include <prt_buildef.h>
+#include <prt_asm_arm_external.h>
+
+.extern OsMainSchedule
+.extern __svc_stack_top
+
+FUNCTION(PRT_HwiLock)
+    MRS     R0, CPSR               // 将CPSR的当前值存入R0
+    CPSID   I                      // 禁用中断（将CPSR中的I位设为1）
+    BX      LR                     // 返回
+
+FUNCTION(PRT_HwiUnLock)
+    MRS     R0, CPSR               // 将CPSR的当前值存入R0
+    CPSIE   I                      // 使能中断（将CPSR中的I位设为0）
+    BX      LR                     // 返回
+
+FUNCTION(PRT_HwiRestore)
+    MSR     cpsr_c, r0
+    BX      LR
+
+
+FUNCTION(OsTaskTrap)
+    LDR    r1, =g_runningTask /* OsTaskTrap是函数调用过来，r0 r1寄存器是caller save，此处能直接使用 */
+    LDR    r0, [r1] /* r0 is the &g_pRunningTask->sp */
+/*
+ * 描述: Task调度处理函数。 SMP调度走这个接口，X0 is SP
+ */
+OsTskTrapSmp:
+    MRS     r1, SPSR
+    PUSH    {r1}
+    PUSH    {lr}
+    PUSH    {r0-r12, lr}
+
+    // 存入SP指针到g_pRunningTask->sp
+    mov    r1, sp
+    str    r1, [r0]   // x0 is the &g_pRunningTask->sp
+
+    ldr    r0, =__exc_stack_top
+    ldr    r0, [r0]
+
+    mov    sp, r0
+    B      OsMainSchedule
+loop1:
+    B      loop1
+
+FUNCTION(OsTskContextLoad)
+    /* clear the flag of ldrex */
+    CLREX
+    /* switch to new task's sp */
+    LDR     SP, [R0]
+
+    POP     {R0-R12, LR}
+
+    POP     {R0}
+    POP     {R1}
+    MSR     CPSR, R1
+    BX      R0
+
+FUNCTION(OsHwiDispatcher)
+    SUB     LR, LR, #4
+
+    /* save spsr and lr(svc's pc) onto the svc stack */
+    SRSDB   #0x13!
+
+    /* disable irq, switch to svc mode */
+    CPSID   i, #0x13
+
+    /* push caller saved regs as trashed regs */
+    PUSH    {R0-R3, R12, LR}
+
+    /* 8 bytes stack align
+    STACK_ALIGN     R0 */
+
+    MOV     R0, sp
+    TST     SP, #4
+    SUBEQ   SP, #4
+    PUSH    {R0}
+
+    PUSH    {R4}
+    MOV     R4, SP
+
+    ldr     R1, =__svc_stack_top
+    ldr     R1, [R1]
+    mov     sp, R1                  /* set  sp */
+
+    BLX     OsHwiDispatchHandle
+
+    DSB
+    ISB
+    MOV     SP, R4
+    POP     {R4}
+
+    POP     {R0}
+    MOV     sp, R0
+
+OsIrqContextRestore:
+    POP     {R0-R3, R12, LR}
+    RFEIA   SP!
+
diff --git a/src/arch/cpu/armv7-r/common/hwi/prt_hwi.c b/src/arch/cpu/armv7-r/common/hwi/prt_hwi.c
new file mode 100755
index 0000000000000000000000000000000000000000..a961a3c6be04db5e4cc778cb696fc3ccb128b71e
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/hwi/prt_hwi.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2025-06-13
+ * Description: 硬中断。
+ */
+#include "prt_hwi_external.h"
+#include "prt_task_external.h"
+#include "prt_irq_external.h"
+#include "prt_hwi_internal.h"
+#include <stdio.h>
+
+/*
+ * 描述: GIC模块初始化
+ */
+INIT_SEC_L4_TEXT void OsHwiGICInit(void)
+{
+    return;
+}
+
+/*
+ * 描述: 获取硬中断优先级
+ */
+INIT_SEC_L4_TEXT U32 OsHwiPriorityGet(HwiHandle hwiNum)
+{
+    return OsGicGetPriority(hwiNum);
+}
+
+/*
+ * 描述: 设置硬中断优先级
+ */
+INIT_SEC_L4_TEXT void OsHwiPrioritySet(HwiHandle hwiNum, HwiPrior hwiPrio)
+{   
+    OS_ERR_RECORD(OsGicSetPriority(hwiNum, hwiPrio));
+}
+
+/*
+ * 描述: 禁止指定中断
+ */
+OS_SEC_L2_TEXT U32 PRT_HwiDisable(HwiHandle hwiNum)
+{
+    if (hwiNum > OS_HWI_MAX) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+    OsGicDisableInt(hwiNum);
+
+    return OS_OK;
+}
+
+/*
+ * 描述: 使能指定中断
+ */
+OS_SEC_L2_TEXT U32 PRT_HwiEnable(HwiHandle hwiNum)
+{
+    if (hwiNum > OS_HWI_MAX) {
+        return OS_ERRNO_HWI_NUM_INVALID;
+    }
+    OsGicEnableInt(hwiNum);
+
+    return OS_OK;
+}
+
+#if defined(OS_OPTION_SMP)
+/*
+ * 描述: 出发核间SGI中断，SMP调度频繁使用，放置OS_SEC_TEXT段
+ */
+OS_SEC_TEXT void OsHwiMcTrigger(enum OsHwiIpiType type, U32 coreMask, U32 hwiNum)
+{
+    /* 判断输入参数的合法性 */
+    if (type >= OS_TYPE_TRIGGER_BUTT) {
+        return OS_ERRNO_HWI_TRIGGER_TYPE_INVALID;
+    }
+    
+    U32 coreList = coreMask;
+    if (type == OS_TYPE_TRIGGER_TO_SELF) {
+        coreList = (1U << OsGetCoreID());
+    } else if (type == OS_TYPE_TRIGGER_TO_OTHER) {
+        coreList = OS_ALLCORES_MASK;
+        coreList &= ~(1U << OsGetCoreID());
+        for(U32 coreId = 0; coreId < g_cfgPrimaryCore; coreId++) {
+            coreList &= ~(1U << coreId);
+        }
+    }
+    OsGicTrigIntToCores(hwiNum, coreList);
+    return;
+}
+
+#else
+/*
+ * 描述: 触发核间SGI中断,放置OS_SEC_TEXT段
+ */
+OS_SEC_TEXT void OsHwiMcTrigger(U32 coreMask, U32 hwiNum)
+{
+    OsGicTrigIntToCores(hwiNum, coreMask);
+    return;
+}
+#endif
+/*
+ * 描述: 上报中断号错误
+ */
+OS_SEC_TEXT void OsHwiReportHwiNumErr(void)
+{
+    OS_REPORT_ERROR(OS_ERRNO_HWI_HW_REPORT_HWINO_INVALID);
+    return;
+}
+
+/*
+ * 描述: 中断处理流程尾部处理，TICK 、任务调用
+ * 备注: NA
+ */
+OS_SEC_L0_TEXT void OsHwiDispatchTail_armv7_r(void)
+{
+    U64 irqStartTime = 0;
+    if (TICK_NO_RESPOND_CNT > 0) {
+        if ((UNI_FLAG & OS_FLG_TICK_ACTIVE) != 0) {
+            // OsTskContextLoad， 回到被打断的tick处理现场
+            return;
+        }
+#if defined(OS_OPTION_RR_SCHED) && defined(OS_OPTION_RR_SCHED_IRQ_TIME_DISCOUNT)
+        irqStartTime = OsCurCycleGet64();
+#endif
+        UNI_FLAG |= OS_FLG_TICK_ACTIVE;
+
+        do {
+            OsIntEnable();
+            // tickISRִ，这里开中断
+            g_tickDispatcher();
+            OsIntDisable();
+            TICK_NO_RESPOND_CNT--;
+        } while (TICK_NO_RESPOND_CNT > 0);
+        UNI_FLAG &= ~OS_FLG_TICK_ACTIVE;
+        OS_IRQ_TIME_RECORD(irqStartTime);
+    }
+#if defined(OS_OPTION_RR_SCHED)
+    OsHwiEndCheckTimeSlice(OsCurCycleGet64());
+#endif
+}
+
+/*
+ * 描述: 中断处理, 调用处外部已关中断
+ */
+OS_SEC_L0_TEXT void OsHwiDispatchHandle(void)
+{
+    U32 hwiNum;
+
+    UNI_FLAG |= OS_FLG_HWI_ACTIVE;
+    OS_INT_COUNT++;
+
+    hwiNum = OsHwiNumGet();
+
+    if (OS_HWI_CLEAR_CHECK(hwiNum) || OS_HWI_NUM_CHECK(hwiNum)) {
+        goto OS_HWI_CONTINUE;
+    }
+
+    OsHwiNestedIntEnable();
+    OsHwiHookDispatcher(hwiNum);
+    OsHwiNestedIntDisable();
+
+OS_HWI_CONTINUE:
+    // 清除中断位
+    OsHwiClear(hwiNum);
+    OS_INT_COUNT--;
+    /* 不支持中断嵌套，但这里防止中断服务程序中错误打开了中断 */
+    if (OS_INT_COUNT > 0) {
+        return;
+    }
+
+    OsHwiDispatchTail_armv7_r();
+
+    UNI_FLAG &= ~OS_FLG_HWI_ACTIVE;
+}
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/hwi/prt_hwi_internal.h b/src/arch/cpu/armv7-r/common/hwi/prt_hwi_internal.h
new file mode 100755
index 0000000000000000000000000000000000000000..586a4b7b1bd6c47d57478c6c3d618aed235c16db
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/hwi/prt_hwi_internal.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2022-11-22
+ * Description: hwi模块内部头文件。
+ */
+#ifndef PRT_HWI_INTERNAL_H
+#define PRT_HWI_INTERNAL_H
+
+#include "prt_cpu_external.h"
+
+/*
+ * 模块内 内联函数
+ */
+#if defined(OS_OPTION_HWI_NESTED)
+/*
+ * 描述: 支持中断嵌套场景--进入ISR前开中断
+ */
+OS_SEC_ALW_INLINE INLINE void OsHwiNestedIntEnable(void)
+{
+    OsIntEnable();
+}
+
+/*
+ * 描述: 支持中断嵌套场景--退出ISR后关中断
+ */
+OS_SEC_ALW_INLINE INLINE void OsHwiNestedIntDisable(void)
+{
+    OsIntDisable();
+}
+#else
+OS_SEC_ALW_INLINE INLINE void OsHwiNestedIntEnable(void)
+{
+}
+
+OS_SEC_ALW_INLINE INLINE void OsHwiNestedIntDisable(void)
+{
+}
+#endif /* OS_OPTION_HWI_NESTED */
+
+#endif /* PRT_HWI_INTERNAL_H */
diff --git a/src/arch/cpu/armv7-r/common/os_asm_armv7_r_external.h b/src/arch/cpu/armv7-r/common/os_asm_armv7_r_external.h
new file mode 100755
index 0000000000000000000000000000000000000000..621af65e417df8073b9866902fceb0456422c823
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/os_asm_armv7_r_external.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013-2020. All rights reserved.
+ * Description: Aarch32 Assembly Defines and Macros HeadFile
+ * Author: Huawei LiteOS Team
+ * Create: 2013-01-01
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --------------------------------------------------------------------------- */
+
+#ifndef _ARCH_ASM_H
+#define _ARCH_ASM_H
+
+#include <prt_buildef.h>
+#include "armv7_r.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define FUNCTION(x)             .global x; .type x,STT_FUNC; x:
+
+/*
+ * Used to set current cpu's exception stack pointer.
+ * The stack distribution is as follows:
+ *           ------------------------------------------
+ * stackTop |   cpu n   |  ... |   cpu 1   |   cpu 0   | stackBottom
+ *           ------------------------------------------
+ *          | stackSize |  ... | stackSize | stackSize |
+ */
+.macro EXC_SP_SET stackBottom, stackSize, reg0, reg1
+    mrc    p15, 0, \reg0, c0, c0, 5
+    and    \reg0, \reg0, #MPIDR_CPUID_MASK /* get cpu id */
+    mov    \reg1, #\stackSize
+    mul    \reg1, \reg1, \reg0             /* calculate current cpu stack offset */
+    ldr    \reg0, =\stackBottom
+    ldr    \reg0, [\reg0]
+    sub    \reg0, \reg0, \reg1             /* calculate current cpu stack bottom */
+    mov    sp, \reg0                       /* set  sp */
+.endm
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _ARCH_ASM_H */
diff --git a/src/arch/cpu/armv7-r/common/os_attr_armv7_r_external.h b/src/arch/cpu/armv7-r/common/os_attr_armv7_r_external.h
new file mode 100755
index 0000000000000000000000000000000000000000..4ba9b6a17b5216137770c4cbaa8a8443a5a63bbb
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/os_attr_armv7_r_external.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-12-22
+ * Description: 属性宏相关内部头文件
+ */
+#ifndef OS_ATTR_ARMV7_R_EXTERNAL_H
+#define OS_ATTR_ARMV7_R_EXTERNAL_H
+
+/* 定义操作系统的代码数据分段 */
+#ifndef OS_SEC_L0_TEXT
+#define OS_SEC_L0_TEXT
+#endif
+
+#ifndef OS_SEC_TEXT
+#define OS_SEC_TEXT
+#endif
+
+#ifndef OS_SEC_L2_TEXT
+#define OS_SEC_L2_TEXT
+#endif
+
+#ifndef OS_SEC_L4_TEXT
+#define OS_SEC_L4_TEXT
+#endif
+
+#ifndef OS_SEC_DATA
+#define OS_SEC_DATA __attribute__((section(".os.data")))
+#endif
+
+#ifndef OS_SEC_L4_DATA
+#define OS_SEC_L4_DATA
+#endif
+
+#ifndef OS_SEC_BSS
+#define OS_SEC_BSS
+#endif
+
+#ifndef OS_SEC_L4_BSS
+#define OS_SEC_L4_BSS
+#endif
+
+#endif /* OS_ATTR_ARMV7_M_EXTERNAL_H */
diff --git a/src/arch/cpu/armv7-r/common/os_cpu_armv7_r_external.h b/src/arch/cpu/armv7-r/common/os_cpu_armv7_r_external.h
new file mode 100755
index 0000000000000000000000000000000000000000..3c0dac3826563bb47d9e6237d294c6fb5230cfac
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/os_cpu_armv7_r_external.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2024-11-04
+ * Description: 属性宏相关内部头文件
+ */
+#ifndef OS_CPU_ARMV7_R_EXTERNAL_H
+#define OS_CPU_ARMV7_R_EXTERNAL_H
+
+#include "prt_buildef.h"
+#include "prt_hwi.h"
+#include "prt_gic_external.h"
+#include "prt_atomic.h"
+#include "prt_clk.h"
+#include "armv7_r.h"
+
+/*
+ * 模块间宏定义
+ */
+#define OS_IRQ2HWI(irqNum)           (irqNum)
+#define OS_HWI2IRQ(hwiNum)           (hwiNum)
+#define OS_HWI_GET_HWINUM(archNum)   (archNum)
+#define OS_HWI_GET_HWI_PRIO(hwiPrio) (hwiPrio)
+#define OS_HWI_IS_SGI(hwiNum)        ((hwiNum) <= MAX_SGI_ID)
+#define OS_HWI_IS_PPI(hwiNum)        (((hwiNum) > MAX_SGI_ID) && ((hwiNum) <= MAX_PPI_ID))
+
+/* OS_HWI_MAX_NUM 大小会影响bss段大小。需要根据实际使用hwi个数配置 */
+#if defined(OS_OPTION_GIC_LPI)
+#define OS_HWI_MAX_NUM           0x10000U  /* 后续整改这里，当前这样用 */
+#define OS_HWI_NUM_CHECK(hwiNum)    ((hwiNum) >= OS_HWI_MAX_NUM) || \
+    (((hwiNum) > MAX_SPI_ID) && ((hwiNum) < MIN_LPI_ID))
+#else
+#define OS_HWI_MAX_NUM           0x120U
+#define OS_HWI_NUM_CHECK(hwiNum) ((hwiNum) >= OS_HWI_MAX_NUM)
+#endif
+
+#define OS_HWI_MAX           (OS_HWI_MAX_NUM - 1)
+#define OS_HWI_FORMARRAY_NUM OS_HWI_MAX_NUM
+#define OS_HWI_MIN           0
+#define OS_HWI_PRI_NUM       0x10
+
+/* 中断优先级0~15，但非安全世界的中断优先级只能是偶数 */
+#define OS_HWI_PRIO_CHECK(hwiPrio)     ((hwiPrio) >= OS_HWI_PRI_NUM || ((hwiPrio) & 1U))
+#define OS_HWI_SET_HOOK_ATTR(hwiNum, hwiPrio, hook)
+
+#if defined(OS_OPTION_HWI_AFFINITY)
+/* 仅1-1/1-N SPI中断支持中断路由 */
+#define OS_HWI_AFFINITY_CHECK(hwiNum) OsGicIsSpi(hwiNum)
+
+#endif
+
+#define OS_HWI_CLEAR_CHECK(hwiNum)    ((hwiNum) == GIC_INT_ID_MASK)
+
+/*
+ * SMP系统占用的硬件SGI号
+ */
+#define OS_SMP_SCHED_TRIGGER_OTHER_CORE_SGI OS_HWI_IPI_NO_01 // 触发它核响应一次调度的IPI中断号
+#define OS_SMP_EXC_STOP_OTHER_CORE_SGI      OS_HWI_IPI_NO_02 // 一个核异常后将其他核停住的IPI中断号
+#define OS_SMP_TICK_TRIGGER_OTHER_CORE_SGI  OS_HWI_IPI_NO_03 // 响应tick中断的核触发它核的模拟tickIPI中断号
+#define OS_SMP_MC_CORE_IPC_SGI              OS_HWI_IPI_NO_04 // SMP核间通信使用的IPI中断号
+
+/*
+ * SMP系统占用的硬件SGI的优先级
+ */
+#define OS_SMP_SCHED_TRIGGER_OTHER_CORE_SGI_PRI 0
+#define OS_SMP_EXC_STOP_OTHER_CORE_SGI_PRI      0  // 一个核异常后将其他核停住的IPI中断号
+#define OS_SMP_TICK_TRIGGER_OTHER_CORE_SGI_PRI  0
+#define OS_SMP_MC_CORE_IPC_SGI_PRI              0
+
+#define OS_HWI_INTERNAL_NUM 5
+
+#define OS_DI_STATE_CHECK(intSave)   ((intSave) & 0x80U)
+
+#define OS_TICK_COUNT_UPDATE()
+OS_SEC_ALW_INLINE INLINE void OsSpinLockInitInner(volatile uintptr_t *lockVar)
+{
+    *lockVar = OS_SPINLOCK_UNLOCK;
+}
+
+#define OS_SPINLOCK_INIT_FOREACH(maxNum, structName, field)
+#define OS_SPIN_FREE_FOREACH(maxNum, structName, field)
+#define OS_SPIN_FREE(lockVar)
+
+#define OS_HW_TICK_INIT() OS_OK
+
+#define OS_IS_TICK_PERIOD_INVALID(cyclePerTick) (FALSE)
+
+#define OS_TSK_STACK_SIZE_ALIGN  16U
+#define OS_TSK_STACK_SIZE_ALLOC_ALIGN MEM_ADDR_ALIGN_016
+#define OS_TSK_STACK_ADDR_ALIGN  16U
+#define OS_ALLCORES_MASK g_validAllCoreMask
+
+#define OS_MAX_CACHE_LINE_SIZE   4 /* 单核芯片定义为4 */
+
+/* 任务栈最小值 */
+#define OS_TSK_MIN_STACK_SIZE (ALIGN((0x1D0 + 0x10 + 0x4), 16))
+/* Idle任务的消息队列数 */
+#define OS_IDLE_TASK_QUE_NUM 1
+
+/* Unwind 相关 寄存器在解析帧中的位置，前面30个通用寄存器忽略 */
+#define OS_UNWEIND_LR_OFFSET 0x1EU
+#define OS_UNWEIND_SP_OFFSET 0x24U
+#define OS_UNWEIND_PC_OFFSET 0x23U
+
+/* SPINLOCK 相关 */
+#define OS_SPINLOCK_RELOCK_NEGATIVE 0x80000000U
+
+extern U64 OsU64DivGetQuotient(U64 dividend, U64 divisor);
+extern U64 OsU64DivGetRemainder(U64 dividend, U64 divisor);
+#define DIV64(a, b) OsU64DivGetQuotient((a), (b))
+#define DIV64_REMAIN(a, b) OsU64DivGetRemainder((a), (b))
+
+#define OsIntUnLock() PRT_HwiUnLock()
+#define OsIntLock()   PRT_HwiLock()
+#define OsIntRestore(intSave) PRT_HwiRestore(intSave)
+
+/*
+ * 任务上下文的结构体定义。
+ */
+struct TagHwContext {
+    uintptr_t reg12;
+    uintptr_t reg11;
+    uintptr_t reg10;
+    uintptr_t reg9;
+    uintptr_t reg8;
+    uintptr_t reg7;
+    uintptr_t reg6;
+    uintptr_t reg5;
+    uintptr_t reg4;
+    uintptr_t reg3;
+    uintptr_t reg2;
+    uintptr_t reg1;
+    uintptr_t reg0;
+    uintptr_t lr;
+    uintptr_t pc;
+    uintptr_t spsr;
+};
+
+/* StackTrace保存的任务上下文 */
+struct TagStackTraceContext {
+    uintptr_t lr;
+    uintptr_t spsr;
+    uintptr_t sp;
+    uintptr_t pc;
+    uintptr_t rregs[13];     // r0~r12
+};
+
+/*
+ * 模块间变量声明
+ */
+extern OsVoidFunc g_hwiSplLockHook;
+extern OsVoidFunc g_hwiSplUnLockHook;
+extern U32 g_validAllCoreMask;
+extern U32 ulPortYieldRequired;
+/*
+ * 模块间函数声明
+ */
+extern void OsTaskTrap(void);
+extern void OsTskContextLoad(uintptr_t stackPointer);
+extern uintptr_t OsGetSysStackStart(U32 core);
+extern uintptr_t OsGetSysStackEnd(U32 core);
+/*
+ * 描述: spinlock初始化
+ */
+OS_SEC_ALW_INLINE INLINE U32 OsSplLockInit(struct PrtSpinLock *spinLock)
+{
+    OsSpinLockInitInner(&spinLock->rawLock);
+    return OS_OK;
+}
+
+/*
+ * 描述: 获取硬线程ID
+ */
+OS_SEC_ALW_INLINE INLINE U32 OsGetHwThreadId(void)
+{
+    return PRT_GetCoreID();
+}
+
+/* 计算一个32bit非0数字的最右位     */
+/* e.g. 0x01000020 ----> 结果返回 5 */
+OS_SEC_ALW_INLINE INLINE U32 OsGetRMB(U32 bit)
+{
+    U32 rev = bit - 1;
+    U32 result;
+
+    OS_EMBED_ASM("EOR %0, %1, %2" : "=r"(result) : "r"(rev), "r"(bit));
+    OS_EMBED_ASM("CLZ %0, %1" : "=r"(rev) : "r"(result));
+    return (OS_DWORD_BIT_NUM - rev -1);
+}
+
+/* 计算一个32bit非0 bit的最左位数   */
+OS_SEC_ALW_INLINE INLINE U32 OsGetLMB1(U32 value)
+{
+    U32 mb;
+
+    OS_EMBED_ASM("CLZ %w0, %w1" : "=r"(mb) : "r"(value));
+
+    return mb;
+}
+
+#define OsIntEnable()  PRT_HwiUnLock()
+#define OsIntDisable()  PRT_HwiLock()
+
+/*
+ * 描述: 使能FIQ中断
+ */
+OS_SEC_ALW_INLINE INLINE void OsFiqEnable(void)
+{
+    OS_EMBED_ASM("CPSIE F");
+}
+
+/*
+ * 描述: 设置中断亲核性
+ */
+OS_SEC_ALW_INLINE INLINE U32 OsHwiAffinitySet(HwiHandle hwiNum, U32 coreMask)
+{
+    U32 targetCore;
+
+    if ((coreMask & (coreMask - 1)) != 0) {
+        return OS_ERRNO_MULTI_TARGET_CORE;
+    }
+
+    targetCore = OsGetRMB(coreMask);
+    OsGicSetTargetId(hwiNum, targetCore);
+
+    return OS_OK;
+}
+
+OS_SEC_ALW_INLINE INLINE U32 OsHwiNumGet(void)
+{
+    U32 iar;
+
+    iar = GIC_REG_READ(GICC_IAR);
+
+    return (iar & IAR_MASK);
+}
+
+OS_SEC_ALW_INLINE INLINE void OsHwiClear(U32 intId)
+{
+    GIC_REG_WRITE(GICC_EOIR, intId & IAR_MASK);
+}
+
+OS_SEC_ALW_INLINE INLINE uintptr_t PRT_GetCpsr(void)
+{
+    U32 cpsr;
+
+    __asm__ volatile
+    (
+        "\tmrs    %0, cpsr\n"
+        "\tcpsid  i\n"
+        : "=r" (cpsr)
+        :
+        : "memory"
+    );
+
+    return cpsr;
+}
+
+/*
+ * 描述: 获取SP
+ */
+OS_SEC_ALW_INLINE INLINE uintptr_t OsGetSp(void)
+{
+    uintptr_t sp;
+
+    OS_EMBED_ASM("MOV  %0, sp" : "=r"(sp));
+
+    return sp;
+}
+
+/*
+ * 描述: 获取LR
+ */
+OS_SEC_ALW_INLINE INLINE uintptr_t OsGetLR(void)
+{
+    uintptr_t LR_Get;
+
+    OS_EMBED_ASM("MOV  %0, lr" : "=r"(LR_Get));
+
+    return LR_Get;
+}
+
+/*
+ * 描述: 获取PC
+ */
+OS_SEC_ALW_INLINE INLINE uintptr_t OsGetPC(void)
+{
+    uintptr_t pc;
+
+    OS_EMBED_ASM("1:adr  %0, pc" : "=r"(pc));
+
+    return pc;
+}
+
+/*
+ * 描述: 传入任务切换时的栈地址
+ */
+OS_SEC_ALW_INLINE INLINE uintptr_t OsTskGetInstrAddr(uintptr_t addr)
+{
+    return ((struct TagHwContext *)addr)->pc;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsTaskTrapFast(void)
+{
+    OsTaskTrap();
+}
+
+OS_SEC_ALW_INLINE INLINE void OsTaskTrapFastPs(uintptr_t intSave)
+{
+    (void)intSave;
+    OsTaskTrap();
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplLock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplUnlock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplReadLock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplReadUnlock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplWriteLock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsSplWriteUnlock(volatile uintptr_t *spinLock)
+{
+    (void)spinLock;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsHwiSetSplLockHook(OsVoidFunc hook)
+{
+    (void)hook;
+}
+
+OS_SEC_ALW_INLINE INLINE void OsHwiSetSplUnlockHook(OsVoidFunc hook)
+{
+    (void)hook;
+}
+#endif /* OS_CPU_ARMV7_R_EXTERNAL_H */
diff --git a/src/arch/cpu/armv7-r/common/prt_div64.c b/src/arch/cpu/armv7-r/common/prt_div64.c
new file mode 100755
index 0000000000000000000000000000000000000000..8107a0494e543ea0a7651aad03878a0ef6801cce
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/prt_div64.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2009-07-25
+ * Description: 64位除法文件。
+ */
+#include "prt_typedef.h"
+#include "prt_lib_external.h"
+#include "prt_attr_external.h"
+
+#define OS_32_BITS_COUNT 32
+
+/*
+ * 描述：前导0个数获取
+ */
+static inline U32 OsleadingZeroCount(U64 data)
+{
+    U32 high = (U32)OS_GET_64BIT_HIGH_32BIT(data);
+    U32 low = (U32)OS_GET_64BIT_LOW_32BIT(data);
+    U32 count = 0;
+
+    if (high == 0) {
+        OS_EMBED_ASM("CLZ %0, %1" : "=r"(count) : "r"(low));
+        count += OS_32_BITS_COUNT;
+    } else {
+        OS_EMBED_ASM("CLZ %0, %1" : "=r"(count) : "r"(high));
+    }
+
+    return count;
+}
+
+OS_SEC_TEXT void OsU64Div(U64 dividend, U64 divisor, U64 *quotient, U64 *remainder)
+{
+    U32 alignShift;
+    U32 i;
+    U64 tmpDivisor;
+    U64 tmpRemainder;
+    U64 tmpQuotient = 0;
+
+    if (divisor == 0) {
+        return;                  // 除数为0返回1
+    }
+
+    if (dividend < divisor) {
+        /* 被除数小于除数,商为0,余数即被除数 */
+        *remainder = dividend;
+        *quotient = 0;
+        return;
+    }
+
+    alignShift = OsleadingZeroCount(divisor) - OsleadingZeroCount(dividend);
+    tmpDivisor = divisor << alignShift;
+    tmpRemainder = dividend;
+
+    /* 竖式除法, 类大数相除 */
+    for (i = 0; i <= alignShift; i++) {
+        tmpQuotient <<= 1;
+        if (tmpRemainder >= tmpDivisor) {
+            tmpRemainder -= tmpDivisor;
+            tmpQuotient += 1;
+        }
+        tmpDivisor >>= 1;
+    }
+
+    *quotient = tmpQuotient;
+    *remainder = tmpRemainder;
+
+    return;
+}
+
+OS_SEC_TEXT U64 OsU64DivGetQuotient(U64 dividend, U64 divisor)
+{
+    U64 quotient = 0;
+    U64 remainder;
+
+    OsU64Div(dividend, divisor, &quotient, &remainder);
+
+    return quotient;
+}
+
+OS_SEC_TEXT U64 OsU64DivGetRemainder(U64 dividend, U64 divisor)
+{
+    U64 quotient;
+    U64 remainder = 0;
+
+    OsU64Div(dividend, divisor, &quotient, &remainder);
+
+    return remainder;
+}
\ No newline at end of file
diff --git a/src/arch/cpu/armv7-r/common/prt_port.c b/src/arch/cpu/armv7-r/common/prt_port.c
new file mode 100755
index 0000000000000000000000000000000000000000..a8330283803e89a8af6dcea17d597f47913fc34b
--- /dev/null
+++ b/src/arch/cpu/armv7-r/common/prt_port.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version：各模式下栈初始化及任务栈初始化
+ */
+
+#include "prt_typedef.h"
+#include "prt_cpu_external.h"
+#include "prt_sys_external.h"
+
+#ifdef __thumb__
+#define ARMV7R_SPSR_INIT_VALUE      (PSR_SVC_MODE | PSR_T_THUMB | PSR_F_BIT)
+#else
+#define ARMV7R_SPSR_INIT_VALUE        (PSR_SVC_MODE | PSR_T_ARM   | PSR_F_BIT)
+#endif
+
+/* Tick中断对应的硬件定时器ID */
+// OS_SEC_DATA U32 g_tickTimerID = U32_INVALID;
+// 系统栈配置
+uint8_t abt_stack[OS_ARCH_ABT_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+uint8_t sys_stack[OS_ARCH_SYS_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+uint8_t und_stack[OS_ARCH_UND_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+uint8_t fiq_stack[OS_ARCH_FIQ_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+uint8_t irq_stack[OS_ARCH_IRQ_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+uint8_t svc_stack[OS_ARCH_SVC_STACK_SIZE] __CACHE_ALIGN OS_SEC_DATA;
+
+uintptr_t __exc_stack_top = (uintptr_t)(sys_stack + OS_ARCH_SYS_STACK_SIZE);
+uintptr_t __svc_stack_top = (uintptr_t)(svc_stack + OS_ARCH_SVC_STACK_SIZE);
+
+/*
+ * 描述: 分配核的系统栈空间
+ */
+// INIT_SEC_L4_TEXT void InitSystemSp(uintptr_t sysStackHigh, uintptr_t svcStackHigh)
+// {
+//     return;
+// }
+
+/*
+ * 描述: 获取系统栈的起始地址（低地址)
+ */
+INIT_SEC_L4_TEXT uintptr_t OsGetSysStackStart(U32 core)
+{
+    (void)core;
+    return (uintptr_t)sys_stack;
+}
+
+/*
+ * 描述: 获取系统栈的结束地址（高地址)
+ */
+INIT_SEC_L4_TEXT uintptr_t OsGetSysStackEnd(U32 core)
+{
+    (void)core;
+    return __exc_stack_top;
+}
+
+// /*
+//  * 描述: 获取系统栈的栈底（高地址)
+//  */
+// OS_SEC_L0_TEXT uintptr_t OsGetSysStackSP(U32 core)
+// {
+//     return OsGetSysStackEnd(core);
+// }
+
+INIT_SEC_L4_TEXT void *OsTskContextInit(U32 taskID, U32 stackSize, uintptr_t *topStack, uintptr_t funcTskEntry)
+{
+    (void)taskID;
+    struct TskContext *stack = (struct TskContext *)((uintptr_t)topStack + stackSize);
+
+    stack -= 1;
+    stack->reg12 = 0x12121212;
+    stack->reg11 = 0x11111111;
+    stack->reg10 = 0x10101010;
+    stack->reg9 = 0x09090909;
+    stack->reg8 = 0x08080808;
+    stack->reg7 = 0x07070707;
+    stack->reg6 = 0x06060606;
+    stack->reg5 = 0x05050505;
+    stack->reg4 = 0x04040404;
+    stack->reg3 = 0x03030303;
+    stack->reg2 = 0x02020202;
+    stack->reg1 = 0x01010101;
+    stack->reg0 = 0x00000000;
+    stack->lr = funcTskEntry;
+    stack->spsr = ARMV7R_SPSR_INIT_VALUE;
+    stack->pc = funcTskEntry;
+
+    return stack;
+}
+
+/*
+ * 描述: 从指定地址获取任务上下文
+ */
+OS_SEC_L4_TEXT void OsTskContextGet(uintptr_t saveAddr, struct TskContext *context)
+{
+    *context = *((struct TskContext *)saveAddr);
+
+    return;
+}
+
+/*
+ * 描述: 手动触发异常（EL1）
+ */
+OS_SEC_L4_TEXT void OsAsmIll(void)
+{
+    OS_EMBED_ASM("svc  0");
+}
diff --git a/src/arch/drv/CMakeLists.txt b/src/arch/drv/CMakeLists.txt
index 032beeb2e2627d7ee351a91cb4d65fbeacda8609..e8dc4cef01e94835afe528aa33c94c93222f1caa 100644
--- a/src/arch/drv/CMakeLists.txt
+++ b/src/arch/drv/CMakeLists.txt
@@ -1,3 +1,3 @@
-if(${CONFIG_OS_ARCH_ARMV8})
+if((${CONFIG_OS_ARCH_ARMV8}) OR (${CONFIG_OS_ARCH_ARMV7_R}))
     add_subdirectory(gic)
 endif()
diff --git a/src/arch/drv/gic/Kconfig b/src/arch/drv/gic/Kconfig
index fde5c2ecf2b6eaf4eed45452f6132efb061738f1..0f0e46e17f297d16b0362284ca6c17dece8d396e 100644
--- a/src/arch/drv/gic/Kconfig
+++ b/src/arch/drv/gic/Kconfig
@@ -1,4 +1,4 @@
 config INTERNAL_OS_GIC_VER
     string
     depends on OS_ARCH_ARMV8
-    default "gicv600" if (INTERNAL_OS_RASPI4)
\ No newline at end of file
+    default "gicv600" if (INTERNAL_OS_RASPI4 || INTERNAL_OS_D9_SECURE)
\ No newline at end of file
diff --git a/src/arch/drv/gic/gicv600/prt_gic_internal.h b/src/arch/drv/gic/gicv600/prt_gic_internal.h
index 0859bd124b8f4e9f28a04ffa400f44f83d25cd2f..ed9f6761b8c9cbf0c392f5693ca9967cdf177c3e 100644
--- a/src/arch/drv/gic/gicv600/prt_gic_internal.h
+++ b/src/arch/drv/gic/gicv600/prt_gic_internal.h
@@ -22,7 +22,9 @@
  * 模块间宏定义
  */
 /* 各个board有差异的中断配置 */
+#ifndef MAX_NNSPI_ID
 #define MAX_NNSPI_ID             31 // 系统可支持的最大NNSPI的中断号，为了代码归一，不支持NNSPI场景配置成MAX_PPI_ID相同
+#endif
 #define MIN_SPI_ID               32 // 系统可支持的最小SPI的中断号
 #define GICD_SPI_IROUTERN_L_ADDR (GIC_GICD_BASE + 0x6000U) // GIC亲和性配置寄存器
 
diff --git a/src/arch/include/prt_asm_arm_external.h b/src/arch/include/prt_asm_arm_external.h
index c2b16f5ad5a573070465c967826e6bc52acc1b32..29b8931e5b01a912ba6bc70c475ed4332301770e 100644
--- a/src/arch/include/prt_asm_arm_external.h
+++ b/src/arch/include/prt_asm_arm_external.h
@@ -15,10 +15,16 @@
 #ifndef PRT_ASM_ARM_EXTERNAL_H
 #define PRT_ASM_ARM_EXTERNAL_H
 
+#include <prt_buildef.h>
+
 #if defined(OS_ARCH_ARMV8)
 #include "../cpu/armv8/common/os_asm_cpu_armv8_external.h"
 #endif
 
+#if defined(OS_ARCH_ARMV7_R)
+#include "../cpu/armv7-r/common/os_asm_armv7_r_external.h"
+#endif
+
 /*
  * 描述 : stack_chk_guard支持用户传入seed写入函数宏
  *        argA argB argC 需要使用处传入三个可用寄存器
diff --git a/src/arch/include/prt_attr_external.h b/src/arch/include/prt_attr_external.h
index 4ea7cbcf28e4e03a0c8d5d8930c1f1ad398464e9..8308b79781d6e95d85bbc42eef1f8bcf50ce8f95 100644
--- a/src/arch/include/prt_attr_external.h
+++ b/src/arch/include/prt_attr_external.h
@@ -33,4 +33,8 @@
 #include "../cpu/riscv64/common/os_attr_riscv64_external.h"
 #endif
 
+#if defined(OS_ARCH_ARMV7_R)
+#include "../cpu/armv7-r/common/os_attr_armv7_r_external.h"
+#endif
+
 #endif /* PRT_ATTR_EXTERNAL_H */
diff --git a/src/arch/include/prt_cpu_external.h b/src/arch/include/prt_cpu_external.h
index 9febd82b38d0d33ce98f5592decf8653a90427b8..57a578b47c576c188365718635645e041f6cb9ff 100644
--- a/src/arch/include/prt_cpu_external.h
+++ b/src/arch/include/prt_cpu_external.h
@@ -71,4 +71,8 @@ extern void OsTickStartRegSet(U16 tickHwTimerIndex, U32 cyclePerTick);
 #include "../cpu/riscv64/common/os_cpu_riscv64_external.h"
 #endif
 
+#if defined(OS_ARCH_ARMV7_R)
+#include "../cpu/armv7-r/common/os_cpu_armv7_r_external.h"
+#endif
+
 #endif /* PRT_CPU_EXTERNAL_H */
diff --git a/src/arch/include/prt_gic_external.h b/src/arch/include/prt_gic_external.h
index 4df0f251cfade7d8a88e0fa57380fd601c00cf9e..3dd50e89cc4fca5c77eb5388a900d3fcb84d08f3 100644
--- a/src/arch/include/prt_gic_external.h
+++ b/src/arch/include/prt_gic_external.h
@@ -24,8 +24,10 @@
 #define GIC_IPRIORITY_HIGH_BIT    4
 
 #if (OS_GIC_VER == 2)
+#ifndef GIC_DIST_BASE
 #define GIC_DIST_BASE   0xff841000
-#define GIC_CPU_BASE    0xff842000
+#endif
+#define GIC_CPU_BASE    (GIC_DIST_BASE + 0x1000U)
 #define IAR_MASK        0x3FFU
 #define GICC_IAR		(GIC_CPU_BASE + 0xc)
 #define GICC_EOIR		(GIC_CPU_BASE + 0x10)
diff --git a/src/core/kernel/CMakeLists.txt b/src/core/kernel/CMakeLists.txt
index 9dae5b6f63fd16259cbc13cee9378e12c12734e3..6fe951a998e0154f549a10320c557b40080b9ba3 100644
--- a/src/core/kernel/CMakeLists.txt
+++ b/src/core/kernel/CMakeLists.txt
@@ -5,7 +5,7 @@ add_subdirectory(task)
 add_subdirectory(tick)
 add_subdirectory(timer)
 add_subdirectory(spinlock)
-if((${CONFIG_OS_ARCH_ARMV8}) OR (${CONFIG_OS_ARCH_X86_64}) OR (${CONFIG_OS_ARCH_RISCV64}))
+if((${CONFIG_OS_ARCH_ARMV8}) OR (${CONFIG_OS_ARCH_X86_64}) OR (${CONFIG_OS_ARCH_RISCV64}) OR (${CONFIG_OS_ARCH_ARMV7_R}))
     add_subdirectory(sched)
 endif()
 
diff --git a/src/include/uapi/hw/armv7-r/os_atomic_armv7_r.h b/src/include/uapi/hw/armv7-r/os_atomic_armv7_r.h
new file mode 100755
index 0000000000000000000000000000000000000000..987342192d044378cb5d11304d116331f72cfe42
--- /dev/null
+++ b/src/include/uapi/hw/armv7-r/os_atomic_armv7_r.h
@@ -0,0 +1,799 @@
+/* ----------------------------------------------------------------------------
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013-2020. All rights reserved.
+ * Description: Aarch32 Atomic HeadFile
+ * Author: Huawei LiteOS Team
+ * Create: 2013-01-01
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --------------------------------------------------------------------------- */
+
+#ifndef OS_ATOMIC_ARMV7_R_H
+#define OS_ATOMIC_ARMV7_R_H
+
+#include "prt_typedef.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+typedef S32     INT32;
+typedef S64     INT64;
+typedef bool    BOOL;
+typedef U32     UINT32;
+typedef void    VOID;
+typedef volatile INT32 Atomic;
+typedef volatile INT64 Atomic64;
+
+#define STATIC
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+    return *(volatile INT32 *)v;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+    *(volatile INT32 *)v = setVal;
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "add   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %1, [%2]\n"
+                             "sub   %1, %1, %3\n"
+                             "strex   %0, %1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "add   %0, %0, #1\n"
+                             "strex   %1, %0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "add   %0, %0, #1\n"
+                             "strex   %1, %0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "sub   %0, %0, #1\n"
+                             "strex   %1, %0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+    INT32 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "sub   %0, %0, #1\n"
+                             "strex   %1, %0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+    INT64 val;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%1]"
+                             : "=&r"(val)
+                             : "r"(v)
+                             : "cc");
+    } while (0);
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+    INT64 tmp;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %1, %H1, [%2]\n"
+                             "strexd   %0, %3, %H3, [%2]"
+                             : "=&r"(status), "=&r"(tmp)
+                             : "r"(v), "r"(setVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %1, %H1, [%2]\n"
+                             "adds   %Q1, %Q1, %Q3\n"
+                             "adc   %R1, %R1, %R3\n"
+                             "strexd   %0, %1, %H1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(addVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %1, %H1, [%2]\n"
+                             "subs   %Q1, %Q1, %Q3\n"
+                             "sbc   %R1, %R1, %R3\n"
+                             "strexd   %0, %1, %H1, [%2]"
+                             : "=&r"(status), "=&r"(val)
+                             : "r"(v), "r"(subVal)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "adds   %Q0, %Q0, #1\n"
+                             "adc   %R0, %R0, #0\n"
+                             "strexd   %1, %0, %H0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "adds   %Q0, %Q0, #1\n"
+                             "adc   %R0, %R0, #0\n"
+                             "strexd   %1, %0, %H0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "subs   %Q0, %Q0, #1\n"
+                             "sbc   %R0, %R0, #0\n"
+                             "strexd   %1, %0, %H0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+    INT64 val;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "subs   %Q0, %Q0, #1\n"
+                             "sbc   %R0, %R0, #0\n"
+                             "strexd   %1, %0, %H0, [%3]"
+                             : "=&r"(val), "=&r"(status), "+m"(*v)
+                             : "r"(v)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return val;
+}
+
+STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
+{
+    INT32 prevVal;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex   %0, [%3]\n"
+                             "strex   %1, %4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+    INT64 prevVal;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "strexd   %1, %4, %H4, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
+{
+    INT32 prevVal;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrex %0, [%3]\n"
+                             "mov %1, #0\n"
+                             "teq %0, %4\n"
+                             "strexeq %1, %5, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+    INT64 prevVal;
+    UINT32 status;
+
+    do {
+        __asm__ __volatile__("ldrexd   %0, %H0, [%3]\n"
+                             "mov   %1, #0\n"
+                             "teq   %0, %4\n"
+                             "teqeq   %H0, %H4\n"
+                             "strexdeq   %1, %5, %H5, [%3]"
+                             : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+                             : "r"(v), "r"(oldVal), "r"(val)
+                             : "cc");
+    } while (__builtin_expect(status != 0, 0));
+
+    return prevVal != oldVal;
+}
+
+OS_SEC_ALW_INLINE INLINE U64 OsLdrExd(volatile void *ptr)
+{
+    (void)ptr;
+    return 0;
+}
+
+OS_SEC_ALW_INLINE INLINE S32 OsStrExd(U64 val, volatile void *ptr)
+{
+    (void)ptr;
+    return (S32)val;
+}
+
+
+/*
+ * @brief 有符号32位变量的原子加，并返回累加后的值
+ *
+ * @par 描述
+ * 有符号32位变量的原子加，并返回累加后的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S32*, 要累加变量的地址。
+ * @param[in]       incr 类型#S32, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAdd32Rtn| PRT_AtomicFetchAndAdd32
+ */
+OS_SEC_ALW_INLINE INLINE S32 PRT_AtomicAdd32Rtn(S32 *ptr, S32 incr)
+{
+    return ArchAtomicAdd((Atomic *)ptr, incr);
+}
+
+/*
+ * @brief 无符号32位变量的原子加，并返回累加后的值
+ *
+ * @par 描述
+ * 有符号32位变量的原子加，并返回累加后的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S32*, 要累加变量的地址。
+ * @param[in]       incr 类型#S32, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU32| PRT_AtomicFetchAndAddU32
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicAddU32Rtn(U32 *ptr, U32 incr)
+{
+    return (U32)ArchAtomicAdd((Atomic *)ptr, (S32)incr);
+}
+
+
+/*
+ * @brief 有符号64位变量的原子加，并返回累加后的值
+ *
+ * @par 描述
+ * 有符号32位变量的原子加，并返回累加后的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S64*, 要累加变量的地址。
+ * @param[in]       incr 类型#S64, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAdd64Rtn| PRT_AtomicFetchAndAdd64
+ */
+OS_SEC_ALW_INLINE INLINE S64 PRT_AtomicAdd64Rtn(S64 *atomic, S64 incr)
+{
+    return ArchAtomic64Add((Atomic64 *)atomic, incr);
+}
+
+/*
+ * @brief 无符号64位变量的原子加，并返回累加后的值
+ *
+ * @par 描述
+ * 有符号64位变量的原子加，并返回累加后的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S64*, 要累加变量的地址。
+ * @param[in]       incr 类型#S64, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU64 | PRT_AtomicFetchAndAddU64
+ */
+OS_SEC_ALW_INLINE INLINE U64 PRT_AtomicAddU64Rtn(U64 *atomic, U64 incr)
+{
+    return (U64)ArchAtomic64Add((Atomic64 *)atomic, (S64)incr);
+}
+
+/*
+ * @brief 有符号32位变量的原子加
+ *
+ * @par 描述
+ * 有符号32位变量的原子加
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S32*, 要累加变量的地址。
+ * @param[in]       incr 类型#S32, 要累加的数值。
+ *
+ * @retval 无
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddS32Rtn| PRT_AtomicFetchAndAddS32
+ */
+OS_SEC_ALW_INLINE INLINE void PRT_AtomicAdd32(S32 *ptr, S32 incr)
+{
+    (void)ArchAtomicAdd((Atomic *)ptr, incr);
+}
+
+/*
+ * @brief 无符号32位变量的原子加
+ *
+ * @par 描述
+ * 有符号32位变量的原子加
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S32*, 要累加变量的地址。
+ * @param[in]       incr 类型#S32, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU32Rtn| PRT_AtomicFetchAndAddU32
+ */
+OS_SEC_ALW_INLINE INLINE void PRT_AtomicAddU32(U32 *ptr, U32 incr)
+{
+    (void)ArchAtomicAdd((Atomic *)ptr, (S32)incr);
+}
+
+/*
+ * @brief 有符号64位变量的原子加
+ *
+ * @par 描述
+ * 有符号32位变量的原子加
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S64*, 要累加变量的地址。
+ * @param[in]       incr 类型#S64, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddS64| PRT_AtomicFetchAndAddS64
+ */
+OS_SEC_ALW_INLINE INLINE void PRT_AtomicAddS64(S64 *atomic, S64 incr)
+{
+    (void)ArchAtomic64Add((Atomic64 *)atomic, incr);
+}
+
+/*
+ * @brief 无符号64位变量的原子加
+ *
+ * @par 描述
+ * 有符号64位变量的原子加
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S64*, 要累加变量的地址。
+ * @param[in]       incr 类型#S64, 要累加的数值。
+ *
+ * @retval 变量累加后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU64Rtn | PRT_AtomicFetchAndAddU64
+ */
+OS_SEC_ALW_INLINE INLINE void PRT_AtomicAddU64(U64 *atomic, U64 incr)
+{
+    (void)ArchAtomic64Add((Atomic64 *)atomic, (S64)incr);
+}
+
+
+/*
+ * @brief 32位原子交换，并返回交换前的值
+ *
+ * @par 描述
+ * 32位原子交换，并返回交换前的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U32*, 要交换变量的地址。
+ * @param[in]       newValue 类型#U32，要交换的值。
+ *
+ * @retval 变量交换前的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicSwap64
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicSwap32(U32 *ptr, U32 newValue)
+{
+    return (U32)ArchAtomicXchg32bits((Atomic *)ptr, (S32)newValue);
+}
+
+/*
+ * @brief 64位原子交换，并返回交换前的值
+ *
+ * @par 描述
+ * 64位原子交换，并返回交换前的值
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U64*, 要交换变量的地址。
+ * @param[in]       newValue 类型#U64，要交换的值。
+ *
+ * @retval 变量交换前的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicSwap64
+ */
+OS_SEC_ALW_INLINE INLINE U64 PRT_AtomicSwap64(U64 *ptr, U64 newValue)
+{
+    return (U64)ArchAtomicXchg64bits((Atomic64 *)ptr, (S64)newValue);
+}
+
+/*
+ * @brief 完成32位无符号的变量与指定内存的值比较，并在相等的情况下赋值
+ *
+ * @par 描述
+ * 完成32位无符号的变量与指定内存的值比较，并在相等的情况下赋值，相等时赋值并返回1，不相等时返回零。
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U32*, 要比较/赋值变量的地址。
+ * @param[in]       oldVal 类型#U32，要比较的值。
+ * @param[in]       newVal 类型#U32，相等时要写入的新值。
+ *
+ * @retval 1，相等并赋值
+ * @retval 0，不相等。
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicCompareAndStore64
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicCompareAndStore32(U32 *ptr, U32 oldVal, U32 newVal)
+{
+    if(ArchAtomicCmpXchg32bits((Atomic *)ptr, (INT32)oldVal, (INT32)newVal))
+    {
+        return 0;
+    }
+    else
+    {
+        return 1;
+    }
+}
+
+
+/*
+ * @brief 有符号32位变量的原子加，并返回累加前的值
+ *
+ * @par 描述
+ * 有符号32位变量的原子加，并返回累加前的值
+ * 
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#S32*, 要累加变量的地址。
+ * @param[in]       incr 类型#S32, 要累加的数值。
+ *
+ * @retval 变量累加前的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddS32| PRT_AtomicAddS32Rtn
+ */
+OS_SEC_ALW_INLINE INLINE S32 PRT_AtomicFetchAndAddS32(S32 *ptr, S32 incr){
+    return ArchAtomicAdd((Atomic *)ptr, incr);
+}
+
+/*
+ * @brief 无符号的32位原子或操作
+ *
+ * @par 描述
+ * 无符号的32位原子或操作
+ * 
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  addr 类型#U32*, 要执行逻辑或变量的地址。
+ * @param[in]       incr 类型#U32, 要逻辑或的值。
+ *
+ * @retval 执行或操作以后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicOr(U32 *addr, U32 val)
+{
+    U32 ret = *addr;
+
+    *addr = ret | val;
+
+    return ret;
+}
+
+/*
+ * @brief 无符号的32位原子与操作
+ *
+ * @par 描述
+ * 无符号的32位原子与操作
+ * 
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  addr 类型#U32*, 要执行逻辑与变量的地址。
+ * @param[in]       incr 类型#U32, 要逻辑与的值。
+ *
+ * @retval 执行或操作以后的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicAnd(U32 *addr, U32 val)
+{
+    U32 ret = *addr;
+
+    *addr = ret & val;
+
+    return ret;
+}
+
+/*
+ * @brief 完成64位无符号的变量与指定内存的值比较，并在相等的情况下赋值
+ *
+ * @par 描述
+ * 完成64位无符号的变量与指定内存的值比较，并在相等的情况下赋值，相等时赋值并返回1，不相等时返回零。
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U64*, 要比较/赋值变量的地址。
+ * @param[in]       oldVal 类型#U64，要比较的值。
+ * @param[in]       newVal 类型#U64，相等时要写入的新值。
+ *
+ * @retval 1，相等并赋值
+ * @retval 0，不相等。
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicCompareAndStore64
+ */
+OS_SEC_ALW_INLINE INLINE U64 PRT_AtomicCompareAndStore64(U64 *ptr, U64 oldVal, U64 newVal)
+{
+    if(ArchAtomicCmpXchg64bits((Atomic64 *)ptr, (INT64)newVal, (INT64)oldVal)){
+        return 0;
+    }
+    return 1;
+}
+
+/*
+ * @brief 无符号32位变量的原子加，并返回累加前的值
+ *
+ * @par 描述
+ * 无符号32位变量的原子加，并返回累加前的值
+ * 
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U32*, 要累加变量的地址。
+ * @param[in]       incr 类型#U32, 要累加的数值。
+ *
+ * @retval 变量累加前的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU32| PRT_AtomicAddU32Rtn
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_AtomicFetchAndAddU32(U32 *ptr, U32 incr)
+{
+    // OsArmPrefecthw(ptr);
+    return (U32)ArchAtomicAdd((Atomic *)ptr, (S32)incr);
+}
+
+/*
+ * @brief 无符号64位变量的原子加，并返回累加前的值
+ *
+ * @par 描述
+ * 无符号64位变量的原子加，并返回累加前的值
+ * 
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U64*, 要累加变量的地址。
+ * @param[in]       incr 类型#U64, 要累加的数值。
+ *
+ * @retval 变量累加前的值
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicAddU64| PRT_AtomicAddU64Rtn
+ */
+OS_SEC_ALW_INLINE INLINE U64 PRT_AtomicFetchAndAddU64(U64 *ptr, U64 incr)
+{
+    // OsArmPrefecthw(ptr);
+    return (U64)ArchAtomic64Add((Atomic64 *)ptr, (S64)incr);
+}
+
+/*
+ * @brief 无符号64位原子读
+ *
+ * @par 描述
+ * 无符号64位原子读
+ *
+ * @attention
+ * 在部分的CPU或DSP上用特殊指令实现，性能较高。
+ *
+ * @param[in, out]  ptr 类型#U64*, 要读取的地址。
+ *
+ * @retval 读取的数据
+ * @par 依赖
+ * <ul><li>prt_atomic.h：该接口声明所在的头文件。</li></ul>
+ * @see PRT_AtomicRead32 | PRT_AtomicReadU32 | PRT_AtomicRead64
+ */
+OS_SEC_ALW_INLINE INLINE U64 PRT_AtomicReadU64(U64 *ptr)
+{
+    return ArchAtomic64Read((const Atomic64 *)ptr);
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* OS_ATOMIC_ARMV7_R_H */
+
diff --git a/src/include/uapi/hw/armv7-r/os_cpu_armv7_r.h b/src/include/uapi/hw/armv7-r/os_cpu_armv7_r.h
new file mode 100755
index 0000000000000000000000000000000000000000..aa56c1e19b650e2aad4ef3d0685248c753484441
--- /dev/null
+++ b/src/include/uapi/hw/armv7-r/os_cpu_armv7_r.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2024, Greater Bay Area National Center of Technology Innovation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:  任务切换接口及中断处理函数实现
+ * Date           Author       Notes
+ * 2025-06-13     WuPeifeng    the first version：cpu架构相关的外部头文件
+ */
+
+#ifndef OS_CPU_ARMV7_R_H
+#define OS_CPU_ARMV7_R_H
+
+#include "prt_buildef.h"
+#include "prt_typedef.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+/*
+ * 任务上下文的结构体定义。
+ */
+struct TskContext {
+    uintptr_t reg12;
+    uintptr_t reg11;
+    uintptr_t reg10;
+    uintptr_t reg9;
+    uintptr_t reg8;
+    uintptr_t reg7;
+    uintptr_t reg6;
+    uintptr_t reg5;
+    uintptr_t reg4;
+    uintptr_t reg3;
+    uintptr_t reg2;
+    uintptr_t reg1;
+    uintptr_t reg0;
+    uintptr_t lr;
+    uintptr_t pc;
+    uintptr_t spsr;
+};
+
+/*
+ *  描述: 读取当前核号
+ */
+OS_SEC_ALW_INLINE INLINE U32 OsGetCoreID(void)
+{
+    return 0;//单核运行，不需要获取核号
+}
+
+/*
+ * 获取当前核ID
+ */
+OS_SEC_ALW_INLINE INLINE U32 PRT_GetCoreID(void)
+{
+    return OsGetCoreID();
+}
+
+#define PRT_DSB() OS_EMBED_ASM("DSB sy" : : : "memory")
+#define PRT_DMB() OS_EMBED_ASM("DMB sy" : : : "memory")
+#define PRT_ISB() OS_EMBED_ASM("ISB" : : : "memory")
+
+#define PRT_MemWait PRT_DSB
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+#endif /* OS_CPU_ARMV7_R_H */
diff --git a/src/include/uapi/hw/armv7-r/os_exc_armv7_r.h b/src/include/uapi/hw/armv7-r/os_exc_armv7_r.h
new file mode 100755
index 0000000000000000000000000000000000000000..1b022f721ce86827d08f0bf643d601f2091e30c6
--- /dev/null
+++ b/src/include/uapi/hw/armv7-r/os_exc_armv7_r.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved.
+ *
+ * UniProton is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ * Create: 2022-11-22
+ * Description: 异常模块的对外头文件。
+ */
+#ifndef ARMV7_R_EXC_H
+#define ARMV7_R_EXC_H
+
+#include "prt_typedef.h"
+#include "prt_sys.h"
+#if defined(OS_OPTION_HAVE_FPU)
+#include "os_cpu_armv7_r.h"
+#endif
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+struct ExcRegInfo {
+    uintptr_t regCPSR; /**< Current program status register (CPSR) */
+    uintptr_t R0;      /**< Register R0 */
+    uintptr_t R1;      /**< Register R1 */
+    uintptr_t R2;      /**< Register R2 */
+    uintptr_t R3;      /**< Register R3 */
+    uintptr_t R4;      /**< Register R4 */
+    uintptr_t R5;      /**< Register R5 */
+    uintptr_t R6;      /**< Register R6 */
+    uintptr_t R7;      /**< Register R7 */
+    uintptr_t R8;      /**< Register R8 */
+    uintptr_t R9;      /**< Register R9 */
+    uintptr_t R10;     /**< Register R10 */
+    uintptr_t R11;     /**< Register R11 */
+    uintptr_t R12;     /**< Register R12 */
+    uintptr_t SP;      /**< Stack pointer */
+    uintptr_t LR;      /**< Program returning address. */
+    uintptr_t PC;      /**< PC pointer of the exceptional function */
+};
+
+/*
+ * CpuTick结构体类型。
+ *
+ * 用于记录64位的cycle计数值。
+ */
+struct SreCpuTick {
+    U32 cntHi; /* cycle计数高32位 */
+    U32 cntLo; /* cycle计数低32位 */
+};
+
+/*
+ * 异常信息结构体
+ */
+struct ExcInfo {
+    // OS版本号
+    char osVer[OS_SYS_OS_VER_LEN];
+    // 产品版本号
+    char appVer[OS_SYS_APP_VER_LEN];
+    // 异常原因
+    U32 excCause;
+    // 异常前的线程类型
+    U32 threadType;
+    // 异常前的线程ID, 该ID组成threadID = LTID
+    U32 threadId;
+    // 字节序
+    U16 byteOrder;
+    // CPU类型
+    U16 cpuType;
+    // CPU ID
+    U32 coreId;
+    // CPU Tick
+    struct SreCpuTick cpuTick;
+    // 异常嵌套计数
+    U32 nestCnt;
+    // 致命错误码，发生致命错误时有效
+    U32 fatalErrNo;
+    // 异常前栈指针
+    uintptr_t sp;
+    // 异常前栈底
+    uintptr_t stackBottom;
+    // 异常发生时的核内寄存器上下文信息
+    struct ExcRegInfo regInfo;
+};
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cpluscplus */
+#endif /* __cpluscplus */
+
+#endif /* ARMV7_R_EXC_H */
diff --git a/src/include/uapi/prt_atomic.h b/src/include/uapi/prt_atomic.h
index ecda7f4d25aa10d192544c75d18e0a3803d34b32..17a7c706b328249699e84cb0e7dc74519d820503 100644
--- a/src/include/uapi/prt_atomic.h
+++ b/src/include/uapi/prt_atomic.h
@@ -25,6 +25,10 @@
 #include "hw/armv8/os_atomic_armv8.h"
 #endif
 
+#if(OS_HARDWARE_PLATFORM == OS_CORTEX_R5)
+#include "hw/armv7-r/os_atomic_armv7_r.h"
+#endif
+
 #ifdef __cplusplus
 #if __cplusplus
 extern "C" {
diff --git a/src/include/uapi/prt_buildef_common.h b/src/include/uapi/prt_buildef_common.h
index 0389552d3b70a5d4c862107e1508c058d54b7fa3..a49922164ca99879402bd169347e1d2882562c0b 100755
--- a/src/include/uapi/prt_buildef_common.h
+++ b/src/include/uapi/prt_buildef_common.h
@@ -25,7 +25,8 @@
 #define OS_ARMV8            0x02
 #define OS_X86_64           0x03
 #define OS_RISCV64          0x04
-#define OS_PLATFORM_INVALID 0x05
+#define OS_CORTEX_R5        0x05
+#define OS_PLATFORM_INVALID 0x06
 
 /* To define OS_CPU_TYPE */
 /* 编译器有个bug, 未定义的宏的数值默认是0，所以不用使用'0' */
@@ -44,7 +45,8 @@
 #define OS_RV64_VISIONFIVE2 0x0d
 #define OS_KP920_LITE       0x0e
 #define OS_HI3095           0x0f
-#define OS_CPU_TYPE_INVALID 0x10
+#define OS_D9_SECURE        0x10
+#define OS_CPU_TYPE_INVALID 0x11
 
 #ifndef INIT_SEC_L4_TEXT
 #define INIT_SEC_L4_TEXT 
diff --git a/src/include/uapi/prt_exc.h b/src/include/uapi/prt_exc.h
index 7bc41f64b46e65cc825016543570f4d86a7b21b1..f2118e181a3e904a3d50b0a99f70b924ade06b2d 100644
--- a/src/include/uapi/prt_exc.h
+++ b/src/include/uapi/prt_exc.h
@@ -34,6 +34,10 @@
 #include "./hw/riscv64/os_exc_riscv64.h"
 #endif
 
+#if (OS_HARDWARE_PLATFORM == OS_CORTEX_R5)
+#include "./hw/armv7-r/os_exc_armv7_r.h"
+#endif
+
 #ifdef __cplusplus
 #if __cplusplus
 extern "C" {
diff --git a/src/include/uapi/prt_task.h b/src/include/uapi/prt_task.h
index 6a81aea25cc94da600b4b8d922de6f32ecba7be2..2cdec005a583f57734bb88c88d359b8acee0f9ff 100644
--- a/src/include/uapi/prt_task.h
+++ b/src/include/uapi/prt_task.h
@@ -35,6 +35,10 @@
 #include "./hw/riscv64/os_cpu_riscv64.h"
 #endif
 
+#if (OS_HARDWARE_PLATFORM == OS_CORTEX_R5)
+#include "./hw/armv7-r/os_cpu_armv7_r.h"
+#endif
+
 #ifdef __cplusplus
 #if __cplusplus
 extern "C" {
diff --git a/src/utility/log/prt_log_internal.h b/src/utility/log/prt_log_internal.h
index 81f51116deadcf93e010075a02a8f0a3ae52f0b9..a048efc8b34b043128ad992c924a5659a4567824 100644
--- a/src/utility/log/prt_log_internal.h
+++ b/src/utility/log/prt_log_internal.h
@@ -38,7 +38,7 @@ struct logHeader {
     U8 logContent[];
 };
 
-#if defined(OS_ARCH_ARMV7_M)
+#if defined(OS_ARCH_ARMV7_M) || defined(OS_ARCH_ARMV7_R)
     #define STORE_FENCE() __asm__ __volatile__ ("dmb sy" : : : "memory");
     #define M_FENCE() __asm__ __volatile__ ("dmb sy" : : : "memory");
     #define LOAD_FENCE() __asm__ __volatile__ ("dmb sy" : : : "memory");