diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 4ca02f1927f70d327ddb6aed33d90e87095dbd2e..98b37340376bcc3f6724ea0b6dd79f24f84601c3 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -36,7 +36,6 @@ static inline void harden_branch_predictor(void)
 #define UDBG_BUS	(1 << 4)
 
 extern unsigned int user_debug;
-extern int nospectre_v2;
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
index b59c4d8ea7627375d2e0cdadfec2f7599f4c177b..8bc7a2d6d6c7f96cda00741fe76faa148cee7b51 100644
--- a/arch/arm/mm/proc-v7-bugs.c
+++ b/arch/arm/mm/proc-v7-bugs.c
@@ -9,19 +9,6 @@
 #include <asm/spectre.h>
 #include <asm/system_misc.h>
 
-/*
- * 32-bit ARM spectre hardening, enabled by default, can be disabled via boot
- * cmdline param 'nospectre_v2' to avoid performance regression.
- */
-int nospectre_v2 __read_mostly;
-
-static int __init nospectre_v2_setup(char *str)
-{
-	nospectre_v2 = 1;
-	return 0;
-}
-early_param("nospectre_v2", nospectre_v2_setup);
-
 #ifdef CONFIG_ARM_PSCI
 static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
 {
@@ -131,11 +118,6 @@ static void cpu_v7_spectre_v2_init(void)
 {
 	unsigned int state, method = 0;
 
-	if (nospectre_v2) {
-		pr_info_once("Spectre v2: hardening is disabled\n");
-		return;
-	}
-
 	switch (read_cpuid_part()) {
 	case ARM_CPU_PART_CORTEX_A8:
 	case ARM_CPU_PART_CORTEX_A9:
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d1bbbb5dae7d37a072331eaafb52fa547cd403fb..193c7aeb670391ff27b764d9667baa1ffa1e4992 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -113,23 +113,14 @@ ENTRY(cpu_v7_hvc_switch_mm)
 	b	cpu_v7_switch_mm
 ENDPROC(cpu_v7_hvc_switch_mm)
 #endif
-
 ENTRY(cpu_v7_iciallu_switch_mm)
-	ldr_l r3, nospectre_v2
-	cmp r3, #1
-	beq 1f
 	mov	r3, #0
 	mcr	p15, 0, r3, c7, c5, 0		@ ICIALLU
-1:
 	b	cpu_v7_switch_mm
 ENDPROC(cpu_v7_iciallu_switch_mm)
 ENTRY(cpu_v7_bpiall_switch_mm)
-	ldr_l r3, nospectre_v2
-	cmp r3, #1
-	beq 1f
 	mov	r3, #0
 	mcr	p15, 0, r3, c7, c5, 6		@ flush BTAC/BTB
-1:
 	b	cpu_v7_switch_mm
 ENDPROC(cpu_v7_bpiall_switch_mm)