diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 39e7a63fd6b9a7c45229ec59376c5279ea3ea3ef..414bfc057f077319f052e7f634df45997fee429c 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -294,8 +294,11 @@ static struct device_attribute format_attr_##_var = \ DEFINE_UNCORE_FORMAT_ATTR(event12, event, "config:0-7,32-35"); DEFINE_UNCORE_FORMAT_ATTR(event14, event, "config:0-7,32-35,59-60"); /* F17h+ DF */ DEFINE_UNCORE_FORMAT_ATTR(event14v2, event, "config:0-7,32-37"); /* PerfMonV2 DF */ +DEFINE_UNCORE_FORMAT_ATTR(event14f18h, event, "config:0-7,32-35,61-62"); /* F18h DF */ DEFINE_UNCORE_FORMAT_ATTR(event8, event, "config:0-7"); /* F17h+ L3, PerfMonV2 UMC */ DEFINE_UNCORE_FORMAT_ATTR(umask8, umask, "config:8-15"); +DEFINE_UNCORE_FORMAT_ATTR(umask10f18h, umask, "config:8-17"); /* F18h M4h DF */ +DEFINE_UNCORE_FORMAT_ATTR(umask12f18h, umask, "config:8-19"); /* F18h M6h DF */ DEFINE_UNCORE_FORMAT_ATTR(umask12, umask, "config:8-15,24-27"); /* PerfMonV2 DF */ DEFINE_UNCORE_FORMAT_ATTR(coreid, coreid, "config:42-44"); /* F19h L3 */ DEFINE_UNCORE_FORMAT_ATTR(slicemask, slicemask, "config:48-51"); /* F17h L3 */ @@ -708,8 +711,19 @@ int amd_uncore_df_ctx_init(struct amd_uncore *uncore, unsigned int cpu) if (pmu_version >= 2) { *df_attr++ = &format_attr_event14v2.attr; *df_attr++ = &format_attr_umask12.attr; - } else if (boot_cpu_data.x86 >= 0x17) { + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && + boot_cpu_data.x86 >= 0x17) { *df_attr = &format_attr_event14.attr; + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && + boot_cpu_data.x86 == 0x18) { + *df_attr++ = &format_attr_event14f18h.attr; + if (boot_cpu_data.x86_model == 0x4 || + boot_cpu_data.x86_model == 0x5) + *df_attr++ = &format_attr_umask10f18h.attr; + else if (boot_cpu_data.x86_model == 0x6 || + boot_cpu_data.x86_model == 0x7 || + boot_cpu_data.x86_model == 0x10) + *df_attr++ = &format_attr_umask12f18h.attr; } pmu->ctx = alloc_percpu(struct amd_uncore_ctx *);