From 9cc93f1a010e19015f8a453059deb62384c2546b Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Fri, 28 May 2021 16:14:17 +0800
Subject: [PATCH 01/20] x86/cstate: Allow ACPI C1 FFH MWAIT use on Hygon
 systems

mainline inclusion
from mainline-v5.14-rc1
commit 280b68a3b3b96b027fcdeb5a3916a8e2aaf84d03
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

Reference: https://git.kernel.org/torvalds/c/280b68a3b3b96b027fcdeb5a3916a8e2aaf84d03

---------------------------

commit 280b68a3b3b96b027fcdeb5a3916a8e2aaf84d03 upstream.

Hygon systems support the MONITOR/MWAIT instructions and these can be
used for ACPI C1 in the same way as on AMD and Intel systems.

The BIOS declares a C1 state in _CST to use FFH and CPUID_Fn00000005_EDX
is non-zero on Hygon systems.

Allow ffh_cstate_init() to succeed on Hygon systems to default using FFH
MWAIT instead of HALT for ACPI C1.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20210528081417.31474-1-puwen@hygon.cn
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/acpi/cstate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index bd4a50db8da3..e1091aa7facd 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -220,7 +220,8 @@ static int __init ffh_cstate_init(void)
 	struct cpuinfo_x86 *c = &boot_cpu_data;
 
 	if (c->x86_vendor != X86_VENDOR_INTEL &&
-	    c->x86_vendor != X86_VENDOR_AMD)
+	    c->x86_vendor != X86_VENDOR_AMD &&
+	    c->x86_vendor != X86_VENDOR_HYGON)
 		return -1;
 
 	cpu_cstate_entry = alloc_percpu(struct cstate_entry);
-- 
Gitee


From 2b1b5c1d39e9a44ebe472f02306957cc2cb9bf8b Mon Sep 17 00:00:00 2001
From: Yazen Ghannam <yazen.ghannam@amd.com>
Date: Tue, 18 Oct 2022 10:36:30 -0500
Subject: [PATCH 02/20] EDAC/mc_sysfs: Increase legacy channel support to 12

mainline inclusion
from mainline-v6.2-rc1
commit 25836ce1df827cb4830291cb2325067efb46753a
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

Reference: https://git.kernel.org/torvalds/c/25836ce1df827cb4830291cb2325067efb46753a

---------------------------

commit 25836ce1df827cb4830291cb2325067efb46753a upstream.

Newer AMD systems, such as Genoa, can support up to 12 channels per EDAC
"mc" device. These are detected by the device's EDAC module, and the
current EDAC interface is properly enumerated. However, the legacy EDAC
sysfs interface provides device attributes only for channels 0 to 7.
Therefore, channels 8 to 11 will not be visible in the legacy interface.
This was overlooked in the initial support for AMD Genoa.

Add additional device attributes so that up to 12 channels are visible
in the legacy EDAC sysfs interface.

Fixes: e2be5955a886 ("EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh")
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20221018153630.14664-1-yazen.ghannam@amd.com
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/edac_mc_sysfs.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index 2f9f1e74bb35..4fe4985e7e34 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -298,6 +298,14 @@ DEVICE_CHANNEL(ch6_dimm_label, S_IRUGO | S_IWUSR,
 	channel_dimm_label_show, channel_dimm_label_store, 6);
 DEVICE_CHANNEL(ch7_dimm_label, S_IRUGO | S_IWUSR,
 	channel_dimm_label_show, channel_dimm_label_store, 7);
+DEVICE_CHANNEL(ch8_dimm_label, S_IRUGO | S_IWUSR,
+	channel_dimm_label_show, channel_dimm_label_store, 8);
+DEVICE_CHANNEL(ch9_dimm_label, S_IRUGO | S_IWUSR,
+	channel_dimm_label_show, channel_dimm_label_store, 9);
+DEVICE_CHANNEL(ch10_dimm_label, S_IRUGO | S_IWUSR,
+	channel_dimm_label_show, channel_dimm_label_store, 10);
+DEVICE_CHANNEL(ch11_dimm_label, S_IRUGO | S_IWUSR,
+	channel_dimm_label_show, channel_dimm_label_store, 11);
 
 /* Total possible dynamic DIMM Label attribute file table */
 static struct attribute *dynamic_csrow_dimm_attr[] = {
@@ -309,6 +317,10 @@ static struct attribute *dynamic_csrow_dimm_attr[] = {
 	&dev_attr_legacy_ch5_dimm_label.attr.attr,
 	&dev_attr_legacy_ch6_dimm_label.attr.attr,
 	&dev_attr_legacy_ch7_dimm_label.attr.attr,
+	&dev_attr_legacy_ch8_dimm_label.attr.attr,
+	&dev_attr_legacy_ch9_dimm_label.attr.attr,
+	&dev_attr_legacy_ch10_dimm_label.attr.attr,
+	&dev_attr_legacy_ch11_dimm_label.attr.attr,
 	NULL
 };
 
@@ -329,6 +341,14 @@ DEVICE_CHANNEL(ch6_ce_count, S_IRUGO,
 		   channel_ce_count_show, NULL, 6);
 DEVICE_CHANNEL(ch7_ce_count, S_IRUGO,
 		   channel_ce_count_show, NULL, 7);
+DEVICE_CHANNEL(ch8_ce_count, S_IRUGO,
+		   channel_ce_count_show, NULL, 8);
+DEVICE_CHANNEL(ch9_ce_count, S_IRUGO,
+		   channel_ce_count_show, NULL, 9);
+DEVICE_CHANNEL(ch10_ce_count, S_IRUGO,
+		   channel_ce_count_show, NULL, 10);
+DEVICE_CHANNEL(ch11_ce_count, S_IRUGO,
+		   channel_ce_count_show, NULL, 11);
 
 /* Total possible dynamic ce_count attribute file table */
 static struct attribute *dynamic_csrow_ce_count_attr[] = {
@@ -340,6 +360,10 @@ static struct attribute *dynamic_csrow_ce_count_attr[] = {
 	&dev_attr_legacy_ch5_ce_count.attr.attr,
 	&dev_attr_legacy_ch6_ce_count.attr.attr,
 	&dev_attr_legacy_ch7_ce_count.attr.attr,
+	&dev_attr_legacy_ch8_ce_count.attr.attr,
+	&dev_attr_legacy_ch9_ce_count.attr.attr,
+	&dev_attr_legacy_ch10_ce_count.attr.attr,
+	&dev_attr_legacy_ch11_ce_count.attr.attr,
 	NULL
 };
 
-- 
Gitee


From 92cff2f9551b377bf7b7628e2dec638df7a9def2 Mon Sep 17 00:00:00 2001
From: Muralidhara M K <muralimk@amd.com>
Date: Fri, 27 Jan 2023 15:16:01 +0000
Subject: [PATCH 03/20] x86/MCE/AMD: Use an u64 for bank_map

stable inclusion
from stable-v5.10.180
commit 4c1cdec319b9aadb65737c3eb1f5cb74bd6aa156
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

Reference: https://git.kernel.org/torvalds/c/4c1cdec319b9aadb65737c3eb1f5cb74bd6aa156

---------------------------

commit 4c1cdec319b9aadb65737c3eb1f5cb74bd6aa156 upstream.

Thee maximum number of MCA banks is 64 (MAX_NR_BANKS), see

  a0bc32b3cacf ("x86/mce: Increase maximum number of banks to 64").

However, the bank_map which contains a bitfield of which banks to
initialize is of type unsigned int and that overflows when those bit
numbers are >= 32, leading to UBSAN complaining correctly:

  UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/mce/amd.c:1365:38
  shift exponent 32 is too large for 32-bit type 'int'

Change the bank_map to a u64 and use the proper BIT_ULL() macro when
modifying bits in there.

  [ bp: Rewrite commit message. ]

Fixes: a0bc32b3cacf ("x86/mce: Increase maximum number of banks to 64")
Signed-off-by: Muralidhara M K <muralimk@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127151601.1068324-1-muralimk@amd.com
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/cpu/mce/amd.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 3217af483acc..78349b7e481d 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -235,10 +235,10 @@ static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
  * A list of the banks enabled on each logical CPU. Controls which respective
  * descriptors to initialize later in mce_threshold_create_device().
  */
-static DEFINE_PER_CPU(unsigned int, bank_map);
+static DEFINE_PER_CPU(u64, bank_map);
 
 /* Map of banks that have more than MCA_MISC0 available. */
-static DEFINE_PER_CPU(u32, smca_misc_banks_map);
+static DEFINE_PER_CPU(u64, smca_misc_banks_map);
 
 static void amd_threshold_interrupt(void);
 static void amd_deferred_error_interrupt(void);
@@ -267,7 +267,7 @@ static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
 		return;
 
 	if (low & MASK_BLKPTR_LO)
-		per_cpu(smca_misc_banks_map, cpu) |= BIT(bank);
+		per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank);
 
 }
 
@@ -528,7 +528,7 @@ static u32 smca_get_block_address(unsigned int bank, unsigned int block,
 	if (!block)
 		return MSR_AMD64_SMCA_MCx_MISC(bank);
 
-	if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank)))
+	if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank)))
 		return 0;
 
 	return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
@@ -572,7 +572,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 	int new;
 
 	if (!block)
-		per_cpu(bank_map, cpu) |= (1 << bank);
+		per_cpu(bank_map, cpu) |= BIT_ULL(bank);
 
 	memset(&b, 0, sizeof(b));
 	b.cpu			= cpu;
@@ -884,7 +884,7 @@ static void amd_threshold_interrupt(void)
 		return;
 
 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
-		if (!(per_cpu(bank_map, cpu) & (1 << bank)))
+		if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))
 			continue;
 
 		first_block = bp[bank]->blocks;
@@ -1361,7 +1361,7 @@ int mce_threshold_create_device(unsigned int cpu)
 		return -ENOMEM;
 
 	for (bank = 0; bank < numbanks; ++bank) {
-		if (!(this_cpu_read(bank_map) & (1 << bank)))
+		if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
 			continue;
 		err = threshold_create_bank(bp, cpu, bank);
 		if (err) {
-- 
Gitee


From 0f1ef9855c4d1ee9b570b630b6b9cad99cd9b71c Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:08:04 +0800
Subject: [PATCH 04/20] x86/cpu/hygon: Modify the CPU topology deriving method
 for Hygon

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Hygon processors before model 4h have not use the CPUID leaf 0xB, so use
commit e0ceeae708ce ("x86/CPU/hygon: Fix phys_proc_id calculation logic
for multi-die processors") to derive the socket ID when running on host.
If kernel running on guest, use the hypervisor's default.

From model 4h, Hygon processors use CPUID leaf 0xB to identify SMT and
CORE level types, so use function detect_extended_topology() to derive
the core ID, socket ID and APIC ID. But still set __max_die_per_package
to nodes_per_socket because of lacking the DIE level type.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/cpu/hygon.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 13f8a2164deb..90bbfcd5edee 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -81,16 +81,25 @@ static void hygon_get_topology(struct cpuinfo_x86 *c)
 		if (smp_num_siblings > 1)
 			c->x86_max_cores /= smp_num_siblings;
 
-		/*
-		 * In case leaf B is available, use it to derive
-		 * topology information.
-		 */
-		err = detect_extended_topology(c);
-		if (!err)
-			c->x86_coreid_bits = get_count_order(c->x86_max_cores);
-
-		/* Socket ID is ApicId[6] for these processors. */
-		c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
+		if (c->x86_model < 0x4 &&
+		    !boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
+			/*
+			 * Socket ID is ApicId[6] for the processors with
+			 * model < 0x4 when running on host.
+			 */
+			c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
+		} else {
+			/*
+			 * In case leaf 0xB is available, use it to derive
+			 * topology information.
+			 */
+			err = detect_extended_topology(c);
+			if (!err) {
+				c->x86_coreid_bits =
+					get_count_order(c->x86_max_cores);
+				__max_die_per_package = nodes_per_socket;
+			}
+		}
 
 		cacheinfo_hygon_init_llc_id(c, cpu);
 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
-- 
Gitee


From 3f893ab52f9b241e654b92faced639e2cc4a6b78 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:10:38 +0800
Subject: [PATCH 05/20] x86/microcode/hygon: Add microcode loading support for
 Hygon processors

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add support for loading Hygon microcode, which is compatible with AMD one.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 Documentation/x86/microcode.rst      | 13 ++++++-
 arch/x86/Kconfig                     | 21 +++++++----
 arch/x86/include/asm/microcode.h     | 12 +++++++
 arch/x86/kernel/cpu/microcode/amd.c  | 52 +++++++++++++++++++++++-----
 arch/x86/kernel/cpu/microcode/core.c | 22 +++++++++++-
 5 files changed, 104 insertions(+), 16 deletions(-)

diff --git a/Documentation/x86/microcode.rst b/Documentation/x86/microcode.rst
index a320d37982ed..1cc734412397 100644
--- a/Documentation/x86/microcode.rst
+++ b/Documentation/x86/microcode.rst
@@ -34,6 +34,8 @@ on Intel:
   kernel/x86/microcode/GenuineIntel.bin
 on AMD  :
   kernel/x86/microcode/AuthenticAMD.bin
+on Hygon:
+  kernel/x86/microcode/HygonGenuine.bin
 
 During BSP (BootStrapping Processor) boot (pre-SMP), the kernel
 scans the microcode file in the initrd. If microcode matching the
@@ -68,6 +70,10 @@ here for future reference only).
   cd $TMPDIR
   mkdir -p $DSTDIR
 
+  if [ -d /lib/firmware/hygon-ucode ]; then
+          cat /lib/firmware/hygon-ucode/microcode_hygon*.bin > $DSTDIR/HygonGenuine.bin
+  fi
+
   if [ -d /lib/firmware/amd-ucode ]; then
           cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
   fi
@@ -119,7 +125,8 @@ currently supported.
 
 Here's an example::
 
-  CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
+  CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 \
+    amd-ucode/microcode_amd_fam15h.bin hygon-ucode/microcode_hygon_fam18h.bin"
   CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
 
 This basically means, you have the following tree structure locally::
@@ -129,6 +136,10 @@ This basically means, you have the following tree structure locally::
   ...
   |   |-- microcode_amd_fam15h.bin
   ...
+  |-- hygon-ucode
+  ...
+  |   |-- microcode_hygon_fam18h.bin
+  ...
   |-- intel-ucode
   ...
   |   |-- 06-3a-09
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a592417c9521..5bdf36c0d789 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1299,14 +1299,14 @@ config X86_REBOOTFIXUPS
 config MICROCODE
 	bool "CPU microcode loading support"
 	default y
-	depends on CPU_SUP_AMD || CPU_SUP_INTEL
+	depends on CPU_SUP_AMD || CPU_SUP_INTEL || CPU_SUP_HYGON
 	help
-	  If you say Y here, you will be able to update the microcode on
-	  Intel and AMD processors. The Intel support is for the IA32 family,
+	  If you say Y here, you will be able to update the microcode on Intel,
+	  AMD and Hygon processors. The Intel support is for the IA32 family,
 	  e.g. Pentium Pro, Pentium II, Pentium III, Pentium 4, Xeon etc. The
-	  AMD support is for families 0x10 and later. You will obviously need
-	  the actual microcode binary data itself which is not shipped with
-	  the Linux kernel.
+	  AMD support is for families 0x10 and later. The Hygon support is for
+	  families 0x18 and later. You will obviously need the actual microcode
+	  binary data itself which is not shipped with the Linux kernel.
 
 	  The preferred method to load microcode from a detached initrd is described
 	  in Documentation/x86/microcode.rst. For that you need to enable
@@ -1336,6 +1336,15 @@ config MICROCODE_AMD
 	  If you select this option, microcode patch loading support for AMD
 	  processors will be enabled.
 
+config MICROCODE_HYGON
+	bool "Hygon microcode loading support"
+	depends on CPU_SUP_HYGON && MICROCODE
+	default MICROCODE
+	select MICROCODE_AMD
+	help
+	  If you select this option, microcode patch loading support for Hygon
+	  processors will be enabled.
+
 config MICROCODE_OLD_INTERFACE
 	bool "Ancient loading interface (DEPRECATED)"
 	default n
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 015fb7ca4d6a..29563f76f1b5 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -80,6 +80,12 @@ static inline struct microcode_ops * __init init_amd_microcode(void)
 static inline void __exit exit_amd_microcode(void) {}
 #endif
 
+#ifdef CONFIG_MICROCODE_HYGON
+extern const struct microcode_ops * __init init_hygon_microcode(void);
+#else
+#define init_hygon_microcode()	NULL
+#endif
+
 #define MAX_UCODE_COUNT 128
 
 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
@@ -89,6 +95,9 @@ static inline void __exit exit_amd_microcode(void) {}
 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
+#define CPUID_HYGON1 QCHAR('H', 'y', 'g', 'o')
+#define CPUID_HYGON2 QCHAR('n', 'G', 'e', 'n')
+#define CPUID_HYGON3 QCHAR('u', 'i', 'n', 'e')
 
 #define CPUID_IS(a, b, c, ebx, ecx, edx)	\
 		(!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
@@ -115,6 +124,9 @@ static inline int x86_cpuid_vendor(void)
 	if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
 		return X86_VENDOR_AMD;
 
+	if (CPUID_IS(CPUID_HYGON1, CPUID_HYGON2, CPUID_HYGON3, ebx, ecx, edx))
+		return X86_VENDOR_HYGON;
+
 	return X86_VENDOR_UNKNOWN;
 }
 
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 234a96f25248..2a38f5e59a40 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -464,11 +464,14 @@ apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_p
 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family)
 {
 #ifdef CONFIG_X86_64
-	char fw_name[36] = "amd-ucode/microcode_amd.bin";
+	char fw_name[40] = "amd-ucode/microcode_amd.bin";
 
-	if (family >= 0x15)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD && family >= 0x15)
 		snprintf(fw_name, sizeof(fw_name),
 			 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
+	else if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+		snprintf(fw_name, sizeof(fw_name),
+			 "hygon-ucode/microcode_hygon_fam%.2xh.bin", family);
 
 	return get_builtin_firmware(cp, fw_name);
 #else
@@ -485,11 +488,18 @@ static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret)
 
 	if (IS_ENABLED(CONFIG_X86_32)) {
 		uci	= (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info);
-		path	= (const char *)__pa_nodebug(ucode_path);
+		if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+			path = (const char *)__pa_nodebug(
+				"kernel/x86/microcode/HygonGenuine.bin");
+		else
+			path	= (const char *)__pa_nodebug(ucode_path);
 		use_pa	= true;
 	} else {
 		uci     = ucode_cpu_info;
-		path	= ucode_path;
+		if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+			path = "kernel/x86/microcode/HygonGenuine.bin";
+		else
+			path	= ucode_path;
 		use_pa	= false;
 	}
 
@@ -556,8 +566,14 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
 	struct cont_desc desc = { 0 };
 	enum ucode_state ret;
 	struct cpio_data cp;
+	const char *path;
 
-	cp = find_microcode_in_initrd(ucode_path, false);
+	if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+		path = "kernel/x86/microcode/HygonGenuine.bin";
+	else
+		path = ucode_path;
+
+	cp = find_microcode_in_initrd(path, false);
 	if (!(cp.data && cp.size))
 		return -EINVAL;
 
@@ -899,7 +915,7 @@ load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
 					      bool refresh_fw)
 {
-	char fw_name[36] = "amd-ucode/microcode_amd.bin";
+	char fw_name[40] = "amd-ucode/microcode_amd.bin";
 	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
 	enum ucode_state ret = UCODE_NFOUND;
@@ -909,8 +925,12 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
 	if (!refresh_fw || !bsp)
 		return UCODE_OK;
 
-	if (c->x86 >= 0x15)
-		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD && c->x86 >= 0x15)
+		snprintf(fw_name, sizeof(fw_name),
+			"amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
+	else if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+		snprintf(fw_name, sizeof(fw_name),
+			"hygon-ucode/microcode_hygon_fam%.2xh.bin", c->x86);
 
 	if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
 		pr_debug("failed to load file %s\n", fw_name);
@@ -967,6 +987,22 @@ struct microcode_ops * __init init_amd_microcode(void)
 	return &microcode_amd_ops;
 }
 
+#ifdef CONFIG_MICROCODE_HYGON
+const struct microcode_ops * __init init_hygon_microcode(void)
+{
+	struct cpuinfo_x86 *c = &boot_cpu_data;
+
+	if (c->x86_vendor != X86_VENDOR_HYGON)
+		return NULL;
+
+	if (ucode_new_rev)
+		pr_info_once("microcode updated early to new patch_level=0x%08x\n",
+			     ucode_new_rev);
+
+	return &microcode_amd_ops;
+}
+#endif
+
 void __exit exit_amd_microcode(void)
 {
 	cleanup();
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 0b1732b98e71..21bdbbfa915c 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -42,7 +42,11 @@
 
 #define DRIVER_VERSION	"2.2"
 
+#ifdef CONFIG_MICROCODE_HYGON
+static const struct microcode_ops	*microcode_ops;
+#else
 static struct microcode_ops	*microcode_ops;
+#endif
 static bool dis_ucode_ldr = true;
 
 bool initrd_gone;
@@ -129,7 +133,8 @@ static bool __init check_loader_disabled_bsp(void)
 	if (native_cpuid_ecx(1) & BIT(31))
 		return *res;
 
-	if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD ||
+	    x86_cpuid_vendor() == X86_VENDOR_HYGON) {
 		if (amd_check_current_patch_level())
 			return *res;
 	}
@@ -179,6 +184,10 @@ void __init load_ucode_bsp(void)
 		intel = false;
 		break;
 
+	case X86_VENDOR_HYGON:
+		intel = false;
+		break;
+
 	default:
 		return;
 	}
@@ -219,6 +228,9 @@ void load_ucode_ap(void)
 		if (x86_family(cpuid_1_eax) >= 0x10)
 			load_ucode_amd_ap(cpuid_1_eax);
 		break;
+	case X86_VENDOR_HYGON:
+		load_ucode_amd_ap(cpuid_1_eax);
+		break;
 	default:
 		break;
 	}
@@ -238,6 +250,9 @@ static int __init save_microcode_in_initrd(void)
 		if (c->x86 >= 0x10)
 			ret = save_microcode_in_initrd_amd(cpuid_eax(1));
 		break;
+	case X86_VENDOR_HYGON:
+		ret = save_microcode_in_initrd_amd(cpuid_eax(1));
+		break;
 	default:
 		break;
 	}
@@ -331,6 +346,9 @@ void reload_early_microcode(void)
 		if (family >= 0x10)
 			reload_ucode_amd();
 		break;
+	case X86_VENDOR_HYGON:
+		reload_ucode_amd();
+		break;
 	default:
 		break;
 	}
@@ -842,6 +860,8 @@ int __init microcode_init(void)
 		microcode_ops = init_intel_microcode();
 	else if (c->x86_vendor == X86_VENDOR_AMD)
 		microcode_ops = init_amd_microcode();
+	else if (c->x86_vendor == X86_VENDOR_HYGON)
+		microcode_ops = init_hygon_microcode();
 	else
 		pr_err("no support for this CPU vendor\n");
 
-- 
Gitee


From a00b0087e48da53324b4c47587afa94fd017ff8a Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:11:00 +0800
Subject: [PATCH 06/20] x86/amd_nb: Add Hygon family 18h model 4h PCI IDs

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add the PCI device IDs for Hygon family 18h model 4h processors.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/amd_nb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 832ce4251a2f..7fe0c6382381 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -91,16 +91,19 @@ static const struct pci_device_id amd_nb_link_ids[] = {
 
 static const struct pci_device_id hygon_root_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
 	{}
 };
 
 static const struct pci_device_id hygon_nb_misc_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 	{}
 };
 
 static const struct pci_device_id hygon_nb_link_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
 	{}
 };
 
-- 
Gitee


From 29203c13c08e319bbc30936409fa62e7954eeef5 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:11:24 +0800
Subject: [PATCH 07/20] x86/amd_nb: Add northbridge support for Hygon family
 18h model 4h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add dedicated functions to initialize the northbridge for Hygon family
18h model 4h processors.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/include/asm/amd_nb.h |   8 ++
 arch/x86/kernel/amd_nb.c      | 194 ++++++++++++++++++++++++++++++++++
 2 files changed, 202 insertions(+)

diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 455066a06f60..f53447965d39 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -84,6 +84,10 @@ u16 amd_nb_num(void);
 bool amd_nb_has_feature(unsigned int feature);
 struct amd_northbridge *node_to_amd_nb(int node);
 
+bool hygon_f18h_m4h(void);
+u16 hygon_nb_num(void);
+int get_df_id(struct pci_dev *misc, u8 *id);
+
 static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
 {
 	struct pci_dev *misc;
@@ -121,6 +125,10 @@ static inline bool amd_gart_present(void)
 #define node_to_amd_nb(x)	NULL
 #define amd_gart_present(x)	false
 
+#define hygon_f18h_m4h		false
+#define hygon_nb_num(x)	0
+#define get_df_id(x, y)	NULL
+
 #endif
 
 
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 7fe0c6382381..6f065c22c137 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -31,10 +31,13 @@
 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
 
+#define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1 0x1491
+
 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
 static DEFINE_MUTEX(smn_mutex);
 
 static u32 *flush_words;
+static u16 nb_num;
 
 static const struct pci_device_id amd_root_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
@@ -238,6 +241,192 @@ int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
 }
 EXPORT_SYMBOL_GPL(amd_df_indirect_read);
 
+bool hygon_f18h_m4h(void)
+{
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+		return false;
+
+	if (boot_cpu_data.x86 == 0x18 &&
+	    boot_cpu_data.x86_model >= 0x4 &&
+	    boot_cpu_data.x86_model <= 0xf)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(hygon_f18h_m4h);
+
+u16 hygon_nb_num(void)
+{
+	return nb_num;
+}
+EXPORT_SYMBOL_GPL(hygon_nb_num);
+
+static int get_df1_register(struct pci_dev *misc, int offset, u32 *value)
+{
+	struct pci_dev *df_f1 = NULL;
+	int err;
+
+	while ((df_f1 = pci_get_device(misc->vendor,
+			PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1, df_f1)))
+		if (pci_domain_nr(df_f1->bus) == pci_domain_nr(misc->bus) &&
+		    df_f1->bus->number == misc->bus->number &&
+		    PCI_SLOT(df_f1->devfn) == PCI_SLOT(misc->devfn))
+			break;
+
+	if (!df_f1) {
+		pr_warn("Error getting DF F1 device.\n");
+		return -ENODEV;
+	}
+
+	err = pci_read_config_dword(df_f1, offset, value);
+	if (err)
+		pr_warn("Error reading DF F1 register.\n");
+
+	return err;
+}
+
+int get_df_id(struct pci_dev *misc, u8 *id)
+{
+	u32 value;
+	int ret;
+
+	/* F1x200[23:20]: DF ID */
+	ret = get_df1_register(misc, 0x200, &value);
+	*id = (value >> 20) & 0xf;
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(get_df_id);
+
+static u8 get_socket_num(struct pci_dev *misc)
+{
+	u32 value;
+	int ret;
+
+	/* F1x200[7:0]: Which socket is present. */
+	ret = get_df1_register(misc, 0x200, &value);
+
+	return ret ? 0 : hweight8(value & 0xff);
+}
+
+static int northbridge_init_f18h_m4h(const struct pci_device_id *root_ids,
+					const struct pci_device_id *misc_ids,
+					const struct pci_device_id *link_ids)
+{
+	struct pci_dev *root, *misc, *link;
+	struct pci_dev *root_first = NULL;
+	struct amd_northbridge *nb;
+	u16 roots_per_socket = 0;
+	u16 miscs_per_socket = 0;
+	u16 socket_num = 0;
+	u16 root_count = 0;
+	u16 misc_count = 0;
+	int err = -ENODEV;
+	u8 i, j, m, n;
+	u8 id;
+
+	pr_info("Hygon Fam%xh Model%xh NB driver.\n",
+		boot_cpu_data.x86, boot_cpu_data.x86_model);
+
+	misc = next_northbridge(NULL, misc_ids);
+	if (misc != NULL) {
+		socket_num = get_socket_num(misc);
+		pr_info("Socket number: %d\n", socket_num);
+		if (!socket_num) {
+			err = -ENODEV;
+			goto ret;
+		}
+	} else {
+		err = -ENODEV;
+		goto ret;
+	}
+
+	misc = NULL;
+	while ((misc = next_northbridge(misc, misc_ids)) != NULL)
+		misc_count++;
+
+	root = NULL;
+	while ((root = next_northbridge(root, root_ids)) != NULL)
+		root_count++;
+
+	if (!root_count || !misc_count) {
+		err = -ENODEV;
+		goto ret;
+	}
+
+	/*
+	 * There should be _exactly_ N roots for each DF/SMN
+	 * interface, and M DF/SMN interfaces in one socket.
+	 */
+	roots_per_socket = root_count / socket_num;
+	miscs_per_socket = misc_count / socket_num;
+
+	if (!roots_per_socket || !miscs_per_socket) {
+		err = -ENODEV;
+		goto ret;
+	}
+
+	nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
+	if (!nb) {
+		err = -ENOMEM;
+		goto ret;
+	}
+
+	amd_northbridges.nb = nb;
+	amd_northbridges.num = misc_count;
+
+	link = misc = root = NULL;
+	j = m = n = 0;
+	for (i = 0; i < amd_northbridges.num; i++) {
+		misc = next_northbridge(misc, misc_ids);
+		link = next_northbridge(link, link_ids);
+
+		/* Only save the first PCI root device for each socket. */
+		if (!(i % miscs_per_socket)) {
+			root_first = next_northbridge(root, root_ids);
+			root = root_first;
+			j = 1;
+		}
+
+		if (get_df_id(misc, &id)) {
+			err = -ENODEV;
+			goto err;
+		}
+		pr_info("DF ID: %d\n", id);
+
+		if (id < 4) {
+			/* Add the devices with id<4 from the tail. */
+			node_to_amd_nb(misc_count - m - 1)->misc = misc;
+			node_to_amd_nb(misc_count - m - 1)->link = link;
+			node_to_amd_nb(misc_count - m - 1)->root = root_first;
+			m++;
+		} else {
+			node_to_amd_nb(n)->misc = misc;
+			node_to_amd_nb(n)->link = link;
+			node_to_amd_nb(n)->root = root_first;
+			n++;
+		}
+
+		/* Skip the redundant PCI root devices per socket. */
+		while (j < roots_per_socket) {
+			root = next_northbridge(root, root_ids);
+			j++;
+		}
+	}
+	nb_num = n;
+
+	return 0;
+
+err:
+	kfree(nb);
+	amd_northbridges.nb = NULL;
+
+ret:
+	pr_err("Hygon Fam%xh Model%xh northbridge init failed(%d)!\n",
+		boot_cpu_data.x86, boot_cpu_data.x86_model, err);
+	return err;
+}
+
 int amd_cache_northbridges(void)
 {
 	const struct pci_device_id *misc_ids = amd_nb_misc_ids;
@@ -257,6 +446,11 @@ int amd_cache_northbridges(void)
 		root_ids = hygon_root_ids;
 		misc_ids = hygon_nb_misc_ids;
 		link_ids = hygon_nb_link_ids;
+
+		if (boot_cpu_data.x86_model >= 0x4 &&
+		    boot_cpu_data.x86_model <= 0xf)
+			return northbridge_init_f18h_m4h(root_ids,
+					misc_ids, link_ids);
 	}
 
 	misc = NULL;
-- 
Gitee


From a2e4e35b6daeaf5db5db8d914770000e47248eed Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:11:46 +0800
Subject: [PATCH 08/20] iommu/hygon: Add support for Hygon family 18h model 4h
 IOAPIC

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

The SB IOAPIC is on the device 0xb from Hygon family 18h model 4h.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/iommu/amd/init.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index ce822347f747..d6b7a1599f46 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -2513,6 +2513,9 @@ static void __init free_iommu_resources(void)
 /* SB IOAPIC is always on this device in AMD systems */
 #define IOAPIC_SB_DEVID		((0x00 << 8) | PCI_DEVFN(0x14, 0))
 
+/* SB IOAPIC for Hygon family 18h model 4h is on the device 0xb */
+#define IOAPIC_SB_DEVID_FAM18H_M4H	((0x00 << 8) | PCI_DEVFN(0xb, 0))
+
 static bool __init check_ioapic_information(void)
 {
 	const char *fw_bug = FW_BUG;
@@ -2538,7 +2541,12 @@ static bool __init check_ioapic_information(void)
 			pr_err("%s: IOAPIC[%d] not in IVRS table\n",
 				fw_bug, id);
 			ret = false;
-		} else if (devid == IOAPIC_SB_DEVID) {
+		} else if (devid == IOAPIC_SB_DEVID ||
+			   (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
+			    boot_cpu_data.x86 == 0x18 &&
+			    boot_cpu_data.x86_model >= 0x4 &&
+			    boot_cpu_data.x86_model <= 0xf &&
+			    devid == IOAPIC_SB_DEVID_FAM18H_M4H)) {
 			has_sb_ioapic = true;
 			ret           = true;
 		}
-- 
Gitee


From ce8672f5a3c9c4837b05667dff098f61c4e6d9b2 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:12:04 +0800
Subject: [PATCH 09/20] EDAC/amd64: Get UMC channel from the 6th nibble for
 Hygon

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

On Hygon family 18h platforms, we look at the 6th nibble(bit 20~23)
in the instance_id to derive the channel number.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/amd64_edac.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 7f018fc111c0..9dc981c7e014 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2905,6 +2905,9 @@ static inline void decode_bus_error(int node_id, struct mce *m)
  */
 static int find_umc_channel(struct mce *m)
 {
+	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
+	    boot_cpu_data.x86 == 0x18)
+		return (m->ipid & GENMASK(23, 0)) >> 20;
 	return (m->ipid & GENMASK(31, 0)) >> 20;
 }
 
-- 
Gitee


From 55b016659d09a95f6d295b0d0c877d35693c5224 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:12:20 +0800
Subject: [PATCH 10/20] EDAC/amd64: Add support for Hygon family 18h model 4h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Hygon family 18h model 4h processor has the same F0/F6 device IDs
as F17h_M30h.

Add support to determine which DDR memory types it supports, but
determine syndrome sizes from different bits of the DRAM ECC control
reg.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/amd64_edac.c | 88 ++++++++++++++++++++++++++++++++-------
 1 file changed, 74 insertions(+), 14 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 9dc981c7e014..8b7d0f3b8a84 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -98,6 +98,17 @@ int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
 	return err;
 }
 
+static u32 get_umc_base_f18h_m4h(u16 node, u8 channel)
+{
+	struct pci_dev *f3 = node_to_amd_nb(node)->misc;
+	u8 df_id;
+
+	get_df_id(f3, &df_id);
+	df_id -= 4;
+
+	return get_umc_base(channel) + (0x80000000 + (0x10000000 * df_id));
+}
+
 /*
  * Select DCT to which PCI cfg accesses are routed
  */
@@ -1064,7 +1075,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
 	u32 i, tmp, umc_base;
 
 	for_each_umc(i) {
-		umc_base = get_umc_base(i);
+		if (hygon_f18h_m4h())
+			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
+		else
+			umc_base = get_umc_base(i);
 		umc = &pvt->umc[i];
 
 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
@@ -1184,11 +1198,17 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
 	u32 mask_reg, mask_reg_sec;
 	u32 *base, *base_sec;
 	u32 *mask, *mask_sec;
+	u32 umc_base;
 	int cs, umc;
 
 	for_each_umc(umc) {
-		umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
-		umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;
+		if (hygon_f18h_m4h())
+			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc);
+		else
+			umc_base = get_umc_base(umc);
+
+		umc_base_reg = umc_base + UMCCH_BASE_ADDR;
+		umc_base_reg_sec = umc_base + UMCCH_BASE_ADDR_SEC;
 
 		for_each_chip_select(cs, umc, pvt) {
 			base = &pvt->csels[umc].csbases[cs];
@@ -1206,8 +1226,8 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
 					 umc, cs, *base_sec, base_reg_sec);
 		}
 
-		umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
-		umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(UMCCH_ADDR_MASK_SEC);
+		umc_mask_reg = umc_base + UMCCH_ADDR_MASK;
+		umc_mask_reg_sec = umc_base + get_umc_reg(UMCCH_ADDR_MASK_SEC);
 
 		for_each_chip_select_mask(cs, umc, pvt) {
 			mask = &pvt->csels[umc].csmasks[cs];
@@ -1295,7 +1315,8 @@ static void determine_memory_type_df(struct amd64_pvt *pvt)
 		 * Check if the system supports the "DDR Type" field in UMC Config
 		 * and has DDR5 DIMMs in use.
 		 */
-		if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
+		if ((fam_type->flags.zn_regs_v2 || hygon_f18h_m4h()) &&
+		    ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
 			if (umc->dimm_cfg & BIT(5))
 				umc->dram_type = MEM_LRDDR5;
 			else if (umc->dimm_cfg & BIT(4))
@@ -3031,6 +3052,14 @@ static void free_mc_sibling_devs(struct amd64_pvt *pvt)
 	}
 }
 
+static void determine_ecc_sym_sz_f18h_m4h(struct amd64_pvt *pvt, int channel)
+{
+	if (pvt->umc[channel].ecc_ctrl & BIT(8))
+		pvt->ecc_sym_sz = 16;
+	else if (pvt->umc[channel].ecc_ctrl & BIT(7))
+		pvt->ecc_sym_sz = 8;
+}
+
 static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
 {
 	pvt->ecc_sym_sz = 4;
@@ -3041,6 +3070,14 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
 		for_each_umc(i) {
 			/* Check enabled channels only: */
 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
+				if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
+				    boot_cpu_data.x86 == 0x18 &&
+				    boot_cpu_data.x86_model == 0x4 &&
+				    (pvt->umc[i].umc_cfg & GENMASK(2, 0)) == 0x1) {
+					determine_ecc_sym_sz_f18h_m4h(pvt, i);
+					return;
+				}
+
 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
 					pvt->ecc_sym_sz = 16;
 					return;
@@ -3075,8 +3112,11 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt)
 
 	/* Read registers from each UMC */
 	for_each_umc(i) {
+		if (hygon_f18h_m4h())
+			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
+		else
+			umc_base = get_umc_base(i);
 
-		umc_base = get_umc_base(i);
 		umc = &pvt->umc[i];
 
 		amd_smn_read(nid, umc_base + get_umc_reg(UMCCH_DIMM_CFG), &umc->dimm_cfg);
@@ -3686,13 +3726,21 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
 			pvt->ops = &family_types[F17_M70H_CPUS].ops;
 			break;
 		}
-		fallthrough;
-	case 0x18:
 		fam_type	= &family_types[F17_CPUS];
 		pvt->ops	= &family_types[F17_CPUS].ops;
+		break;
 
-		if (pvt->fam == 0x18)
-			family_types[F17_CPUS].ctl_name = "F18h";
+	case 0x18:
+		if (pvt->model == 0x4) {
+			fam_type = &family_types[F17_M30H_CPUS];
+			pvt->ops = &family_types[F17_M30H_CPUS].ops;
+			family_types[F17_M30H_CPUS].max_mcs = 3;
+			family_types[F17_M30H_CPUS].ctl_name = "F18h_M04h";
+			break;
+		}
+		fam_type	= &family_types[F17_CPUS];
+		pvt->ops	= &family_types[F17_CPUS].ops;
+		family_types[F17_CPUS].ctl_name = "F18h";
 		break;
 
 	case 0x19:
@@ -3970,6 +4018,7 @@ static int __init amd64_edac_init(void)
 {
 	const char *owner;
 	int err = -ENODEV;
+	u16 instance_num;
 	int i;
 
 	owner = edac_get_owner();
@@ -3984,8 +4033,13 @@ static int __init amd64_edac_init(void)
 
 	opstate_init();
 
+	if (hygon_f18h_m4h())
+		instance_num = hygon_nb_num();
+	else
+		instance_num = amd_nb_num();
+
 	err = -ENOMEM;
-	ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL);
+	ecc_stngs = kcalloc(instance_num, sizeof(ecc_stngs[0]), GFP_KERNEL);
 	if (!ecc_stngs)
 		goto err_free;
 
@@ -3993,7 +4047,7 @@ static int __init amd64_edac_init(void)
 	if (!msrs)
 		goto err_free;
 
-	for (i = 0; i < amd_nb_num(); i++) {
+	for (i = 0; i < instance_num; i++) {
 		err = probe_one_instance(i);
 		if (err) {
 			/* unwind properly */
@@ -4040,6 +4094,7 @@ static int __init amd64_edac_init(void)
 
 static void __exit amd64_edac_exit(void)
 {
+	u16 instance_num;
 	int i;
 
 	if (pci_ctl)
@@ -4051,7 +4106,12 @@ static void __exit amd64_edac_exit(void)
 	else
 		amd_unregister_ecc_decoder(decode_bus_error);
 
-	for (i = 0; i < amd_nb_num(); i++)
+	if (hygon_f18h_m4h())
+		instance_num = hygon_nb_num();
+	else
+		instance_num = amd_nb_num();
+
+	for (i = 0; i < instance_num; i++)
 		remove_one_instance(i);
 
 	kfree(ecc_stngs);
-- 
Gitee


From f2f10bd1625a612f3c36628c4042b0be7de84674 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:12:39 +0800
Subject: [PATCH 11/20] EDAC/amd64: Adjust address translation for Hygon family
 18h model 4h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add Hygon family 18h model 4h processor support for DramOffset and
HiAddrOffset, and get the socket interleaving number from DramBase-
Address(D18F0x110).

Update intlv_num_chan and num_intlv_bits support for Hygon family 18h
model 4h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/amd64_edac.c | 48 +++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 10 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8b7d0f3b8a84..390a6534d030 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -751,13 +751,21 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	u8 cs_mask, cs_id = 0;
 	bool hash_enabled = false;
 
-	/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
-	if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
+	/* Read DramOffset, check if base 1 is used. */
+	if (hygon_f18h_m4h() &&
+	    amd_df_indirect_read(nid, 0, 0x214, umc, &tmp))
+		goto out_err;
+	else if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 		goto out_err;
 
 	/* Remove HiAddrOffset from normalized address, if enabled: */
 	if (tmp & BIT(0)) {
-		u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
+		u64 hi_addr_offset;
+
+		if (hygon_f18h_m4h())
+			hi_addr_offset = (tmp & GENMASK_ULL(31, 18)) << 8;
+		else
+			hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 
 		if (norm_addr >= hi_addr_offset) {
 			ret_addr -= hi_addr_offset;
@@ -776,6 +784,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 		goto out_err;
 	}
 
+	intlv_num_sockets = 0;
+	if (hygon_f18h_m4h())
+		intlv_num_sockets = (tmp >> 2) & 0x3;
 	lgcy_mmio_hole_en = tmp & BIT(1);
 	intlv_num_chan	  = (tmp >> 4) & 0xF;
 	intlv_addr_sel	  = (tmp >> 8) & 0x7;
@@ -792,7 +803,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 		goto out_err;
 
-	intlv_num_sockets = (tmp >> 8) & 0x1;
+	if (!hygon_f18h_m4h())
+		intlv_num_sockets = (tmp >> 8) & 0x1;
 	intlv_num_dies	  = (tmp >> 10) & 0x3;
 	dram_limit_addr	  = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 
@@ -802,6 +814,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	switch (intlv_num_chan) {
 	case 0:	intlv_num_chan = 0; break;
 	case 1: intlv_num_chan = 1; break;
+	case 2:
+		if (hygon_f18h_m4h())
+			intlv_num_chan = 2;
+		break;
 	case 3: intlv_num_chan = 2; break;
 	case 5:	intlv_num_chan = 3; break;
 	case 7:	intlv_num_chan = 4; break;
@@ -828,8 +844,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	/* Add a bit if sockets are interleaved. */
 	num_intlv_bits += intlv_num_sockets;
 
-	/* Assert num_intlv_bits <= 4 */
-	if (num_intlv_bits > 4) {
+	/* Assert num_intlv_bits in the correct range. */
+	if ((hygon_f18h_m4h() && num_intlv_bits > 7) ||
+	    (!hygon_f18h_m4h() && num_intlv_bits > 4)) {
 		pr_err("%s: Invalid interleave bits %d.\n",
 			__func__, num_intlv_bits);
 		goto out_err;
@@ -848,7 +865,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 		if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 			goto out_err;
 
-		cs_fabric_id = (tmp >> 8) & 0xFF;
+		if (hygon_f18h_m4h())
+			cs_fabric_id = (tmp >> 8) & 0x7FF;
+		else
+			cs_fabric_id = (tmp >> 8) & 0xFF;
 		die_id_bit   = 0;
 
 		/* If interleaved over more than 1 channel: */
@@ -868,8 +888,13 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 		/* If interleaved over more than 1 die. */
 		if (intlv_num_dies) {
 			sock_id_bit  = die_id_bit + intlv_num_dies;
-			die_id_shift = (tmp >> 24) & 0xF;
-			die_id_mask  = (tmp >> 8) & 0xFF;
+			if (hygon_f18h_m4h()) {
+				die_id_shift = (tmp >> 12) & 0xF;
+				die_id_mask  = tmp & 0x7FF;
+			} else {
+				die_id_shift = (tmp >> 24) & 0xF;
+				die_id_mask  = (tmp >> 8) & 0xFF;
+			}
 
 			cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 		}
@@ -877,7 +902,10 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 		/* If interleaved over more than 1 socket. */
 		if (intlv_num_sockets) {
 			socket_id_shift	= (tmp >> 28) & 0xF;
-			socket_id_mask	= (tmp >> 16) & 0xFF;
+			if (hygon_f18h_m4h())
+				socket_id_mask	= (tmp >> 16) & 0x7FF;
+			else
+				socket_id_mask	= (tmp >> 16) & 0xFF;
 
 			cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 		}
-- 
Gitee


From 103eb8748c8f67e33d908fe718b168ef22f54c9e Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:12:55 +0800
Subject: [PATCH 12/20] EDAC/mce_amd: Use struct cpuinfo_x86.logical_die_id for
 Hygon NodeId

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

The cpuinfo_x86.cpu_die_id is get from CPUID or MSR in the commit
028c221ed190 ("x86/CPU/AMD: Save AMD NodeId as cpu_die_id"). But the
value may not be continuous for Hygon model 4h~6h processors.

Use cpuinfo_x86.logical_die_id will always format continuous die
(or node) IDs, because it will convert the physical die ID to logical
die ID.

So use topology_logical_die_id() instead of topology_die_id() to
decode UMC ECC errors for Hygon processors.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/mce_amd.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 414dcab73715..b39fb9932bed 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -1186,8 +1186,13 @@ static void decode_smca_error(struct mce *m)
 	if (xec < smca_mce_descs[bank_type].num_descs)
 		pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);
 
-	if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
-		decode_dram_ecc(topology_die_id(m->extcpu), m);
+	if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) {
+		if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
+		    boot_cpu_data.x86 == 0x18)
+			decode_dram_ecc(topology_logical_die_id(m->extcpu), m);
+		else
+			decode_dram_ecc(topology_die_id(m->extcpu), m);
+	}
 }
 
 static inline void amd_decode_err_code(u16 ec)
-- 
Gitee


From 597cd9ff6fb86eaaeb76b256ac5fea4ce348e00f Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:13:12 +0800
Subject: [PATCH 13/20] hwmon/k10temp: Add support for Hygon family 18h model
 4h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

The DF F3 device ID used to get the temperature for Hygon family 18h
model 4h processor is the same as 17H_M30H, but with different offsets,
which may span two distributed ranges. The second offset range can be
considered as private for Hygon, so use struct hygon_private to describe
it.

Add a pointer priv in k10temp_data to point to the private data.
Add functions k10temp_get_ccd_support_2nd() and hygon_read_temp()
to support reading the second offset range.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/hwmon/k10temp.c | 84 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 2 deletions(-)

diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 4e239bd75b1d..2a282d0e7051 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -76,6 +76,11 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
 #define ZEN_CUR_TEMP_SHIFT			21
 #define ZEN_CUR_TEMP_RANGE_SEL_MASK		BIT(19)
 
+struct hygon_private {
+	u32 index_2nd;
+	u32 offset_2nd;
+};
+
 struct k10temp_data {
 	struct pci_dev *pdev;
 	void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
@@ -85,6 +90,7 @@ struct k10temp_data {
 	u32 show_temp;
 	bool is_zen;
 	u32 ccd_offset;
+	void *priv;
 };
 
 #define TCTL_BIT	0
@@ -191,6 +197,23 @@ static int k10temp_read_labels(struct device *dev,
 	return 0;
 }
 
+static void hygon_read_temp(struct k10temp_data *data, int channel,
+			       u32 *regval)
+{
+	struct hygon_private *h_priv;
+
+	h_priv = (struct hygon_private *)data->priv;
+	if ((channel - 2) < h_priv->index_2nd)
+		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
+			     ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
+					  regval);
+	else
+		amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
+			     ZEN_CCD_TEMP(h_priv->offset_2nd,
+					  channel - 2 - h_priv->index_2nd),
+					  regval);
+}
+
 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 			     long *val)
 {
@@ -211,7 +234,10 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 				*val = 0;
 			break;
 		case 2 ... 13:		/* Tccd{1-12} */
-			amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
+			if (hygon_f18h_m4h())
+				hygon_read_temp(data, channel, &regval);
+			else
+				amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 				     ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
 						  &regval);
 			*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
@@ -378,14 +404,48 @@ static void k10temp_get_ccd_support(struct pci_dev *pdev,
 	}
 }
 
+static void k10temp_get_ccd_support_2nd(struct pci_dev *pdev,
+					struct k10temp_data *data, int limit)
+{
+	struct hygon_private *h_priv;
+	u32 regval;
+	int i;
+
+	h_priv = (struct hygon_private *)data->priv;
+	for (i = h_priv->index_2nd; i < limit; i++) {
+		amd_smn_read(amd_pci_dev_to_node_id(pdev),
+			     ZEN_CCD_TEMP(h_priv->offset_2nd,
+			     i - h_priv->index_2nd),
+			     &regval);
+		if (regval & ZEN_CCD_TEMP_VALID)
+			data->show_temp |= BIT(TCCD_BIT(i));
+	}
+}
+
 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
 	int unreliable = has_erratum_319(pdev);
 	struct device *dev = &pdev->dev;
+	struct hygon_private *h_priv;
 	struct k10temp_data *data;
 	struct device *hwmon_dev;
+	u8 df_id;
 	int i;
 
+	if (hygon_f18h_m4h()) {
+		if (get_df_id(pdev, &df_id)) {
+			pr_err("Get DF ID failed.\n");
+			return -ENODEV;
+		}
+
+		/*
+		 * The temperature should be get from the devices
+		 * with id < 4.
+		 */
+		if (df_id >= 4)
+			return 0;
+	}
+
 	if (unreliable) {
 		if (!force) {
 			dev_err(dev,
@@ -408,7 +468,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	     (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
 		data->read_htcreg = read_htcreg_nb_f15;
 		data->read_tempreg = read_tempreg_nb_f15;
-	} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
+	} else if (boot_cpu_data.x86 == 0x17) {
 		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
 		data->read_tempreg = read_tempreg_nb_zen;
 		data->is_zen = true;
@@ -429,6 +489,25 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 			k10temp_get_ccd_support(pdev, data, 8);
 			break;
 		}
+	} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
+		   boot_cpu_data.x86 == 0x18) {
+		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
+		data->read_tempreg = read_tempreg_nb_zen;
+		data->is_zen = true;
+
+		if (boot_cpu_data.x86_model >= 0x4 &&
+		    boot_cpu_data.x86_model <= 0xf) {
+			data->ccd_offset = 0x154;
+			data->priv = devm_kzalloc(dev, sizeof(*h_priv),
+						  GFP_KERNEL);
+			if (!data->priv)
+				return -ENOMEM;
+			h_priv = (struct hygon_private *)data->priv;
+			h_priv->offset_2nd = 0x2f8;
+			h_priv->index_2nd = 3;
+			k10temp_get_ccd_support(pdev, data, h_priv->index_2nd);
+			k10temp_get_ccd_support_2nd(pdev, data, 8);
+		}
 	} else if (boot_cpu_data.x86 == 0x19) {
 		data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
 		data->read_tempreg = read_tempreg_nb_zen;
@@ -494,6 +573,7 @@ static const struct pci_device_id k10temp_id_table[] = {
 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
 	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 	{}
 };
 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
-- 
Gitee


From d74eee0d0d6b79880b191cbf94a6b66b80172418 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:13:29 +0800
Subject: [PATCH 14/20] i2c-piix4: Remove the IMC detecting for Hygon SMBus

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Remove IMC detecting path for Hygon processors.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/i2c/busses/i2c-piix4.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index aa1d3657ab4e..45e5170e030f 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -924,8 +924,7 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
 		bool notify_imc = false;
 		is_sb800 = true;
 
-		if ((dev->vendor == PCI_VENDOR_ID_AMD ||
-		     dev->vendor == PCI_VENDOR_ID_HYGON) &&
+		if (dev->vendor == PCI_VENDOR_ID_AMD &&
 		    dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
 			u8 imc;
 
-- 
Gitee


From ffb3b8cc35cdad50d1e3da9c7b9a0aabef3cbb6b Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:13:54 +0800
Subject: [PATCH 15/20] x86/cpu: Get LLC ID for Hygon family 18h model 5h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add support to calculate LLC ID from the number of threads sharing
the cache for Hygon family 18h model 5h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/cpu/cacheinfo.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index b458b0fd98bf..f33d55338da4 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -693,11 +693,30 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu)
 	if (!cpuid_edx(0x80000006))
 		return;
 
-	/*
-	 * LLC is at the core complex level.
-	 * Core complex ID is ApicId[3] for these processors.
-	 */
-	per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
+	if (c->x86_model < 0x5) {
+		/*
+		 * LLC is at the core complex level.
+		 * Core complex ID is ApicId[3] for these processors.
+		 */
+		per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
+	} else {
+		/*
+		 * LLC ID is calculated from the number of threads
+		 * sharing the cache.
+		 */
+		u32 eax, ebx, ecx, edx, num_sharing_cache = 0;
+		u32 llc_index = find_num_cache_leaves(c) - 1;
+
+		cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx);
+		if (eax)
+			num_sharing_cache = ((eax >> 14) & 0xfff) + 1;
+
+		if (num_sharing_cache) {
+			int bits = get_count_order(num_sharing_cache);
+
+			per_cpu(cpu_llc_id, cpu) = c->apicid >> bits;
+		}
+	}
 }
 
 void init_amd_cacheinfo(struct cpuinfo_x86 *c)
-- 
Gitee


From c6716f1d312d37df9ac605e0c089712d7e2cdfa8 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:14:35 +0800
Subject: [PATCH 16/20] x86/amd_nb: Add support for Hygon family 18h model 5h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add root and DF F1/F3/F4 device IDs for Hygon family 18h model
5h processors. But some model 5h processors have the legacy(M04H)
DF devices, so add a if conditional to read the df1 register.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/amd_nb.c | 24 ++++++++++++++++++++++--
 include/linux/pci_ids.h  |  1 +
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 6f065c22c137..345e6104c3bf 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -31,7 +31,10 @@
 #define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
 
+#define PCI_DEVICE_ID_HYGON_18H_M05H_ROOT  0x14a0
 #define PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1 0x1491
+#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1 0x14b1
+#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4 0x14b4
 
 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
 static DEFINE_MUTEX(smn_mutex);
@@ -95,18 +98,21 @@ static const struct pci_device_id amd_nb_link_ids[] = {
 static const struct pci_device_id hygon_root_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_ROOT) },
 	{}
 };
 
 static const struct pci_device_id hygon_nb_misc_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) },
 	{}
 };
 
 static const struct pci_device_id hygon_nb_link_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F4) },
 	{}
 };
 
@@ -264,10 +270,24 @@ EXPORT_SYMBOL_GPL(hygon_nb_num);
 static int get_df1_register(struct pci_dev *misc, int offset, u32 *value)
 {
 	struct pci_dev *df_f1 = NULL;
+	u32 device;
 	int err;
 
-	while ((df_f1 = pci_get_device(misc->vendor,
-			PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1, df_f1)))
+	switch (boot_cpu_data.x86_model) {
+	case 0x4:
+		device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;
+		break;
+	case 0x5:
+		if (misc->device == PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3)
+			device = PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1;
+		else
+			device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;
+		break;
+	default:
+		return -ENODEV;
+	}
+
+	while ((df_f1 = pci_get_device(misc->vendor, device, df_f1)))
 		if (pci_domain_nr(df_f1->bus) == pci_domain_nr(misc->bus) &&
 		    df_f1->bus->number == misc->bus->number &&
 		    PCI_SLOT(df_f1->devfn) == PCI_SLOT(misc->devfn))
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ea90e03010b9..fdd8b2fffd53 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2610,6 +2610,7 @@
 #define PCI_VENDOR_ID_ZHAOXIN		0x1d17
 
 #define PCI_VENDOR_ID_HYGON		0x1d94
+#define PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3	0x14b3
 
 #define PCI_VENDOR_ID_HXT		0x1dbf
 
-- 
Gitee


From bec622ac48bd33e309eeee99c8a237b771cd1b95 Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:14:53 +0800
Subject: [PATCH 17/20] EDAC/amd64: Add support for Hygon family 18h model 5h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Hygon family 18h model 5h processor has the same F0/F6 device IDs as
F17h_M30h, and the syndrome size is the same as model 4h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/amd64_edac.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 390a6534d030..63278176d282 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3100,7 +3100,8 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
 				if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
 				    boot_cpu_data.x86 == 0x18 &&
-				    boot_cpu_data.x86_model == 0x4 &&
+				    (boot_cpu_data.x86_model == 0x4 ||
+				     boot_cpu_data.x86_model == 0x5) &&
 				    (pvt->umc[i].umc_cfg & GENMASK(2, 0)) == 0x1) {
 					determine_ecc_sym_sz_f18h_m4h(pvt, i);
 					return;
@@ -3765,6 +3766,12 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
 			family_types[F17_M30H_CPUS].max_mcs = 3;
 			family_types[F17_M30H_CPUS].ctl_name = "F18h_M04h";
 			break;
+		} else if (pvt->model == 0x5) {
+			fam_type = &family_types[F17_M30H_CPUS];
+			pvt->ops = &family_types[F17_M30H_CPUS].ops;
+			family_types[F17_M30H_CPUS].max_mcs = 1;
+			family_types[F17_M30H_CPUS].ctl_name = "F18h_M05h";
+			break;
 		}
 		fam_type	= &family_types[F17_CPUS];
 		pvt->ops	= &family_types[F17_CPUS].ops;
-- 
Gitee


From 81b79593c98cb272f2241d7de981f3921f7639fc Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:15:11 +0800
Subject: [PATCH 18/20] hwmon/k10temp: Add support for Hygon family 18h model
 5h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add 18H_M05H DF F3 device ID to get the temperature for Hygon
family 18h model 5h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/hwmon/k10temp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 2a282d0e7051..06903f40c02a 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -574,6 +574,7 @@ static const struct pci_device_id k10temp_id_table[] = {
 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
 	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+	{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_DF_F3) },
 	{}
 };
 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
-- 
Gitee


From ff3fb5b8f643638377021535423507b7167b7c1d Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:15:44 +0800
Subject: [PATCH 19/20] x86/amd_nb: Add support for Hygon family 18h model 6h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Hygon family 18h model 6h processor has the same DF F1 device ID
as M05H_DF_F1.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/amd_nb.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 345e6104c3bf..a94b3844b059 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -283,6 +283,9 @@ static int get_df1_register(struct pci_dev *misc, int offset, u32 *value)
 		else
 			device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;
 		break;
+	case 0x6:
+		device = PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1;
+		break;
 	default:
 		return -ENODEV;
 	}
-- 
Gitee


From b3861530865964b95b7ee67fd87db7802cab99ac Mon Sep 17 00:00:00 2001
From: Pu Wen <puwen@hygon.cn>
Date: Sat, 22 Jul 2023 15:16:07 +0800
Subject: [PATCH 20/20] EDAC/amd64: Add support for Hygon family 18h model 6h

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V
CVE: NA

---------------------------

Add F0/F6 device IDs for Hygon family 18h model 6h processor.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 drivers/edac/amd64_edac.c | 14 ++++++++++++++
 drivers/edac/amd64_edac.h |  4 ++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 63278176d282..24842a747f99 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2673,6 +2673,16 @@ static struct amd64_family_type family_types[] = {
 			.dbam_to_cs		= f17_addr_mask_to_cs_size,
 		}
 	},
+	[F18_M06H_CPUS] = {
+		.ctl_name = "F18h_M06h",
+		.f0_id = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0,
+		.f6_id = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6,
+		.max_mcs = 2,
+		.ops = {
+			.early_channel_count	= f17_early_channel_count,
+			.dbam_to_cs		= f17_addr_mask_to_cs_size,
+		}
+	},
 	[F19_CPUS] = {
 		.ctl_name = "F19h",
 		.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
@@ -3772,6 +3782,10 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
 			family_types[F17_M30H_CPUS].max_mcs = 1;
 			family_types[F17_M30H_CPUS].ctl_name = "F18h_M05h";
 			break;
+		} else if (pvt->model == 0x6) {
+			fam_type = &family_types[F18_M06H_CPUS];
+			pvt->ops = &family_types[F18_M06H_CPUS].ops;
+			break;
 		}
 		fam_type	= &family_types[F17_CPUS];
 		pvt->ops	= &family_types[F17_CPUS].ops;
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 5a273d589e30..3c82cedc4eec 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -129,6 +129,9 @@
 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
 #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
 
+#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0 0x14b0
+#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6 0x14b6
+
 /*
  * Function 1 - Address Map
  */
@@ -302,6 +305,7 @@ enum amd_families {
 	F17_M30H_CPUS,
 	F17_M60H_CPUS,
 	F17_M70H_CPUS,
+	F18_M06H_CPUS,
 	F19_CPUS,
 	F19_M10H_CPUS,
 	NUM_FAMILIES,
-- 
Gitee