diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 28dafda30fe54d077f24f8c838be4739dd0411ac..97b63dc1145773e8e3c0a6254570d1529148e8d0 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2709,6 +2709,9 @@
 			[KVM,ARM] Allow use of GICv4 for direct injection of
 			LPIs.
 
+	kvm-arm.ipiv_enabled=
+			[KVM,ARM] Allow use of HiSilicon ipiv on GICv4.1
+
 	kvm-arm.dvmbm_enabled=
 			[KVM,ARM] Allow use of HiSilicon DVMBM capability.
 			Default: 0
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 81898bb87c5e999375bfd9e23c80f48b976509aa..80276f048aef933dc5e532276d300f7c48df205d 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -1294,5 +1294,6 @@ bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
 extern bool force_wfi_trap;
 extern bool kvm_ncsnp_support;
 extern bool kvm_dvmbm_support;
+extern bool kvm_ipiv_support;
 
 #endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0d36f20ecd3365d3cdf7db7ad38e57273ac196f0..17f8397b78daa4e6848c6c626ae656a34c2a2087 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -585,6 +585,9 @@
 #define SYS_CNTHV_CTL_EL2		sys_reg(3, 4, 14, 3, 1)
 #define SYS_CNTHV_CVAL_EL2		sys_reg(3, 4, 14, 3, 2)
 
+/* IPIV private register */
+#define CPU_SYS_TRAP_EL2		sys_reg(3, 4, 15, 7, 2)
+
 /* VHE encodings for architectural EL0/1 system registers */
 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
 #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index d0d4e6bdc06bb716627ca67a6a1a3dcde1a99a75..5bd31fc0e4469211c565af86f88748d2400400e2 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -67,6 +67,9 @@ bool kvm_ncsnp_support;
 /* Capability of DVMBM */
 bool kvm_dvmbm_support;
 
+/* Capability of IPIV */
+bool kvm_ipiv_support;
+
 static DEFINE_PER_CPU(unsigned char, kvm_hyp_initialized);
 
 bool is_kvm_arm_initialised(void)
@@ -383,6 +386,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
 #endif
 }
 
+extern struct static_key_false ipiv_enable;
+
 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 {
 	int r;
@@ -512,6 +517,12 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
 		r = system_supports_hdbss();
 		break;
 #endif
+	case KVM_CAP_ARM_IPIV_MODE:
+		if (static_branch_unlikely(&ipiv_enable))
+			r = 1;
+		else
+			r = 0;
+		break;
 	default:
 		r = 0;
 	}
@@ -2781,12 +2792,17 @@ static __init int kvm_arm_init(void)
 	probe_hisi_cpu_type();
 	kvm_ncsnp_support = hisi_ncsnp_supported();
 	kvm_dvmbm_support = hisi_dvmbm_supported();
+	kvm_ipiv_support = hisi_ipiv_supported();
 	kvm_info("KVM ncsnp %s\n", kvm_ncsnp_support ? "enabled" : "disabled");
 	kvm_info("KVM dvmbm %s\n", kvm_dvmbm_support ? "enabled" : "disabled");
+	kvm_info("KVM ipiv %s\n", kvm_ipiv_support ? "enabled" : "disabled");
 
 	if (kvm_dvmbm_support)
 		kvm_get_pg_cfg();
 
+	if (kvm_ipiv_support)
+		ipiv_gicd_init();
+
 	in_hyp_mode = is_kernel_in_hyp_mode();
 
 #ifdef CONFIG_HISI_VIRTCCA_HOST
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c
index d95b96ee7237c5522f6f4a703c016bb534c0da93..dd2739e16d09c91d434ed73301f7b57dbd8a0b0c 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.c
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.c
@@ -12,6 +12,7 @@
 static enum hisi_cpu_type cpu_type = UNKNOWN_HI_TYPE;
 
 static bool dvmbm_enabled;
+static bool ipiv_enabled;
 
 static const char * const hisi_cpu_type_str[] = {
 	"Hisi1612",
@@ -157,6 +158,43 @@ static void hardware_disable_dvmbm(void *data)
 	write_sysreg_s(val, SYS_LSUDVM_CTRL_EL2);
 }
 
+static int __init early_ipiv_enable(char *buf)
+{
+	return strtobool(buf, &ipiv_enabled);
+}
+early_param("kvm-arm.ipiv_enabled", early_ipiv_enable);
+
+bool hisi_ipiv_supported(void)
+{
+	if (cpu_type != HI_IP12)
+		return false;
+
+	/* Determine whether IPIV is supported by the hardware */
+	if (!(read_sysreg(aidr_el1) & AIDR_EL1_IPIV_MASK)) {
+		kvm_info("Hisi ipiv not supported by the hardware\n");
+		return false;
+	} else
+		kvm_info("Hisi ipiv detected on the hardware\n");
+
+	/* User provided kernel command-line parameter */
+	if (!ipiv_enabled || !is_kernel_in_hyp_mode())
+		return false;
+
+	/* Enable IPIV feature if necessary */
+	if (!is_gicv4p1()) {
+		kvm_info("Hisi ipiv needs to enable GICv4p1!\n");
+		return false;
+	}
+
+	kvm_info("Enable Hisi ipiv, do not support vSGI broadcast\n");
+	return true;
+}
+
+void ipiv_gicd_init(void)
+{
+	gic_dist_enable_ipiv();
+}
+
 bool hisi_dvmbm_supported(void)
 {
 	if (cpu_type != HI_IP10 && cpu_type != HI_IP10C &&
diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.h b/arch/arm64/kvm/hisilicon/hisi_virt.h
index c45d319e7b41d72537c05cfe31637e2273ea9add..f0b47c020261f58119aa354ae2964356f9cfa605 100644
--- a/arch/arm64/kvm/hisilicon/hisi_virt.h
+++ b/arch/arm64/kvm/hisilicon/hisi_virt.h
@@ -18,6 +18,8 @@ enum hisi_cpu_type {
 	UNKNOWN_HI_TYPE
 };
 
+/* HIP12 */
+#define AIDR_EL1_IPIV_MASK	GENMASK_ULL(17, 16)
 /* HIP10 */
 #define AIDR_EL1_DVMBM_MASK	GENMASK_ULL(13, 12)
 #define SYS_LSUDVM_CTRL_EL2	sys_reg(3, 4, 15, 7, 4)
@@ -75,7 +77,9 @@ enum hisi_cpu_type {
 void probe_hisi_cpu_type(void);
 bool hisi_ncsnp_supported(void);
 bool hisi_dvmbm_supported(void);
+bool hisi_ipiv_supported(void);
 void kvm_get_pg_cfg(void);
+void ipiv_gicd_init(void);
 
 int kvm_sched_affinity_vcpu_init(struct kvm_vcpu *vcpu);
 void kvm_sched_affinity_vcpu_destroy(struct kvm_vcpu *vcpu);
@@ -94,7 +98,12 @@ static inline bool hisi_dvmbm_supported(void)
 {
 	return false;
 }
+static inline bool hisi_ipiv_supported(void)
+{
+	return false;
+}
 static inline void kvm_get_pg_cfg(void) {}
+static inline void ipiv_gicd_init(void) {}
 
 static inline int kvm_sched_affinity_vcpu_init(struct kvm_vcpu *vcpu)
 {
@@ -111,4 +120,6 @@ static inline void kvm_tlbi_dvmbm_vcpu_put(struct kvm_vcpu *vcpu) {}
 static inline void kvm_hisi_reload_lsudvmbm(struct kvm *kvm) {}
 #endif /* CONFIG_KVM_HISI_VIRT */
 
+extern bool gic_dist_enable_ipiv(void);
+extern bool is_gicv4p1(void);
 #endif /* __HISI_VIRT_H__ */
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 0cfa8d93e2ee36ecb14b1db62db3b25a3c8db299..6a3dddaddd94dcbbf2734b05e8bdee2f5eedb0f4 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -711,6 +711,8 @@ static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 	return actlr;
 }
 
+extern struct static_key_false ipiv_enable;
+
 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 {
 	u64 mpidr;
@@ -725,6 +727,15 @@ static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
 	mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
 	mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
 	mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
+
+	if (static_branch_unlikely(&ipiv_enable)) {
+		/*
+		 * To avoid sending multi-SGIs in guest OS, make aff1/aff2 unique
+		 */
+		mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(1);
+		mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(2);
+	}
+
 	mpidr |= (1ULL << 31);
 	vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
 
diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
index db5db9402c3a1fd08e306a75bd758cfaa2e75618..f44a794af6f7fda31ac51a8054e8347fc04c7757 100644
--- a/arch/arm64/kvm/vgic/vgic-init.c
+++ b/arch/arm64/kvm/vgic/vgic-init.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2015, 2016 ARM Ltd.
  */
 
+#include <linux/acpi.h>
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 #include <linux/cpu.h>
@@ -531,17 +532,30 @@ int kvm_vgic_map_resources(struct kvm *kvm)
 	return ret;
 }
 
+extern struct static_key_false ipiv_enable;
+static int ipiv_irq;
+
 /* GENERIC PROBE */
 
 void kvm_vgic_cpu_up(void)
 {
 	enable_percpu_irq(kvm_vgic_global_state.maint_irq, 0);
+	if (static_branch_unlikely(&ipiv_enable))
+		enable_percpu_irq(ipiv_irq, 0);
 }
 
 
 void kvm_vgic_cpu_down(void)
 {
 	disable_percpu_irq(kvm_vgic_global_state.maint_irq);
+	if (static_branch_unlikely(&ipiv_enable))
+		disable_percpu_irq(ipiv_irq);
+}
+
+static irqreturn_t vgic_ipiv_irq_handler(int irq, void *data)
+{
+	kvm_info("IPIV irq handler!\n");
+	return IRQ_HANDLED;
 }
 
 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
@@ -652,5 +666,23 @@ int kvm_vgic_hyp_init(void)
 	}
 
 	kvm_info("vgic interrupt IRQ%d\n", kvm_vgic_global_state.maint_irq);
+
+	if (static_branch_unlikely(&ipiv_enable)) {
+		ipiv_irq = acpi_register_gsi(NULL, 18, ACPI_EDGE_SENSITIVE,
+			ACPI_ACTIVE_HIGH);
+		if (ipiv_irq < 0) {
+			kvm_err("No ipiv exception irq\n");
+			return -ENXIO;
+		}
+
+		ret = request_percpu_irq(ipiv_irq, vgic_ipiv_irq_handler,
+				 "ipiv exception", kvm_get_running_vcpus());
+		if (ret) {
+			kvm_err("Cannot register interrupt %d\n", ipiv_irq);
+			free_percpu_irq(kvm_vgic_global_state.maint_irq,
+					kvm_get_running_vcpus());
+		}
+	}
+
 	return 0;
 }
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
index 961c3a79f41d9d19a705c185686dc99d60af75b8..d55607dcd226fb5a8f432a2d1f38cc85e2b6b460 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
@@ -136,6 +136,7 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
 
 		/* Switching HW SGIs? */
 		dist->nassgireq = val & GICD_CTLR_nASSGIreq;
+		dist->its_vm.nassgireq = dist->nassgireq;
 		if (is_hwsgi != dist->nassgireq)
 			vgic_v4_configure_vsgis(vcpu->kvm);
 
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 49a60999f661d09a14b57a334e91f2e9342ebb90..73be9108efdf4d28b5c04c38fdea440ab3901e76 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -39,6 +39,10 @@
 #include <linux/irqchip/arm-gic-v3.h>
 #include <linux/irqchip/arm-gic-v4.h>
 
+#ifdef CONFIG_ARM64
+#include <asm/sysreg.h>
+#endif
+
 #include <asm/cputype.h>
 #include <asm/exception.h>
 
@@ -388,6 +392,8 @@ static int alloc_devid_from_rsv_pools(struct rsv_devid_pool **devid_pool,
 #define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
 #define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
 
+extern struct static_key_false ipiv_enable;
+
 #ifdef CONFIG_VIRT_PLAT_DEV
 /*
  * Currently we only build *one* devid pool.
@@ -4562,11 +4568,61 @@ static void its_vpe_4_1_unmask_irq(struct irq_data *d)
 	its_vpe_4_1_send_inv(d);
 }
 
+static void ipiv_disable_vsgi_trap(void)
+{
+#ifdef CONFIG_ARM64
+	u64 val;
+
+	/* disable guest access ICC_SGI1R_EL1 trap, enable ipiv */
+	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
+	val |= 1ULL;
+	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
+#endif
+}
+
+static void ipiv_enable_vsgi_trap(void)
+{
+#ifdef CONFIG_ARM64
+	u64 val;
+
+	/* enable guest access ICC_SGI1R_EL1 trap, disable ipiv */
+	val = read_sysreg_s(CPU_SYS_TRAP_EL2);
+	val &= ~1UL;
+	write_sysreg_s(val, CPU_SYS_TRAP_EL2);
+#endif
+}
+
 static void its_vpe_4_1_schedule(struct its_vpe *vpe,
 				 struct its_cmd_info *info)
 {
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
+	struct its_vm *vm = vpe->its_vm;
+	unsigned long vpeid_page_addr;
+	u64 ipiv_val = 0;
 	u64 val = 0;
+	u32 nr_vpes;
+
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vm->nassgireq) {
+		/* wait gicr_ipiv_busy */
+		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
+					ipiv_val, !(ipiv_val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
+		vpeid_page_addr = virt_to_phys(page_address(vm->vpeid_page));
+		writel_relaxed(lower_32_bits(vpeid_page_addr),
+					vlpi_base + GICR_VM_TABLE_BAR_L);
+		writel_relaxed(upper_32_bits(vpeid_page_addr),
+					vlpi_base + GICR_VM_TABLE_BAR_H);
+
+		/* setup gicr_vcpu_entry_num_max and gicr_ipiv_its_ta_sel */
+		nr_vpes = vpe->its_vm->nr_vpes;
+		ipiv_val = ((nr_vpes - 1) << GICR_IPIV_CTRL_VCPU_ENTRY_NUM_MAX_SHIFT) |
+			(0 << GICR_IPIV_CTRL_IPIV_ITS_TA_SEL_SHIFT);
+		writel_relaxed(ipiv_val, vlpi_base + GICR_IPIV_CTRL);
+
+		ipiv_disable_vsgi_trap();
+	} else if (static_branch_unlikely(&ipiv_enable)) {
+		ipiv_enable_vsgi_trap();
+	}
 
 	/* Schedule the VPE */
 	val |= GICR_VPENDBASER_Valid;
@@ -4581,6 +4637,7 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 				   struct its_cmd_info *info)
 {
 	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
+	struct its_vm *vm = vpe->its_vm;
 	u64 val;
 
 	if (info->req_db) {
@@ -4612,6 +4669,17 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 					    GICR_VPENDBASER_PendingLast);
 		vpe->pending_last = true;
 	}
+
+	if (static_branch_unlikely(&ipiv_enable) &&
+	    vm->nassgireq) {
+		/* wait gicr_ipiv_busy */
+		WARN_ON_ONCE(readl_relaxed_poll_timeout_atomic(vlpi_base + GICR_IPIV_ST,
+					val, !(val & GICR_IPIV_ST_IPIV_BUSY), 1, 500));
+		writel_relaxed(0, vlpi_base + GICR_VM_TABLE_BAR_L);
+		writel_relaxed(0, vlpi_base + GICR_VM_TABLE_BAR_H);
+
+		ipiv_enable_vsgi_trap();
+	}
 }
 
 static void its_vpe_4_1_invall(struct its_vpe *vpe)
@@ -5014,6 +5082,10 @@ static void its_vpe_irq_domain_free(struct irq_domain *domain,
 	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
 		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
 		its_free_prop_table(vm->vprop_page);
+		if (static_branch_unlikely(&ipiv_enable)) {
+			free_pages((unsigned long)page_address(vm->vpeid_page),
+				    get_order(nr_irqs * 2));
+		}
 	}
 }
 
@@ -5023,8 +5095,10 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 	struct irq_chip *irqchip = &its_vpe_irq_chip;
 	struct its_vm *vm = args;
 	unsigned long *bitmap;
-	struct page *vprop_page;
+	struct page *vprop_page, *vpeid_page;
 	int base, nr_ids, i, err = 0;
+	void *vpeid_table_va;
+	u16 *vpeid_entry;
 
 	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
 	if (!bitmap)
@@ -5047,14 +5121,33 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
 	vm->vprop_page = vprop_page;
 	raw_spin_lock_init(&vm->vmapp_lock);
 
-	if (gic_rdists->has_rvpeid)
+	if (gic_rdists->has_rvpeid) {
 		irqchip = &its_vpe_4_1_irq_chip;
+		if (static_branch_unlikely(&ipiv_enable)) {
+			/*
+			 * The vpeid's size is 2 bytes, so we need to allocate 2 *
+			 * (num of vcpus). nr_irqs is equal to the number of vCPUs.
+			 */
+			vpeid_page = alloc_pages(GFP_KERNEL, get_order(nr_irqs * 2));
+			if (!vpeid_page) {
+				its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
+				its_free_prop_table(vm->vprop_page);
+				return -ENOMEM;
+			}
+			vm->vpeid_page = vpeid_page;
+			vpeid_table_va = page_address(vm->vpeid_page);
+		}
+	}
 
 	for (i = 0; i < nr_irqs; i++) {
 		vm->vpes[i]->vpe_db_lpi = base + i;
 		err = its_vpe_init(vm->vpes[i]);
 		if (err)
 			break;
+		if (static_branch_unlikely(&ipiv_enable)) {
+			vpeid_entry = (u16 *)vpeid_table_va + i;
+			*(u16 *)vpeid_entry = vm->vpes[i]->vpe_id;
+		}
 		err = its_irq_gic_domain_alloc(domain, virq + i,
 					       vm->vpes[i]->vpe_db_lpi);
 		if (err)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 0af1eed9ad351dbe62823f8ca0e5163f694e11d6..7a64d77be181d092bfaa4cb2368ab792e4fc9643 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -111,6 +111,9 @@ static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
 EXPORT_SYMBOL(gic_nonsecure_priorities);
 
+DEFINE_STATIC_KEY_FALSE(ipiv_enable);
+EXPORT_SYMBOL(ipiv_enable);
+
 /*
  * When the Non-secure world has access to group 0 interrupts (as a
  * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
@@ -1511,6 +1514,36 @@ static int gic_dist_supports_lpis(void)
 		!gicv3_nolpi);
 }
 
+bool is_gicv4p1(void)
+{
+	if (!gic_data.rdists.has_rvpeid)
+		return false;
+
+	return true;
+}
+EXPORT_SYMBOL(is_gicv4p1);
+
+void gic_dist_enable_ipiv(void)
+{
+	u32 val;
+
+	val = readl_relaxed(gic_data.dist_base + GICD_MISC_CTRL);
+	val |= GICD_MISC_CTRL_CFG_IPIV_EN;
+	writel_relaxed(val, gic_data.dist_base + GICD_MISC_CTRL);
+	static_branch_enable(&ipiv_enable);
+
+	val = (0 << GICD_IPIV_CTRL_AFF_DIRECT_VPEID_SHIFT) |
+		(0 << GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT) |
+		(4 << GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT) |
+		(7 << GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT) |
+		(2 << GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT);
+	writel_relaxed(val, gic_data.dist_base + GICD_IPIV_CTRL);
+
+	/* Set target ITS address of IPIV feature */
+	writel_relaxed(0x4880, gic_data.dist_base + GICD_IPIV_ITS_TA_BASE);
+}
+EXPORT_SYMBOL(gic_dist_enable_ipiv);
+
 static void gic_cpu_init(void)
 {
 	void __iomem *rbase;
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 548b8a5c46cfcd383a3b1304742d28506b267671..5fdc3ae4cd9958ac87659a4e67765586e6c4c1dd 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -113,6 +113,18 @@
 #define GIC_PAGE_SIZE_64K		2ULL
 #define GIC_PAGE_SIZE_MASK		3ULL
 
+#define GICD_MISC_CTRL			0x2084
+#define GICD_MISC_CTRL_CFG_IPIV_EN	(1U << 19)
+
+/* IPIV private register */
+#define GICD_IPIV_CTRL			0xc05c
+#define GICD_IPIV_CTRL_AFF_DIRECT_VPEID_SHIFT 4
+#define GICD_IPIV_CTRL_AFF1_LEFT_SHIFT_SHIFT 8
+#define GICD_IPIV_CTRL_AFF2_LEFT_SHIFT_SHIFT 12
+#define GICD_IPIV_CTRL_VM_TABLE_INNERCACHE_SHIFT 16
+#define GICD_IPIV_CTRL_VM_TABLE_SHAREABILITY_SHIFT 19
+#define GICD_IPIV_ITS_TA_BASE	0xc010
+
 /*
  * Re-Distributor registers, offsets from RD_base
  */
@@ -362,6 +374,18 @@
 #define GICR_VSGIPENDR_BUSY		(1U << 31)
 #define GICR_VSGIPENDR_PENDING		GENMASK(15, 0)
 
+/* IPIV VM table address */
+#define GICR_VM_TABLE_BAR_L		0x140
+#define GICR_VM_TABLE_BAR_H		0x144
+
+#define GICR_IPIV_CTRL		0x148
+#define GICR_IPIV_CTRL_VCPU_ENTRY_NUM_MAX_SHIFT 8
+#define GICR_IPIV_CTRL_IPIV_ITS_TA_SEL_SHIFT 4
+
+#define GICR_IPIV_ST		0x14c
+#define GICR_IPIV_ST_IPIV_BUSY_SHIFT 0
+#define GICR_IPIV_ST_IPIV_BUSY (1 << GICR_IPIV_ST_IPIV_BUSY_SHIFT)
+
 /*
  * ITS registers, offsets from ITS_base
  */
diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h
index 2d6f41001a46fa7872e04db222520120826f7234..9109a841c8da1ef741df4de26d0ded442c9e10e1 100644
--- a/include/linux/irqchip/arm-gic-v4.h
+++ b/include/linux/irqchip/arm-gic-v4.h
@@ -34,6 +34,8 @@ struct its_vm {
 	 */
 	raw_spinlock_t		vmapp_lock;
 	u32			vlpi_count[GICv4_ITS_LIST_MAX];
+	KABI_EXTEND(struct page		*vpeid_page)
+	KABI_EXTEND(bool			nassgireq)
 };
 
 /* Embedded in kvm_vcpu.arch */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 52695dea196e5c150664e943fdd53297a14d3ee5..582d65422f81990531556a64d6d4e65345375cc0 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1201,6 +1201,8 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
 #define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
 
+#define KVM_CAP_ARM_IPIV_MODE 301 /* ipiv mode */
+
 #define KVM_CAP_SEV_ES_GHCB 500
 #define KVM_CAP_HYGON_COCO_EXT 501
 /* support userspace to request firmware to build CSV3 guest's memory space */