diff --git a/drivers/platform/mpam/mpam_devices.c b/drivers/platform/mpam/mpam_devices.c
index ebc8887d8267a22987d3940a043a8432b2f54090..387fc444267c9982d959c07250437789a7a31c17 100644
--- a/drivers/platform/mpam/mpam_devices.c
+++ b/drivers/platform/mpam/mpam_devices.c
@@ -91,6 +91,11 @@ static DECLARE_WORK(mpam_broken_work, &mpam_disable);
  */
 LIST_HEAD(mpam_classes);
 
+static const struct midr_range hip12_cpus[] = {
+	MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
+	{ /* sentinel */ }
+};
+
 static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg)
 {
 	WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz);
@@ -576,15 +581,10 @@ static struct mpam_msc_ris *mpam_get_or_create_ris(struct mpam_msc *msc,
 u16 mpam_cpbm_wd_hisi_workaround(u16 cpbm_wd, enum mpam_device_features feat,
 				 u8 cache_level)
 {
-	static const struct midr_range cpus[] = {
-		MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
-		{ /* sentinel */ }
-	};
-
 	if (cache_level != 3)
 		return cpbm_wd;
 
-	if (is_midr_in_range_list(cpus)) {
+	if (is_midr_in_range_list(hip12_cpus)) {
 		if (feat == mpam_feat_cpor_part)
 			return 19;
 		else if (feat == mpam_feat_ccap_part ||
@@ -745,6 +745,14 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
 	}
 }
 
+static int mpam_pmg_max_workaround(u64 idr)
+{
+	if (is_midr_in_range_list(hip12_cpus))
+		return 0;
+
+	return FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
+}
+
 static int mpam_msc_hw_probe(struct mpam_msc *msc)
 {
 	u64 idr;
@@ -770,7 +778,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
 
 	/* Use these values so partid/pmg always starts with a valid value */
 	msc->partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
-	msc->pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
+	msc->pmg_max = mpam_pmg_max_workaround(idr);
 
 	for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
 		spin_lock(&msc->part_sel_lock);
@@ -912,16 +920,11 @@ static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
 static bool mpam_csu_hisi_need_retrigger(struct mpam_msc_ris *ris,
 					 bool read_again)
 {
-	static const struct midr_range cpus[] = {
-		MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
-		{ /* sentinel */ }
-	};
-
 	if (ris->comp->class->type != MPAM_CLASS_CACHE ||
 	    ris->comp->class->level != 3)
 		return false;
 
-	if (!is_midr_in_range_list(cpus))
+	if (!is_midr_in_range_list(hip12_cpus))
 		return false;
 
 	if (read_again)
@@ -994,12 +997,7 @@ static bool mpam_ris_has_nrdy_bit(struct mpam_msc_ris *ris)
 
 static u64 mpam_csu_hisi_need_halved(struct mpam_msc_ris *ris, u64 now)
 {
-	static const struct midr_range cpus[] = {
-		MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
-		{ /* sentinel */ }
-	};
-
-	if (!is_midr_in_range_list(cpus))
+	if (!is_midr_in_range_list(hip12_cpus))
 		return now;
 
 	if (ris->comp->class->type != MPAM_CLASS_CACHE ||
@@ -1296,13 +1294,7 @@ static void mpam_reset_msc_bitmap(struct mpam_msc *msc, u16 reg, u16 wd)
 
 static u32 mpam_cpbm_hisi_workaround(u32 cpbm, u8 cache_level)
 {
-	static const struct midr_range cpus[] = {
-		MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
-		{ /* sentinel */ }
-	};
-
-	if (cache_level != 3 ||
-	   !is_midr_in_range_list(cpus))
+	if (cache_level != 3 || !is_midr_in_range_list(hip12_cpus))
 		return cpbm;
 
 	if (cpbm & BIT(18))
@@ -1316,6 +1308,21 @@ static u32 mpam_cpbm_hisi_workaround(u32 cpbm, u8 cache_level)
 	return cpbm;
 }
 
+bool mpam_cpbm_hisi_check_invalid(struct rdt_resource *r,
+				  unsigned long val)
+{
+	if (!is_midr_in_range_list(hip12_cpus))
+		return false;
+
+	if (r->cache_level != 3)
+		return false;
+
+	if (val & ~(BIT(18) | BIT(17)))
+		return false;
+
+	return true;
+}
+
 static u16 mpam_intpri_default_val(struct mpam_msc_ris *ris)
 {
 	struct mpam_class *class = ris->comp->class;
diff --git a/drivers/platform/mpam/mpam_internal.h b/drivers/platform/mpam/mpam_internal.h
index 204005331334280ffaad8ee3bf58f26e5e3a14ef..7fe4ac6369528e355b3a6de347f44d6c13b698d5 100644
--- a/drivers/platform/mpam/mpam_internal.h
+++ b/drivers/platform/mpam/mpam_internal.h
@@ -329,6 +329,7 @@ int mpam_resctrl_setup(void);
 void mpam_resctrl_exit(void);
 
 u16 mpam_cpbm_wd_hisi_workaround(u16 cpbm_wd, enum mpam_device_features feat, u8 cache_level);
+bool mpam_cpbm_hisi_check_invalid(struct rdt_resource *r, unsigned long val);
 
 /*
  * MPAM MSCs have the following register layout. See:
diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c
index e3ff6a8354a9b7edab4e434b6b747252aad2f2fb..2d3a1827a48ce0772fc6565a008b4bcfa754ff9e 100644
--- a/drivers/platform/mpam/mpam_resctrl.c
+++ b/drivers/platform/mpam/mpam_resctrl.c
@@ -1322,26 +1322,6 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d,
 	}
 }
 
-static bool mpam_cpbm_hisi_check_invalid(struct rdt_resource *r,
-					 unsigned long val)
-{
-	static const struct midr_range cpus[] = {
-		MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
-		{ /* sentinel */ }
-	};
-
-	if (!is_midr_in_range_list(cpus))
-		return false;
-
-	if (r->cache_level != 3)
-		return false;
-
-	if (val & ~(BIT(18) | BIT(17)))
-		return false;
-
-	return true;
-}
-
 int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d,
 			    u32 closid, enum resctrl_conf_type t, u32 cfg_val)
 {