diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c
index 58f726ba022f91c06681c0088f2c509a6fa5dfa6..a568d5363c1e0a0da74e0a244f70f1edb4840cf9 100644
--- a/drivers/crypto/hisilicon/sec2/sec_main.c
+++ b/drivers/crypto/hisilicon/sec2/sec_main.c
@@ -255,33 +255,19 @@ static const struct pci_device_id sec_dev_ids[] = {
 };
 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
 
-static u8 sec_get_endian(struct hisi_qm *qm)
+static void sec_set_endian(struct hisi_qm *qm)
 {
 	u32 reg;
 
-	/*
-	 * As for VF, it is a wrong way to get endian setting by
-	 * reading a register of the engine
-	 */
-	if (qm->pdev->is_virtfn) {
-		dev_err_ratelimited(&qm->pdev->dev,
-				    "cannot access a register in VF!\n");
-		return SEC_LE;
-	}
-	reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF +
-			    SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG);
-
-	/* BD little endian mode */
-	if (!(reg & BIT(0)))
-		return SEC_LE;
+	reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
+	reg &= ~(BIT(1) | BIT(0));
+	if (IS_ENABLED(CONFIG_64BIT))
+		reg |= BIT(1);
 
-	/* BD 32-bits big endian mode */
-	else if (!(reg & BIT(1)))
-		return SEC_32BE;
+	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+		reg |= BIT(0);
 
-	/* BD 64-bits big endian mode */
-	else
-		return SEC_64BE;
+	writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
 }
 
 static int sec_engine_init(struct hisi_qm *qm)
@@ -331,9 +317,7 @@ static int sec_engine_init(struct hisi_qm *qm)
 		       SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG3));
 
 	/* config endian */
-	reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG));
-	reg |= sec_get_endian(qm);
-	writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG));
+	sec_set_endian(qm);
 
 	return 0;
 }
@@ -813,7 +797,7 @@ static int sec_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev)
 {
 	int ret;
 
-	qm->algs = "sec\ncipher\ndigest\naead\n";
+	qm->algs = "cipher\ndigest\naead\n";
 	qm->uacce_mode = uacce_mode;
 	qm->pdev = pdev;
 	ret = hisi_qm_pre_init(qm, pf_q_num, SEC_PF_DEF_Q_BASE);