From 76b745fa3a0e6e72c56231f3b10a7d385d5da4f0 Mon Sep 17 00:00:00 2001 From: Hao Lan Date: Thu, 7 Dec 2023 22:23:09 +0800 Subject: [PATCH 1/3] net: hns3: Disable SerDes serial loopback for HiLink H60 driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8MV8N CVE: NA ---------------------------------------------------------------------- When the hilink is H60, the serdes serial loopback test is not supported. This patch add hilink detection. When the value is H60, the serdes serial loopback test will be disable. Fixes: c39c4d98dc65 ("net: hns3: Add mac loopback selftest support in hns3 driver") Signed-off-by: Hao Lan --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 1 + drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 ++ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 3 ++- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 9 +++++++-- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 6 ++++++ 5 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index d57e7635885c..bec351f71ac7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -453,6 +453,7 @@ struct hnae3_dev_specs { u8 tnl_num; u16 guid_tbl_space; u16 ip_tbl_space; + u8 hilink_version; }; struct hnae3_client_ops { diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c index fefb18feba90..e01b5dad4448 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -1099,6 +1099,8 @@ hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) *pos += scnprintf(buf + *pos, len - *pos, "TX timeout threshold: %d seconds\n", dev->watchdog_timeo / HZ); + *pos += scnprintf(buf + *pos, len - *pos, "Hilink Version: %u\n", + dev_specs->hilink_version); } static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h index 3b2b1831e5da..c22fbf37f5b2 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h @@ -868,7 +868,8 @@ struct hclge_dev_specs_1_cmd { __le16 guid_tbl_space; __le16 ip_tbl_space; u8 tnl_num; - u8 rsv2[5]; + u8 hilink_version; + u8 rsv2[4]; }; /* mac speed type defined in firmware command */ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 228882cb3bfb..f703cd1f7175 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -704,8 +704,12 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; } - count += 1; - handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; + if (hdev->ae_dev->dev_specs.hilink_version != + HCLGE_HILINK_H60) { + count += 1; + handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; + } + count += 1; handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; count += 1; @@ -1424,6 +1428,7 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev, ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); ae_dev->dev_specs.tnl_num = req1->tnl_num; + ae_dev->dev_specs.hilink_version = req1->hilink_version; #ifdef CONFIG_HNS3_UBL if (hnae3_dev_ubl_supported(ae_dev)) { ae_dev->dev_specs.guid_tbl_space = diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index f2f49de992ff..bf8af8b7ca91 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -259,6 +259,12 @@ enum HCLGE_MAC_DUPLEX { HCLGE_MAC_FULL }; +/* hilink version */ +enum hclge_hilink_version { + HCLGE_HILINK_H32 = 0, + HCLGE_HILINK_H60 = 1, +}; + #define QUERY_SFP_SPEED 0 #define QUERY_ACTIVE_SPEED 1 -- Gitee From 677ddbc711b470928a5271fa288b4de2f0968469 Mon Sep 17 00:00:00 2001 From: Hao Lan Date: Mon, 11 Dec 2023 17:09:59 +0800 Subject: [PATCH 2/3] net: hns3: add new 200G link modes for hisilicon device driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8OH8B CVE: NA ---------------------------------------------------------------------- The hisilicon device now supports a new 200G link interface, which query from firmware in a new bit. Therefore, the HCLGE_SUPPORT_200G_R4_BIT capability bit has been added. The HCLGE_SUPPORT_200G_BIT has been renamed as HCLGE_SUPPORT_200G_R4_EXT_BIT, and the firmware has extended support for this mode. Fixes: ae6f010cb1a7 ("net: hns3: add support for 200G device") Signed-off-by: Hao Lan --- .../hisilicon/hns3/hns3pf/hclge_main.c | 28 ++++++++++++------- .../hisilicon/hns3/hns3pf/hclge_main.h | 5 +++- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index f703cd1f7175..047d3280a138 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -962,7 +962,7 @@ static const struct hclge_speed_bit_map speed_bit_map[] = { {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, - {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, + {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, }; static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) @@ -1018,7 +1018,7 @@ static void hclge_update_fec_support(struct hclge_mac *mac) mac->supported); } -static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = { +static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, @@ -1026,10 +1026,12 @@ static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = { {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, - {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_EXT_BIT, + ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, }; -static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = { +static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, @@ -1037,11 +1039,13 @@ static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = { ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, - {HCLGE_SUPPORT_200G_BIT, + {HCLGE_SUPPORT_200G_R4_EXT_BIT, + ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, }; -static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = { +static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, @@ -1049,10 +1053,12 @@ static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = { {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, - {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_EXT_BIT, + ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, }; -static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = { +static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, @@ -1061,7 +1067,9 @@ static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = { {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, - {HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_EXT_BIT, + ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, + {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, }; static void hclge_convert_setting_sr(u16 speed_ability, @@ -1232,7 +1240,7 @@ static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) static u32 hclge_get_max_speed(u16 speed_ability) { - if (speed_ability & HCLGE_SUPPORT_200G_BIT) + if (speed_ability & HCLGE_SUPPORT_200G_BITS) return HCLGE_MAC_SPEED_200G; if (speed_ability & HCLGE_SUPPORT_100G_BITS) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index bf8af8b7ca91..6d17f36e5e0e 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -195,9 +195,10 @@ enum HLCGE_PORT_TYPE { #define HCLGE_SUPPORT_40G_BIT BIT(5) #define HCLGE_SUPPORT_100M_BIT BIT(6) #define HCLGE_SUPPORT_10M_BIT BIT(7) -#define HCLGE_SUPPORT_200G_BIT BIT(8) +#define HCLGE_SUPPORT_200G_R4_EXT_BIT BIT(8) #define HCLGE_SUPPORT_50G_R1_BIT BIT(9) #define HCLGE_SUPPORT_100G_R2_BIT BIT(10) +#define HCLGE_SUPPORT_200G_R4_BIT BIT(11) #define HCLGE_SUPPORT_GE \ (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) @@ -205,6 +206,8 @@ enum HLCGE_PORT_TYPE { (HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT) #define HCLGE_SUPPORT_100G_BITS \ (HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT) +#define HCLGE_SUPPORT_200G_BITS \ + (HCLGE_SUPPORT_200G_R4_EXT_BIT | HCLGE_SUPPORT_200G_R4_BIT) enum HCLGE_DEV_STATE { HCLGE_STATE_REINITING, -- Gitee From e526b8bd87b61060dae9e2770fed2327030072ee Mon Sep 17 00:00:00 2001 From: Hao Chen Date: Thu, 7 Dec 2023 18:53:34 +0800 Subject: [PATCH 3/3] net: hns3: add use limit for 1D torus feature driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8MV8N CVE: NA ---------------------------------------------------------------------- 1D torus feature is not supported for board which version is V4. So, add judgement for it. Fixes: 18c7dc4f0711 ("net: hns3: add support to get/set 1d torus param") Signed-off-by: Hao Chen --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 1 + drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index bec351f71ac7..79bc5d531ce3 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -41,6 +41,7 @@ #define HNAE3_DEVICE_VERSION_V1 0x00020 #define HNAE3_DEVICE_VERSION_V2 0x00021 #define HNAE3_DEVICE_VERSION_V3 0x00030 +#define HNAE3_DEVICE_VERSION_V4 0x00032 #define HNAE3_PCI_REVISION_BIT_SIZE 8 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c index 9c73b4291228..e999c6c5fa66 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c @@ -281,6 +281,9 @@ static int hclge_set_torus_param(struct hclge_dev *hdev, void *data, struct hnae3_torus_param *param = (struct hnae3_torus_param *)data; int ret; + if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V4) + return -EOPNOTSUPP; + if (length != sizeof(struct hnae3_torus_param)) return -EINVAL; @@ -318,6 +321,9 @@ static int hclge_get_torus_param(struct hclge_dev *hdev, void *data, struct hclge_desc desc; int ret; + if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V4) + return -EOPNOTSUPP; + if (length != sizeof(struct hnae3_torus_param)) return -EINVAL; -- Gitee