From ea7db710f631beac8eafa8bcd11159c2a799c2fe Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Tue, 14 Mar 2023 10:00:39 -0700 Subject: [PATCH 1/4] perf/x86/intel: Add Granite Rapids mainline inclusion from mainline-v6.4-rc1 commit bc4000fdb009a531fc5b94339f8531eee64bc232 category: feature feature: GNR core PMU bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bc4000fdb009a531fc5b94339f8531eee64bc232 Intel-SIG: commit bc4000fdb009 perf/x86/intel: Add Granite Rapids Backport Granite Rapids core PMU support to kernel 5.10. ------------------------------------- From core PMU's perspective, Granite Rapids is similar to the Sapphire Rapids. The key differences include: - Doesn't need the AUX event workaround for the mem load event. (Implement in this patch). - Support Retire Latency (Has been implemented in the commit c87a31093c70 ("perf/x86: Support Retire Latency")) - The event list, which will be supported in the perf tool later. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20230314170041.2967712-1-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/intel/core.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 8de383e42730..f9fe2e5e0a7d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5139,6 +5139,15 @@ pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) return x86_pmu.pebs ? attr->mode : 0; } +static umode_t +mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) +{ + if (attr == &event_attr_mem_ld_aux.attr.attr) + return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0; + + return pebs_is_visible(kobj, attr, i); +} + static umode_t lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) { @@ -5166,7 +5175,7 @@ static struct attribute_group group_events_td = { static struct attribute_group group_events_mem = { .name = "events", - .is_visible = pebs_is_visible, + .is_visible = mem_is_visible, }; static struct attribute_group group_events_tsx = { @@ -5792,6 +5801,10 @@ __init int intel_pmu_init(void) case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_EMERALDRAPIDS_X: + x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; + fallthrough; + case INTEL_FAM6_GRANITERAPIDS_X: + case INTEL_FAM6_GRANITERAPIDS_D: pmem = true; x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids)); @@ -5808,7 +5821,6 @@ __init int intel_pmu_init(void) x86_pmu.flags |= PMU_FL_NO_HT_SHARING; x86_pmu.flags |= PMU_FL_PEBS_ALL; x86_pmu.flags |= PMU_FL_INSTR_LATENCY; - x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = spr_get_event_constraints; -- Gitee From 389b5fe7da8bfb1fd7b4781b0e60207aafd4407e Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Tue, 14 Mar 2023 10:00:40 -0700 Subject: [PATCH 2/4] perf/x86/msr: Add Granite Rapids mainline inclusion from mainline-v6.4-rc1 commit 5a796d5cb5d11f5aad4893a59f22715810769928 category: feature feature: GNR core PMU bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5a796d5cb5d11f5aad4893a59f22715810769928 Intel-SIG: commit 5a796d5cb5d1 perf/x86/msr: Add Granite Rapids Backport Granite Rapids core PMU support to kernel 5.10. ------------------------------------- The same as Sapphire Rapids, the SMI_COUNT MSR is also supported on Granite Rapids. Add Granite Rapids model. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20230314170041.2967712-2-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/msr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 2b74e81fc09a..cb4462fae77c 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -70,6 +70,8 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_EMERALDRAPIDS_X: + case INTEL_FAM6_GRANITERAPIDS_X: + case INTEL_FAM6_GRANITERAPIDS_D: case INTEL_FAM6_ATOM_SILVERMONT: case INTEL_FAM6_ATOM_SILVERMONT_D: -- Gitee From 0889138f5424ffeb86642dd1e15c938e26830c34 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 14 Mar 2023 10:00:41 -0700 Subject: [PATCH 3/4] perf/x86/cstate: Add Granite Rapids support mainline inclusion from mainline-v6.4-rc1 commit 872d28001be56b205bd9b3f97cea1571a1bde317 category: feature feature: GNR core PMU bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=872d28001be56b205bd9b3f97cea1571a1bde317 Intel-SIG: commit 872d28001be5 perf/x86/cstate: Add Granite Rapids support Backport Granite Rapids core PMU support to kernel 5.10. ------------------------------------- Granite Rapids Xeon is successor or Emerald Rapids Xeon, and it will use the same C-state residency counters as Emerald Rapids (and previous Xeons, all the way back to Ice Lake Xeon). Add Granite Rapids Xeon support. Signed-off-by: Artem Bityutskiy Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20230314170041.2967712-3-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/intel/cstate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index a56bcf798048..e58eb407c947 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -659,6 +659,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &icx_cstates), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &icx_cstates), X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &icx_cstates), + X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X, &icx_cstates), + X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D, &icx_cstates), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates), -- Gitee From bef0f5daf0298fd58b6f2bb4a64722a99ed77e63 Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Thu, 15 Jun 2023 10:32:42 -0700 Subject: [PATCH 4/4] perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL mainline inclusion from mainline-v6.4 commit a6742cb90b567f952a95efa27dee345748d09fc7 category: feature feature: GNR core PMU bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41 CVE: NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a6742cb90b567f952a95efa27dee345748d09fc7 Intel-SIG: commit a6742cb90b56 perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL Backport a following upstream bugfix for GNR core PMU support. ------------------------------------- When counting a FRONTEND event, the MSR_PEBS_FRONTEND is not correctly set on GNR and MTL p-core. The umask value for the FRONTEND events is changed on GNR and MTL. The new umask is missing in the extra_regs[] table. Add a dedicated intel_gnr_extra_regs[] for GNR and MTL p-core. Fixes: bc4000fdb009 ("perf/x86/intel: Add Granite Rapids") Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20230615173242.3726364-1-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/intel/core.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index f9fe2e5e0a7d..ccafd242162e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -326,6 +326,16 @@ static struct event_constraint intel_spr_event_constraints[] = { EVENT_CONSTRAINT_END }; +static struct extra_reg intel_gnr_extra_regs[] __read_mostly = { + INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), + INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), + INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), + INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), + INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE), + INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE), + EVENT_EXTRA_END +}; EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3"); EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3"); @@ -5802,6 +5812,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_EMERALDRAPIDS_X: x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX; + x86_pmu.extra_regs = intel_spr_extra_regs; fallthrough; case INTEL_FAM6_GRANITERAPIDS_X: case INTEL_FAM6_GRANITERAPIDS_D: @@ -5812,7 +5823,8 @@ __init int intel_pmu_init(void) x86_pmu.event_constraints = intel_spr_event_constraints; x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; - x86_pmu.extra_regs = intel_spr_extra_regs; + if (!x86_pmu.extra_regs) + x86_pmu.extra_regs = intel_gnr_extra_regs; x86_pmu.limit_period = spr_limit_period; x86_pmu.pebs_aliases = NULL; x86_pmu.pebs_prec_dist = true; -- Gitee