From 2e5e2919494b1ad90dc349fef8415cba098c93df Mon Sep 17 00:00:00 2001 From: Devyn Liu Date: Thu, 1 Feb 2024 14:13:44 +0800 Subject: [PATCH 1/2] i2c: hisi: Optimized the value setting of maxwrite limit to fifo depth - 1 maillist inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I92EM3 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git/commit/?h=i2c/i2c-host&id=69dc3880100288972fe341c2c59c40fdecf511f5 -------------------------------------- The driver finishes a write cycle by read the fifo tx full status or write limit decrease to 0. The driver starts to write data to the FIFO after the I2C FIFO almost empty interrupt is reported. The threshold for FIFO almost empty interrupt is that the amount of data in the FIFO is less than or equal to 1. Reduce write maxwrite to the fifo depth - aempty interrupt threshold. Limiting the number of data to be written at a time to remaining fifo capacity. Signed-off-by: Devyn Liu Reviewed-by: Yicong Yang Reviewed-by: Andi Shyti Signed-off-by: Andi Shyti (cherry picked from commit 80c5f30afa7d58cf1ff7a0b56ce85d27659a9f3c) --- drivers/i2c/busses/i2c-hisi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c index e6e40236e6ec..3448f9527a3f 100644 --- a/drivers/i2c/busses/i2c-hisi.c +++ b/drivers/i2c/busses/i2c-hisi.c @@ -270,7 +270,7 @@ static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) { - int max_write = HISI_I2C_TX_FIFO_DEPTH; + int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH; bool need_restart = false, last_msg; struct i2c_msg *cur_msg; u32 cmd, fifo_state; -- Gitee From aff8d64f01742db851afc878557b28615c064d10 Mon Sep 17 00:00:00 2001 From: Devyn Liu Date: Thu, 1 Feb 2024 14:13:45 +0800 Subject: [PATCH 2/2] i2c: hisi: Add clearing tx aempty interrupt operation maillist inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I92EM3 Reference: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git/commit/?h=i2c/i2c-host&id=2f9af34c79ffd97858649822e1730ead2a31f6c6 ----------------------------------------------------- The driver receives the tx fifo almost empty(aempty) interrupt and reads the tx_aempty_int_mstat to start a round of data transfer. The operation of clearing the TX aempty interrupt after completing a write cycle is added to ensure that the FIFO is truly at almost empty status when an aempty interrupt is received. The threshold for fifo almost empty interrupt is defined as 1. Signed-off-by: Devyn Liu Reviewed-by: Yicong Yang Reviewed-by: Andi Shyti Signed-off-by: Andi Shyti (cherry picked from commit 12b08189a0495c72b5098943a538f22974df608d) --- drivers/i2c/busses/i2c-hisi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c index 3448f9527a3f..8c6ca1ec401a 100644 --- a/drivers/i2c/busses/i2c-hisi.c +++ b/drivers/i2c/busses/i2c-hisi.c @@ -57,6 +57,8 @@ #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) #define HISI_I2C_HS_SPK_LEN 0x003c #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) +#define HISI_I2C_TX_INT_CLR 0x0040 +#define HISI_I2C_TX_AEMPTY_INT BIT(0) #define HISI_I2C_INT_MSTAT 0x0044 #define HISI_I2C_INT_CLR 0x0048 #define HISI_I2C_INT_MASK 0x004C @@ -128,6 +130,11 @@ static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); } +static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask) +{ + writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); +} + static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) { u32 int_err = ctlr->xfer_err, reg; @@ -172,6 +179,7 @@ static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); return 0; @@ -327,6 +335,8 @@ static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) */ if (ctlr->msg_tx_idx == ctlr->msg_num) hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY); + + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); } static irqreturn_t hisi_i2c_irq(int irq, void *context) @@ -367,6 +377,7 @@ static irqreturn_t hisi_i2c_irq(int irq, void *context) if (int_stat & HISI_I2C_INT_TRANS_CPLT) { hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); complete(ctlr->completion); } -- Gitee