diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 5100469fef323206881b62c9963c8f7f17ec31ee..a4c164e7f9c03dc35be7fac6c3a434eb43ec8c25 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -203,7 +203,7 @@ static u64 l3_thread_slice_mask(u64 config)
 
 	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
 	    boot_cpu_data.x86 == 0x18) {
-		if (boot_cpu_data.x86_model == 0x6)
+		if (boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf)
 			return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |
 			       ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);
 		else
@@ -282,7 +282,8 @@ amd_f17h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)
 static umode_t
 hygon_f18h_m6h_uncore_is_visible(struct kobject *kobj, struct attribute *attr, int i)
 {
-	return boot_cpu_data.x86 == 0x18 && boot_cpu_data.x86_model == 0x6 ?
+	return boot_cpu_data.x86 == 0x18 &&
+	       boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf ?
 	       attr->mode : 0;
 }
 
@@ -755,7 +756,7 @@ static int __init amd_uncore_init(void)
 			   boot_cpu_data.x86 == 0x18) {
 			*l3_attr++ = &format_attr_event8.attr;
 			*l3_attr++ = &format_attr_umask8.attr;
-			if (boot_cpu_data.x86_model == 0x6) {
+			if (boot_cpu_data.x86_model >= 0x6 && boot_cpu_data.x86_model <= 0xf) {
 				*l3_attr++ = &format_attr_threadmask32.attr;
 				amd_llc_pmu.attr_update = hygon_uncore_l3_attr_update;
 			} else {
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index ff44efecae5ecceec831c2c80af82d3848f6b55d..2c4b64994c6d48822667167a82bddb6b6667183a 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -286,6 +286,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value
 				device = PCI_DEVICE_ID_HYGON_18H_M04H_DF_F1;
 			break;
 		case 0x6:
+		case 0x7:
 			device = PCI_DEVICE_ID_HYGON_18H_M05H_DF_F1;
 			break;
 		default:
@@ -294,6 +295,7 @@ static int get_df_register(struct pci_dev *misc, u8 func, int offset, u32 *value
 	} else if (func == 5) {
 		switch (boot_cpu_data.x86_model) {
 		case 0x6:
+		case 0x7:
 			device = PCI_DEVICE_ID_HYGON_18H_M06H_DF_F5;
 			break;
 		default:
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 75e12117a23e0b01fd31e8b5d80d1dcb952263b0..c239db751093013eefd81920c406314732eeacd1 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3786,6 +3786,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
 			fam_type = &family_types[F18_M06H_CPUS];
 			pvt->ops = &family_types[F18_M06H_CPUS].ops;
 			break;
+		} else if (pvt->model == 0x7) {
+			fam_type = &family_types[F18_M06H_CPUS];
+			pvt->ops = &family_types[F18_M06H_CPUS].ops;
+			family_types[F18_M06H_CPUS].ctl_name = "F18h_M07h";
+			break;
 		}
 		fam_type	= &family_types[F17_CPUS];
 		pvt->ops	= &family_types[F17_CPUS].ops;