diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 5e6bacda05d8620f85f2963efca794eccbb3df41..63db8e5ec9f8a915a7cbddfddaba6b4e08049d48 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -466,9 +466,10 @@ USER(\label, ic	ivau, \tmp2)			// invalidate I line PoU
  */
 	.macro	reset_pmuserenr_el0, tmpreg
 	mrs	\tmpreg, id_aa64dfr0_el1
-	sbfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
-	cmp	\tmpreg, #1			// Skip if no PMU present
-	b.lt	9000f
+	ubfx	\tmpreg, \tmpreg, #ID_AA64DFR0_PMUVER_SHIFT, #4
+	cmp     \tmpreg, #ID_AA64DFR0_PMUVER_NI
+	ccmp    \tmpreg, #ID_AA64DFR0_PMUVER_IMP_DEF, #4, ne
+	b.eq	9000f
 	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
 9000:
 	.endm
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8bcc9ac9963e757ff1bc4e089c7c5f6669a5fa7c..9705f7abd42871475d95408396aee49b8c9f34b2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1488,6 +1488,7 @@
 #define ID_AA64DFR0_EL1_BRBE_NI		0x0
 #define ID_AA64DFR0_EL1_BRBE_IMP	0x1
 #define ID_AA64DFR0_EL1_BRBE_BRBE_V1P1	0x2
+#define ID_AA64DFR0_PMUVER_NI		0x0
 #define ID_AA64DFR0_PMUVER_8_0		0x1
 #define ID_AA64DFR0_PMUVER_8_1		0x4
 #define ID_AA64DFR0_PMUVER_8_4		0x5
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 91890de6cefaa3ac9ef672fd1e3808cd73458387..b44213388bab155e85bec9256aeec28338d15493 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -623,13 +623,14 @@ set_hcr:
 
 	/* EL2 debug */
 	mrs	x1, id_aa64dfr0_el1
-	sbfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
-	cmp	x0, #1
-	b.lt	4f				// Skip if no PMU present
+	ubfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
+	cmp	x0, #ID_AA64DFR0_PMUVER_NI
+	ccmp	x0, #ID_AA64DFR0_PMUVER_IMP_DEF, #4, ne
+	b.eq	4f				// Skip if no PMU present
 	mrs	x0, pmcr_el0			// Disable debug access traps
 	ubfx	x0, x0, #11, #5			// to EL2 and allow access to
 4:
-	csel	x3, xzr, x0, lt			// all PMU counters from EL1
+	csel	x3, xzr, x0, eq			// all PMU counters from EL1
 
 	/* Statistical profiling */
 	ubfx	x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4