diff --git a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
index 2dcb561a4882ebc4505f1b229c2f6a13375e8edc..b8ec7d4a39eea700b246e9bb179a24ced62c81c0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 def HIP12Model : SchedMachineModel {
-  let IssueWidth            =  16; // HIP12 can dispatch 16 micro-ops per cycle.
+  let IssueWidth            =   8; // HIP12 can dispatch 16 micro-ops per cycle.
   let MicroOpBufferSize     = 320; // Based on the reorder buffer.
   let LoadLatency           =   4; // Basic latency for most load instructions.
   let MispredictPenalty     =  10; // Based on ALU pipeline depth.