From 010fdab999748532aaab37e5bf320d1ae8fbe036 Mon Sep 17 00:00:00 2001 From: liuke20 Date: Thu, 13 Aug 2020 15:31:42 +0800 Subject: [PATCH] Add new functions, test examples and refactor. Signed-off-by: liuke20 --- README | 41 ++ prefetch_mod.c | 895 +++++++++++++++++++++++++--------------- prefetch_mod.h | 227 +++++++++- prefetch_reg.c | 801 ++++++++++++++++++++++++++++------- tests/HhaCanumH.sh | 98 +++++ tests/HhaCanumL.sh | 98 +++++ tests/HhaCtrl.sh | 60 +++ tests/HhaFuncDis.sh | 38 ++ tests/HhaTotemnum.sh | 48 +++ tests/L3tDAuctrl0.sh | 53 +++ tests/L3tDAuctrl1.sh | 133 ++++++ tests/L3tDynamicCtrl.sh | 96 +++++ tests/L3tPrefetch.sh | 264 ++++++++++++ 13 files changed, 2346 insertions(+), 506 deletions(-) create mode 100644 tests/HhaCanumH.sh create mode 100644 tests/HhaCanumL.sh create mode 100644 tests/HhaCtrl.sh create mode 100644 tests/HhaFuncDis.sh create mode 100644 tests/HhaTotemnum.sh create mode 100644 tests/L3tDAuctrl0.sh create mode 100644 tests/L3tDAuctrl1.sh create mode 100644 tests/L3tDynamicCtrl.sh create mode 100644 tests/L3tPrefetch.sh diff --git a/README b/README index a45d941..97e7242 100644 --- a/README +++ b/README @@ -7,6 +7,47 @@ Build: There will be some files under /sys/class/misc/prefetch/ policy: Prefetch policy, can be set to 0~15. read_unique: Whether to allow cross-numa access to cache. 0--allow 1--forbid. + iocapacity_limit: Whether to limit the io capacity of cache. 0--unlimiet 1--limit. + tag_rep_alg: Choose cache line algorithm. 0--random 1--drrip 2--plru 3--random. + ramswap: Full or partial when doing ramswap. 1--partial 0--full. + sqmerge: whether consecutive address access can occupy only one entry in the squeue to accelerate the merge process. 0--limit 1--merge. + prefetch_drop_hha: Whether to merge a non-prefetch operation with the previous prefetch operation. 0--allow 1--limit. + prime_drop_mask: Enable prefetch to retry randomly. 0--disable 1--enable. + sequence_opt: Whether change the L3T processing to serial mode when blocking. 0--limit 1--enable. + bankintlv: Choose bank interleaving algorithm. 0--simple 1--complex. + prefetch_utl_ddr: The utilization of ddr that leads to the halving the threshold of prefetch. 0--less thean 1/2 1--1/2 2--3/4 3--almost full. + prefetch_utl_ddr_en: Whether to allow the automatic threshold reduction according to the utilization of ddr. 0--forbid 1--allow. + prefetch_utl_l3t: The utilization of l3t that leads to the halving the threshold of prefetch. 0--less thean 1/2 1--1/2 2--3/4 3--almost full. + prefetch_utl_l3t_en: Whether to allow the automatic threshold reduction according to the utilization of l3t. 0--forbid 1--allow. + prefetch_start_level: The number of missing addresses that leads to prefetch. 0--32 1--2 n-1--n, can be 0~31. + totem_dual: Assign the number of totems in each socket. 0--1, 1--2. + canum_sktvec: Vector configuration of chip, active high. Range form 0 to 255. + skt1_tb_cavec: Vector configuration of L3T partition in Socket1 TotemB, active high. Range from 0 to 255. + skt1_ta_cavec: Vector configuration of L3T partition in Socket1 TotemA, active high. Range from 0 to 255. + skt0_tb_cavec: Vector configuration of L3T partition in Socket0 TotemB, active high. Range from 0 to 255. + skt0_ta_cavec: Vector configuration of L3T partition in Socket0 TotemA, active high. Range from 0 to 255. + skt3_tb_cavec: Vector configuration of L3T partition in Socket3 TotemB, active high. Range from 0 to 255. + skt3_ta_cavec: Vector configuration of L3T partition in Socket3 TotemA, active high. Range from 0 to 255. + skt2_tb_cavec: Vector configuration of L3T partition in Socket2 TotemB, active high. Range from 0 to 255. + skt2_ta_cavec: Vector configuration of L3T partition in Socket2 TotemA, active high. Range from 0 to 255. + rdmerge_upgrade_en: Whether to allow the RS to merge with the preceding ReadE. 0--disabl 1--allow. + ddr_compress_opt_en: Optimization switch of support HHA compression access. 0--disable 1--enable. + snpsleep_en: Whether to enable snp sleep. 0--disable 1--enable. + prefetchtgt_en: Whether to enable the prefetchtgt. 0--disable 1--enable. + bankintl_stagger: Simple interleave mode fine-tuning enable. 0--disable --enable. + cpu_pf_lqos_en: Whether to enable the prefetch operation delivered by the CPU to be forcibly processed as the lqos operation. 0--disable 1--enable. + refillsize_com_ada_en: Whether to enable the auto-sensing of the size of the request sent to the HHA. If the size of the continuously received requests is 128 bytes or 64 bytes, the size of the prefetched request is automatically adjusted. 0--disable 1--enable adaptive size adjustment. + refillsize_pre_ada_en: Whether to enable the adaptation of the size of the request sent to the HHA. If the size of the continuously received request is 128 bytes or 64 bytes, the size of the normal request is automatically adjusted. 0--disable 1--enable adaptive size adjustment. + prefetch_overide_level: Initial coverage priority for an operation to enter the prefetch buffer. If the value is incorrect, the threshold is decreased by 1. If the value is correct, the threshold is increased by 1. If the value is 0, the prefetch rule needs to be replaced. range 0~15. + prefetch_vague_en: Indicates whether to enable fuzzy match for prefetch. After the function is enabled, the prefetch summarizes the same 16 KB address rule. The four 4 KB address rules are the same and can be used together. 0--disable 1--enable. + prefetch_core_en: Core prefetch enable; Bit 1 indicates that the core request needs to be prefetched. range 0~15. + prefetch_match_en: Whether to enable the prefetch operation after the prefetch hit. 0--disable 1--enable. + reg_ctrl_prefetch_drop: Prefetch operation discard enable. 0--disable 1--enable. + reg_ctrl_dmcassign: DDR access address alignment enable. 0--The DDR read operation uses the wrap mode, and the address is 32-byte-aligned. The DDR write operation is always in INCR mode, and the address is aligned with the access boundary. 1--The DDR read operation is always in INCR mode, and the address is aligned with the access boundary. The DDR write operation is always in INCR mode, and the address is aligned with the access boundary. + reg_ctrl_rdatabyp: DDR read data bypass memory enable in the HHA. 0--disable 1--The internal data of the HHA is bypassed, and the DDR read data can be transmitted quickly. + reg_dir_replace_alg: Directory replacement algorithm configuration. 0--EDIR random+SDIR random 1--EDIR random+SDIR polling 2--EDIR PLRU+SDIR random 3--EDIR PLRU+SDIR polling + prefetch_comb: Read operation and prefetchtgt merge enable. 0--The read operation can be merged with the fetchtgt operation. 1--The read operation and the fetchtgt merge operation are not allowed. + reg_funcdis_comb: Whether to merge write operations whose size is less than 128 bytes. 0--enable 1--disables the merge function of the write operation. Configuration example: echo 1 > /sys/class/misc/prefetch/read_unique diff --git a/prefetch_mod.c b/prefetch_mod.c index aa67f3d..fe6543b 100644 --- a/prefetch_mod.c +++ b/prefetch_mod.c @@ -1,336 +1,559 @@ - // SPDX-License-Identifier: GPL-2.0 -/* - * Copyright(c) 2019 Huawei Technologies Co., Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "prefetch_mod.h" - -#ifndef is_affinity_mask_valid -#define is_affinity_mask_valid(val) 1 -#endif - -static cpumask_var_t prefetch_cpumask_value; -static cfg_t __percpu *cur_cfg; -static cfg_t __percpu *old_cfg; -static DEFINE_MUTEX(prefetch_mtx); - -static ssize_t read_unique_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count); -static ssize_t read_unique_show(struct device* dev, - struct device_attribute* attr, char* buf); -static ssize_t prefetch_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count); -static ssize_t prefetch_show(struct device* dev, - struct device_attribute* attr, char* buf); -static ssize_t prefetch_mask_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count); -static ssize_t prefetch_mask_show(struct device* dev, - struct device_attribute* attr, char* buf); -static ssize_t iocapacity_limit_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count); -static ssize_t iocapacity_limit_show(struct device* dev, - struct device_attribute* attr, char* buf); - -/* Device create */ -static DEVICE_ATTR(read_unique, S_IRUGO|S_IWUSR, - read_unique_show, read_unique_store); - -static DEVICE_ATTR(policy, S_IRUGO|S_IWUSR, - prefetch_show, prefetch_store); - -static DEVICE_ATTR(cpumask, S_IRUGO|S_IWUSR, - prefetch_mask_show, prefetch_mask_store); - -static DEVICE_ATTR(iocapacity_limit, S_IRUGO|S_IWUSR, - iocapacity_limit_show, iocapacity_limit_store); - -static struct attribute *prefetch_attrs[] = { - &dev_attr_policy.attr, - &dev_attr_cpumask.attr, - &dev_attr_read_unique.attr, - &dev_attr_iocapacity_limit.attr, - NULL, -}; - -static const struct attribute_group prefetch_attr_group = { - .attrs = prefetch_attrs, -}; - -static const struct attribute_group *attr_groups[] = { - &prefetch_attr_group, - NULL, -}; - -static struct miscdevice misc = { - .minor = MISC_DYNAMIC_MINOR, - .name = "prefetch", - .groups = attr_groups, -}; - -/* 0--close, 1--open */ -static ssize_t read_unique_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count) -{ - ssize_t ret = -1; - int value = -1; - - ret = kstrtouint(buf, 0, &value); - if (ret || (value != 0 && value != 1)) { - pr_err("invalid input!\n"); - return count; - } - - mutex_lock(&prefetch_mtx); - on_each_cpu_mask(prefetch_cpumask_value, read_unique_set, &value, 1); - mutex_unlock(&prefetch_mtx); - - return count; -} - -static ssize_t read_unique_show(struct device* dev, - struct device_attribute* attr, char* buf) -{ - int cpu = -1; - int count = 0; - - int __percpu *cur = alloc_percpu(int); - if (!cur) { - pr_err("alloc_percpu fail\n"); - return -ENOMEM; - } - mutex_lock(&prefetch_mtx); - on_each_cpu_mask(prefetch_cpumask_value, read_unique_get, cur, 1); - - for_each_cpu(cpu, prefetch_cpumask_value) { - int *ptr = per_cpu_ptr(cur, cpu); - count += scnprintf(buf + count, PAGE_SIZE, "cpu(%d): %d.\n", - cpu, (ptr == NULL) ? -1 : *ptr); - } - mutex_unlock(&prefetch_mtx); - free_percpu(cur); - return count; -} - - -static ssize_t prefetch_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count) -{ - ssize_t ret = -1; - int policy = -1; - - ret = kstrtouint(buf, 0, &policy); - if (ret) { - pr_err("invalid input\n"); - return count; - } - - mutex_lock(&prefetch_mtx); - if (policy < prefetch_policy_num()) { - on_each_cpu_mask(prefetch_cpumask_value, set_prefetch, prefetch_policy(policy), 1); - } else { - pr_err("policy %d is out of range\n", policy); - } - mutex_unlock(&prefetch_mtx); - - return count; -} - -static ssize_t prefetch_show(struct device* dev, - struct device_attribute* attr, char* buf) -{ - int cpu = -1; - int policy = -1; - int count = 0; - - mutex_lock(&prefetch_mtx); - on_each_cpu_mask(prefetch_cpumask_value, get_prefetch, cur_cfg, 1); - for_each_cpu(cpu, prefetch_cpumask_value) { - cfg_t *this_cfg = per_cpu_ptr(cur_cfg, cpu); - for (policy = prefetch_policy_num() - 1; policy >= 0; policy--) { - if (!memcmp(prefetch_policy(policy), this_cfg, sizeof(cfg_t))) - break; - } - count += scnprintf(buf + count, PAGE_SIZE, "cpu(%d): %d\n", - cpu, policy); - } - mutex_unlock(&prefetch_mtx); - - return count; -} - -static ssize_t prefetch_mask_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count) -{ - int ret = -1; - - mutex_lock(&prefetch_mtx); - ret = cpulist_parse(buf, prefetch_cpumask_value); - if (ret) { - pr_err("cpulist_parse error: %d\n", ret); - goto prefetch_mask_end; - } - - if (!is_affinity_mask_valid(prefetch_cpumask_value)) { - pr_err("mask value error\n"); - goto prefetch_mask_end; - } - -prefetch_mask_end: - mutex_unlock(&prefetch_mtx); - return count; -} - -static ssize_t prefetch_mask_show(struct device* dev, - struct device_attribute* attr, char* buf) -{ - ssize_t ret = -1; - mutex_lock(&prefetch_mtx); - ret = cpumap_print_to_pagebuf(true, buf, prefetch_cpumask_value); - mutex_unlock(&prefetch_mtx); - return ret; -} - -/* 0--unlimit, 1--limit */ -static ssize_t iocapacity_limit_store(struct device* dev, - struct device_attribute* attr, const char* buf, size_t count) -{ - ssize_t ret = -1; - int iocapacity_limit = -1; - - ret = kstrtouint(buf, 0, &iocapacity_limit); - if (ret || (iocapacity_limit != 0 && iocapacity_limit != 1)) { - pr_err("invalid input!\n"); - return count; - } - - iocapacity_limit_set(&iocapacity_limit); - - return count; -} - -static ssize_t iocapacity_limit_show(struct device* dev, - struct device_attribute* attr, char* buf) -{ - int reg =1, count = 0; - unsigned int die_idx = 0, skt_idx = 0; - unsigned long skt_offset = 0x200000000000ULL; - unsigned nr_skt = 2, totem_num = 1; - nr_skt = get_nr_skt(); - totem_num = get_totem_num(); - skt_offset = get_skt_offset(); - for (skt_idx = 0; skt_idx < nr_skt; skt_idx++) { - for (die_idx = 0; die_idx < 2; die_idx++) { - unsigned long base2 = 0, addres = 0; - unsigned long base = skt_idx * skt_offset;//g_cpu_info_skt_offset; - unsigned val = 0; - if ((totem_num == 1) && (die_idx == 1)) - continue; - if (die_idx == 1) - base += TOTEM_OFFSET; - base2 = (unsigned long)ioremap(base + TB_L3T0_BASE, REG_RANGE); - if (!base2) - return count; - addres = base2 + L3T_DYNAMIC_CTRL; - val = iocapacity_limit_get(&addres); - count += scnprintf(buf + count, PAGE_SIZE, "register(%d): %d.\n", - reg++, val); - iounmap((volatile void*)base2); - } - } - return count; -} - -/* - * prefetch policy, can be 0~15: - * 0: disable; 1~15: different thresholds for sms,amop algrithom; - */ -static int __init prefetch_init(void) -{ - int ret = -1; - int cpu = -1; - /* mask: initial a mask */ - if (!alloc_cpumask_var(&prefetch_cpumask_value, GFP_KERNEL)) { - ret = -ENOMEM; - goto err_mask_alloc; - } - - cpumask_clear(prefetch_cpumask_value); - for_each_online_cpu(cpu) - cpumask_set_cpu(cpu, prefetch_cpumask_value); - - if (!is_affinity_mask_valid(prefetch_cpumask_value)) { - pr_err("incalid affinity_mask\n"); - ret = -EINVAL; - goto err_mask_init; - } - - cur_cfg = alloc_percpu(cfg_t); - if (!cur_cfg) { - pr_err("alloc_percpu fail\n"); - ret = -ENOMEM; - goto err_mask_init; - } - - old_cfg = alloc_percpu(cfg_t); - if (!old_cfg) { - pr_err("alloc_percpu fail\n"); - ret = -ENOMEM; - goto err_cfg_alloc; - } - - on_each_cpu(get_prefetch, old_cfg, 1); - - /*get cpu infomation to identify iocapacity_limit registers*/ - initial_cpu_info(); - - /* initial prefetch misc and initial prefetch_ops */ - ret = misc_register(&misc); - if (ret < 0) { - pr_err("misc register fail\n"); - goto err_misc_reg; - } - - return 0; - -err_misc_reg: - free_percpu(old_cfg); -err_cfg_alloc: - free_percpu(cur_cfg); -err_mask_init: - free_cpumask_var(prefetch_cpumask_value); -err_mask_alloc: - return ret; -} - -static void __exit prefetch_exit(void) -{ - misc_deregister(&misc); - on_each_cpu(reset_prefetch, old_cfg, 1); - free_percpu(old_cfg); - free_percpu(cur_cfg); - free_cpumask_var(prefetch_cpumask_value); -} - -module_init(prefetch_init); -module_exit(prefetch_exit); -MODULE_LICENSE("GPL"); \ No newline at end of file +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "prefetch_mod.h" + +#ifndef is_affinity_mask_valid +#define is_affinity_mask_valid(val) 1 +#endif + +static cpumask_var_t prefetch_cpumask_value; +static cfg_t __percpu *cur_cfg; +static cfg_t __percpu *old_cfg; +static int old_cfg_int[FUNC_NUM] = {0}; +static DEFINE_MUTEX(prefetch_mtx); + +static ssize_t read_unique_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count); +static ssize_t read_unique_show(struct device* dev, + struct device_attribute* attr, char* buf); +static ssize_t prefetch_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count); +static ssize_t prefetch_show(struct device* dev, + struct device_attribute* attr, char* buf); +static ssize_t prefetch_mask_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count); +static ssize_t prefetch_mask_show(struct device* dev, + struct device_attribute* attr, char* buf); +static ssize_t val_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count); +static ssize_t val_show(struct device* dev, + struct device_attribute* attr, char* buf); + +/* Device create */ +static DEVICE_ATTR(read_unique, S_IRUGO|S_IWUSR, + read_unique_show, read_unique_store); + +static DEVICE_ATTR(policy, S_IRUGO|S_IWUSR, + prefetch_show, prefetch_store); + +static DEVICE_ATTR(cpumask, S_IRUGO|S_IWUSR, + prefetch_mask_show, prefetch_mask_store); + +static DEVICE_ATTR(iocapacity_limit, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(tag_rep_alg, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(ramswap, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(sqmerge, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(rdmerge, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_drop_hha, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prime_drop_mask, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(sequence_opt, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(bankintlv, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_utl_ddr, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_utl_ddr_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_utl_l3t, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_utl_l3t_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_start_level, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(totem_dual, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(canum_sktvec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt1_tb_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt1_ta_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt0_tb_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt0_ta_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt3_tb_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt3_ta_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt2_tb_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(skt2_ta_cavec, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(rdmerge_upgrade_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(ddr_compress_opt_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(snpsleep_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetchtgt_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(bankintl_stagger, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(cpu_pf_lqos_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(refillsize_com_ada_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(refillsize_pre_ada_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_overide_level, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_vague_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_core_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_match_en, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(reg_ctrl_prefetch_drop, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(reg_ctrl_dmcassign, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(reg_ctrl_rdatabyp, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(reg_dir_replace_alg, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(prefetch_comb, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(reg_funcdis_comb, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(ddr_intlv_skt, S_IRUGO|S_IWUSR, + val_show, val_store); + +static DEVICE_ATTR(ddr_intlv_die, S_IRUGO|S_IWUSR, + val_show, val_store); + +static struct attribute *prefetch_attrs[] = { + &dev_attr_policy.attr, + &dev_attr_cpumask.attr, + &dev_attr_read_unique.attr, + &dev_attr_iocapacity_limit.attr, + &dev_attr_tag_rep_alg.attr, + &dev_attr_ramswap.attr, + &dev_attr_sqmerge.attr, + &dev_attr_rdmerge.attr, + &dev_attr_prefetch_drop_hha.attr, + &dev_attr_prime_drop_mask.attr, + &dev_attr_sequence_opt.attr, + &dev_attr_bankintlv.attr, + &dev_attr_prefetch_utl_ddr.attr, + &dev_attr_prefetch_utl_ddr_en.attr, + &dev_attr_prefetch_utl_l3t.attr, + &dev_attr_prefetch_utl_l3t_en.attr, + &dev_attr_prefetch_start_level.attr, + &dev_attr_totem_dual.attr, + &dev_attr_canum_sktvec.attr, + &dev_attr_skt1_tb_cavec.attr, + &dev_attr_skt1_ta_cavec.attr, + &dev_attr_skt0_tb_cavec.attr, + &dev_attr_skt0_ta_cavec.attr, + &dev_attr_skt3_tb_cavec.attr, + &dev_attr_skt3_ta_cavec.attr, + &dev_attr_skt2_tb_cavec.attr, + &dev_attr_skt2_ta_cavec.attr, + &dev_attr_rdmerge_upgrade_en.attr, + &dev_attr_ddr_compress_opt_en.attr, + &dev_attr_snpsleep_en.attr, + &dev_attr_prefetchtgt_en.attr, + &dev_attr_bankintl_stagger.attr, + &dev_attr_cpu_pf_lqos_en.attr, + &dev_attr_refillsize_com_ada_en.attr, + &dev_attr_refillsize_pre_ada_en.attr, + &dev_attr_prefetch_overide_level.attr, + &dev_attr_prefetch_vague_en.attr, + &dev_attr_prefetch_core_en.attr, + &dev_attr_prefetch_match_en.attr, + &dev_attr_reg_ctrl_prefetch_drop.attr, + &dev_attr_reg_ctrl_dmcassign.attr, + &dev_attr_reg_ctrl_rdatabyp.attr, + &dev_attr_reg_dir_replace_alg.attr, + &dev_attr_prefetch_comb.attr, + &dev_attr_reg_funcdis_comb.attr, + &dev_attr_ddr_intlv_skt.attr, + &dev_attr_ddr_intlv_die.attr, + NULL, +}; + +static const struct attribute_group prefetch_attr_group = { + .attrs = prefetch_attrs, +}; + +static const struct attribute_group *attr_groups[] = { + &prefetch_attr_group, + NULL, +}; + +static struct miscdevice misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "prefetch", + .groups = attr_groups, +}; + +/* 0--close, 1--open */ +static ssize_t read_unique_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count) +{ + ssize_t ret = -1; + int value = -1; + + ret = kstrtouint(buf, 0, &value); + if (ret || (value != 0 && value != 1)) { + pr_err("invalid input!\n"); + return count; + } + + mutex_lock(&prefetch_mtx); + on_each_cpu_mask(prefetch_cpumask_value, read_unique_set, &value, 1); + mutex_unlock(&prefetch_mtx); + + return count; +} + +static ssize_t read_unique_show(struct device* dev, + struct device_attribute* attr, char* buf) +{ + int cpu = -1; + int count = 0; + + int __percpu *cur = alloc_percpu(int); + if (!cur) { + pr_err("alloc_percpu fail\n"); + return -ENOMEM; + } + mutex_lock(&prefetch_mtx); + on_each_cpu_mask(prefetch_cpumask_value, read_unique_get, cur, 1); + + for_each_cpu(cpu, prefetch_cpumask_value) { + int *ptr = per_cpu_ptr(cur, cpu); + count += scnprintf(buf + count, PAGE_SIZE, "cpu(%d): %d.\n", + cpu, (ptr == NULL) ? -1 : *ptr); + } + mutex_unlock(&prefetch_mtx); + free_percpu(cur); + return count; +} + +static ssize_t prefetch_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count) +{ + ssize_t ret = -1; + int policy = -1; + + ret = kstrtouint(buf, 0, &policy); + if (ret) { + pr_err("invalid input\n"); + return count; + } + + mutex_lock(&prefetch_mtx); + if (policy < prefetch_policy_num()) { + on_each_cpu_mask(prefetch_cpumask_value, set_prefetch, prefetch_policy(policy), 1); + } else { + pr_err("policy %d is out of range\n", policy); + } + mutex_unlock(&prefetch_mtx); + + return count; +} + +static ssize_t prefetch_show(struct device* dev, + struct device_attribute* attr, char* buf) +{ + int cpu = -1; + int policy = -1; + int count = 0; + + mutex_lock(&prefetch_mtx); + on_each_cpu_mask(prefetch_cpumask_value, get_prefetch, cur_cfg, 1); + for_each_cpu(cpu, prefetch_cpumask_value) { + cfg_t *this_cfg = per_cpu_ptr(cur_cfg, cpu); + for (policy = prefetch_policy_num() - 1; policy >= 0; policy--) { + if (!memcmp(prefetch_policy(policy), this_cfg, sizeof(cfg_t))) + break; + } + count += scnprintf(buf + count, PAGE_SIZE, "cpu(%d): %d\n", cpu, policy); + } + mutex_unlock(&prefetch_mtx); + + return count; +} + +static ssize_t prefetch_mask_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count) +{ + int ret = -1; + + mutex_lock(&prefetch_mtx); + ret = cpulist_parse(buf, prefetch_cpumask_value); + if (ret) { + pr_err("cpulist_parse error: %d\n", ret); + goto prefetch_mask_end; + } + + if (!is_affinity_mask_valid(prefetch_cpumask_value)) { + pr_err("mask value error\n"); + goto prefetch_mask_end; + } + +prefetch_mask_end: + mutex_unlock(&prefetch_mtx); + return count; +} + +static ssize_t prefetch_mask_show(struct device* dev, + struct device_attribute* attr, char* buf) +{ + ssize_t ret = -1; + mutex_lock(&prefetch_mtx); + ret = cpumap_print_to_pagebuf(true, buf, prefetch_cpumask_value); + mutex_unlock(&prefetch_mtx); + return ret; +} + +static ssize_t show_all(struct device* dev, struct device_attribute* attr, char* buf, FuncStruct* temp) +{ + int reg = 1, count = 0; + unsigned int die_idx = 0, skt_idx = 0, die_nr = 2; + unsigned long skt_offset = 0x200000000000ULL; + unsigned nr_skt = 2, totem_num = 1; + nr_skt = get_nr_skt(); + totem_num = get_totem_num(); + skt_offset = get_skt_offset(); + for (skt_idx = 0; skt_idx < nr_skt; skt_idx++) { + for (die_idx = 0; die_idx < die_nr + 1; die_idx++) { + unsigned long base_remap = 0; + unsigned long base = skt_idx * skt_offset; + unsigned val = 0; + if ((totem_num == 1) && (die_idx == 1)) + continue; + + if (die_idx == 1) + base += TOTEM_OFFSET; + + if (die_idx < die_nr) + base_remap = (unsigned long)ioremap(base + (*temp).Base, REG_RANGE); + else if ((*temp).Base == TB_AA_BASE) // To get the NIBUS configuration + base_remap = (unsigned long)ioremap(base + NI_AA_BASE, REG_RANGE); + else + continue; + + if (!base_remap) + return count; + + (*temp).Address = base_remap + (*temp).Offset; + val = get_val(*temp); + count += scnprintf(buf + count, PAGE_SIZE, "register(%d): %d.\n", + reg++, val); + iounmap((volatile void*)base_remap); + } + } + return count; +} + +static ssize_t val_store(struct device* dev, + struct device_attribute* attr, const char* buf, size_t count) +{ + int ret = -1, val = -1; + FuncStruct *temp = NULL; + + temp = get_func(attr); + if (temp == NULL) { + return count; + } + + ret = kstrtouint(buf, 0, &val); + if (ret || val < (*temp).Glb || val > (*temp).Sup) { + pr_err("invalid input!\n"); + return count; + } + + (*temp).Val = val; + mutex_lock((*temp).temp_mtx); + set_val(*temp); + mutex_unlock((*temp).temp_mtx); + return count; +} + +static ssize_t val_show(struct device* dev, + struct device_attribute* attr, char* buf) +{ + int count = 0; + FuncStruct *temp = NULL; + + temp = get_func(attr); + if (temp == NULL) { + return count; + } + + mutex_lock((*temp).temp_mtx); + count = show_all(dev, attr, buf, temp); + mutex_unlock((*temp).temp_mtx); + return count; +} + +/* + * prefetch policy, can be 0~15: + * 0: disable; 1~15: different thresholds for sms,amop algrithom; + */ +static int __init prefetch_init(void) +{ +#ifdef CONFIG_ARCH_HISI + int ret = -1; + int cpu = -1; + /* get cpu infomation to identify L3T_DYNAMIC_CTRL registers */ + ret = initial_cpu_info(); + if (ret < 0) { + pr_err("get cpu information fail\n"); + goto err_init; + } + + /* get the and store default configurations */ + ret = get_default_cfg(old_cfg_int); + if (ret < 0) { + pr_err("get default cfg fail\n"); + goto err_init; + } + + /* mask: initial a mask */ + if (!alloc_cpumask_var(&prefetch_cpumask_value, GFP_KERNEL)) { + ret = -ENOMEM; + goto err_mask_alloc; + } + + cpumask_clear(prefetch_cpumask_value); + for_each_online_cpu(cpu) + cpumask_set_cpu(cpu, prefetch_cpumask_value); + + if (!is_affinity_mask_valid(prefetch_cpumask_value)) { + pr_err("incalid affinity_mask\n"); + ret = -EINVAL; + goto err_mask_init; + } + + cur_cfg = alloc_percpu(cfg_t); + if (!cur_cfg) { + pr_err("alloc_percpu fail\n"); + ret = -ENOMEM; + goto err_mask_init; + } + + old_cfg = alloc_percpu(cfg_t); + if (!old_cfg) { + pr_err("alloc_percpu fail\n"); + ret = -ENOMEM; + goto err_cfg_alloc; + } + + on_each_cpu(get_prefetch, old_cfg, 1); + + /* initial prefetch misc and initial prefetch_ops */ + ret = misc_register(&misc); + if (ret < 0) { + pr_err("misc register fail\n"); + goto err_misc_reg; + } + + return 0; + +err_misc_reg: + free_percpu(old_cfg); +err_cfg_alloc: + free_percpu(cur_cfg); +err_mask_init: + free_cpumask_var(prefetch_cpumask_value); +err_mask_alloc: + return ret; +err_init: + return ret; + +#else + return 0; +#endif +} + +static void __exit prefetch_exit(void) +{ +#ifdef CONFIG_ARCH_HISI + misc_deregister(&misc); + on_each_cpu(reset_prefetch, old_cfg, 1); + free_percpu(old_cfg); + free_percpu(cur_cfg); + free_cpumask_var(prefetch_cpumask_value); + reset_default_cfg(old_cfg_int); +#endif +} + +module_init(prefetch_init); +module_exit(prefetch_exit); +MODULE_LICENSE("GPL"); diff --git a/prefetch_mod.h b/prefetch_mod.h index bae47dc..a6cbe6d 100644 --- a/prefetch_mod.h +++ b/prefetch_mod.h @@ -12,6 +12,7 @@ * for more details. * Create: 2020-07-02 * Author: Liqiang (liqiang9102@gitee) + * Liuke20 (liuke20@gitee) */ #ifndef __PREFETCH_TUNING__ #define __PREFETCH_TUNING__ @@ -21,13 +22,215 @@ enum { ENABLE }; +enum FunctionOrderList { + IOCAPACITY_LIMIT_ORDER = 0, + TAG_REP_ALG_ORDER, + SQMERGE_ORDER, + RDMERGE_ORDER, + PREFETCH_DROP_HHA_ORDER, + RAMSWAP_ORDER, + PRIME_DROP_MASK_ORDER, + SEQUENCE_OPT_ORDER, + BANKINTLV_ORDER, + PREFETCH_ULT_DDR_ORDER, + PREFETCH_ULT_DDR_EN_ORDER, + PREFETCH_ULT_L3T_ORDER, + PREFETCH_UTL_L3T_EN_ORDER, + PREFETCH_START_LEVEL_ORDER, + REG_TOTEM_DUAL_ORDER, + REG_CANUM_SKTVEC_ORDER, + REG_SKT1_TB_CAVEC_ORDER, + REG_SKT1_TA_CAVEC_ORDER, + REG_SKT0_TB_CAVEC_ORDER, + REG_SKT0_TA_CAVEC_ORDER, + REG_SKT3_TB_CAVEC_ORDER, + REG_SKT3_TA_CAVEC_ORDER, + REG_SKT2_TB_CAVEC_ORDER, + REG_SKT2_TA_CAVEC_ORDER, + RDMERGE_UPGRADE_EN_ORDER, + DDR_COMPRESS_OPT_EN_ORDER, + SNPSLEEP_EN_ORDER, + PREFETCHTGT_EN_ORDER, + BANKINTL_STAGGER_ORDER, + CPU_PF_LQOS_EN_ORDER, + REFILLSIZE_COM_ADA_EN_ORDER, + REFILLSIZE_PRE_ADA_EN_ORDER, + PREFETCH_OVERIDE_LEVEL_ORDER, + PREFETCH_VAGUE_EN_ORDER, + PREFETCH_CORE_EN_ORDER, + PREFETCH_MATCH_EN_ORDER, + REG_CTRL_PREFETCH_DROP_ORDER, + REG_CTRL_DMCASSIGN_ORDER, + REG_CTRL_RDATABYP_ORDER, + REG_DIR_REPLACE_ALG_ORDER, + PREFETCH_COMB_ORDER, + REG_FUNCDIS_COMB_ORDER, + DDR_INTLV_SKT_ORDER, + DDR_INTLV_DIE_ORDER, + FUNC_NUM +}; + +enum RegOffsetList { + L3T_DYNAMIC_CTRL = 0x400, + L3T_STATIC_CTRL = 0x000, + L3T_DYNAMIC_AUCTRL0 = 0x404, + L3T_DYNAMIC_AUCTRL1 = 0x40c, + L3T_PREFETCH = 0x410, + HHA_TOTEMNUM = 0x020, + HHA_CANUM_L = 0x024, + HHA_CANUM_H = 0x028, + HHA_CTRL = 0x000, + HHA_DIR_CTRL = 0x00c, + HHA_FUNC_DIS = 0x010, + AA_MSD1_CTRL = 0x384 +}; + +enum ComMsd1Ctrl { + DDR_INTLV_SKT_START = 29, + DDR_INTLV_SKT_END = 30, + DDR_INTLV_DIE_START = 27, + DDR_INTLV_DIE_END = 27, +}; + +enum HhaFuncDisReg { + PREFETCH_COMB_START = 21, + PREFETCH_COMB_END = 21, + PREFETCH_FUNCDIS_COMB_START = 2, + PREFETCH_FUNCDIS_COMB_END = 2 +}; + +enum HhaDirCtrlReg { + REG_DIR_REPLACE_ALG_START = 0, + REG_DIR_REPLACE_ALG_END = 1 +}; + +enum HhaCtrlReg { + REG_CTRL_PREFETCH_DROP_START = 6, + REG_CTRL_PREFETCH_DROP_END = 6, + REG_CTRL_DMCASSIGN_START = 5, + REG_CTRL_DMCASSIGN_END = 5, + REG_CTRL_RDATABYP_START = 4, + REG_CTRL_RDATABYP_END = 4 +}; + +enum L3tStaticCtrlReg { + RAMSWAP_START = 16, + RAMSWAP_END = 16 +}; + +enum L3tDynamicAuctrl0Reg { + DDR_COMPRESS_OPT_EN_START = 7, + DDR_COMPRESS_OPT_EN_END = 7, + SNPSLEEP_EN_START = 1, + SNPSLEEP_EN_END = 1, + PREFETCHTGT_EN_START = 0, + PREFETCHTGT_EN_END = 0 +}; + +enum L3tDynamicCtrlReg { + TAG_REP_ALG_START = 0, + TAG_REP_ALG_END = 1, + PREFETCH_DROP_HHA_START = 4, + PREFETCH_DROP_HHA_END = 4, + RDMERGE_UPGRADE_EN_START = 8, + RDMERGE_UPGRADE_EN_END = 8, + RDMERGE_START = 9, + RDMERGE_END = 9, + SQMERGE_START = 10, + SQMERGE_END = 10, + IOCAPACITY_LIMIT_START = 13, + IOCAPACITY_LIMIT_END = 13 +}; + +enum L3tDynamicAuctrl1Reg { + BANKINTLV_START = 0, + BANKINTLV_END = 0, + SEQUENCE_OPT_START = 1, + SEQUENCE_OPT_END = 1, + REFILLSIZE_PRE_ADA_EN_START = 2, + REFILLSIZE_PRE_ADA_EN_END = 2, + REFILLSIZE_COM_ADA_EN_START = 3, + REFILLSIZE_COM_ADA_EN_END = 3, + PRIME_DROP_MASK_START = 5, + PRIME_DROP_MASK_END = 5, + CPU_PF_LQOS_EN_START = 11, + CPU_PF_LQOS_EN_END = 11, + BANKINTL_STAGGER_START = 19, + BANKINTL_STAGGER_END = 19 +}; + +enum L3tPrefetchReg { + PREFETCH_START_LEVEL_START = 0, + PREFETCH_START_LEVEL_END = 4, + PREFETCH_MATCH_EN_START = 7, + PREFETCH_MATCH_EN_END = 7, + PREFETCH_CORE_EN_START = 8, + PREFETCH_CORE_EN_END = 11, + PREFETCH_VAGUE_EN_START = 12, + PREFETCH_VAGUE_EN_END = 12, + PREFETCH_UTL_L3T_EN_START = 13, + PREFETCH_UTL_L3T_EN_END = 13, + PREFETCH_ULT_L3T_START = 14, + PREFETCH_ULT_L3T_END = 15, + PREFETCH_ULT_DDR_EN_START = 16, + PREFETCH_ULT_DDR_EN_END = 16, + PREFETCH_ULT_DDR_START = 17, + PREFETCH_ULT_DDR_END = 18, + PREFETCH_OVERIDE_LEVEL_START = 20, + PREFETCH_OVERIDE_LEVEL_END = 23 +}; + +enum HhaTotemnumReg { + REG_CANUM_SKTVEC_START = 0, + REG_CANUM_SKTVEC_END = 3, + REG_TOTEM_DUAL_START = 4, + REG_TOTEM_DUAL_END = 4 +}; + +enum HhaCanumLReg { + REG_SKT0_TA_CAVEC_START = 0, + REG_SKT0_TA_CAVEC_END = 7, + REG_SKT0_TB_CAVEC_START = 8, + REG_SKT0_TB_CAVEC_END = 15, + REG_SKT1_TA_CAVEC_START = 16, + REG_SKT1_TA_CAVEC_END = 23, + REG_SKT1_TB_CAVEC_START = 24, + REG_SKT1_TB_CAVEC_END = 31 +}; + +enum HhaCanumHReg { + REG_SKT2_TA_CAVEC_START = 0, + REG_SKT2_TA_CAVEC_END = 7, + REG_SKT2_TB_CAVEC_START = 8, + REG_SKT2_TB_CAVEC_END = 15, + REG_SKT3_TA_CAVEC_START = 16, + REG_SKT3_TA_CAVEC_END = 23, + REG_SKT3_TB_CAVEC_START = 24, + REG_SKT3_TB_CAVEC_END = 31 +}; + #define CACHE_READUNIQ_CTRL (1L << 40) #define TB_L3T0_BASE 0x90180000 -#define L3T_DYNAMIC_CTRL 0x400 #define TOTEM_OFFSET 0x8000000 -#define REG_RANGE 0x5000 -#define writel_reg(val, addr) (*(volatile unsigned int *)(addr) = (val)) -#define readl_reg(addr) (*(volatile unsigned int*)(addr)) +#define TB_AA_BASE 0x90300000 +#define TB_HHA0_BASE 0x90120000 +#define NI_AA_BASE 0x200140000ULL +#define REG_RANGE 0x5000 +#define MAX_STR 32 + + +typedef struct { + unsigned long Base; + unsigned long Offset; + unsigned long Address; + int Val; + int StartBit; + int EndBit; + int Glb; + int Sup; + char Name[MAX_STR]; + struct mutex* temp_mtx; +} FuncStruct; #ifdef CONFIG_ARCH_HISI typedef struct { @@ -36,6 +239,7 @@ typedef struct { long adpp_l1v_mop_el1; long adps_lld_l3_el1; } cfg_t; + #else typedef long cfg_t; #endif @@ -45,14 +249,17 @@ extern void get_prefetch(void* dummy); extern void read_unique_set(void *dummy); extern void read_unique_get(void *dummy); extern void reset_prefetch(void* dummy); -extern void initial_cpu_info(void); -extern int iocapacity_limit_get(void *dummy); -extern void iocapacity_limit_set(void *dummy); -unsigned get_totem_num(void); -unsigned get_nr_skt(void); +extern int initial_cpu_info(void); +extern void set_val(FuncStruct Str); +extern int get_val(FuncStruct Str); +extern int get_default_cfg(int* arr); +extern FuncStruct *get_func(struct device_attribute* attr); -unsigned long get_skt_offset(void); +extern unsigned get_totem_num(void); +extern unsigned get_nr_skt(void); +extern unsigned long get_skt_offset(void); extern int prefetch_policy_num(void); extern cfg_t *prefetch_policy(int policy); +extern void reset_default_cfg(int *old_cfg_int); #endif diff --git a/prefetch_reg.c b/prefetch_reg.c index 06b42a2..33f15ab 100644 --- a/prefetch_reg.c +++ b/prefetch_reg.c @@ -12,6 +12,7 @@ * for more details. * Create: 2020-07-02 * Author: Liqiang (liqiang9102@gitee) + * Liuke (liuke20@gitee) */ #include @@ -26,76 +27,563 @@ #include #include "prefetch_mod.h" +static DEFINE_MUTEX(l3t_dctrl_mtx); +static DEFINE_MUTEX(l3t_dauctrl_mtx); +static DEFINE_MUTEX(l3t_dauctr0_mtx); +static DEFINE_MUTEX(l3t_prefetch_mtx); +static DEFINE_MUTEX(hha_totemnum_mtx); +static DEFINE_MUTEX(hha_canuml_mtx); +static DEFINE_MUTEX(hha_canumh_mtx); +static DEFINE_MUTEX(l3t_sctrl_mtx); +static DEFINE_MUTEX(hha_ctrl_mtx); +static DEFINE_MUTEX(hha_dirctrl_mtx); +static DEFINE_MUTEX(hha_funcdis_mtx); +static DEFINE_MUTEX(com_msd1ctrl_mtx); + unsigned int read_reg(void *addr, int bitstart, int bitend); void write_reg(void *addr, unsigned setval, unsigned bitstart, unsigned bitend); - -#ifdef CONFIG_ARCH_HISI #define PREFETCH_POLICY_MAX 15 + static cfg_t prefetch_cfg[] = { - [0] = {.cpuprefctrl_el1 = 0x112f8127f, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [1] = {.cpuprefctrl_el1 = 0x112f81254, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [2] = {.cpuprefctrl_el1 = 0x112f81254, - .adps_lld_ddr_el1 = 0x4d34a200, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [3] = {.cpuprefctrl_el1 = 0xb52f81254, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [4] = {.cpuprefctrl_el1 = 0x112f81254, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x65965700}, - [5] = {.cpuprefctrl_el1 = 0x3012f81254, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x65965700}, - [6] = {.cpuprefctrl_el1 = 0x3012f81254, - .adps_lld_ddr_el1 = 0x4d142000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x65965700}, - [7] = {.cpuprefctrl_el1 = 0x3012f81254, - .adps_lld_ddr_el1 = 0x4d142000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x4d145100}, - [8] = {.cpuprefctrl_el1 = 0x4112f81254, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [9] = {.cpuprefctrl_el1 = 0x112f81260, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [10] = {.cpuprefctrl_el1 = 0x112f81260, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x658e5700}, - [11] = {.cpuprefctrl_el1 = 0x3412f81254, - .adps_lld_ddr_el1 = 0x4d142000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x65965700}, - [12] = {.cpuprefctrl_el1 = 0x3412F81260, - .adps_lld_ddr_el1 = 0x4d12000, - .adpp_l1v_mop_el1 = 0x29080082a880, - .adps_lld_l3_el1 = 0x65965700}, - [13] = {.cpuprefctrl_el1 = 0x112f81240, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [14] = {.cpuprefctrl_el1 = 0x112f81240, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x69154332a840, - .adps_lld_l3_el1 = 0x65965700}, - [15] = {.cpuprefctrl_el1 = 0x80110f81380, - .adps_lld_ddr_el1 = 0x6554a000, - .adpp_l1v_mop_el1 = 0x29154332a840, - .adps_lld_l3_el1 = 0x65965700}, + [0] = { + .cpuprefctrl_el1 = 0x112f8127f, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [1] = { + .cpuprefctrl_el1 = 0x112f81254, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [2] = { + .cpuprefctrl_el1 = 0x112f81254, + .adps_lld_ddr_el1 = 0x4d34a200, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [3] = { + .cpuprefctrl_el1 = 0xb52f81254, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [4] = { + .cpuprefctrl_el1 = 0x112f81254, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x65965700 + }, + [5] = { + .cpuprefctrl_el1 = 0x3012f81254, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x65965700 + }, + [6] = { + .cpuprefctrl_el1 = 0x3012f81254, + .adps_lld_ddr_el1 = 0x4d142000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x65965700 + }, + [7] = { + .cpuprefctrl_el1 = 0x3012f81254, + .adps_lld_ddr_el1 = 0x4d142000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x4d145100 + }, + [8] = { + .cpuprefctrl_el1 = 0x4112f81254, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [9] = { + .cpuprefctrl_el1 = 0x112f81260, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [10] = { + .cpuprefctrl_el1 = 0x112f81260, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x658e5700 + }, + [11] = { + .cpuprefctrl_el1 = 0x3412f81254, + .adps_lld_ddr_el1 = 0x4d142000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x65965700 + }, + [12] = { + .cpuprefctrl_el1 = 0x3412F81260, + .adps_lld_ddr_el1 = 0x4d12000, + .adpp_l1v_mop_el1 = 0x29080082a880, + .adps_lld_l3_el1 = 0x65965700 + }, + [13] = { + .cpuprefctrl_el1 = 0x112f81240, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [14] = { + .cpuprefctrl_el1 = 0x112f81240, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x69154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, + [15] = { + .cpuprefctrl_el1 = 0x80110f81380, + .adps_lld_ddr_el1 = 0x6554a000, + .adpp_l1v_mop_el1 = 0x29154332a840, + .adps_lld_l3_el1 = 0x65965700 + }, +}; + +static FuncStruct Funcs[] = { + [IOCAPACITY_LIMIT_ORDER] = { + .StartBit = IOCAPACITY_LIMIT_START, + .EndBit = IOCAPACITY_LIMIT_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "iocapacity_limit" + }, + [TAG_REP_ALG_ORDER] = { + .StartBit = TAG_REP_ALG_START, + .EndBit = TAG_REP_ALG_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 3, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "tag_rep_alg" + }, + [SQMERGE_ORDER] = { + .StartBit = SQMERGE_START, + .EndBit = SQMERGE_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "sqmerge" + }, + [RDMERGE_ORDER] = { + .StartBit = RDMERGE_START, + .EndBit = RDMERGE_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "rdmerge" + }, + [PREFETCH_DROP_HHA_ORDER] = { + .StartBit = PREFETCH_DROP_HHA_START, + .EndBit = PREFETCH_DROP_HHA_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "prefetch_drop_hha" + }, + [RAMSWAP_ORDER] = { + .StartBit = RAMSWAP_START, + .EndBit = RAMSWAP_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_STATIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_sctrl_mtx, + .Name = "ramswap" + }, + [PRIME_DROP_MASK_ORDER] = { + .StartBit = PRIME_DROP_MASK_START, + .EndBit = PRIME_DROP_MASK_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "prime_drop_mask" + }, + [SEQUENCE_OPT_ORDER] = { + .StartBit = SEQUENCE_OPT_START, + .EndBit = SEQUENCE_OPT_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "sequence_opt" + }, + [BANKINTLV_ORDER] = { + .StartBit = BANKINTLV_START, + .EndBit = BANKINTLV_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "bankintlv" + }, + [PREFETCH_ULT_DDR_ORDER] = { + .StartBit = PREFETCH_ULT_DDR_START, + .EndBit = PREFETCH_ULT_DDR_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 3, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_utl_ddr" + }, + [PREFETCH_ULT_DDR_EN_ORDER] = { + .StartBit = PREFETCH_ULT_DDR_EN_START, + .EndBit = PREFETCH_ULT_DDR_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_utl_ddr_en" + }, + [PREFETCH_ULT_L3T_ORDER] = { + .StartBit = PREFETCH_ULT_L3T_START, + .EndBit = PREFETCH_ULT_L3T_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 3, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_utl_l3t" + }, + [PREFETCH_UTL_L3T_EN_ORDER] = { + .StartBit = PREFETCH_UTL_L3T_EN_START, + .EndBit = PREFETCH_UTL_L3T_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_utl_l3t_en" + }, + [PREFETCH_START_LEVEL_ORDER] = { + .StartBit = PREFETCH_START_LEVEL_START, + .EndBit = PREFETCH_START_LEVEL_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 31, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_start_level" + }, + [REG_TOTEM_DUAL_ORDER] = { + .StartBit = REG_TOTEM_DUAL_START, + .EndBit = REG_TOTEM_DUAL_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_TOTEMNUM, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_totemnum_mtx, + .Name = "totem_dual" + }, + [REG_CANUM_SKTVEC_ORDER] = { + .StartBit = REG_CANUM_SKTVEC_START, + .EndBit = REG_CANUM_SKTVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_TOTEMNUM, + .Sup = 15, + .Glb = 0, + .temp_mtx = &hha_totemnum_mtx, + .Name = "canum_sktvec" + }, + [REG_SKT1_TB_CAVEC_ORDER] = { + .StartBit = REG_SKT1_TB_CAVEC_START, + .EndBit = REG_SKT1_TB_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_L, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canuml_mtx, + .Name = "skt1_tb_cavec" + }, + [REG_SKT1_TA_CAVEC_ORDER] = { + .StartBit = REG_SKT1_TA_CAVEC_START, + .EndBit = REG_SKT1_TA_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_L, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canuml_mtx, + .Name = "skt1_ta_cavec" + }, + [REG_SKT0_TB_CAVEC_ORDER] = { + .StartBit = REG_SKT0_TB_CAVEC_START, + .EndBit = REG_SKT0_TB_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_L, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canuml_mtx, + .Name = "skt0_tb_cavec" + }, + [REG_SKT0_TA_CAVEC_ORDER] = { + .StartBit = REG_SKT0_TA_CAVEC_START, + .EndBit = REG_SKT0_TA_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_L, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canuml_mtx, + .Name = "skt0_ta_cavec" + }, + [REG_SKT3_TB_CAVEC_ORDER] = { + .StartBit = REG_SKT3_TB_CAVEC_START, + .EndBit = REG_SKT3_TB_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_H, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canumh_mtx, + .Name = "skt3_tb_cavec" + }, + [REG_SKT3_TA_CAVEC_ORDER] = { + .StartBit = REG_SKT3_TA_CAVEC_START, + .EndBit = REG_SKT3_TA_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_H, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canumh_mtx, + .Name = "skt3_ta_cavec" + }, + [REG_SKT2_TB_CAVEC_ORDER] = { + .StartBit = REG_SKT2_TB_CAVEC_START, + .EndBit = REG_SKT2_TB_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_H, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canumh_mtx, + .Name = "skt2_tb_cavec" + }, + [REG_SKT3_TA_CAVEC_END] = { + .StartBit = REG_SKT2_TA_CAVEC_START, + .EndBit = REG_SKT2_TA_CAVEC_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CANUM_H, + .Sup = 255, + .Glb = 0, + .temp_mtx = &hha_canumh_mtx, + .Name = "skt2_ta_cavec" + }, + [RDMERGE_UPGRADE_EN_ORDER] = { + .StartBit = RDMERGE_UPGRADE_EN_START, + .EndBit = RDMERGE_UPGRADE_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dctrl_mtx, + .Name = "rdmerge_upgrade_en" + }, + [DDR_COMPRESS_OPT_EN_ORDER] = { + .StartBit = PRIME_DROP_MASK_START, + .EndBit = PRIME_DROP_MASK_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL0, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctr0_mtx, + .Name = "ddr_compress_opt_en" + }, + [SNPSLEEP_EN_ORDER] = { + .StartBit = SNPSLEEP_EN_START, + .EndBit = SNPSLEEP_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL0, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctr0_mtx, + .Name = "snpsleep_en" + }, + [PREFETCHTGT_EN_ORDER] = { + .StartBit = PREFETCHTGT_EN_START, + .EndBit = PREFETCHTGT_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL0, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctr0_mtx, + .Name = "prefetchtgt_en" + }, + [BANKINTL_STAGGER_ORDER] = { + .StartBit = BANKINTL_STAGGER_START, + .EndBit = BANKINTL_STAGGER_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "bankintl_stagger" + }, + [CPU_PF_LQOS_EN_ORDER] = { + .StartBit = CPU_PF_LQOS_EN_START, + .EndBit = CPU_PF_LQOS_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "cpu_pf_lqos_en" + }, + [REFILLSIZE_COM_ADA_EN_ORDER] = { + .StartBit = REFILLSIZE_COM_ADA_EN_START, + .EndBit = REFILLSIZE_COM_ADA_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "refillsize_com_ada_en" + }, + [REFILLSIZE_PRE_ADA_EN_ORDER] = { + .StartBit = REFILLSIZE_PRE_ADA_EN_START, + .EndBit = REFILLSIZE_PRE_ADA_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_DYNAMIC_AUCTRL1, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_dauctrl_mtx, + .Name = "refillsize_pre_ada_en" + }, + [PREFETCH_OVERIDE_LEVEL_ORDER] = { + .StartBit = PREFETCH_OVERIDE_LEVEL_START, + .EndBit = PREFETCH_OVERIDE_LEVEL_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 15, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_overide_level" + }, + [PREFETCH_VAGUE_EN_ORDER] = { + .StartBit = PREFETCH_VAGUE_EN_START, + .EndBit = PREFETCH_VAGUE_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_vague_en" + }, + [PREFETCH_CORE_EN_ORDER] = { + .StartBit = PREFETCH_CORE_EN_START, + .EndBit = PREFETCH_CORE_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 15, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_core_en" + }, + [PREFETCH_MATCH_EN_ORDER] = { + .StartBit = PREFETCH_MATCH_EN_START, + .EndBit = PREFETCH_MATCH_EN_END, + .Base = TB_L3T0_BASE, + .Offset = L3T_PREFETCH, + .Sup = 1, + .Glb = 0, + .temp_mtx = &l3t_prefetch_mtx, + .Name = "prefetch_match_en" + }, + [REG_CTRL_PREFETCH_DROP_ORDER] = { + .StartBit = REG_CTRL_PREFETCH_DROP_START, + .EndBit = REG_CTRL_PREFETCH_DROP_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_ctrl_mtx, + .Name = "reg_ctrl_prefetch_drop" + }, + [REG_CTRL_DMCASSIGN_ORDER] = { + .StartBit = REG_CTRL_DMCASSIGN_START, + .EndBit = REG_CTRL_DMCASSIGN_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_ctrl_mtx, + .Name = "reg_ctrl_dmcassign" + }, + [REG_CTRL_RDATABYP_ORDER] = { + .StartBit = REG_CTRL_RDATABYP_START, + .EndBit = REG_CTRL_RDATABYP_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_ctrl_mtx, + .Name = "reg_ctrl_rdatabyp" + }, + [REG_DIR_REPLACE_ALG_ORDER] = { + .StartBit = REG_DIR_REPLACE_ALG_START, + .EndBit = REG_DIR_REPLACE_ALG_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_DIR_CTRL, + .Sup = 3, + .Glb = 0, + .temp_mtx = &hha_dirctrl_mtx, + .Name = "reg_dir_replace_alg" + }, + [PREFETCH_COMB_ORDER] = { + .StartBit = PREFETCH_COMB_START, + .EndBit = PREFETCH_COMB_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_FUNC_DIS, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_funcdis_mtx, + .Name = "prefetch_comb" + }, + [REG_FUNCDIS_COMB_ORDER] = { + .StartBit = PREFETCH_FUNCDIS_COMB_START, + .EndBit = PREFETCH_FUNCDIS_COMB_END, + .Base = TB_HHA0_BASE, + .Offset = HHA_FUNC_DIS, + .Sup = 1, + .Glb = 0, + .temp_mtx = &hha_funcdis_mtx, + .Name = "reg_funcdis_comb" + }, + [DDR_INTLV_SKT_ORDER] = { + .StartBit = DDR_INTLV_SKT_START, + .EndBit = DDR_INTLV_SKT_END, + .Base = TB_AA_BASE, + .Offset = AA_MSD1_CTRL, + .Sup = 3, + .Glb = 0, + .temp_mtx = &com_msd1ctrl_mtx, + .Name = "ddr_intlv_skt" + }, + [DDR_INTLV_DIE_ORDER] = { + .StartBit = DDR_INTLV_DIE_START, + .EndBit = DDR_INTLV_DIE_END, + .Base = TB_AA_BASE, + .Offset = AA_MSD1_CTRL, + .Sup = 1, + .Glb = 0, + .temp_mtx = &com_msd1ctrl_mtx, + .Name = "ddr_intlv_die" + }, }; void set_prefetch(void* dummy) @@ -104,6 +592,7 @@ void set_prefetch(void* dummy) unsigned long read_uniq = read_sysreg(S3_1_c15_c6_4); if (cfg == NULL) return; + read_uniq &= CACHE_READUNIQ_CTRL; write_sysreg(cfg->cpuprefctrl_el1 | read_uniq, S3_1_c15_c6_4); write_sysreg(cfg->adps_lld_ddr_el1, S3_1_c15_c7_1); @@ -119,7 +608,7 @@ void get_prefetch(void* dummy) pcfg->adps_lld_ddr_el1 = read_sysreg(S3_1_c15_c7_1); pcfg->adpp_l1v_mop_el1 = read_sysreg(S3_1_c15_c6_5); pcfg->adps_lld_l3_el1 = read_sysreg(S3_1_c15_c7_0); - + /* Ignore READUNIQ bit */ pcfg->cpuprefctrl_el1 &= ~(CACHE_READUNIQ_CTRL); return; @@ -132,7 +621,7 @@ void read_unique_set(void *dummy) sysreg_clear_set(S3_1_c15_c6_4, 0, CACHE_READUNIQ_CTRL); else if (*value == DISABLE) sysreg_clear_set(S3_1_c15_c6_4, CACHE_READUNIQ_CTRL, 0); - + return; } @@ -146,18 +635,25 @@ void read_unique_get(void *dummy) } static unsigned long skt_offset = 0x200000000000ULL; -static unsigned nr_skt = 2, totem_num = 1; -void initial_cpu_info(void) +static unsigned nr_skt = 1, totem_num = 1; +int initial_cpu_info(void) { - u32 midr = read_cpuid_id(); - unsigned cvariant = 0x1, core_per_skt = 48; - int max_cpu = nr_cpu_ids; - cvariant = MIDR_VARIANT(midr); - if (cvariant == 0x1) - skt_offset = 0x200000000000ULL; - else - skt_offset = 0x400000000000ULL; - if (max_cpu == 24 || max_cpu == 32 || max_cpu == 8 || max_cpu == 12) { + u32 midr = read_cpuid_id(); + unsigned cvariant = 0x1, core_per_skt = 48; + int max_cpu = nr_cpu_ids; + u32 implementor = read_cpuid_implementor(); + if (implementor != 0x48) { + printk(KERN_ALERT "This is not HiSilicon CPU core;\n"); + return -ENOMEM; + } + + cvariant = MIDR_VARIANT(midr); + if (cvariant == 0x1) + skt_offset = 0x200000000000ULL; + else + skt_offset = 0x400000000000ULL; + + if (max_cpu == 24 || max_cpu == 32 || max_cpu == 8 || max_cpu == 12) { nr_skt = 1; totem_num = 1; } else { @@ -165,117 +661,88 @@ void initial_cpu_info(void) nr_skt = max_cpu / core_per_skt; totem_num = 2; } + return 1; } -/*To modify the L3 register. Traverse the socket and totem（skt_idx, die_idx）*/ -/* 0--unlimit 1--limit*/ -static const u32 iocapacityLimitOffset = 13; -int iocapacity_limit_get(void *dummy) +int get_val(FuncStruct Str) { - unsigned long *addr = (unsigned long *)dummy; - u32 reg_value = readl_reg(*addr); - int value = (reg_value >> iocapacityLimitOffset) & 0x1; - return value; + return read_reg((void *)(Str.Address), Str.StartBit, Str.EndBit); } -void iocapacity_limit_set(void *dummy) +void set_val(FuncStruct Str) { - int *value = (int *)dummy; - unsigned int die_idx = 0, skt_idx = 0; - for (skt_idx = 0; skt_idx < nr_skt; skt_idx++) { - for (die_idx = 0; die_idx < 2; die_idx++) { - unsigned long base = skt_idx * skt_offset, base2 = 0; - unsigned val = 0; - if ((totem_num == 1) && (die_idx == 1)) + unsigned int die_idx = 0, skt_idx = 0, die_nr = 2; + for (skt_idx = 0; skt_idx < nr_skt; skt_idx++) { + for (die_idx = 0; die_idx < die_nr + 1; die_idx++) { + unsigned long base = skt_idx * skt_offset, base_remap = 0; + if ((totem_num == 1) && (die_idx == 1)) continue; + if (die_idx == 1) base += TOTEM_OFFSET; - base2 = (unsigned long)ioremap(base + TB_L3T0_BASE, REG_RANGE); - if (!base2) - return; - val = readl_reg(base2 + L3T_DYNAMIC_CTRL); - if (*value == ENABLE) - val |= (1<> bitstart) & bitmask; @@ -323,7 +804,7 @@ inline unsigned int read_reg(void *addr, int bitstart, int bitend) * Attention: "setval" no need to shift, just pass native value, like set 0110B to 23:20 is "write_reg(addr, 0x6, 20, 23)" */ -inline void write_reg(void *addr, unsigned setval, unsigned bitstart, unsigned bitend) +inline void write_reg(void* addr, unsigned setval, unsigned bitstart, unsigned bitend) { unsigned int val = 0; int bitwide = 0; diff --git a/tests/HhaCanumH.sh b/tests/HhaCanumH.sh new file mode 100644 index 0000000..cbc0385 --- /dev/null +++ b/tests/HhaCanumH.sh @@ -0,0 +1,98 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-22 +# Author: Liuke (liuke20@gitee) + +echo "skt2_ta_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt2_ta_cavec + cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +done + +echo "skt2_tb_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt2_tb_cavec + cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +done + +echo "skt3_ta_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt3_ta_cavec + cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +done + +echo "skt3_tb_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt3_tb_cavec + cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) +done + +echo "set skt2_ta_cavec to 0: (exp 0, 255, 255, 255)" +echo 0 > /sys/class/misc/prefetch/skt2_ta_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt2_ta_cavec to 128: (exp 128, 255, 255, 255)" +echo 128 > /sys/class/misc/prefetch/skt2_ta_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt2_tb_cavec to 0: (exp 128, 0, 255, 255)" +echo 0 > /sys/class/misc/prefetch/skt2_tb_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt2_tb_cavec to 128: (exp 128, 128, 255, 255)" +echo 128 > /sys/class/misc/prefetch/skt2_tb_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt3_ta_cavec to 0: (exp 128, 128, 0, 255)" +echo 0 > /sys/class/misc/prefetch/skt3_ta_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt3_tb_cavec to 128: (exp 128, 128, 128, 255)" +echo 128 > /sys/class/misc/prefetch/skt3_ta_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt3_tb_cavec to 0: (exp 128, 128, 128, 0)" +echo 0 > /sys/class/misc/prefetch/skt3_tb_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) + +echo "set skt3_tb_cavec to 128: (exp 128, 128, 128, 128)" +echo 128 > /sys/class/misc/prefetch/skt3_tb_cavec +cat /sys/class/misc/prefetch/skt2_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt2_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt3_tb_cavec | grep register\(1\) \ No newline at end of file diff --git a/tests/HhaCanumL.sh b/tests/HhaCanumL.sh new file mode 100644 index 0000000..d5197fa --- /dev/null +++ b/tests/HhaCanumL.sh @@ -0,0 +1,98 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-22 +# Author: Liuke (liuke20@gitee) + +echo "skt0_ta_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt0_ta_cavec + cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +done + +echo "skt0_tb_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt0_tb_cavec + cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +done + +echo "skt1_ta_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt1_ta_cavec + cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +done + +echo "skt1_tb_cavec set test (exp 0~255) :" +for i in {0..255} +do + echo $i > /sys/class/misc/prefetch/skt1_tb_cavec + cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) +done + +echo "set skt0_ta_cavec to 0: (exp 0, 255, 255, 255)" +echo 0 > /sys/class/misc/prefetch/skt0_ta_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt0_ta_cavec to 128: (exp 128, 255, 255, 255)" +echo 128 > /sys/class/misc/prefetch/skt0_ta_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt0_tb_cavec to 0: (exp 128, 0, 255, 255)" +echo 0 > /sys/class/misc/prefetch/skt0_tb_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt0_tb_cavec to 128: (exp 128, 128, 255, 255)" +echo 128 > /sys/class/misc/prefetch/skt0_tb_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt1_ta_cavec to 0: (exp 128, 128, 0, 255)" +echo 0 > /sys/class/misc/prefetch/skt1_ta_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt0_tb_cavec to 128: (exp 128, 128, 128, 255)" +echo 128 > /sys/class/misc/prefetch/skt1_ta_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt1_tb_cavec to 0: (exp 128, 128, 128, 0)" +echo 0 > /sys/class/misc/prefetch/skt1_tb_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) + +echo "set skt1_tb_cavec to 128: (exp 128, 128, 128, 128)" +echo 128 > /sys/class/misc/prefetch/skt1_tb_cavec +cat /sys/class/misc/prefetch/skt0_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt0_tb_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_ta_cavec | grep register\(1\) +cat /sys/class/misc/prefetch/skt1_tb_cavec | grep register\(1\) \ No newline at end of file diff --git a/tests/HhaCtrl.sh b/tests/HhaCtrl.sh new file mode 100644 index 0000000..6e9f0b0 --- /dev/null +++ b/tests/HhaCtrl.sh @@ -0,0 +1,60 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-08-06 +# Author: Liuke (liuke20@gitee) + +echo "reg_ctrl_prefetch_drop set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/reg_ctrl_prefetch_drop + cat /sys/class/misc/prefetch/reg_ctrl_prefetch_drop | grep register\(1\) +done + +echo "reg_ctrl_dmcassign set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/reg_ctrl_dmcassign + cat /sys/class/misc/prefetch/reg_ctrl_dmcassign | grep register\(1\) +done + +echo "reg_ctrl_rdatabyp set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/reg_ctrl_rdatabyp + cat /sys/class/misc/prefetch/reg_ctrl_rdatabyp | grep register\(1\) +done + +echo "set reg_ctrl_prefetch_drop to be 0: exp(0, 1, 1)" +echo 0 > /sys/class/misc/prefetch/reg_ctrl_prefetch_drop +cat /sys/class/misc/prefetch/reg_ctrl_prefetch_drop | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_dmcassign | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_rdatabyp | grep register\(1\) + +echo "set reg_ctrl_dmcassign to be 0: exp(0, 0, 1)" +echo 0 > /sys/class/misc/prefetch/reg_ctrl_dmcassign +cat /sys/class/misc/prefetch/reg_ctrl_prefetch_drop | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_dmcassign | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_rdatabyp | grep register\(1\) + +echo "set reg_ctrl_rdatabyp to be 0: exp(0, 0, 0)" +echo 0 > /sys/class/misc/prefetch/reg_ctrl_rdatabyp +cat /sys/class/misc/prefetch/reg_ctrl_prefetch_drop | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_dmcassign | grep register\(1\) +cat /sys/class/misc/prefetch/reg_ctrl_rdatabyp | grep register\(1\) + +echo "reg_dir_replace_alg set text (exp 0, 1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/reg_dir_replace_alg + cat /sys/class/misc/prefetch/reg_dir_replace_alg | grep register\(1\) +done \ No newline at end of file diff --git a/tests/HhaFuncDis.sh b/tests/HhaFuncDis.sh new file mode 100644 index 0000000..01b813a --- /dev/null +++ b/tests/HhaFuncDis.sh @@ -0,0 +1,38 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-08-06 +# Author: Liuke (liuke20@gitee) + +echo "prefetch_comb set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_comb + cat /sys/class/misc/prefetch/prefetch_comb | grep register\(1\) +done + +echo "reg_funcdis_comb set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/reg_funcdis_comb + cat /sys/class/misc/prefetch/reg_funcdis_comb | grep register\(1\) +done + +echo "set prefetch_comb to be 0: exp(0,1)" +echo 0 > /sys/class/misc/prefetch/prefetch_comb +cat /sys/class/misc/prefetch/prefetch_comb | grep register\(1\) +cat /sys/class/misc/prefetch/reg_funcdis_comb | grep register\(1\) + +echo "set reg_funcdis_comb to be 0: exp(0,0)" +echo 0 > /sys/class/misc/prefetch/reg_funcdis_comb +cat /sys/class/misc/prefetch/prefetch_comb | grep register\(1\) +cat /sys/class/misc/prefetch/reg_funcdis_comb | grep register\(1\) diff --git a/tests/HhaTotemnum.sh b/tests/HhaTotemnum.sh new file mode 100644 index 0000000..b589555 --- /dev/null +++ b/tests/HhaTotemnum.sh @@ -0,0 +1,48 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-22 +# Author: Liuke (liuke20@gitee) + +echo "totem_dual set test (exp 0,1) :" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/totem_dual + cat /sys/class/misc/prefetch/totem_dual | grep register\(1\) +done + +echo "canum_sktvec set test (exp 0~15) :" +for i in {0..15} +do + echo $i > /sys/class/misc/prefetch/canum_sktvec + cat /sys/class/misc/prefetch/canum_sktvec | grep register\(1\) +done + +echo "set totem_dual to 0 (exp 0, 15) :" +echo 0 > /sys/class/misc/prefetch/totem_dual +cat /sys/class/misc/prefetch/totem_dual | grep register\(1\) +cat /sys/class/misc/prefetch/canum_sktvec | grep register\(1\) + +echo "set canum_sktvec to 2 (exp 0, 2) :" +echo 2 > /sys/class/misc/prefetch/canum_sktvec +cat /sys/class/misc/prefetch/totem_dual | grep register\(1\) +cat /sys/class/misc/prefetch/canum_sktvec | grep register\(1\) + +echo "set canum_sktvec to 8 (exp 0, 8) :" +echo 8 > /sys/class/misc/prefetch/canum_sktvec +cat /sys/class/misc/prefetch/totem_dual | grep register\(1\) +cat /sys/class/misc/prefetch/canum_sktvec | grep register\(1\) + +echo "set canum_sktvec to 11 (exp 0, 11) :" +echo 11 > /sys/class/misc/prefetch/canum_sktvec +cat /sys/class/misc/prefetch/totem_dual | grep register\(1\) +cat /sys/class/misc/prefetch/canum_sktvec | grep register\(1\) \ No newline at end of file diff --git a/tests/L3tDAuctrl0.sh b/tests/L3tDAuctrl0.sh new file mode 100644 index 0000000..e1e5290 --- /dev/null +++ b/tests/L3tDAuctrl0.sh @@ -0,0 +1,53 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-08-06 +# Author: Liuke (liuke20@gitee) + +echo "L3T_DYNAMIC_AUCTRL0: ddr_compress_opt_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/ddr_compress_opt_en + cat /sys/class/misc/prefetch/ddr_compress_opt_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL0: snpsleep_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/snpsleep_en + cat /sys/class/misc/prefetch/snpsleep_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL0: prefetchtgt_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetchtgt_en + cat /sys/class/misc/prefetch/prefetchtgt_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL0: set ddr_compress_opt_en to 0, (exp:0,1,1)" +echo 0 > /sys/class/misc/prefetch/ddr_compress_opt_en +cat /sys/class/misc/prefetch/ddr_compress_opt_en | grep register\(1\) +cat /sys/class/misc/prefetch/snpsleep_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetchtgt_en | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL0: set sequence_opt to 0, (exp:0,0,1)" +echo 0 > /sys/class/misc/prefetch/snpsleep_en +cat /sys/class/misc/prefetch/ddr_compress_opt_en | grep register\(1\) +cat /sys/class/misc/prefetch/snpsleep_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetchtgt_en | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL0: set prefetchtgt_en to 0, (exp:0,0,0)" +echo 0 > /sys/class/misc/prefetch/prefetchtgt_en +cat /sys/class/misc/prefetch/ddr_compress_opt_en | grep register\(1\) +cat /sys/class/misc/prefetch/snpsleep_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetchtgt_en | grep register\(1\) \ No newline at end of file diff --git a/tests/L3tDAuctrl1.sh b/tests/L3tDAuctrl1.sh new file mode 100644 index 0000000..0410e82 --- /dev/null +++ b/tests/L3tDAuctrl1.sh @@ -0,0 +1,133 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-21 +# Author: Liuke (liuke20@gitee) + +echo "L3T_DYNAMIC_AUCTRL1: bankintl_stagger set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/bankintl_stagger + cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: cpu_pf_lqos_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/cpu_pf_lqos_en + cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: prime_drop_mask set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prime_drop_mask + cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: refillsize_com_ada_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/refillsize_com_ada_en + cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: refillsize_pre_ada_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/refillsize_pre_ada_en + cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: sequence_opt set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/sequence_opt + cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: bankintlv set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/bankintlv + cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) +done + +echo "L3T_DYNAMIC_AUCTRL1: set bankintl_stagger to 0, (exp:0,1,1,1,1,1,1)" +echo 0 > /sys/class/misc/prefetch/bankintl_stagger +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set cpu_pf_lqos_en to 0, (exp:0,0,1,1,1,1,1)" +echo 0 > /sys/class/misc/prefetch/cpu_pf_lqos_en +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set prime_drop_mask to 0, (exp:0,0,0,1,1,1,1)" +echo 0 > /sys/class/misc/prefetch/prime_drop_mask +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set refillsize_com_ada_en to 0, (exp:0,0,0,0,1,1,1)" +echo 0 > /sys/class/misc/prefetch/refillsize_com_ada_en +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set refillsize_pre_ada_en to 0, (exp:0,0,0,0,0,1,1)" +echo 0 > /sys/class/misc/prefetch/refillsize_pre_ada_en +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set sequence_opt to 0, (exp:0,0,0,0,0,0,1)" +echo 0 > /sys/class/misc/prefetch/sequence_opt +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) + +echo "L3T_DYNAMIC_AUCTRL1: set bankintlv to 0, (exp:0,0,0,0,0,0,0)" +echo 0 > /sys/class/misc/prefetch/bankintlv +cat /sys/class/misc/prefetch/bankintl_stagger | grep register\(1\) +cat /sys/class/misc/prefetch/cpu_pf_lqos_en | grep register\(1\) +cat /sys/class/misc/prefetch/prime_drop_mask | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_com_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/refillsize_pre_ada_en | grep register\(1\) +cat /sys/class/misc/prefetch/sequence_opt | grep register\(1\) +cat /sys/class/misc/prefetch/bankintlv | grep register\(1\) \ No newline at end of file diff --git a/tests/L3tDynamicCtrl.sh b/tests/L3tDynamicCtrl.sh new file mode 100644 index 0000000..4541e25 --- /dev/null +++ b/tests/L3tDynamicCtrl.sh @@ -0,0 +1,96 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-13 +# Author: Liuke (liuke20@gitee) + +echo "L3T_STATIC_CTRL: ramswap set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/ramswap + cat /sys/class/misc/prefetch/ramswap | grep register\(1\) +done + +echo "L3T_DYNAMIC_CTRL: iocapacity_limit set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/iocapacity_limit + cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +done + +echo "L3T_DYNAMIC_CTRL: sqmerge set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/sqmerge + cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +done +''' +echo "L3T_DYNAMIC_CTRL: prefetch_drop_hha set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_drop_hha + cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +done +''' +echo "L3T_DYNAMIC_CTRL: tag_rep_alg set test, (exp:0~3)" +for i in {0..3} +do + echo $i > /sys/class/misc/prefetch/tag_rep_alg + cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +done + +echo "L3T_DYNAMIC_CTRL: rdmerge_upgrade_en set test, (exp:0~1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/rdmerge_upgrade_en + cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) +done + +echo "L3T_DYNAMIC_CTRL: set iocapacity_limit to 0, (exp:0, 1, 1, 3, 1)" +echo 0 > /sys/class/misc/prefetch/iocapacity_limit +cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) + +echo "L3T_DYNAMIC_CTRL: set sqmerge to 0, (exp:0, 0, 1, 3, 1)" +echo 0 > /sys/class/misc/prefetch/sqmerge +cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) +''' +echo "L3T_DYNAMIC_CTRL: set prefetch_drop_hha to 0, (exp:0, 0, 0, 3, 1)" +echo 0 > /sys/class/misc/prefetch/prefetch_drop_hha +cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) +''' +echo "L3T_DYNAMIC_CTRL: set tag_rep_alg to 2, (exp:0, 0, 0, 2, 1)" +echo 2 > /sys/class/misc/prefetch/tag_rep_alg +cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) + +echo "L3T_DYNAMIC_CTRL: set rdmerge_upgrade_en to 0, (exp:0, 0, 0, 2, 0)" +echo 0 > /sys/class/misc/prefetch/rdmerge_upgrade_en +cat /sys/class/misc/prefetch/iocapacity_limit | grep register\(1\) +cat /sys/class/misc/prefetch/sqmerge | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_drop_hha | grep register\(1\) +cat /sys/class/misc/prefetch/tag_rep_alg | grep register\(1\) +cat /sys/class/misc/prefetch/rdmerge_upgrade_en | grep register\(1\) \ No newline at end of file diff --git a/tests/L3tPrefetch.sh b/tests/L3tPrefetch.sh new file mode 100644 index 0000000..8ebfa8f --- /dev/null +++ b/tests/L3tPrefetch.sh @@ -0,0 +1,264 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# * Copyright(c) 2019 Huawei Technologies Co., Ltd +# * +# * This program is free software; you can redistribute it and/or modify it +# * under the terms and conditions of the GNU General Public License, +# * version 2, as published by the Free Software Foundation. +# * +# * This program is distributed in the hope it will be useful, but WITHOUT +# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# * for more details. +# Create: 2020-07-21 +# Author: Liuke (liuke20@gitee) + +<<<<<<< HEAD +======= +echo "L3T_PREFETCH: prefetch_overide_level set test, (exp:0~15)" +for i in {0..15} +do + echo $i > /sys/class/misc/prefetch/prefetch_overide_level + cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +done + +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +echo "L3T_PREFETCH: prefetch_utl_ddr set test, (exp:0~3)" +for i in {0..3} +do + echo $i > /sys/class/misc/prefetch/prefetch_utl_ddr + cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +done + +echo "L3T_PREFETCH: prefetch_utl_ddr_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_utl_ddr_en + cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +done + +echo "L3T_PREFETCH: prefetch_utl_l3t set test, (exp:0~3)" +for i in {0..3} +do + echo $i > /sys/class/misc/prefetch/prefetch_utl_l3t + cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +done + +echo "L3T_PREFETCH: prefetch_utl_l3t_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_utl_l3t_en + cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +done + +<<<<<<< HEAD +======= +echo "L3T_PREFETCH: prefetch_vague_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_vague_en + cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +done + +echo "L3T_PREFETCH: prefetch_core_en set test, (exp:0~15)" +for i in {0..15} +do + echo $i > /sys/class/misc/prefetch/prefetch_core_en + cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +done + +echo "L3T_PREFETCH: prefetch_match_en set test, (exp:0,1)" +for i in {0..1} +do + echo $i > /sys/class/misc/prefetch/prefetch_match_en + cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +done + +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +echo "L3T_PREFETCH: prefetch_start_level set test, (exp:0~15)" +for i in {0..15} +do + echo $i > /sys/class/misc/prefetch/prefetch_start_level + cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) +done + +<<<<<<< HEAD +echo "L3T_PREFETCH: set prefetch_utl_ddr to 0, (exp:0,1,3,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_ddr +======= +echo "L3T_PREFETCH: set prefetch_overide_level to 10, (exp:10,3,1,3,1,1,15,1,15)" +echo 10 > /sys/class/misc/prefetch/prefetch_overide_level +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_ddr to 2, (exp:2,1,3,1,15)" +echo 2 > /sys/class/misc/prefetch/prefetch_utl_ddr +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_ddr to 0, (exp:10,0,1,3,1,1,15,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_ddr +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_ddr_en to 0, (exp:2,0,3,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_ddr_en +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_ddr_en to 0, (exp:10,0,0,3,1,1,15,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_ddr_en +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_l3t to 0, (exp:2,0,0,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_l3t +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_l3t to 0, (exp:10,0,0,0,1,1,15,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_l3t +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_l3t to 2, (exp:2,0,2,1,15)" +echo 2 > /sys/class/misc/prefetch/prefetch_utl_l3t +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_l3t_en to 0, (exp:10,0,0,0,0,1,15,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_l3t_en +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_utl_l3t_en to 0, (exp:2,0,2,0,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_utl_l3t_en +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_vague_en to 0, (exp:10,0,0,0,0,0,15,1,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_vague_en +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_start_level to 0, (exp:2,0,2,0,0)" +echo 0 > /sys/class/misc/prefetch/prefetch_start_level +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_core_en to 10, (exp:10,0,0,0,0,0,10,1,15)" +echo 10 > /sys/class/misc/prefetch/prefetch_core_en +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_start_level to 4, (exp:2,0,2,0,4)" +echo 4 > /sys/class/misc/prefetch/prefetch_start_level +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_match_en to 10, (exp:10,0,0,0,0,0,10,0,15)" +echo 0 > /sys/class/misc/prefetch/prefetch_match_en +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_start_level to 10, (exp:2,0,2,0,10)" +echo 10 > /sys/class/misc/prefetch/prefetch_start_level +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_start_level to 10, (exp:10,0,0,0,0,0,10,0,10)" +echo 10 > /sys/class/misc/prefetch/prefetch_start_level +cat /sys/class/misc/prefetch/prefetch_overide_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +<<<<<<< HEAD +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) + +echo "L3T_PREFETCH: set prefetch_start_level to 15, (exp:2,0,2,0,15)" +echo 15 > /sys/class/misc/prefetch/prefetch_start_level +cat /sys/class/misc/prefetch/prefetch_utl_ddr | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_ddr_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_utl_l3t_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) +======= +cat /sys/class/misc/prefetch/prefetch_vague_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_core_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_match_en | grep register\(1\) +cat /sys/class/misc/prefetch/prefetch_start_level | grep register\(1\) +>>>>>>> 6acb3957d70036f30447fb21f5d76af392855196 -- Gitee