From bd98f9a7dc03c2125787f6ff28367c528824cc29 Mon Sep 17 00:00:00 2001 From: guningbo Date: Wed, 20 Mar 2024 12:38:31 +0000 Subject: [PATCH] =?UTF-8?q?=E9=80=82=E9=85=8Droc-rk3588s-pc=E4=B8=BB?= =?UTF-8?q?=E6=9D=BF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .oebuild/platform/roc-rk3588s-pc.yaml | 17 + .../conf/machine/roc-rk3588s-pc.conf | 6 + .../packagegroups/packagegroup-base.bbappend | 1 + .../roc-rk3588s-pc/roc-rk3588s-pc_defconfig | 6894 +++++++++++++++ .../patches/0001-roc-rk3588s-pc-dts.patch | 7397 +++++++++++++++++ .../linux/linux-openeuler-rt.bbappend | 2 +- .../linux/linux-openeuler.bbappend | 2 +- .../recipes-kernel/linux/linux-rockchip.inc | 5 + .../recipes-kernel/linux/rockchip-kernel.bb | 2 +- 9 files changed, 14323 insertions(+), 3 deletions(-) create mode 100644 .oebuild/platform/roc-rk3588s-pc.yaml create mode 100644 bsp/meta-openeuler-bsp/conf/machine/roc-rk3588s-pc.conf create mode 100644 bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/config/roc-rk3588s-pc/roc-rk3588s-pc_defconfig create mode 100644 bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/patches/0001-roc-rk3588s-pc-dts.patch diff --git a/.oebuild/platform/roc-rk3588s-pc.yaml b/.oebuild/platform/roc-rk3588s-pc.yaml new file mode 100644 index 00000000000..7cd83786d31 --- /dev/null +++ b/.oebuild/platform/roc-rk3588s-pc.yaml @@ -0,0 +1,17 @@ +type: platform + +machine: roc-rk3588s-pc + +toolchain_type: EXTERNAL_TOOLCHAIN:aarch64 + +repos: + yocto-meta-rockchip: + url: https://gitee.com/openeuler/yocto-meta-rockchip.git + path: yocto-meta-rockchip + refspec: dev_kirkstone + +layers: + - yocto-meta-rockchip + +local_conf: | + PREFERRED_PROVIDER_virtual/kernel ?= "linux-openeuler" diff --git a/bsp/meta-openeuler-bsp/conf/machine/roc-rk3588s-pc.conf b/bsp/meta-openeuler-bsp/conf/machine/roc-rk3588s-pc.conf new file mode 100644 index 00000000000..6ccec3e4861 --- /dev/null +++ b/bsp/meta-openeuler-bsp/conf/machine/roc-rk3588s-pc.conf @@ -0,0 +1,6 @@ +require conf/machine/include/openeuler-rockchip-rk3588-evb.conf + +# 将KBUILD_DEFCONFIG设置为空，使用OPENEULER_KERNEL_CONFIG变量设置config +KBUILD_DEFCONFIG = "" +ROCKCHIP_KERNEL_DTB_NAME = "roc-rk3588s-pc.dtb" +SERIAL_CONSOLES = "115200;ttyFIQ0" \ No newline at end of file diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-core/packagegroups/packagegroup-base.bbappend b/bsp/meta-openeuler-bsp/rockchip/recipes-core/packagegroups/packagegroup-base.bbappend index 784d40a2323..e825da86edb 100644 --- a/bsp/meta-openeuler-bsp/rockchip/recipes-core/packagegroups/packagegroup-base.bbappend +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-core/packagegroups/packagegroup-base.bbappend @@ -2,4 +2,5 @@ RDEPENDS:packagegroup-base:append = " \ wpa-supplicant \ wififirmware \ +parted util-linux-findmnt e2fsprogs-resize2fs \ " diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/config/roc-rk3588s-pc/roc-rk3588s-pc_defconfig b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/config/roc-rk3588s-pc/roc-rk3588s-pc_defconfig new file mode 100644 index 00000000000..b1150f2764c --- /dev/null +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/config/roc-rk3588s-pc/roc-rk3588s-pc_defconfig @@ -0,0 +1,6894 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.10.0 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="aarch64-openeuler-linux-gnu-gcc (crosstool-NG 1.25.0) 10.3.1" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100301 +CONFIG_LD_VERSION=237000000 +CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="localhost" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_SCHED_THERMAL_PRESSURE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +CONFIG_UCLAMP_TASK=y +CONFIG_UCLAMP_BUCKETS_COUNT=20 +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_CGROUP_SCHED=y +# CONFIG_QOS_SCHED is not set +# CONFIG_SCHED_PRIO_LB is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_UCLAMP_TASK_GROUP=y +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +# CONFIG_CGROUP_FILES is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_STEAL is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_INITRAMFS_FILE_METADATA="" +# CONFIG_BOOT_CONFIG is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_KABI_RESERVE=y +CONFIG_KABI_SIZE_ALIGN_CHECKS=y +# end of General setup + +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA32=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_HAS_CPU_RELAX=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PHYTIUM is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_ROCKCHIP=y +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y + +# +# Enable Livepatch +# +# end of Enable Livepatch + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_1508412=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_CAVIUM_TX2_ERRATUM_219=y +CONFIG_FUJITSU_ERRATUM_010001=y +CONFIG_HISILICON_ERRATUM_161600802=y +# CONFIG_HISILICON_ERRATUM_1980005 is not set +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y +# CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SCHED_MC=y +# CONFIG_SCHED_CLUSTER is not set +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_NUMA is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_LLC_128_LINE_SIZE=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_ARM64_PMEM_LEGACY is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +# CONFIG_AARCH32_EL0 is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LSE_ATOMICS=y +CONFIG_ARM64_VHE=y +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +# end of ARMv8.3 architectural features + +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +CONFIG_AS_HAS_ARMV8_4=y +CONFIG_ARM64_TLB_RANGE=y +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_ARM64_BTI=y +CONFIG_ARM64_BTI_KERNEL=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +CONFIG_ARM64_E0PD=y +CONFIG_ARCH_RANDOM=y +CONFIG_ARM64_AS_HAS_MTE=y +CONFIG_ARM64_MTE=y +# end of ARMv8.5 architectural features + +# +# ARMv8.6 architectural features +# +CONFIG_ARM64_TWED=y +# end of ARMv8.6 architectural features + +# +# ARMv8.7 architectural features +# +CONFIG_ARM64_EPAN=y +# end of ARMv8.7 architectural features + +CONFIG_ARM64_SVE=y +CONFIG_ARM64_SME=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_RELOCATABLE=y +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# CONFIG_ASCEND_FEATURES is not set +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y +# end of Boot options + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_DT_IDLE_STATES=y + +# +# ARM CPU Idle Drivers +# +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +# end of ARM CPU Idle Drivers + +CONFIG_HALTPOLL_CPUIDLE=y +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_ARM_ROCKCHIP_CPUFREQ=y +# CONFIG_ARM_SCMI_CPUFREQ is not set +# end of CPU Frequency scaling +# end of CPU Power Management + +# +# Firmware Drivers +# +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCMI_POWER_DOMAIN=y +# CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_ROCKCHIP_SIP=y +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_ZBOOT=y +# CONFIG_EFI_ZBOOT_SIGNED is not set +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +CONFIG_ARM_SMCCC_SOC_ID=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +# CONFIG_VIRTUALIZATION is not set +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA256_ARM64=y +# CONFIG_CRYPTO_SHA512_ARM64 is not set +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +# CONFIG_CRYPTO_SHA512_ARM64_CE is not set +# CONFIG_CRYPTO_SHA3_ARM64 is not set +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_POLY1305_NEON is not set +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +# CONFIG_CRYPTO_AES_ARM64_BS is not set + +# +# General architecture-dependent options +# +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_CMDLINE_PARSER=y +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_CMDLINE_PARTITION=y +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HOLES_IN_ZONE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PAGE_REPORTING is not set +CONFIG_MIGRATION=y +# CONFIG_HUGE_VMALLOC_DEFAULT_ENABLED is not set +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_ETMEM_SCAN is not set +# CONFIG_ETMEM_SWAP is not set +# CONFIG_PAGE_CACHE_LIMIT is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_FRAME_VECTOR=y +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# CONFIG_PIN_MEMORY is not set +# CONFIG_CLEAR_FREELIST_PAGE is not set + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_ESP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_TCP_COMP is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_VTI is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_MPTCP is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_FAMILY_BRIDGE=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NETFILTER_NETLINK_OSF=y +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_SECMARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=y +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_TABLES=y +# CONFIG_NF_TABLES_INET is not set +# CONFIG_NF_TABLES_NETDEV is not set +# CONFIG_NFT_NUMGEN is not set +# CONFIG_NFT_CT is not set +# CONFIG_NFT_COUNTER is not set +# CONFIG_NFT_CONNLIMIT is not set +# CONFIG_NFT_LOG is not set +# CONFIG_NFT_LIMIT is not set +# CONFIG_NFT_MASQ is not set +# CONFIG_NFT_REDIR is not set +# CONFIG_NFT_NAT is not set +# CONFIG_NFT_TUNNEL is not set +# CONFIG_NFT_OBJREF is not set +# CONFIG_NFT_QUOTA is not set +# CONFIG_NFT_REJECT is not set +# CONFIG_NFT_COMPAT is not set +# CONFIG_NFT_HASH is not set +# CONFIG_NFT_XFRM is not set +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=y +CONFIG_NETFILTER_XT_TARGET_NETMAP=y +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_IPVS=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +CONFIG_NETFILTER_XT_MATCH_MAC=y +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +CONFIG_IP_VS=y +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +# CONFIG_IP_VS_PROTO_TCP is not set +# CONFIG_IP_VS_PROTO_UDP is not set +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +# CONFIG_IP_VS_RR is not set +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_FO is not set +# CONFIG_IP_VS_OVF is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_MH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +# CONFIG_IP_VS_NFCT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_SOCKET_IPV4=y +CONFIG_NF_TPROXY_IPV4=y +CONFIG_NF_TABLES_IPV4=y +# CONFIG_NFT_DUP_IPV4 is not set +# CONFIG_NFT_FIB_IPV4 is not set +# CONFIG_NF_TABLES_ARP is not set +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=y +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=y +CONFIG_NF_TPROXY_IPV6=y +# CONFIG_NF_TABLES_IPV6 is not set +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_NAT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_TABLES_BRIDGE is not set +CONFIG_NF_CONNTRACK_BRIDGE=y +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_MRP=y +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_CLS_CGROUP=y +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_L3_MASTER_DEV=y +# CONFIG_QRTR is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y +CONFIG_CAN_GW=y +# CONFIG_CAN_J1939 is not set +# CONFIG_CAN_ISOTP is not set + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +# CONFIG_CAN_VXCAN is not set +# CONFIG_CAN_SLCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_KVASER_PCIEFD is not set +# CONFIG_CAN_XILINXCAN is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_PEAK_PCIEFD is not set +CONFIG_CAN_ROCKCHIP=y +CONFIG_CANFD_ROCKCHIP=y +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_SOFTING is not set + +# +# CAN SPI interfaces +# +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +# CONFIG_CAN_8DEV_USB is not set +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_ESD_USB2 is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_KVASER_USB is not set +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_PEAK_USB is not set +# CONFIG_CAN_UCAN is not set +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set +# end of CAN Device Drivers + +CONFIG_BT=y +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +# CONFIG_BT_HS is not set +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +# CONFIG_BT_MSFTEXT is not set +CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=y +CONFIG_BT_BCM=y +CONFIG_BT_RTL=y +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set +CONFIG_BT_HCIBTUSB_RTL=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIUART_ATH3K=y +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_AG6XX is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +CONFIG_BT_HCIBFUSB=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +# CONFIG_BT_ATH3K is not set +# CONFIG_BT_MTKSDIO is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +CONFIG_RFKILL_RK=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y +CONFIG_FAILOVER=y +CONFIG_ETHTOOL_NETLINK=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_POWERSAVE=y +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +CONFIG_PCIE_ROCKCHIP=y +CONFIG_PCIE_ROCKCHIP_HOST=y + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +CONFIG_PCIE_DW_ROCKCHIP=y +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +CONFIG_DEBUG_DEVRES=y +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_SIMPLE_PM_BUS is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_MHI_BUS is not set +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_GNSS is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set + +# +# Partition parsers +# +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +CONFIG_MTD_SPI_NAND=y + +# +# ECC engine support +# +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_HYPERBUS is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_CDROM=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_ZRAM=y +# CONFIG_ZRAM_WRITEBACK is not set +# CONFIG_ZRAM_MEMORY_TRACKING is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_HISI_SAS is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_SMARTPQI is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_RAMAXEL_SPRAID is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_MYRB is not set +# CONFIG_SCSI_MYRS is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FDOMAIN_PCI is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_QORIQ is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +# CONFIG_BLK_DEV_DM is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +CONFIG_VIRTIO_NET=y +CONFIG_NLMON=y +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +# CONFIG_NET_VENDOR_AMD is not set +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_VENDOR_AURORA=y +# CONFIG_AURORA_NB8800 is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_BMA is not set +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +CONFIG_E1000E=y +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +CONFIG_NET_VENDOR_NETSWIFT=y +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_ROCKCHIP=y +CONFIG_DWMAC_ROCKCHIP_TOOL=y +# CONFIG_DWMAC_RK_AUTO_DELAYLINE is not set +# CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_STMMAC_PCI is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +CONFIG_ROCKCHIP_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=y +# end of PCS device drivers + +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +# CONFIG_SLIP is not set +CONFIG_SLHC=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_CATC=y +CONFIG_USB_KAWETH=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8150=y +CONFIG_USB_RTL8152=y +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_CDCETHER=y +CONFIG_USB_NET_CDC_EEM=y +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +CONFIG_USB_NET_CDC_MBIM=y +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=y +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=y +CONFIG_USB_NET_CDC_SUBSET=y +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=y +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +CONFIG_USB_IPHETH=y +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +# CONFIG_ADM8211 is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +# CONFIG_ATH10K is not set +# CONFIG_WCN36XX is not set +CONFIG_WLAN_VENDOR_ATMEL=y +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLWIFI is not set +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_PRISM54 is not set +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_MWIFIEX is not set +# CONFIG_MWL8K is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +# CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x0E is not set +# CONFIG_MT76x2E is not set +# CONFIG_MT76x2U is not set +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_RALINK=y +# CONFIG_RT2X00 is not set +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +CONFIG_RTL_CARDS=y +# CONFIG_RTL8192CE is not set +# CONFIG_RTL8192SE is not set +# CONFIG_RTL8192DE is not set +# CONFIG_RTL8723AE is not set +# CONFIG_RTL8723BE is not set +# CONFIG_RTL8188EE is not set +# CONFIG_RTL8192EE is not set +# CONFIG_RTL8821AE is not set +# CONFIG_RTL8192CU is not set +# CONFIG_RTL8XXXU is not set +# CONFIG_RTW88 is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_ZD1211RW is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_QTNFMAC_PCIE is not set +CONFIG_WL_ROCKCHIP=y +CONFIG_WIFI_BUILD_MODULE=y +# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set +# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set +# CONFIG_MXMWIFIEX is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=y +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ADC=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +CONFIG_MOUSE_CYAPA=y +CONFIG_MOUSE_ELAN_I2C=y +CONFIG_MOUSE_ELAN_I2C_I2C=y +# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GOODIX=y +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +CONFIG_TOUCHSCREEN_ELAN=y +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +CONFIG_TOUCHSCREEN_USB_COMPOSITE=y +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_IQS5XX is not set +# CONFIG_TOUCHSCREEN_ZINITIX is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +CONFIG_INPUT_RK805_PWRKEY=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_16550A_VARIANTS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=10 +CONFIG_SERIAL_8250_RUNTIME_UARTS=10 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_VIRTIO is not set +CONFIG_HW_RANDOM_OPTEE=y +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_ROCKCHIP=y +# CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y +# CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +# CONFIG_TCG_TIS is not set +# CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +CONFIG_TCG_TIS_I2C_INFINEON=y +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +# CONFIG_TCG_ATMEL is not set +# CONFIG_TCG_VTPM_PROXY is not set +# CONFIG_TCG_FTPM_TEE is not set +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_HISI is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_RK3X=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_ROCKCHIP=y +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_RK805=y +# CONFIG_PINCTRL_OCELOT is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +CONFIG_GPIO_ROCKCHIP=y +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# CONFIG_GPIO_TPS6586X is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_W1 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +CONFIG_REBOOT_MODE=y +CONFIG_SYSCON_REBOOT_MODE=y +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +CONFIG_BATTERY_SBS=y +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +CONFIG_CHARGER_GPIO=y +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +CONFIG_CHARGER_BQ24735=y +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_ARM_SCMI is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +CONFIG_SENSORS_PWM_FAN=y +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_MMIO is not set +CONFIG_ROCKCHIP_THERMAL=y +# CONFIG_GENERIC_ADC_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +CONFIG_DW_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ARM_SMC_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=y +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +CONFIG_MFD_TPS6586X=y +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_INTEL_M10_BMC is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_ACT8865=y +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=y +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +CONFIG_REGULATOR_RK808=y +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=y +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_TPS6586X=y +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_RC_CORE is not set +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_CEC_CH7322 is not set +# CONFIG_USB_PULSE8_CEC is not set +# CONFIG_USB_RAINSHADOW_CEC is not set +CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_V4L2_MEM2MEM_DEV=y +CONFIG_V4L2_FWNODE=y +# end of Video4Linux options + +# +# Media controller options +# +# CONFIG_MEDIA_CONTROLLER_DVB is not set +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=16 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=y +# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog TV USB devices +# +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_STK1160_COMMON is not set +# CONFIG_VIDEO_GO7007 is not set + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_CX231XX is not set + +# +# Digital TV USB devices +# +# CONFIG_DVB_USB_V2 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set + +# +# Software defined radio USB devices +# +# CONFIG_USB_AIRSPY is not set +# CONFIG_USB_HACKRF is not set +# CONFIG_USB_MSI2500 is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_MR800 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_SHARK is not set +# CONFIG_RADIO_SHARK2 is not set +# CONFIG_USB_KEENE is not set +# CONFIG_USB_RAREMONO is not set +# CONFIG_USB_MA901 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEOBUF2_DMA_SG=y +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +CONFIG_VIDEO_ROCKCHIP_RGA=y +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_SDR_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_TEST_DRIVERS is not set +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_MAX9286 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AD9389B is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# end of Miscellaneous helper chips + +# +# Camera sensor devices +# +# CONFIG_VIDEO_HI556 is not set +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +CONFIG_VIDEO_OV5645=y +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5675 is not set +CONFIG_VIDEO_OV5695=y +CONFIG_VIDEO_OV7251=y +# CONFIG_VIDEO_OV772X is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RDACM20 is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set +# end of Camera sensor devices + +# +# Lens drivers +# +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9768 is not set +# CONFIG_VIDEO_DW9807_VCM is not set +# end of Lens drivers + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set +# end of Flash devices + +# +# SPI helper chips +# +# CONFIG_VIDEO_GS1662 is not set +# end of SPI helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m +CONFIG_DVB_MN88443X=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set + +# +# ARM devices +# +# end of ARM devices + +# CONFIG_MALI400 is not set +# CONFIG_MALI_MIDGARD is not set +# CONFIG_MALI_KUTF is not set +# CONFIG_MALI_BIFROST is not set + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set +# end of Backlight & LCD device support + +# +# Rockchip Misc Video driver +# + +# +# RGA +# +# CONFIG_ROCKCHIP_RGA is not set +# end of RGA + +CONFIG_ROCKCHIP_MULTI_RGA=y +CONFIG_ROCKCHIP_RGA_ASYNC=y +# CONFIG_ROCKCHIP_RGA_PROC_FS is not set +CONFIG_ROCKCHIP_RGA_DEBUG_FS=y +CONFIG_ROCKCHIP_RGA_DEBUGGER=y +# CONFIG_ROCKCHIP_RVE is not set + +# +# IEP +# +# CONFIG_IEP is not set +# end of IEP + +# CONFIG_ROCKCHIP_MPP_SERVICE is not set +# CONFIG_ROCKCHIP_DVBM is not set +# end of Rockchip Misc Video driver + +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_SEQ_DEVICE=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_SEQUENCER=y +CONFIG_SND_SEQ_DUMMY=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=y +CONFIG_SND_SEQ_MIDI=y +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_PCI is not set + +# +# HD-Audio +# +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +CONFIG_SND_SOC_ROCKCHIP=y +CONFIG_SND_SOC_ROCKCHIP_I2S=y +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y +CONFIG_SND_SOC_ROCKCHIP_PDM=y +CONFIG_SND_SOC_ROCKCHIP_SPDIF=y +CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=y +# CONFIG_SND_SOC_ROCKCHIP_VAD is not set +CONFIG_SND_SOC_ROCKCHIP_MAX98090=y +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y +CONFIG_SND_SOC_ROCKCHIP_RT5645=y +CONFIG_SND_SOC_ROCKCHIP_HDMI=y +# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_DUMMY_CODEC=y +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8316=y +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +CONFIG_SND_SOC_MAX98090=y +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +CONFIG_SND_SOC_RK3328=y +CONFIG_SND_SOC_RK817=y +CONFIG_SND_SOC_RK_CODEC_DIGITAL=y +CONFIG_SND_SOC_RL6231=y +CONFIG_SND_SOC_RT5616=y +# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5645=y +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +CONFIG_SND_SOC_SPDIF=y +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +CONFIG_SND_SOC_TS3A227E=y +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +CONFIG_SND_SOC_NAU8822=y +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +# CONFIG_SND_AUDIO_GRAPH_CARD is not set + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +CONFIG_HID_MULTITOUCH=y +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_U2FZERO is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +CONFIG_I2C_HID=y +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEFAULT_PERSIST is not set +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=y + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PCI is not set +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=y +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_PCI is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=y +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=y +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +CONFIG_USB_SERIAL_KEYSPAN=y +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OTI6858=y +# CONFIG_USB_SERIAL_QCAUX is not set +CONFIG_USB_SERIAL_QUALCOMM=y +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SIERRAWIRELESS=y +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_EZUSB_FX2=y +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_U_SERIAL_CONSOLE is not set + +# +# USB Peripheral Controller +# +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_MAX3420_UDC is not set +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=y +CONFIG_USB_F_ACM=y +CONFIG_USB_U_SERIAL=y +CONFIG_USB_F_MASS_STORAGE=y +CONFIG_USB_F_FS=y +CONFIG_USB_F_UVC=y +CONFIG_USB_CONFIGFS=y +# CONFIG_USB_CONFIGFS_SERIAL is not set +CONFIG_USB_CONFIGFS_ACM=y +# CONFIG_USB_CONFIGFS_OBEX is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +# CONFIG_USB_CONFIGFS_RNDIS is not set +# CONFIG_USB_CONFIGFS_EEM is not set +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +CONFIG_USB_CONFIGFS_F_FS=y +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_HID is not set +CONFIG_USB_CONFIGFS_F_UVC=y +# CONFIG_USB_CONFIGFS_F_PRINTER is not set + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_TCPCI_MAXIM is not set +CONFIG_TYPEC_FUSB302=y +# CONFIG_TYPEC_UCSI is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_STUSB160X is not set + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=y +# CONFIG_TYPEC_NVIDIA_ALTMODE is not set +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +# CONFIG_PWRSEQ_SD8787 is not set +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_SDIO_UART is not set +CONFIG_MMC_TEST=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=y +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_ROCKCHIP=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +CONFIG_LEDS_IS31FL32XX=y + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +CONFIG_RTC_DRV_HYM8563=y +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RK808=y +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=y +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_TPS6586X is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +CONFIG_RTC_DRV_RX8010=y +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_HISI_DMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_MV_XOR_V2 is not set +CONFIG_PL330_DMA=y +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_DMABUF_CACHE=y +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_SYSFS_STATS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +# CONFIG_DMABUF_HEAPS_ROCKCHIP is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_INPUT is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL8723BS is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_RTS5208 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# CONFIG_AD7280 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +# CONFIG_FB_SM750 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +# CONFIG_ASHMEM is not set +# CONFIG_DEBUG_KINFO is not set +# CONFIG_ION is not set +CONFIG_FIQ_DEBUGGER=y +CONFIG_FIQ_DEBUGGER_NO_SLEEP=y +# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set +CONFIG_FIQ_DEBUGGER_CONSOLE=y +CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y +CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y +# CONFIG_FIQ_DEBUGGER_UART_OVERLAY is not set +CONFIG_RK_CONSOLE_THREAD=y +# end of Android + +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_FB_TFT is not set +# CONFIG_KS7010 is not set +# CONFIG_PI433 is not set + +# +# Gasket devices +# +# CONFIG_STAGING_GASKET_FRAMEWORK is not set +# end of Gasket devices + +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_FIELDBUS_DEV is not set +# CONFIG_QLGE is not set +# CONFIG_WFX is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_HAVE_CLK=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_MAX9485 is not set +CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_XGENE is not set +CONFIG_COMMON_CLK_PWM=y +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_ROCKCHIP=y +CONFIG_CLK_PX30=y +CONFIG_CLK_RK1808=y +CONFIG_CLK_RK3328=y +CONFIG_CLK_RK3399=y +CONFIG_CLK_RK3568=y +CONFIG_CLK_RK3588=y +# CONFIG_ROCKCHIP_CLK_COMPENSATION is not set +CONFIG_ROCKCHIP_CLK_LINK=y +CONFIG_ROCKCHIP_CLK_BOOST=y +CONFIG_ROCKCHIP_CLK_INV=y +CONFIG_ROCKCHIP_CLK_PVTM=y +CONFIG_ROCKCHIP_DDRCLK=y +# CONFIG_ROCKCHIP_DDRCLK_SCPI is not set +CONFIG_ROCKCHIP_DDRCLK_SIP=y +CONFIG_ROCKCHIP_DDRCLK_SIP_V2=y +# CONFIG_ROCKCHIP_PLL_RK3066 is not set +CONFIG_ROCKCHIP_PLL_RK3399=y +CONFIG_ROCKCHIP_PLL_RK3588=y +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +# CONFIG_ARM_MHU is not set +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PL320_MBOX is not set +# CONFIG_ROCKCHIP_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +CONFIG_IOMMU_IO_PGTABLE=y +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_OF_IOMMU=y +CONFIG_IOMMU_DMA=y +CONFIG_ROCKCHIP_IOMMU=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set +# CONFIG_VIRTIO_IOMMU is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# CONFIG_FSL_RCPM is not set +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# +# Rockchip CPU selection +# +CONFIG_CPU_PX30=y +CONFIG_CPU_RK1808=y +# CONFIG_CPU_RK3308 is not set +CONFIG_CPU_RK3328=y +# CONFIG_CPU_RK3368 is not set +CONFIG_CPU_RK3399=y +CONFIG_CPU_RK3568=y +CONFIG_CPU_RK3588=y +# end of Rockchip CPU selection + +CONFIG_NO_GKI=y +CONFIG_ROCKCHIP_CPUINFO=y +CONFIG_ROCKCHIP_GRF=y +# CONFIG_ROCKCHIP_HW_DECOMPRESS is not set +CONFIG_ROCKCHIP_IODOMAIN=y +# CONFIG_ROCKCHIP_IOMUX is not set +CONFIG_ROCKCHIP_IPA=y +CONFIG_ROCKCHIP_OPP=y +# CONFIG_ROCKCHIP_PERFORMANCE is not set +CONFIG_ROCKCHIP_PM_DOMAINS=y +CONFIG_ROCKCHIP_PVTM=y +# CONFIG_ROCKCHIP_RAMDISK is not set +CONFIG_ROCKCHIP_SUSPEND_MODE=y +CONFIG_ROCKCHIP_SYSTEM_MONITOR=y +CONFIG_ROCKCHIP_VENDOR_STORAGE=y +CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE=y +# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set +CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y +CONFIG_ROCKCHIP_FIQ_DEBUGGER=y +CONFIG_ROCKCHIP_DEBUG=y +# CONFIG_ROCKCHIP_MINI_KERNEL is not set +# CONFIG_ROCKCHIP_THUNDER_BOOT is not set +# CONFIG_ROCKCHIP_NPOR_POWERGOOD is not set +# CONFIG_RK_CMA_PROCFS is not set +# CONFIG_RK_DMABUF_PROCFS is not set +# CONFIG_RK_MEMBLOCK_PROCFS is not set +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=y +CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +# CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_DMA is not set +# CONFIG_IIO_BUFFER_DMAENGINE is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGERED_BUFFER=y +# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_SW_DEVICE is not set +# CONFIG_IIO_SW_TRIGGER is not set +# CONFIG_IIO_TRIGGERED_EVENT is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7091R5 is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_ADI_AXI_ADC is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_ENVELOPE_DETECTOR is not set +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1241 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +CONFIG_ROCKCHIP_SARADC=y +# CONFIG_SD_ADC_MODULATOR is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set +# end of Analog to digital converters + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set +# end of Amplifiers + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_SCD30_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SPS30 is not set +# CONFIG_VZ89X is not set +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +# end of Hid Sensor IIO Common + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5770R is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# end of IIO dummy driver + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS290 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_FXAS21002C is not set +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HDC2010 is not set +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADIS16475 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_ICM42600_I2C is not set +# CONFIG_INV_ICM42600_SPI is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set +# end of Inertial measurement units + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_AS73211 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM3605 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set +# CONFIG_GP2AP020A00F is not set +CONFIG_SENSORS_ISL29018=y +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_MAX44009 is not set +# CONFIG_NOA1305 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +CONFIG_SENSORS_TSL2563=y +CONFIG_TSL2583=y +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set +# end of Light sensors + +# +# Magnetometer sensors +# +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +# CONFIG_IIO_MUX is not set +# end of Multiplexers + +# +# Inclinometer sensors +# +# end of Inclinometer sensors + +# +# Triggers - standalone +# +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_SYSFS_TRIGGER=y +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set +# end of Digital potentiometers + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set +# end of Digital potentiostats + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +# CONFIG_DLHL60D is not set +# CONFIG_DPS310 is not set +# CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_MB1232 is not set +# CONFIG_PING is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9310 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VCNL3020 is not set +# CONFIG_VL53L0X_I2C is not set +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +# CONFIG_LTC2983 is not set +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_MAX31856 is not set +# end of Temperature sensors + +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_ROCKCHIP=y + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SCMI=y +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_PHY_XGENE is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y +CONFIG_PHY_ROCKCHIP_DP=y +# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_EMMC=y +# CONFIG_PHY_ROCKCHIP_INNO_COMBPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_HDMI_PHY is not set +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_INNO_USB3=y +# CONFIG_PHY_ROCKCHIP_INNO_VIDEO_COMBO_PHY is not set +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y +CONFIG_PHY_ROCKCHIP_MIPI_RX=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y +CONFIG_PHY_ROCKCHIP_NANENG_EDP=y +# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set +CONFIG_PHY_ROCKCHIP_PCIE=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USB=y +CONFIG_PHY_ROCKCHIP_USBDP=y +# CONFIG_PHY_SAMSUNG_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# CONFIG_HISI_PCIE_PMU is not set +# end of Performance monitor support + +# CONFIG_RAS is not set +# CONFIG_USB4 is not set + +# +# Android +# +CONFIG_ANDROID=y +# CONFIG_ANDROID_BINDER_IPC is not set +# end of Android + +# +# Vendor Hooks +# +# CONFIG_VENDOR_HOOKS is not set +# end of Vendor Hooks + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +CONFIG_TEE=y + +# +# TEE drivers +# +CONFIG_OPTEE=y +CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 +# end of TEE drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# CONFIG_RK_FLASH is not set +# CONFIG_RK_NAND is not set + +# +# Headset device support +# +CONFIG_RK_HEADSET=y +# end of Headset device support + +# +# RKNPU +# +# end of RKNPU +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_SUPPORT_V4=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +CONFIG_VIRTIO_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_OVERLAY_FS_REDIRECT_DIR=y +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +CONFIG_OVERLAY_FS_INDEX=y +CONFIG_OVERLAY_FS_XINO_AUTO=y +CONFIG_OVERLAY_FS_METACOPY=y + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTFS3_FS is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +# CONFIG_HUGETLBFS is not set +CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=y +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UBIFS_FS_ZSTD=y +# CONFIG_UBIFS_ATIME_SUPPORT is not set +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_SECURITY=y +# CONFIG_UBIFS_FS_AUTHENTICATION is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +CONFIG_PSTORE_CONSOLE=y +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +# CONFIG_NFS_V4_1 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_SWAP=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_TRUSTED_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options + +# CONFIG_SECURITY_BOOT_INIT is not set +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_SIMD=y + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECDSA is not set +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +CONFIG_CRYPTO_ZSTD=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set +CONFIG_CRYPTO_DEV_ROCKCHIP=y +# CONFIG_CRYPTO_DEV_VIRTIO is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set +# CONFIG_PGP_LIBRARY is not set +# CONFIG_PGP_KEY_PARSER is not set +# CONFIG_PGP_PRELOAD is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# CONFIG_PGP_PRELOAD_PUBLIC_KEYS is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_INDIRECT_PIO is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +# CONFIG_DMA_PERNUMA_CMA is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=1 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_BTF is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_OPTIMIZE_INLINING is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set + +# +# ARM64 NMI watchdog configuration +# +# end of ARM64 NMI watchdog configuration + +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +CONFIG_DEBUG_CREDENTIALS=y + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +# CONFIG_FUNCTION_PROFILER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_OSNOISE_TRACER is not set +# CONFIG_TIMERLAT_TRACER is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_UPROBE_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_SYNTH_EVENTS is not set +# CONFIG_HIST_TRIGGERS is not set +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_IO_STRICT_DEVMEM is not set + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +CONFIG_LKDTM=y +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/patches/0001-roc-rk3588s-pc-dts.patch b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/patches/0001-roc-rk3588s-pc-dts.patch new file mode 100644 index 00000000000..74242304d6c --- /dev/null +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/files/patches/0001-roc-rk3588s-pc-dts.patch @@ -0,0 +1,7397 @@ +From 5f93355e3198a0d3671d207ef049344143d87e6f Mon Sep 17 00:00:00 2001 +From: guningbo +Date: Tue, 19 Mar 2024 09:41:51 +0000 +Subject: [PATCH] =?UTF-8?q?roc-rk3588s-pc=20=E8=AE=BE=E5=A4=87=E6=A0=91?= +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +--- + .../boot/dts/rockchip/roc-rk3588s-pc.dts | 7370 +++++++++++++++++ + roc-rk3588s-pc.dts | 0 + 2 files changed, 7370 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts + create mode 100644 roc-rk3588s-pc.dts + +diff --git a/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts b/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts +new file mode 100644 +index 000000000..eb0f13588 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/roc-rk3588s-pc.dts +@@ -0,0 +1,7370 @@ ++/dts-v1/; ++ ++/ { ++ compatible = "rockchip,roc-rk3588s-pc\0rockchip,rk3588"; ++ interrupt-parent = <0x01>; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ model = "Firefly ROC-RK3588S-PC HDMI(Linux)"; ++ ++ aliases { ++ csi2dcphy0 = "/csi2-dcphy0"; ++ csi2dcphy1 = "/csi2-dcphy1"; ++ csi2dphy0 = "/csi2-dphy0"; ++ csi2dphy1 = "/csi2-dphy1"; ++ csi2dphy2 = "/csi2-dphy2"; ++ dsi0 = "/dsi@fde20000"; ++ dsi1 = "/dsi@fde30000"; ++ ethernet0 = "/ethernet@fe1b0000"; ++ ethernet1 = "/ethernet@fe1c0000"; ++ gpio0 = "/pinctrl/gpio@fd8a0000"; ++ gpio1 = "/pinctrl/gpio@fec20000"; ++ gpio2 = "/pinctrl/gpio@fec30000"; ++ gpio3 = "/pinctrl/gpio@fec40000"; ++ gpio4 = "/pinctrl/gpio@fec50000"; ++ i2c0 = "/i2c@fd880000"; ++ i2c1 = "/i2c@fea90000"; ++ i2c2 = "/i2c@feaa0000"; ++ i2c3 = "/i2c@feab0000"; ++ i2c4 = "/i2c@feac0000"; ++ i2c5 = "/i2c@fead0000"; ++ i2c6 = "/i2c@fec80000"; ++ i2c7 = "/i2c@fec90000"; ++ i2c8 = "/i2c@feca0000"; ++ rkcif_mipi_lvds0 = "/rkcif-mipi-lvds"; ++ rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; ++ rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; ++ rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; ++ rkvenc0 = "/rkvenc-core@fdbd0000"; ++ rkvenc1 = "/rkvenc-core@fdbe0000"; ++ jpege0 = "/jpege-core@fdba0000"; ++ jpege1 = "/jpege-core@fdba4000"; ++ jpege2 = "/jpege-core@fdba8000"; ++ jpege3 = "/jpege-core@fdbac000"; ++ serial0 = "/serial@fd890000"; ++ serial1 = "/serial@feb40000"; ++ serial2 = "/serial@feb50000"; ++ serial3 = "/serial@feb60000"; ++ serial4 = "/serial@feb70000"; ++ serial5 = "/serial@feb80000"; ++ serial6 = "/serial@feb90000"; ++ serial7 = "/serial@feba0000"; ++ serial8 = "/serial@febb0000"; ++ serial9 = "/serial@febc0000"; ++ spi0 = "/spi@feb00000"; ++ spi1 = "/spi@feb10000"; ++ spi2 = "/spi@feb20000"; ++ spi3 = "/spi@feb30000"; ++ spi4 = "/spi@fecb0000"; ++ spi5 = "/spi@fe2b0000"; ++ }; ++ ++ clocks { ++ compatible = "simple-bus"; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ ++ spll { ++ compatible = "fixed-clock"; ++ #clock-cells = <0x00>; ++ clock-frequency = <0x29d7ab80>; ++ clock-output-names = "spll"; ++ }; ++ ++ xin32k { ++ compatible = "fixed-clock"; ++ #clock-cells = <0x00>; ++ clock-frequency = <0x8000>; ++ clock-output-names = "xin32k"; ++ }; ++ ++ xin24m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0x00>; ++ clock-frequency = <0x16e3600>; ++ clock-output-names = "xin24m"; ++ }; ++ ++ hclk_vo1@fd7c08ec { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08ec 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x264>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ phandle = <0x05>; ++ }; ++ ++ aclk_vdpu_low_pre@fd7c08b0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08b0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1bc>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_vo0@fd7c08dc { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08dc 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x26d>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ phandle = <0x04>; ++ }; ++ ++ hclk_usb@fd7c08a8 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a8 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x264>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_nvm@fd7c087c { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c087c 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x141>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ phandle = <0x03>; ++ }; ++ ++ aclk_usb@fd7c08a8 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a8 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x263>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_isp1_pre@fd7c0868 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c0868 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1e1>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_isp1_pre@fd7c0868 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c0868 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1e0>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_rkvdec0_pre@fd7c08a0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1bc>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_rkvdec0_pre@fd7c08a0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1be>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_rkvdec1_pre@fd7c08a4 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a4 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1bc>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_rkvdec1_pre@fd7c08a4 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08a4 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1be>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_jpeg_decoder_pre@fd7c08b0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08b0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1bc>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_rkvenc1_pre@fd7c08c0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08c0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1c5>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_rkvenc1_pre@fd7c08c0 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08c0 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1c4>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_hdcp0_pre@fd7c08dc { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08dc 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x26c>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_hdcp1_pre@fd7c08ec { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08ec 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x263>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ pclk_av1_pre@fd7c0910 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c0910 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1be>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ aclk_av1_pre@fd7c0910 { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c0910 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x02 0x1bc>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ hclk_sdio_pre@fd7c092c { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c092c 0x00 0x10>; ++ clock-names = "link"; ++ clocks = <0x03>; ++ #power-domain-cells = <0x01>; ++ #clock-cells = <0x00>; ++ }; ++ ++ pclk_vo0_grf@fd7c08dc { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08dc 0x00 0x04>; ++ clocks = <0x04>; ++ clock-names = "link"; ++ #clock-cells = <0x00>; ++ phandle = <0x59>; ++ }; ++ ++ pclk_vo1_grf@fd7c08ec { ++ compatible = "rockchip,rk3588-clock-gate-link"; ++ reg = <0x00 0xfd7c08ec 0x00 0x04>; ++ clocks = <0x05>; ++ clock-names = "link"; ++ #clock-cells = <0x00>; ++ phandle = <0x5a>; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ cpu-map { ++ ++ cluster0 { ++ ++ core0 { ++ cpu = <0x06>; ++ }; ++ ++ core1 { ++ cpu = <0x07>; ++ }; ++ ++ core2 { ++ cpu = <0x08>; ++ }; ++ ++ core3 { ++ cpu = <0x09>; ++ }; ++ }; ++ ++ cluster1 { ++ ++ core0 { ++ cpu = <0x0a>; ++ }; ++ ++ core1 { ++ cpu = <0x0b>; ++ }; ++ }; ++ ++ cluster2 { ++ ++ core0 { ++ cpu = <0x0c>; ++ }; ++ ++ core1 { ++ cpu = <0x0d>; ++ }; ++ }; ++ }; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x00>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x212>; ++ clocks = <0x0e 0x00>; ++ operating-points-v2 = <0x0f>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x80>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x80>; ++ next-level-cache = <0x11>; ++ #cooling-cells = <0x02>; ++ dynamic-power-coefficient = <0x64>; ++ cpu-supply = <0x12>; ++ mem-supply = <0x12>; ++ phandle = <0x06>; ++ }; ++ ++ cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x212>; ++ clocks = <0x0e 0x00>; ++ operating-points-v2 = <0x0f>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x80>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x80>; ++ next-level-cache = <0x13>; ++ phandle = <0x07>; ++ }; ++ ++ cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x212>; ++ clocks = <0x0e 0x00>; ++ operating-points-v2 = <0x0f>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x80>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x80>; ++ next-level-cache = <0x14>; ++ phandle = <0x08>; ++ }; ++ ++ cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a55"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x212>; ++ clocks = <0x0e 0x00>; ++ operating-points-v2 = <0x0f>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x80>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x80>; ++ next-level-cache = <0x15>; ++ phandle = <0x09>; ++ }; ++ ++ cpu@400 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x400>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x400>; ++ clocks = <0x0e 0x02>; ++ operating-points-v2 = <0x16>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x100>; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x100>; ++ next-level-cache = <0x17>; ++ #cooling-cells = <0x02>; ++ dynamic-power-coefficient = <0x12c>; ++ cpu-supply = <0x18>; ++ mem-supply = <0x18>; ++ phandle = <0x0a>; ++ }; ++ ++ cpu@500 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x500>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x400>; ++ clocks = <0x0e 0x02>; ++ operating-points-v2 = <0x16>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x100>; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x100>; ++ next-level-cache = <0x19>; ++ phandle = <0x0b>; ++ }; ++ ++ cpu@600 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x600>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x400>; ++ clocks = <0x0e 0x03>; ++ operating-points-v2 = <0x1a>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x100>; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x100>; ++ next-level-cache = <0x1b>; ++ #cooling-cells = <0x02>; ++ dynamic-power-coefficient = <0x12c>; ++ cpu-supply = <0x1c>; ++ mem-supply = <0x1c>; ++ phandle = <0x0c>; ++ }; ++ ++ cpu@700 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x700>; ++ enable-method = "psci"; ++ capacity-dmips-mhz = <0x400>; ++ clocks = <0x0e 0x03>; ++ operating-points-v2 = <0x1a>; ++ cpu-idle-states = <0x10>; ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <0x40>; ++ i-cache-sets = <0x100>; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <0x40>; ++ d-cache-sets = <0x100>; ++ next-level-cache = <0x1d>; ++ phandle = <0x0d>; ++ }; ++ ++ idle-states { ++ entry-method = "psci"; ++ ++ cpu-sleep { ++ compatible = "arm,idle-state"; ++ local-timer-stop; ++ arm,psci-suspend-param = <0x10000>; ++ entry-latency-us = <0x64>; ++ exit-latency-us = <0x78>; ++ min-residency-us = <0x3e8>; ++ phandle = <0x10>; ++ }; ++ }; ++ ++ l2-cache-l0 { ++ compatible = "cache"; ++ cache-size = <0x20000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x200>; ++ next-level-cache = <0x1e>; ++ phandle = <0x11>; ++ }; ++ ++ l2-cache-l1 { ++ compatible = "cache"; ++ cache-size = <0x20000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x200>; ++ next-level-cache = <0x1e>; ++ phandle = <0x13>; ++ }; ++ ++ l2-cache-l2 { ++ compatible = "cache"; ++ cache-size = <0x20000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x200>; ++ next-level-cache = <0x1e>; ++ phandle = <0x14>; ++ }; ++ ++ l2-cache-l3 { ++ compatible = "cache"; ++ cache-size = <0x20000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x200>; ++ next-level-cache = <0x1e>; ++ phandle = <0x15>; ++ }; ++ ++ l2-cache-b0 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x400>; ++ next-level-cache = <0x1e>; ++ phandle = <0x17>; ++ }; ++ ++ l2-cache-b1 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x400>; ++ next-level-cache = <0x1e>; ++ phandle = <0x19>; ++ }; ++ ++ l2-cache-b2 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x400>; ++ next-level-cache = <0x1e>; ++ phandle = <0x1b>; ++ }; ++ ++ l2-cache-b3 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x400>; ++ next-level-cache = <0x1e>; ++ phandle = <0x1d>; ++ }; ++ ++ l3-cache { ++ compatible = "cache"; ++ cache-size = <0x300000>; ++ cache-line-size = <0x40>; ++ cache-sets = <0x1000>; ++ phandle = <0x1e>; ++ }; ++ }; ++ ++ cluster0-opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ nvmem-cells = <0x1f>; ++ nvmem-cell-names = "leakage"; ++ rockchip,supported-hw; ++ rockchip,opp-shared-dsu; ++ rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>; ++ rockchip,pvtm-pvtpll; ++ rockchip,pvtm-offset = <0x64>; ++ rockchip,pvtm-sample-time = <0x44c>; ++ rockchip,pvtm-freq = <0x159b40>; ++ rockchip,pvtm-volt = <0xb71b0>; ++ rockchip,pvtm-ref-temp = <0x19>; ++ rockchip,pvtm-temp-prop = <0xf4 0xf4>; ++ rockchip,pvtm-thermal-zone = "soc-thermal"; ++ rockchip,grf = <0x20>; ++ rockchip,reboot-freq = <0x159b40>; ++ rockchip,temp-hysteresis = <0x1388>; ++ rockchip,low-temp = <0x2710>; ++ rockchip,low-temp-min-volt = <0xb71b0>; ++ rockchip,high-temp = <0x14c08>; ++ rockchip,high-temp-max-freq = <0x188940>; ++ phandle = <0x0f>; ++ ++ opp-408000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x18519600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-600000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x23c34600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-816000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x30a32c00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1008000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x3c14dc00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1200000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x47868c00>; ++ opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; ++ opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; ++ opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; ++ opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1416000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x54667200>; ++ opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; ++ opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; ++ opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; ++ opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; ++ opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; ++ opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; ++ opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ opp-suspend; ++ }; ++ ++ opp-1608000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x5fd82200>; ++ opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; ++ opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; ++ opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; ++ opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; ++ opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; ++ opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; ++ opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1800000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x6b49d200>; ++ opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; ++ opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; ++ opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; ++ opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; ++ opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; ++ opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; ++ opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ }; ++ ++ cluster1-opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ nvmem-cells = <0x21>; ++ nvmem-cell-names = "leakage"; ++ rockchip,supported-hw; ++ rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; ++ rockchip,pvtm-pvtpll; ++ rockchip,pvtm-offset = <0x18>; ++ rockchip,pvtm-sample-time = <0x44c>; ++ rockchip,pvtm-freq = <0x188940>; ++ rockchip,pvtm-volt = <0xb71b0>; ++ rockchip,pvtm-ref-temp = <0x19>; ++ rockchip,pvtm-temp-prop = <0x10e 0x10e>; ++ rockchip,pvtm-thermal-zone = "soc-thermal"; ++ rockchip,pvtm-low-len-sel = <0x03>; ++ rockchip,grf = <0x22>; ++ volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; ++ low-volt-mem-read-margin = <0x04>; ++ intermediate-threshold-freq = <0xf6180>; ++ rockchip,idle-threshold-freq = <0x21b100>; ++ rockchip,reboot-freq = <0x1b7740>; ++ rockchip,temp-hysteresis = <0x1388>; ++ rockchip,low-temp = <0x2710>; ++ rockchip,low-temp-min-volt = <0xb71b0>; ++ rockchip,high-temp = <0x14c08>; ++ rockchip,high-temp-max-freq = <0x21b100>; ++ phandle = <0x16>; ++ ++ opp-408000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x18519600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ opp-suspend; ++ }; ++ ++ opp-600000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x23c34600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-816000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x30a32c00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1008000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x3c14dc00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1200000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x47868c00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1416000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x54667200>; ++ opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; ++ opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; ++ opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; ++ opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1608000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x5fd82200>; ++ opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; ++ opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; ++ opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; ++ opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; ++ opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; ++ opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1800000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x6b49d200>; ++ opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; ++ opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; ++ opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; ++ opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; ++ opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; ++ opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; ++ opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; ++ opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2016000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x7829b800>; ++ opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; ++ opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; ++ opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; ++ opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; ++ opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; ++ opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; ++ opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; ++ opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2208000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x839b6800>; ++ opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; ++ opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; ++ opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; ++ opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; ++ opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; ++ opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; ++ opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; ++ opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2256000000 { ++ opp-supported-hw = <0xff 0x13>; ++ opp-hz = <0x00 0x8677d400>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2304000000 { ++ opp-supported-hw = <0xff 0x24>; ++ opp-hz = <0x00 0x89544000>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2352000000 { ++ opp-supported-hw = <0xff 0x48>; ++ opp-hz = <0x00 0x8c30ac00>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2400000000 { ++ opp-supported-hw = <0xff 0x80>; ++ opp-hz = <0x00 0x8f0d1800>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ }; ++ ++ cluster2-opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ nvmem-cells = <0x23>; ++ nvmem-cell-names = "leakage"; ++ rockchip,supported-hw; ++ rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; ++ rockchip,pvtm-pvtpll; ++ rockchip,pvtm-offset = <0x18>; ++ rockchip,pvtm-sample-time = <0x44c>; ++ rockchip,pvtm-freq = <0x188940>; ++ rockchip,pvtm-volt = <0xb71b0>; ++ rockchip,pvtm-ref-temp = <0x19>; ++ rockchip,pvtm-temp-prop = <0x10e 0x10e>; ++ rockchip,pvtm-thermal-zone = "soc-thermal"; ++ rockchip,pvtm-low-len-sel = <0x03>; ++ rockchip,grf = <0x24>; ++ volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; ++ low-volt-mem-read-margin = <0x04>; ++ intermediate-threshold-freq = <0xf6180>; ++ rockchip,idle-threshold-freq = <0x21b100>; ++ rockchip,reboot-freq = <0x1b7740>; ++ rockchip,temp-hysteresis = <0x1388>; ++ rockchip,low-temp = <0x2710>; ++ rockchip,low-temp-min-volt = <0xb71b0>; ++ rockchip,high-temp = <0x14c08>; ++ rockchip,high-temp-max-freq = <0x21b100>; ++ phandle = <0x1a>; ++ ++ opp-408000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x18519600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ opp-suspend; ++ }; ++ ++ opp-600000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x23c34600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-816000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x30a32c00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1008000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x3c14dc00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1200000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x47868c00>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1416000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x54667200>; ++ opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; ++ opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; ++ opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; ++ opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1608000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x5fd82200>; ++ opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; ++ opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; ++ opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; ++ opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; ++ opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; ++ opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-1800000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x6b49d200>; ++ opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; ++ opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; ++ opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; ++ opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; ++ opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; ++ opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; ++ opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; ++ opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2016000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x7829b800>; ++ opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; ++ opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; ++ opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; ++ opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; ++ opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; ++ opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; ++ opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; ++ opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2208000000 { ++ opp-supported-hw = <0xff 0xffff>; ++ opp-hz = <0x00 0x839b6800>; ++ opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; ++ opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; ++ opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; ++ opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; ++ opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; ++ opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2256000000 { ++ opp-supported-hw = <0xff 0x13>; ++ opp-hz = <0x00 0x8677d400>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2304000000 { ++ opp-supported-hw = <0xff 0x24>; ++ opp-hz = <0x00 0x89544000>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2352000000 { ++ opp-supported-hw = <0xff 0x48>; ++ opp-hz = <0x00 0x8c30ac00>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ ++ opp-2400000000 { ++ opp-supported-hw = <0xff 0x80>; ++ opp-hz = <0x00 0x8f0d1800>; ++ opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; ++ clock-latency-ns = <0x9c40>; ++ }; ++ }; ++ ++ arm-pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = <0x01 0x07 0x08>; ++ interrupt-affinity = <0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d>; ++ }; ++ ++ cpuinfo { ++ compatible = "rockchip,cpuinfo"; ++ nvmem-cells = <0x25 0x26 0x27>; ++ nvmem-cell-names = "id\0cpu-version\0cpu-code"; ++ }; ++ ++ csi2-dcphy0 { ++ compatible = "rockchip,rk3588-csi2-dcphy"; ++ phys = <0x28>; ++ phy-names = "dcphy"; ++ status = "disabled"; ++ }; ++ ++ csi2-dcphy1 { ++ compatible = "rockchip,rk3588-csi2-dcphy"; ++ phys = <0x29>; ++ phy-names = "dcphy"; ++ status = "disabled"; ++ }; ++ ++ csi2-dphy0 { ++ compatible = "rockchip,rk3568-csi2-dphy"; ++ rockchip,hw = <0x2a>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0x2b>; ++ data-lanes = <0x01 0x02 0x03 0x04>; ++ phandle = <0x155>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <0x01>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0x2c>; ++ phandle = <0xb4>; ++ }; ++ }; ++ }; ++ }; ++ ++ csi2-dphy1 { ++ compatible = "rockchip,rk3568-csi2-dphy"; ++ rockchip,hw = <0x2a>; ++ status = "disabled"; ++ }; ++ ++ csi2-dphy2 { ++ compatible = "rockchip,rk3568-csi2-dphy"; ++ rockchip,hw = <0x2a>; ++ status = "disabled"; ++ }; ++ ++ display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <0x2d>; ++ memory-region = <0x2e>; ++ memory-region-names = "drm-logo"; ++ ++ route { ++ ++ route-dp0 { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x2f>; ++ }; ++ ++ route-dsi0 { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x30>; ++ }; ++ ++ route-dsi1 { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x31>; ++ }; ++ ++ route-edp0 { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x32>; ++ }; ++ ++ route-edp1 { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ }; ++ ++ route-hdmi0 { ++ status = "okay"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x33>; ++ }; ++ ++ route-rgb { ++ status = "disabled"; ++ logo,uboot = "logo.bmp"; ++ logo,kernel = "logo_kernel.bmp"; ++ logo,mode = "center"; ++ charge_logo,mode = "center"; ++ connect = <0x34>; ++ }; ++ }; ++ }; ++ ++ dmc { ++ compatible = "rockchip,rk3588-dmc"; ++ interrupts = <0x00 0x49 0x04>; ++ interrupt-names = "complete"; ++ devfreq-events = <0x35>; ++ clocks = <0x0e 0x04>; ++ clock-names = "dmc_clk"; ++ operating-points-v2 = <0x36>; ++ upthreshold = <0x28>; ++ downdifferential = <0x14>; ++ system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>; ++ auto-freq-en = <0x01>; ++ status = "okay"; ++ center-supply = <0x37>; ++ }; ++ ++ dmc-opp-table { ++ compatible = "operating-points-v2"; ++ nvmem-cells = <0x38>; ++ nvmem-cell-names = "leakage"; ++ phandle = <0x36>; ++ ++ opp-528000000 { ++ opp-hz = <0x00 0x1f78a400>; ++ opp-microvolt = <0xa4cb8>; ++ }; ++ ++ opp-1068000000 { ++ opp-hz = <0x00 0x3fa86300>; ++ opp-microvolt = <0xb1008>; ++ }; ++ ++ opp-1560000000 { ++ opp-hz = <0x00 0x5cfbb600>; ++ opp-microvolt = <0xc3500>; ++ }; ++ ++ opp-2750000000 { ++ opp-hz = <0x00 0xa3e9ab80>; ++ opp-microvolt = <0xcf850>; ++ }; ++ }; ++ ++ firmware { ++ ++ scmi { ++ compatible = "arm,scmi-smc"; ++ shmem = <0x39>; ++ arm,smc-id = <0x82000010>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ protocol@14 { ++ reg = <0x14>; ++ #clock-cells = <0x01>; ++ assigned-clocks = <0x0e 0x00 0x0e 0x02 0x0e 0x03>; ++ assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; ++ phandle = <0x0e>; ++ }; ++ ++ protocol@16 { ++ reg = <0x16>; ++ #reset-cells = <0x01>; ++ phandle = <0xf4>; ++ }; ++ }; ++ ++ sdei { ++ compatible = "arm,sdei-1.0"; ++ method = "smc"; ++ }; ++ ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; ++ ++ jpege-ccu { ++ compatible = "rockchip,vpu-encoder-v2-ccu"; ++ status = "okay"; ++ phandle = <0xa0>; ++ }; ++ ++ mpp-srv { ++ compatible = "rockchip,mpp-service"; ++ rockchip,taskqueue-count = <0x0c>; ++ status = "okay"; ++ phandle = <0x9b>; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ rkcif-dvp { ++ compatible = "rockchip,rkcif-dvp"; ++ rockchip,hw = <0x3a>; ++ iommus = <0x3b>; ++ status = "disabled"; ++ phandle = <0x3c>; ++ }; ++ ++ rkcif-dvp-sditf { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3c>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds { ++ compatible = "rockchip,rkcif-mipi-lvds"; ++ rockchip,hw = <0x3a>; ++ iommus = <0x3b>; ++ status = "disabled"; ++ phandle = <0x3d>; ++ }; ++ ++ rkcif-mipi-lvds-sditf { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3d>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds-sditf-vir1 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3d>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds-sditf-vir2 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3d>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds-sditf-vir3 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3d>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds1 { ++ compatible = "rockchip,rkcif-mipi-lvds"; ++ rockchip,hw = <0x3a>; ++ iommus = <0x3b>; ++ status = "disabled"; ++ phandle = <0x3e>; ++ }; ++ ++ rkcif-mipi-lvds1-sditf { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3e>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds1-sditf-vir1 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3e>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds1-sditf-vir2 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3e>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds1-sditf-vir3 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x3e>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds2 { ++ compatible = "rockchip,rkcif-mipi-lvds"; ++ rockchip,hw = <0x3a>; ++ iommus = <0x3b>; ++ status = "okay"; ++ phandle = <0x40>; ++ ++ port { ++ ++ endpoint { ++ remote-endpoint = <0x3f>; ++ phandle = <0xb5>; ++ }; ++ }; ++ }; ++ ++ rkcif-mipi-lvds2-sditf { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x40>; ++ status = "disabled"; ++ ++ port { ++ ++ endpoint { ++ remote-endpoint = <0x41>; ++ phandle = <0x44>; ++ }; ++ }; ++ }; ++ ++ rkcif-mipi-lvds2-sditf-vir1 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x40>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds2-sditf-vir2 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x40>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds2-sditf-vir3 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x40>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds3 { ++ compatible = "rockchip,rkcif-mipi-lvds"; ++ rockchip,hw = <0x3a>; ++ iommus = <0x3b>; ++ status = "disabled"; ++ phandle = <0x42>; ++ }; ++ ++ rkcif-mipi-lvds3-sditf { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x42>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds3-sditf-vir1 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x42>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds3-sditf-vir2 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x42>; ++ status = "disabled"; ++ }; ++ ++ rkcif-mipi-lvds3-sditf-vir3 { ++ compatible = "rockchip,rkcif-sditf"; ++ rockchip,cif = <0x42>; ++ status = "disabled"; ++ }; ++ ++ rkisp0-vir0 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x43>; ++ status = "disabled"; ++ ++ port { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0x44>; ++ phandle = <0x41>; ++ }; ++ }; ++ }; ++ ++ rkisp0-vir1 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x43>; ++ status = "disabled"; ++ }; ++ ++ rkisp0-vir2 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x43>; ++ status = "disabled"; ++ }; ++ ++ rkisp0-vir3 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x43>; ++ status = "disabled"; ++ }; ++ ++ rkisp1-vir0 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x45>; ++ status = "disabled"; ++ }; ++ ++ rkisp1-vir1 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x45>; ++ status = "disabled"; ++ }; ++ ++ rkisp1-vir2 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x45>; ++ status = "disabled"; ++ }; ++ ++ rkisp1-vir3 { ++ compatible = "rockchip,rkisp-vir"; ++ rockchip,hw = <0x45>; ++ status = "disabled"; ++ }; ++ ++ rkispp0-vir0 { ++ compatible = "rockchip,rk3588-rkispp-vir"; ++ rockchip,hw = <0x46>; ++ status = "disabled"; ++ }; ++ ++ rkispp1-vir0 { ++ compatible = "rockchip,rk3588-rkispp-vir"; ++ rockchip,hw = <0x47>; ++ status = "disabled"; ++ }; ++ ++ rkvenc-ccu { ++ compatible = "rockchip,rkv-encoder-v2-ccu"; ++ status = "okay"; ++ phandle = <0xa6>; ++ }; ++ ++ rockchip-suspend { ++ compatible = "rockchip,pm-rk3588"; ++ status = "okay"; ++ rockchip,sleep-debug-en = <0x01>; ++ rockchip,sleep-mode-config = <0x5000604>; ++ rockchip,wakeup-config = <0x100>; ++ }; ++ ++ rockchip-system-monitor { ++ compatible = "rockchip,system-monitor"; ++ rockchip,thermal-zone = "soc-thermal"; ++ }; ++ ++ thermal-zones { ++ ++ soc-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ sustainable-power = <0x834>; ++ thermal-sensors = <0x48 0x00>; ++ ++ trips { ++ ++ trip-point-0 { ++ temperature = <0x124f8>; ++ hysteresis = <0x7d0>; ++ type = "passive"; ++ }; ++ ++ trip-point-1 { ++ temperature = <0x14c08>; ++ hysteresis = <0x7d0>; ++ type = "passive"; ++ phandle = <0x49>; ++ }; ++ ++ soc-crit { ++ temperature = <0x1c138>; ++ hysteresis = <0x7d0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ ++ map0 { ++ trip = <0x49>; ++ cooling-device = <0x06 0xffffffff 0xffffffff>; ++ contribution = <0x400>; ++ }; ++ ++ map1 { ++ trip = <0x49>; ++ cooling-device = <0x0a 0xffffffff 0xffffffff>; ++ contribution = <0x400>; ++ }; ++ ++ map2 { ++ trip = <0x49>; ++ cooling-device = <0x0c 0xffffffff 0xffffffff>; ++ contribution = <0x400>; ++ }; ++ ++ map3 { ++ trip = <0x49>; ++ cooling-device = <0x4a 0xffffffff 0xffffffff>; ++ contribution = <0x400>; ++ }; ++ }; ++ }; ++ ++ bigcore0-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x01>; ++ }; ++ ++ bigcore1-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x02>; ++ }; ++ ++ littlecore-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x03>; ++ }; ++ ++ center-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x04>; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x05>; ++ }; ++ ++ npu-thermal { ++ polling-delay-passive = <0x14>; ++ polling-delay = <0x3e8>; ++ thermal-sensors = <0x48 0x06>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; ++ }; ++ ++ sram@10f000 { ++ compatible = "mmio-sram"; ++ reg = <0x00 0x10f000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ ranges = <0x00 0x00 0x10f000 0x100>; ++ ++ sram@0 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x00 0x100>; ++ phandle = <0x39>; ++ }; ++ }; ++ ++ gpu@fb000000 { ++ compatible = "arm,mali-bifrost"; ++ reg = <0x00 0xfb000000 0x00 0x200000>; ++ interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>; ++ interrupt-names = "GPU\0MMU\0JOB"; ++ clocks = <0x0e 0x05 0x02 0x115 0x02 0x116 0x02 0x114>; ++ clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu"; ++ assigned-clocks = <0x0e 0x05>; ++ assigned-clock-rates = <0xbebc200>; ++ power-domains = <0x4b 0x0c>; ++ operating-points-v2 = <0x4c>; ++ #cooling-cells = <0x02>; ++ dynamic-power-coefficient = <0xba6>; ++ upthreshold = <0x1e>; ++ downdifferential = <0x0a>; ++ status = "okay"; ++ mali-supply = <0x4d>; ++ mem-supply = <0x4d>; ++ phandle = <0x4a>; ++ }; ++ ++ gpu-opp-table { ++ compatible = "operating-points-v2"; ++ nvmem-cells = <0x4e>; ++ nvmem-cell-names = "leakage"; ++ rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; ++ rockchip,pvtm-pvtpll; ++ rockchip,pvtm-offset = <0x1c>; ++ rockchip,pvtm-sample-time = <0x44c>; ++ rockchip,pvtm-freq = <0xc3500>; ++ rockchip,pvtm-volt = <0xb71b0>; ++ rockchip,pvtm-ref-temp = <0x19>; ++ rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>; ++ rockchip,pvtm-thermal-zone = "gpu-thermal"; ++ clocks = <0x02 0x114>; ++ clock-names = "clk"; ++ rockchip,grf = <0x4f>; ++ volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; ++ low-volt-mem-read-margin = <0x04>; ++ intermediate-threshold-freq = <0x61a80>; ++ rockchip,temp-hysteresis = <0x1388>; ++ rockchip,low-temp = <0x2710>; ++ rockchip,low-temp-min-volt = <0xb71b0>; ++ rockchip,high-temp = <0x14c08>; ++ rockchip,high-temp-max-freq = <0xc3500>; ++ phandle = <0x4c>; ++ ++ opp-300000000 { ++ opp-hz = <0x00 0x11e1a300>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = <0x00 0x17d78400>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-500000000 { ++ opp-hz = <0x00 0x1dcd6500>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = <0x00 0x23c34600>; ++ opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-700000000 { ++ opp-hz = <0x00 0x29b92700>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = <0x00 0x2faf0800>; ++ opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; ++ opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; ++ opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; ++ opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; ++ opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ }; ++ ++ opp-900000000 { ++ opp-hz = <0x00 0x35a4e900>; ++ opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; ++ opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; ++ opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; ++ opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; ++ opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = <0x00 0x3b9aca00>; ++ opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; ++ opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; ++ opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; ++ opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; ++ opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; ++ }; ++ }; ++ ++ usbdrd3_0 { ++ compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; ++ clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>; ++ clock-names = "ref\0suspend\0bus"; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ status = "okay"; ++ ++ usb@fc000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x00 0xfc000000 0x00 0x400000>; ++ interrupts = <0x00 0xdc 0x04>; ++ power-domains = <0x4b 0x1f>; ++ resets = <0x02 0x2a4>; ++ reset-names = "usb3-otg"; ++ dr_mode = "otg"; ++ phys = <0x50 0x51>; ++ phy-names = "usb2-phy\0usb3-phy"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ quirk-skip-phy-init; ++ status = "okay"; ++ usb-role-switch; ++ ++ port { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0x52>; ++ phandle = <0x121>; ++ }; ++ }; ++ }; ++ }; ++ ++ usb@fc800000 { ++ compatible = "generic-ehci"; ++ reg = <0x00 0xfc800000 0x00 0x40000>; ++ interrupts = <0x00 0xd7 0x04>; ++ clocks = <0x02 0x19d 0x02 0x19e 0x53>; ++ clock-names = "usbhost\0arbiter\0utmi"; ++ phys = <0x54>; ++ phy-names = "usb2-phy"; ++ power-domains = <0x4b 0x1f>; ++ status = "okay"; ++ }; ++ ++ usb@fc840000 { ++ compatible = "generic-ohci"; ++ reg = <0x00 0xfc840000 0x00 0x40000>; ++ interrupts = <0x00 0xd8 0x04>; ++ clocks = <0x02 0x19d 0x02 0x19e 0x53>; ++ clock-names = "usbhost\0arbiter\0utmi"; ++ phys = <0x54>; ++ phy-names = "usb2-phy"; ++ power-domains = <0x4b 0x1f>; ++ status = "okay"; ++ }; ++ ++ usb@fc880000 { ++ compatible = "generic-ehci"; ++ reg = <0x00 0xfc880000 0x00 0x40000>; ++ interrupts = <0x00 0xda 0x04>; ++ clocks = <0x02 0x19f 0x02 0x1a0 0x55>; ++ clock-names = "usbhost\0arbiter\0utmi"; ++ phys = <0x56>; ++ phy-names = "usb2-phy"; ++ power-domains = <0x4b 0x1f>; ++ status = "okay"; ++ }; ++ ++ usb@fc8c0000 { ++ compatible = "generic-ohci"; ++ reg = <0x00 0xfc8c0000 0x00 0x40000>; ++ interrupts = <0x00 0xdb 0x04>; ++ clocks = <0x02 0x19f 0x02 0x1a0 0x55>; ++ clock-names = "usbhost\0arbiter\0utmi"; ++ phys = <0x56>; ++ phy-names = "usb2-phy"; ++ power-domains = <0x4b 0x1f>; ++ status = "okay"; ++ }; ++ ++ iommu@fc900000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x00 0xfc900000 0x00 0x200000>; ++ interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>; ++ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; ++ #iommu-cells = <0x01>; ++ status = "disabled"; ++ }; ++ ++ iommu@fcb00000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x00 0xfcb00000 0x00 0x200000>; ++ interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>; ++ interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; ++ #iommu-cells = <0x01>; ++ status = "disabled"; ++ }; ++ ++ usbhost3_0 { ++ compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; ++ clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>; ++ clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe"; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ status = "okay"; ++ ++ usb@fcd00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x00 0xfcd00000 0x00 0x400000>; ++ interrupts = <0x00 0xde 0x04>; ++ resets = <0x02 0x237>; ++ reset-names = "usb3-host"; ++ dr_mode = "host"; ++ phys = <0x57 0x04>; ++ phy-names = "usb3-phy"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "okay"; ++ }; ++ }; ++ ++ syscon@fd588000 { ++ compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd588000 0x00 0x2000>; ++ ++ reboot-mode { ++ compatible = "syscon-reboot-mode"; ++ offset = <0x80>; ++ mode-bootloader = <0x5242c301>; ++ mode-charge = <0x5242c30b>; ++ mode-fastboot = <0x5242c309>; ++ mode-loader = <0x5242c301>; ++ mode-normal = <0x5242c300>; ++ mode-recovery = <0x5242c303>; ++ mode-ums = <0x5242c30c>; ++ mode-panic = <0x5242c307>; ++ mode-watchdog = <0x5242c308>; ++ }; ++ }; ++ ++ syscon@fd58a000 { ++ compatible = "rockchip,rk3588-pmu1-grf\0syscon"; ++ reg = <0x00 0xfd58a000 0x00 0x2000>; ++ phandle = <0xda>; ++ }; ++ ++ syscon@fd58c000 { ++ compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd58c000 0x00 0x1000>; ++ phandle = <0xb3>; ++ ++ rgb { ++ compatible = "rockchip,rk3588-rgb"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x58>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0x34>; ++ status = "disabled"; ++ phandle = <0xc8>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ syscon@fd590000 { ++ compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; ++ reg = <0x00 0xfd590000 0x00 0x100>; ++ phandle = <0x22>; ++ }; ++ ++ syscon@fd592000 { ++ compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; ++ reg = <0x00 0xfd592000 0x00 0x100>; ++ phandle = <0x24>; ++ }; ++ ++ syscon@fd594000 { ++ compatible = "rockchip,rk3588-litcore-grf\0syscon"; ++ reg = <0x00 0xfd594000 0x00 0x100>; ++ phandle = <0x20>; ++ }; ++ ++ syscon@fd598000 { ++ compatible = "rockchip,rk3588-dsu-grf\0syscon"; ++ reg = <0x00 0xfd598000 0x00 0x100>; ++ }; ++ ++ syscon@fd5a0000 { ++ compatible = "rockchip,rk3588-gpu-grf\0syscon"; ++ reg = <0x00 0xfd5a0000 0x00 0x100>; ++ phandle = <0x4f>; ++ }; ++ ++ syscon@fd5a2000 { ++ compatible = "rockchip,rk3588-npu-grf\0syscon"; ++ reg = <0x00 0xfd5a2000 0x00 0x100>; ++ phandle = <0x99>; ++ }; ++ ++ syscon@fd5a4000 { ++ compatible = "rockchip,rk3588-vop-grf\0syscon"; ++ reg = <0x00 0xfd5a4000 0x00 0x2000>; ++ phandle = <0xb8>; ++ }; ++ ++ syscon@fd5a6000 { ++ compatible = "rockchip,rk3588-vo-grf\0syscon"; ++ reg = <0x00 0xfd5a6000 0x00 0x2000>; ++ clocks = <0x59>; ++ phandle = <0x15d>; ++ }; ++ ++ syscon@fd5a8000 { ++ compatible = "rockchip,rk3588-vo-grf\0syscon"; ++ reg = <0x00 0xfd5a8000 0x00 0x100>; ++ clocks = <0x5a>; ++ phandle = <0xb9>; ++ }; ++ ++ syscon@fd5ac000 { ++ compatible = "rockchip,rk3588-usb-grf\0syscon"; ++ reg = <0x00 0xfd5ac000 0x00 0x4000>; ++ phandle = <0x5b>; ++ }; ++ ++ syscon@fd5b0000 { ++ compatible = "rockchip,rk3588-php-grf\0syscon"; ++ reg = <0x00 0xfd5b0000 0x00 0x1000>; ++ phandle = <0x5d>; ++ }; ++ ++ syscon@fd5b4000 { ++ compatible = "rockchip,mipi-dphy-grf\0syscon"; ++ reg = <0x00 0xfd5b4000 0x00 0x1000>; ++ phandle = <0x163>; ++ }; ++ ++ syscon@fd5b5000 { ++ compatible = "rockchip,mipi-dphy-grf\0syscon"; ++ reg = <0x00 0xfd5b5000 0x00 0x1000>; ++ }; ++ ++ syscon@fd5bc000 { ++ compatible = "rockchip,pipe-phy-grf\0syscon"; ++ reg = <0x00 0xfd5bc000 0x00 0x100>; ++ phandle = <0x164>; ++ }; ++ ++ syscon@fd5c4000 { ++ compatible = "rockchip,pipe-phy-grf\0syscon"; ++ reg = <0x00 0xfd5c4000 0x00 0x100>; ++ phandle = <0x165>; ++ }; ++ ++ syscon@fd5c8000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; ++ reg = <0x00 0xfd5c8000 0x00 0x4000>; ++ phandle = <0x15c>; ++ }; ++ ++ syscon@fd5d0000 { ++ compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd5d0000 0x00 0x4000>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ phandle = <0x15b>; ++ ++ usb2-phy@0 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x00 0x10>; ++ interrupts = <0x00 0x189 0x04>; ++ resets = <0x02 0xc0047 0x02 0x488>; ++ reset-names = "phy\0apb"; ++ clocks = <0x02 0x2b5>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy0"; ++ #clock-cells = <0x00>; ++ rockchip,usbctrl-grf = <0x5b>; ++ status = "okay"; ++ phandle = <0x15e>; ++ ++ otg-port { ++ #phy-cells = <0x00>; ++ status = "okay"; ++ rockchip,typec-vbus-det; ++ phandle = <0x50>; ++ }; ++ }; ++ }; ++ ++ syscon@fd5d8000 { ++ compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd5d8000 0x00 0x4000>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ ++ usb2-phy@8000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x8000 0x10>; ++ interrupts = <0x00 0x187 0x04>; ++ resets = <0x02 0xc0049 0x02 0x48a>; ++ reset-names = "phy\0apb"; ++ clocks = <0x02 0x2b5>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy2"; ++ #clock-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x53>; ++ ++ host-port { ++ #phy-cells = <0x00>; ++ status = "okay"; ++ phy-supply = <0x5c>; ++ phandle = <0x54>; ++ }; ++ }; ++ }; ++ ++ syscon@fd5dc000 { ++ compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd5dc000 0x00 0x4000>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ ++ usb2-phy@c000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0xc000 0x10>; ++ interrupts = <0x00 0x188 0x04>; ++ resets = <0x02 0xc004a 0x02 0x48b>; ++ reset-names = "phy\0apb"; ++ clocks = <0x02 0x2b5>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy3"; ++ #clock-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x55>; ++ ++ host-port { ++ #phy-cells = <0x00>; ++ status = "okay"; ++ phy-supply = <0x5c>; ++ phandle = <0x56>; ++ }; ++ }; ++ }; ++ ++ syscon@fd5e0000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; ++ reg = <0x00 0xfd5e0000 0x00 0x100>; ++ phandle = <0x15a>; ++ }; ++ ++ syscon@fd5e8000 { ++ compatible = "rockchip,mipi-dcphy-grf\0syscon"; ++ reg = <0x00 0xfd5e8000 0x00 0x4000>; ++ phandle = <0x161>; ++ }; ++ ++ syscon@fd5ec000 { ++ compatible = "rockchip,mipi-dcphy-grf\0syscon"; ++ reg = <0x00 0xfd5ec000 0x00 0x4000>; ++ phandle = <0x162>; ++ }; ++ ++ syscon@fd5f0000 { ++ compatible = "rockchip,rk3588-ioc\0syscon"; ++ reg = <0x00 0xfd5f0000 0x00 0x10000>; ++ phandle = <0x166>; ++ }; ++ ++ sram@fd601000 { ++ compatible = "mmio-sram"; ++ reg = <0x00 0xfd601000 0x00 0xef000>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ ranges = <0x00 0x00 0xfd601000 0xef000>; ++ ++ rkvdec-sram@0 { ++ reg = <0x00 0x78000>; ++ phandle = <0xaa>; ++ }; ++ ++ rkvdec-sram@78000 { ++ reg = <0x78000 0x77000>; ++ phandle = <0xac>; ++ }; ++ }; ++ ++ clock-controller@fd7c0000 { ++ compatible = "rockchip,rk3588-cru"; ++ rockchip,grf = <0x5d>; ++ reg = <0x00 0xfd7c0000 0x00 0x5c000>; ++ #clock-cells = <0x01>; ++ #reset-cells = <0x01>; ++ assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x270 0x02 0x7b 0x02 0xec 0x02 0x114>; ++ assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2faf0800 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x2faf0800 0x165a0bc0 0x8f0d180 0xbebc200>; ++ phandle = <0x02>; ++ }; ++ ++ i2c@fd880000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfd880000 0x00 0x1000>; ++ clocks = <0x02 0x287 0x02 0x286>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x13d 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x5e>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ ++ rk8602@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ vin-supply = <0x5f>; ++ regulator-compatible = "rk860x-reg"; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0x100590>; ++ regulator-ramp-delay = <0x8fc>; ++ rockchip,suspend-voltage-selector = <0x01>; ++ regulator-boot-on; ++ regulator-always-on; ++ phandle = <0x18>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk8603@43 { ++ compatible = "rockchip,rk8603"; ++ reg = <0x43>; ++ vin-supply = <0x5f>; ++ regulator-compatible = "rk860x-reg"; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0x100590>; ++ regulator-ramp-delay = <0x8fc>; ++ rockchip,suspend-voltage-selector = <0x01>; ++ regulator-boot-on; ++ regulator-always-on; ++ phandle = <0x1c>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ ++ serial@fd890000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfd890000 0x00 0x100>; ++ interrupts = <0x00 0x14b 0x04>; ++ clocks = <0x02 0x2ae 0x02 0x2af>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0x60 0x06 0x60 0x07>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x61>; ++ status = "disabled"; ++ }; ++ ++ pwm@fd8b0000 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfd8b0000 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x62>; ++ clocks = <0x02 0x2a5 0x02 0x2a4>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@fd8b0010 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfd8b0010 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x63>; ++ clocks = <0x02 0x2a5 0x02 0x2a4>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@fd8b0020 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfd8b0020 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x64>; ++ clocks = <0x02 0x2a5 0x02 0x2a4>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@fd8b0030 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfd8b0030 0x00 0x10>; ++ interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x65>; ++ clocks = <0x02 0x2a5 0x02 0x2a4>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ power-management@fd8d8000 { ++ compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; ++ reg = <0x00 0xfd8d8000 0x00 0x400>; ++ phandle = <0xba>; ++ ++ power-controller { ++ compatible = "rockchip,rk3588-power-controller"; ++ #power-domain-cells = <0x01>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x4b>; ++ ++ power-domain@8 { ++ reg = <0x08>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ power-domain@9 { ++ reg = <0x09>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>; ++ pm_qos = <0x66 0x67 0x68>; ++ ++ power-domain@10 { ++ reg = <0x0a>; ++ clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; ++ pm_qos = <0x69>; ++ }; ++ ++ power-domain@11 { ++ reg = <0x0b>; ++ clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; ++ pm_qos = <0x6a>; ++ }; ++ }; ++ }; ++ ++ power-domain@12 { ++ reg = <0x0c>; ++ clocks = <0x02 0x114 0x02 0x115 0x02 0x116>; ++ pm_qos = <0x6b 0x6c 0x6d 0x6e>; ++ }; ++ ++ power-domain@13 { ++ reg = <0x0d>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ power-domain@14 { ++ reg = <0x0e>; ++ clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>; ++ pm_qos = <0x6f>; ++ }; ++ ++ power-domain@15 { ++ reg = <0x0f>; ++ clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>; ++ pm_qos = <0x70>; ++ }; ++ ++ power-domain@16 { ++ reg = <0x10>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0x1c4 0x02 0x1c5>; ++ pm_qos = <0x71 0x72 0x73>; ++ ++ power-domain@17 { ++ reg = <0x11>; ++ clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>; ++ pm_qos = <0x74 0x75 0x76>; ++ }; ++ }; ++ }; ++ ++ power-domain@21 { ++ reg = <0x15>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>; ++ pm_qos = <0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e>; ++ ++ power-domain@23 { ++ reg = <0x17>; ++ clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>; ++ pm_qos = <0x7f>; ++ }; ++ ++ power-domain@14 { ++ reg = <0x0e>; ++ clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>; ++ pm_qos = <0x6f>; ++ }; ++ ++ power-domain@15 { ++ reg = <0x0f>; ++ clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>; ++ pm_qos = <0x70>; ++ }; ++ ++ power-domain@22 { ++ reg = <0x16>; ++ clocks = <0x02 0x1ba 0x02 0x1b9>; ++ pm_qos = <0x80>; ++ }; ++ }; ++ ++ power-domain@24 { ++ reg = <0x18>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>; ++ pm_qos = <0x81 0x82>; ++ ++ power-domain@25 { ++ reg = <0x19>; ++ clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>; ++ pm_qos = <0x83>; ++ }; ++ }; ++ ++ power-domain@26 { ++ reg = <0x1a>; ++ clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>; ++ pm_qos = <0x84 0x85>; ++ }; ++ ++ power-domain@27 { ++ reg = <0x1b>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>; ++ pm_qos = <0x86 0x87 0x88 0x89>; ++ ++ power-domain@28 { ++ reg = <0x1c>; ++ clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>; ++ pm_qos = <0x8a 0x8b>; ++ }; ++ ++ power-domain@29 { ++ reg = <0x1d>; ++ clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>; ++ pm_qos = <0x8c 0x8d>; ++ }; ++ }; ++ ++ power-domain@30 { ++ reg = <0x1e>; ++ clocks = <0x02 0x189 0x02 0x18a>; ++ pm_qos = <0x8e>; ++ }; ++ ++ power-domain@31 { ++ reg = <0x1f>; ++ clocks = <0x02 0x166 0x02 0x19b 0x02 0x19c 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>; ++ pm_qos = <0x8f 0x90 0x91 0x92>; ++ }; ++ ++ power-domain@33 { ++ reg = <0x21>; ++ clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; ++ }; ++ ++ power-domain@34 { ++ reg = <0x22>; ++ clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; ++ }; ++ ++ power-domain@37 { ++ reg = <0x25>; ++ clocks = <0x02 0x199 0x02 0x140>; ++ pm_qos = <0x93>; ++ }; ++ ++ power-domain@38 { ++ reg = <0x26>; ++ clocks = <0x02 0x3c 0x02 0x3d>; ++ }; ++ ++ power-domain@40 { ++ reg = <0x28>; ++ pm_qos = <0x94>; ++ }; ++ }; ++ }; ++ ++ pvtm@fda40000 { ++ compatible = "rockchip,rk3588-bigcore0-pvtm"; ++ reg = <0x00 0xfda40000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ pvtm@0 { ++ reg = <0x00>; ++ clocks = <0x02 0x2c6 0x02 0x15>; ++ clock-names = "clk\0pclk"; ++ }; ++ }; ++ ++ pvtm@fda50000 { ++ compatible = "rockchip,rk3588-bigcore1-pvtm"; ++ reg = <0x00 0xfda50000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ pvtm@1 { ++ reg = <0x01>; ++ clocks = <0x02 0x2c8 0x02 0x17>; ++ clock-names = "clk\0pclk"; ++ }; ++ }; ++ ++ pvtm@fda60000 { ++ compatible = "rockchip,rk3588-litcore-pvtm"; ++ reg = <0x00 0xfda60000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ pvtm@2 { ++ reg = <0x02>; ++ clocks = <0x02 0x2ca 0x02 0x1b>; ++ clock-names = "clk\0pclk"; ++ }; ++ }; ++ ++ pvtm@fdaf0000 { ++ compatible = "rockchip,rk3588-npu-pvtm"; ++ reg = <0x00 0xfdaf0000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ pvtm@3 { ++ reg = <0x03>; ++ clocks = <0x02 0x12b 0x02 0x129>; ++ clock-names = "clk\0pclk"; ++ resets = <0x02 0x1de 0x02 0x1dc>; ++ reset-names = "rts\0rst-p"; ++ }; ++ }; ++ ++ pvtm@fdb30000 { ++ compatible = "rockchip,rk3588-gpu-pvtm"; ++ reg = <0x00 0xfdb30000 0x00 0x100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ pvtm@4 { ++ reg = <0x04>; ++ clocks = <0x02 0x118>; ++ clock-names = "clk"; ++ resets = <0x02 0x430 0x02 0x42f>; ++ reset-names = "rts\0rst-p"; ++ }; ++ }; ++ ++ npu@fdab0000 { ++ compatible = "rockchip,rk3588-rknpu"; ++ reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>; ++ interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; ++ interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq"; ++ clocks = <0x0e 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>; ++ clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk"; ++ assigned-clocks = <0x0e 0x06>; ++ assigned-clock-rates = <0xbebc200>; ++ resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>; ++ reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2"; ++ power-domains = <0x4b 0x09 0x4b 0x0a 0x4b 0x0b>; ++ power-domain-names = "npu0\0npu1\0npu2"; ++ operating-points-v2 = <0x95>; ++ iommus = <0x96>; ++ status = "okay"; ++ rknpu-supply = <0x97>; ++ mem-supply = <0x97>; ++ }; ++ ++ npu-opp-table { ++ compatible = "operating-points-v2"; ++ nvmem-cells = <0x98>; ++ nvmem-cell-names = "leakage"; ++ rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; ++ rockchip,pvtm-pvtpll; ++ rockchip,pvtm-offset = <0x50>; ++ rockchip,pvtm-sample-time = <0x44c>; ++ rockchip,pvtm-freq = <0xc3500>; ++ rockchip,pvtm-volt = <0xb71b0>; ++ rockchip,pvtm-ref-temp = <0x19>; ++ rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>; ++ rockchip,pvtm-thermal-zone = "npu-thermal"; ++ clocks = <0x02 0x12a>; ++ clock-names = "pclk"; ++ rockchip,grf = <0x99>; ++ volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; ++ low-volt-read-margin = <0x04>; ++ intermediate-threshold-freq = <0x7a120>; ++ rockchip,init-freq = <0xf4240>; ++ rockchip,temp-hysteresis = <0x1388>; ++ rockchip,low-temp = <0x2710>; ++ rockchip,low-temp-min-volt = <0xb71b0>; ++ rockchip,high-temp = <0x14c08>; ++ rockchip,high-temp-max-freq = <0xc3500>; ++ phandle = <0x95>; ++ ++ opp-300000000 { ++ opp-hz = <0x00 0x11e1a300>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-400000000 { ++ opp-hz = <0x00 0x17d78400>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-500000000 { ++ opp-hz = <0x00 0x1dcd6500>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = <0x00 0x23c34600>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-700000000 { ++ opp-hz = <0x00 0x29b92700>; ++ opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; ++ opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = <0x00 0x2faf0800>; ++ opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; ++ opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; ++ opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; ++ opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; ++ opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; ++ }; ++ ++ opp-900000000 { ++ opp-hz = <0x00 0x35a4e900>; ++ opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; ++ opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; ++ opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; ++ opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; ++ opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; ++ opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = <0x00 0x3b9aca00>; ++ opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; ++ opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; ++ opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; ++ opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; ++ opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; ++ opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; ++ }; ++ }; ++ ++ iommu@fdab9000 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>; ++ interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; ++ interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu"; ++ clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>; ++ clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2"; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x96>; ++ }; ++ ++ vdpu@fdb50400 { ++ compatible = "rockchip,vpu-decoder-v2"; ++ reg = <0x00 0xfdb50400 0x00 0x400>; ++ interrupts = <0x00 0x77 0x04>; ++ interrupt-names = "irq_vdpu"; ++ clocks = <0x02 0x1c0 0x02 0x1c1>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x2367b880 0x00>; ++ assigned-clocks = <0x02 0x1c0>; ++ assigned-clock-rates = <0x2367b880>; ++ resets = <0x02 0x2c8 0x02 0x2c9>; ++ reset-names = "shared_video_a\0shared_video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0x9a>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x00>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdb50800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdb50800 0x00 0x40>; ++ interrupts = <0x00 0x76 0x04>; ++ interrupt-names = "irq_vdpu_mmu"; ++ clocks = <0x02 0x1c0 0x02 0x1c1>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x9a>; ++ }; ++ ++ avsd-plus@fdb51000 { ++ compatible = "rockchip,avs-plus-decoder"; ++ reg = <0x00 0xfdb51000 0x00 0x200>; ++ interrupts = <0x00 0x77 0x04>; ++ interrupt-names = "irq_avsd"; ++ clocks = <0x02 0x1c0 0x02 0x1c1>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ resets = <0x02 0x2c8 0x02 0x2c9>; ++ reset-names = "shared_video_a\0shared_video_h"; ++ iommus = <0x9a>; ++ power-domains = <0x4b 0x15>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x00>; ++ status = "disabled"; ++ }; ++ ++ rga@fdb60000 { ++ compatible = "rockchip,rga3_core0"; ++ reg = <0x00 0xfdb60000 0x00 0x1000>; ++ interrupts = <0x00 0x72 0x04>; ++ interrupt-names = "rga3_core0_irq"; ++ clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>; ++ clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0"; ++ power-domains = <0x4b 0x16>; ++ iommus = <0x9c>; ++ status = "okay"; ++ }; ++ ++ iommu@fdb60f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdb60f00 0x00 0x100>; ++ interrupts = <0x00 0x72 0x04>; ++ interrupt-names = "rga3_0_mmu"; ++ clocks = <0x02 0x1ba 0x02 0x1b9>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x16>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x9c>; ++ }; ++ ++ rga@fdb70000 { ++ compatible = "rockchip,rga3_core1"; ++ reg = <0x00 0xfdb70000 0x00 0x1000>; ++ interrupts = <0x00 0x73 0x04>; ++ interrupt-names = "rga3_core1_irq"; ++ clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>; ++ clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1"; ++ power-domains = <0x4b 0x1e>; ++ iommus = <0x9d>; ++ status = "okay"; ++ }; ++ ++ iommu@fdb70f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdb70f00 0x00 0x100>; ++ interrupts = <0x00 0x73 0x04>; ++ interrupt-names = "rga3_1_mmu"; ++ clocks = <0x02 0x18a 0x02 0x189>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x1e>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x9d>; ++ }; ++ ++ rga@fdb80000 { ++ compatible = "rockchip,rga2_core0"; ++ reg = <0x00 0xfdb80000 0x00 0x1000>; ++ interrupts = <0x00 0x74 0x04>; ++ interrupt-names = "rga2_irq"; ++ clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>; ++ clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2"; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ jpegd@fdb90000 { ++ compatible = "rockchip,rkv-jpeg-decoder-v1"; ++ reg = <0x00 0xfdb90000 0x00 0x400>; ++ interrupts = <0x00 0x81 0x04>; ++ interrupt-names = "irq_jpegd"; ++ clocks = <0x02 0x1b4 0x02 0x1b5>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x23c34600 0x00>; ++ assigned-clocks = <0x02 0x1b4>; ++ assigned-clock-rates = <0x23c34600>; ++ resets = <0x02 0x2d2 0x02 0x2d3>; ++ reset-names = "video_a\0video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0x9e>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x01>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdb90480 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdb90480 0x00 0x40>; ++ interrupts = <0x00 0x82 0x04>; ++ interrupt-names = "irq_jpegd_mmu"; ++ clocks = <0x02 0x1b4 0x02 0x1b5>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x9e>; ++ }; ++ ++ jpege-core@fdba0000 { ++ compatible = "rockchip,vpu-encoder-v2-core"; ++ reg = <0x00 0xfdba0000 0x00 0x400>; ++ interrupts = <0x00 0x7a 0x04>; ++ interrupt-names = "irq_jpege0"; ++ clocks = <0x02 0x1ac 0x02 0x1ad>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x2367b880 0x00>; ++ assigned-clocks = <0x02 0x1ac>; ++ assigned-clock-rates = <0x2367b880>; ++ resets = <0x02 0x2ca 0x02 0x2cb>; ++ reset-names = "video_a\0video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0x9f>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x02>; ++ rockchip,ccu = <0xa0>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdba0800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdba0800 0x00 0x40>; ++ interrupts = <0x00 0x79 0x04>; ++ interrupt-names = "irq_jpege0_mmu"; ++ clocks = <0x02 0x1ac 0x02 0x1ad>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x9f>; ++ }; ++ ++ jpege-core@fdba4000 { ++ compatible = "rockchip,vpu-encoder-v2-core"; ++ reg = <0x00 0xfdba4000 0x00 0x400>; ++ interrupts = <0x00 0x7c 0x04>; ++ interrupt-names = "irq_jpege1"; ++ clocks = <0x02 0x1ae 0x02 0x1af>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x2367b880 0x00>; ++ assigned-clocks = <0x02 0x1ae>; ++ assigned-clock-rates = <0x2367b880>; ++ resets = <0x02 0x2cc 0x02 0x2cd>; ++ reset-names = "video_a\0video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa1>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x03>; ++ rockchip,ccu = <0xa0>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdba4800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdba4800 0x00 0x40>; ++ interrupts = <0x00 0x7b 0x04>; ++ interrupt-names = "irq_jpege1_mmu"; ++ clocks = <0x02 0x1ae 0x02 0x1af>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0xa1>; ++ }; ++ ++ jpege-core@fdba8000 { ++ compatible = "rockchip,vpu-encoder-v2-core"; ++ reg = <0x00 0xfdba8000 0x00 0x400>; ++ interrupts = <0x00 0x7e 0x04>; ++ interrupt-names = "irq_jpege2"; ++ clocks = <0x02 0x1b0 0x02 0x1b1>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x2367b880 0x00>; ++ assigned-clocks = <0x02 0x1b0>; ++ assigned-clock-rates = <0x2367b880>; ++ resets = <0x02 0x2ce 0x02 0x2cf>; ++ reset-names = "video_a\0video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa2>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x04>; ++ rockchip,ccu = <0xa0>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdba8800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdba8800 0x00 0x40>; ++ interrupts = <0x00 0x7d 0x04>; ++ interrupt-names = "irq_jpege2_mmu"; ++ clocks = <0x02 0x1b0 0x02 0x1b1>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0xa2>; ++ }; ++ ++ jpege-core@fdbac000 { ++ compatible = "rockchip,vpu-encoder-v2-core"; ++ reg = <0x00 0xfdbac000 0x00 0x400>; ++ interrupts = <0x00 0x80 0x04>; ++ interrupt-names = "irq_jpege3"; ++ clocks = <0x02 0x1b2 0x02 0x1b3>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x2367b880 0x00>; ++ assigned-clocks = <0x02 0x1b2>; ++ assigned-clock-rates = <0x2367b880>; ++ resets = <0x02 0x2d0 0x02 0x2d1>; ++ reset-names = "video_a\0video_h"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa3>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x05>; ++ rockchip,ccu = <0xa0>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ }; ++ ++ iommu@fdbac800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdbac800 0x00 0x40>; ++ interrupts = <0x00 0x7f 0x04>; ++ interrupt-names = "irq_jpege3_mmu"; ++ clocks = <0x02 0x1b2 0x02 0x1b3>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x15>; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0xa3>; ++ }; ++ ++ iep@fdbb0000 { ++ compatible = "rockchip,iep-v2"; ++ reg = <0x00 0xfdbb0000 0x00 0x500>; ++ interrupts = <0x00 0x75 0x04>; ++ interrupt-names = "irq_iep"; ++ clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>; ++ clock-names = "aclk\0hclk\0sclk"; ++ resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>; ++ reset-names = "rst_a\0rst_h\0rst_s"; ++ rockchip,skip-pmu-idle-request; ++ power-domains = <0x4b 0x15>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x06>; ++ iommus = <0xa4>; ++ status = "okay"; ++ }; ++ ++ iommu@fdbb0800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdbb0800 0x00 0x100>; ++ interrupts = <0x00 0x75 0x04>; ++ interrupt-names = "irq_iep_mmu"; ++ clocks = <0x02 0x1aa 0x02 0x1a9>; ++ clock-names = "aclk\0iface"; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x15>; ++ status = "okay"; ++ phandle = <0xa4>; ++ }; ++ ++ rkvenc-core@fdbd0000 { ++ compatible = "rockchip,rkv-encoder-v2-core"; ++ reg = <0x00 0xfdbd0000 0x00 0x6000>; ++ interrupts = <0x00 0x65 0x04>; ++ interrupt-names = "irq_rkvenc0"; ++ clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>; ++ clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; ++ rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>; ++ assigned-clocks = <0x02 0x1c5 0x02 0x1c6>; ++ assigned-clock-rates = <0x23c34600 0x2faf0800>; ++ resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>; ++ reset-names = "video_a\0video_h\0video_core"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa5>; ++ rockchip,srv = <0x9b>; ++ rockchip,ccu = <0xa6>; ++ rockchip,taskqueue-node = <0x07>; ++ rockchip,task-capacity = <0x08>; ++ power-domains = <0x4b 0x10>; ++ status = "okay"; ++ }; ++ ++ iommu@fdbdf000 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>; ++ interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>; ++ interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1"; ++ clocks = <0x02 0x1c5 0x02 0x1c4>; ++ clock-names = "aclk\0iface"; ++ rockchip,disable-mmu-reset; ++ rockchip,enable-cmd-retry; ++ rockchip,shootdown-entire; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x10>; ++ status = "okay"; ++ phandle = <0xa5>; ++ }; ++ ++ rkvenc-core@fdbe0000 { ++ compatible = "rockchip,rkv-encoder-v2-core"; ++ reg = <0x00 0xfdbe0000 0x00 0x6000>; ++ interrupts = <0x00 0x68 0x04>; ++ interrupt-names = "irq_rkvenc1"; ++ clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>; ++ clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; ++ rockchip,normal-rates = <0x23c34600 0x00 0x2faf0800>; ++ assigned-clocks = <0x02 0x1ca 0x02 0x1cb>; ++ assigned-clock-rates = <0x23c34600 0x2faf0800>; ++ resets = <0x02 0x305 0x02 0x304 0x02 0x306>; ++ reset-names = "video_a\0video_h\0video_core"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa7>; ++ rockchip,srv = <0x9b>; ++ rockchip,ccu = <0xa6>; ++ rockchip,taskqueue-node = <0x07>; ++ rockchip,task-capacity = <0x08>; ++ power-domains = <0x4b 0x11>; ++ status = "okay"; ++ }; ++ ++ iommu@fdbef000 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>; ++ interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>; ++ interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1"; ++ clocks = <0x02 0x1ca 0x02 0x1c9>; ++ lock-names = "aclk\0iface"; ++ rockchip,disable-mmu-reset; ++ rockchip,enable-cmd-retry; ++ rockchip,shootdown-entire; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x11>; ++ status = "okay"; ++ phandle = <0xa7>; ++ }; ++ ++ rkvdec-ccu@fdc30000 { ++ compatible = "rockchip,rkv-decoder-v2-ccu"; ++ reg = <0x00 0xfdc30000 0x00 0x100>; ++ reg-names = "ccu"; ++ clocks = <0x02 0x18e>; ++ clock-names = "aclk_ccu"; ++ assigned-clocks = <0x02 0x18e>; ++ assigned-clock-rates = <0x23c34600>; ++ resets = <0x02 0x282>; ++ reset-names = "video_ccu"; ++ rockchip,skip-pmu-idle-request; ++ power-domains = <0x4b 0x0e>; ++ status = "okay"; ++ phandle = <0xa9>; ++ }; ++ ++ rkvdec-core@fdc38000 { ++ compatible = "rockchip,rkv-decoder-v2"; ++ reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>; ++ reg-names = "regs\0link"; ++ interrupts = <0x00 0x5f 0x04>; ++ interrupt-names = "irq_rkvdec0"; ++ clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>; ++ clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; ++ rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; ++ assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>; ++ assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; ++ resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>; ++ reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xa8>; ++ rockchip,srv = <0x9b>; ++ rockchip,ccu = <0xa9>; ++ rockchip,core-mask = <0x10001>; ++ rockchip,taskqueue-node = <0x09>; ++ rockchip,sram = <0xaa>; ++ rockchip,rcb-iova = <0x10000000 0x100000>; ++ rockchip,rcb-min-width = <0x200>; ++ power-domains = <0x4b 0x0e>; ++ status = "okay"; ++ }; ++ ++ iommu@fdc38700 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>; ++ interrupts = <0x00 0x60 0x04>; ++ interrupt-names = "irq_rkvdec0_mmu"; ++ clocks = <0x02 0x190 0x02 0x18f>; ++ clock-names = "aclk\0iface"; ++ rockchip,disable-mmu-reset; ++ rockchip,enable-cmd-retry; ++ rockchip,shootdown-entire; ++ rockchip,master-handle-irq; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x0e>; ++ status = "okay"; ++ phandle = <0xa8>; ++ }; ++ ++ rkvdec-core@fdc48000 { ++ compatible = "rockchip,rkv-decoder-v2"; ++ reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>; ++ reg-names = "regs\0link"; ++ interrupts = <0x00 0x61 0x04>; ++ interrupt-names = "irq_rkvdec1"; ++ clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>; ++ clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; ++ rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; ++ assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>; ++ assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; ++ resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>; ++ reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; ++ rockchip,skip-pmu-idle-request; ++ iommus = <0xab>; ++ rockchip,srv = <0x9b>; ++ rockchip,ccu = <0xa9>; ++ rockchip,core-mask = <0x20002>; ++ rockchip,taskqueue-node = <0x09>; ++ rockchip,sram = <0xac>; ++ rockchip,rcb-iova = <0x10100000 0x100000>; ++ rockchip,rcb-min-width = <0x200>; ++ power-domains = <0x4b 0x0f>; ++ status = "okay"; ++ }; ++ ++ iommu@fdc48700 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>; ++ interrupts = <0x00 0x62 0x04>; ++ interrupt-names = "irq_rkvdec1_mmu"; ++ clocks = <0x02 0x195 0x02 0x194>; ++ clock-names = "aclk\0iface"; ++ rockchip,disable-mmu-reset; ++ rockchip,enable-cmd-retry; ++ rockchip,shootdown-entire; ++ rockchip,master-handle-irq; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x0f>; ++ status = "okay"; ++ phandle = <0xab>; ++ }; ++ ++ av1d@fdc70000 { ++ compatible = "rockchip,av1-decoder"; ++ reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>; ++ reg-names = "vcd\0cache\0afbc"; ++ interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>; ++ interrupt-names = "irq_av1d\0irq_cache\0irq_afbc"; ++ clocks = <0x02 0x49 0x02 0x4b>; ++ clock-names = "aclk_vcodec\0hclk_vcodec"; ++ rockchip,normal-rates = <0x17d78400 0x17d78400>; ++ assigned-clocks = <0x02 0x49 0x02 0x4b>; ++ assigned-clock-rates = <0x17d78400 0x17d78400>; ++ resets = <0x02 0x442 0x02 0x445>; ++ reset-names = "video_a\0video_h"; ++ iommus = <0xad>; ++ rockchip,srv = <0x9b>; ++ rockchip,taskqueue-node = <0x0b>; ++ power-domains = <0x4b 0x17>; ++ status = "okay"; ++ }; ++ ++ iommu@fdca0000 { ++ compatible = "rockchip,iommu-av1"; ++ reg = <0x00 0xfdca0000 0x00 0x600>; ++ interrupts = <0x00 0x6d 0x04>; ++ interrupt-names = "irq_av1d_mmu"; ++ clocks = <0x02 0x49 0x02 0x4b>; ++ clock-names = "aclk\0iface"; ++ #iommu-cells = <0x00>; ++ power-domains = <0x4b 0x17>; ++ status = "okay"; ++ phandle = <0xad>; ++ }; ++ ++ rkisp-unite@fdcb0000 { ++ compatible = "rockchip,rk3588-rkisp-unite"; ++ reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>; ++ interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; ++ interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; ++ clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; ++ clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1"; ++ power-domains = <0x4b 0x1c>; ++ iommus = <0xae>; ++ status = "disabled"; ++ }; ++ ++ rkisp@fdcb0000 { ++ compatible = "rockchip,rk3588-rkisp"; ++ reg = <0x00 0xfdcb0000 0x00 0x7f00>; ++ interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>; ++ interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; ++ clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>; ++ clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; ++ power-domains = <0x4b 0x1b>; ++ iommus = <0xaf>; ++ status = "disabled"; ++ phandle = <0x43>; ++ }; ++ ++ rkisp-unite-mmu@fdcb7f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>; ++ interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>; ++ interrupt-names = "isp0_mmu\0isp1_mmu"; ++ clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>; ++ clock-names = "aclk0\0iface0\0aclk1\0iface1"; ++ power-domains = <0x4b 0x1c>; ++ #iommu-cells = <0x00>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ phandle = <0xae>; ++ }; ++ ++ iommu@fdcb7f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdcb7f00 0x00 0x100>; ++ interrupts = <0x00 0x84 0x04>; ++ interrupt-names = "isp0_mmu"; ++ clocks = <0x02 0x1de 0x02 0x1df>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x1b>; ++ #iommu-cells = <0x00>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ phandle = <0xaf>; ++ }; ++ ++ rkisp@fdcc0000 { ++ compatible = "rockchip,rk3588-rkisp"; ++ reg = <0x00 0xfdcc0000 0x00 0x7f00>; ++ interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; ++ interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; ++ clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; ++ clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; ++ power-domains = <0x4b 0x1c>; ++ iommus = <0xb0>; ++ status = "disabled"; ++ phandle = <0x45>; ++ }; ++ ++ iommu@fdcc7f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdcc7f00 0x00 0x100>; ++ interrupts = <0x00 0x88 0x04>; ++ interrupt-names = "isp1_mmu"; ++ clocks = <0x02 0x120 0x02 0x121>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x1c>; ++ #iommu-cells = <0x00>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ phandle = <0xb0>; ++ }; ++ ++ rkispp@fdcd0000 { ++ compatible = "rockchip,rk3588-rkispp"; ++ reg = <0x00 0xfdcd0000 0x00 0xf00>; ++ interrupts = <0x00 0x8b 0x04>; ++ interrupt-names = "fec_irq"; ++ clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; ++ clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; ++ power-domains = <0x4b 0x1d>; ++ iommus = <0xb1>; ++ status = "disabled"; ++ phandle = <0x46>; ++ }; ++ ++ iommu@fdcd0f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdcd0f00 0x00 0x100>; ++ interrupts = <0x00 0x8c 0x04>; ++ interrupt-names = "fec0_mmu"; ++ clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; ++ clock-names = "aclk\0iface\0pclk"; ++ power-domains = <0x4b 0x1d>; ++ #iommu-cells = <0x00>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ phandle = <0xb1>; ++ }; ++ ++ rkispp@fdcd8000 { ++ compatible = "rockchip,rk3588-rkispp"; ++ reg = <0x00 0xfdcd8000 0x00 0xf00>; ++ interrupts = <0x00 0x8d 0x04>; ++ interrupt-names = "fec_irq"; ++ clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; ++ clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; ++ power-domains = <0x4b 0x1d>; ++ iommus = <0xb2>; ++ status = "disabled"; ++ phandle = <0x47>; ++ }; ++ ++ iommu@fdcd8f00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdcd8f00 0x00 0x100>; ++ interrupts = <0x00 0x8e 0x04>; ++ interrupt-names = "fec1_mmu"; ++ clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; ++ clock-names = "aclk\0iface\0pclk"; ++ power-domains = <0x4b 0x1d>; ++ #iommu-cells = <0x00>; ++ rockchip,disable-mmu-reset; ++ status = "disabled"; ++ phandle = <0xb2>; ++ }; ++ ++ rkcif@fdce0000 { ++ compatible = "rockchip,rk3588-cif"; ++ reg = <0x00 0xfdce0000 0x00 0x800>; ++ reg-names = "cif_regs"; ++ interrupts = <0x00 0x9b 0x04>; ++ interrupt-names = "cif-intr"; ++ clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3>; ++ clock-names = "aclk_cif\0hclk_cif\0dclk_cif"; ++ resets = <0x02 0x317 0x02 0x318 0x02 0x316>; ++ reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d"; ++ assigned-clocks = <0x02 0x1e3>; ++ assigned-clock-rates = <0x23c34600>; ++ power-domains = <0x4b 0x1b>; ++ rockchip,grf = <0xb3>; ++ iommus = <0x3b>; ++ status = "okay"; ++ phandle = <0x3a>; ++ }; ++ ++ iommu@fdce0800 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>; ++ interrupts = <0x00 0x71 0x04>; ++ interrupt-names = "cif_mmu"; ++ clocks = <0x02 0x1e4 0x02 0x1e5>; ++ clock-names = "aclk\0iface"; ++ power-domains = <0x4b 0x1b>; ++ rockchip,disable-mmu-reset; ++ #iommu-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x3b>; ++ }; ++ ++ mipi0-csi2@fdd10000 { ++ compatible = "rockchip,rk3588-mipi-csi2"; ++ reg = <0x00 0xfdd10000 0x00 0x10000>; ++ reg-names = "csihost_regs"; ++ interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>; ++ interrupt-names = "csi-intr1\0csi-intr2"; ++ clocks = <0x02 0x1cf 0x02 0x1cd>; ++ clock-names = "pclk_csi2host\0iclk_csi2host"; ++ resets = <0x02 0x324 0x02 0x334>; ++ reset-names = "srst_csihost_p\0srst_csihost_vicap"; ++ status = "disabled"; ++ }; ++ ++ mipi1-csi2@fdd20000 { ++ compatible = "rockchip,rk3588-mipi-csi2"; ++ reg = <0x00 0xfdd20000 0x00 0x10000>; ++ reg-names = "csihost_regs"; ++ interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>; ++ interrupt-names = "csi-intr1\0csi-intr2"; ++ clocks = <0x02 0x1d0 0x02 0x1ce>; ++ clock-names = "pclk_csi2host\0iclk_csi2host"; ++ resets = <0x02 0x325 0x02 0x335>; ++ reset-names = "srst_csihost_p\0srst_csihost_vicap"; ++ status = "disabled"; ++ }; ++ ++ mipi2-csi2@fdd30000 { ++ compatible = "rockchip,rk3588-mipi-csi2"; ++ reg = <0x00 0xfdd30000 0x00 0x10000>; ++ reg-names = "csihost_regs"; ++ interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>; ++ interrupt-names = "csi-intr1\0csi-intr2"; ++ clocks = <0x02 0x1d1>; ++ clock-names = "pclk_csi2host"; ++ resets = <0x02 0x326 0x02 0x336>; ++ reset-names = "srst_csihost_p\0srst_csihost_vicap"; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xb4>; ++ phandle = <0x2c>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <0x01>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xb5>; ++ phandle = <0x3f>; ++ }; ++ }; ++ }; ++ }; ++ ++ mipi3-csi2@fdd40000 { ++ compatible = "rockchip,rk3588-mipi-csi2"; ++ reg = <0x00 0xfdd40000 0x00 0x10000>; ++ reg-names = "csihost_regs"; ++ interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>; ++ interrupt-names = "csi-intr1\0csi-intr2"; ++ clocks = <0x02 0x1d2>; ++ clock-names = "pclk_csi2host"; ++ resets = <0x02 0x327 0x02 0x337>; ++ reset-names = "srst_csihost_p\0srst_csihost_vicap"; ++ status = "disabled"; ++ }; ++ ++ vop@fdd90000 { ++ compatible = "rockchip,rk3588-vop"; ++ reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>; ++ reg-names = "regs\0gamma_lut"; ++ interrupts = <0x00 0x9c 0x04>; ++ clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273 0xb6>; ++ clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2\0hdmi0_phy_pll"; ++ resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>; ++ reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3"; ++ iommus = <0xb7>; ++ power-domains = <0x4b 0x18>; ++ rockchip,grf = <0xb3>; ++ rockchip,vop-grf = <0xb8>; ++ rockchip,vo1-grf = <0xb9>; ++ rockchip,pmu = <0xba>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ phandle = <0x2d>; ++ ++ port@0 { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x00>; ++ rockchip,plane-mask = <0x05>; ++ rockchip,primary-plane = <0x02>; ++ assigned-clocks = <0x02 0x270>; ++ assigned-clock-rates = <0x2faf0800>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xbb>; ++ phandle = <0xce>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xbc>; ++ phandle = <0xd8>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xbd>; ++ phandle = <0x33>; ++ }; ++ }; ++ ++ port@1 { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x01>; ++ rockchip,plane-mask = <0x0a>; ++ rockchip,primary-plane = <0x03>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xbe>; ++ phandle = <0x2f>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xbf>; ++ phandle = <0xd9>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xc0>; ++ phandle = <0xd5>; ++ }; ++ }; ++ ++ port@2 { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x02>; ++ assigned-clocks = <0x02 0x273>; ++ assigned-clock-parents = <0x02 0x04>; ++ rockchip,plane-mask = <0x140>; ++ rockchip,primary-plane = <0x08>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xc1>; ++ phandle = <0xcf>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xc2>; ++ phandle = <0x32>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xc3>; ++ phandle = <0xd6>; ++ }; ++ ++ endpoint@3 { ++ reg = <0x03>; ++ remote-endpoint = <0xc4>; ++ phandle = <0xcb>; ++ }; ++ ++ endpoint@4 { ++ reg = <0x04>; ++ remote-endpoint = <0xc5>; ++ phandle = <0xcc>; ++ }; ++ }; ++ ++ port@3 { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x03>; ++ rockchip,plane-mask = <0x280>; ++ rockchip,primary-plane = <0x09>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xc6>; ++ phandle = <0x30>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xc7>; ++ phandle = <0x31>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xc8>; ++ phandle = <0x34>; ++ }; ++ }; ++ }; ++ }; ++ ++ iommu@fdd97e00 { ++ compatible = "rockchip,iommu-v2"; ++ reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>; ++ interrupts = <0x00 0x9c 0x04>; ++ interrupt-names = "vop_mmu"; ++ clocks = <0x02 0x270 0x02 0x26f>; ++ clock-names = "aclk\0iface"; ++ #iommu-cells = <0x00>; ++ rockchip,disable-device-link-resume; ++ rockchip,shootdown-entire; ++ status = "okay"; ++ phandle = <0xb7>; ++ }; ++ ++ spdif-tx@fddb0000 { ++ compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; ++ reg = <0x00 0xfddb0000 0x00 0x1000>; ++ interrupts = <0x00 0xc3 0x04>; ++ dmas = <0xc9 0x06>; ++ dma-names = "tx"; ++ clock-names = "mclk\0hclk"; ++ clocks = <0x02 0x209 0x02 0x204>; ++ assigned-clocks = <0x02 0x205>; ++ assigned-clock-parents = <0x02 0x05>; ++ power-domains = <0x4b 0x19>; ++ #sound-dai-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x177>; ++ }; ++ ++ i2s@fddc0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x00 0xfddc0000 0x00 0x1000>; ++ interrupts = <0x00 0xb8 0x04>; ++ clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>; ++ clock-names = "mclk_tx\0mclk_rx\0hclk"; ++ assigned-clocks = <0x02 0x1f9>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xca 0x00>; ++ dma-names = "tx"; ++ power-domains = <0x4b 0x19>; ++ resets = <0x02 0x38d>; ++ reset-names = "tx-m"; ++ rockchip,playback-only; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ spdif-tx@fdde0000 { ++ compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; ++ reg = <0x00 0xfdde0000 0x00 0x1000>; ++ interrupts = <0x00 0xc4 0x04>; ++ dmas = <0xc9 0x07>; ++ dma-names = "tx"; ++ clock-names = "mclk\0hclk"; ++ clocks = <0x02 0x257 0x02 0x253>; ++ assigned-clocks = <0x02 0x254>; ++ assigned-clock-parents = <0x02 0x05>; ++ power-domains = <0x4b 0x1a>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ i2s@fddf0000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x00 0xfddf0000 0x00 0x1000>; ++ interrupts = <0x00 0xb9 0x04>; ++ clocks = <0x02 0x246 0x02 0x246 0x02 0x248>; ++ clock-names = "mclk_tx\0mclk_rx\0hclk"; ++ assigned-clocks = <0x02 0x243>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xca 0x02>; ++ dma-names = "tx"; ++ power-domains = <0x4b 0x1a>; ++ resets = <0x02 0x3e8>; ++ reset-names = "tx-m"; ++ rockchip,playback-only; ++ #sound-dai-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x175>; ++ }; ++ ++ i2s@fddfc000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x00 0xfddfc000 0x00 0x1000>; ++ interrupts = <0x00 0xbd 0x04>; ++ clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>; ++ clock-names = "mclk_tx\0mclk_rx\0hclk"; ++ assigned-clocks = <0x02 0x23f>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xca 0x17>; ++ dma-names = "rx"; ++ power-domains = <0x4b 0x1a>; ++ resets = <0x02 0x413>; ++ reset-names = "rx-m"; ++ rockchip,capture-only; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ spdif-rx@fde08000 { ++ compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; ++ reg = <0x00 0xfde08000 0x00 0x1000>; ++ interrupts = <0x00 0xc7 0x04>; ++ clocks = <0x02 0x25e 0x02 0x25d>; ++ clock-names = "mclk\0hclk"; ++ assigned-clocks = <0x02 0x25e>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0x60 0x15>; ++ dma-names = "rx"; ++ power-domains = <0x4b 0x1a>; ++ resets = <0x02 0x3fd>; ++ reset-names = "spdifrx-m"; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ dsi@fde20000 { ++ compatible = "rockchip,rk3588-mipi-dsi2"; ++ reg = <0x00 0xfde20000 0x00 0x10000>; ++ interrupts = <0x00 0xa7 0x04>; ++ clocks = <0x02 0x278 0x02 0x27a>; ++ clock-names = "pclk\0sys_clk"; ++ resets = <0x02 0x354>; ++ reset-names = "apb"; ++ power-domains = <0x4b 0x18>; ++ phys = <0x28>; ++ phy-names = "dcphy"; ++ rockchip,grf = <0xb8>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xcb>; ++ status = "disabled"; ++ phandle = <0xc4>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0x30>; ++ status = "disabled"; ++ phandle = <0xc6>; ++ }; ++ }; ++ }; ++ }; ++ ++ dsi@fde30000 { ++ compatible = "rockchip,rk3588-mipi-dsi2"; ++ reg = <0x00 0xfde30000 0x00 0x10000>; ++ interrupts = <0x00 0xa8 0x04>; ++ clocks = <0x02 0x279 0x02 0x27b>; ++ clock-names = "pclk\0sys_clk"; ++ resets = <0x02 0x355>; ++ reset-names = "apb"; ++ power-domains = <0x4b 0x18>; ++ phys = <0x29>; ++ phy-names = "dcphy"; ++ rockchip,grf = <0xb8>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xcc>; ++ status = "disabled"; ++ phandle = <0xc5>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0x31>; ++ status = "disabled"; ++ phandle = <0xc7>; ++ }; ++ }; ++ }; ++ }; ++ ++ dp@fde50000 { ++ compatible = "rockchip,rk3588-dp"; ++ reg = <0x00 0xfde50000 0x00 0x4000>; ++ interrupts = <0x00 0xa1 0x04>; ++ clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04>; ++ clock-names = "apb\0aux\0i2s\0spdif\0hclk"; ++ assigned-clocks = <0x02 0x2cc>; ++ assigned-clock-rates = <0xf42400>; ++ resets = <0x02 0x388>; ++ phys = <0xcd>; ++ power-domains = <0x4b 0x19>; ++ #sound-dai-cells = <0x01>; ++ status = "okay"; ++ phandle = <0x178>; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xce>; ++ status = "disabled"; ++ phandle = <0xbb>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0x2f>; ++ status = "disabled"; ++ phandle = <0xbe>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xcf>; ++ status = "okay"; ++ phandle = <0xc1>; ++ }; ++ }; ++ }; ++ }; ++ ++ hdmi@fde80000 { ++ compatible = "rockchip,rk3588-dw-hdmi"; ++ reg = <0x00 0xfde80000 0x00 0x20000>; ++ interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>; ++ clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05>; ++ clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1"; ++ resets = <0x02 0x3d0 0x02 0x49c>; ++ reset-names = "ref\0hdp"; ++ power-domains = <0x4b 0x1a>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xd0 0xd1 0xd2 0xd3>; ++ reg-io-width = <0x04>; ++ rockchip,grf = <0xb3>; ++ rockchip,vo1_grf = <0xb9>; ++ phys = <0xb6>; ++ phy-names = "hdmi"; ++ #sound-dai-cells = <0x00>; ++ status = "okay"; ++ enable-gpios = <0xd4 0x0a 0x00>; ++ phandle = <0x176>; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0x33>; ++ status = "okay"; ++ phandle = <0xbd>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xd5>; ++ status = "disabled"; ++ phandle = <0xc0>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0xd6>; ++ status = "disabled"; ++ phandle = <0xc3>; ++ }; ++ }; ++ }; ++ }; ++ ++ edp@fdec0000 { ++ compatible = "rockchip,rk3588-edp"; ++ reg = <0x00 0xfdec0000 0x00 0x1000>; ++ interrupts = <0x00 0xa3 0x04>; ++ clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>; ++ clock-names = "dp\0pclk\0spdif\0hclk"; ++ resets = <0x02 0x3e1 0x02 0x3e0>; ++ reset-names = "dp\0apb"; ++ phys = <0xd7>; ++ phy-names = "dp"; ++ power-domains = <0x4b 0x1a>; ++ rockchip,grf = <0xb9>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0xd8>; ++ status = "disabled"; ++ phandle = <0xbc>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0xd9>; ++ status = "disabled"; ++ phandle = <0xbf>; ++ }; ++ ++ endpoint@2 { ++ reg = <0x02>; ++ remote-endpoint = <0x32>; ++ status = "disabled"; ++ phandle = <0xc2>; ++ }; ++ }; ++ }; ++ }; ++ ++ qos@fdf35000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf35000 0x00 0x20>; ++ phandle = <0x6b>; ++ }; ++ ++ qos@fdf35200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf35200 0x00 0x20>; ++ phandle = <0x6c>; ++ }; ++ ++ qos@fdf35400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf35400 0x00 0x20>; ++ phandle = <0x6d>; ++ }; ++ ++ qos@fdf35600 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf35600 0x00 0x20>; ++ phandle = <0x6e>; ++ }; ++ ++ qos@fdf36000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf36000 0x00 0x20>; ++ phandle = <0x8e>; ++ }; ++ ++ qos@fdf39000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf39000 0x00 0x20>; ++ phandle = <0x93>; ++ }; ++ ++ qos@fdf3d800 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf3d800 0x00 0x20>; ++ phandle = <0x94>; ++ }; ++ ++ qos@fdf3e000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf3e000 0x00 0x20>; ++ phandle = <0x90>; ++ }; ++ ++ qos@fdf3e200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf3e200 0x00 0x20>; ++ phandle = <0x8f>; ++ }; ++ ++ qos@fdf3e400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf3e400 0x00 0x20>; ++ phandle = <0x91>; ++ }; ++ ++ qos@fdf3e600 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf3e600 0x00 0x20>; ++ phandle = <0x92>; ++ }; ++ ++ qos@fdf40000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40000 0x00 0x20>; ++ phandle = <0x8c>; ++ }; ++ ++ qos@fdf40200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40200 0x00 0x20>; ++ phandle = <0x8d>; ++ }; ++ ++ qos@fdf40400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40400 0x00 0x20>; ++ phandle = <0x86>; ++ }; ++ ++ qos@fdf40500 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40500 0x00 0x20>; ++ phandle = <0x87>; ++ }; ++ ++ qos@fdf40600 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40600 0x00 0x20>; ++ phandle = <0x88>; ++ }; ++ ++ qos@fdf40800 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf40800 0x00 0x20>; ++ phandle = <0x89>; ++ }; ++ ++ qos@fdf41000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf41000 0x00 0x20>; ++ phandle = <0x8a>; ++ }; ++ ++ qos@fdf41100 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf41100 0x00 0x20>; ++ phandle = <0x8b>; ++ }; ++ ++ qos@fdf60000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf60000 0x00 0x20>; ++ phandle = <0x71>; ++ }; ++ ++ qos@fdf60200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf60200 0x00 0x20>; ++ phandle = <0x72>; ++ }; ++ ++ qos@fdf60400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf60400 0x00 0x20>; ++ phandle = <0x73>; ++ }; ++ ++ qos@fdf61000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf61000 0x00 0x20>; ++ phandle = <0x74>; ++ }; ++ ++ qos@fdf61200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf61200 0x00 0x20>; ++ phandle = <0x75>; ++ }; ++ ++ qos@fdf61400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf61400 0x00 0x20>; ++ phandle = <0x76>; ++ }; ++ ++ qos@fdf62000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf62000 0x00 0x20>; ++ phandle = <0x6f>; ++ }; ++ ++ qos@fdf63000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf63000 0x00 0x20>; ++ phandle = <0x70>; ++ }; ++ ++ qos@fdf64000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf64000 0x00 0x20>; ++ phandle = <0x7f>; ++ }; ++ ++ qos@fdf66000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66000 0x00 0x20>; ++ phandle = <0x77>; ++ }; ++ ++ qos@fdf66200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66200 0x00 0x20>; ++ phandle = <0x78>; ++ }; ++ ++ qos@fdf66400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66400 0x00 0x20>; ++ phandle = <0x79>; ++ }; ++ ++ qos@fdf66600 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66600 0x00 0x20>; ++ phandle = <0x7a>; ++ }; ++ ++ qos@fdf66800 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66800 0x00 0x20>; ++ phandle = <0x7b>; ++ }; ++ ++ qos@fdf66a00 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66a00 0x00 0x20>; ++ phandle = <0x7c>; ++ }; ++ ++ qos@fdf66c00 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66c00 0x00 0x20>; ++ phandle = <0x7d>; ++ }; ++ ++ qos@fdf66e00 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf66e00 0x00 0x20>; ++ phandle = <0x7e>; ++ }; ++ ++ qos@fdf67000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf67000 0x00 0x20>; ++ phandle = <0x80>; ++ }; ++ ++ qos@fdf67200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf67200 0x00 0x20>; ++ }; ++ ++ qos@fdf70000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf70000 0x00 0x20>; ++ phandle = <0x69>; ++ }; ++ ++ qos@fdf71000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf71000 0x00 0x20>; ++ phandle = <0x6a>; ++ }; ++ ++ qos@fdf72000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf72000 0x00 0x20>; ++ phandle = <0x66>; ++ }; ++ ++ qos@fdf72200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf72200 0x00 0x20>; ++ phandle = <0x67>; ++ }; ++ ++ qos@fdf72400 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf72400 0x00 0x20>; ++ phandle = <0x68>; ++ }; ++ ++ qos@fdf80000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf80000 0x00 0x20>; ++ phandle = <0x83>; ++ }; ++ ++ qos@fdf81000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf81000 0x00 0x20>; ++ phandle = <0x84>; ++ }; ++ ++ qos@fdf81200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf81200 0x00 0x20>; ++ phandle = <0x85>; ++ }; ++ ++ qos@fdf82000 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf82000 0x00 0x20>; ++ phandle = <0x81>; ++ }; ++ ++ qos@fdf82200 { ++ compatible = "syscon"; ++ reg = <0x00 0xfdf82200 0x00 0x20>; ++ phandle = <0x82>; ++ }; ++ ++ dfi@fe060000 { ++ reg = <0x00 0xfe060000 0x00 0x10000>; ++ compatible = "rockchip,rk3588-dfi"; ++ rockchip,pmu_grf = <0xda>; ++ status = "okay"; ++ phandle = <0x35>; ++ }; ++ ++ pcie@fe180000 { ++ compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; ++ #address-cells = <0x03>; ++ #size-cells = <0x02>; ++ bus-range = <0x30 0x3f>; ++ clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>; ++ clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; ++ device_type = "pci"; ++ interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>; ++ interrupt-names = "sys\0pmc\0msg\0legacy\0err"; ++ #interrupt-cells = <0x01>; ++ interrupt-map-mask = <0x00 0x00 0x00 0x07>; ++ interrupt-map = <0x00 0x00 0x00 0x01 0xdb 0x00 0x00 0x00 0x00 0x02 0xdb 0x01 0x00 0x00 0x00 0x03 0xdb 0x02 0x00 0x00 0x00 0x04 0xdb 0x03>; ++ linux,pci-domain = <0x03>; ++ num-ib-windows = <0x08>; ++ num-ob-windows = <0x08>; ++ num-viewport = <0x04>; ++ max-link-speed = <0x02>; ++ msi-map = <0x3000 0xdc 0x3000 0x1000>; ++ num-lanes = <0x01>; ++ phys = <0x57 0x02>; ++ phy-names = "pcie-phy"; ++ ranges = <0x800 0x00 0xf3000000 0x00 0xf3000000 0x00 0x100000 0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>; ++ reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000>; ++ reg-names = "pcie-apb\0pcie-dbi"; ++ resets = <0x02 0x210 0x02 0x21f>; ++ reset-names = "pcie\0periph"; ++ rockchip,pipe-grf = <0x5d>; ++ status = "disabled"; ++ ++ legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0x00>; ++ #interrupt-cells = <0x01>; ++ interrupt-parent = <0x01>; ++ interrupts = <0x00 0xf5 0x01>; ++ phandle = <0xdb>; ++ }; ++ }; ++ ++ pcie@fe190000 { ++ compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; ++ #address-cells = <0x03>; ++ #size-cells = <0x02>; ++ bus-range = <0x40 0x4f>; ++ clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>; ++ clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; ++ device_type = "pci"; ++ interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>; ++ interrupt-names = "sys\0pmc\0msg\0legacy\0err"; ++ #interrupt-cells = <0x01>; ++ interrupt-map-mask = <0x00 0x00 0x00 0x07>; ++ interrupt-map = <0x00 0x00 0x00 0x01 0xdd 0x00 0x00 0x00 0x00 0x02 0xdd 0x01 0x00 0x00 0x00 0x03 0xdd 0x02 0x00 0x00 0x00 0x04 0xdd 0x03>; ++ linux,pci-domain = <0x04>; ++ num-ib-windows = <0x08>; ++ num-ob-windows = <0x08>; ++ num-viewport = <0x04>; ++ max-link-speed = <0x02>; ++ msi-map = <0x4000 0xdc 0x4000 0x1000>; ++ num-lanes = <0x01>; ++ phys = <0xde 0x02>; ++ phy-names = "pcie-phy"; ++ ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>; ++ reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000>; ++ reg-names = "pcie-apb\0pcie-dbi"; ++ resets = <0x02 0x211 0x02 0x220>; ++ reset-names = "pcie\0periph"; ++ rockchip,pipe-grf = <0x5d>; ++ status = "disabled"; ++ ++ legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0x00>; ++ #interrupt-cells = <0x01>; ++ interrupt-parent = <0x01>; ++ interrupts = <0x00 0xfa 0x01>; ++ phandle = <0xdd>; ++ }; ++ }; ++ ++ ethernet@fe1b0000 { ++ compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; ++ reg = <0x00 0xfe1b0000 0x00 0x10000>; ++ interrupts = <0x00 0xe3 0x04 0x00 0xe2 0x04>; ++ interrupt-names = "macirq\0eth_wake_irq"; ++ rockchip,grf = <0xb3>; ++ rockchip,php_grf = <0x5d>; ++ clocks = <0x02 0x144 0x02 0x145 0x02 0x167 0x02 0x16c 0x02 0x142>; ++ clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; ++ resets = <0x02 0x20a>; ++ reset-names = "stmmaceth"; ++ power-domains = <0x4b 0x21>; ++ snps,mixed-burst; ++ snps,tso; ++ snps,axi-config = <0xdf>; ++ snps,mtl-rx-config = <0xe0>; ++ snps,mtl-tx-config = <0xe1>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ }; ++ ++ stmmac-axi-config { ++ snps,wr_osr_lmt = <0x04>; ++ snps,rd_osr_lmt = <0x08>; ++ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; ++ phandle = <0xdf>; ++ }; ++ ++ rx-queues-config { ++ snps,rx-queues-to-use = <0x02>; ++ phandle = <0xe0>; ++ ++ queue0 { ++ }; ++ ++ queue1 { ++ }; ++ }; ++ ++ tx-queues-config { ++ snps,tx-queues-to-use = <0x02>; ++ phandle = <0xe1>; ++ ++ queue0 { ++ }; ++ ++ queue1 { ++ }; ++ }; ++ }; ++ ++ ethernet@fe1c0000 { ++ compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; ++ reg = <0x00 0xfe1c0000 0x00 0x10000>; ++ interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>; ++ interrupt-names = "macirq\0eth_wake_irq"; ++ rockchip,grf = <0xb3>; ++ rockchip,php_grf = <0x5d>; ++ clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>; ++ clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; ++ resets = <0x02 0x20b>; ++ reset-names = "stmmaceth"; ++ power-domains = <0x4b 0x21>; ++ snps,mixed-burst; ++ snps,tso; ++ snps,axi-config = <0xe2>; ++ snps,mtl-rx-config = <0xe3>; ++ snps,mtl-tx-config = <0xe4>; ++ status = "okay"; ++ phy-mode = "rgmii-rxid"; ++ clock_in_out = "output"; ++ snps,reset-gpio = <0xe5 0x1b 0x01>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0x00 0x4e20 0x186a0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xe6 0xe7 0xe8 0xe9 0xea>; ++ tx_delay = <0x43>; ++ phy-handle = <0xeb>; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x01>; ++ phandle = <0xeb>; ++ }; ++ }; ++ ++ stmmac-axi-config { ++ snps,wr_osr_lmt = <0x04>; ++ snps,rd_osr_lmt = <0x08>; ++ snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; ++ phandle = <0xe2>; ++ }; ++ ++ rx-queues-config { ++ snps,rx-queues-to-use = <0x02>; ++ phandle = <0xe3>; ++ ++ queue0 { ++ }; ++ ++ queue1 { ++ }; ++ }; ++ ++ tx-queues-config { ++ snps,tx-queues-to-use = <0x02>; ++ phandle = <0xe4>; ++ ++ queue0 { ++ }; ++ ++ queue1 { ++ }; ++ }; ++ }; ++ ++ sata@fe210000 { ++ compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; ++ reg = <0x00 0xfe210000 0x00 0x1000>; ++ clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>; ++ clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; ++ interrupts = <0x00 0x111 0x04>; ++ interrupt-names = "hostc"; ++ phys = <0xde 0x01>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x01>; ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xec>; ++ }; ++ ++ sata@fe230000 { ++ compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; ++ reg = <0x00 0xfe230000 0x00 0x1000>; ++ clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>; ++ clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; ++ interrupts = <0x00 0x113 0x04>; ++ interrupt-names = "hostc"; ++ phys = <0x57 0x01>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x01>; ++ status = "disabled"; ++ }; ++ ++ spi@fe2b0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x00 0xfe2b0000 0x00 0x4000>; ++ interrupts = <0x00 0xce 0x04>; ++ clocks = <0x02 0x13d 0x02 0x13e>; ++ clock-names = "clk_sfc\0hclk_sfc"; ++ assigned-clocks = <0x02 0x13d>; ++ assigned-clock-rates = <0x5f5e100>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ mmc@fe2c0000 { ++ compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; ++ reg = <0x00 0xfe2c0000 0x00 0x4000>; ++ interrupts = <0x00 0xcb 0x04>; ++ clocks = <0x0e 0x17 0x0e 0x09 0x02 0x2c2 0x02 0x2c3>; ++ clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <0x8f0d180>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xed 0xee 0xef 0xf0>; ++ power-domains = <0x4b 0x28>; ++ status = "okay"; ++ no-sdio; ++ no-mmc; ++ bus-width = <0x04>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ sd-uhs-sdr104; ++ vqmmc-supply = <0xf1>; ++ vmmc-supply = <0xf2>; ++ }; ++ ++ mmc@fe2d0000 { ++ compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; ++ reg = <0x00 0xfe2d0000 0x00 0x4000>; ++ interrupts = <0x00 0xcc 0x04>; ++ clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>; ++ clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <0xbebc200>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xf3>; ++ power-domains = <0x4b 0x25>; ++ status = "disabled"; ++ }; ++ ++ mmc@fe2e0000 { ++ compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; ++ reg = <0x00 0xfe2e0000 0x00 0x10000>; ++ interrupts = <0x00 0xcd 0x04>; ++ assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>; ++ assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; ++ clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>; ++ clock-names = "core\0bus\0axi\0block\0timer"; ++ resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>; ++ reset-names = "core\0bus\0axi\0block\0timer"; ++ max-frequency = <0xbebc200>; ++ status = "okay"; ++ bus-width = <0x08>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ }; ++ ++ crypto@fe370000 { ++ compatible = "rockchip,rk3588-crypto"; ++ reg = <0x00 0xfe370000 0x00 0x2000>; ++ interrupts = <0x00 0xd1 0x04>; ++ clocks = <0x0e 0x0b 0x0e 0x0c 0x0e 0x14 0x0e 0x15>; ++ clock-names = "aclk\0hclk\0sclk\0pka"; ++ resets = <0xf4 0x0f>; ++ reset-names = "crypto-rst"; ++ status = "disabled"; ++ }; ++ ++ rng@fe378000 { ++ compatible = "rockchip,trngv1"; ++ reg = <0x00 0xfe378000 0x00 0x200>; ++ interrupts = <0x00 0x190 0x04>; ++ clocks = <0x0e 0x0c>; ++ clock-names = "hclk_trng"; ++ resets = <0xf4 0x30>; ++ reset-names = "reset"; ++ status = "okay"; ++ }; ++ ++ i2s@fe470000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x00 0xfe470000 0x00 0x1000>; ++ interrupts = <0x00 0xb4 0x04>; ++ clocks = <0x02 0x33 0x02 0x37 0x02 0x30>; ++ clock-names = "mclk_tx\0mclk_rx\0hclk"; ++ assigned-clocks = <0x02 0x31 0x02 0x35>; ++ assigned-clock-parents = <0x02 0x05 0x02 0x05>; ++ dmas = <0x60 0x00 0x60 0x01>; ++ dma-names = "tx\0rx"; ++ power-domains = <0x4b 0x26>; ++ resets = <0x02 0x77 0x02 0x7a>; ++ reset-names = "tx-m\0rx-m"; ++ rockchip,clk-trcm = <0x01>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xf5 0xf6 0xf7 0xf8>; ++ #sound-dai-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x17c>; ++ }; ++ ++ i2s@fe480000 { ++ compatible = "rockchip,rk3588-i2s-tdm"; ++ reg = <0x00 0xfe480000 0x00 0x1000>; ++ interrupts = <0x00 0xb5 0x04>; ++ clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>; ++ clock-names = "mclk_tx\0mclk_rx\0hclk"; ++ dmas = <0x60 0x02 0x60 0x03>; ++ dma-names = "tx\0rx"; ++ resets = <0x02 0xc002a 0x02 0xc002d>; ++ reset-names = "tx-m\0rx-m"; ++ rockchip,clk-trcm = <0x01>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ i2s@fe490000 { ++ compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; ++ reg = <0x00 0xfe490000 0x00 0x1000>; ++ interrupts = <0x00 0xb6 0x04>; ++ clocks = <0x02 0x27 0x02 0x22>; ++ clock-names = "i2s_clk\0i2s_hclk"; ++ assigned-clocks = <0x02 0x24>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xc9 0x00 0xc9 0x01>; ++ dma-names = "tx\0rx"; ++ power-domains = <0x4b 0x26>; ++ rockchip,clk-trcm = <0x01>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x103 0x104 0x105 0x106>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ i2s@fe4a0000 { ++ compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; ++ reg = <0x00 0xfe4a0000 0x00 0x1000>; ++ interrupts = <0x00 0xb7 0x04>; ++ clocks = <0x02 0x2d 0x02 0x23>; ++ clock-names = "i2s_clk\0i2s_hclk"; ++ assigned-clocks = <0x02 0x2a>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xc9 0x02 0xc9 0x03>; ++ dma-names = "tx\0rx"; ++ power-domains = <0x4b 0x26>; ++ rockchip,clk-trcm = <0x01>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x107 0x108 0x109 0x10a>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ pdm@fe4b0000 { ++ compatible = "rockchip,rk3588-pdm"; ++ reg = <0x00 0xfe4b0000 0x00 0x1000>; ++ clocks = <0x02 0x29f 0x02 0x29e>; ++ clock-names = "pdm_clk\0pdm_hclk"; ++ dmas = <0x60 0x04>; ++ dma-names = "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x10b 0x10c 0x10d 0x10e 0x10f 0x110>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ pdm@fe4c0000 { ++ compatible = "rockchip,rk3588-pdm"; ++ reg = <0x00 0xfe4c0000 0x00 0x1000>; ++ clocks = <0x02 0x3b 0x02 0x3a>; ++ clock-names = "pdm_clk\0pdm_hclk"; ++ assigned-clocks = <0x02 0x3b>; ++ assigned-clock-parents = <0x02 0x05>; ++ dmas = <0xc9 0x04>; ++ dma-names = "rx"; ++ power-domains = <0x4b 0x26>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x111 0x112 0x113 0x114 0x115 0x116>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ vad@fe4d0000 { ++ compatible = "rockchip,rk3588-vad"; ++ reg = <0x00 0xfe4d0000 0x00 0x1000>; ++ reg-names = "vad"; ++ clocks = <0x02 0x2a0>; ++ clock-names = "hclk"; ++ interrupts = <0x00 0xca 0x04>; ++ rockchip,audio-src = <0x00>; ++ rockchip,det-channel = <0x00>; ++ rockchip,mode = <0x00>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ spdif-tx@fe4e0000 { ++ compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; ++ reg = <0x00 0xfe4e0000 0x00 0x1000>; ++ interrupts = <0x00 0xc1 0x04>; ++ dmas = <0x60 0x05>; ++ dma-names = "tx"; ++ clock-names = "mclk\0hclk"; ++ clocks = <0x02 0x41 0x02 0x3e>; ++ assigned-clocks = <0x02 0x3f>; ++ assigned-clock-parents = <0x02 0x05>; ++ power-domains = <0x4b 0x26>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x117>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ spdif-tx@fe4f0000 { ++ compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; ++ reg = <0x00 0xfe4f0000 0x00 0x1000>; ++ interrupts = <0x00 0xc2 0x04>; ++ dmas = <0xc9 0x05>; ++ dma-names = "tx"; ++ clock-names = "mclk\0hclk"; ++ clocks = <0x02 0x47 0x02 0x44>; ++ assigned-clocks = <0x02 0x45>; ++ assigned-clock-parents = <0x02 0x05>; ++ power-domains = <0x4b 0x26>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x118>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ phandle = <0x179>; ++ }; ++ ++ codec-digital@fe500000 { ++ compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1"; ++ reg = <0x00 0xfe500000 0x00 0x1000>; ++ clocks = <0x02 0x29 0x02 0x2f>; ++ clock-names = "dac\0pclk"; ++ power-domains = <0x4b 0x26>; ++ resets = <0x02 0x84>; ++ reset-names = "reset"; ++ rockchip,grf = <0xb3>; ++ rockchip,pwm-output-mode; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x119>; ++ #sound-dai-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ hwspinlock@fe5a0000 { ++ compatible = "rockchip,hwspinlock"; ++ reg = <0x00 0xfe5a0000 0x00 0x100>; ++ #hwlock-cells = <0x01>; ++ }; ++ ++ interrupt-controller@fe600000 { ++ compatible = "arm,gic-v3"; ++ #interrupt-cells = <0x03>; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ interrupt-controller; ++ reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; ++ interrupts = <0x01 0x09 0x04>; ++ phandle = <0x01>; ++ ++ msi-controller@fe640000 { ++ compatible = "arm,gic-v3-its"; ++ msi-controller; ++ #msi-cells = <0x01>; ++ reg = <0x00 0xfe640000 0x00 0x20000>; ++ phandle = <0xdc>; ++ }; ++ ++ msi-controller@fe660000 { ++ compatible = "arm,gic-v3-its"; ++ msi-controller; ++ #msi-cells = <0x01>; ++ reg = <0x00 0xfe660000 0x00 0x20000>; ++ }; ++ }; ++ ++ dma-controller@fea10000 { ++ compatible = "arm,pl330\0arm,primecell"; ++ reg = <0x00 0xfea10000 0x00 0x4000>; ++ interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>; ++ clocks = <0x02 0x78>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <0x01>; ++ arm,pl330-periph-burst; ++ phandle = <0x60>; ++ }; ++ ++ dma-controller@fea30000 { ++ compatible = "arm,pl330\0arm,primecell"; ++ reg = <0x00 0xfea30000 0x00 0x4000>; ++ interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>; ++ clocks = <0x02 0x79>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <0x01>; ++ arm,pl330-periph-burst; ++ phandle = <0xc9>; ++ }; ++ ++ can@fea50000 { ++ compatible = "rockchip,can-2.0"; ++ reg = <0x00 0xfea50000 0x00 0x1000>; ++ interrupts = <0x00 0x155 0x04>; ++ clocks = <0x02 0x70 0x02 0x6f>; ++ clock-names = "baudclk\0apb_pclk"; ++ resets = <0x02 0xb9 0x02 0xb8>; ++ reset-names = "can\0can-apb"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11a>; ++ tx-fifo-depth = <0x01>; ++ rx-fifo-depth = <0x06>; ++ status = "disabled"; ++ }; ++ ++ can@fea60000 { ++ compatible = "rockchip,can-2.0"; ++ reg = <0x00 0xfea60000 0x00 0x1000>; ++ interrupts = <0x00 0x156 0x04>; ++ clocks = <0x02 0x72 0x02 0x71>; ++ clock-names = "baudclk\0apb_pclk"; ++ resets = <0x02 0xbb 0x02 0xba>; ++ reset-names = "can\0can-apb"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11b>; ++ tx-fifo-depth = <0x01>; ++ rx-fifo-depth = <0x06>; ++ status = "disabled"; ++ }; ++ ++ can@fea70000 { ++ compatible = "rockchip,can-2.0"; ++ reg = <0x00 0xfea70000 0x00 0x1000>; ++ interrupts = <0x00 0x157 0x04>; ++ clocks = <0x02 0x74 0x02 0x73>; ++ clock-names = "baudclk\0apb_pclk"; ++ resets = <0x02 0xbd 0x02 0xbc>; ++ reset-names = "can\0can-apb"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11c>; ++ tx-fifo-depth = <0x01>; ++ rx-fifo-depth = <0x06>; ++ status = "disabled"; ++ }; ++ ++ decompress@fea80000 { ++ compatible = "rockchip,hw-decompress"; ++ reg = <0x00 0xfea80000 0x00 0x1000>; ++ interrupts = <0x00 0x55 0x04>; ++ clocks = <0x02 0x75 0x02 0x77 0x02 0x76>; ++ clock-names = "aclk\0dclk\0pclk"; ++ resets = <0x02 0x118>; ++ reset-names = "dresetn"; ++ status = "disabled"; ++ }; ++ ++ i2c@fea90000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfea90000 0x00 0x1000>; ++ clocks = <0x02 0x8d 0x02 0x85>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x13e 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11d>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ i2c@feaa0000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfeaa0000 0x00 0x1000>; ++ clocks = <0x02 0x8e 0x02 0x86>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x13f 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11e>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ clock-frequency = <0x61a80>; ++ ++ rk8602@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ vin-supply = <0x5f>; ++ regulator-compatible = "rk860x-reg"; ++ regulator-name = "vdd_npu_s0"; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0xe7ef0>; ++ regulator-ramp-delay = <0x8fc>; ++ rockchip,suspend-voltage-selector = <0x01>; ++ regulator-boot-on; ++ regulator-always-on; ++ phandle = <0x97>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ fusb302@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <0xe5>; ++ interrupts = <0x14 0x08>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x11f>; ++ vbus-supply = <0x120>; ++ status = "okay"; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ ++ endpoint@0 { ++ remote-endpoint = <0x121>; ++ phandle = <0x52>; ++ }; ++ }; ++ }; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "dual"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <0xf4240>; ++ sink-pdos = <0x4019064>; ++ source-pdos = <0x401912c>; ++ ++ altmodes { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ altmode@0 { ++ reg = <0x00>; ++ svid = <0xff01>; ++ vdo = <0xffffffff>; ++ }; ++ }; ++ ++ ports { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ port@0 { ++ reg = <0x00>; ++ ++ endpoint { ++ remote-endpoint = <0x122>; ++ phandle = <0x15f>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <0x01>; ++ ++ endpoint { ++ remote-endpoint = <0x123>; ++ phandle = <0x160>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ hym8563@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0x00>; ++ clock-frequency = <0x8000>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x124>; ++ interrupt-parent = <0xe5>; ++ interrupts = <0x08 0x08>; ++ wakeup-source; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c@feab0000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfeab0000 0x00 0x1000>; ++ clocks = <0x02 0x8f 0x02 0x87>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x140 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x125>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ ++ es8388@11 { ++ status = "okay"; ++ #sound-dai-cells = <0x00>; ++ compatible = "everest,es8388\0everest,es8323"; ++ reg = <0x11>; ++ clocks = <0x02 0x39>; ++ clock-names = "mclk"; ++ assigned-clocks = <0x02 0x39>; ++ assigned-clock-rates = <0xbb8000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x126>; ++ phandle = <0x17d>; ++ }; ++ }; ++ ++ i2c@feac0000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfeac0000 0x00 0x1000>; ++ clocks = <0x02 0x90 0x02 0x88>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x141 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x127>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ }; ++ ++ i2c@fead0000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfead0000 0x00 0x1000>; ++ clocks = <0x02 0x91 0x02 0x89>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x142 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x128>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ timer@feae0000 { ++ compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer"; ++ reg = <0x00 0xfeae0000 0x00 0x20>; ++ interrupts = <0x00 0x121 0x04>; ++ clocks = <0x02 0x5c 0x02 0x5f>; ++ clock-names = "pclk\0timer"; ++ }; ++ ++ watchdog@feaf0000 { ++ compatible = "snps,dw-wdt"; ++ reg = <0x00 0xfeaf0000 0x00 0x100>; ++ clocks = <0x02 0x6c 0x02 0x6b>; ++ clock-names = "tclk\0pclk"; ++ interrupts = <0x00 0x13b 0x04>; ++ status = "disabled"; ++ }; ++ ++ spi@feb00000 { ++ compatible = "rockchip,rk3066-spi"; ++ reg = <0x00 0xfeb00000 0x00 0x1000>; ++ interrupts = <0x00 0x146 0x04>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0xa3 0x02 0x9e>; ++ clock-names = "spiclk\0apb_pclk"; ++ dmas = <0x60 0x0e 0x60 0x0f>; ++ dma-names = "tx\0rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x129 0x12a 0x12b>; ++ num-cs = <0x02>; ++ status = "disabled"; ++ }; ++ ++ spi@feb10000 { ++ compatible = "rockchip,rk3066-spi"; ++ reg = <0x00 0xfeb10000 0x00 0x1000>; ++ interrupts = <0x00 0x147 0x04>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0xa4 0x02 0x9f>; ++ clock-names = "spiclk\0apb_pclk"; ++ dmas = <0x60 0x10 0x60 0x11>; ++ dma-names = "tx\0rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x12c 0x12d>; ++ num-cs = <0x01>; ++ status = "okay"; ++ }; ++ ++ spi@feb20000 { ++ compatible = "rockchip,rk3066-spi"; ++ reg = <0x00 0xfeb20000 0x00 0x1000>; ++ interrupts = <0x00 0x148 0x04>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0xa5 0x02 0xa0>; ++ clock-names = "spiclk\0apb_pclk"; ++ dmas = <0xc9 0x0f 0xc9 0x10>; ++ dma-names = "tx\0rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x12e 0x12f>; ++ num-cs = <0x01>; ++ status = "okay"; ++ assigned-clocks = <0x02 0xa5>; ++ assigned-clock-rates = <0xbebc200>; ++ ++ rk806single@0 { ++ compatible = "rockchip,rk806"; ++ spi-max-frequency = <0xf4240>; ++ reg = <0x00>; ++ interrupt-parent = <0xe5>; ++ interrupts = <0x07 0x08>; ++ pinctrl-names = "default\0pmic-power-off"; ++ pinctrl-0 = <0x130 0x131 0x132 0x133>; ++ pinctrl-1 = <0x134>; ++ low_voltage_threshold = <0xbb8>; ++ shutdown_voltage_threshold = <0xa8c>; ++ shutdown_temperture_threshold = <0xa0>; ++ hotdie_temperture_threshold = <0x73>; ++ pmic-reset-func = <0x01>; ++ vcc1-supply = <0x5f>; ++ vcc2-supply = <0x5f>; ++ vcc3-supply = <0x5f>; ++ vcc4-supply = <0x5f>; ++ vcc5-supply = <0x5f>; ++ vcc6-supply = <0x5f>; ++ vcc7-supply = <0x5f>; ++ vcc8-supply = <0x5f>; ++ vcc9-supply = <0x5f>; ++ vcc10-supply = <0x5f>; ++ vcc11-supply = <0x135>; ++ vcc12-supply = <0x5f>; ++ vcc13-supply = <0x136>; ++ vcc14-supply = <0x136>; ++ vcca-supply = <0x5f>; ++ ++ pwrkey { ++ status = "okay"; ++ }; ++ ++ pinctrl_rk806 { ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ ++ rk806_dvs1_null { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ phandle = <0x131>; ++ }; ++ ++ rk806_dvs1_slp { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun1"; ++ }; ++ ++ rk806_dvs1_pwrdn { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun2"; ++ phandle = <0x134>; ++ }; ++ ++ rk806_dvs1_rst { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs2_null { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ phandle = <0x132>; ++ }; ++ ++ rk806_dvs2_slp { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun1"; ++ }; ++ ++ rk806_dvs2_pwrdn { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun2"; ++ }; ++ ++ rk806_dvs2_rst { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs2_dvs { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun4"; ++ }; ++ ++ rk806_dvs2_gpio { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun5"; ++ }; ++ ++ rk806_dvs3_null { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ phandle = <0x133>; ++ }; ++ ++ rk806_dvs3_slp { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun1"; ++ }; ++ ++ rk806_dvs3_pwrdn { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun2"; ++ }; ++ ++ rk806_dvs3_rst { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun3"; ++ }; ++ ++ rk806_dvs3_dvs { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun4"; ++ }; ++ ++ rk806_dvs3_gpio { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun5"; ++ }; ++ }; ++ ++ regulators { ++ ++ DCDC_REG1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0xe7ef0>; ++ regulator-ramp-delay = <0x30d4>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <0x190>; ++ phandle = <0x4d>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0xe7ef0>; ++ regulator-ramp-delay = <0x30d4>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ phandle = <0x12>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xa4cb8>; ++ regulator-max-microvolt = <0xb71b0>; ++ regulator-ramp-delay = <0x30d4>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-suspend-microvolt = <0xb71b0>; ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x86470>; ++ regulator-max-microvolt = <0xe7ef0>; ++ regulator-init-microvolt = <0xb71b0>; ++ regulator-ramp-delay = <0x30d4>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xa4cb8>; ++ regulator-max-microvolt = <0xdbba0>; ++ regulator-ramp-delay = <0x30d4>; ++ regulator-name = "vdd_ddr_s0"; ++ phandle = <0x37>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <0xcf850>; ++ }; ++ }; ++ ++ DCDC_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1e8480>; ++ regulator-max-microvolt = <0x1e8480>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ phandle = <0x135>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <0x1e8480>; ++ }; ++ }; ++ ++ DCDC_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ regulator-name = "vcc_3v3_s3"; ++ phandle = <0x183>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <0x325aa0>; ++ }; ++ }; ++ ++ DCDC_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ DCDC_REG10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1b7740>; ++ regulator-max-microvolt = <0x1b7740>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <0x1b7740>; ++ }; ++ }; ++ ++ PLDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1b7740>; ++ regulator-max-microvolt = <0x1b7740>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ PLDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1b7740>; ++ regulator-max-microvolt = <0x1b7740>; ++ regulator-name = "vcc_1v8_s0"; ++ phandle = <0x151>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <0x1b7740>; ++ }; ++ }; ++ ++ PLDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x124f80>; ++ regulator-max-microvolt = <0x124f80>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ PLDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ PLDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1b7740>; ++ regulator-max-microvolt = <0x325aa0>; ++ regulator-name = "vccio_sd_s0"; ++ phandle = <0xf1>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ PLDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x1b7740>; ++ regulator-max-microvolt = <0x1b7740>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <0x1b7740>; ++ }; ++ }; ++ ++ NLDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xb71b0>; ++ regulator-max-microvolt = <0xb71b0>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <0xb71b0>; ++ }; ++ }; ++ ++ NLDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xcf850>; ++ regulator-max-microvolt = <0xcf850>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <0xcf850>; ++ }; ++ }; ++ ++ NLDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xb71b0>; ++ regulator-max-microvolt = <0xb71b0>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ NLDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xcf850>; ++ regulator-max-microvolt = <0xcf850>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ NLDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xb71b0>; ++ regulator-max-microvolt = <0xb71b0>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ spi@feb30000 { ++ compatible = "rockchip,rk3066-spi"; ++ reg = <0x00 0xfeb30000 0x00 0x1000>; ++ interrupts = <0x00 0x149 0x04>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0xa6 0x02 0xa1>; ++ clock-names = "spiclk\0apb_pclk"; ++ dmas = <0xc9 0x11 0xc9 0x12>; ++ dma-names = "tx\0rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x137 0x138 0x139>; ++ num-cs = <0x02>; ++ status = "disabled"; ++ }; ++ ++ serial@feb40000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb40000 0x00 0x100>; ++ interrupts = <0x00 0x14c 0x04>; ++ clocks = <0x02 0xb7 0x02 0xab>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0x60 0x08 0x60 0x09>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13a>; ++ status = "disabled"; ++ }; ++ ++ serial@feb50000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb50000 0x00 0x100>; ++ interrupts = <0x00 0x14d 0x04>; ++ clocks = <0x02 0xbb 0x02 0xac>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0x60 0x0a 0x60 0x0b>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13b>; ++ status = "disabled"; ++ }; ++ ++ serial@feb60000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb60000 0x00 0x100>; ++ interrupts = <0x00 0x14e 0x04>; ++ clocks = <0x02 0xbf 0x02 0xad>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0x60 0x0c 0x60 0x0d>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13c>; ++ status = "disabled"; ++ }; ++ ++ serial@feb70000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb70000 0x00 0x100>; ++ interrupts = <0x00 0x14f 0x04>; ++ clocks = <0x02 0xc3 0x02 0xae>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xc9 0x09 0xc9 0x0a>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13d>; ++ status = "disabled"; ++ }; ++ ++ serial@feb80000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb80000 0x00 0x100>; ++ interrupts = <0x00 0x150 0x04>; ++ clocks = <0x02 0xc7 0x02 0xaf>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xc9 0x0b 0xc9 0x0c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13e>; ++ status = "disabled"; ++ }; ++ ++ serial@feb90000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeb90000 0x00 0x100>; ++ interrupts = <0x00 0x151 0x04>; ++ clocks = <0x02 0xcb 0x02 0xb0>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xc9 0x0d 0xc9 0x0e>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x13f>; ++ status = "disabled"; ++ }; ++ ++ serial@feba0000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfeba0000 0x00 0x100>; ++ interrupts = <0x00 0x152 0x04>; ++ clocks = <0x02 0xcf 0x02 0xb1>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xca 0x07 0xca 0x08>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x140>; ++ status = "okay"; ++ }; ++ ++ serial@febb0000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfebb0000 0x00 0x100>; ++ interrupts = <0x00 0x153 0x04>; ++ clocks = <0x02 0xd3 0x02 0xb2>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xca 0x09 0xca 0x0a>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x141>; ++ status = "disabled"; ++ }; ++ ++ serial@febc0000 { ++ compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; ++ reg = <0x00 0xfebc0000 0x00 0x100>; ++ interrupts = <0x00 0x154 0x04>; ++ clocks = <0x02 0xd7 0x02 0xb3>; ++ clock-names = "baudclk\0apb_pclk"; ++ reg-shift = <0x02>; ++ reg-io-width = <0x04>; ++ dmas = <0xca 0x0b 0xca 0x0c>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x142>; ++ status = "disabled"; ++ }; ++ ++ pwm@febd0000 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebd0000 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x143>; ++ clocks = <0x02 0x54 0x02 0x53>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febd0010 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebd0010 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x144>; ++ clocks = <0x02 0x54 0x02 0x53>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febd0020 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebd0020 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x145>; ++ clocks = <0x02 0x54 0x02 0x53>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febd0030 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebd0030 0x00 0x10>; ++ interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x146>; ++ clocks = <0x02 0x54 0x02 0x53>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febe0000 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebe0000 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x147>; ++ clocks = <0x02 0x57 0x02 0x56>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febe0010 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebe0010 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x148>; ++ clocks = <0x02 0x57 0x02 0x56>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febe0020 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebe0020 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x149>; ++ clocks = <0x02 0x57 0x02 0x56>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febe0030 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebe0030 0x00 0x10>; ++ interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x14a>; ++ clocks = <0x02 0x57 0x02 0x56>; ++ clock-names = "pwm\0pclk"; ++ status = "okay"; ++ phandle = <0x182>; ++ }; ++ ++ pwm@febf0000 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebf0000 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x14b>; ++ clocks = <0x02 0x5a 0x02 0x59>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febf0010 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebf0010 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x14c>; ++ clocks = <0x02 0x5a 0x02 0x59>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febf0020 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebf0020 0x00 0x10>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x14d>; ++ clocks = <0x02 0x5a 0x02 0x59>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ pwm@febf0030 { ++ compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; ++ reg = <0x00 0xfebf0030 0x00 0x10>; ++ interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>; ++ #pwm-cells = <0x03>; ++ pinctrl-names = "active"; ++ pinctrl-0 = <0x14e>; ++ clocks = <0x02 0x5a 0x02 0x59>; ++ clock-names = "pwm\0pclk"; ++ status = "disabled"; ++ }; ++ ++ tsadc@fec00000 { ++ compatible = "rockchip,rk3588-tsadc"; ++ reg = <0x00 0xfec00000 0x00 0x400>; ++ interrupts = <0x00 0x18d 0x04>; ++ clocks = <0x02 0xaa 0x02 0xa9>; ++ clock-names = "tsadc\0apb_pclk"; ++ assigned-clocks = <0x02 0xaa>; ++ assigned-clock-rates = <0x1e8480>; ++ resets = <0x02 0xc1 0x02 0xc0>; ++ reset-names = "tsadc\0tsadc-apb"; ++ #thermal-sensor-cells = <0x01>; ++ rockchip,hw-tshut-temp = <0x1d4c0>; ++ rockchip,hw-tshut-mode = <0x00>; ++ rockchip,hw-tshut-polarity = <0x00>; ++ pinctrl-names = "gpio\0otpout"; ++ pinctrl-0 = <0x14f>; ++ pinctrl-1 = <0x150>; ++ status = "okay"; ++ phandle = <0x48>; ++ }; ++ ++ saradc@fec10000 { ++ compatible = "rockchip,rk3588-saradc"; ++ reg = <0x00 0xfec10000 0x00 0x10000>; ++ interrupts = <0x00 0x18e 0x04>; ++ #io-channel-cells = <0x01>; ++ clocks = <0x02 0x9d 0x02 0x9c>; ++ clock-names = "saradc\0apb_pclk"; ++ resets = <0x02 0xbe>; ++ reset-names = "saradc-apb"; ++ status = "okay"; ++ vref-supply = <0x151>; ++ phandle = <0x17b>; ++ }; ++ ++ mailbox@fec60000 { ++ compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; ++ reg = <0x00 0xfec60000 0x00 0x200>; ++ interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>; ++ clocks = <0x02 0x4c>; ++ clock-names = "pclk_mailbox"; ++ #mbox-cells = <0x01>; ++ status = "disabled"; ++ }; ++ ++ mailbox@fec70000 { ++ compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; ++ reg = <0x00 0xfec70000 0x00 0x200>; ++ interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>; ++ clocks = <0x02 0x4d>; ++ clock-names = "pclk_mailbox"; ++ #mbox-cells = <0x01>; ++ status = "disabled"; ++ }; ++ ++ i2c@fec80000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfec80000 0x00 0x1000>; ++ clocks = <0x02 0x92 0x02 0x8a>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x143 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x152>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ }; ++ ++ i2c@fec90000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfec90000 0x00 0x1000>; ++ clocks = <0x02 0x93 0x02 0x8b>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x144 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x153>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "okay"; ++ ++ XC7160b@1b { ++ compatible = "firefly,xc7160"; ++ reg = <0x1b>; ++ clocks = <0x02 0x100>; ++ clock-names = "xvclk"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x154>; ++ power-domains = <0x4b 0x1b>; ++ power-gpios = <0xd4 0x0d 0x01>; ++ reset-gpios = <0xe5 0x1d 0x00>; ++ pwdn-gpios = <0xd4 0x0c 0x00>; ++ firefly,clkout-enabled-index = <0x00>; ++ rockchip,camera-module-index = <0x00>; ++ rockchip,camera-module-facing = "back"; ++ rockchip,camera-module-name = "NC"; ++ rockchip,camera-module-lens-name = "NC"; ++ ++ port { ++ ++ endpoint { ++ remote-endpoint = <0x155>; ++ data-lanes = <0x01 0x02 0x03 0x04>; ++ phandle = <0x2b>; ++ }; ++ }; ++ }; ++ }; ++ ++ i2c@feca0000 { ++ compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; ++ reg = <0x00 0xfeca0000 0x00 0x1000>; ++ clocks = <0x02 0x94 0x02 0x8c>; ++ clock-names = "i2c\0pclk"; ++ interrupts = <0x00 0x145 0x04>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x156>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ status = "disabled"; ++ }; ++ ++ spi@fecb0000 { ++ compatible = "rockchip,rk3066-spi"; ++ reg = <0x00 0xfecb0000 0x00 0x1000>; ++ interrupts = <0x00 0x14a 0x04>; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ clocks = <0x02 0xa7 0x02 0xa2>; ++ clock-names = "spiclk\0apb_pclk"; ++ dmas = <0xca 0x0d 0xca 0x0e>; ++ dma-names = "tx\0rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x157 0x158 0x159>; ++ num-cs = <0x02>; ++ status = "disabled"; ++ }; ++ ++ otp@fecc0000 { ++ compatible = "rockchip,rk3588-otp"; ++ reg = <0x00 0xfecc0000 0x00 0x400>; ++ #address-cells = <0x01>; ++ #size-cells = <0x01>; ++ clocks = <0x02 0x96 0x02 0x95 0x02 0x97 0x02 0x99>; ++ clock-names = "otpc\0apb\0arb\0phy"; ++ resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>; ++ reset-names = "otpc\0apb\0arb"; ++ ++ cpu-code@2 { ++ reg = <0x02 0x02>; ++ phandle = <0x27>; ++ }; ++ ++ id@7 { ++ reg = <0x07 0x10>; ++ phandle = <0x25>; ++ }; ++ ++ cpu-version@1c { ++ reg = <0x1c 0x01>; ++ bits = <0x03 0x03>; ++ phandle = <0x26>; ++ }; ++ ++ cpub0-leakage@17 { ++ reg = <0x17 0x01>; ++ phandle = <0x21>; ++ }; ++ ++ cpub1-leakage@18 { ++ reg = <0x18 0x01>; ++ phandle = <0x23>; ++ }; ++ ++ cpul-leakage@19 { ++ reg = <0x19 0x01>; ++ phandle = <0x1f>; ++ }; ++ ++ log-leakage@1a { ++ reg = <0x1a 0x01>; ++ phandle = <0x38>; ++ }; ++ ++ gpu-leakage@1b { ++ reg = <0x1b 0x01>; ++ phandle = <0x4e>; ++ }; ++ ++ npu-leakage@28 { ++ reg = <0x28 0x01>; ++ phandle = <0x98>; ++ }; ++ ++ codec-leakage@29 { ++ reg = <0x29 0x01>; ++ }; ++ }; ++ ++ mailbox@fece0000 { ++ compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; ++ reg = <0x00 0xfece0000 0x00 0x200>; ++ interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>; ++ clocks = <0x02 0x4e>; ++ clock-names = "pclk_mailbox"; ++ #mbox-cells = <0x01>; ++ status = "disabled"; ++ }; ++ ++ dma-controller@fed10000 { ++ compatible = "arm,pl330\0arm,primecell"; ++ reg = <0x00 0xfed10000 0x00 0x4000>; ++ interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>; ++ clocks = <0x02 0x7a>; ++ clock-names = "apb_pclk"; ++ #dma-cells = <0x01>; ++ arm,pl330-periph-burst; ++ phandle = <0xca>; ++ }; ++ ++ phy@fed60000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x00 0xfed60000 0x00 0x2000>; ++ clocks = <0x02 0x2b5 0x02 0x267>; ++ clock-names = "ref\0apb"; ++ resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>; ++ reset-names = "apb\0init\0cmn\0lane"; ++ rockchip,grf = <0x15a>; ++ #phy-cells = <0x00>; ++ status = "disabled"; ++ phandle = <0xd7>; ++ }; ++ ++ hdmiphy@fed60000 { ++ compatible = "rockchip,rk3588-hdptx-phy-hdmi"; ++ reg = <0x00 0xfed60000 0x00 0x2000>; ++ clocks = <0x02 0x2b5 0x02 0x267>; ++ clock-names = "ref\0apb"; ++ resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>; ++ reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; ++ rockchip,grf = <0x15a>; ++ #phy-cells = <0x00>; ++ #clock-cells = <0x00>; ++ status = "okay"; ++ phandle = <0xb6>; ++ }; ++ ++ phy@fed80000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x00 0xfed80000 0x00 0x10000>; ++ rockchip,u2phy-grf = <0x15b>; ++ rockchip,usb-grf = <0x5b>; ++ rockchip,usbdpphy-grf = <0x15c>; ++ rockchip,vo-grf = <0x15d>; ++ clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x15e>; ++ clock-names = "refclk\0immortal\0pclk\0utmi"; ++ resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>; ++ reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; ++ status = "okay"; ++ orientation-switch; ++ svid = <0xff01>; ++ sbu1-dc-gpios = <0xd4 0x0d 0x00>; ++ sbu2-dc-gpios = <0xd4 0x07 0x00>; ++ ++ dp-port { ++ #phy-cells = <0x00>; ++ status = "okay"; ++ phandle = <0xcd>; ++ }; ++ ++ u3-port { ++ #phy-cells = <0x00>; ++ status = "okay"; ++ phandle = <0x51>; ++ }; ++ ++ port { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ ++ endpoint@0 { ++ reg = <0x00>; ++ remote-endpoint = <0x15f>; ++ phandle = <0x122>; ++ }; ++ ++ endpoint@1 { ++ reg = <0x01>; ++ remote-endpoint = <0x160>; ++ phandle = <0x123>; ++ }; ++ }; ++ }; ++ ++ phy@feda0000 { ++ compatible = "rockchip,rk3588-mipi-dcphy"; ++ reg = <0x00 0xfeda0000 0x00 0x10000>; ++ rockchip,grf = <0x161>; ++ clocks = <0x02 0x108 0x02 0x2b6>; ++ clock-names = "pclk\0ref"; ++ resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>; ++ reset-names = "m_phy\0apb\0grf\0s_phy"; ++ #phy-cells = <0x00>; ++ status = "disabled"; ++ phandle = <0x28>; ++ }; ++ ++ phy@fedb0000 { ++ compatible = "rockchip,rk3588-mipi-dcphy"; ++ reg = <0x00 0xfedb0000 0x00 0x10000>; ++ rockchip,grf = <0x162>; ++ clocks = <0x02 0x109 0x02 0x2b6>; ++ clock-names = "pclk\0ref"; ++ resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>; ++ reset-names = "m_phy\0apb\0grf\0s_phy"; ++ #phy-cells = <0x00>; ++ status = "disabled"; ++ phandle = <0x29>; ++ }; ++ ++ csi2-dphy0-hw@fedc0000 { ++ compatible = "rockchip,rk3588-csi2-dphy-hw"; ++ reg = <0x00 0xfedc0000 0x00 0x8000>; ++ clocks = <0x02 0x10c>; ++ clock-names = "pclk"; ++ resets = <0x02 0x17 0x02 0x16>; ++ reset-names = "srst_csiphy0\0srst_p_csiphy0"; ++ rockchip,grf = <0x163>; ++ rockchip,sys_grf = <0xb3>; ++ status = "okay"; ++ phandle = <0x2a>; ++ }; ++ ++ phy@fee00000 { ++ compatible = "rockchip,rk3588-naneng-combphy"; ++ reg = <0x00 0xfee00000 0x00 0x100>; ++ #phy-cells = <0x01>; ++ clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>; ++ clock-names = "refclk\0apbclk\0phpclk"; ++ assigned-clocks = <0x02 0x2bd>; ++ assigned-clock-rates = <0x5f5e100>; ++ resets = <0x02 0x20005 0x02 0x4d6>; ++ reset-names = "combphy-apb\0combphy"; ++ rockchip,pipe-grf = <0x5d>; ++ rockchip,pipe-phy-grf = <0x164>; ++ status = "okay"; ++ phandle = <0xde>; ++ }; ++ ++ phy@fee20000 { ++ compatible = "rockchip,rk3588-naneng-combphy"; ++ reg = <0x00 0xfee20000 0x00 0x100>; ++ #phy-cells = <0x01>; ++ clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>; ++ clock-names = "refclk\0apbclk\0phpclk"; ++ assigned-clocks = <0x02 0x2bf>; ++ assigned-clock-rates = <0x5f5e100>; ++ resets = <0x02 0x20007 0x02 0x4d8>; ++ reset-names = "combphy-apb\0combphy"; ++ rockchip,pipe-grf = <0x5d>; ++ rockchip,pipe-phy-grf = <0x165>; ++ rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>; ++ status = "okay"; ++ phandle = <0x57>; ++ }; ++ ++ pinctrl { ++ compatible = "rockchip,rk3588-pinctrl"; ++ rockchip,grf = <0x166>; ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ phandle = <0x167>; ++ ++ gpio@fd8a0000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x00 0xfd8a0000 0x00 0x100>; ++ interrupts = <0x00 0x115 0x04>; ++ clocks = <0x02 0x284 0x02 0x285>; ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ gpio-ranges = <0x167 0x00 0x00 0x20>; ++ interrupt-controller; ++ #interrupt-cells = <0x02>; ++ phandle = <0xe5>; ++ }; ++ ++ gpio@fec20000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x00 0xfec20000 0x00 0x100>; ++ interrupts = <0x00 0x116 0x04>; ++ clocks = <0x02 0x7d 0x02 0x7e>; ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ gpio-ranges = <0x167 0x00 0x20 0x20>; ++ interrupt-controller; ++ #interrupt-cells = <0x02>; ++ phandle = <0x170>; ++ }; ++ ++ gpio@fec30000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x00 0xfec30000 0x00 0x100>; ++ interrupts = <0x00 0x117 0x04>; ++ clocks = <0x02 0x7f 0x02 0x80>; ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ gpio-ranges = <0x167 0x00 0x40 0x20>; ++ interrupt-controller; ++ #interrupt-cells = <0x02>; ++ }; ++ ++ gpio@fec40000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x00 0xfec40000 0x00 0x100>; ++ interrupts = <0x00 0x118 0x04>; ++ clocks = <0x02 0x81 0x02 0x82>; ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ gpio-ranges = <0x167 0x00 0x60 0x20>; ++ interrupt-controller; ++ #interrupt-cells = <0x02>; ++ phandle = <0x172>; ++ }; ++ ++ gpio@fec50000 { ++ compatible = "rockchip,gpio-bank"; ++ reg = <0x00 0xfec50000 0x00 0x100>; ++ interrupts = <0x00 0x119 0x04>; ++ clocks = <0x02 0x83 0x02 0x84>; ++ gpio-controller; ++ #gpio-cells = <0x02>; ++ gpio-ranges = <0x167 0x00 0x80 0x20>; ++ interrupt-controller; ++ #interrupt-cells = <0x02>; ++ phandle = <0xd4>; ++ }; ++ ++ pcfg-pull-up { ++ bias-pull-up; ++ phandle = <0x16b>; ++ }; ++ ++ pcfg-pull-none { ++ bias-disable; ++ phandle = <0x168>; ++ }; ++ ++ pcfg-pull-none-drv-level-2 { ++ bias-disable; ++ drive-strength = <0x02>; ++ phandle = <0x16d>; ++ }; ++ ++ pcfg-pull-up-drv-level-1 { ++ bias-pull-up; ++ drive-strength = <0x01>; ++ phandle = <0x16c>; ++ }; ++ ++ pcfg-pull-up-drv-level-2 { ++ bias-pull-up; ++ drive-strength = <0x02>; ++ phandle = <0x169>; ++ }; ++ ++ pcfg-pull-none-smt { ++ bias-disable; ++ input-schmitt-enable; ++ phandle = <0x16a>; ++ }; ++ ++ auddsm { ++ ++ auddsm-pins { ++ rockchip,pins = <0x03 0x01 0x04 0x168 0x03 0x02 0x04 0x168 0x03 0x03 0x04 0x168 0x03 0x04 0x04 0x168>; ++ phandle = <0x119>; ++ }; ++ }; ++ ++ bt1120 { ++ ++ bt1120-pins { ++ rockchip,pins = <0x04 0x08 0x02 0x168 0x04 0x00 0x02 0x168 0x04 0x01 0x02 0x168 0x04 0x02 0x02 0x168 0x04 0x03 0x02 0x168 0x04 0x04 0x02 0x168 0x04 0x05 0x02 0x168 0x04 0x06 0x02 0x168 0x04 0x07 0x02 0x168 0x04 0x0a 0x02 0x168 0x04 0x0b 0x02 0x168 0x04 0x0c 0x02 0x168 0x04 0x0d 0x02 0x168 0x04 0x0e 0x02 0x168 0x04 0x0f 0x02 0x168 0x04 0x10 0x02 0x168 0x04 0x11 0x02 0x168>; ++ phandle = <0x58>; ++ }; ++ }; ++ ++ can0 { ++ ++ can0m0-pins { ++ rockchip,pins = <0x00 0x10 0x0b 0x168 0x00 0x0f 0x0b 0x168>; ++ phandle = <0x11a>; ++ }; ++ }; ++ ++ can1 { ++ ++ can1m0-pins { ++ rockchip,pins = <0x03 0x0d 0x09 0x168 0x03 0x0e 0x09 0x168>; ++ phandle = <0x11b>; ++ }; ++ }; ++ ++ can2 { ++ ++ can2m0-pins { ++ rockchip,pins = <0x03 0x14 0x09 0x168 0x03 0x15 0x09 0x168>; ++ phandle = <0x11c>; ++ }; ++ }; ++ ++ gmac1 { ++ ++ gmac1-miim { ++ rockchip,pins = <0x03 0x12 0x01 0x168 0x03 0x13 0x01 0x168>; ++ phandle = <0xe6>; ++ }; ++ ++ gmac1-rx-bus2 { ++ rockchip,pins = <0x03 0x07 0x01 0x168 0x03 0x08 0x01 0x168 0x03 0x09 0x01 0x168>; ++ phandle = <0xe8>; ++ }; ++ ++ gmac1-tx-bus2 { ++ rockchip,pins = <0x03 0x0b 0x01 0x168 0x03 0x0c 0x01 0x168 0x03 0x0d 0x01 0x168>; ++ phandle = <0xe7>; ++ }; ++ ++ gmac1-rgmii-clk { ++ rockchip,pins = <0x03 0x05 0x01 0x168 0x03 0x04 0x01 0x168>; ++ phandle = <0xe9>; ++ }; ++ ++ gmac1-rgmii-bus { ++ rockchip,pins = <0x03 0x02 0x01 0x168 0x03 0x03 0x01 0x168 0x03 0x00 0x01 0x168 0x03 0x01 0x01 0x168>; ++ phandle = <0xea>; ++ }; ++ }; ++ ++ hdmi { ++ ++ hdmim0-tx0-cec { ++ rockchip,pins = <0x04 0x11 0x05 0x168>; ++ phandle = <0xd0>; ++ }; ++ ++ hdmim0-tx0-hpd { ++ rockchip,pins = <0x01 0x05 0x05 0x168>; ++ phandle = <0xd1>; ++ }; ++ ++ hdmim0-tx0-scl { ++ rockchip,pins = <0x04 0x0f 0x05 0x168>; ++ phandle = <0xd2>; ++ }; ++ ++ hdmim0-tx0-sda { ++ rockchip,pins = <0x04 0x10 0x05 0x168>; ++ phandle = <0xd3>; ++ }; ++ }; ++ ++ i2c0 { ++ ++ i2c0m2-xfer { ++ rockchip,pins = <0x00 0x19 0x03 0x16a 0x00 0x1a 0x03 0x16a>; ++ phandle = <0x5e>; ++ }; ++ }; ++ ++ i2c1 { ++ ++ i2c1m0-xfer { ++ rockchip,pins = <0x00 0x0d 0x09 0x16a 0x00 0x0e 0x09 0x16a>; ++ phandle = <0x11d>; ++ }; ++ }; ++ ++ i2c2 { ++ ++ i2c2m0-xfer { ++ rockchip,pins = <0x00 0x0f 0x09 0x16a 0x00 0x10 0x09 0x16a>; ++ phandle = <0x11e>; ++ }; ++ }; ++ ++ i2c3 { ++ ++ i2c3m0-xfer { ++ rockchip,pins = <0x01 0x11 0x09 0x16a 0x01 0x10 0x09 0x16a>; ++ phandle = <0x125>; ++ }; ++ }; ++ ++ i2c4 { ++ ++ i2c4m3-xfer { ++ rockchip,pins = <0x01 0x03 0x09 0x16a 0x01 0x02 0x09 0x16a>; ++ phandle = <0x127>; ++ }; ++ }; ++ ++ i2c5 { ++ ++ i2c5m0-xfer { ++ rockchip,pins = <0x03 0x17 0x09 0x16a 0x03 0x18 0x09 0x16a>; ++ phandle = <0x128>; ++ }; ++ }; ++ ++ i2c6 { ++ ++ i2c6m3-xfer { ++ rockchip,pins = <0x04 0x09 0x09 0x16a 0x04 0x08 0x09 0x16a>; ++ phandle = <0x152>; ++ }; ++ }; ++ ++ i2c7 { ++ ++ i2c7m2-xfer { ++ rockchip,pins = <0x03 0x1a 0x09 0x16a 0x03 0x1b 0x09 0x16a>; ++ phandle = <0x153>; ++ }; ++ }; ++ ++ i2c8 { ++ ++ i2c8m0-xfer { ++ rockchip,pins = <0x04 0x1a 0x09 0x16a 0x04 0x1b 0x09 0x16a>; ++ phandle = <0x156>; ++ }; ++ }; ++ ++ i2s0 { ++ ++ i2s0-lrck { ++ rockchip,pins = <0x01 0x15 0x01 0x168>; ++ phandle = <0xf5>; ++ }; ++ ++ i2s0-mclk { ++ rockchip,pins = <0x01 0x12 0x01 0x168>; ++ phandle = <0x126>; ++ }; ++ ++ i2s0-sclk { ++ rockchip,pins = <0x01 0x13 0x01 0x168>; ++ phandle = <0xf6>; ++ }; ++ ++ i2s0-sdi0 { ++ rockchip,pins = <0x01 0x1c 0x02 0x168>; ++ phandle = <0xf7>; ++ }; ++ ++ i2s0-sdo0 { ++ rockchip,pins = <0x01 0x17 0x01 0x168>; ++ phandle = <0xf8>; ++ }; ++ }; ++ ++ i2s1 { ++ ++ i2s1m0-lrck { ++ rockchip,pins = <0x04 0x02 0x03 0x168>; ++ phandle = <0xf9>; ++ }; ++ ++ i2s1m0-sclk { ++ rockchip,pins = <0x04 0x01 0x03 0x168>; ++ phandle = <0xfa>; ++ }; ++ ++ i2s1m0-sdi0 { ++ rockchip,pins = <0x04 0x05 0x03 0x168>; ++ phandle = <0xfb>; ++ }; ++ ++ i2s1m0-sdi1 { ++ rockchip,pins = <0x04 0x06 0x03 0x168>; ++ phandle = <0xfc>; ++ }; ++ ++ i2s1m0-sdi2 { ++ rockchip,pins = <0x04 0x07 0x03 0x168>; ++ phandle = <0xfd>; ++ }; ++ ++ i2s1m0-sdi3 { ++ rockchip,pins = <0x04 0x08 0x03 0x168>; ++ phandle = <0xfe>; ++ }; ++ ++ i2s1m0-sdo0 { ++ rockchip,pins = <0x04 0x09 0x03 0x168>; ++ phandle = <0xff>; ++ }; ++ ++ i2s1m0-sdo1 { ++ rockchip,pins = <0x04 0x0a 0x03 0x168>; ++ phandle = <0x100>; ++ }; ++ ++ i2s1m0-sdo2 { ++ rockchip,pins = <0x04 0x0b 0x03 0x168>; ++ phandle = <0x101>; ++ }; ++ ++ i2s1m0-sdo3 { ++ rockchip,pins = <0x04 0x0c 0x03 0x168>; ++ phandle = <0x102>; ++ }; ++ }; ++ ++ i2s2 { ++ ++ i2s2m1-lrck { ++ rockchip,pins = <0x03 0x0e 0x03 0x168>; ++ phandle = <0x103>; ++ }; ++ ++ i2s2m1-sclk { ++ rockchip,pins = <0x03 0x0d 0x03 0x168>; ++ phandle = <0x104>; ++ }; ++ ++ i2s2m1-sdi { ++ rockchip,pins = <0x03 0x0a 0x03 0x168>; ++ phandle = <0x105>; ++ }; ++ ++ i2s2m1-sdo { ++ rockchip,pins = <0x03 0x0b 0x03 0x168>; ++ phandle = <0x106>; ++ }; ++ }; ++ ++ i2s3 { ++ ++ i2s3-lrck { ++ rockchip,pins = <0x03 0x02 0x03 0x168>; ++ phandle = <0x107>; ++ }; ++ ++ i2s3-sclk { ++ rockchip,pins = <0x03 0x01 0x03 0x168>; ++ phandle = <0x108>; ++ }; ++ ++ i2s3-sdi { ++ rockchip,pins = <0x03 0x04 0x03 0x168>; ++ phandle = <0x109>; ++ }; ++ ++ i2s3-sdo { ++ rockchip,pins = <0x03 0x03 0x03 0x168>; ++ phandle = <0x10a>; ++ }; ++ }; ++ ++ mipi { ++ ++ mipim1-camera1-clk { ++ rockchip,pins = <0x03 0x06 0x04 0x168>; ++ phandle = <0x154>; ++ }; ++ }; ++ ++ pdm0 { ++ ++ pdm0m0-clk { ++ rockchip,pins = <0x01 0x16 0x03 0x168>; ++ phandle = <0x10b>; ++ }; ++ ++ pdm0m0-clk1 { ++ rockchip,pins = <0x01 0x14 0x03 0x168>; ++ phandle = <0x10c>; ++ }; ++ ++ pdm0m0-sdi0 { ++ rockchip,pins = <0x01 0x1d 0x03 0x168>; ++ phandle = <0x10d>; ++ }; ++ ++ pdm0m0-sdi1 { ++ rockchip,pins = <0x01 0x19 0x03 0x168>; ++ phandle = <0x10e>; ++ }; ++ ++ pdm0m0-sdi2 { ++ rockchip,pins = <0x01 0x1a 0x03 0x168>; ++ phandle = <0x10f>; ++ }; ++ ++ pdm0m0-sdi3 { ++ rockchip,pins = <0x01 0x1b 0x03 0x168>; ++ phandle = <0x110>; ++ }; ++ }; ++ ++ pdm1 { ++ ++ pdm1m0-clk { ++ rockchip,pins = <0x04 0x1d 0x02 0x168>; ++ phandle = <0x111>; ++ }; ++ ++ pdm1m0-clk1 { ++ rockchip,pins = <0x04 0x1c 0x02 0x168>; ++ phandle = <0x112>; ++ }; ++ ++ pdm1m0-sdi0 { ++ rockchip,pins = <0x04 0x1b 0x02 0x168>; ++ phandle = <0x113>; ++ }; ++ ++ pdm1m0-sdi1 { ++ rockchip,pins = <0x04 0x1a 0x02 0x168>; ++ phandle = <0x114>; ++ }; ++ ++ pdm1m0-sdi2 { ++ rockchip,pins = <0x04 0x19 0x02 0x168>; ++ phandle = <0x115>; ++ }; ++ ++ pdm1m0-sdi3 { ++ rockchip,pins = <0x04 0x18 0x02 0x168>; ++ phandle = <0x116>; ++ }; ++ }; ++ ++ pmic { ++ ++ pmic-pins { ++ rockchip,pins = <0x00 0x07 0x00 0x16b 0x00 0x02 0x01 0x168 0x00 0x03 0x01 0x168 0x00 0x11 0x01 0x168 0x00 0x12 0x01 0x168 0x00 0x13 0x01 0x168 0x00 0x1e 0x01 0x168>; ++ phandle = <0x130>; ++ }; ++ }; ++ ++ pwm0 { ++ ++ pwm0m0-pins { ++ rockchip,pins = <0x00 0x0f 0x03 0x168>; ++ phandle = <0x62>; ++ }; ++ }; ++ ++ pwm1 { ++ ++ pwm1m0-pins { ++ rockchip,pins = <0x00 0x10 0x03 0x168>; ++ phandle = <0x63>; ++ }; ++ }; ++ ++ pwm2 { ++ ++ pwm2m0-pins { ++ rockchip,pins = <0x00 0x14 0x03 0x168>; ++ phandle = <0x64>; ++ }; ++ }; ++ ++ pwm3 { ++ ++ pwm3m0-pins { ++ rockchip,pins = <0x00 0x1c 0x03 0x168>; ++ phandle = <0x65>; ++ }; ++ }; ++ ++ pwm4 { ++ ++ pwm4m0-pins { ++ rockchip,pins = <0x00 0x15 0x0b 0x168>; ++ phandle = <0x143>; ++ }; ++ }; ++ ++ pwm5 { ++ ++ pwm5m0-pins { ++ rockchip,pins = <0x00 0x09 0x03 0x168>; ++ phandle = <0x144>; ++ }; ++ }; ++ ++ pwm6 { ++ ++ pwm6m0-pins { ++ rockchip,pins = <0x00 0x17 0x0b 0x168>; ++ phandle = <0x145>; ++ }; ++ }; ++ ++ pwm7 { ++ ++ pwm7m0-pins { ++ rockchip,pins = <0x00 0x18 0x0b 0x168>; ++ phandle = <0x146>; ++ }; ++ }; ++ ++ pwm8 { ++ ++ pwm8m0-pins { ++ rockchip,pins = <0x03 0x07 0x0b 0x168>; ++ phandle = <0x147>; ++ }; ++ }; ++ ++ pwm9 { ++ ++ pwm9m0-pins { ++ rockchip,pins = <0x03 0x08 0x0b 0x168>; ++ phandle = <0x148>; ++ }; ++ }; ++ ++ pwm10 { ++ ++ pwm10m0-pins { ++ rockchip,pins = <0x03 0x00 0x0b 0x168>; ++ phandle = <0x149>; ++ }; ++ }; ++ ++ pwm11 { ++ ++ pwm11m3-pins { ++ rockchip,pins = <0x03 0x1d 0x0b 0x168>; ++ phandle = <0x14a>; ++ }; ++ }; ++ ++ pwm12 { ++ ++ pwm12m0-pins { ++ rockchip,pins = <0x03 0x0d 0x0b 0x168>; ++ phandle = <0x14b>; ++ }; ++ }; ++ ++ pwm13 { ++ ++ pwm13m0-pins { ++ rockchip,pins = <0x03 0x0e 0x0b 0x168>; ++ phandle = <0x14c>; ++ }; ++ }; ++ ++ pwm14 { ++ ++ pwm14m0-pins { ++ rockchip,pins = <0x03 0x12 0x0b 0x168>; ++ phandle = <0x14d>; ++ }; ++ }; ++ ++ pwm15 { ++ ++ pwm15m0-pins { ++ rockchip,pins = <0x03 0x13 0x0b 0x168>; ++ phandle = <0x14e>; ++ }; ++ }; ++ ++ sata { ++ ++ sata-reset { ++ rockchip,pins = <0x03 0x19 0x00 0x16b>; ++ phandle = <0xec>; ++ }; ++ }; ++ ++ sdio { ++ ++ sdiom1-pins { ++ rockchip,pins = <0x03 0x05 0x02 0x168 0x03 0x04 0x02 0x16b 0x03 0x00 0x02 0x16b 0x03 0x01 0x02 0x16b 0x03 0x02 0x02 0x16b 0x03 0x03 0x02 0x16b>; ++ phandle = <0xf3>; ++ }; ++ }; ++ ++ sdmmc { ++ ++ sdmmc-bus4 { ++ rockchip,pins = <0x04 0x18 0x01 0x169 0x04 0x19 0x01 0x169 0x04 0x1a 0x01 0x169 0x04 0x1b 0x01 0x169>; ++ phandle = <0xf0>; ++ }; ++ ++ sdmmc-clk { ++ rockchip,pins = <0x04 0x1d 0x01 0x169>; ++ phandle = <0xed>; ++ }; ++ ++ sdmmc-cmd { ++ rockchip,pins = <0x04 0x1c 0x01 0x169>; ++ phandle = <0xee>; ++ }; ++ ++ sdmmc-det { ++ rockchip,pins = <0x00 0x04 0x01 0x16b>; ++ phandle = <0xef>; ++ }; ++ }; ++ ++ spdif0 { ++ ++ spdif0m0-tx { ++ rockchip,pins = <0x01 0x0e 0x03 0x168>; ++ phandle = <0x117>; ++ }; ++ }; ++ ++ spdif1 { ++ ++ spdif1m0-tx { ++ rockchip,pins = <0x01 0x0f 0x03 0x168>; ++ phandle = <0x118>; ++ }; ++ }; ++ ++ spi0 { ++ ++ spi0m0-pins { ++ rockchip,pins = <0x00 0x16 0x08 0x16c 0x00 0x17 0x08 0x16c 0x00 0x10 0x08 0x16c>; ++ phandle = <0x12b>; ++ }; ++ ++ spi0m0-cs0 { ++ rockchip,pins = <0x00 0x19 0x08 0x16c>; ++ phandle = <0x129>; ++ }; ++ ++ spi0m0-cs1 { ++ rockchip,pins = <0x00 0x0f 0x08 0x16c>; ++ phandle = <0x12a>; ++ }; ++ }; ++ ++ spi1 { ++ ++ spi1m2-pins { ++ rockchip,pins = <0x01 0x1a 0x08 0x16c 0x01 0x18 0x08 0x16c 0x01 0x19 0x08 0x16c>; ++ phandle = <0x12d>; ++ }; ++ ++ spi1m2-cs0 { ++ rockchip,pins = <0x01 0x1b 0x08 0x16c>; ++ phandle = <0x12c>; ++ }; ++ }; ++ ++ spi2 { ++ ++ spi2m2-pins { ++ rockchip,pins = <0x00 0x05 0x01 0x16c 0x00 0x0b 0x01 0x16c 0x00 0x06 0x01 0x16c>; ++ phandle = <0x12f>; ++ }; ++ ++ spi2m2-cs0 { ++ rockchip,pins = <0x00 0x09 0x01 0x16c>; ++ phandle = <0x12e>; ++ }; ++ }; ++ ++ spi3 { ++ ++ spi3m1-pins { ++ rockchip,pins = <0x04 0x0f 0x08 0x16c 0x04 0x0d 0x08 0x16c 0x04 0x0e 0x08 0x16c>; ++ phandle = <0x139>; ++ }; ++ ++ spi3m1-cs0 { ++ rockchip,pins = <0x04 0x10 0x08 0x16c>; ++ phandle = <0x137>; ++ }; ++ ++ spi3m1-cs1 { ++ rockchip,pins = <0x04 0x11 0x08 0x16c>; ++ phandle = <0x138>; ++ }; ++ }; ++ ++ spi4 { ++ ++ spi4m0-pins { ++ rockchip,pins = <0x01 0x12 0x08 0x16c 0x01 0x10 0x08 0x16c 0x01 0x11 0x08 0x16c>; ++ phandle = <0x159>; ++ }; ++ ++ spi4m0-cs0 { ++ rockchip,pins = <0x01 0x13 0x08 0x16c>; ++ phandle = <0x157>; ++ }; ++ ++ spi4m0-cs1 { ++ rockchip,pins = <0x01 0x14 0x08 0x16c>; ++ phandle = <0x158>; ++ }; ++ }; ++ ++ tsadc { ++ ++ tsadc-shut { ++ rockchip,pins = <0x00 0x01 0x02 0x168>; ++ phandle = <0x150>; ++ }; ++ }; ++ ++ uart0 { ++ ++ uart0m1-xfer { ++ rockchip,pins = <0x00 0x08 0x04 0x16b 0x00 0x09 0x04 0x16b>; ++ phandle = <0x61>; ++ }; ++ }; ++ ++ uart1 { ++ ++ uart1m1-xfer { ++ rockchip,pins = <0x01 0x0f 0x0a 0x16b 0x01 0x0e 0x0a 0x16b>; ++ phandle = <0x13a>; ++ }; ++ }; ++ ++ uart2 { ++ ++ uart2m0-xfer { ++ rockchip,pins = <0x00 0x0e 0x0a 0x16b 0x00 0x0d 0x0a 0x16b>; ++ phandle = <0x16f>; ++ }; ++ ++ uart2m1-xfer { ++ rockchip,pins = <0x04 0x19 0x0a 0x16b 0x04 0x18 0x0a 0x16b>; ++ phandle = <0x13b>; ++ }; ++ }; ++ ++ uart3 { ++ ++ uart3m1-xfer { ++ rockchip,pins = <0x03 0x0e 0x0a 0x16b 0x03 0x0d 0x0a 0x16b>; ++ phandle = <0x13c>; ++ }; ++ }; ++ ++ uart4 { ++ ++ uart4m1-xfer { ++ rockchip,pins = <0x03 0x18 0x0a 0x16b 0x03 0x19 0x0a 0x16b>; ++ phandle = <0x13d>; ++ }; ++ }; ++ ++ uart5 { ++ ++ uart5m1-xfer { ++ rockchip,pins = <0x03 0x15 0x0a 0x16b 0x03 0x14 0x0a 0x16b>; ++ phandle = <0x13e>; ++ }; ++ }; ++ ++ uart6 { ++ ++ uart6m1-xfer { ++ rockchip,pins = <0x01 0x00 0x0a 0x16b 0x01 0x01 0x0a 0x16b>; ++ phandle = <0x13f>; ++ }; ++ }; ++ ++ uart7 { ++ ++ uart7m2-xfer { ++ rockchip,pins = <0x01 0x0c 0x0a 0x16b 0x01 0x0d 0x0a 0x16b>; ++ phandle = <0x140>; ++ }; ++ }; ++ ++ uart8 { ++ ++ uart8m1-xfer { ++ rockchip,pins = <0x03 0x03 0x0a 0x16b 0x03 0x02 0x0a 0x16b>; ++ phandle = <0x141>; ++ }; ++ }; ++ ++ uart9 { ++ ++ uart9m1-xfer { ++ rockchip,pins = <0x04 0x0d 0x0a 0x16b 0x04 0x0c 0x0a 0x16b>; ++ phandle = <0x142>; ++ }; ++ }; ++ ++ gpio-func { ++ ++ tsadc-gpio-func { ++ rockchip,pins = <0x00 0x01 0x00 0x168>; ++ phandle = <0x14f>; ++ }; ++ }; ++ ++ leds { ++ ++ led-user { ++ rockchip,pins = <0x03 0x0a 0x00 0x168>; ++ phandle = <0x173>; ++ }; ++ ++ led-power { ++ rockchip,pins = <0x01 0x1d 0x00 0x168>; ++ phandle = <0x171>; ++ }; ++ ++ led-user1 { ++ rockchip,pins = <0x03 0x10 0x00 0x168>; ++ phandle = <0x174>; ++ }; ++ }; ++ ++ headphone { ++ ++ hp-det { ++ rockchip,pins = <0x01 0x06 0x00 0x168>; ++ phandle = <0x17e>; ++ }; ++ }; ++ ++ hym8563 { ++ ++ hym8563-int { ++ rockchip,pins = <0x00 0x08 0x00 0x16b>; ++ phandle = <0x124>; ++ }; ++ }; ++ ++ usb { ++ ++ vcc5v0-host-en { ++ rockchip,pins = <0x01 0x0e 0x00 0x168>; ++ phandle = <0x180>; ++ }; ++ }; ++ ++ usb-typec { ++ ++ usbc0-int { ++ rockchip,pins = <0x00 0x14 0x00 0x16b>; ++ phandle = <0x11f>; ++ }; ++ ++ typec5v-pwren { ++ rockchip,pins = <0x01 0x09 0x00 0x168>; ++ phandle = <0x181>; ++ }; ++ }; ++ ++ cam { ++ ++ mipidphy0-pwr { ++ rockchip,pins = <0x01 0x09 0x00 0x168>; ++ phandle = <0x184>; ++ }; ++ }; ++ }; ++ ++ test-power { ++ status = "okay"; ++ }; ++ ++ vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0xb71b00>; ++ regulator-max-microvolt = <0xb71b00>; ++ phandle = <0x16e>; ++ }; ++ ++ vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x4c4b40>; ++ regulator-max-microvolt = <0x4c4b40>; ++ vin-supply = <0x16e>; ++ phandle = <0x5f>; ++ }; ++ ++ vcc5v0-usbdcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usbdcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x4c4b40>; ++ regulator-max-microvolt = <0x4c4b40>; ++ vin-supply = <0x16e>; ++ }; ++ ++ vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x4c4b40>; ++ regulator-max-microvolt = <0x4c4b40>; ++ vin-supply = <0x16e>; ++ phandle = <0x17f>; ++ }; ++ ++ vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <0x10c8e0>; ++ regulator-max-microvolt = <0x10c8e0>; ++ vin-supply = <0x5f>; ++ phandle = <0x136>; ++ }; ++ ++ chosen { ++ bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 rw rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1"; ++ }; ++ ++ cspmu@fd10c000 { ++ compatible = "rockchip,cspmu"; ++ reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>; ++ }; ++ ++ debug@fd104000 { ++ compatible = "rockchip,debug"; ++ reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>; ++ }; ++ ++ fiq-debugger { ++ compatible = "rockchip,fiq-debugger"; ++ rockchip,serial-id = <0x02>; ++ rockchip,wake-irq = <0x00>; ++ rockchip,irq-mode-enable = <0x01>; ++ rockchip,baudrate = <0x16e360>; ++ interrupts = <0x00 0x1a7 0x08>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x16f>; ++ status = "okay"; ++ }; ++ ++ ramoops@110000 { ++ compatible = "ramoops"; ++ reg = <0x00 0x110000 0x00 0xf0000>; ++ record-size = <0x20000>; ++ console-size = <0x80000>; ++ ftrace-size = <0x00>; ++ pmsg-size = <0x50000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ ranges; ++ ++ cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x00 0x800000>; ++ linux,cma-default; ++ }; ++ ++ drm-logo@00000000 { ++ compatible = "rockchip,drm-logo"; ++ reg = <0x00 0x00 0x00 0x00>; ++ phandle = <0x2e>; ++ }; ++ ++ drm-cubic-lut@00000000 { ++ compatible = "rockchip,drm-cubic-lut"; ++ reg = <0x00 0x00 0x00 0x00>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ status = "okay"; ++ ++ power { ++ label = ":power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <0x170 0x1d 0x00>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x171>; ++ }; ++ ++ user { ++ label = ":user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <0x172 0x0a 0x00>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x173>; ++ }; ++ ++ user1 { ++ label = ":user1"; ++ default-state = "off"; ++ gpios = <0x172 0x10 0x00>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x174>; ++ }; ++ }; ++ ++ hdmi0-sound { ++ status = "okay"; ++ compatible = "rockchip,hdmi"; ++ rockchip,mclk-fs = <0x80>; ++ rockchip,card-name = "rockchip-hdmi0"; ++ rockchip,cpu = <0x175>; ++ rockchip,codec = <0x176>; ++ rockchip,jack-det; ++ }; ++ ++ dp0-sound { ++ status = "okay"; ++ compatible = "rockchip,hdmi"; ++ rockchip,card-name = "rockchip,dp0"; ++ rockchip,mclk-fs = <0x200>; ++ rockchip,cpu = <0x177>; ++ rockchip,codec = <0x178 0x01>; ++ rockchip,jack-det; ++ }; ++ ++ spdif-tx1-dc { ++ status = "disabled"; ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0x00>; ++ phandle = <0x17a>; ++ }; ++ ++ spdif-tx1-sound { ++ status = "disabled"; ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "rockchip,spdif-tx1"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <0x179>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <0x17a>; ++ }; ++ }; ++ ++ adc-keys { ++ status = "okay"; ++ compatible = "adc-keys"; ++ io-channels = <0x17b 0x01>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <0x1b7740>; ++ poll-interval = <0x64>; ++ ++ recovery-key { ++ label = "F12"; ++ linux,code = <0x58>; ++ press-threshold-microvolt = <0x4268>; ++ }; ++ }; ++ ++ es8388-sound { ++ status = "okay"; ++ compatible = "firefly,multicodecs-card"; ++ rockchip,card-name = "rockchip-es8388"; ++ hp-det-gpio = <0x170 0x06 0x01>; ++ io-channels = <0x17b 0x05>; ++ io-channel-names = "hw-ver"; ++ hp-con-gpio = <0x170 0x04 0x00>; ++ linein-type = <0x01>; ++ rockchip,format = "i2s"; ++ rockchip,mclk-fs = <0x100>; ++ rockchip,cpu = <0x17c>; ++ rockchip,codec = <0x17d>; ++ rockchip,audio-routing = "Headphone\0LOUT2\0Headphone\0ROUT2\0Speaker\0LOUT1\0Speaker\0ROUT1\0Headphone\0Headphone Power\0Headphone\0Headphone Power\0LINPUT1\0Main Mic\0LINPUT2\0Main Mic\0RINPUT1\0Headset Mic\0RINPUT2\0Headset Mic"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x17e>; ++ }; ++ ++ vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-boot-on; ++ regulator-always-on; ++ enable-active-high; ++ gpio = <0x170 0x0e 0x00>; ++ vin-supply = <0x17f>; ++ status = "okay"; ++ reset-delay-us = <0x30d40>; ++ startup-delay-us = <0x124f80>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x180>; ++ phandle = <0x5c>; ++ }; ++ ++ vcc-hub-reset-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_hub_reset"; ++ regulator-boot-on; ++ regulator-always-on; ++ enable-active-high; ++ status = "okay"; ++ gpio = <0x170 0x08 0x00>; ++ }; ++ ++ vbus5v0-typec-pwr-en-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vbus5v0_typec_pwr_en"; ++ enable-active-high; ++ status = "okay"; ++ gpio = <0x170 0x09 0x00>; ++ regulator-min-microvolt = <0x4c4b40>; ++ regulator-max-microvolt = <0x4c4b40>; ++ vin-supply = <0x17f>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x181>; ++ phandle = <0x120>; ++ }; ++ ++ pwm-fan { ++ compatible = "pwm-fan"; ++ #cooling-cells = <0x02>; ++ fan-supply = <0x16e>; ++ pwms = <0x182 0x00 0xc350 0x01>; ++ }; ++ ++ vcc3v3-pcie20 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie20"; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ regulator-always-on; ++ enable-active-high; ++ gpios = <0x170 0x1f 0x00>; ++ startup-delay-us = <0x1388>; ++ vin-supply = <0x16e>; ++ }; ++ ++ vcc-3v3-sd-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_3v3_sd_s0"; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ gpios = <0x170 0x00 0x01>; ++ enable-active-low; ++ vin-supply = <0x183>; ++ phandle = <0xf2>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ lcd_rst { ++ status = "disabled"; ++ compatible = "regulator-fixed"; ++ regulator-name = "lcd_rst"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ enable-active-high; ++ gpio = <0x170 0x01 0x00>; ++ startup-delay-us = <0x7d0>; ++ vin-supply = <0x16e>; ++ }; ++ ++ lcd_en { ++ status = "disabled"; ++ compatible = "regulator-fixed"; ++ regulator-name = "lcd_en"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <0x325aa0>; ++ regulator-max-microvolt = <0x325aa0>; ++ enable-active-high; ++ gpio = <0x170 0x0b 0x00>; ++ vin-supply = <0x16e>; ++ }; ++ ++ firefly_wake { ++ compatible = "firefly-wake"; ++ status = "okay"; ++ }; ++ ++ cam_ircut { ++ status = "disabled"; ++ compatible = "rockchip,ircut"; ++ ircut-open-gpios = <0xd4 0x06 0x00>; ++ ircut-close-gpios = <0xd4 0x07 0x00>; ++ rockchip,camera-module-index = <0x00>; ++ rockchip,camera-module-facing = "back"; ++ }; ++ ++ vcc-mipidcphy0-regulator { ++ status = "disabled"; ++ compatible = "regulator-fixed"; ++ gpio = <0x170 0x09 0x00>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <0x184>; ++ regulator-name = "vcc_mipidphy0"; ++ enable-active-high; ++ }; ++}; +diff --git a/roc-rk3588s-pc.dts b/roc-rk3588s-pc.dts +new file mode 100644 +index 000000000..e69de29bb +-- +2.25.1 + diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler-rt.bbappend b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler-rt.bbappend index cecd19350f0..87f94f55478 100644 --- a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler-rt.bbappend +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler-rt.bbappend @@ -9,4 +9,4 @@ SRC_URI:remove:rockchip = " \ " #add COMPATIBLE_MACHINE -COMPATIBLE_MACHINE = "ok3568|ryd-3568|ok3588|ok3399" +COMPATIBLE_MACHINE = "ok3568|ryd-3568|ok3588|ok3399|roc-rk3588s-pc" diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler.bbappend b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler.bbappend index e71ec5a929c..143e5062b73 100644 --- a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler.bbappend +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-openeuler.bbappend @@ -1,4 +1,4 @@ require recipes-kernel/linux/linux-rockchip.inc # add COMPATIBLE_MACHINE -COMPATIBLE_MACHINE = "ok3568|ryd-3568|ok3588|ok3399|orangepi4-lts" +COMPATIBLE_MACHINE = "ok3568|ryd-3568|ok3588|ok3399|orangepi4-lts|roc-rk3588s-pc" diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-rockchip.inc b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-rockchip.inc index 962f3248c88..141fc091a61 100644 --- a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-rockchip.inc +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/linux-rockchip.inc @@ -28,6 +28,11 @@ SRC_URI:append = " \ ${@bb.utils.contains('MCS_FEATURES', 'openamp', 'file://patches/0003-ok3568-support-mcs.patch', '', d)} \ " +# patches for roc-rk3588s-pc +SRC_URI:append:roc-rk3588s-pc = " \ + file://patches/0001-roc-rk3588s-pc-dts.patch \ +" + # more support of device is coming. so we documented this patch md5sum. SRC_URI[rockchip-kernel-patch.md5sum] = "8ee3af4d73b122ca17f536788e87cef6" diff --git a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/rockchip-kernel.bb b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/rockchip-kernel.bb index 37d8785460c..5953ec1d631 100644 --- a/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/rockchip-kernel.bb +++ b/bsp/meta-openeuler-bsp/rockchip/recipes-kernel/linux/rockchip-kernel.bb @@ -2,7 +2,7 @@ require recipes-kernel/linux/linux-openeuler.inc FILESEXTRAPATHS:append := "${THISDIR}/files/:" -OPENEULER_KERNEL_CONFIG = "" +# OPENEULER_KERNEL_CONFIG = "" SRC_URI:remove = "file://patches/${ARCH}/0001-arm64-add-zImage-support-for-arm64.patch" # For orangepi5, use rockchip-kernel -- Gitee