From dce78d5084dd8f503dc941324a2fd3dfa48b2916 Mon Sep 17 00:00:00 2001 From: Wanming Hu Date: Tue, 2 Sep 2025 22:03:39 +0800 Subject: [PATCH] mcs: support mcs baremetal on hieulerpi1 * Support MCS feature for hieulerpi1, and pack needed RTOS conf/elf. * Reserve memory for mcs in hieulerpi dts. * Export cpu_logical_map symbol in linux, so that mcs_km does not rely on kprobe anymore. * Since bootargs of hieulerpi will always be modified by uboot, we could not use maxcpus to turn mcs cpu offline. Therefore we add mcs-script to handle cpu offlining in init scripts. Signed-off-by: Wanming Hu --- .oebuild/features/mcs.yaml | 2 +- .../conf/machine/hieulerpi1.conf | 2 + .../linux/files/dtbs/ss928-pi_mcs.dts | 1190 +++++++++++++++++ .../recipes-kernel/linux/linux-hieulerpi1.inc | 4 +- .../packagegroups/packagegroup-mcs.bb | 1 + ...xport-cpu_logical_map-symbol-for-mcs.patch | 31 + .../recipes-kernel/linux/linux-openeuler.inc | 4 + .../mcs-linux/files/mcs_cpu_offline.sh | 2 + .../recipes-mcs/mcs-linux/mcs-script.bb | 47 + .../recipes-mcs/mcs-linux/mcsctl.bb | 1 + 10 files changed, 1282 insertions(+), 2 deletions(-) create mode 100644 bsp/meta-hisilicon/recipes-kernel/linux/files/dtbs/ss928-pi_mcs.dts create mode 100644 meta-openeuler/recipes-kernel/linux/files/meta-data/features/mcs/0005-arm64-cpu-export-cpu_logical_map-symbol-for-mcs.patch create mode 100644 meta-openeuler/recipes-mcs/mcs-linux/files/mcs_cpu_offline.sh create mode 100644 meta-openeuler/recipes-mcs/mcs-linux/mcs-script.bb diff --git a/.oebuild/features/mcs.yaml b/.oebuild/features/mcs.yaml index d3b7d0186dd..1c7da196562 100644 --- a/.oebuild/features/mcs.yaml +++ b/.oebuild/features/mcs.yaml @@ -1,6 +1,6 @@ type: feature -support: qemu-aarch64|raspberrypi4-64|hi3093|ok3568|kp920|x86-64 +support: qemu-aarch64|raspberrypi4-64|hi3093|ok3568|kp920|x86-64|hieulerpi1 layers: - yocto-meta-openeuler/rtos/meta-openeuler-rtos diff --git a/bsp/meta-hisilicon/conf/machine/hieulerpi1.conf b/bsp/meta-hisilicon/conf/machine/hieulerpi1.conf index b92f07d58df..7eb5927b124 100644 --- a/bsp/meta-hisilicon/conf/machine/hieulerpi1.conf +++ b/bsp/meta-hisilicon/conf/machine/hieulerpi1.conf @@ -27,3 +27,5 @@ IMAGE_INSTALL:append = " kernel-modules" KERNEL_MODULE_AUTOLOAD = "" USE_VT ?= "0" +# prepare env for mcs +MCS_CPUID_OFFLINE = "3" diff --git a/bsp/meta-hisilicon/recipes-kernel/linux/files/dtbs/ss928-pi_mcs.dts b/bsp/meta-hisilicon/recipes-kernel/linux/files/dtbs/ss928-pi_mcs.dts new file mode 100644 index 00000000000..99d60a8b8f6 --- /dev/null +++ b/bsp/meta-hisilicon/recipes-kernel/linux/files/dtbs/ss928-pi_mcs.dts @@ -0,0 +1,1190 @@ +/dts-v1/; + +/memreserve/ 0x0000000052fff000 0x0000000001a02000; +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + interrupt-parent = <0x1>; + model = "Vendor SS928V100 DEMO Board"; + compatible = "vendor,ss928v100"; + + interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x0>; + interrupt-controller; + reg = <0x0 0x12400000 0x0 0x10000 0x0 0x12440000 0x0 0x140000>; + phandle = <0x1>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x1 0x17 0xf04>; + }; + + clock0 { + compatible = "vendor,ss928v100_clock", "syscon"; + #clock-cells = <0x1>; + #reset-cells = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0 0x11010000 0x0 0x44a0>; + phandle = <0x5>; + }; + + smmu_npu@14040000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x14040000 0x0 0x40000>; + interrupts = <0x0 0x7d 0x4>; + interrupt-names = "combined"; + #iommu-cells = <0x1>; + vendor,broken-prefetch-cmd; + phandle = <0x2>; + }; + + svm_npu@14020000 { + compatible = "vendor,svm"; + crg-base = <0x11010000>; + crg-size = <0x10000>; + npu_crg_6560 = <0x6680>; + ranges; + #size-cells = <0x2>; + #address-cells = <0x2>; + + svm_aicore { + reg = <0x0 0x14020000 0x0 0x10000>; + iommus = <0x2 0x1>; + dma-can-stall; + pasid-num-bits = <0x10>; + }; + }; + + smmu_pqp@0x15410000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x15410000 0x0 0x40000>; + interrupts = <0x0 0xb9 0x4>; + interrupt-names = "combined"; + #iommu-cells = <0x1>; + vendor,broken-prefetch-cmd; + phandle = <0x3>; + }; + + svm_pqp@15400000 { + compatible = "vendor,svm"; + ranges; + #size-cells = <0x2>; + #address-cells = <0x2>; + crg-base = <0x11010000>; + crg-size = <0x10000>; + pqp_crg_6592 = <0x6700>; + + svm_aicore { + reg = <0x0 0x15400000 0x0 0x10000>; + iommus = <0x3 0x1>; + dma-can-stall; + pasid-num-bits = <0x10>; + }; + + svm_hwts { + iommus = <0x3 0x2>; + dma-can-stall; + pasid-bits = <0x10>; + vendor,smmu_bypass; + }; + }; + + firmware { + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + ipcm@11031000 { + compatible = "vendor,ipcm-interrupt"; + interrupt-parent = <0x1>; + interrupts = <0x0 0x1a 0x4 0x0 0x1b 0x4>; + reg = <0x0 0x11031000 0x0 0x1000>; + status = "okay"; + }; + + soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "simple-bus"; + device_type = "soc"; + ranges = <0x0 0x0 0x0 0xffffffff>; + + clk_3m { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x2dc6c0>; + phandle = <0x4>; + }; + + clk_20m { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x1312d00>; + phandle = <0x8>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + arm-timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04>; + clock-frequency = <0x16e3600>; + always-on; + }; + + timer@11000000 { + compatible = "vendor,bsp_sp804"; + reg = <0x11000000 0x1000 0x11001000 0x1000 0x11002000 0x1000 0x11003000 0x1000 0x11004000 0x1000>; + interrupts = <0x0 0x5 0x4 0x0 0x6 0x4 0x0 0x7 0x4 0x0 0x8 0x4>; + clocks = <0x4>; + clock-names = "apb_pclk"; + }; + + uart@11040000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11040000 0x1000>; + interrupts = <0x0 0x38 0x4>; + clocks = <0x5 0x5b>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + uart@11041000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11041000 0x1000>; + interrupts = <0x0 0x39 0x4>; + clocks = <0x5 0x5c>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + uart@11042000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11042000 0x1000>; + interrupts = <0x0 0x3a 0x4>; + clocks = <0x5 0x5d>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + uart@11043000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11043000 0x1000>; + interrupts = <0x0 0x3b 0x4>; + clocks = <0x5 0x5e>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + uart@11044000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11044000 0x1000>; + interrupts = <0x0 0x3c 0x4>; + clocks = <0x5 0x5f>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + uart@11045000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x11045000 0x1000>; + interrupts = <0x0 0x3d 0x4>; + clocks = <0x5 0x60>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + i2c@11060000 { + compatible = "vendor,i2c"; + reg = <0x11060000 0x1000>; + clocks = <0x5 0x32>; + clock-frequency = <0x186a0>; + status = "okay"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tca9535@20 { + compatible = "i2c,tca9535"; + reg = <0x20>; + id = <0x1>; + }; + }; + + i2c@11061000 { + compatible = "vendor,i2c"; + reg = <0x11061000 0x1000>; + clocks = <0x5 0x33>; + clock-frequency = <0x186a0>; + status = "okay"; + }; + + i2c@11062000 { + compatible = "vendor,i2c"; + reg = <0x11062000 0x1000>; + clocks = <0x5 0x34>; + clock-frequency = <0x186a0>; + status = "okay"; + }; + + i2c@11063000 { + compatible = "vendor,i2c"; + reg = <0x11063000 0x1000>; + clocks = <0x5 0x35>; + clock-frequency = <0x186a0>; + status = "okay"; + }; + + i2c@11064000 { + compatible = "vendor,i2c"; + reg = <0x11064000 0x1000>; + clocks = <0x5 0x36>; + clock-frequency = <0x186a0>; + status = "okay"; + }; + + i2c@11065000 { + compatible = "vendor,i2c"; + reg = <0x11065000 0x1000>; + clocks = <0x5 0x37>; + clock-frequency = <0x186a0>; + status = "okay"; + }; + + i2c@0 { + compatible = "i2c,soft"; + reg = <0x0 0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + gpio-scl = <0x6 0x7 0x0>; + gpio-sda = <0x6 0x6 0x0>; + clock-frequency = <0xf4240>; + status = "okay"; + }; + + i2c@1 { + compatible = "i2c,soft"; + reg = <0x1 0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + gpio-scl = <0x7 0x2 0x0>; + gpio-sda = <0x7 0x0 0x0>; + clock-frequency = <0xf4240>; + status = "okay"; + }; + + spi@11070000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x800022>; + reg = <0x11070000 0x1000>; + interrupts = <0x0 0x44 0x4>; + clocks = <0x5 0x3e>; + clock-names = "apb_pclk"; + #address-cells = <0x1>; + spi,slave_mode = <0x0>; + #size-cells = <0x0>; + status = "okay"; + num-cs = <0x1>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0x0>; + clocks = <0x8>; + spi-max-frequency = <0x1e8480>; + interrupt-parent = <0x9>; + interrupts = <0x2 0x2>; + status = "okay"; + }; + }; + + spi@11071000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x800022>; + reg = <0x11071000 0x1000 0x110d2100 0x4>; + interrupts = <0x0 0x45 0x4>; + clocks = <0x5 0x3f>; + clock-names = "apb_pclk"; + #address-cells = <0x1>; + spi,slave_mode = <0x0>; + #size-cells = <0x0>; + status = "okay"; + num-cs = <0x2>; + spi_cs_sb = <0x2>; + spi_cs_mask_bit = <0x4>; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + spi-max-frequency = <0x17d7840>; + }; + + spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <0x1>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + spi-max-frequency = <0x17d7840>; + }; + }; + + spi@11073000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x800022>; + reg = <0x11073000 0x1000>; + interrupts = <0x0 0x46 0x4>; + clocks = <0x5 0x40>; + clock-names = "apb_pclk"; + #address-cells = <0x1>; + spi,slave_mode = <0x0>; + #size-cells = <0x0>; + status = "okay"; + num-cs = <0x1>; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + spi-max-frequency = <0x17d7840>; + }; + }; + + spi@11074000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x800022>; + reg = <0x11074000 0x1000>; + interrupts = <0x0 0x47 0x4>; + clocks = <0x5 0x41>; + clock-names = "apb_pclk"; + spi,slave_mode = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + num-cs = <0x1>; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0x0>; + pl022,interface = <0x0>; + pl022,com-mode = <0x0>; + spi-max-frequency = <0x17d7840>; + }; + }; + + gpio_chip@11090000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11090000 0x1000>; + interrupts = <0x0 0x49 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11091000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11091000 0x1000>; + interrupts = <0x0 0x4a 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + phandle = <0x6>; + }; + + gpio_chip@11092000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11092000 0x1000>; + interrupts = <0x0 0x4b 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + phandle = <0x7>; + }; + + gpio_chip@11093000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11093000 0x1000>; + interrupts = <0x0 0x4c 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11094000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11094000 0x1000>; + interrupts = <0x0 0x4d 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x9>; + }; + + gpio_chip@11095000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11095000 0x1000>; + interrupts = <0x0 0x4e 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11096000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11096000 0x1000>; + interrupts = <0x0 0x4f 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11097000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11097000 0x1000>; + interrupts = <0x0 0x50 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11098000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11098000 0x1000>; + interrupts = <0x0 0x51 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@11099000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x11099000 0x1000>; + interrupts = <0x0 0x52 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109A000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109a000 0x1000>; + interrupts = <0x0 0x53 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109B000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109b000 0x1000>; + interrupts = <0x0 0x54 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109C000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109c000 0x1000>; + interrupts = <0x0 0x55 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109D000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109d000 0x1000>; + interrupts = <0x0 0x56 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109E000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109e000 0x1000>; + interrupts = <0x0 0x57 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@1109F000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1109f000 0x1000>; + interrupts = <0x0 0x58 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@110a0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x110a0000 0x1000>; + interrupts = <0x0 0x59 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + + gpio_chip@110a1000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x110a1000 0x1000>; + interrupts = <0x0 0x5a 0x4>; + #gpio-cells = <0x2>; + clocks = <0x5 0x23>; + clock-names = "apb_pclk"; + status = "okay"; + }; + }; + + misc-controller@11024000 { + compatible = "vendor,miscctrl", "syscon"; + reg = <0x11024000 0x5000>; + }; + + ioconfig0@10230000 { + compatible = "vendor,ioconfig", "syscon"; + reg = <0x10230000 0x10000>; + phandle = <0xc>; + }; + + ioconfig1@102f0000 { + compatible = "vendor,ioconfig", "syscon"; + reg = <0x102f0000 0x10000>; + phandle = <0xd>; + }; + + flash-memory-controller@10000000 { + compatible = "vendor,fmc"; + reg = <0x10000000 0x1000 0xf000000 0x1000000>; + reg-names = "control", "memory"; + clocks = <0x5 0x5a>; + max-dma-size = <0x2000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + spi_nor_controller { + compatible = "vendor,fmc-spi-nor"; + assigned-clocks = <0x5 0x5a>; + assigned-clock-rates = <0x16e3600>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sfc { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <0x9896800>; + m25p,fast-read; + }; + }; + + spi_nand_controller { + compatible = "vendor,fmc-spi-nand"; + assigned-clocks = <0x5 0x5a>; + assigned-clock-rates = <0x16e3600>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + nand { + compatible = "jedec,spi-nand"; + reg = <0x0>; + spi-max-frequency = <0x9896800>; + }; + }; + + parallel-nand-controller { + compatible = "vendor,fmc-nand"; + assigned-clocks = <0x5 0x5a>; + assigned-clock-rates = <0xbebc200>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + nand { + compatible = "jedec,nand"; + reg = <0x0>; + nand-max-frequency = <0xbebc200>; + }; + }; + }; + + mdio@102903c0 { + compatible = "vendor,gemac-mdio"; + reg = <0x102903c0 0x20>; + clocks = <0x5 0x65>; + resets = <0x5 0x37cc 0x0>; + reset-names = "phy_reset"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ethernet-phy@1 { + reg = <0x1>; + phandle = <0xa>; + }; + }; + + mdio@102a03c0 { + compatible = "vendor,gemac-mdio"; + reg = <0x102a03c0 0x20>; + clocks = <0x5 0x67>; + resets = <0x5 0x380c 0x0>; + reset-names = "phy_reset"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ethernet-phy@1 { + reg = <0x1>; + phandle = <0xb>; + }; + }; + + ethernet@10290000 { + compatible = "vendor,gmac-v5"; + reg = <0x10290000 0x1000 0x1029300c 0x4>; + interrupts = <0x0 0x65 0x4 0x0 0x66 0x4 0x0 0x67 0x4 0x0 0x68 0x4>; + clocks = <0x5 0x65 0x5 0x66>; + clock-names = "gmac_clk", "macif_clk"; + resets = <0x5 0x37c4 0x0 0x5 0x37c0 0x0>; + reset-names = "port_reset", "macif_reset"; + mac-address = [00 00 00 00 00 00]; + phy-handle = <0xa>; + phy-mode = "rgmii"; + }; + + ethernet@102a0000 { + compatible = "vendor,gmac-v5"; + reg = <0x102a0000 0x1000 0x102a300c 0x4>; + interrupts = <0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4>; + clocks = <0x5 0x67 0x5 0x68>; + clock-names = "gmac_clk", "macif_clk"; + resets = <0x5 0x3804 0x0 0x5 0x3800 0x0>; + reset-names = "port_reset", "macif_reset"; + mac-address = [00 00 00 00 00 00]; + phy-handle = <0xb>; + phy-mode = "rgmii"; + }; + + phy3 { + compatible = "vendor,usb-phy"; + reg = <0x11010000 0x10000 0x11024000 0x5000 0x11020000 0x4000>; + phyid = <0x0>; + }; + + xhci_0@0x10300000 { + compatible = "generic-xhci"; + reg = <0x10300000 0x10000>; + interrupts = <0x0 0x78 0x4>; + usb2-lpm-disable; + }; + + xhci_1@0x10320000 { + compatible = "generic-xhci"; + reg = <0x10320000 0x10000>; + interrupts = <0x0 0x79 0x4>; + usb2-lpm-disable; + }; + + eMMC@0x10020000 { + compatible = "vendor,sdhci"; + reg = <0x10020000 0x1000>; + interrupts = <0x0 0x5f 0x4>; + clocks = <0x5 0x61>; + clock-names = "mmc_clk"; + resets = <0x5 0x34c0 0x10 0x5 0x34c4 0x1>; + reset-names = "crg_reset", "dll_reset"; + max-frequency = <0xbebc200>; + crg_regmap = <0x5>; + non-removable; + iocfg_regmap = <0xc>; + bus-width = <0x8>; + cap-mmc-highspeed; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + devid = <0x0>; + status = "okay"; + }; + + SDIO@0x10030000 { + compatible = "vendor,sdhci"; + reg = <0x10030000 0x1000>; + interrupts = <0x0 0x5b 0x4>; + clocks = <0x5 0x62>; + clock-names = "mmc_clk"; + resets = <0x5 0x35c0 0x10 0x5 0x35c4 0x1>; + reset-names = "crg_reset", "dll_reset"; + max-frequency = <0xbebc200>; + crg_regmap = <0x5>; + iocfg_regmap = <0xd>; + bus-width = <0x4>; + cap-sd-highspeed; + sd-uhs-sdr104; + sd-uhs-sdr50; + full-pwr-cycle; + disable-wp; + no-emmc; + no-sdio; + devid = <0x1>; + status = "okay"; + }; + + SDIO1@0x10040000 { + compatible = "vendor,sdhci"; + reg = <0x10040000 0x1000>; + interrupts = <0x0 0x5c 0x4>; + clocks = <0x5 0x63>; + clock-names = "mmc_clk"; + resets = <0x5 0x36c0 0x10 0x5 0x36c4 0x1>; + reset-names = "crg_reset", "dll_reset"; + max-frequency = <0xbebc200>; + crg_regmap = <0x5>; + non-removable; + iocfg_regmap = <0xd>; + bus-width = <0x4>; + cap-sd-highspeed; + no-emmc; + no-sd; + devid = <0x2>; + status = "okay"; + }; + + pcie@0x103d0000 { + device_type = "pci"; + compatible = "vendor,pcie"; + #size-cells = <0x2>; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + bus-range = <0x0 0xff>; + reg = <0x0 0x103d0000 0x0 0x2000>; + ranges = <0x2000000 0x0 0x30000000 0x30000000 0x0 0x10000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x6f 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x70 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x71 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x72 0x4>; + pcie_controller = <0x0>; + dev_mem_size = <0x10000000>; + dev_conf_size = <0x10000000>; + sys_ctrl_base = <0x11020000>; + pcie_dbi_base = <0x103d0000>; + ep_conf_base = <0x20000000>; + pcie_clk_rest_reg = <0x3a40>; + status = "okay"; + }; + + pcie_mcc@0x0 { + compatible = "vendor,pcie_mcc"; + interrupts = <0x0 0x6f 0x4 0x0 0x70 0x4 0x0 0x71 0x4 0x0 0x72 0x4 0x0 0x73 0x4 0x0 0x0 0x4>; + }; + + edma-controller@10280000 { + compatible = "vendor,edmacv310"; + reg = <0x10280000 0x1000 0x102e0024 0x4>; + reg-names = "dmac", "dma_peri_channel_req_sel"; + interrupts = <0x0 0x62 0x4>; + clocks = <0x5 0x45 0x5 0x46>; + clock-names = "apb_pclk", "axi_aclk"; + #clock-cells = <0x2>; + resets = <0x5 0x2a80 0x0>; + reset-names = "dma-reset"; + dma-requests = <0x20>; + dma-channels = <0x8>; + devid = <0x0>; + #dma-cells = <0x2>; + status = "disabled"; + }; + + sys@11010000 { + compatible = "vendor,sys"; + reg = <0x11014500 0xbb00 0x11020000 0x4000 0x11130000 0x10000 0x11024000 0x5000>; + reg-names = "crg", "sys", "ddr", "misc"; + }; + + mipi_rx@0x173c0000 { + compatible = "vendor,mipi_rx"; + reg = <0x173c0000 0x10000>; + reg-names = "mipi_rx"; + interrupts = <0x0 0x9a 0x4>; + interrupt-names = "mipi_rx"; + }; + + vi@0x17400000 { + compatible = "vendor,vi"; + reg = <0x17400000 0x200000 0x17800000 0x40000 0x17840000 0x40000>; + reg-names = "vi_cap0", "vi_proc0", "vi_proc1"; + interrupts = <0x0 0x9b 0x4 0x0 0x9c 0x4 0x0 0x9d 0x4>; + interrupt-names = "vi_cap0", "vi_proc0", "vi_proc1"; + }; + + vpss@0x17900000 { + compatible = "vendor,vpss"; + reg = <0x17900000 0x10000>; + reg-names = "vpss0"; + interrupts = <0x0 0x9e 0x4>; + interrupt-names = "vpss0"; + }; + + vo@0x17A00000 { + compatible = "vendor,vo"; + reg = <0x17a00000 0x40000>; + reg-names = "vo"; + interrupts = <0x0 0xa0 0x4>; + interrupt-names = "vo"; + }; + + gfbg@0x17A00000 { + compatible = "vendor,gfbg"; + reg = <0x17a00000 0x40000>; + reg-names = "gfbg"; + interrupts = <0x0 0xa1 0x4>; + interrupt-names = "gfbg"; + }; + + hdmi@0x17B40000 { + compatible = "vendor,hdmi"; + reg = <0x17b40000 0x20000 0x17bc0000 0x10000>; + reg-names = "hdmi0", "phy"; + interrupts = <0x0 0xa3 0x4 0x0 0xa4 0x4 0x0 0xa5 0x4>; + interrupt-names = "tx_aon", "tx_sec", "tx_pwd"; + }; + + mipi_tx@0x17A80000 { + compatible = "vendor,mipi_tx"; + reg = <0x17a80000 0x10000>; + reg-names = "mipi_tx"; + interrupts = <0x0 0xa6 0x4>; + interrupt-names = "mipi_tx"; + }; + + vgs@0x17240000 { + compatible = "vendor,vgs"; + reg = <0x17240000 0x10000 0x17250000 0x10000>; + reg-names = "vgs0", "vgs1"; + interrupts = <0x0 0xaa 0x4 0x0 0xab 0x4>; + interrupt-names = "vgs0", "vgs1"; + }; + + vdh@0x17100000 { + compatible = "vendor,vdh"; + reg = <0x17100000 0x10000>; + reg-names = "vdh_scd"; + interrupts = <0x0 0xae 0x4 0x0 0xaf 0x4 0x0 0xb1 0x4 0x0 0xb2 0x4>; + interrupt-names = "vdh_bsp", "vdh_pxp", "scd", "vdh_mdma"; + }; + + gdc@0x172c0000 { + compatible = "vendor,gdc"; + reg = <0x172c0000 0x10000>; + reg-names = "gdc"; + interrupts = <0x0 0xb3 0x4>; + interrupt-names = "gdc"; + }; + + tde@0x17280000 { + compatible = "vendor,tde"; + reg = <0x17280000 0x10000>; + reg-names = "tde"; + interrupts = <0x0 0xb4 0x4>; + interrupt-names = "tde_osr_isr"; + }; + + jpegd@0x17180000 { + compatible = "vendor,jpegd"; + reg = <0x17180000 0x10000>; + reg-names = "jpegd"; + interrupts = <0x0 0xb6 0x4>; + interrupt-names = "jpegd"; + }; + + venc@0x17140000 { + compatible = "vendor,vedu"; + reg = <0x17140000 0x10000 0x171c0000 0x10000>; + reg-names = "vedu0", "jpge"; + interrupts = <0x0 0xb7 0x4 0x0 0xb5 0x4>; + interrupt-names = "vedu0", "jpge"; + }; + + npu@0x14000000 { + compatible = "vendor,npu"; + reg = <0x14000000 0x100000 0x14100000 0x200000 0x14300000 0x200000 0x17150000 0x10000 0x11010000 0x10000>; + reg-names = "npu_top", "npu_htws", "npu_aicore", "npu_peri", "crg"; + interrupts = <0x0 0x80 0x4 0x0 0x81 0x4 0x0 0x82 0x4 0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4 0x0 0x87 0x4 0x0 0x88 0x4>; + interrupt-names = "hwts_dfx", "hwts_normal_s", "hwts_debug_s", "hwts_error_s", "hwts_normal_ns", "hwts_debug_ns", "hwts_error_ns", "hwts_aicpu_s", "hwts_aicpu_ns"; + }; + + pqp@0x15000000 { + compatible = "vendor,pqp"; + reg = <0x15000000 0x10000>; + reg-names = "pqp"; + interrupts = <0x0 0xbe 0x4 0x0 0xbf 0x4>; + interrupt-names = "pqp_ns", "pqp_s"; + }; + + svp_npu@0x15000000 { + compatible = "vendor,svp_npu"; + reg = <0x15000000 0x10000>; + reg-names = "svp_npu"; + interrupts = <0x0 0xbe 0x4 0x0 0xbf 0x4>; + interrupt-names = "svp_npu_ns", "svp_npu_s"; + }; + + ive@0x17000000 { + compatible = "vendor,ive"; + reg = <0x17000000 0x10000>; + reg-names = "ive"; + interrupts = <0x0 0xc0 0x4>; + interrupt-names = "ive"; + }; + + mau@0x17030000 { + compatible = "vendor,mau"; + reg = <0x17030000 0x10000>; + reg-names = "mau0"; + interrupts = <0x0 0xc4 0x4>; + interrupt-names = "mau0"; + }; + + dpu_rect@0x17030000 { + compatible = "vendor,dpu_rect"; + reg = <0x17030000 0x10000>; + reg-names = "dpu_rect"; + interrupts = <0x0 0xc1 0x4>; + interrupt-names = "rect"; + }; + + dpu_match@0x17030000 { + compatible = "vendor,dpu_match"; + reg = <0x17030000 0x10000>; + reg-names = "dpu_match"; + interrupts = <0x0 0xc2 0x4>; + interrupt-names = "match"; + }; + + dsp@0x16110000 { + compatible = "vendor,dsp"; + reg = <0x16110000 0x20000 0x16310000 0x20000>; + reg-names = "dsp0", "dsp1"; + }; + + avs@0x17930000 { + compatible = "vendor,avs"; + reg = <0x17930000 0x10000>; + reg-names = "avs"; + interrupts = <0x0 0x8a 0x4>; + interrupt-names = "avs"; + }; + + aiao@17c00000 { + compatible = "vendor,aiao"; + reg = <0x17c00000 0x10000 0x17c40000 0x10000>; + reg-names = "aiao", "acodec"; + interrupts = <0x0 0xa2 0x4>; + interrupt-names = "AIO"; + }; + + cipher@0x10100000 { + compatible = "vendor,cipher"; + reg = <0x10100000 0x10000>; + reg-names = "cipher"; + interrupts = <0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4 0x0 0x2c 0x4>; + interrupt-names = "nsec_spacc", "sec_spacc", "nsec_pke", "sec_pke"; + }; + + klad@0x10110000 { + compatible = "vendor,klad"; + reg = <0x10110000 0x1000>; + reg-names = "klad"; + interrupts = <0x0 0x2e 0x4 0x0 0x2f 0x4 0x0 0x30 0x4 0x0 0x31 0x4>; + interrupt-names = "nsec_rkp", "sec_rkp", "nsec_klad", "sec_klad"; + }; + + otp@0x10120000 { + compatible = "vendor,otp"; + reg = <0x10120000 0x1000>; + reg-names = "otp"; + }; + + adc@0x11080000 { + compatible = "vendor,lsadc"; + reg = <0x11080000 0x1000>; + reg-names = "lsadc"; + interrupts = <0x0 0x48 0x4>; + interrupt-names = "lsadc"; + clocks = <0x5 0x78>; + clock-names = "lsadc-clk"; + resets = <0x5 0x46c0 0x0>; + reset-names = "lsadc-crg"; + status = "okay"; + }; + + ir@0x110F0000 { + compatible = "vendor,ir"; + reg = <0x110f0000 0x10000>; + reg-names = "ir"; + interrupts = <0x0 0x37 0x4>; + interrupt-names = "ir"; + }; + + wdg@0x11030000 { + compatible = "vendor,wdg"; + reg = <0x11030000 0x1000>; + reg-names = "wdg0"; + interrupts = <0x0 0x3 0x4>; + interrupt-names = "wdg"; + }; + + pwm@0x1102D000 { + compatible = "vendor,pwm"; + reg = <0x110b0000 0x1000 0x1102d000 0x1000>; + reg-names = "pwm0", "pwm1"; + clocks = <0x5 0x79 0x5 0x7a>; + clock-names = "pwm0", "pwm1"; + resets = <0x5 0x4588 0x0 0x5 0x4590 0x0>; + reset-names = "pwm0", "pwm1"; + status = "okay"; + }; + }; + + aliases { + serial0 = "/soc/amba/uart@11040000"; + serial1 = "/soc/amba/uart@11041000"; + serial2 = "/soc/amba/uart@11042000"; + serial3 = "/soc/amba/uart@11043000"; + serial4 = "/soc/amba/uart@11044000"; + serial5 = "/soc/amba/uart@11045000"; + i2c0 = "/soc/amba/i2c@11060000"; + i2c1 = "/soc/amba/i2c@11061000"; + i2c2 = "/soc/amba/i2c@11062000"; + i2c3 = "/soc/amba/i2c@11063000"; + i2c4 = "/soc/amba/i2c@11064000"; + i2c5 = "/soc/amba/i2c@11065000"; + spi0 = "/soc/amba/spi@11070000"; + spi1 = "/soc/amba/spi@11071000"; + spi2 = "/soc/amba/spi@11073000"; + spi3 = "/soc/amba/spi@11074000"; + gpio0 = "/soc/amba/gpio_chip@11090000"; + gpio1 = "/soc/amba/gpio_chip@11091000"; + gpio2 = "/soc/amba/gpio_chip@11092000"; + gpio3 = "/soc/amba/gpio_chip@11093000"; + gpio4 = "/soc/amba/gpio_chip@11094000"; + gpio5 = "/soc/amba/gpio_chip@11095000"; + gpio6 = "/soc/amba/gpio_chip@11096000"; + gpio7 = "/soc/amba/gpio_chip@11097000"; + gpio8 = "/soc/amba/gpio_chip@11098000"; + gpio9 = "/soc/amba/gpio_chip@11099000"; + gpio10 = "/soc/amba/gpio_chip@1109A000"; + gpio11 = "/soc/amba/gpio_chip@1109B000"; + gpio12 = "/soc/amba/gpio_chip@1109C000"; + gpio13 = "/soc/amba/gpio_chip@1109D000"; + gpio14 = "/soc/amba/gpio_chip@1109E000"; + gpio15 = "/soc/amba/gpio_chip@1109F000"; + gpio16 = "/soc/amba/gpio_chip@110a0000"; + gpio17 = "/soc/amba/gpio_chip@110a1000"; + }; + + chosen { + bootargs = "earlycon=pl011,0x11040000 mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/dev/mtdblock2 rootfstype=yaffs2 rw mtdparts=bspnand:1M(boot),9M(kernel),32M(rootfs),1M(this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!)"; + linux,initrd-start = <0x60000040>; + linux,initrd-end = <0x61000000>; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x50000000 0x1 0xf0000000>; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + client_os_reserved: client_os_reserved@43000000 { + reg = <0x00 0x43000000 0x00 0x4000000>; + no-map; + }; + + client_os_dma_memory_region: client_os-dma-memory@40000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x40000000 0x00 0x3000000>; + no-map; + }; + }; + mcs-remoteproc { + compatible = "oe,mcs_remoteproc"; + memory-region = <&client_os_dma_memory_region>, + <&client_os_reserved>; + }; +}; diff --git a/bsp/meta-hisilicon/recipes-kernel/linux/linux-hieulerpi1.inc b/bsp/meta-hisilicon/recipes-kernel/linux/linux-hieulerpi1.inc index dae21d66160..52c5402f5c0 100644 --- a/bsp/meta-hisilicon/recipes-kernel/linux/linux-hieulerpi1.inc +++ b/bsp/meta-hisilicon/recipes-kernel/linux/linux-hieulerpi1.inc @@ -11,6 +11,7 @@ PV = "5.10-tag928" SRC_URI:append = " \ file://HiEuler-driver/linux/5.10.0-153.28.0.patch \ file://dtbs/ss928-pi.dts \ + file://dtbs/ss928-pi_mcs.dts \ " # remove default patch @@ -27,11 +28,12 @@ OPENEULER_KERNEL_CONFIG = "" # after patches are unpatched KBUILD_DEFCONFIG = "hieulerpi1_defconfig" +WORKDTS = "${@bb.utils.contains('MCS_FEATURES', 'openamp', 'ss928-pi_mcs.dts', 'ss928-pi.dts', d)}" # add method to do_compile task to produce bootable Image do_compile:append(){ mkimage -A arm64 -O linux -T kernel -C none -a 0x080000 -e 0x080000 -n "Linux-5.10.0" -d ${KERNEL_OUTPUT_DIR}/Image uImage-tmp oe_runmake dtbs - dtc -I dts -O dtb ${WORKDIR}/dtbs/ss928-pi.dts -o ${WORKDIR}/ss928-pi.dtb + dtc -I dts -O dtb ${WORKDIR}/dtbs/${WORKDTS} -o ${WORKDIR}/ss928-pi.dtb cat uImage-tmp ${WORKDIR}/ss928-pi.dtb > ${KERNEL_OUTPUT_DIR}/uImage-pi } diff --git a/meta-openeuler/recipes-core/packagegroups/packagegroup-mcs.bb b/meta-openeuler/recipes-core/packagegroups/packagegroup-mcs.bb index 9fc796882e8..e4736b07505 100644 --- a/meta-openeuler/recipes-core/packagegroups/packagegroup-mcs.bb +++ b/meta-openeuler/recipes-core/packagegroups/packagegroup-mcs.bb @@ -25,6 +25,7 @@ ${@bb.utils.contains('DISTRO_FEATURES', 'xen', 'packagegroup-xen', '', d)} \ ### MCS DEPLOY TOOLS RDEPENDS:${PN}:append:aarch64 = " mcsctl" RDEPENDS:${PN}:append:x86-64 = " mcs-tools" +RDEPENDS:${PN}:append = " ${@bb.utils.contains('MCS_FEATURES', 'openamp', 'mcs-script', '', d)}" # add openamp dev to sdk TOOLCHAIN_TARGET_TASK += " \ diff --git a/meta-openeuler/recipes-kernel/linux/files/meta-data/features/mcs/0005-arm64-cpu-export-cpu_logical_map-symbol-for-mcs.patch b/meta-openeuler/recipes-kernel/linux/files/meta-data/features/mcs/0005-arm64-cpu-export-cpu_logical_map-symbol-for-mcs.patch new file mode 100644 index 00000000000..276ddba6a94 --- /dev/null +++ b/meta-openeuler/recipes-kernel/linux/files/meta-data/features/mcs/0005-arm64-cpu-export-cpu_logical_map-symbol-for-mcs.patch @@ -0,0 +1,31 @@ +From 6422b6ee5734463af9deb5d44415d17779824fd0 Mon Sep 17 00:00:00 2001 +From: Wanming Hu +Date: Sat, 30 Aug 2025 19:58:42 +0800 +Subject: [PATCH] arm64/cpu: export cpu_logical_map symbol for mcs + +* MCS needs cpu_logical_map symbol to fetch MPIDR value of certain cpu. + However, kernel did not export this symbol, which forces mcs module + to use kprobe to use it. As we find out that kprobe is not always supported + by all the embedded images, we export this symbol in linux to replace the + kprobe. + +Signed-off-by: Wanming Hu +--- + arch/arm64/kernel/setup.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c +index 0d6cd99f7..922e379a7 100644 +--- a/arch/arm64/kernel/setup.c ++++ b/arch/arm64/kernel/setup.c +@@ -342,6 +342,7 @@ u64 cpu_logical_map(int cpu) + { + return __cpu_logical_map[cpu]; + } ++EXPORT_SYMBOL(cpu_logical_map); + + void __init __no_sanitize_address setup_arch(char **cmdline_p) + { +-- +2.34.1 + diff --git a/meta-openeuler/recipes-kernel/linux/linux-openeuler.inc b/meta-openeuler/recipes-kernel/linux/linux-openeuler.inc index 15725b69f54..f14cfbb44d6 100644 --- a/meta-openeuler/recipes-kernel/linux/linux-openeuler.inc +++ b/meta-openeuler/recipes-kernel/linux/linux-openeuler.inc @@ -106,6 +106,10 @@ KERNEL_FEATURES:append = " \ KERNEL_FEATURES:append:x86-64 = " \ ${@bb.utils.contains('MCS_FEATURES', 'openamp', 'features/mcs/0001-x86-irq-add-a-vector-define-for-mcs.patch', '', d)} \ " +KERNEL_FEATURES:append:aarch64 = " \ + ${@bb.utils.contains('MCS_FEATURES', 'openamp', 'features/mcs/0005-arm64-cpu-export-cpu_logical_map-symbol-for-mcs.patch', '', d)} \ +" + # xen kernel support KERNEL_FEATURES:append = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)}" diff --git a/meta-openeuler/recipes-mcs/mcs-linux/files/mcs_cpu_offline.sh b/meta-openeuler/recipes-mcs/mcs-linux/files/mcs_cpu_offline.sh new file mode 100644 index 00000000000..a508a8a4c2c --- /dev/null +++ b/meta-openeuler/recipes-mcs/mcs-linux/files/mcs_cpu_offline.sh @@ -0,0 +1,2 @@ +CPU_ID= +echo 0 > /sys/devices/system/cpu/cpu${CPU_ID}/online diff --git a/meta-openeuler/recipes-mcs/mcs-linux/mcs-script.bb b/meta-openeuler/recipes-mcs/mcs-linux/mcs-script.bb new file mode 100644 index 00000000000..cc2933c7cbd --- /dev/null +++ b/meta-openeuler/recipes-mcs/mcs-linux/mcs-script.bb @@ -0,0 +1,47 @@ +### Descriptive metadata: SUMMARY,DESCRITPION, HOMEPAGE, AUTHOR, BUGTRACKER +SUMMARY = "Init script for preparing mcs environment" +DESCRIPTION = "${SUMMARY}" +AUTHOR = "" +HOMEPAGE = "https://gitee.com/openeuler/mcs" +BUGTRACKER = "https://gitee.com/openeuler/yocto-meta-openeuler" + +### License metadata +LICENSE = "MulanPSL-2.0" +LIC_FILES_CHKSUM = "file://LICENSE;md5=74b1b7a7ee537a16390ed514498bf23c" + + +### Build metadata: SRC_URI, SRCDATA, S, B, FILESEXTRAPATHS.... +OPENEULER_LOCAL_NAME = "mcs" + +SRC_URI = " \ + file://mcs \ + file://mcs_cpu_offline.sh \ + " +S = "${WORKDIR}/mcs" + +do_fetch[depends] += "mcs-linux:do_fetch" + +DEPENDS = "update-rc.d-native" + +OLD_SCRIPT="mcs_cpu_offline.sh" +INITD_DIR="${D}${sysconfdir}/init.d" + +do_install:append () { + install -d ${INITD_DIR} + + # If multiple cpus need to be turned offline, e.g. use MCS_CPUID_OFFLINE = "2 3" + if [ ! -z "${MCS_CPUID_OFFLINE}" ]; then + for cpu_id in ${MCS_CPUID_OFFLINE}; do + NEW_SCRIPT="mcs_cpu${cpu_id}_offline.sh" + SCRIPT_PATH="${INITD_DIR}/${NEW_SCRIPT}" + install -m 0755 ${WORKDIR}/${OLD_SCRIPT} ${SCRIPT_PATH} + sed -i "1s/.*/CPU_ID=${cpu_id}/" ${SCRIPT_PATH} + update-rc.d -r ${D} ${NEW_SCRIPT} start 89 5 . + done + + # TODO: handle systemd scripts + fi +} + +FILES:${PN} += "${sysconfdir}/init.d/" +FILES:${PN} += "${sysconfdir}/rc5.d/" diff --git a/meta-openeuler/recipes-mcs/mcs-linux/mcsctl.bb b/meta-openeuler/recipes-mcs/mcs-linux/mcsctl.bb index 8d302243051..7054d46c0bd 100644 --- a/meta-openeuler/recipes-mcs/mcs-linux/mcsctl.bb +++ b/meta-openeuler/recipes-mcs/mcs-linux/mcsctl.bb @@ -27,6 +27,7 @@ RDEPENDS:${PN} = "python3 python3-argcomplete" RTOS_IMGS:raspberrypi4-64 = "rpi4" RTOS_IMGS:qemu-aarch64 = "qemu" +RTOS_IMGS:hieulerpi1 = "hieulerpi" do_install:append () { # install Configuration file -- Gitee