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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/OAT.xml b/OAT.xml new file mode 100755 index 0000000000000000000000000000000000000000..5c2643786ecfd65c083b689a61aef1aaa80b063a --- /dev/null +++ b/OAT.xml @@ -0,0 +1,108 @@ + + + + + + LICENSE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/BUILD.gn b/hardware/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..a134d34f00ffe6af1f054b239184a46f7ca10617 --- /dev/null +++ b/hardware/BUILD.gn @@ -0,0 +1,22 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import("//build/ohos.gni") + +group("hardware_group") { + deps = [ + "//device/soc/rockchip/hardware/isp:isp", + "//device/soc/rockchip/hardware/mpp:mpp", + "//device/soc/rockchip/hardware/wifi:ap6xxx", + ] +} diff --git a/hardware/README.en.md b/hardware/README.en.md new file mode 100644 index 0000000000000000000000000000000000000000..6dd5fcd548bae504026ef2223c23d2862755ffed --- /dev/null +++ b/hardware/README.en.md @@ -0,0 +1,14 @@ +# rockchip hardware + +## Introduction +Media and wifi southbound interface implementation, framework and docking layer library directory。 +## Constraints + +Currently, rk3568 are supported. +## Repositories Involved +1. device_soc_rockchip/hardware/display +2. device_soc_rockchip/hardware/gpu +3. device_soc_rockchip/hardware/isp +4. device_soc_rockchip/hardware/mpp +5. device_soc_rockchip/hardware/rga +6. device_soc_rockchip/hardware/wifi diff --git a/hardware/README.zh.md b/hardware/README.zh.md new file mode 100644 index 0000000000000000000000000000000000000000..d9e1468affb8f2f2df34af6ab75d5c42222b5c2d --- /dev/null +++ b/hardware/README.zh.md @@ -0,0 +1,14 @@ +# rockchip hardware组件 + +#### 简介 +媒体及wifi南向接口实现、框架及对接层库目录。 +#### 约束 +目前支持rk3568 +#### 对应仓库 + +1. device_soc_rockchip/hardware/display +2. device_soc_rockchip/hardware/gpu +3. device_soc_rockchip/hardware/isp +4. device_soc_rockchip/hardware/mpp +5. device_soc_rockchip/hardware/rga +6. device_soc_rockchip/hardware/wifi diff --git a/hardware/display/BUILD.gn b/hardware/display/BUILD.gn new file mode 100644 index 0000000000000000000000000000000000000000..c66724712d856b48d560816dcc66958b3cdee9ba --- /dev/null +++ b/hardware/display/BUILD.gn @@ -0,0 +1,165 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import("//build/ohos.gni") + +group("display_group") { + deps = [ + ":display_device", + ":display_gfx", + ":display_gralloc", + ":higbm", + ] +} + +ohos_static_library("higbm") { + sources = [ "src/display_gralloc/hi_gbm.c" ] + include_dirs = [ + "include", + "//utils/native/base/include", + "//base/hiviewdfx/interfaces/innerkits/libhilog/include", + ] + output_name = "higbm" + cflags = [ + "-DGRALLOC_GBM_SUPPORT", + "-Wno-macro-redefined", + ] + deps = [ + "//third_party/libdrm:libdrm", + "//utils/native/base:utils", + ] + external_deps = [ "hiviewdfx_hilog_native:libhilog" ] +} + +ohos_shared_library("display_gralloc") { + sources = [ + "src/display_gralloc/display_gralloc.c", + "src/display_gralloc/display_gralloc_gbm.c", + "src/display_gralloc/wayland_drm_auth_client.c", + ] + include_dirs = [ + "include", + "//drivers/peripheral/display/interfaces/include", + "//drivers/peripheral/base", + "//drivers/framework/include/utils", + "//drivers/adapter/uhdf2/osal/include", + "//utils/native/base/include", + "//foundation/graphic/standard/utils/include", + "//foundation/graphic/standard/prebuilts/librarys/drm/include", + "//base/hiviewdfx/interfaces/innerkits/libhilog/include", + ] + output_name = "display_gralloc" + cflags = [ + "-DGRALLOC_GBM_SUPPORT", + "-Wno-macro-redefined", + ] + deps = [ + ":higbm", + "//third_party/libdrm:libdrm", + "//third_party/wayland_standard:libwayland_client", + "//third_party/weston:drm_auth_protocol", + "//utils/native/base:utils", + ] + + external_deps = [ "hiviewdfx_hilog_native:libhilog" ] + + install_enable = true + install_images = [ chipset_base_dir ] + subsystem_name = "hdf" + part_name = "display_device_driver" +} + +ohos_shared_library("display_gfx") { + sources = [ "src/display_gfx/display_gfx.c" ] + include_dirs = [ + "include", + "//drivers/peripheral/display/interfaces/include", + "//drivers/peripheral/base", + "//drivers/framework/include/utils", + "//drivers/adapter/uhdf2/adapter/osal/include/", + "//utils/native/base/include", + "//foundation/graphic/standard/utils/include", + "//device/soc/rockchip/hardware/rga/include/", + "//base/hiviewdfx/interfaces/innerkits/libhilog/include", + ] + output_name = "display_gfx" + cflags = [ "-Wno-macro-redefined" ] + deps = [ + ":display_gralloc", + "//device/soc/rockchip/hardware/rga:librga", + "//utils/native/base:utils", + ] + + external_deps = [ "hiviewdfx_hilog_native:libhilog" ] + + install_enable = true + install_images = [ chipset_base_dir ] + subsystem_name = "hdf" + part_name = "display_device_driver" +} + +ohos_shared_library("display_device") { + sources = [ + "src/display_device/drm_connector.cpp", + "src/display_device/drm_crtc.cpp", + "src/display_device/drm_device.cpp", + "src/display_device/drm_display.cpp", + "src/display_device/drm_encoder.cpp", + "src/display_device/drm_plane.cpp", + "src/display_device/drm_vsync_worker.cpp", + "src/display_device/hdi_composer.cpp", + "src/display_device/hdi_device_interface.cpp", + "src/display_device/hdi_display.cpp", + "src/display_device/hdi_drm_composition.cpp", + "src/display_device/hdi_drm_layer.cpp", + "src/display_device/hdi_gfx_composition.cpp", + "src/display_device/hdi_layer.cpp", + "src/display_device/hdi_netlink_monitor.cpp", + "src/display_device/hdi_session.cpp", + ] + output_name = "display_device" + include_dirs = [ + "src/display_device", + "include", + "//drivers/peripheral/display/interfaces/include", + "//drivers/peripheral/base", + "//drivers/framework/include/utils", + "//drivers/adapter/uhdf2/osal/include", + "//utils/native/base/include", + "//foundation/graphic/standard/utils/include", + "//foundation/graphic/standard/prebuilts/librarys/drm/include", + "//base/hiviewdfx/interfaces/innerkits/libhilog/include", + ] + deps = [ + ":display_gfx", + ":display_gralloc", + "//third_party/libdrm:libdrm", + "//utils/native/base:utils", + ] + cflags = [ "-Wno-unused-function" ] + external_deps = [ "hiviewdfx_hilog_native:libhilog" ] + + install_enable = true + install_images = [ chipset_base_dir ] + subsystem_name = "hdf" + part_name = "display_device_driver" +} + +group("display_layer") { + deps = [ + ":display_device", + ":display_gfx", + ":display_gralloc", + ":higbm", + ] +} diff --git a/hardware/display/include/display_common.h b/hardware/display/include/display_common.h new file mode 100644 index 0000000000000000000000000000000000000000..ae6fefa945f5a4d1e68d57a0d73d380de765731d --- /dev/null +++ b/hardware/display/include/display_common.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DISP_COMMON_H +#define DISP_COMMON_H +#include +#include +#include "hilog/log.h" +#include "stdio.h" +#ifdef HDF_LOG_TAG +#undef HDF_LOG_TAG +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#undef LOG_TAG +#undef LOG_DOMAIN +#define LOG_TAG "DISP" +#define LOG_DOMAIN 0xD001400 + +#ifndef DISPLAY_UNUSED +#define DISPLAY_UNUSED(x) (void)(x) +#endif + +#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1) : __FILE__) + +#ifndef DISPLAY_DEBUGLOG +#define DISPLAY_DEBUGLOG(format, ...) \ + do { \ + HILOG_DEBUG(LOG_CORE, "[%{public}s@%{public}s:%{public}d] " format "\n", __FUNCTION__, __FILENAME__, __LINE__, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DISPLAY_LOGI +#define DISPLAY_LOGI(format, ...) \ + do { \ + HILOG_INFO(LOG_CORE, "[%{public}s@%{public}s:%{public}d] " format "\n", __FUNCTION__, __FILENAME__, __LINE__, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DISPLAY_LOGW +#define DISPLAY_LOGW(format, ...) \ + do { \ + HILOG_WARN(LOG_CORE, "[%{public}s@%{public}s:%{public}d] " format "\n", __FUNCTION__, __FILENAME__, __LINE__, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DISPLAY_LOGE +#define DISPLAY_LOGE(format, ...) \ + do { \ + HILOG_ERROR(LOG_CORE, \ + "\033[0;32;31m" \ + "[%{public}s@%{public}s:%{public}d] " format "\033[m" \ + "\n", \ + __FUNCTION__, __FILENAME__, __LINE__, ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef CHECK_NULLPOINTER_RETURN_VALUE +#define CHECK_NULLPOINTER_RETURN_VALUE(pointer, ret) \ + do { \ + if ((pointer) == NULL) { \ + DISPLAY_LOGE("pointer is null and return ret\n"); \ + return (ret); \ + } \ + } while (0) +#endif + +#ifndef CHECK_NULLPOINTER_RETURN +#define CHECK_NULLPOINTER_RETURN(pointer) \ + do { \ + if ((pointer) == NULL) { \ + DISPLAY_LOGE("pointer is null and return\n"); \ + return; \ + } \ + } while (0) +#endif + +#ifndef DISPLAY_CHK_RETURN +#define DISPLAY_CHK_RETURN(val, ret, ...) \ + do { \ + if (val) { \ + __VA_ARGS__; \ + return (ret); \ + } \ + } while (0) +#endif + +#ifndef DISPLAY_CHK_RETURN_NOT_VALUE +#define DISPLAY_CHK_RETURN_NOT_VALUE(val, ret, ...) \ + do { \ + if (val) { \ + __VA_ARGS__; \ + return; \ + } \ + } while (0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* DISP_COMMON_H */ diff --git a/hardware/display/include/display_gralloc_private.h b/hardware/display/include/display_gralloc_private.h new file mode 100644 index 0000000000000000000000000000000000000000..e5ce9e0cefa946019050cd4a37de2c428dad1a50 --- /dev/null +++ b/hardware/display/include/display_gralloc_private.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DISPLAY_GRALLOC_INTERNAL_H +#define DISPLAY_GRALLOC_INTERNAL_H +#include "display_type.h" +#ifdef __cplusplus +extern "C" { +#endif +#define GRALLOC_NUM_FDS 1 +#define GRALLOC_NUM_INTS ((sizeof(struct PrivBufferHandle) - sizeof(BufferHandle)) / sizeof(int) - GRALLOC_NUM_FDS) + +#define INVALID_PIXEL_FMT 0 + +typedef struct { + BufferHandle hdl; +} PriBufferHandle; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/hardware/display/src/display_device/drm_connector.cpp b/hardware/display/src/display_device/drm_connector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3e13595a1ee1a277cd94b4a8f0e74af4e08d29f3 --- /dev/null +++ b/hardware/display/src/display_device/drm_connector.cpp @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_connector.h" +#include +#include +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +void DrmMode::ConvertToHdiMode(DisplayModeInfo &hdiMode) +{ + hdiMode.height = mModeInfo.vdisplay; + hdiMode.width = mModeInfo.hdisplay; + hdiMode.freshRate = mModeInfo.vrefresh; + hdiMode.id = mId; +} + +DrmConnector::DrmConnector(drmModeConnector c, FdPtr &fd) + : mId(c.connector_id), + mPhyWidth(c.mmWidth), + mPhyHeight(c.mmHeight), + mEncoderId(c.encoder_id), + mConnectState(c.connection), + mDrmFdPtr(fd) +{ + DISPLAY_DEBUGLOG("encoder_id %{public}d", mEncoderId); + DISPLAY_DEBUGLOG("the connect state is %{public}d", mConnectState); + + for (int i = 0; i < c.count_encoders; i++) { + mPossibleEncoders.push_back(c.encoders[i]); + DISPLAY_DEBUGLOG("add possible encoder id %{public}d", c.encoders[i]); + } + + ConvertToHdiType(c.connector_type, mType); + ConvertTypeToName(mType, mName); + InitModes(c); + DISPLAY_DEBUGLOG("name %{public}s", mName.c_str()); +} + +void DrmConnector::InitModes(drmModeConnector c) +{ + DISPLAY_DEBUGLOG("id %{public}d", mId); + mModes.clear(); + mPreferenceId = INVALID_MODE_ID; + for (int i = 0; i < c.count_modes; i++) { + drmModeModeInfoPtr mode = c.modes + i; + DISPLAY_DEBUGLOG("mode: hdisplay %{public}d, vdisplay %{public}d vrefresh %{public}d type %{public}d", + mode->hdisplay, mode->vdisplay, mode->vrefresh, mode->type); + if ((mPreferenceId == INVALID_MODE_ID) && (mode->type & DRM_MODE_TYPE_PREFERRED)) { + DISPLAY_DEBUGLOG("set it to prefernce id %{public}d", i); + mPreferenceId = i; + } + mModes.emplace(i, DrmMode { *mode, i }); + } + DISPLAY_DEBUGLOG("mode count %{public}zd", mModes.size()); +} + +int32_t DrmConnector::Init(DrmDevice &drmDevice) +{ + int32_t ret; + DrmProperty prop; + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((mDrmFdPtr == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("the mDrmFdPtr is NULL")); + DISPLAY_CHK_RETURN((mDrmFdPtr->GetFd() == -1), DISPLAY_FAILURE, DISPLAY_LOGE("the drm fd is -1")); + // find dpms prop + ret = drmDevice.GetConnectorProperty(*this, PROP_DPMS, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not get mode prop id")); + mPropDpmsId = prop.propId; + mDpmsState = prop.value; + DISPLAY_DEBUGLOG("dpms state : %{public}" PRIu64 "", mDpmsState); + // find the crtcid + ret = drmDevice.GetConnectorProperty(*this, PROP_CRTCID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get out fence prop id")); + mPropCrtcId = prop.propId; + DISPLAY_DEBUGLOG("encoder_id %{public}d", mEncoderId); + DISPLAY_DEBUGLOG("mPropCrtcId %{public}d", mPropCrtcId); + // find the brightness + ret = drmDevice.GetConnectorProperty(*this, PROP_BRIGHTNESS, prop); + if (ret == DISPLAY_SUCCESS) { + mPropBrightnessId = prop.propId; + mBrightnessLevel = static_cast(prop.value); + DISPLAY_DEBUGLOG("prop brightness is %{public}d, level is %{public}d", mPropBrightnessId, mBrightnessLevel); + } else { + DISPLAY_LOGW("can not get the brightness prop, can not set the brightness"); + } + return DISPLAY_SUCCESS; +} + +int32_t DrmConnector::GetBrightness(uint32_t& level) +{ + if (mPropBrightnessId == DRM_INVALID_ID) { + DISPLAY_LOGE("the prop id of brightness is invalid"); + return DISPLAY_NOT_SUPPORT; + } + level = mBrightnessLevel; + return DISPLAY_SUCCESS; +} + +const int BACKLIGHT_MIN = 10; +int32_t DrmConnector::SetBrightness(uint32_t level) +{ + static int32_t brFd = 0; + const int32_t buffer_size = 10; /* buffer size */ + char buffer[buffer_size]; + + DISPLAY_DEBUGLOG("set %{public}d", level); + if (mPropBrightnessId == DRM_INVALID_ID) { + DISPLAY_LOGE("the prop id of brightness is invalid"); + return DISPLAY_NOT_SUPPORT; + } + if (brFd <= 0) { + brFd = open("/sys/class/backlight/backlight/brightness", O_RDWR); + if (brFd < 0) { + DISPLAY_LOGE("oepn Brightness file failed\n"); + return DISPLAY_NOT_SUPPORT; + } + } + errno_t ret = memset_s(buffer, sizeof(buffer), 0, sizeof(buffer)); + if (ret != EOK) { + DISPLAY_LOGE("memset_s failed\n"); + return DISPLAY_FAILURE; + } + if (level < BACKLIGHT_MIN) { + level = BACKLIGHT_MIN; + } + int bytes = sprintf_s(buffer, sizeof(buffer), "%d\n", level); + if (bytes < 0) { + DISPLAY_LOGE("change failed\n"); + return DISPLAY_FAILURE; + } + write(brFd, buffer, bytes); + mBrightnessLevel = level; + return DISPLAY_SUCCESS; +} + +void DrmConnector::GetDisplayCap(DisplayCapability &cap) +{ + cap.phyHeight = mPhyHeight; + cap.phyWidth = mPhyWidth; + cap.type = mType; + memcpy_s(cap.name, sizeof(cap.name), mName.c_str(), mName.size()); + if (mName.size() >= sizeof(cap.name)) { + cap.name[sizeof(cap.name) - 1] = 0; + } else { + cap.name[mName.size()] = 0; + } + cap.supportLayers = mSupportLayers; + cap.virtualDispCount = mVirtualDispCount; + cap.supportWriteBack = mSupportWriteBack; + cap.propertyCount = mPropertyCount; +} + +void DrmConnector::ConvertTypeToName(uint32_t type, std::string &name) +{ + DISPLAY_DEBUGLOG("type %{public}d", type); + switch (type) { + case DISP_INTF_VGA: + name = "VGA"; + break; + case DISP_INTF_HDMI: + name = "HDMI"; + break; + case DISP_INTF_MIPI: + name = "MIPI"; + break; + default: + name = "Unknown"; + break; + } +} + +void DrmConnector::ConvertToHdiType(uint32_t type, InterfaceType &hdiType) +{ + switch (type) { + case DRM_MODE_CONNECTOR_VGA: + hdiType = DISP_INTF_VGA; + break; + case DRM_MODE_CONNECTOR_DSI: + hdiType = DISP_INTF_MIPI; + break; + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: + hdiType = DISP_INTF_HDMI; + break; + default: + hdiType = DISP_INTF_BUTT; + break; + } +} +int32_t DrmConnector::TryPickEncoder(IdMapPtr &encoders, uint32_t encoderId, IdMapPtr &crtcs, + uint32_t &crtcId) +{ + int ret; + auto encoderIter = encoders.find(encoderId); + if (encoderIter == encoders.end()) { + DISPLAY_LOGW("can not find encoder for id : %{public}d", encoderId); + return DISPLAY_FAILURE; + } + + auto &encoder = encoderIter->second; + DISPLAY_DEBUGLOG("connector : %{public}d encoder : %{public}d", mId, encoder->GetId()); + ret = encoder->PickIdleCrtcId(crtcs, crtcId); + DISPLAY_CHK_RETURN((ret == DISPLAY_SUCCESS), DISPLAY_SUCCESS, + DISPLAY_DEBUGLOG("connector : %{public}d pick encoder : %{public}d", mId, encoder->GetId())); + return DISPLAY_FAILURE; +} + +int32_t DrmConnector::PickIdleCrtcId(IdMapPtr &encoders, IdMapPtr &crtcs, uint32_t &crtcId) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_DEBUGLOG("encoder_id %{public}d", mEncoderId); + int ret = TryPickEncoder(encoders, mEncoderId, crtcs, crtcId); + DISPLAY_CHK_RETURN((ret == DISPLAY_SUCCESS), DISPLAY_SUCCESS, + DISPLAY_DEBUGLOG("connector : %{public}d pick endcoder : %{public}d crtcId : %{public}d", + mId, mEncoderId, crtcId)); + + for (auto encoder : mPossibleEncoders) { + ret = TryPickEncoder(encoders, encoder, crtcs, crtcId); + DISPLAY_CHK_RETURN((ret == DISPLAY_SUCCESS), DISPLAY_SUCCESS, + DISPLAY_DEBUGLOG("connector : %{public}d pick endcoder : %{public}d crtcId : %{public}d", mId, mEncoderId, + crtcId)); + } + + DISPLAY_LOGW("can not pick a crtc for connector"); + return DISPLAY_FAILURE; +} + +int32_t DrmConnector::UpdateModes() +{ + int drmFd = mDrmFdPtr->GetFd(); + drmModeConnectorPtr c = drmModeGetConnector(drmFd, mId); + DISPLAY_CHK_RETURN((c == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not get connector")); + mConnectState = c->connection; + // init the modes + InitModes(*c); + drmModeFreeConnector(c); + return DISPLAY_SUCCESS; +} + +bool DrmConnector::HandleHotplug() +{ + int drmFd = mDrmFdPtr->GetFd(); + drmModeConnectorPtr c = drmModeGetConnector(drmFd, mId); + DISPLAY_CHK_RETURN((c == nullptr), false, DISPLAY_LOGE("can not get connector")); + if (mConnectState == c->connection) { + drmModeFreeConnector(c); + return false; + } else { + mConnectState = c->connection; + InitModes(*c); + drmModeFreeConnector(c); + return true; + } +} +int32_t DrmConnector::GetDisplaySupportedModes(uint32_t *num, DisplayModeInfo *modes) +{ + DISPLAY_CHK_RETURN((num == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("num is nullptr")); + *num = static_cast(mModes.size()); + if (modes != nullptr) { + int i = 0; + for (const auto &modeMap : mModes) { + DrmMode mode = modeMap.second; + mode.ConvertToHdiMode(*(modes + i)); + i++; + } + } + return DISPLAY_SUCCESS; +} + +int32_t DrmConnector::SetDpmsState(uint64_t dmps) +{ + DISPLAY_DEBUGLOG("dmps %{public}" PRIu64 "", dmps); + int ret = drmModeConnectorSetProperty(mDrmFdPtr->GetFd(), mId, mPropDpmsId, dmps); + DISPLAY_CHK_RETURN((ret != 0), DISPLAY_FAILURE, DISPLAY_LOGE("can not set dpms")); + mDpmsState = dmps; + return DISPLAY_SUCCESS; +} + +bool DrmConnector::IsConnected() +{ + return (mConnectState == DRM_MODE_CONNECTED); +} + +int32_t DrmConnector::GetModeFromId(int32_t id, DrmMode &mode) +{ + DISPLAY_DEBUGLOG(); + auto iter = mModes.find(id); + if (iter == mModes.end()) { + return DISPLAY_FAILURE; + } + mode = mModes[id]; + return DISPLAY_SUCCESS; +} + +std::unique_ptr DrmConnector::GetModeBlockFromId(int32_t id) +{ + DISPLAY_DEBUGLOG("id %{public}d", id); + auto iter = mModes.find(id); + DISPLAY_CHK_RETURN((iter == mModes.end()), nullptr, DISPLAY_LOGE("can not the mode %{public}d", id)); + return std::make_unique(mModes[id]); +} + +DrmModeBlock::DrmModeBlock(DrmMode &mode) +{ + DISPLAY_DEBUGLOG(); + Init(mode); +} + +int32_t DrmModeBlock::Init(DrmMode &mode) +{ + int ret; + int drmFd; + drmFd = DrmDevice::GetDrmFd(); + DISPLAY_CHK_RETURN((drmFd < 0), DISPLAY_FAILURE, DISPLAY_LOGE("the drm fd is invalid")); + drmModeModeInfo modeInfo = *(mode.GetModeInfoPtr()); + ret = drmModeCreatePropertyBlob(drmFd, static_cast(&modeInfo), sizeof(modeInfo), &mBlockId); + DISPLAY_CHK_RETURN((ret != 0), DISPLAY_FAILURE, DISPLAY_LOGE("create property blob failed")); + DISPLAY_DEBUGLOG("mBlockId %{public}d", mBlockId); + return DISPLAY_SUCCESS; +} + +DrmModeBlock::~DrmModeBlock() +{ + DISPLAY_DEBUGLOG("mBlockId %{public}d", mBlockId); + int drmFd; + drmFd = DrmDevice::GetDrmFd(); + if ((mBlockId != DRM_INVALID_ID) && (drmFd >= 0)) { + int ret = drmModeDestroyPropertyBlob(drmFd, mBlockId); + if (ret != 0) { + DISPLAY_LOGE("destroy property blob failed errno %{public}d", errno); + } + } else { + DISPLAY_LOGE("can not destruct the block id %{public}d drmFd %{public}d", mBlockId, drmFd); + } +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_connector.h b/hardware/display/src/display_device/drm_connector.h new file mode 100644 index 0000000000000000000000000000000000000000..b282a755d19446c3930e6f2d8eb7a0f9d6df697f --- /dev/null +++ b/hardware/display/src/display_device/drm_connector.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_CONNECTOR_H +#define DRM_CONNECTOR_H +#include +#include +#include +#include +#include +#include "display_type.h" +#include "drm_encoder.h" +#include "hdi_device_common.h" +#include "hdi_shared_fd.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const std::string PROP_DPMS = "DPMS"; +const std::string PROP_CRTCID = "CRTC_ID"; +const std::string PROP_BRIGHTNESS = "brightness"; +class DrmDevice; +class DrmModeBlock; + +class DrmMode { +public: + DrmMode() {}; + DrmMode(drmModeModeInfo &modeInfo, uint32_t id) : mModeInfo(modeInfo), mId(id) {} + virtual ~DrmMode() {}; + drmModeModeInfoPtr GetModeInfoPtr() + { + return &mModeInfo; + } + void ConvertToHdiMode(DisplayModeInfo &hdiMode); + +private: + drmModeModeInfo mModeInfo = { 0 }; + int32_t mId = -1; +}; + +class DrmModeBlock { +public: + explicit DrmModeBlock(DrmMode &mode); + virtual ~DrmModeBlock(); + int32_t Init(DrmMode &mode); + uint32_t GetBlockId() const + { + return mBlockId; + } + +private: + uint32_t mBlockId = DRM_INVALID_ID; +}; + +class DrmConnector { +public: + DrmConnector(drmModeConnector c, FdPtr &fd); + virtual ~DrmConnector() {}; + uint32_t GetId() const + { + return mId; + } + uint32_t GetEncoderId() const + { + return mEncoderId; + } + void GetDisplayCap(DisplayCapability &cap); + int32_t Init(DrmDevice &drmDevice); + int32_t PickIdleCrtcId(IdMapPtr &encoders, IdMapPtr &crtcs, uint32_t &crtcId); + int32_t GetDisplaySupportedModes(uint32_t *num, DisplayModeInfo *modes); + int32_t GetPreferenceId() const + { + return mPreferenceId; + } + uint32_t GetPropCrtcId() const + { + return mPropCrtcId; + } + int32_t TryPickEncoder(IdMapPtr &encoders, uint32_t encoderId, IdMapPtr &crtcs, + uint32_t &crtcId); + // update modes will reset the preference mode id and active mode id + int32_t UpdateModes(); + std::unique_ptr GetModeBlockFromId(int32_t id); + int32_t GetModeFromId(int32_t id, DrmMode &mode); + uint64_t GetDpmsState() const + { + return mDpmsState; + } + int32_t SetDpmsState(uint64_t dmps); + bool IsConnected(); + bool HandleHotplug(); + + int32_t GetBrightness(uint32_t& level); + int32_t SetBrightness(uint32_t level); + +private: + static void ConvertTypeToName(uint32_t type, std::string &name); + static void ConvertToHdiType(uint32_t type, InterfaceType &hdiType); + + void InitModes(drmModeConnector c); + uint32_t mId; + InterfaceType mType; + uint32_t mPhyWidth; + uint32_t mPhyHeight; + uint32_t mSupportLayers = 0; + uint32_t mVirtualDispCount = 0; + bool mSupportWriteBack = false; + uint32_t mPropertyCount = 0; + uint32_t mEncoderId; + std::vector mPossibleEncoders; + std::string mName; + drmModeConnection mConnectState; + uint32_t mPropDpmsId = DRM_INVALID_ID; + uint64_t mDpmsState = 0; + uint32_t mPropCrtcId = DRM_INVALID_ID; + uint32_t mPropBrightnessId = DRM_INVALID_ID; + uint32_t mBrightnessLevel = 0; + std::unordered_map mModes; + int32_t mPreferenceId = INVALID_MODE_ID; + + FdPtr mDrmFdPtr; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY +#endif // DRM_CONNECTOR_H diff --git a/hardware/display/src/display_device/drm_crtc.cpp b/hardware/display/src/display_device/drm_crtc.cpp new file mode 100755 index 0000000000000000000000000000000000000000..42a4c8551d8633029657c2dd720658dcf557758a --- /dev/null +++ b/hardware/display/src/display_device/drm_crtc.cpp @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_crtc.h" +#include "display_common.h" +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +struct PlaneMaskName planeMaskNames[] = { + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER0_MASK, "Cluster0" }, + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER1_MASK, "Cluster1" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART0_MASK, "Esmart0" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART1_MASK, "Esmart1" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART0_MASK, "Smart0" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART1_MASK, "Smart1" }, + { DrmPlaneType::DRM_PLANE_TYPE_Unknown, "unknown" }, +}; + +DrmCrtc::DrmCrtc(drmModeCrtcPtr c, uint32_t pipe) : mId(c->crtc_id), mPipe(pipe), mPlaneMask(0) +{ +} + +int32_t DrmCrtc::Init(DrmDevice &drmDevice) +{ + DISPLAY_DEBUGLOG(); + int32_t ret; + DrmProperty prop; + ret = drmDevice.GetCrtcProperty(*this, PROP_MODEID, prop); + mModePropId = prop.propId; + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not get mode prop id")); + + ret = drmDevice.GetCrtcProperty(*this, PROP_OUTFENCE, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get out fence prop id")); + mOutFencePropId = prop.propId; + + ret = drmDevice.GetCrtcProperty(*this, PROP_ACTIVE, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get out fence prop id")); + mActivePropId = prop.propId; + + // Plane mask + mPlaneMask = 0; + ret = drmDevice.GetCrtcProperty(*this, "PLANE_MASK", prop); + if (ret != DISPLAY_SUCCESS) { + DISPLAY_LOGE("Failed to get plane_mask property"); + } else { + for (int i = 0; i < static_cast(ARRAY_SIZE(planeMaskNames)); i++) { + for (auto &drmEnum : prop.enums) { + if (!strncmp(drmEnum.name.c_str(), (const char*)planeMaskNames[i].name, + strlen(drmEnum.name.c_str())) && (prop.value & (1LL << drmEnum.value)) > 0) { + mPlaneMask |= static_cast(planeMaskNames[i].mask); + DISPLAY_LOGI("crtc id %{public}d, plane name %{public}s value %{public}llx", + GetId(), (const char*)planeMaskNames[i].name, + (long long)planeMaskNames[i].mask); + } + } + } + } + return DISPLAY_SUCCESS; +} + +int32_t DrmCrtc::BindToDisplay(uint32_t id) +{ + DISPLAY_CHK_RETURN((mDisplayId != INVALIDE_DISPLAY_ID), DISPLAY_FAILURE, + DISPLAY_LOGE("the crtc has bind to %{public}d", mDisplayId)); + mDisplayId = id; + return DISPLAY_SUCCESS; +} + +void DrmCrtc::UnBindDisplay(uint32_t id) +{ + DISPLAY_DEBUGLOG(); + if (mDisplayId == id) { + mDisplayId = INVALIDE_DISPLAY_ID; + } else { + DISPLAY_LOGE("can not unbind"); + } +} + +bool DrmCrtc::CanBind() +{ + return (mDisplayId == INVALIDE_DISPLAY_ID); +} + +int32_t DrmCrtc::SetActivieMode(int32_t id) +{ + DISPLAY_DEBUGLOG("set activie modeid to %{public}d", id); + DISPLAY_CHK_RETURN((id > 0), DISPLAY_PARAM_ERR, DISPLAY_LOGE("id %{public}d is invalid ", id)); + if (mActiveModeId != id) { + mNeedModeSet = true; + } + mActiveModeId = id; + return DISPLAY_SUCCESS; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_crtc.h b/hardware/display/src/display_device/drm_crtc.h new file mode 100755 index 0000000000000000000000000000000000000000..8f923326860ea4b04c8c21d073c525f203ae543e --- /dev/null +++ b/hardware/display/src/display_device/drm_crtc.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_CRTC_H +#define DRM_CRTC_H +#include +#include +#include +#include +#include "hdi_device_common.h" +#include "hdi_display.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const std::string PROP_ACTIVE = "ACTIVE"; +const std::string PROP_MODEID = "MODE_ID"; +const std::string PROP_OUTFENCE = "OUT_FENCE_PTR"; + +class DrmDevice; + +class DrmCrtc { +public: + DrmCrtc(drmModeCrtcPtr c, uint32_t pipe); + virtual ~DrmCrtc() {}; + int32_t BindToDisplay(uint32_t id); + void UnBindDisplay(uint32_t id); + bool CanBind(); + uint32_t GetId() const + { + return mId; + } + uint32_t GetModePropId() const + { + return mModePropId; + } + uint32_t GetOutFencePropId() const + { + return mOutFencePropId; + } + uint32_t GetActivePropId() const + { + return mActivePropId; + } + uint32_t GetPipe() const + { + return mPipe; + } + int32_t Init(DrmDevice &drmDevice); + int32_t SetActivieMode(int32_t id); + int32_t GetActiveModeId() const + { + return mActiveModeId; + } + bool NeedModeSet() + { + return mNeedModeSet; + } + uint32_t GetPlaneMask() + { + return mPlaneMask; + } +private: + uint32_t mId = 0; + uint32_t mModePropId = 0; + uint32_t mOutFencePropId = 0; + uint32_t mActivePropId = 0; + uint32_t mDisplayId = INVALIDE_DISPLAY_ID; + uint32_t mPipe = 0; + int32_t mActiveModeId = INVALID_MODE_ID; + bool mNeedModeSet = false; + uint32_t mPlaneMask = 0; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // DRM_CRTC_H \ No newline at end of file diff --git a/hardware/display/src/display_device/drm_device.cpp b/hardware/display/src/display_device/drm_device.cpp new file mode 100755 index 0000000000000000000000000000000000000000..fafe456f24b849392d5797f513810558b35152c6 --- /dev/null +++ b/hardware/display/src/display_device/drm_device.cpp @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_device.h" +#include +#include +#include +#include +#include +#include "display_common.h" +#include "drm_display.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +FdPtr DrmDevice::mDrmFd = nullptr; +std::shared_ptr DrmDevice::mInstance; + +std::shared_ptr DrmDevice::Create() +{ + DISPLAY_DEBUGLOG(); + if (mDrmFd == nullptr) { + const std::string name("rockchip"); + int drmFd = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); // drmOpen(name.c_str(), nullptr); + if (drmFd < 0) { + DISPLAY_LOGE("drm file:%{public}s open failed %{public}s", name.c_str(), strerror(errno)); + return nullptr; + } + DISPLAY_DEBUGLOG("the drm fd is %{public}d", drmFd); + mDrmFd = std::make_shared(drmFd); + } + if (mInstance == nullptr) { + mInstance = std::make_shared(); + } + return mInstance; +} + +int DrmDevice::GetDrmFd() +{ + if (mDrmFd == nullptr) { + DISPLAY_LOGE("the drmfd is null not open"); + return -1; + } + return mDrmFd->GetFd(); +} + +using PixelFormatConvertTbl = struct PixFmtConvertTbl { + uint32_t drmFormat; + PixelFormat pixFormat; +}; + +uint32_t DrmDevice::ConvertToDrmFormat(PixelFormat fmtIn) +{ + static const PixelFormatConvertTbl convertTable[] = { + {DRM_FORMAT_XBGR8888, PIXEL_FMT_RGBX_8888}, {DRM_FORMAT_ABGR8888, PIXEL_FMT_RGBA_8888}, + {DRM_FORMAT_RGB888, PIXEL_FMT_RGB_888}, {DRM_FORMAT_RGB565, PIXEL_FMT_BGR_565}, + {DRM_FORMAT_BGRX4444, PIXEL_FMT_BGRX_4444}, {DRM_FORMAT_BGRA4444, PIXEL_FMT_BGRA_4444}, + {DRM_FORMAT_RGBA4444, PIXEL_FMT_RGBA_4444}, {DRM_FORMAT_RGBX4444, PIXEL_FMT_RGBX_4444}, + {DRM_FORMAT_BGRX5551, PIXEL_FMT_BGRX_5551}, {DRM_FORMAT_BGRA5551, PIXEL_FMT_BGRA_5551}, + {DRM_FORMAT_BGRX8888, PIXEL_FMT_BGRX_8888}, {DRM_FORMAT_ARGB8888, PIXEL_FMT_BGRA_8888}, + {DRM_FORMAT_NV12, PIXEL_FMT_YCBCR_420_SP}, {DRM_FORMAT_NV21, PIXEL_FMT_YCRCB_420_SP}, + {DRM_FORMAT_YUV420, PIXEL_FMT_YCBCR_420_P}, {DRM_FORMAT_YVU420, PIXEL_FMT_YCRCB_420_P}, + {DRM_FORMAT_NV16, PIXEL_FMT_YCBCR_422_SP}, {DRM_FORMAT_NV61, PIXEL_FMT_YCRCB_422_SP}, + {DRM_FORMAT_YUV422, PIXEL_FMT_YCBCR_422_P}, {DRM_FORMAT_YVU422, PIXEL_FMT_YCRCB_422_P}, + }; + uint32_t fmtOut = 0; + for (uint32_t i = 0; i < sizeof(convertTable) / sizeof(convertTable[0]); i++) { + if (convertTable[i].pixFormat == fmtIn) { + fmtOut = convertTable[i].drmFormat; + } + } + DISPLAY_DEBUGLOG("fmtIn %{public}d, outFmt %{public}d", fmtIn, fmtOut); + return fmtOut; +} + +DrmDevice::DrmDevice() {} + +int32_t DrmDevice::GetCrtcProperty(const DrmCrtc &crtc, const std::string &name, DrmProperty &prop) +{ + return GetProperty(crtc.GetId(), DRM_MODE_OBJECT_CRTC, name, prop); +} + +int32_t DrmDevice::GetConnectorProperty(const DrmConnector &connector, const std::string &name, DrmProperty &prop) +{ + return GetProperty(connector.GetId(), DRM_MODE_OBJECT_CONNECTOR, name, prop); +} + +int32_t DrmDevice::GetPlaneProperty(const DrmPlane &plane, const std::string &name, DrmProperty &prop) +{ + return GetProperty(plane.GetId(), DRM_MODE_OBJECT_PLANE, name, prop); +} + +int32_t DrmDevice::GetProperty(uint32_t objId, uint32_t objType, const std::string &name, DrmProperty &prop) +{ + drmModeObjectPropertiesPtr props = drmModeObjectGetProperties(GetDrmFd(), objId, objType); + DISPLAY_CHK_RETURN((!props), DISPLAY_FAILURE, DISPLAY_LOGE("can not get properties")); + bool found = false; + for (uint32_t i = 0; i < props->count_props; i++) { + drmModePropertyPtr p = drmModeGetProperty(GetDrmFd(), props->props[i]); + if (strcmp(p->name, name.c_str()) == 0) { + found = true; + prop.propId = p->prop_id; + prop.value = props->prop_values[i]; + prop.name = p->name; + prop.flags = p->flags; + + for (int i = 0; i < p->count_values; ++i) { + prop.values.push_back(p->values[i]); + } + for (int i = 0; i < p->count_enums; ++i) { + prop.enums.push_back(DrmPropertyEnum(&p->enums[i])); + } + + for (int i = 0; i < p->count_blobs; ++i) { + prop.blob_ids.push_back(p->blob_ids[i]); + } + if (prop.flags & DRM_MODE_PROP_RANGE) { + prop.type = static_cast(DrmPropertyType::DRM_PROPERTY_TYPE_INT); + } else if (prop.flags & DRM_MODE_PROP_ENUM) { + prop.type = static_cast(DrmPropertyType::DRM_PROPERTY_TYPE_ENUM); + } else if (prop.flags & DRM_MODE_PROP_OBJECT) { + prop.type = static_cast(DrmPropertyType::DRM_PROPERTY_TYPE_OBJECT); + } else if (prop.flags & DRM_MODE_PROP_BLOB) { + prop.type = static_cast(DrmPropertyType::DRM_PROPERTY_TYPE_BLOB); + } else if (prop.flags & DRM_MODE_PROP_BITMASK) { + prop.type = static_cast(DrmPropertyType::DRM_PROPERTY_TYPE_BITMASK); + } + } + drmModeFreeProperty(p); + } + drmModeFreeObjectProperties(props); + return found ? DISPLAY_SUCCESS : DISPLAY_NOT_SUPPORT; +} + +int32_t DrmDevice::Init() +{ + int ret = drmSetClientCap(GetDrmFd(), DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1); + DISPLAY_CHK_RETURN((ret), DISPLAY_FAILURE, + DISPLAY_LOGE("DRM_CLIENT_CAP_UNIVERSAL_PLANES set failed %{public}s", strerror(errno))); + ret = drmSetClientCap(GetDrmFd(), DRM_CLIENT_CAP_ATOMIC, 1); + DISPLAY_CHK_RETURN((ret), DISPLAY_FAILURE, + DISPLAY_LOGE("DRM_CLIENT_CAP_ATOMIC set failed %{public}s", strerror(errno))); + + ret = drmSetMaster(GetDrmFd()); + DISPLAY_CHK_RETURN((ret), DISPLAY_FAILURE, DISPLAY_LOGE("can not set to master errno : %{public}d", errno)); + DISPLAY_LOGE("chenyf master"); + ret = drmIsMaster(GetDrmFd()); + DISPLAY_CHK_RETURN((!ret), DISPLAY_FAILURE, DISPLAY_LOGE("is not master : %{public}d", errno)); + + return DISPLAY_SUCCESS; +} + +void DrmDevice::DeInit() +{ + mDisplays.clear(); + mCrtcs.clear(); +} + +void DrmDevice::FindAllCrtc(const drmModeResPtr &res) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((res == nullptr), DISPLAY_LOGE("the res is null")); + mCrtcs.clear(); + for (int i = 0; i < res->count_crtcs; i++) { + drmModeCrtcPtr crtc = drmModeGetCrtc(GetDrmFd(), res->crtcs[i]); + if (!crtc) { + DISPLAY_LOGE("can not get crtc %{public}d", i); + continue; + } + uint32_t crtc_id = crtc->crtc_id; + std::shared_ptr drmCrtc = std::make_shared(crtc, i); + int ret = drmCrtc->Init(*this); + drmModeFreeCrtc(crtc); + if (ret != DISPLAY_SUCCESS) { + DISPLAY_LOGE("crtc %{public}d init failed", i); + continue; + } + mCrtcs.emplace(crtc_id, std::move(drmCrtc)); + } +} + +void DrmDevice::FindAllEncoder(const drmModeResPtr &res) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((res == nullptr), DISPLAY_LOGE("the res is null")); + mEncoders.clear(); + for (int i = 0; i < res->count_encoders; i++) { + drmModeEncoderPtr encoder = drmModeGetEncoder(GetDrmFd(), res->encoders[i]); + if (!encoder) { + DISPLAY_LOGE("can not get encoder %{public}d", i); + continue; + } + std::shared_ptr drmEncoder = std::make_shared(*encoder); + mEncoders.emplace(encoder->encoder_id, std::move(drmEncoder)); + drmModeFreeEncoder(encoder); + } + DISPLAY_DEBUGLOG("find encoder count %{public}zd", mEncoders.size()); +} + +void DrmDevice::FindAllConnector(const drmModeResPtr &res) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((res == nullptr), DISPLAY_LOGE("the res is null")); + mConnectors.clear(); + int ret; + for (int i = 0; i < res->count_connectors; i++) { + drmModeConnectorPtr connector = drmModeGetConnector(GetDrmFd(), res->connectors[i]); + if (!connector) { + DISPLAY_LOGE("can not get connector mode %{public}d", i); + continue; + } + std::shared_ptr drmConnector = std::make_shared(*connector, mDrmFd); + ret = drmConnector->Init(*this); + drmModeFreeConnector(connector); + if (ret != DISPLAY_SUCCESS) { + continue; + } + int connectorId = drmConnector->GetId(); + mConnectors.emplace(connectorId, std::move(drmConnector)); + } + DISPLAY_DEBUGLOG("find connector count %{public}zd", mConnectors.size()); +} + +void DrmDevice::FindAllPlane() +{ + mPlanes.clear(); + int ret; + drmModePlaneResPtr planeRes = drmModeGetPlaneResources(GetDrmFd()); + DISPLAY_CHK_RETURN_NOT_VALUE((planeRes == nullptr), DISPLAY_LOGE("can not get plane resource")); + DISPLAY_DEBUGLOG("count_planes %{public}d", planeRes->count_planes); + for (uint32_t i = 0; i < planeRes->count_planes; i++) { + drmModePlanePtr p = drmModeGetPlane(GetDrmFd(), planeRes->planes[i]); + if (!p) { + DISPLAY_LOGE("can not get plane %{public}d", i); + continue; + } + std::shared_ptr drmPlane = std::make_shared(*p); + DISPLAY_DEBUGLOG(); + ret = drmPlane->Init(*this); + DISPLAY_DEBUGLOG(); + drmModeFreePlane(p); + if (ret != DISPLAY_SUCCESS) { + DISPLAY_LOGE("drm plane %{public}d init failed", i); + continue; + } + mPlanes.emplace_back(std::move(drmPlane)); + } + DISPLAY_DEBUGLOG("find plane count %{public}zd", mPlanes.size()); +} + +std::shared_ptr DrmDevice::GetDrmEncoderFromId(uint32_t id) +{ + return nullptr; +} + +std::shared_ptr DrmDevice::GetDrmConnectorFromId(uint32_t id) +{ + return nullptr; +} + +std::shared_ptr DrmDevice::GetDrmCrtcFromId(uint32_t id) +{ + return nullptr; +} + +std::vector> DrmDevice::GetDrmPlane(uint32_t pipe, uint32_t type) +{ + std::vector> planes; + for (const auto &plane : mPlanes) { + if (plane->IsIdle() && ((1 << pipe) & plane->GetPossibleCrtcs()) && (type == plane->GetType())) { + planes.push_back(plane); + } + } + DISPLAY_DEBUGLOG("the planes count %{public}zd", planes.size()); + return planes; +} + +bool DrmDevice::HandleHotplug(uint32_t dispId, bool plugIn) +{ + uint32_t find = 0; + uint32_t connectorId; + + for (auto &dispConnectorIdMap : dispConnectorIdMaps_) { + if (dispConnectorIdMap.first == dispId) { + connectorId = dispConnectorIdMap.second; + find = 1; + break; + } + } + if (find) { + for (auto &connectorPair : mConnectors) { + auto connector = connectorPair.second; + if (connectorId == connector->GetId()) { + if (connector->HandleHotplug() == true) { + connector->Init(*this); + return true; + } + } + } + } + return false; +} + +std::unordered_map> DrmDevice::DiscoveryDisplay() +{ + uint32_t dispId; + uint32_t connectorId; + + dispConnectorIdMaps_.clear(); + mDisplays.clear(); + drmModeResPtr res = drmModeGetResources(GetDrmFd()); + DISPLAY_CHK_RETURN((res == nullptr), mDisplays, DISPLAY_LOGE("can not get drm resource")); + // discovery all drm resource + FindAllCrtc(res); + FindAllEncoder(res); + FindAllConnector(res); + FindAllPlane(); + DISPLAY_DEBUGLOG(); + // travel all connector + for (auto &connectorPair : mConnectors) { + auto connector = connectorPair.second; + uint32_t crtcId = 0; + int32_t ret = connector->PickIdleCrtcId(mEncoders, mCrtcs, crtcId); + if (ret != DISPLAY_SUCCESS) { + continue; + } + DISPLAY_DEBUGLOG(); + + auto crtcIter = mCrtcs.find(crtcId); + if (crtcIter == mCrtcs.end()) { + DISPLAY_LOGE("can not find crtc for the id %{public}d", connector->GetId()); + continue; + } + DISPLAY_DEBUGLOG(); + auto crtc = crtcIter->second; + DISPLAY_DEBUGLOG("crtc %{public}p", crtc.get()); + // create the display + std::shared_ptr display = std::make_shared(connector, crtc, mInstance); + DISPLAY_DEBUGLOG(); + display->Init(); + dispId = display->GetId(); + connectorId = connector->GetId(); + mDisplays.emplace(dispId, std::move(display)); + dispConnectorIdMaps_.emplace(dispId, connectorId); + } + DISPLAY_DEBUGLOG("find display size %{public}zd", mDisplays.size()); + return mDisplays; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_device.h b/hardware/display/src/display_device/drm_device.h new file mode 100755 index 0000000000000000000000000000000000000000..875cacb5c9b22a6f079b9ba4397955e30139c7e7 --- /dev/null +++ b/hardware/display/src/display_device/drm_device.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_DEVICE_H +#define DRM_DEVICE_H +#include +#include +#include +#include +#include "drm_connector.h" +#include "drm_crtc.h" +#include "drm_encoder.h" +#include "drm_plane.h" +#include "hdi_device_common.h" +#include "hdi_device_interface.h" +#include "hdi_display.h" +#include "hdi_shared_fd.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +class DrmPropertyEnum { +public: + explicit DrmPropertyEnum(drm_mode_property_enum *e) : value(e->value), name(e->name) { + } + ~DrmPropertyEnum() {}; + + uint64_t value; + std::string name; +}; + +struct DrmProperty { + uint32_t propId; + uint64_t value; + uint32_t type; + uint32_t flags; + std::string name; + std::vector values; + std::vector enums; + std::vector blob_ids; +}; + +class DrmDevice : public HdiDeviceInterface, std::enable_shared_from_this { +public: + static std::shared_ptr Create(); + static uint32_t ConvertToDrmFormat(PixelFormat fmtIn); + static int GetDrmFd(); + DrmDevice(); + ~DrmDevice() override {} + + std::vector> GetDrmPlane(uint32_t pipe, uint32_t type); + + int32_t GetCrtcProperty(const DrmCrtc &crtc, const std::string &name, DrmProperty &prop); + int32_t GetConnectorProperty(const DrmConnector &connector, const std::string &name, DrmProperty &prop); + int32_t GetPlaneProperty(const DrmPlane &plane, const std::string &name, DrmProperty &prop); + + int32_t GetProperty(uint32_t objId, uint32_t objType, const std::string &name, DrmProperty &prop); + std::shared_ptr GetDrmEncoderFromId(uint32_t id); + std::shared_ptr GetDrmConnectorFromId(uint32_t id); + std::shared_ptr GetDrmCrtcFromId(uint32_t id); + void CreateCrtc(drmModeCrtcPtr c); + std::unordered_map> DiscoveryDisplay() override; + int32_t Init() override; + void DeInit() override; + bool HandleHotplug(uint32_t dispId, bool plugIn) override; + +private: + static FdPtr mDrmFd; + static std::shared_ptr mInstance; + void FindAllCrtc(const drmModeResPtr &drmRes); + void FindAllEncoder(const drmModeResPtr &drmRes); + void FindAllConnector(const drmModeResPtr &drmRes); + void FindAllPlane(); + int InitNetLink(); + IdMapPtr mDisplays; + IdMapPtr mCrtcs; + IdMapPtr mEncoders; + IdMapPtr mConnectors; + std::vector> mPlanes; + std::unordered_map dispConnectorIdMaps_; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // DRM_DEVICE_H diff --git a/hardware/display/src/display_device/drm_display.cpp b/hardware/display/src/display_device/drm_display.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0d794449d731586984f565595eba8c4e0fdb6b2 --- /dev/null +++ b/hardware/display/src/display_device/drm_display.cpp @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_display.h" +#include +#include +#include +#include +#include +#include "display_gralloc.h" +#include "display_common.h" +#include "drm_device.h" +#include "drm_vsync_worker.h" +#include "hdi_drm_composition.h" +#include "hdi_gfx_composition.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +DrmDisplay::DrmDisplay(std::shared_ptr connector, std::shared_ptr crtc, + std::shared_ptr drmDevice) + : mDrmDevice(drmDevice), mConnector(connector), mCrtc(crtc) +{} + +DrmDisplay::~DrmDisplay() +{ + if (mCrtc != nullptr) { + mCrtc->UnBindDisplay(GetId()); + } +} + +int32_t DrmDisplay::Init() +{ + int ret; + DISPLAY_CHK_RETURN((mCrtc == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("crtc is null")); + DISPLAY_CHK_RETURN((mConnector == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("connector is null")); + DISPLAY_CHK_RETURN((mDrmDevice == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("drmDevice is null")); + + ret = HdiDisplay::Init(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("init failed")); + auto preComp = std::make_unique(); + DISPLAY_CHK_RETURN((preComp == nullptr), DISPLAY_FAILURE, + DISPLAY_LOGE("can not new HdiGfxComposition errno %{public}d", errno)); + ret = preComp->Init(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not init HdiGfxComposition")); + + auto postComp = std::make_unique(mConnector, mCrtc, mDrmDevice); + DISPLAY_CHK_RETURN((postComp == nullptr), DISPLAY_FAILURE, + DISPLAY_LOGE("can not new HdiDrmComposition errno %{public}d", errno)); + ret = postComp->Init(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not init HdiDrmComposition")); + mComposer = std::make_unique(std::move(preComp), std::move(postComp)); + ret = mCrtc->BindToDisplay(GetId()); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("bind crtc failed")); + + ret = ChosePreferenceMode(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("choose preference mode fialed")); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::GetDisplayCapability(DisplayCapability *info) +{ + mConnector->GetDisplayCap(*info); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::GetDisplaySupportedModes(uint32_t *num, DisplayModeInfo *modes) +{ + mConnector->GetDisplaySupportedModes(num, modes); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::GetDisplayMode(uint32_t *modeId) +{ + DISPLAY_CHK_RETURN((modeId == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("the in modeId is nullptr")); + *modeId = mCrtc->GetActiveModeId(); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::SetDisplayMode(uint32_t modeId) +{ + return mCrtc->SetActivieMode(modeId); +} + +int32_t DrmDisplay::GetDisplayPowerStatus(DispPowerStatus *status) +{ + DISPLAY_CHK_RETURN((status == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("status is nullptr")); + return ConvertToHdiPowerState(mConnector->GetDpmsState(), *status); +} + +int32_t DrmDisplay::SetDisplayPowerStatus(DispPowerStatus status) +{ + static int32_t fb_fd = -1; + int32_t err = -1; + const uint32_t FBIOBLANK = 0x4611; /* arg: 0 or vesa level + 1 */ + const uint32_t FB_BLANK_UNBLANK = 0; /* screen: unblanked, hsync: on, vsync: on */ + const uint32_t FB_BLANK_POWERDOWN = 4; /* screen: blanked, hsync: off, vsync: off */ + + DISPLAY_DEBUGLOG("SetDisplayPowerStatus power state %{public}u", status); + if (fb_fd < 0) { + fb_fd = open("/dev/graphics/fb0", O_RDWR); + if (fb_fd < 0) { + DISPLAY_LOGE("oepn fb0 file failed\n"); + return DISPLAY_NOT_SUPPORT; + } + } + switch (status) { + case POWER_STATUS_OFF: + case POWER_STATUS_STANDBY: + case POWER_STATUS_SUSPEND: + err = ioctl(fb_fd, FBIOBLANK, FB_BLANK_POWERDOWN); + break; + case POWER_STATUS_ON: + err = ioctl(fb_fd, FBIOBLANK, FB_BLANK_UNBLANK); + break; + default: + err = DISPLAY_FAILURE; + break; + } + if (err < 0) { + DISPLAY_LOGE("ioctl fb0 failed\n"); + return DISPLAY_FAILURE; + } + + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::ConvertToHdiPowerState(uint32_t drmPowerState, DispPowerStatus &hdiPowerState) +{ + int32_t ret = DISPLAY_SUCCESS; + switch (drmPowerState) { + case DRM_MODE_DPMS_OFF: + hdiPowerState = POWER_STATUS_OFF; + break; + case DRM_MODE_DPMS_ON: + hdiPowerState = POWER_STATUS_ON; + break; + case DRM_MODE_DPMS_STANDBY: + hdiPowerState = POWER_STATUS_STANDBY; + break; + case DRM_MODE_DPMS_SUSPEND: + hdiPowerState = POWER_STATUS_SUSPEND; + break; + default: + hdiPowerState = POWER_STATUS_BUTT; + ret = DISPLAY_FAILURE; + break; + } + DISPLAY_DEBUGLOG("hdi power state %{public}u", hdiPowerState); + return ret; +} + +int32_t DrmDisplay::ConvertToDrmPowerState(DispPowerStatus hdiPowerState, uint32_t &drmPowerState) +{ + int32_t ret = DISPLAY_SUCCESS; + switch (hdiPowerState) { + case POWER_STATUS_OFF: + drmPowerState = DRM_MODE_DPMS_OFF; + break; + case POWER_STATUS_ON: + drmPowerState = DRM_MODE_DPMS_ON; + break; + case POWER_STATUS_STANDBY: + drmPowerState = DRM_MODE_DPMS_STANDBY; + break; + case POWER_STATUS_SUSPEND: + drmPowerState = DRM_MODE_DPMS_SUSPEND; + break; + default: + ret = DISPLAY_FAILURE; + break; + } + return ret; +} + +std::unique_ptr DrmDisplay::CreateHdiLayer(LayerType type) +{ + DISPLAY_DEBUGLOG(); + return std::make_unique(type); +} + +int32_t DrmDisplay::WaitForVBlank(uint64_t *ns) +{ + int ret; + constexpr uint64_t nPerS = 1000000000; + constexpr uint64_t nPerUS = 1000; + drmVBlank vbl = { + .request.type = DRM_VBLANK_RELATIVE, + .request.sequence = 0, + .request.signal = 0, + }; + DISPLAY_CHK_RETURN((ns == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in ns is nullptr")); + ret = drmWaitVBlank(mDrmDevice->GetDrmFd(), &vbl); + DISPLAY_CHK_RETURN((ret != 0), DISPLAY_FAILURE, DISPLAY_LOGE("wait vblank failed errno %{public}d", errno)); + *ns = static_cast(vbl.reply.tval_sec * nPerS + vbl.reply.tval_usec * nPerUS); + return DISPLAY_SUCCESS; +} + +bool DrmDisplay::IsConnected() +{ + DISPLAY_DEBUGLOG("conneted %{public}d", mConnector->IsConnected()); + return mConnector->IsConnected(); +} + +int32_t DrmDisplay::PushFirstFrame() +{ + GrallocFuncs *grallocFucs = nullptr; + int ret = GrallocInitialize(&grallocFucs); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("Gralloc init failed")); + DrmMode mode; + ret = mConnector->GetModeFromId(mCrtc->GetActiveModeId(), mode); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, + DISPLAY_LOGE("can not get the mode from id %{public}d", mCrtc->GetActiveModeId())); + AllocInfo info = { + .width = mode.GetModeInfoPtr()->hdisplay, + .height = mode.GetModeInfoPtr()->vdisplay, + .usage = HBM_USE_MEM_DMA | HBM_USE_CPU_READ | HBM_USE_CPU_WRITE, + .format = PIXEL_FMT_BGRA_8888 + }; + + BufferHandle *buffer = nullptr; + ret = grallocFucs->AllocMem(&info, &buffer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not alloc memory")); + mClientLayer->SetLayerBuffer(buffer, -1); + + std::vector layers; + HdiDrmComposition *drmComp = static_cast(mComposer->GetPostCompostion()); + drmComp->SetLayers(layers, *mClientLayer); + drmComp->Apply(true); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::ChosePreferenceMode() +{ + int32_t ret; + int32_t modeId = mConnector->GetPreferenceId(); + if (modeId == INVALID_MODE_ID) { + uint32_t num = 0; + ret = GetDisplaySupportedModes(&num, nullptr); + DISPLAY_CHK_RETURN((num == 0) && (ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not get modes")); + modeId = 0; + } + ret = SetDisplayMode(modeId); + // Push first frame to the drm, for that the vblank must init all the componet. + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("set display mode failed")); + return PushFirstFrame(); +} + +int32_t DrmDisplay::RegDisplayVBlankCallback(VBlankCallback cb, void *data) +{ + DISPLAY_DEBUGLOG("the VBlankCallback %{public}p ", cb); + (void)data; + std::shared_ptr vsyncCb = std::make_shared(cb, nullptr, mCrtc->GetPipe()); + DrmVsyncWorker::GetInstance().ReqesterVBlankCb(vsyncCb); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::SetDisplayVsyncEnabled(bool enabled) +{ + DISPLAY_DEBUGLOG("enable %{public}d", enabled); + DrmVsyncWorker::GetInstance().EnableVsync(enabled); + return DISPLAY_SUCCESS; +} + +int32_t DrmDisplay::GetDisplayBacklight(uint32_t *value) +{ + DISPLAY_CHK_RETURN((value == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("value is nullptr")); + return mConnector->GetBrightness(*value); +} + +int32_t DrmDisplay::SetDisplayBacklight(uint32_t value) +{ + return mConnector->SetBrightness(value); +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_display.h b/hardware/display/src/display_device/drm_display.h new file mode 100644 index 0000000000000000000000000000000000000000..31b3bb40b4276598721b3f9d7a34b0ba32e88458 --- /dev/null +++ b/hardware/display/src/display_device/drm_display.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_DISPLAY_H +#define DRM_DISPLAY_H +#include +#include +#include "drm_connector.h" +#include "drm_crtc.h" +#include "drm_device.h" +#include "drm_plane.h" +#include "hdi_composer.h" +#include "hdi_drm_composition.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class DrmDisplay : public HdiDisplay { +public: + DrmDisplay(std::shared_ptr connector, std::shared_ptr crtc, + std::shared_ptr drmDevice); + + ~DrmDisplay() override; + + int32_t Init() override; + int32_t GetDisplayCapability(DisplayCapability *info) override; + int32_t GetDisplaySupportedModes(uint32_t *num, DisplayModeInfo *modes) override; + int32_t GetDisplayMode(uint32_t *modeId) override; + int32_t SetDisplayMode(uint32_t modeId) override; + int32_t GetDisplayPowerStatus(DispPowerStatus *status) override; + int32_t SetDisplayPowerStatus(DispPowerStatus status) override; + int32_t GetDisplayBacklight(uint32_t *value) override; + int32_t SetDisplayBacklight(uint32_t value) override; + int32_t ChosePreferenceMode(); + int32_t RegDisplayVBlankCallback(VBlankCallback cb, void *data) override; + int32_t WaitForVBlank(uint64_t *ns) override; + bool IsConnected() override; + int32_t SetDisplayVsyncEnabled(bool enabled) override; + HdiDrmComposition *GetDrmComposition(); + +protected: + std::unique_ptr CreateHdiLayer(LayerType type) override; + +private: + int32_t PushFirstFrame(); + int32_t ConvertToHdiPowerState(uint32_t drmPowerState, DispPowerStatus &hdiPowerState); + int32_t ConvertToDrmPowerState(DispPowerStatus hdiPowerState, uint32_t &drmPowerState); + std::shared_ptr mDrmDevice; + std::shared_ptr mConnector; + std::shared_ptr mCrtc; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_DISPLAY_H diff --git a/hardware/display/src/display_device/drm_encoder.cpp b/hardware/display/src/display_device/drm_encoder.cpp new file mode 100755 index 0000000000000000000000000000000000000000..c69882a5b3aba33f74639fd9bbf539a527922142 --- /dev/null +++ b/hardware/display/src/display_device/drm_encoder.cpp @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_encoder.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +DrmEncoder::DrmEncoder(drmModeEncoder e) +{ + mEncoderId = e.encoder_id; + mCrtcId = e.crtc_id; + mPossibleCrtcs = e.possible_crtcs; +} + +int32_t DrmEncoder::PickIdleCrtcId(IdMapPtr &crtcs, uint32_t &crtcId) +{ + // find the crtc id; + DISPLAY_DEBUGLOG("crtcs szie %{public}zu", crtcs.size()); + std::shared_ptr crtc; + auto crtcIter = crtcs.find(mCrtcId); + if (crtcIter == crtcs.end()) { + DISPLAY_LOGW("can not find crtc for id %{public}d", mCrtcId); + crtcIter = crtcs.begin(); + return DISPLAY_FAILURE; + } + DISPLAY_CHK_RETURN((crtcIter == crtcs.end()), DISPLAY_FAILURE, + DISPLAY_LOGE("have no crtc %{public}zu ", crtcs.size())); + crtc = crtcIter->second; + DISPLAY_CHK_RETURN((crtc == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("crtc is null")); + + if (!crtc->CanBind()) { + crtc = nullptr; + for (const auto &posCrtcPair : crtcs) { + auto &posCrts = posCrtcPair.second; + DISPLAY_DEBUGLOG("try crtc id : %{public}d", posCrts->GetId()); + if (posCrts->CanBind() && ((1 << posCrts->GetPipe()) & mPossibleCrtcs)) { + crtc = posCrts; + } + } + } + DISPLAY_CHK_RETURN((crtc == nullptr), DISPLAY_FAILURE, + DISPLAY_LOGE("encoder %{public}d can not bind to idle crtc", mEncoderId)); + crtcId = crtc->GetId(); + return DISPLAY_SUCCESS; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_encoder.h b/hardware/display/src/display_device/drm_encoder.h new file mode 100644 index 0000000000000000000000000000000000000000..4f35578a54ef9ac26439f1ebf19cf342307fa509 --- /dev/null +++ b/hardware/display/src/display_device/drm_encoder.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_ENCODER_H +#define DRM_ENCODER_H +#include +#include +#include +#include +#include +#include + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class DrmEncoder { +public: + explicit DrmEncoder(drmModeEncoder e); + virtual ~DrmEncoder() {} + uint32_t GetCrtcId() const + { + return mCrtcId; + } + void SetCrtcId(uint32_t id) + { + mCrtcId = id; + } + uint32_t GetPossibleCrtcs() const + { + return mPossibleCrtcs; + } + int32_t PickIdleCrtcId(IdMapPtr &crtcs, uint32_t &crtcId); + uint32_t GetId() const + { + return mEncoderId; + } + +private: + uint32_t mEncoderId; + uint32_t mCrtcId; + uint32_t mPossibleCrtcs; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // DRM_ENCODER_H \ No newline at end of file diff --git a/hardware/display/src/display_device/drm_plane.cpp b/hardware/display/src/display_device/drm_plane.cpp new file mode 100755 index 0000000000000000000000000000000000000000..8735a3e2671eb966bc1eb62461030dc6d1fcb8f4 --- /dev/null +++ b/hardware/display/src/display_device/drm_plane.cpp @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_plane.h" +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +struct PlaneTypeName planeTypeNames[] = { + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER0_WIN0, "Cluster0-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER0_WIN1, "Cluster0-win1" }, + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER1_WIN0, "Cluster1-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_CLUSTER1_WIN1, "Cluster1-win1" }, + + { DrmPlaneType::DRM_PLANE_TYPE_ESMART0_WIN0, "Esmart0-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART0_WIN1, "Esmart0-win1" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART0_WIN2, "Esmart0-win2" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART0_WIN3, "Esmart0-win3" }, + + { DrmPlaneType::DRM_PLANE_TYPE_ESMART1_WIN0, "Esmart1-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART1_WIN1, "Esmart1-win1" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART1_WIN2, "Esmart1-win2" }, + { DrmPlaneType::DRM_PLANE_TYPE_ESMART1_WIN3, "Esmart1-win3" }, + + { DrmPlaneType::DRM_PLANE_TYPE_SMART0_WIN0, "Smart0-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART0_WIN1, "Smart0-win1" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART0_WIN2, "Smart0-win2" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART0_WIN3, "Smart0-win3" }, + + { DrmPlaneType::DRM_PLANE_TYPE_SMART1_WIN0, "Smart1-win0" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART1_WIN1, "Smart1-win1" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART1_WIN2, "Smart1-win2" }, + { DrmPlaneType::DRM_PLANE_TYPE_SMART1_WIN3, "Smart1-win3" }, + + { DrmPlaneType::DRM_PLANE_TYPE_Unknown, "unknown" }, +}; + +DrmPlane::DrmPlane(drmModePlane &p) + : mId(p.plane_id), mPossibleCrtcs(p.possible_crtcs), mCrtcId(p.crtc_id), + mFormats(p.formats, p.formats + p.count_formats) +{} + +DrmPlane::~DrmPlane() +{ + DISPLAY_DEBUGLOG(); +} + +int DrmPlane::GetCrtcProp(DrmDevice &drmDevice) +{ + int32_t ret; + int32_t crtc_x, crtc_y, crtc_w, crtc_h; + DrmProperty prop; + + ret = drmDevice.GetPlaneProperty(*this, PROP_CRTC_X_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc_x prop id")); + mPropCrtc_xId = prop.propId; + crtc_x = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_CRTC_Y_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc_y prop id")); + mPropCrtc_yId = prop.propId; + crtc_y = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_CRTC_W_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc_w prop id")); + mPropCrtc_wId = prop.propId; + crtc_w = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_CRTC_H_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc_h prop id")); + mPropCrtc_hId = prop.propId; + crtc_h = prop.value; + + DISPLAY_LOGE("plane %{public}d crtc_x %{public}d crtc_y %{public}d crtc_w %{public}d crtc_h %{public}d", + GetId(), crtc_x, crtc_y, crtc_w, crtc_h); + + return 0; +} + +int DrmPlane::GetSrcProp(DrmDevice &drmDevice) +{ + int32_t ret; + int32_t src_x, src_y, src_w, src_h; + DrmProperty prop; + + ret = drmDevice.GetPlaneProperty(*this, PROP_SRC_X_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane src_x prop id")); + mPropSrc_xId = prop.propId; + src_x = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_SRC_Y_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane src_y prop id")); + mPropSrc_yId = prop.propId; + src_y = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_SRC_W_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane src_w prop id")); + mPropSrc_wId = prop.propId; + src_w = prop.value; + + ret = drmDevice.GetPlaneProperty(*this, PROP_SRC_H_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane src_h prop id")); + mPropSrc_hId = prop.propId; + src_h = prop.value; + + DISPLAY_LOGE("plane %{public}d src_x %{public}d src_y %{public}d src_w %{public}d src_h %{public}d", + GetId(), src_x, src_y, src_w, src_h); + + return 0; +} + +int32_t DrmPlane::Init(DrmDevice &drmDevice) +{ + DISPLAY_DEBUGLOG(); + int32_t ret; + uint32_t find_name = 0; + DrmProperty prop; + GetCrtcProp(drmDevice); + GetSrcProp(drmDevice); + ret = drmDevice.GetPlaneProperty(*this, PROP_FBID, prop); + mPropFbId = prop.propId; + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not get plane fb id")); + ret = drmDevice.GetPlaneProperty(*this, PROP_IN_FENCE_FD, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get plane in fence prop id")); + mPropFenceInId = prop.propId; + ret = drmDevice.GetPlaneProperty(*this, PROP_CRTC_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc prop id")); + mPropCrtcId = prop.propId; + + ret = drmDevice.GetPlaneProperty(*this, PROP_ZPOS_ID, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc prop id")); + mPropZposId = prop.propId; + + ret = drmDevice.GetPlaneProperty(*this, "NAME", prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc prop id")); + + for (int i = 0; i < static_castARRAY_SIZE(planeTypeNames); i++) { + find_name = 0; + + for (auto &drmEnum : prop.enums) { + if (!strncmp(drmEnum.name.c_str(), (const char*)planeTypeNames[i].name, + strlen(planeTypeNames[i].name))) { + find_name = (1LL << drmEnum.value); + } + } + + if (find_name) { + DISPLAY_LOGI("find plane id %{public}d, type %{public}x %{public}s", + GetId(), planeTypeNames[i].type, planeTypeNames[i].name); + mWinType = planeTypeNames[i].type; + mName = planeTypeNames[i].name; + break; + } + } + + ret = drmDevice.GetPlaneProperty(*this, PROP_TYPE, prop); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("cat not get pane crtc prop id")); + switch (prop.value) { + case DRM_PLANE_TYPE_OVERLAY: + case DRM_PLANE_TYPE_PRIMARY: + case DRM_PLANE_TYPE_CURSOR: + mType = static_cast(prop.value); + break; + default: + DISPLAY_LOGE("unknown type value %{public}" PRIu64 "", prop.value); + return DISPLAY_FAILURE; + } + return DISPLAY_SUCCESS; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/drm_plane.h b/hardware/display/src/display_device/drm_plane.h new file mode 100755 index 0000000000000000000000000000000000000000..8b29d3913c913a05c721edaa88f579cd65aa3aaf --- /dev/null +++ b/hardware/display/src/display_device/drm_plane.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_PLANE_H +#define DRM_PLANE_H +#include +#include +#include +#include +#include + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +enum class DrmPropertyType { + DRM_PROPERTY_TYPE_INT, + DRM_PROPERTY_TYPE_ENUM, + DRM_PROPERTY_TYPE_OBJECT, + DRM_PROPERTY_TYPE_BLOB, + DRM_PROPERTY_TYPE_BITMASK, + DRM_PROPERTY_TYPE_INVALID, +}; + +enum class DrmPlaneType { + DRM_PLANE_TYPE_CLUSTER0_WIN0 = 1 << 0, + DRM_PLANE_TYPE_CLUSTER0_WIN1 = 1 << 1, + + DRM_PLANE_TYPE_CLUSTER1_WIN0 = 1 << 2, + DRM_PLANE_TYPE_CLUSTER1_WIN1 = 1 << 3, + + DRM_PLANE_TYPE_ESMART0_WIN0 = 1 << 4, + DRM_PLANE_TYPE_ESMART0_WIN1 = 1 << 5, + DRM_PLANE_TYPE_ESMART0_WIN2 = 1 << 6, + DRM_PLANE_TYPE_ESMART0_WIN3 = 1 << 7, + + DRM_PLANE_TYPE_ESMART1_WIN0 = 1 << 8, + DRM_PLANE_TYPE_ESMART1_WIN1 = 1 << 9, + DRM_PLANE_TYPE_ESMART1_WIN2 = 1 << 10, + DRM_PLANE_TYPE_ESMART1_WIN3 = 1 << 11, + + DRM_PLANE_TYPE_SMART0_WIN0 = 1 << 12, + DRM_PLANE_TYPE_SMART0_WIN1 = 1 << 13, + DRM_PLANE_TYPE_SMART0_WIN2 = 1 << 14, + DRM_PLANE_TYPE_SMART0_WIN3 = 1 << 15, + + DRM_PLANE_TYPE_SMART1_WIN0 = 1 << 16, + DRM_PLANE_TYPE_SMART1_WIN1 = 1 << 17, + DRM_PLANE_TYPE_SMART1_WIN2 = 1 << 18, + DRM_PLANE_TYPE_SMART1_WIN3 = 1 << 19, + + DRM_PLANE_TYPE_CLUSTER0_MASK = 0x3, + DRM_PLANE_TYPE_CLUSTER1_MASK = 0xc, + DRM_PLANE_TYPE_CLUSTER_MASK = 0xf, + DRM_PLANE_TYPE_ESMART0_MASK = 0xf0, + DRM_PLANE_TYPE_ESMART1_MASK = 0xf00, + DRM_PLANE_TYPE_SMART0_MASK = 0xf000, + DRM_PLANE_TYPE_SMART1_MASK = 0xf0000, + DRM_PLANE_TYPE_Unknown = 0xffffffff, +}; + +struct PlaneMaskName { + DrmPlaneType mask; + const char *name; +}; + +struct PlaneTypeName { + DrmPlaneType type; + const char *name; +}; + +const std::string PROP_FBID = "FB_ID"; +const std::string PROP_IN_FENCE_FD = "IN_FENCE_FD"; +const std::string PROP_CRTC_ID = "CRTC_ID"; +const std::string PROP_TYPE = "type"; + +const std::string PROP_CRTC_X_ID = "CRTC_X"; +const std::string PROP_CRTC_Y_ID = "CRTC_Y"; +const std::string PROP_CRTC_W_ID = "CRTC_W"; +const std::string PROP_CRTC_H_ID = "CRTC_H"; + +const std::string PROP_SRC_X_ID = "SRC_X"; +const std::string PROP_SRC_Y_ID = "SRC_Y"; +const std::string PROP_SRC_W_ID = "SRC_W"; +const std::string PROP_SRC_H_ID = "SRC_H"; + +const std::string PROP_ZPOS_ID = "zpos"; + +class DrmDevice; + +class DrmPlane { +public: + explicit DrmPlane(drmModePlane &p); + virtual ~DrmPlane(); + int32_t Init(DrmDevice &drmDevice); + int GetCrtcProp(DrmDevice &drmDevice); + int GetSrcProp(DrmDevice &drmDevice); + uint32_t GetId() const + { + return mId; + } + uint32_t GetPropFbId() const + { + return mPropFbId; + } + uint32_t GetPropCrtc_xId() const + { + return mPropCrtc_xId; + } + uint32_t GetPropCrtc_yId() const + { + return mPropCrtc_yId; + } + uint32_t GetPropCrtc_wId() const + { + return mPropCrtc_wId; + } + uint32_t GetPropCrtc_hId() const + { + return mPropCrtc_hId; + } + uint32_t GetPropSrc_xId() const + { + return mPropSrc_xId; + } + uint32_t GetPropSrc_yId() const + { + return mPropSrc_yId; + } + uint32_t GetPropSrc_wId() const + { + return mPropSrc_wId; + } + uint32_t GetPropSrc_hId() const + { + return mPropSrc_hId; + } + uint32_t GetPropZposId() const + { + return mPropZposId; + } + uint32_t GetPropFenceInId() const + { + return mPropFenceInId; + } + uint32_t GetPropCrtcId() const + { + return mPropCrtcId; + } + uint32_t GetPossibleCrtcs() const + { + return mPossibleCrtcs; + } + uint32_t GetType() const + { + return mType; + } + void BindToPipe(uint32_t pipe) + { + mPipe = pipe; + } + void UnBindPipe() + { + mPipe = 0; + } + bool IsIdle() const + { + return (mPipe == 0); + } + uint32_t GetCrtcId() + { + return mCrtcId; + } + uint32_t GetPipe() + { + return mPipe; + } + DrmPlaneType GetWinType() + { + return mWinType; + } + std::string GetName() + { + return mName; + } +private: + uint32_t mId = 0; + uint32_t mPossibleCrtcs = 0; + uint32_t mCrtcId = 0; + uint32_t mPropFbId = 0; + uint32_t mPropFenceInId = 0; + uint32_t mPropCrtcId = 0; + DrmPlaneType mWinType = DrmPlaneType::DRM_PLANE_TYPE_Unknown; + std::string mName; + + uint32_t mPropCrtc_xId = 0; + uint32_t mPropCrtc_yId = 0; + uint32_t mPropCrtc_wId = 0; + uint32_t mPropCrtc_hId = 0; + + uint32_t mPropSrc_xId = 0; + uint32_t mPropSrc_yId = 0; + uint32_t mPropSrc_wId = 0; + uint32_t mPropSrc_hId = 0; + + uint32_t mPropZposId = 0; + + uint32_t mPipe = 0; + uint32_t mType = 0; + std::vector mFormats; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // DRM_PLANE_H diff --git a/hardware/display/src/display_device/drm_vsync_worker.cpp b/hardware/display/src/display_device/drm_vsync_worker.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53ddd63aa399e82d047fe3c5981c3f2da607ec3e --- /dev/null +++ b/hardware/display/src/display_device/drm_vsync_worker.cpp @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drm_vsync_worker.h" +#include +#include "display_common.h" +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +DrmVsyncWorker::DrmVsyncWorker() {} + +int32_t DrmVsyncWorker::Init(int fd) +{ + DISPLAY_CHK_RETURN((fd < 0), DISPLAY_FAILURE, DISPLAY_LOGE("the fd is invalid")); + mDrmFd = fd; + DISPLAY_DEBUGLOG("the drm fd is %{public}d", fd); + mThread = std::make_unique([this]() { WorkThread(); }); + DISPLAY_CHK_RETURN((mThread == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not create thread")); + mRunning = true; + return DISPLAY_SUCCESS; +} + +DrmVsyncWorker &DrmVsyncWorker::GetInstance() +{ + static DrmVsyncWorker instance; + static std::once_flag once; + std::call_once(once, [&]() { + int ret = instance.Init(DrmDevice::GetDrmFd()); + if (ret != DISPLAY_SUCCESS) { + DISPLAY_LOGE("Vsync Worker Init failed"); + } + }); + return instance; +} + +DrmVsyncWorker::~DrmVsyncWorker() +{ + DISPLAY_DEBUGLOG(); + { + std::lock_guard lg(mMutex); + mRunning = false; + } + DISPLAY_DEBUGLOG(); + mCondition.notify_one(); + if (mThread != nullptr) { + mThread->join(); + } + DISPLAY_DEBUGLOG(); +} + +bool DrmVsyncWorker::WaitSignalAndCheckRuning() +{ + std::unique_lock ul(mMutex); + mCondition.wait(ul, [this]() { return (mEnable || !mRunning); }); + return mRunning; +} + + +uint64_t DrmVsyncWorker::WaitNextVBlank(unsigned int &sq) +{ + constexpr uint64_t SEC_TO_NSEC = 1000 * 1000 * 1000; + constexpr uint64_t USEC_TO_NSEC = 1000; + drmVBlank vblank = { + .request = + drmVBlankReq { + .type = DRM_VBLANK_RELATIVE, + .sequence = 1, + .signal = 0, + } + }; + /* The drmWaitVBlank need set the crtc pipe when there are multi crtcs in the system. */ + if (mCallBack->GetPipe() == 1) + vblank.request.type = drmVBlankSeqType((int)(vblank.request.type) | (int)DRM_VBLANK_SECONDARY); + int ret = drmWaitVBlank(mDrmFd, &vblank); + DISPLAY_CHK_RETURN((ret < 0), 0, + DISPLAY_LOGE("wait vblank failed ret :　%{public}d　errno %{public}d", ret, errno)); + sq = vblank.reply.sequence; + return (uint64_t)(vblank.reply.tval_sec * SEC_TO_NSEC + vblank.reply.tval_usec * USEC_TO_NSEC); +} + + +void DrmVsyncWorker::EnableVsync(bool enable) +{ + DISPLAY_DEBUGLOG(); + { + std::lock_guard lg(mMutex); + mEnable = enable; + } + mCondition.notify_one(); +} + +void DrmVsyncWorker::WorkThread() +{ + DISPLAY_DEBUGLOG(); + unsigned int seq = 0; + while (WaitSignalAndCheckRuning()) { + // wait the vblank + uint64_t time = WaitNextVBlank(seq); + if (mCallBack != nullptr) { + mCallBack->Vsync(seq, time); + } else { + DISPLAY_LOGE("the callbac is nullptr"); + } + } +} + +void DrmVsyncWorker::ReqesterVBlankCb(std::shared_ptr &cb) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN_NOT_VALUE((cb == nullptr), DISPLAY_LOGE("the VBlankCallback is nullptr ")); + mCallBack = cb; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY \ No newline at end of file diff --git a/hardware/display/src/display_device/drm_vsync_worker.h b/hardware/display/src/display_device/drm_vsync_worker.h new file mode 100644 index 0000000000000000000000000000000000000000..c578e91c49e9fc8722115ef711cfd097fe1a3737 --- /dev/null +++ b/hardware/display/src/display_device/drm_vsync_worker.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DRM_VSYNC_WORKER_H +#define DRM_VSYNC_WORKER_H +#include +#include +#include +#include +#include "display_device.h" +#include "hdi_device_common.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class DrmVsyncWorker { +public: + DrmVsyncWorker(); + virtual ~DrmVsyncWorker(); + int32_t Init(int fd); + static DrmVsyncWorker &GetInstance(); + + void EnableVsync(bool enable); + void WorkThread(); + uint64_t WaitNextVBlank(unsigned int &sq); + bool WaitSignalAndCheckRuning(); + void ReqesterVBlankCb(std::shared_ptr &cb); + +private: + int mDrmFd = 0; + std::unique_ptr mThread; + bool mEnable = false; + std::mutex mMutex; + std::condition_variable mCondition; + std::shared_ptr mCallBack; + bool mRunning = false; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // DRM_VSYNC_WORKER_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_composer.cpp b/hardware/display/src/display_device/hdi_composer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04eefdbcf0fefbbd48ede43d5cd37c50150e6d5f --- /dev/null +++ b/hardware/display/src/display_device/hdi_composer.cpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_composer.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +HdiComposer::HdiComposer(std::unique_ptr pre, std::unique_ptr post) +{ + mPreComp = std::move(pre); + mPostComp = std::move(post); +} + +int32_t HdiComposer::Prepare(std::vector &layers, HdiLayer &clientLayer) +{ + int ret = mPreComp->SetLayers(layers, clientLayer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("pre composition prepare failed")); + ret = mPostComp->SetLayers(layers, clientLayer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("post composition prepare failed")); + return DISPLAY_SUCCESS; +} + +int32_t HdiComposer::Commit(bool modeSet) +{ + int ret = mPreComp->Apply(modeSet); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("pre composition apply failed")); + ret = mPostComp->Apply(modeSet); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("post composition apply failed")); + return DISPLAY_SUCCESS; +} +} // OHOS +} // HDI +} // DISPLAY diff --git a/hardware/display/src/display_device/hdi_composer.h b/hardware/display/src/display_device/hdi_composer.h new file mode 100644 index 0000000000000000000000000000000000000000..a3b69de50dd58f1af8317533bf1ce9ab4fb23e38 --- /dev/null +++ b/hardware/display/src/display_device/hdi_composer.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_COMPOSER_H +#define HDI_COMPOSER_H +#include +#include +#include "hdi_layer.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiComposition { +public: + HdiComposition() {} + virtual int32_t Init() + { + return DISPLAY_SUCCESS; + }; + virtual int32_t SetLayers(std::vector &layers, HdiLayer &clientLayer) + { + return DISPLAY_SUCCESS; + } + virtual int32_t Apply(bool modeSet) + { + return DISPLAY_SUCCESS; + } + virtual ~HdiComposition() {} + +protected: + std::vector mCompLayers; +}; + +class HdiComposer { +public: + HdiComposer(std::unique_ptr pre, std::unique_ptr post); + virtual ~HdiComposer() {}; + int32_t Prepare(std::vector &layers, HdiLayer &clientLayer); + int32_t Commit(bool modeSet); + HdiComposition *GetPreCompostion() + { + return mPreComp.get(); + } + HdiComposition *GetPostCompostion() + { + return mPostComp.get(); + } + +private: + std::unique_ptr mPreComp; + std::unique_ptr mPostComp; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_COMPOSER_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_device_common.h b/hardware/display/src/display_device/hdi_device_common.h new file mode 100644 index 0000000000000000000000000000000000000000..c5ceaf092a29ef909e045ffa8916668e69910c67 --- /dev/null +++ b/hardware/display/src/display_device/hdi_device_common.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_DEVICE_COMMON_H +#define HDI_DEVICE_COMMON_H +#include +#include +#include "display_type.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const int32_t INVALID_MODE_ID = -1; +const uint32_t DRM_INVALID_ID = 0xFFFFFFFF; +template using IdMapPtr = std::unordered_map>; +class DrmEncoder; +class DrmCrtc; +class DrmPlane; +class DrmDevice; +class DrmConnector; +class VsyncCallBack; +class DrmVsyncWorker; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_DEVICE_COMMON_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_device_interface.cpp b/hardware/display/src/display_device/hdi_device_interface.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f79074b9f9516b224afa8b109cdb87a2c37a3be --- /dev/null +++ b/hardware/display/src/display_device/hdi_device_interface.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_device_interface.h" +#include +#include "display_common.h" +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +std::vector> HdiDeviceInterface::DiscoveryDevice() +{ + DISPLAY_DEBUGLOG(); + int ret; + std::vector> devices; + std::shared_ptr drmDevice = DrmDevice::Create(); + if (!drmDevice) { + DISPLAY_LOGE("can not create drm device"); + } + ret = drmDevice->Init(); + if (ret == DISPLAY_SUCCESS) { + DISPLAY_DEBUGLOG("drm device init success"); + devices.push_back(std::move(drmDevice)); + } else { + DISPLAY_LOGE("drm device init failed"); + } + return devices; +} +} +} +} \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_device_interface.h b/hardware/display/src/display_device/hdi_device_interface.h new file mode 100644 index 0000000000000000000000000000000000000000..f0bb3cccd4137bf53a02ff7c48d03b77a5ba3eb4 --- /dev/null +++ b/hardware/display/src/display_device/hdi_device_interface.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_DEVICE_INTERFACE_H +#define HDI_DEVICE_INTERFACE_H +#include +#include +#include +#include "hdi_display.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiDeviceInterface { +public: + static std::vector> DiscoveryDevice(); + virtual std::unordered_map> DiscoveryDisplay() = 0; + virtual bool HandleHotplug(uint32_t dispId, bool plugIn) = 0; + virtual int32_t Init() = 0; + virtual void DeInit() = 0; + virtual ~HdiDeviceInterface() {}; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_DEVICE_INTERFACE_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_display.cpp b/hardware/display/src/display_device/hdi_display.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf229c0062b5c979319f374b189e0df7dd673b47 --- /dev/null +++ b/hardware/display/src/display_device/hdi_display.cpp @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_display.h" +#include +#include "display_common.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +uint32_t HdiDisplay::mIdleId = 0; +std::unordered_set HdiDisplay::mIdSets; + +uint32_t HdiDisplay::GetIdleId() +{ + const uint32_t oldIdleId = mIdleId; + uint32_t id = INVALIDE_DISPLAY_ID; + // ensure the mIdleId not INVALIDE_DISPLAY_ID + mIdleId = mIdleId % INVALIDE_DISPLAY_ID; + do { + auto iter = mIdSets.find(mIdleId); + if (iter == mIdSets.end()) { + id = mIdleId; + break; + } + mIdleId = (mIdleId + 1) % INVALIDE_DISPLAY_ID; + } while (oldIdleId != mIdleId); + mIdSets.emplace(id); + mIdleId++; + return id; +} + + +int32_t HdiDisplay::Init() +{ + DISPLAY_DEBUGLOG(); + uint32_t id = GetIdleId(); + DISPLAY_CHK_RETURN((id == INVALIDE_DISPLAY_ID), DISPLAY_FAILURE, DISPLAY_LOGE("have no id to used")); + mId = id; + auto layer = CreateHdiLayer(LAYER_TYPE_GRAPHIC); + DISPLAY_CHK_RETURN((layer.get() == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not create hdi layer for client")); + mClientLayer = std::move(layer); + DISPLAY_DEBUGLOG("the id is %{public}d", id); + return DISPLAY_SUCCESS; +} + + +HdiDisplay::~HdiDisplay() +{ + mIdSets.erase(mId); +} + +int32_t HdiDisplay::SetLayerZorder(uint32_t layerId, uint32_t zorder) +{ + DISPLAY_DEBUGLOG("layerId : %{public}d", layerId); + auto iter = mLayersMap.find(layerId); + DISPLAY_CHK_RETURN((iter == mLayersMap.end()), DISPLAY_FAILURE, + DISPLAY_LOGE("can not find the layer %{public}d", layerId)); + auto layer = mLayersMap[layerId].get(); + if (layer->GetZorder() == zorder) { + DISPLAY_DEBUGLOG("zorder no change layerId %{public}d, zorder %{public}d", layerId, zorder); + return DISPLAY_SUCCESS; + } + // reset to sort + auto zRange = mLayers.equal_range(layer); + DISPLAY_DEBUGLOG("zorder range : zRange.first %{public}p zRange.second %{public}p", *zRange.first, *zRange.second); + for (auto c = zRange.first; c != zRange.second; c++) { + if (*c == layer) { + mLayers.erase(c); + break; + } + } + layer->SetLayerZorder(zorder); + mLayers.emplace(layer); + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::CreateLayer(const LayerInfo *layerInfo, uint32_t *layerId) +{ + DISPLAY_DEBUGLOG(); + int ret; + DISPLAY_CHK_RETURN((layerInfo == nullptr), DISPLAY_PARAM_ERR, DISPLAY_LOGE("LayerInfo is null")); + DISPLAY_CHK_RETURN((layerId == nullptr), DISPLAY_PARAM_ERR, DISPLAY_LOGE("layerId is null")); + auto layer = CreateHdiLayer(layerInfo->type); + DISPLAY_CHK_RETURN((layer.get() == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not create hdi layer")); + ret = layer->Init(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("Layer Init failed")); + *layerId = layer->GetId(); + mLayers.insert(layer.get()); + mLayersMap.emplace(layer->GetId(), std::move(layer)); + DISPLAY_DEBUGLOG("mLayers size %{public}zu", mLayers.size()); + DISPLAY_DEBUGLOG("mLayerMap size %{public}zu", mLayersMap.size()); + return DISPLAY_SUCCESS; +} + +std::unique_ptr HdiDisplay::CreateHdiLayer(LayerType type) +{ + DISPLAY_DEBUGLOG(); + return std::make_unique(type); +} + + +int32_t HdiDisplay::CloseLayer(uint32_t layerId) +{ + DISPLAY_DEBUGLOG("layerId %{public}d", layerId); + auto iter = mLayersMap.find(layerId); + DISPLAY_CHK_RETURN((iter == mLayersMap.end()), DISPLAY_FAILURE, + DISPLAY_LOGE("can not find the layer id %{public}d", layerId)); + mLayers.erase(iter->second.get()); + mLayersMap.erase(layerId); + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::GetDisplayCompChange(uint32_t *num, uint32_t *layers, int32_t *type) +{ + DISPLAY_CHK_RETURN((num == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("the num is nullptr")); + *num = mChangeLayers.size(); + if ((layers == nullptr) && (type == nullptr)) { + return DISPLAY_SUCCESS; + } + DISPLAY_DEBUGLOG("set the layers and type"); + for (uint32_t i = 0; i < mChangeLayers.size(); i++) { + HdiLayer *layer = mChangeLayers[i]; + if (layers != nullptr) { + *(layers + i) = layer->GetId(); + } + if (type != nullptr) { + *(type + i) = layer->GetCompositionType(); + } + } + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::GetDisplayReleaseFence(uint32_t *num, uint32_t *layers, int32_t *fences) +{ + DISPLAY_CHK_RETURN((num == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("the num is nullptr")); + *num = mLayers.size(); + if ((layers == nullptr) && (fences == nullptr)) { + return DISPLAY_SUCCESS; + } + DISPLAY_DEBUGLOG("set the layer fences"); + int i = 0; + for (auto layer : mLayers) { + if (layers != nullptr) { + *(layers + i) = layer->GetId(); + } + if (fences != nullptr) { + *(fences + i) = dup(layer->GetReleaseFenceFd()); + } + DISPLAY_DEBUGLOG("layer id %{public}d fencefd %{public}d", layer->GetId(), layer->GetReleaseFenceFd()); + i++; + } + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::PrepareDisplayLayers(bool *needFlushFb) +{ + DISPLAY_DEBUGLOG(); + mChangeLayers.clear(); + std::vector layers; + uint32_t topZpos = 3; + for (auto c : mLayers) { + layers.push_back(c); + } + DISPLAY_DEBUGLOG(" mLayers size %{public}zu layers size %{public}zu", mLayers.size(), layers.size()); + + /* Set the target layer to the top. + * It would not by cover by other layer. + */ + mClientLayer->SetLayerZorder(topZpos); + + mComposer->Prepare(layers, *mClientLayer); + // get the change layers + for (auto &layer : layers) { + if (layer->GetDeviceSelect() != layer->GetCompositionType()) { + DISPLAY_DEBUGLOG("layer change"); + layer->SetLayerCompositionType(layer->GetDeviceSelect()); + } + mChangeLayers.push_back(layer); + } + *needFlushFb = true; + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::Commit(int32_t *fence) +{ + DISPLAY_DEBUGLOG(); + mComposer->Commit(false); + *fence = dup(mClientLayer->GetReleaseFenceFd()); + DISPLAY_DEBUGLOG("the release fence is %{public}d", *fence); + return DISPLAY_SUCCESS; +} + +int32_t HdiDisplay::SetDisplayClientBuffer(const BufferHandle *buffer, int32_t fence) +{ + mClientLayer->SetLayerBuffer(buffer, fence); + return DISPLAY_SUCCESS; +} + +HdiLayer *HdiDisplay::GetHdiLayer(uint32_t id) +{ + DISPLAY_DEBUGLOG("id : %{public}d", id); + auto iter = mLayersMap.find(id); + DISPLAY_CHK_RETURN((iter == mLayersMap.end()), nullptr, DISPLAY_LOGE("can not find the layer %{public}d", id)); + return iter->second.get(); +} + +VsyncCallBack::VsyncCallBack(VBlankCallback cb, void *data, uint32_t displayId) : mVBlankCb(cb), + mData(data), mPipe(displayId) +{ + DISPLAY_DEBUGLOG("VsyncCallBack %{public}p", cb); +} + +void VsyncCallBack::Vsync(unsigned int sequence, uint64_t ns) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((mVBlankCb == nullptr), DISPLAY_LOGE("the callback is nullptr")); + mVBlankCb(sequence, ns, mData); +} +} +} +} diff --git a/hardware/display/src/display_device/hdi_display.h b/hardware/display/src/display_device/hdi_display.h new file mode 100644 index 0000000000000000000000000000000000000000..277b55cfbb345ae6db02555dabe5bdee21ba8803 --- /dev/null +++ b/hardware/display/src/display_device/hdi_display.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_DISPLAY_H +#define HDI_DISPLAY_H +#include +#include +#include +#include +#include "display_device.h" +#include "hdi_composer.h" +#include "hdi_layer.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const uint32_t INVALIDE_DISPLAY_ID = 0xffffffff; +const uint32_t DISPLAY_TYPE_DRM = (1 << 31); + +class VsyncCallBack { +public: + VsyncCallBack(VBlankCallback cb, void *data, uint32_t pipe); + virtual void Vsync(unsigned int sequence, uint64_t ns); + virtual ~VsyncCallBack() {} + uint32_t GetPipe() + { + return mPipe; + } +private: + VBlankCallback mVBlankCb; + void *mData; + uint32_t mPipe; +}; + + +class HdiDisplay { +public: + uint32_t GetId() const + { + return mId; + } + virtual int32_t Init(); + virtual void DeInit() {} + HdiDisplay() {} + virtual ~HdiDisplay(); + virtual int32_t GetDisplayCapability(DisplayCapability *info) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t GetDisplaySupportedModes(uint32_t *num, DisplayModeInfo *modes) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t GetDisplayMode(uint32_t *modeId) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t SetDisplayMode(uint32_t modeId) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t GetDisplayPowerStatus(DispPowerStatus *status) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t SetDisplayPowerStatus(DispPowerStatus status) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t GetDisplayBacklight(uint32_t *value) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t SetDisplayBacklight(uint32_t value) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t CreateLayer(const LayerInfo *layerInfo, uint32_t *layerId); + virtual int32_t CloseLayer(uint32_t layerId); + virtual int32_t PrepareDisplayLayers(bool *needFlushFb); + virtual int32_t Commit(int32_t *fence); + virtual int32_t GetDisplayCompChange(uint32_t *num, uint32_t *layers, int32_t *type); + virtual int32_t SetLayerZorder(uint32_t layerId, uint32_t zorder); + virtual bool IsConnected() + { + return false; + } + virtual int32_t RegDisplayVBlankCallback(VBlankCallback cb, void *data) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t SetDisplayVsyncEnabled(bool enabled) + { + return DISPLAY_NOT_SUPPORT; + } + virtual int32_t GetDisplayReleaseFence(uint32_t *num, uint32_t *layers, int32_t *fences); + virtual int32_t SetDisplayClientBuffer(const BufferHandle *buffer, int32_t fence); + virtual int32_t WaitForVBlank(uint64_t *ns) + { + return DISPLAY_NOT_SUPPORT; + } + HdiLayer *GetHdiLayer(uint32_t id); + +protected: + virtual std::unique_ptr CreateHdiLayer(LayerType type); + std::unique_ptr mComposer; + + static uint32_t GetIdleId(); + static uint32_t mIdleId; + static std::unordered_set mIdSets; + uint32_t mId = INVALIDE_DISPLAY_ID; + std::unordered_map> mLayersMap; + std::multiset mLayers; + std::unique_ptr mClientLayer; + std::vector mChangeLayers; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_DISPLAY_H diff --git a/hardware/display/src/display_device/hdi_drm_composition.cpp b/hardware/display/src/display_device/hdi_drm_composition.cpp new file mode 100755 index 0000000000000000000000000000000000000000..cfeb1fc5979df28b248dbdd5676cfe44bb7af896 --- /dev/null +++ b/hardware/display/src/display_device/hdi_drm_composition.cpp @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_drm_composition.h" +#include +#include "hdi_drm_layer.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +HdiDrmComposition::HdiDrmComposition(const std::shared_ptr &connector, + const std::shared_ptr &crtc, + const std::shared_ptr &drmDevice) + : mDrmDevice(drmDevice), mConnector(connector), mCrtc(crtc) +{ + DISPLAY_DEBUGLOG(); +} + +int32_t HdiDrmComposition::Init() +{ + DISPLAY_DEBUGLOG(); + mPrimPlanes.clear(); + mOverlayPlanes.clear(); + mPlanes.clear(); + DISPLAY_CHK_RETURN((mCrtc == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("crtc is null")); + DISPLAY_CHK_RETURN((mConnector == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("connector is null")); + DISPLAY_CHK_RETURN((mDrmDevice == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("drmDevice is null")); + mPrimPlanes = mDrmDevice->GetDrmPlane(mCrtc->GetPipe(), DRM_PLANE_TYPE_PRIMARY); + mOverlayPlanes = mDrmDevice->GetDrmPlane(mCrtc->GetPipe(), DRM_PLANE_TYPE_OVERLAY); + mPlanes.insert(mPlanes.end(), mPrimPlanes.begin(), mPrimPlanes.end()); + mPlanes.insert(mPlanes.end(), mOverlayPlanes.begin(), mOverlayPlanes.end()); + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::SetLayers(std::vector &layers, HdiLayer &clientLayer) +{ + // now we do not surpport present direct + DISPLAY_DEBUGLOG(); + mCompLayers.clear(); + mCompLayers.push_back(&clientLayer); + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::SetCrtcProperty(DrmPlane &drmPlane, + drmModeAtomicReqPtr pset, + int32_t bufferW, + int32_t bufferH) +{ + int ret; + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropCrtc_xId(), 0); + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropCrtc_xId %{public}d, crop.x %{public}d", drmPlane.GetId(), + drmPlane.GetPropCrtc_xId(), 0); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropCrtc_yId(), 0); + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropCrtc_yId %{public}d, crop.y %{public}d", drmPlane.GetId(), + drmPlane.GetPropCrtc_yId(), 0); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropCrtc_wId(), bufferW); + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropCrtc_wId %{public}d, crop.w %{public}d", drmPlane.GetId(), + drmPlane.GetPropCrtc_wId(), bufferW); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropCrtc_hId(), bufferH); + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropCrtc_hId %{public}d, crop.h %{public}d", drmPlane.GetId(), + drmPlane.GetPropCrtc_xId(), bufferH); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::SetSrcProperty(DrmPlane &drmPlane, + drmModeAtomicReqPtr pset, + int32_t bufferW, + int32_t bufferH) +{ + int ret; + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropSrc_xId(), 0<<16); // 16:shift left 16 bits + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropSrc_xId %{public}d, displayRect.x %{public}d", drmPlane.GetId(), + drmPlane.GetPropSrc_xId(), 0); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropSrc_yId(), 0<<16); // 16:shift left 16 bits + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropSrc_yId %{public}d, displayRect.y %{public}d", drmPlane.GetId(), + drmPlane.GetPropSrc_yId(), 0); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropSrc_wId(), + bufferW<<16); // 16:shift left 16 bits + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropCrtc_wId %{public}d, displayRect.w %{public}d", + drmPlane.GetId(), drmPlane.GetPropSrc_wId(), bufferW); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropSrc_hId(), + bufferH<<16); // 16:shift left 16 bits + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropSrc_hId %{public}d, displayRect.h %{public}d", drmPlane.GetId(), + drmPlane.GetPropSrc_hId(), bufferH); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the fb planeid fialed errno : %{public}d", errno)); + + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::ApplyPlane(HdiDrmLayer &layer, + HdiLayer &hlayer, + DrmPlane &drmPlane, + drmModeAtomicReqPtr pset) +{ + int ret; + int fenceFd = layer.GetAcquireFenceFd(); + int propId = drmPlane.GetPropFenceInId(); + HdiLayerBuffer *layerBuffer = hlayer.GetCurrentBuffer(); + int32_t bufferW = layerBuffer->GetWight(); + int32_t bufferH = layerBuffer->GetHeight(); + + DISPLAY_DEBUGLOG(); + if (propId != 0) { + DISPLAY_LOGI("set the fence in prop"); + if (fenceFd >= 0) { + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), propId, fenceFd); + DISPLAY_DEBUGLOG("set the IfenceProp plane id %{public}d, propId %{public}d, fenceFd %{public}d", + drmPlane.GetId(), propId, fenceFd); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set IN_FENCE_FD failed")); + } + } + + ret = SetCrtcProperty(drmPlane, pset, bufferW, bufferH); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set Crtc fialed errno : %{public}d", errno)); + + ret = SetSrcProperty(drmPlane, pset, bufferW, bufferH); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set Src fialed errno : %{public}d", errno)); + + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropZposId(), layer.GetZorder()); + DISPLAY_LOGI("set the fb planeid %{public}d, GetPropZposId %{public}d, zpos %{public}d", drmPlane.GetId(), + drmPlane.GetPropZposId(), layer.GetZorder()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the zpos fialed errno : %{public}d", errno)); + + // set fb id + DrmGemBuffer *gemBuffer = layer.GetGemBuffer(); + DISPLAY_CHK_RETURN((gemBuffer == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("current gemBuffer is nullptr")); + DISPLAY_CHK_RETURN((!gemBuffer->IsValid()), DISPLAY_FAILURE, DISPLAY_LOGE("the DrmGemBuffer is invalid")); + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropFbId(), gemBuffer->GetFbId()); + DISPLAY_DEBUGLOG("set the fb planeid %{public}d, propId %{public}d, fbId %{public}d", drmPlane.GetId(), + drmPlane.GetPropFbId(), gemBuffer->GetFbId()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set fb id fialed errno : %{public}d", errno)); + + // set crtc id + ret = drmModeAtomicAddProperty(pset, drmPlane.GetId(), drmPlane.GetPropCrtcId(), mCrtc->GetId()); + DISPLAY_DEBUGLOG("set the crtc planeId %{public}d, propId %{public}d, crtcId %{public}d", drmPlane.GetId(), + drmPlane.GetPropCrtcId(), mCrtc->GetId()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set crtc id fialed errno : %{public}d", errno)); + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::UpdateMode(std::unique_ptr &modeBlock, drmModeAtomicReq &pset) +{ + // set the mode + DISPLAY_LOGI(); + if (mCrtc->NeedModeSet()) { + modeBlock = mConnector->GetModeBlockFromId(mCrtc->GetActiveModeId()); + if ((modeBlock != nullptr) && (modeBlock->GetBlockId() != DRM_INVALID_ID)) { + // set to active + DISPLAY_DEBUGLOG("set crtc to active"); + int ret = drmModeAtomicAddProperty(&pset, mCrtc->GetId(), mCrtc->GetActivePropId(), 1); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, + DISPLAY_LOGE("can not add the active prop errno %{public}d", errno)); + + // set the mode id + DISPLAY_DEBUGLOG("set the mode"); + ret = drmModeAtomicAddProperty(&pset, mCrtc->GetId(), mCrtc->GetModePropId(), modeBlock->GetBlockId()); + DISPLAY_LOGI("set the mode planeId %{public}d, propId %{public}d, GetBlockId: %{public}d", mCrtc->GetId(), + mCrtc->GetModePropId(), modeBlock->GetBlockId()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, + DISPLAY_LOGE("can not add the mode prop errno %{public}d", errno)); + ret = drmModeAtomicAddProperty(&pset, mConnector->GetId(), mConnector->GetPropCrtcId(), mCrtc->GetId()); + DISPLAY_LOGI("set the connector id: %{public}d, propId %{public}d, crtcId %{public}d", mConnector->GetId(), + mConnector->GetPropCrtcId(), mCrtc->GetId()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, + DISPLAY_LOGE("can not add the crtc id prop %{public}d", errno)); + } + } + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::RemoveUnusePlane(drmModeAtomicReqPtr pset) +{ + int ret = 0; + /* Remove useless planes from the drm */ + for (uint32_t j = 0; j < mPlanes.size(); j++) { + auto &drmPlane = mPlanes[j]; + if ((static_cast(drmPlane->GetWinType()) & mCrtc->GetPlaneMask()) && drmPlane->GetPipe() == 0) { + DISPLAY_LOGI("no used plane %{public}s id %{public}d", drmPlane->GetName().c_str(), drmPlane->GetId()); + ret = drmModeAtomicAddProperty(pset, drmPlane->GetId(), drmPlane->GetPropFbId(), 0); + ret = drmModeAtomicAddProperty(pset, drmPlane->GetId(), drmPlane->GetPropFbId(), 0); + drmPlane->UnBindPipe(); + } + } + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::FindPlaneAndApply(drmModeAtomicReqPtr pset) +{ + int32_t ret = 0; + for (uint32_t i = 0; i < mCompLayers.size(); i++) { + HdiDrmLayer *layer = static_cast(mCompLayers[i]); + HdiLayer *hlayer = mCompLayers[i]; + for (uint32_t j = 0; j < mPlanes.size(); j++) { + auto &drmPlane = mPlanes[j]; + if (drmPlane->GetPipe() != 0 && drmPlane->GetPipe() != (1 << mCrtc->GetPipe())) { + DISPLAY_LOGI("plane %{public}d used pipe %{public}d crtc pipe %{public}d", drmPlane->GetId(), + drmPlane->GetPipe(), mCrtc->GetPipe()); + continue; + } + /* Check whether the plane belond to the crtc */ + if (!(static_cast(drmPlane->GetWinType()) & mCrtc->GetPlaneMask())) { + continue; + } + DISPLAY_LOGI("use plane %{public}d WinType %{public}x crtc %{public}d PlaneMask %{public}x", + drmPlane->GetId(), drmPlane->GetWinType(), mCrtc->GetId(), mCrtc->GetPlaneMask()); + + if (drmPlane->GetCrtcId() == mCrtc->GetId() || drmPlane->GetCrtcId() == 0) { + ret = ApplyPlane(*layer, *hlayer, *drmPlane, pset); + if (ret != DISPLAY_SUCCESS) { + DISPLAY_LOGE("apply plane failed"); + break; + } + /* mark the plane is used by crtc */ + drmPlane->BindToPipe(1 << mCrtc->GetPipe()); + break; + } + } + } + return DISPLAY_SUCCESS; +} + +int32_t HdiDrmComposition::Apply(bool modeSet) +{ + uint64_t crtcOutFence = -1; + int ret = 0; + std::unique_ptr modeBlock; + int drmFd = mDrmDevice->GetDrmFd(); + + DISPLAY_LOGI("mPlane size: %{public}zd mCompLayers size: %{public}zd", mPlanes.size(), mCompLayers.size()); + DISPLAY_CHK_RETURN((mPlanes.size() < mCompLayers.size()), DISPLAY_FAILURE, DISPLAY_LOGE("plane not enough")); + drmModeAtomicReqPtr pset = drmModeAtomicAlloc(); + DISPLAY_CHK_RETURN((pset == nullptr), DISPLAY_NULL_PTR, + DISPLAY_LOGE("drm atomic alloc failed errno %{public}d", errno)); + AtomicReqPtr atomicReqPtr = AtomicReqPtr(pset); + + // set the outFence property + ret = drmModeAtomicAddProperty(atomicReqPtr.Get(), mCrtc->GetId(), mCrtc->GetOutFencePropId(), + (uint64_t)&crtcOutFence); + + DISPLAY_DEBUGLOG("Apply Set OutFence crtc id: %{public}d, fencePropId %{public}d", mCrtc->GetId(), + mCrtc->GetOutFencePropId()); + DISPLAY_CHK_RETURN((ret < 0), DISPLAY_FAILURE, DISPLAY_LOGE("set the outfence property of crtc failed ")); + + // set the plane info. + DISPLAY_LOGI("mCompLayers size %{public}zd", mCompLayers.size()); + DISPLAY_LOGI("crtc id %{public}d connect id %{public}d encoder id %{public}d", mCrtc->GetId(), + mConnector->GetId(), mConnector->GetEncoderId()); + + /* Bind the plane not used by other crtcs to the crtc. */ + FindPlaneAndApply(atomicReqPtr.Get()); + /* Remove useless planes from the drm */ + RemoveUnusePlane(atomicReqPtr.Get()); + + ret = UpdateMode(modeBlock, *(atomicReqPtr.Get())); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("update mode failed")); + uint32_t flags = DRM_MODE_ATOMIC_ALLOW_MODESET; + + ret = drmModeAtomicCommit(drmFd, atomicReqPtr.Get(), flags, nullptr); + DISPLAY_CHK_RETURN((ret != 0), DISPLAY_FAILURE, + DISPLAY_LOGE("drmModeAtomicCommit failed %{public}d errno %{public}d", ret, errno)); + // set the release fence + for (auto layer : mCompLayers) { + layer->SetReleaseFence(static_cast(crtcOutFence)); + } + + return DISPLAY_SUCCESS; +} +} // OHOS +} // HDI +} // DISPLAY diff --git a/hardware/display/src/display_device/hdi_drm_composition.h b/hardware/display/src/display_device/hdi_drm_composition.h new file mode 100755 index 0000000000000000000000000000000000000000..042ff3c49fb38009123a625bbb0a715b0d9cc776 --- /dev/null +++ b/hardware/display/src/display_device/hdi_drm_composition.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_DRM_COMPOSITION_H +#define HDI_DRM_COMPOSITION_H +#include +#include +#include +#include +#include "drm_device.h" +#include "hdi_composer.h" +#include "hdi_device_common.h" +#include "hdi_drm_layer.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class AtomicReqPtr { +public: + explicit AtomicReqPtr(drmModeAtomicReqPtr ptr) : mPtr(ptr) {} + virtual ~AtomicReqPtr() + { + if (mPtr != nullptr) + drmModeAtomicFree(mPtr); + } + drmModeAtomicReqPtr Get() const + { + return mPtr; + } + +private: + drmModeAtomicReqPtr mPtr; +}; + +class HdiDrmComposition : public HdiComposition { +public: + HdiDrmComposition(const std::shared_ptr &connector, + const std::shared_ptr &crtc, + const std::shared_ptr &drmDevice); + ~HdiDrmComposition() override {} + int32_t Init() override; + int32_t SetLayers(std::vector &layers, HdiLayer &clientLayer) override; + int32_t Apply(bool modeSet) override; + int32_t UpdateMode(std::unique_ptr &modeBlock, drmModeAtomicReq &pset); + +private: + int32_t ApplyPlane(HdiDrmLayer &layer, HdiLayer &hlayer, DrmPlane &drmPlane, drmModeAtomicReqPtr pset); + int32_t SetSrcProperty(DrmPlane &drmPlane, drmModeAtomicReqPtr pset, int32_t bufferW, int32_t bufferH); + int32_t SetCrtcProperty(DrmPlane &drmPlane, drmModeAtomicReqPtr pset, int32_t bufferW, int32_t bufferH); + int32_t RemoveUnusePlane(drmModeAtomicReqPtr pset); + int32_t FindPlaneAndApply(drmModeAtomicReqPtr pset); + std::shared_ptr mDrmDevice; + std::shared_ptr mConnector; + std::shared_ptr mCrtc; + std::vector> mPrimPlanes; + std::vector> mOverlayPlanes; + std::vector> mPlanes; +}; +} // OHOS +} // HDI +} // DISPLAY + +#endif // HDI_DRM_COMPOSITION_H diff --git a/hardware/display/src/display_device/hdi_drm_layer.cpp b/hardware/display/src/display_device/hdi_drm_layer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5cb701fead6d885993de81477d0e5d7c56781b65 --- /dev/null +++ b/hardware/display/src/display_device/hdi_drm_layer.cpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_drm_layer.h" +#include +#include +#include "drm_device.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +DrmGemBuffer::DrmGemBuffer(int drmFd, HdiLayerBuffer &hdl) : mDrmFd(drmFd) +{ + DISPLAY_DEBUGLOG(); + Init(mDrmFd, hdl); +} + +void DrmGemBuffer::Init(int drmFd, HdiLayerBuffer &hdl) +{ + int ret; + const int MAX_COUNT = 4; + uint32_t pitches[MAX_COUNT] = {0}; + uint32_t gemHandles[MAX_COUNT] = {0}; + uint32_t offsets[MAX_COUNT] = {0}; + DISPLAY_DEBUGLOG("hdl %{public}" PRIx64 "", hdl.GetPhysicalAddr()); + DISPLAY_CHK_RETURN_NOT_VALUE((drmFd < 0), DISPLAY_LOGE("can not init drmfd %{public}d", drmFd)); + mDrmFormat = DrmDevice::ConvertToDrmFormat(static_cast(hdl.GetFormat())); + ret = drmPrimeFDToHandle(drmFd, hdl.GetFb(), &mGemHandle); + DISPLAY_CHK_RETURN_NOT_VALUE((ret != 0), DISPLAY_LOGE("can not get handle errno %{public}d", errno)); + + pitches[0] = hdl.GetStride(); + gemHandles[0] = mGemHandle; + offsets[0] = 0; + ret = drmModeAddFB2(drmFd, hdl.GetWight(), hdl.GetHeight(), mDrmFormat, gemHandles, pitches, offsets, &mFdId, 0); + DISPLAY_DEBUGLOG("mGemHandle %{public}d mFdId %{public}d", mGemHandle, mFdId); + DISPLAY_DEBUGLOG("w: %{public}d h: %{public}d mDrmFormat : %{public}d gemHandles: %{public}d pitches: %{public}d " + "offsets: %{public}d", + hdl.GetWight(), hdl.GetHeight(), mDrmFormat, gemHandles[0], pitches[0], offsets[0]); + DISPLAY_CHK_RETURN_NOT_VALUE((ret != 0), DISPLAY_LOGE("can not add fb errno %{public}d", errno)); +} + +DrmGemBuffer::~DrmGemBuffer() +{ + DISPLAY_DEBUGLOG(); + if (mFdId) { + if (drmModeRmFB(mDrmFd, mFdId)) { + DISPLAY_LOGE("can not free fdid %{public}d errno %{public}d", mFdId, errno); + } + } + + if (mGemHandle) { + struct drm_gem_close gemClose = { 0 }; + gemClose.handle = mGemHandle; + if (drmIoctl(mDrmFd, DRM_IOCTL_GEM_CLOSE, &gemClose)) { + DISPLAY_LOGE("can not free gem handle %{public}d errno : %{public}d", mGemHandle, errno); + } + } +} + +bool DrmGemBuffer::IsValid() +{ + DISPLAY_DEBUGLOG(); + return (mGemHandle != INVALID_DRM_ID) && (mFdId != INVALID_DRM_ID); +} + +DrmGemBuffer *HdiDrmLayer::GetGemBuffer() +{ + DISPLAY_DEBUGLOG(); + std::unique_ptr ptr = std::make_unique(DrmDevice::GetDrmFd(), *GetCurrentBuffer()); + mLastBuffer = std::move(mCurrentBuffer); + mCurrentBuffer = std::move(ptr); + return mCurrentBuffer.get(); +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/hdi_drm_layer.h b/hardware/display/src/display_device/hdi_drm_layer.h new file mode 100644 index 0000000000000000000000000000000000000000..43ad767b4ef42a6f8921cb1f71c3e9cbe8c74630 --- /dev/null +++ b/hardware/display/src/display_device/hdi_drm_layer.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_DRM_LAYER_H +#define HDI_DRM_LAYER_H +#include +#include +#include "buffer_handle.h" +#include "display_common.h" +#include "drm_fourcc.h" +#include "hdi_layer.h" +#include "hdi_device_common.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const int INVALID_DRM_ID = 0; +class DrmGemBuffer { +public: + DrmGemBuffer(int drmFd, HdiLayerBuffer &hdl); + virtual ~DrmGemBuffer(); + uint32_t GetFbId() const + { + return mFdId; + } + bool IsValid(); + +private: + void Init(int drmFd, HdiLayerBuffer &hdl); + uint32_t mGemHandle = 0; + uint32_t mFdId = 0; + int mDrmFd = -1; // the fd can not close. the other module will close it. + uint32_t mDrmFormat = DRM_FORMAT_INVALID; +}; + +class HdiDrmLayer : public HdiLayer { +public: + explicit HdiDrmLayer(LayerType type) : HdiLayer(type) {} + ~HdiDrmLayer() override {} + // Return value optimization + DrmGemBuffer *GetGemBuffer(); + +private: + std::unique_ptr mCurrentBuffer; + std::unique_ptr mLastBuffer; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_DRM_LAYER_H diff --git a/hardware/display/src/display_device/hdi_gfx_composition.cpp b/hardware/display/src/display_device/hdi_gfx_composition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b53fef257bb8745b8c7a173ac1bf9bc58bd8e0f --- /dev/null +++ b/hardware/display/src/display_device/hdi_gfx_composition.cpp @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "display_gfx.h" +#include "hdi_gfx_composition.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +int32_t HdiGfxComposition::Init(void) +{ + DISPLAY_DEBUGLOG(); + int32_t ret = GfxModuleInit(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS) || (mGfxFuncs == nullptr), DISPLAY_FAILURE, + DISPLAY_LOGE("GfxModuleInit failed")); + ret = mGfxFuncs->InitGfx(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("gfx init failed")); + return DISPLAY_SUCCESS; +} + +int32_t HdiGfxComposition::GfxModuleInit(void) +{ + DISPLAY_DEBUGLOG(); + mGfxModule = dlopen("libdisplay_gfx.z.so", RTLD_NOW | RTLD_NOLOAD); + if (mGfxModule != nullptr) { + DISPLAY_LOGI("Module '%{public}s' already loaded", "libdisplay_gfx.z.so"); + } else { + DISPLAY_LOGI("Loading module '%{public}s'", "libdisplay_gfx.z.so"); + mGfxModule = dlopen("libdisplay_gfx.z.so", RTLD_NOW); + if (mGfxModule == nullptr) { + DISPLAY_LOGE("Failed to load module: %{public}s", dlerror()); + return DISPLAY_FAILURE; + } + } + + using InitFunc = int32_t (*)(GfxFuncs **funcs); + InitFunc func = reinterpret_cast(dlsym(mGfxModule, "GfxInitialize")); + if (func == nullptr) { + DISPLAY_LOGE("Failed to lookup %{public}s function: %s", "GfxInitialize", dlerror()); + dlclose(mGfxModule); + return DISPLAY_FAILURE; + } + return func(&mGfxFuncs); +} + +int32_t HdiGfxComposition::GfxModuleDeinit(void) +{ + DISPLAY_DEBUGLOG(); + int32_t ret = DISPLAY_SUCCESS; + if (mGfxModule == nullptr) { + using DeinitFunc = int32_t (*)(GfxFuncs *funcs); + DeinitFunc func = reinterpret_cast(dlsym(mGfxModule, "GfxUninitialize")); + if (func == nullptr) { + DISPLAY_LOGE("Failed to lookup %{public}s function: %s", "GfxUninitialize", dlerror()); + } else { + ret = func(mGfxFuncs); + } + dlclose(mGfxModule); + } + return ret; +} + +bool HdiGfxComposition::CanHandle(HdiLayer &hdiLayer) +{ + DISPLAY_DEBUGLOG(); + (void)hdiLayer; + return true; +} + +int32_t HdiGfxComposition::SetLayers(std::vector &layers, HdiLayer &clientLayer) +{ + DISPLAY_DEBUGLOG("layers size %{public}zd", layers.size()); + mClientLayer = &clientLayer; + mCompLayers.clear(); + for (auto &layer : layers) { + if (CanHandle(*layer)) { + if ((layer->GetCompositionType() != COMPOSITION_VIDEO) && + (layer->GetCompositionType() != COMPOSITION_CURSOR)) { + layer->SetDeviceSelect(COMPOSITION_DEVICE); + } else { + layer->SetDeviceSelect(layer->GetCompositionType()); + } + mCompLayers.push_back(layer); + } + } + DISPLAY_DEBUGLOG("composer layers size %{public}zd", mCompLayers.size()); + return DISPLAY_SUCCESS; +} + +void HdiGfxComposition::InitGfxSurface(ISurface &iSurface, HdiLayerBuffer &buffer) +{ + iSurface.width = buffer.GetWight(); + iSurface.height = buffer.GetHeight(); + iSurface.phyAddr = buffer.GetFb(); // buffer.GetPhysicalAddr(); + iSurface.enColorFmt = (PixelFormat)buffer.GetFormat(); + iSurface.stride = buffer.GetStride(); + iSurface.bAlphaExt1555 = true; + iSurface.bAlphaMax255 = true; + iSurface.alpha0 = 0XFF; + iSurface.alpha1 = 0XFF; + DISPLAY_DEBUGLOG("iSurface fd %{public}d w:%{public}d h:%{public}d addr:0x%{public}" \ + PRIx64 " fmt:%{public}d stride:%{public}d", + buffer.GetFb(), iSurface.width, iSurface.height, + buffer.GetPhysicalAddr(), iSurface.enColorFmt, iSurface.stride); +} + +// now not handle the alpha of layer +int32_t HdiGfxComposition::BlitLayer(HdiLayer &src, HdiLayer &dst) +{ + ISurface srcSurface = { 0 }; + ISurface dstSurface = { 0 }; + GfxOpt opt = { 0 }; + DISPLAY_DEBUGLOG(); + HdiLayerBuffer *srcBuffer = src.GetCurrentBuffer(); + DISPLAY_CHK_RETURN((srcBuffer == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("the srcbuffer is null")); + DISPLAY_DEBUGLOG("init the src iSurface"); + InitGfxSurface(srcSurface, *srcBuffer); + + HdiLayerBuffer *dstBuffer = dst.GetCurrentBuffer(); + DISPLAY_CHK_RETURN((dstBuffer == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not get client layer buffer")); + DISPLAY_DEBUGLOG("init the dst iSurface"); + InitGfxSurface(dstSurface, *dstBuffer); + + opt.blendType = src.GetLayerBlenType(); + DISPLAY_DEBUGLOG("blendType %{public}d", opt.blendType); + opt.enPixelAlpha = true; + opt.enableScale = true; + + if (src.GetAlpha().enGlobalAlpha) { // is alpha is 0xff we not set it + opt.enGlobalAlpha = true; + srcSurface.alpha0 = src.GetAlpha().gAlpha; + DISPLAY_DEBUGLOG("src alpha %{public}x", src.GetAlpha().gAlpha); + } + opt.rotateType = src.GetTransFormType(); + DISPLAY_DEBUGLOG(" the roate type is %{public}d", opt.rotateType); + IRect crop = src.GetLayerCrop(); + IRect displayRect = src.GetLayerDisplayRect(); + DISPLAY_DEBUGLOG("crop x: %{public}d y : %{public}d w : %{public}d h: %{public}d", crop.x, crop.y, crop.w, crop.h); + DISPLAY_DEBUGLOG("displayRect x: %{public}d y : %{public}d w : %{public}d h : %{public}d", + displayRect.x, displayRect.y, displayRect.w, displayRect.h); + DISPLAY_CHK_RETURN(mGfxFuncs == nullptr, DISPLAY_FAILURE, DISPLAY_LOGE("Blit: mGfxFuncs is null")); + return mGfxFuncs->Blit(&srcSurface, &crop, &dstSurface, &displayRect, &opt); +} + +int32_t HdiGfxComposition::ClearRect(HdiLayer &src, HdiLayer &dst) +{ + ISurface dstSurface = { 0 }; + GfxOpt opt = { 0 }; + DISPLAY_DEBUGLOG(); + HdiLayerBuffer *dstBuffer = dst.GetCurrentBuffer(); + DISPLAY_CHK_RETURN((dstBuffer == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not get client layer buffer")); + InitGfxSurface(dstSurface, *dstBuffer); + IRect rect = src.GetLayerDisplayRect(); + DISPLAY_CHK_RETURN(mGfxFuncs == nullptr, DISPLAY_FAILURE, DISPLAY_LOGE("Rect: mGfxFuncs is null")); + return mGfxFuncs->FillRect(&dstSurface, &rect, 0, &opt); +} + +int32_t HdiGfxComposition::Apply(bool modeSet) +{ + int32_t ret; + DISPLAY_DEBUGLOG("composer layers size %{public}zd", mCompLayers.size()); + for (uint32_t i = 0; i < mCompLayers.size(); i++) { + HdiLayer *layer = mCompLayers[i]; + CompositionType compType = layer->GetCompositionType(); + switch (compType) { + case COMPOSITION_VIDEO: + ret = ClearRect(*layer, *mClientLayer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, + DISPLAY_LOGE("clear layer %{public}d failed", i)); + break; + case COMPOSITION_DEVICE: + ret = BlitLayer(*layer, *mClientLayer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, + DISPLAY_LOGE("blit layer %{public}d failed ", i)); + break; + default: + DISPLAY_LOGE("the gfx composition can not surpport the type %{public}d", compType); + break; + } + } + return DISPLAY_SUCCESS; +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/hdi_gfx_composition.h b/hardware/display/src/display_device/hdi_gfx_composition.h new file mode 100644 index 0000000000000000000000000000000000000000..d9654461d39a806aa9952be86d8a4ac327c90d60 --- /dev/null +++ b/hardware/display/src/display_device/hdi_gfx_composition.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_GFX_COMPOSITION_H +#define HDI_GFX_COMPOSITION_H +#include "display_gfx.h" +#include "hdi_composer.h" +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiGfxComposition : public HdiComposition { +public: + int32_t Init(void) override; + int32_t SetLayers(std::vector &layers, HdiLayer &clientLayer) override; + int32_t Apply(bool modeSet) override; + ~HdiGfxComposition() override + { + (void)GfxModuleDeinit(); + } + +private: + bool CanHandle(HdiLayer &hdiLayer); + void InitGfxSurface(ISurface &iSurface, HdiLayerBuffer &buffer); + int32_t BlitLayer(HdiLayer &src, HdiLayer &dst); + int32_t ClearRect(HdiLayer &src, HdiLayer &dst); + int32_t GfxModuleInit(void); + int32_t GfxModuleDeinit(void); + void *mGfxModule = nullptr; + GfxFuncs *mGfxFuncs = nullptr; + HdiLayer *mClientLayer; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_GFX_COMPOSITION_H diff --git a/hardware/display/src/display_device/hdi_layer.cpp b/hardware/display/src/display_device/hdi_layer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20808a91be0de4c6061b362b46dea65cd104b6ad --- /dev/null +++ b/hardware/display/src/display_device/hdi_layer.cpp @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_layer.h" +#include +#include + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +uint32_t HdiLayer::mIdleId = 0; +std::unordered_set HdiLayer::mIdSets; + +HdiLayerBuffer::HdiLayerBuffer(const BufferHandle &hdl) + : mPhyAddr(hdl.phyAddr), mHeight(hdl.height), mWidth(hdl.width), mStride(hdl.stride), mFormat(hdl.format) +{ + DISPLAY_DEBUGLOG(); + mFd = dup(hdl.fd); + mHandle = hdl; + if (mFd < 0) { + DISPLAY_LOGE("the fd : %{public}d dup failed errno %{public}d", hdl.fd, errno); + } +} + +HdiLayerBuffer::~HdiLayerBuffer() +{ + DISPLAY_DEBUGLOG(); + if (mFd >= 0) { + close(mFd); + } +} + +HdiLayerBuffer &HdiLayerBuffer::operator = (const BufferHandle &right) +{ + DISPLAY_DEBUGLOG(); + if (mFd >= 0) { + close(mFd); + } + mFd = dup(right.fd); + mPhyAddr = right.phyAddr; + mWidth = right.width; + mHeight = right.height; + mStride = right.stride; + mFormat = right.format; + return *this; +} + +uint32_t HdiLayer::GetIdleId() +{ + const uint32_t oldIdleId = mIdleId; + uint32_t id = INVALIDE_LAYER_ID; + // ensure the mIdleId not INVALIDE_LAYER_ID + mIdleId = mIdleId % INVALIDE_LAYER_ID; + do { + auto iter = mIdSets.find(mIdleId); + if (iter == mIdSets.end()) { + id = mIdleId; + break; + } + mIdleId = (mIdleId + 1) % INVALIDE_LAYER_ID; + } while (oldIdleId != mIdleId); + mIdSets.emplace(id); + mIdleId++; + DISPLAY_DEBUGLOG("id %{public}d mIdleId %{public}d", id, mIdleId); + return id; +} + +int32_t HdiLayer::Init() +{ + DISPLAY_DEBUGLOG(); + uint32_t id = GetIdleId(); + DISPLAY_CHK_RETURN((id == INVALIDE_LAYER_ID), DISPLAY_FAILURE, DISPLAY_LOGE("have no id to used")); + mId = id; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerSize(IRect *rect) +{ + DISPLAY_CHK_RETURN((rect == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in rect is nullptr")); + DISPLAY_DEBUGLOG(" displayRect x: %{public}d y : %{public}d w : %{public}d h : %{public}d", rect->x, rect->y, + rect->w, rect->h); + mDisplayRect = *rect; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerCrop(IRect *rect) +{ + DISPLAY_CHK_RETURN((rect == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in rect is nullptr")); + DISPLAY_DEBUGLOG("id : %{public}d crop x: %{public}d y : %{public}d w : %{public}d h : %{public}d", mId, + rect->x, rect->y, rect->w, rect->h); + mCrop = *rect; + return DISPLAY_SUCCESS; +} + +void HdiLayer::SetLayerZorder(uint32_t zorder) +{ + DISPLAY_DEBUGLOG("id : %{public}d zorder : %{public}d ", mId, zorder); + mZorder = zorder; +} + +int32_t HdiLayer::SetLayerPreMulti(bool preMul) +{ + DISPLAY_DEBUGLOG(); + mPreMul = preMul; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerAlpha(LayerAlpha *alpha) +{ + DISPLAY_CHK_RETURN((alpha == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in alpha is nullptr")); + DISPLAY_DEBUGLOG("enable alpha %{public}d galpha 0x%{public}x", alpha->enGlobalAlpha, alpha->gAlpha); + mAlpha = *alpha; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetTransformMode(TransformType type) +{ + DISPLAY_DEBUGLOG("TransformType %{public}d", type); + mTransformType = type; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerDirtyRegion(IRect *region) +{ + DISPLAY_CHK_RETURN((region == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("the in rect is null")); + DISPLAY_DEBUGLOG("id : %{public}d DirtyRegion x: %{public}d y : %{public}d w : %{public}d h : %{public}d", mId, + region->x, region->y, region->w, region->h); + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerVisibleRegion(uint32_t num, IRect *rect) +{ + DISPLAY_DEBUGLOG("id : %{public}d DirtyRegion x: %{public}d y : %{public}d w : %{public}d h : %{public}d", mId, rect->x, + rect->y, rect->w, rect->h); + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerBuffer(const BufferHandle *buffer, int32_t fence) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((buffer == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("buffer is nullptr")); + std::unique_ptr layerbuffer = std::make_unique(*buffer); + mHdiBuffer = std::move(layerbuffer); + mAcquireFence = fence; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerCompositionType(CompositionType type) +{ + DISPLAY_DEBUGLOG("CompositionType type %{public}d", type); + mCompositionType = type; + return DISPLAY_SUCCESS; +} + +int32_t HdiLayer::SetLayerBlendType(BlendType type) +{ + DISPLAY_DEBUGLOG("BlendType type %{public}d", type); + mBlendType = type; + return DISPLAY_SUCCESS; +} + +void HdiLayer::SetPixel(const BufferHandle &handle, int x, int y, uint32_t color) +{ + const int32_t pixelBytes = 4; + DISPLAY_CHK_RETURN_NOT_VALUE((handle.format <= 0), + DISPLAY_LOGE("CheckPixel do not support format %{public}d", handle.format)); + DISPLAY_CHK_RETURN_NOT_VALUE((handle.virAddr == nullptr), DISPLAY_LOGE("CheckPixel viraddr is null must map it")); + DISPLAY_CHK_RETURN_NOT_VALUE((x < 0 || x >= handle.width), + DISPLAY_LOGE("CheckPixel invalid parameter x:%{public}d width:%{public}d", x, handle.width)); + DISPLAY_CHK_RETURN_NOT_VALUE((y < 0 || y >= handle.height), + DISPLAY_LOGE("CheckPixel invalid parameter y:%{public}d height:%{public}d", y, handle.height)); + int32_t position = y * handle.width + x; + if ((position * pixelBytes) > handle.size) { + DISPLAY_LOGE("the pixel postion outside\n"); + } + uint32_t *pixel = reinterpret_cast(handle.virAddr) + position; + *pixel = color; +} + +void HdiLayer::ClearColor(uint32_t color) +{ + DISPLAY_DEBUGLOG(); + BufferHandle &handle = mHdiBuffer->mHandle; + for (int32_t x = 0; x < handle.width; x++) { + for (int32_t y = 0; y < handle.height; y++) { + SetPixel(handle, x, y, color); + } + } +} +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY diff --git a/hardware/display/src/display_device/hdi_layer.h b/hardware/display/src/display_device/hdi_layer.h new file mode 100644 index 0000000000000000000000000000000000000000..88803ce8e6086713bd9a33162bcdab8481f9f2ae --- /dev/null +++ b/hardware/display/src/display_device/hdi_layer.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_LAYER_H +#define HDI_LAYER_H +#include +#include +#include "buffer_handle.h" +#include "display_common.h" +#include "hdi_device_common.h" +#include "hdi_shared_fd.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +const uint32_t INVALIDE_LAYER_ID = 0xffffffff; +struct HdiLayerBuffer { +public: + explicit HdiLayerBuffer(const BufferHandle &hdl); + virtual ~HdiLayerBuffer(); + HdiLayerBuffer &operator = (const BufferHandle &right); + uint64_t GetPhysicalAddr() const + { + return mPhyAddr; + } + int32_t GetHeight() const + { + return mHeight; + } + int32_t GetWight() const + { + return mWidth; + } + int32_t GetStride() const + { + return mStride; + } + int32_t GetFormat() const + { + return mFormat; + } + int GetFb() const + { + return mFd; + } + BufferHandle mHandle; + +private: + uint64_t mPhyAddr = 0; + int32_t mHeight = 0; + int32_t mWidth = 0; + int32_t mStride = 0; + int32_t mFormat = 0; + int mFd = -1; +}; + +class HdiLayer { +public: + explicit HdiLayer(LayerType type) : mType(type) {} + int32_t Init(); + uint32_t GetId() const + { + return mId; + } + uint32_t GetZorder() const + { + return mZorder; + } + const IRect &GetLayerDisplayRect() const + { + return mDisplayRect; + } + const IRect &GetLayerCrop() const + { + return mCrop; + } + bool GetLayerPreMulti() const + { + return mPreMul; + } + const LayerAlpha &GetAlpha() const + { + return mAlpha; + } + LayerType GetType() const + { + return mType; + } + TransformType GetTransFormType() const + { + return mTransformType; + } + BlendType GetLayerBlenType() const + { + return mBlendType; + } + CompositionType GetCompositionType() const + { + return mCompositionType; + } + void SetDeviceSelect(CompositionType type) + { + DISPLAY_DEBUGLOG("%{public}d", type); + mDeviceSelect = type; + } + CompositionType GetDeviceSelect() const + { + return mDeviceSelect; + } + + int GetAcquireFenceFd() + { + return mAcquireFence.GetFd(); + } + int GetReleaseFenceFd() + { + return mReleaseFence.GetFd(); + } + void SetReleaseFence(int fd) + { + mReleaseFence = fd; + }; + void ClearColor(uint32_t color); + + void SetPixel(const BufferHandle &handle, int x, int y, uint32_t color); + + virtual int32_t SetLayerSize(IRect *rect); + virtual int32_t SetLayerCrop(IRect *rect); + virtual void SetLayerZorder(uint32_t zorder); + virtual int32_t SetLayerPreMulti(bool preMul); + virtual int32_t SetLayerAlpha(LayerAlpha *alpha); + virtual int32_t SetTransformMode(TransformType type); + virtual int32_t SetLayerDirtyRegion(IRect *region); + virtual int32_t SetLayerVisibleRegion(uint32_t num, IRect *rect); + virtual int32_t SetLayerBuffer(const BufferHandle *buffer, int32_t fence); + virtual int32_t SetLayerCompositionType(CompositionType type); + virtual int32_t SetLayerBlendType(BlendType type); + virtual HdiLayerBuffer *GetCurrentBuffer() + { + return mHdiBuffer.get(); + } + virtual ~HdiLayer() {} + +private: + static uint32_t GetIdleId(); + static uint32_t mIdleId; + static std::unordered_set mIdSets; + + uint32_t mId = 0; + HdiFd mAcquireFence; + HdiFd mReleaseFence; + LayerType mType; + + IRect mDisplayRect; + IRect mCrop; + uint32_t mZorder = -1; + bool mPreMul = false; + LayerAlpha mAlpha; + TransformType mTransformType = ROTATE_BUTT; + CompositionType mCompositionType = COMPOSITION_CLIENT; + CompositionType mDeviceSelect = COMPOSITION_CLIENT; + BlendType mBlendType; + std::unique_ptr mHdiBuffer; +}; + +struct SortLayersByZ { + bool operator () (const HdiLayer *lhs, const HdiLayer *rhs) const + { + if (lhs == nullptr || rhs == nullptr) { + return (lhs == nullptr) && (rhs == nullptr); + } + return lhs->GetZorder() < rhs->GetZorder(); + } +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_LAYER_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_netlink_monitor.cpp b/hardware/display/src/display_device/hdi_netlink_monitor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..003275d3928543ba6ec6d2158e86fdea091b2bda --- /dev/null +++ b/hardware/display/src/display_device/hdi_netlink_monitor.cpp @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hdi_netlink_monitor.h" +#include +#include +#include +#include +#include +#include +#include "display_common.h" +#include "display_device.h" +#include "display_layer.h" +#include "hdi_session.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +HdiNetLinkMonitor::HdiNetLinkMonitor() +{ + DISPLAY_DEBUGLOG(); +} + +int HdiNetLinkMonitor::Init() +{ + DISPLAY_DEBUGLOG(); + mThread = std::make_unique(std::bind(&HdiNetLinkMonitor::MonitorThread, this)); + mThread->detach(); + mRunning = true; + return DISPLAY_SUCCESS; +} + +HdiNetLinkMonitor::~HdiNetLinkMonitor() +{ + DISPLAY_DEBUGLOG(); + if (mScoketFd >= 0) { + close(mScoketFd); + } +} + +static int ThreadInit() +{ + int ret; + int fd = -1; + const int32_t bufferSize = 1024; + struct sockaddr_nl snl; + + bzero(&snl, sizeof(struct sockaddr_nl)); + snl.nl_family = AF_NETLINK; + snl.nl_pid = getpid(); + snl.nl_groups = 1; + fd = socket(PF_NETLINK, SOCK_DGRAM, NETLINK_KOBJECT_UEVENT); + DISPLAY_CHK_RETURN(fd < 0, DISPLAY_FAILURE, DISPLAY_LOGE("socket fail")); + ret = setsockopt(fd, SOL_SOCKET, SO_RCVBUF, &bufferSize, sizeof(bufferSize)); + if (ret == -1) { + DISPLAY_LOGE("setsockopt fail"); + close(fd); + return DISPLAY_FAILURE; + } + ret = bind(fd, (struct sockaddr *)&snl, sizeof(struct sockaddr_nl)); + if (ret < 0) { + DISPLAY_LOGE("bind fail"); + close(fd); + return DISPLAY_FAILURE; + } + return fd; +} + +static void ParseUeventMessage(const char *buf, uint32_t len) +{ + uint32_t num; + + for (num = 0; num < len;) { + const char *event = buf + num; + if (strcmp(event, "STATE=HDMI=0") == 0) { + HdiSession::GetInstance().HandleHotplug(false); + break; + } else if (strcmp(event, "STATE=HDMI=1") == 0) { + HdiSession::GetInstance().HandleHotplug(true); + break; + } + num += strlen(event) + 1; + } +} + +void HdiNetLinkMonitor::MonitorThread() +{ + constexpr int BUFFER_SIZE = 2048; /* buffer for the variables */ + int len; + int fd = -1; + + fd = ThreadInit(); + DISPLAY_CHK_RETURN_NOT_VALUE(fd < 0, DISPLAY_LOGE("socket fail")); + mScoketFd = fd; + while (mRunning) { + char buf[BUFFER_SIZE] = { 0 }; + len = read(fd, &buf, sizeof(buf)); + if (len < 0) { + DISPLAY_LOGE("read uevent message fail"); + break; + } + ParseUeventMessage(buf, len); + } +} +} // DISPLAY +} // HDI +} // OHOS diff --git a/hardware/display/src/display_device/hdi_netlink_monitor.h b/hardware/display/src/display_device/hdi_netlink_monitor.h new file mode 100644 index 0000000000000000000000000000000000000000..12b83182b9c9f90b31e7a41b8ef5faec6042928c --- /dev/null +++ b/hardware/display/src/display_device/hdi_netlink_monitor.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_NETLINK_NONITOR_H +#define HDI_NETLINK_NONITOR_H +#include + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiNetLinkMonitor { +public: + HdiNetLinkMonitor(); + int Init(); + virtual ~HdiNetLinkMonitor(); + +private: + void MonitorThread(); + volatile bool mRunning = false; + int mScoketFd = -1; + std::unique_ptr mThread; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_NETLINK_NONITOR_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_session.cpp b/hardware/display/src/display_device/hdi_session.cpp new file mode 100644 index 0000000000000000000000000000000000000000..352d27c7f31ddf3b3b7ac32352826df4e638448f --- /dev/null +++ b/hardware/display/src/display_device/hdi_session.cpp @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "display_common.h" +#include "display_device.h" +#include "display_layer.h" +#include "hdi_netlink_monitor.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +HdiSession &HdiSession::GetInstance() +{ + static HdiSession instance; + static std::once_flag once; + std::call_once(once, [&]() { instance.Init(); }); + return instance; +} + +void HdiSession::Init() +{ + DISPLAY_DEBUGLOG(); + mHdiDevices = HdiDeviceInterface::DiscoveryDevice(); + DISPLAY_DEBUGLOG("devices size %{public}zd", mHdiDevices.size()); + mHdiDisplays.clear(); + for (auto device : mHdiDevices) { + auto displays = device->DiscoveryDisplay(); + /* Register the connectors instead of display device. + * There are several connectors in one display device + * in rockchip platform. + */ + for (auto display : displays) { + mHdiDisplays[display.first] = display.second; + } + } + std::shared_ptr mNetLinkMonitor = std::make_shared(); + mNetLinkMonitor->Init(); +} + +void HdiSession::HandleHotplug(bool plugIn) +{ + for (auto device : mHdiDevices) { + for (auto displayMap : mHdiDisplays) { + auto display = displayMap.second; + auto isSuccess = device->HandleHotplug(display->GetId(), plugIn); + if (isSuccess == true) { + DoHotPlugCallback(display->GetId(), plugIn); + } + } + } +} + +int32_t HdiSession::RegHotPlugCallback(HotPlugCallback callback, void *data) +{ + DISPLAY_CHK_RETURN((callback == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("the callback is nullptr")); + mHotPlugCallBacks.emplace(callback, data); + for (auto displayMap : mHdiDisplays) { + auto display = displayMap.second; + if (display->IsConnected()) { + DoHotPlugCallback(display->GetId(), true); + } + } + return DISPLAY_SUCCESS; +} + +void HdiSession::DoHotPlugCallback(uint32_t devId, bool connect) +{ + DISPLAY_DEBUGLOG(); + for (const auto &callback : mHotPlugCallBacks) { + callback.first(devId, connect, callback.second); + } +} +} // OHOS +} // HDI +} // DISPLAY + +using namespace OHOS::HDI::DISPLAY; +static int32_t RegHotPlugCallback(HotPlugCallback callback, void *data) +{ + DISPLAY_DEBUGLOG(); + HdiSession::GetInstance().RegHotPlugCallback(callback, data); + return DISPLAY_SUCCESS; +} + +static int32_t GetDisplayCapability(uint32_t devId, DisplayCapability *info) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN(info == nullptr, DISPLAY_NULL_PTR, DISPLAY_LOGE("info is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayCapability, info); +} + +static int32_t GetDisplaySupportedModes(uint32_t devId, uint32_t *num, DisplayModeInfo *modes) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN(num == nullptr, DISPLAY_NULL_PTR, DISPLAY_LOGE("num is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplaySupportedModes, num, modes); +} + +static int32_t GetDisplayMode(uint32_t devId, uint32_t *mode) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((mode == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("mode is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayMode, mode); +} + +static int32_t SetDisplayMode(uint32_t devId, uint32_t mode) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetDisplayMode, mode); +} + +static int32_t GetDisplayPowerStatus(uint32_t devId, DispPowerStatus *status) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((status == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("status is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayPowerStatus, status); +} + +static int32_t SetDisplayPowerStatus(uint32_t devId, DispPowerStatus status) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetDisplayPowerStatus, status); +} + +static int32_t GetDisplayBacklight(uint32_t devId, uint32_t *value) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((value == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("value is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayBacklight, value); +} + +static int32_t SetDisplayBacklight(uint32_t devId, uint32_t value) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetDisplayBacklight, value); +} + +static int32_t GetDisplayProperty(uint32_t devId, uint32_t id, uint64_t *value) +{ + DISPLAY_DEBUGLOG(); + (void)id; + DISPLAY_CHK_RETURN((value == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("value is nullptr")); + return DISPLAY_NOT_SUPPORT; +} + +static int32_t SetDisplayProperty(uint32_t devId, uint32_t id, uint64_t value) +{ + DISPLAY_DEBUGLOG(); + (void)id; + return DISPLAY_NOT_SUPPORT; +} + +static int32_t PrepareDisplayLayers(uint32_t devId, bool *needFlushFb) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((needFlushFb == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("needFlushFb is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::PrepareDisplayLayers, needFlushFb); +} + +static int32_t GetDisplayCompChange(uint32_t devId, uint32_t *num, uint32_t *layers, int32_t *type) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((num == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("num is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayCompChange, num, layers, type); +} + +static int32_t SetDisplayClientCrop(uint32_t devId, IRect *rect) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + return DISPLAY_NOT_SUPPORT; +} + +static int32_t SetDisplayClientDestRect(uint32_t devId, IRect *rect) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + return DISPLAY_NOT_SUPPORT; +} + +static int32_t SetDisplayClientBuffer(uint32_t devId, const BufferHandle *buffer, int32_t fence) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetDisplayClientBuffer, buffer, fence); +} + +static int32_t SetDisplayClientDamage(uint32_t devId, uint32_t num, IRect *rect) +{ + DISPLAY_DEBUGLOG(); + (void)num; + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + return DISPLAY_NOT_SUPPORT; +} + +static int32_t SetDisplayVsyncEnabled(uint32_t devId, bool enabled) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetDisplayVsyncEnabled, enabled); +} + +static int32_t RegDisplayVBlankCallback(uint32_t devId, VBlankCallback callback, void *data) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::RegDisplayVBlankCallback, callback, data); +} + +static int32_t GetDisplayReleaseFence(uint32_t devId, uint32_t *num, uint32_t *layers, int32_t *fences) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::GetDisplayReleaseFence, num, layers, + fences); +} + +static int32_t Commit(uint32_t devId, int32_t *fence) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((fence == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("fence is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::Commit, fence); +} + +static int32_t CreateVirtualDisplay(uint32_t width, uint32_t height, int32_t *format, uint32_t *devId) +{ + DISPLAY_DEBUGLOG(); + return DISPLAY_NOT_SUPPORT; +} +static int32_t DestroyVirtualDisplay(uint32_t devId) +{ + DISPLAY_DEBUGLOG(); + return DISPLAY_NOT_SUPPORT; +} +static int32_t SetVirtualDisplayBuffer(uint32_t devId, BufferHandle *buffer, int32_t releaseFence) +{ + DISPLAY_DEBUGLOG(); + return DISPLAY_NOT_SUPPORT; +} + + +// Layer function +static int32_t CreateLayer(uint32_t devId, const LayerInfo *layerInfo, uint32_t *layerId) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((layerId == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("layerId is nullptr")); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::CreateLayer, layerInfo, layerId); +} + +static int32_t CloseLayer(uint32_t devId, uint32_t layerId) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::CloseLayer, layerId); +} + +static int32_t SetLayerSize(uint32_t devId, uint32_t layerId, IRect *rect) +{ + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerSize, rect); +} + +static int32_t SetLayerCrop(uint32_t devId, uint32_t layerId, IRect *rect) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerCrop, rect); +} + +static int32_t SetLayerZorder(uint32_t devId, uint32_t layerId, uint32_t zorder) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallDisplayFunction(devId, &HdiDisplay::SetLayerZorder, layerId, zorder); +} + +static int32_t SetLayerPreMulti(uint32_t devId, uint32_t layerId, bool preMul) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerPreMulti, preMul); +} + +static int32_t SetLayerAlpha(uint32_t devId, uint32_t layerId, LayerAlpha *alpha) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((alpha == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("alpha is nullptr")); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerAlpha, alpha); +} + +static int32_t SetTransformMode(uint32_t devId, uint32_t layerId, TransformType type) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetTransformMode, type); +} + +static int32_t SetLayerDirtyRegion(uint32_t devId, uint32_t layerId, IRect *region) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((region == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("region is nullptr")); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerDirtyRegion, region); +} + +static int32_t SetLayerVisibleRegion(uint32_t devId, uint32_t layerId, uint32_t num, IRect *rect) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((rect == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("rect is nullptr")); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerVisibleRegion, num, rect); +} + +static int32_t SetLayerBuffer(uint32_t devId, uint32_t layerId, const BufferHandle *buffer, int32_t fence) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerBuffer, buffer, fence); +} + +static int32_t SetLayerCompositionType(uint32_t devId, uint32_t layerId, CompositionType type) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerCompositionType, type); +} + +static int32_t SetLayerBlendType(uint32_t devId, uint32_t layerId, BlendType type) +{ + DISPLAY_DEBUGLOG(); + return HdiSession::GetInstance().CallLayerFunction(devId, layerId, &HdiLayer::SetLayerBlendType, type); +} + + +extern "C" { +int32_t DeviceInitialize(DeviceFuncs **funcs) +{ + DISPLAY_CHK_RETURN((funcs == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in funcs is null")); + DeviceFuncs *dFuncs = (DeviceFuncs *)calloc(1, sizeof(DeviceFuncs)); + DISPLAY_CHK_RETURN((dFuncs == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not calloc")); + + dFuncs->RegHotPlugCallback = RegHotPlugCallback; + dFuncs->GetDisplayCapability = GetDisplayCapability; + dFuncs->GetDisplaySupportedModes = GetDisplaySupportedModes; + dFuncs->GetDisplayMode = GetDisplayMode; + dFuncs->SetDisplayMode = SetDisplayMode; + dFuncs->GetDisplayPowerStatus = GetDisplayPowerStatus; + dFuncs->SetDisplayPowerStatus = SetDisplayPowerStatus; + dFuncs->PrepareDisplayLayers = PrepareDisplayLayers; + dFuncs->GetDisplayBacklight = GetDisplayBacklight; + dFuncs->SetDisplayBacklight = SetDisplayBacklight; + dFuncs->GetDisplayProperty = GetDisplayProperty; + dFuncs->GetDisplayCompChange = GetDisplayCompChange; + dFuncs->SetDisplayClientCrop = SetDisplayClientCrop; + dFuncs->SetDisplayClientDestRect = SetDisplayClientDestRect; + dFuncs->SetDisplayClientBuffer = SetDisplayClientBuffer; + dFuncs->SetDisplayClientDamage = SetDisplayClientDamage; + dFuncs->SetDisplayVsyncEnabled = SetDisplayVsyncEnabled; + dFuncs->RegDisplayVBlankCallback = RegDisplayVBlankCallback; + dFuncs->GetDisplayReleaseFence = GetDisplayReleaseFence; + dFuncs->CreateVirtualDisplay = CreateVirtualDisplay; + dFuncs->DestroyVirtualDisplay = DestroyVirtualDisplay; + dFuncs->SetVirtualDisplayBuffer = SetVirtualDisplayBuffer; + dFuncs->SetDisplayProperty = SetDisplayProperty; + dFuncs->Commit = Commit; + *funcs = dFuncs; + DISPLAY_DEBUGLOG("%{public}s: device initialize success", __func__); + HdiSession::GetInstance(); + return DISPLAY_SUCCESS; +} + +int32_t DeviceUninitialize(DeviceFuncs *funcs) +{ + DISPLAY_CHK_RETURN((funcs == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("in funcs is null")); + free(funcs); + return DISPLAY_SUCCESS; +} + + +int32_t LayerInitialize(LayerFuncs **funcs) +{ + DISPLAY_CHK_RETURN((funcs == nullptr), DISPLAY_NULL_PTR, DISPLAY_LOGE("the in funcs is nullptr")); + LayerFuncs *lFuncs = (LayerFuncs *)calloc(1, sizeof(LayerFuncs)); + DISPLAY_CHK_RETURN((lFuncs == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("can not calloc errno: %{public}d", errno)); + lFuncs->SetLayerAlpha = SetLayerAlpha; + lFuncs->CreateLayer = CreateLayer; + lFuncs->CloseLayer = CloseLayer; + lFuncs->SetLayerSize = SetLayerSize; + lFuncs->SetLayerCrop = SetLayerCrop; + lFuncs->SetLayerZorder = SetLayerZorder; + lFuncs->SetLayerPreMulti = SetLayerPreMulti; + lFuncs->SetTransformMode = SetTransformMode; + lFuncs->SetLayerDirtyRegion = SetLayerDirtyRegion; + lFuncs->SetLayerVisibleRegion = SetLayerVisibleRegion; + lFuncs->SetLayerBuffer = SetLayerBuffer; + lFuncs->SetLayerCompositionType = SetLayerCompositionType; + lFuncs->SetLayerBlendType = SetLayerBlendType; + + *funcs = lFuncs; + DISPLAY_DEBUGLOG("%{public}s: layer initialize success", __func__); + return DISPLAY_SUCCESS; +} + +int32_t LayerUninitialize(LayerFuncs *funcs) +{ + DISPLAY_CHK_RETURN((funcs == nullptr), DISPLAY_FAILURE, DISPLAY_LOGE("the funcs is nullptr")); + free(funcs); + DISPLAY_DEBUGLOG("%{public}s: layer uninitialize success", __func__); + return DISPLAY_SUCCESS; +} +} diff --git a/hardware/display/src/display_device/hdi_session.h b/hardware/display/src/display_device/hdi_session.h new file mode 100644 index 0000000000000000000000000000000000000000..eb040db883243d5796ca99f07d084c51ab56cdd2 --- /dev/null +++ b/hardware/display/src/display_device/hdi_session.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_SESSION_H +#define HDI_SESSION_H +#include +#include +#include +#include "display_device.h" +#include "hdi_device_interface.h" +#include "hdi_display.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiSession { +public: + void Init(); + static HdiSession &GetInstance(); + + template + int32_t CallDisplayFunction(uint32_t devId, int32_t (HdiDisplay::*member)(Args...), Args... args) + { + DISPLAY_DEBUGLOG("device Id : %{public}d", devId); + DISPLAY_CHK_RETURN((devId == INVALIDE_DISPLAY_ID), DISPLAY_FAILURE, DISPLAY_LOGE("invalide device id")); + auto iter = mHdiDisplays.find(devId); + DISPLAY_CHK_RETURN((iter == mHdiDisplays.end()), DISPLAY_FAILURE, + DISPLAY_LOGE("can not find display %{public}d", devId)); + auto display = iter->second.get(); + return (display->*member)(std::forward(args)...); + } + + template + int32_t CallLayerFunction(uint32_t devId, uint32_t layerId, int32_t (HdiLayer::*member)(Args...), Args... args) + { + DISPLAY_DEBUGLOG("device Id : %{public}d", devId); + DISPLAY_CHK_RETURN((devId == INVALIDE_DISPLAY_ID), DISPLAY_FAILURE, DISPLAY_LOGE("invalide device id")); + auto iter = mHdiDisplays.find(devId); + DISPLAY_CHK_RETURN((iter == mHdiDisplays.end()), DISPLAY_FAILURE, + DISPLAY_LOGE("can not find display %{public}d", devId)); + auto display = iter->second.get(); + auto layer = display->GetHdiLayer(layerId); + DISPLAY_CHK_RETURN((layer == nullptr), DISPLAY_FAILURE, + DISPLAY_LOGE("can not find the layer %{public}d", layerId)); + return (layer->*member)(std::forward(args)...); + } + + int32_t RegHotPlugCallback(HotPlugCallback callback, void *data); + void DoHotPlugCallback(uint32_t devId, bool connect); + void HandleHotplug(bool plugIn); + +private: + std::unordered_map> mHdiDisplays; + std::vector> mHdiDevices; + std::unordered_map mHotPlugCallBacks; +}; +} // namespace OHOS +} // namespace HDI +} // namespace DISPLAY + +#endif // HDI_SESSION_H \ No newline at end of file diff --git a/hardware/display/src/display_device/hdi_shared_fd.h b/hardware/display/src/display_device/hdi_shared_fd.h new file mode 100644 index 0000000000000000000000000000000000000000..d21cfb940efe5e4896b2085436cf1a8aeb758670 --- /dev/null +++ b/hardware/display/src/display_device/hdi_shared_fd.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HDI_SHARED_FD +#define HDI_SHARED_FD +#include +#include +#include "display_common.h" + +namespace OHOS { +namespace HDI { +namespace DISPLAY { +class HdiFd { +public: + HdiFd() + { + DISPLAY_DEBUGLOG(); + } + explicit HdiFd(int fd) : mFd(fd) + { + DISPLAY_DEBUGLOG("mFd %{public}d", mFd); + } + int GetFd() const + { + return mFd; + }; + + HdiFd &operator = (int fd) + { + if (mFd >= 0) { + close(mFd); + } + mFd = fd; + return *this; + } + + virtual ~HdiFd() + { + if (mFd >= 0) { + close(mFd); + } + } + +private: + int mFd = -1; +}; + +using FdPtr = std::shared_ptr; +} // OHOS +} // HDIO +} // DISPLAY + +#endif // HDI_SHARED_FD \ No newline at end of file diff --git a/hardware/display/src/display_gfx/display_gfx.c b/hardware/display/src/display_gfx/display_gfx.c new file mode 100644 index 0000000000000000000000000000000000000000..e6105d726f06a8575da0661460164867f7c220f6 --- /dev/null +++ b/hardware/display/src/display_gfx/display_gfx.c @@ -0,0 +1,515 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include "im2d.h" +#include "rga.h" +#include "display_common.h" +#include "display_gralloc.h" +#include "securec.h" +#include "display_gfx.h" + +#define ALIGN_UP(x, a) ((((x) + ((a)-1)) / (a)) * (a)) +GrallocFuncs *grallocFucs = NULL; +int32_t rkInitGfx() +{ + DISPLAY_LOGE("%s\n", querystring(RGA_ALL)); + return DISPLAY_SUCCESS; +} + +int32_t rkDeinitGfx() +{ + return DISPLAY_SUCCESS; +} + +RgaSURF_FORMAT colorSpaceModeChange(PixelFormat color, uint8_t *isYuv) +{ + RgaSURF_FORMAT rkFormat; + switch (color) { + case PIXEL_FMT_RGB_565: /**< RGB565 format */ + rkFormat = RK_FORMAT_RGB_565; + *isYuv = 0; + break; + case PIXEL_FMT_RGBA_4444: /**< RGBA4444 format */ + rkFormat = RK_FORMAT_RGBA_4444; + *isYuv = 0; + break; + case PIXEL_FMT_RGBA_5551: /**< RGBA5551 format */ + rkFormat = RK_FORMAT_RGBA_5551; + *isYuv = 0; + break; + case PIXEL_FMT_RGBX_8888: /**< RGBX8888 format */ + rkFormat = RK_FORMAT_RGBX_8888; + *isYuv = 0; + break; + case PIXEL_FMT_RGBA_8888: /**< RGBA8888 format */ + rkFormat = RK_FORMAT_RGBA_8888; + *isYuv = 0; + break; + case PIXEL_FMT_RGB_888: /**< RGB888 format */ + rkFormat = RK_FORMAT_RGB_888; + *isYuv = 0; + break; + case PIXEL_FMT_BGR_565: /**< BGR565 format */ + rkFormat = RK_FORMAT_BGR_565; + *isYuv = 0; + break; + case PIXEL_FMT_BGRA_4444: /**< BGRA4444 format */ + rkFormat = RK_FORMAT_BGRA_4444; + *isYuv = 0; + break; + case PIXEL_FMT_BGRA_5551: /**< BGRA5551 format */ + rkFormat = RK_FORMAT_BGRA_5551; + *isYuv = 0; + break; + case PIXEL_FMT_BGRX_8888: /**< BGRX8888 format */ + rkFormat = RK_FORMAT_BGRX_8888; + *isYuv = 0; + break; + case PIXEL_FMT_BGRA_8888: /**< BGRA8888 format */ + rkFormat = RK_FORMAT_BGRA_8888; + *isYuv = 0; + break; + case PIXEL_FMT_YCBCR_422_SP: /**< YCBCR422 semi-planar format */ + rkFormat = RK_FORMAT_YCbCr_420_SP; + *isYuv = 1; + break; + case PIXEL_FMT_YCRCB_422_SP: /**< YCRCB422 semi-planar format */ + rkFormat = RK_FORMAT_YCrCb_422_SP; + *isYuv = 1; + break; + case PIXEL_FMT_YCBCR_420_SP: /**< YCBCR420 semi-planar format */ + rkFormat = RK_FORMAT_YCbCr_420_SP; + *isYuv = 1; + break; + case PIXEL_FMT_YCRCB_420_SP: /**< YCRCB420 semi-planar format */ + rkFormat = RK_FORMAT_YCrCb_420_SP; + *isYuv = 1; + break; + case PIXEL_FMT_YCBCR_422_P: /**< YCBCR422 planar format */ + rkFormat = RK_FORMAT_YCbCr_422_P; + *isYuv = 1; + break; + case PIXEL_FMT_YCRCB_422_P: /**< YCRCB422 planar format */ + rkFormat = RK_FORMAT_YCrCb_422_P; + *isYuv = 1; + break; + case PIXEL_FMT_YCBCR_420_P: /**< YCBCR420 planar format */ + rkFormat = RK_FORMAT_YCbCr_420_P; + *isYuv = 1; + break; + case PIXEL_FMT_YCRCB_420_P: /**< YCRCB420 planar format */ + rkFormat = RK_FORMAT_YCrCb_420_P; + *isYuv = 1; + break; + case PIXEL_FMT_YUYV_422_PKG: /**< YUYV422 packed format */ + rkFormat = RK_FORMAT_YUYV_422; + *isYuv = 1; + break; + case PIXEL_FMT_UYVY_422_PKG: /**< UYVY422 packed format */ + rkFormat = RK_FORMAT_UYVY_422; + *isYuv = 1; + break; + case PIXEL_FMT_YVYU_422_PKG: /**< YVYU422 packed format */ + rkFormat = RK_FORMAT_YUYV_422; + *isYuv = 1; + break; + case PIXEL_FMT_VYUY_422_PKG: /**< VYUY422 packed format */ + rkFormat = RK_FORMAT_VYUY_422; + *isYuv = 1; + break; + default: +// PIXEL_FMT_CLUT8: /**< CLUT8 format */ +// PIXEL_FMT_CLUT1, /**< CLUT1 format */ +// PIXEL_FMT_CLUT4, /**< CLUT4 format */ +// PIXEL_FMT_RGBA_5658, /**< RGBA5658 format */ +// PIXEL_FMT_RGBX_4444, /**< RGBX4444 format */ +// PIXEL_FMT_RGB_444, /**< RGB444 format */ +// PIXEL_FMT_RGBX_5551, /**< RGBX5551 format */ +// PIXEL_FMT_RGB_555, /**< RGB555 format */ +// PIXEL_FMT_BGRX_4444, /**< BGRX4444 format */ +// PIXEL_FMT_BGRX_5551, /**< BGRX5551 format */ +// PIXEL_FMT_YUV_422_I, /**< YUV422 interleaved format */ + rkFormat = RK_FORMAT_UNKNOWN; + break; + } + return rkFormat; +} + +int32_t rkFillRect(ISurface *iSurface, IRect *rect, uint32_t color, GfxOpt *opt) +{ + rga_buffer_t dst; + im_rect imRect; + IM_STATUS ret; + uint8_t isYuv; + + errno_t eok = memset_s((void *)&imRect, sizeof(imRect), 0, sizeof(imRect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + imRect.x = rect->x; + imRect.y = rect->y; + imRect.width = rect->w; + imRect.height = rect->h; + + eok = memset_s((void *)&dst, sizeof(dst), 0, sizeof(dst)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + dst.phy_addr = 0; // (void*)iSurface->phyAddr; + dst.vir_addr = 0; // iSurface->virAddr; + dst.fd = (int32_t)iSurface->phyAddr; + if ((int)dst.phy_addr == 0 && dst.fd == 0 && dst.vir_addr == NULL) { + DISPLAY_LOGE("source iSurface address error"); + return DISPLAY_PARAM_ERR; + } + DISPLAY_LOGE("gfx vir %{public}p phy 0x%{public}x fd %{public}d", dst.vir_addr, (int32_t)dst.phy_addr, dst.fd); + dst.width = iSurface->width; + dst.height = iSurface->height; + dst.wstride = ALIGN_UP(iSurface->width, 16); + dst.hstride = ALIGN_UP(iSurface->height, 16); + dst.format = colorSpaceModeChange(iSurface->enColorFmt, &isYuv); + dst.color_space_mode = IM_COLOR_SPACE_DEFAULT; + dst.color = color; + if (opt->enGlobalAlpha) + dst.global_alpha = opt->globalAlpha; + ret = imfill(dst, imRect, color); + if (ret != IM_STATUS_SUCCESS) + return DISPLAY_FAILURE; + else + return DISPLAY_SUCCESS; +} + +int32_t blendTypeChange(BlendType blendType) +{ + int32_t rkBlendType; + switch (blendType) { + case BLEND_SRC: /**< SRC blending */ + rkBlendType = IM_ALPHA_BLEND_SRC; + break; + case BLEND_DST: /**< SRC blending */ + rkBlendType = IM_ALPHA_BLEND_DST; + break; + case BLEND_SRCOVER: /**< SRC_OVER blending */ + rkBlendType = IM_ALPHA_BLEND_SRC_OVER; + break; + case BLEND_DSTOVER: /**< DST_OVER blending */ + rkBlendType = IM_ALPHA_BLEND_DST_OVER; + break; + default: + /* Fix up later */ +// BLEND_NONE /**< No blending */ +// BLEND_CLEAR: /**< CLEAR blending */ +// BLEND_SRCIN: /**< SRC_IN blending */ +// BLEND_DSTIN: /**< DST_IN blending */ +// BLEND_SRCOUT: /**< SRC_OUT blending */ +// BLEND_DSTOUT: /**< DST_OUT blending */ +// BLEND_SRCATOP: /**< SRC_ATOP blending */ +// BLEND_DSTATOP: /**< DST_ATOP blending */ +// BLEND_ADD: /**< ADD blending */ +// BLEND_XOR: /**< XOR blending */ +// BLEND_DST: /**< DST blending */ +// BLEND_AKS: /**< AKS blending */ +// BLEND_AKD: /**< AKD blending */ +// BLEND_BUTT: /**< Null operation */ + rkBlendType = IM_STATUS_NOT_SUPPORTED; + break; + } + return rkBlendType; +} + +int32_t TransformTypeChange(TransformType type) +{ + int32_t rkRotateType; + switch (type) { + case ROTATE_90: /**< Rotation by 90 degrees */ + rkRotateType = IM_HAL_TRANSFORM_ROT_90; + break; + case ROTATE_180: /**< Rotation by 180 degrees */ + rkRotateType = IM_HAL_TRANSFORM_ROT_180; + break; + case ROTATE_270: /**< Rotation by 270 degrees */ + rkRotateType = IM_HAL_TRANSFORM_ROT_270; + break; + default: + rkRotateType = 0; /**< No rotation */ + break; + } + return rkRotateType; +} + +int32_t mirrorTypeChange(MirrorType type) +{ + int32_t rkMirrorType; + switch (type) { + case MIRROR_LR: /**< Left and right mirrors */ + rkMirrorType = IM_HAL_TRANSFORM_FLIP_H; + break; + case MIRROR_TB: /**< Top and bottom mirrors */ + rkMirrorType = IM_HAL_TRANSFORM_FLIP_V; + break; + default: + rkMirrorType = 0; + break; + } + return rkMirrorType; +} + +int32_t doFlit(ISurface *srcSurface, IRect *srcRect, ISurface *dstSurface, IRect *dstRect, GfxOpt *opt) +{ + int32_t usage = 0; + uint8_t isYuv = 0; + rga_buffer_t dstRgaBuffer, srcRgaBuffer, bRgbBuffer; + IM_STATUS ret = 0; + im_rect srect; + im_rect drect; + im_rect prect; + int32_t rkBlendType = 0; + int32_t rkRotateType = 0; + int32_t rkMirrorType = 0; + + errno_t eok = memset_s(&dstRgaBuffer, sizeof(dstRgaBuffer), 0, sizeof(dstRgaBuffer)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + eok = memset_s(&srcRgaBuffer, sizeof(srcRgaBuffer), 0, sizeof(srcRgaBuffer)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + eok = memset_s(&bRgbBuffer, sizeof(bRgbBuffer), 0, sizeof(bRgbBuffer)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + eok = memset_s(&srect, sizeof(srect), 0, sizeof(srect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + eok = memset_s(&drect, sizeof(drect), 0, sizeof(drect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + eok = memset_s(&prect, sizeof(prect), 0, sizeof(prect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + if (opt->enGlobalAlpha) { + dstRgaBuffer.global_alpha = opt->globalAlpha; + srcRgaBuffer.global_alpha = opt->globalAlpha; + } + dstRgaBuffer.width = dstSurface->width; + dstRgaBuffer.height = dstSurface->height; + dstRgaBuffer.wstride = ALIGN_UP(dstSurface->width, 16); + dstRgaBuffer.hstride = ALIGN_UP(dstSurface->height, 16); + dstRgaBuffer.format = colorSpaceModeChange(dstSurface->enColorFmt, &isYuv); + dstRgaBuffer.phy_addr = 0; // (void *)dstSurface->phyAddr; + dstRgaBuffer.vir_addr = 0; // dstSurface->virAddr; + dstRgaBuffer.color_space_mode = IM_COLOR_SPACE_DEFAULT; + dstRgaBuffer.fd = (int32_t)dstSurface->phyAddr; + if (isYuv == 1) { + DISPLAY_LOGE("rk gfx do not support dst buffer is yuv format"); + return DISPLAY_PARAM_ERR; + } + + srcRgaBuffer.width = srcSurface->width; + srcRgaBuffer.height = srcSurface->height; + srcRgaBuffer.wstride = ALIGN_UP(srcSurface->width, 16); + srcRgaBuffer.hstride = ALIGN_UP(srcSurface->height, 16); + srcRgaBuffer.phy_addr = 0; // (void *)srcSurface->phyAddr; + srcRgaBuffer.vir_addr = 0; // srcSurface->virAddr; + srcRgaBuffer.format = colorSpaceModeChange(srcSurface->enColorFmt, &isYuv); + srcRgaBuffer.color_space_mode = IM_COLOR_SPACE_DEFAULT; + srcRgaBuffer.fd = (int32_t)srcSurface->phyAddr; + + if ((int)srcRgaBuffer.phy_addr == 0 && srcRgaBuffer.fd == 0 && srcRgaBuffer.vir_addr == NULL) { + DISPLAY_LOGE("source iSurface address error"); + return DISPLAY_PARAM_ERR; + } + + DISPLAY_LOGE("gfx src fd %{public}d, w %{public}d, h %{publuc}d, sw %{public}d sh %{public}d vir %{public}p", + (int32_t)srcSurface->phyAddr, srcSurface->width, srcSurface->height, ALIGN_UP(srcSurface->width, 16), + ALIGN_UP(srcSurface->height, 16), srcRgaBuffer.vir_addr); + DISPLAY_LOGE("gfx dst fd %{public}d, w %{public}d, h %{public}d, sw %{public}d sh %{public}d vir %{public}p", + (int32_t)dstSurface->phyAddr, dstSurface->width, dstSurface->height, ALIGN_UP(dstSurface->width, 16), + ALIGN_UP(dstSurface->height, 16), dstRgaBuffer.vir_addr); + + srect.x = srcRect->x; + srect.y = srcRect->y; + srect.height = srcRect->h; + srect.width = srcRect->w; + drect.x = dstRect->x; + drect.y = dstRect->y; + drect.height = dstRect->h; + drect.width = dstRect->w; + + if (opt->blendType) { + rkBlendType = blendTypeChange(opt->blendType); + if (rkBlendType > 0) { + usage |= rkBlendType; + if (rkBlendType == IM_ALPHA_BLEND_DST_OVER || rkBlendType == IM_ALPHA_BLEND_SRC_OVER) + usage |= IM_ALPHA_BLEND_PRE_MUL; + } else if (rkBlendType == IM_STATUS_NOT_SUPPORTED) { + return DISPLAY_NOT_SUPPORT; + } + } + if (opt->rotateType) { + rkRotateType = TransformTypeChange(opt->rotateType); + if (rkRotateType != 0) + usage |= rkRotateType; + } + if (opt->mirrorType == MIRROR_LR || opt->mirrorType == MIRROR_TB) { + rkMirrorType = mirrorTypeChange(opt->mirrorType); + if (rkMirrorType != 0) + usage |= rkMirrorType; + } + if (opt->enableScale) { + DISPLAY_LOGE("gfx scale from (%{puhblic}d, %{public}d) to (%{public}d, %{public}d)", srcRgaBuffer.width, srcRgaBuffer.height, dstRgaBuffer.width, + dstRgaBuffer.height); + } + usage |= IM_SYNC; + if (isYuv == 1) { + if (rkBlendType == IM_ALPHA_BLEND_SRC_OVER || rkBlendType == IM_ALPHA_BLEND_SRC) { + usage = 0; + if (opt->enableScale == 0) { + eok = memset_s(&srect, sizeof(srect), 0, sizeof(srect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + srect.width = srcRgaBuffer.width; + srect.height = srcRgaBuffer.height; + + eok = memset_s(&drect, sizeof(drect), 0, sizeof(drect)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + return false; + } + drect.x = dstRgaBuffer.width - srcRgaBuffer.width; + drect.y = dstRgaBuffer.height - srcRgaBuffer.height; + drect.width = srcRgaBuffer.width; + drect.height = srcRgaBuffer.height; + } + usage = rkRotateType | rkMirrorType | IM_SYNC; + ret = improcess(srcRgaBuffer, dstRgaBuffer, bRgbBuffer, srect, drect, prect, usage); + if (ret != IM_STATUS_SUCCESS) { + DISPLAY_LOGE("gfx improcess %{public}s", imStrError(ret)); + } + } else if (rkBlendType == IM_ALPHA_BLEND_DST_OVER) { + if (grallocFucs == NULL) { + ret = GrallocInitialize(&grallocFucs); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("Gralloc init failed")); + } + AllocInfo info = { + .width = dstRgaBuffer.width, + .height = dstRgaBuffer.height, + .usage = HBM_USE_MEM_DMA | HBM_USE_CPU_READ | HBM_USE_CPU_WRITE, + .format = PIXEL_FMT_RGBA_8888, // srcSurface->enColorFmt, + }; + BufferHandle *buffer = NULL; + + ret = grallocFucs->AllocMem(&info, &buffer); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, DISPLAY_LOGE("can not alloc memory")); + + bRgbBuffer.width = dstRgaBuffer.width; + bRgbBuffer.height = dstRgaBuffer.height; + bRgbBuffer.wstride = dstRgaBuffer.wstride; + bRgbBuffer.hstride = dstRgaBuffer.hstride; + bRgbBuffer.format = RK_FORMAT_RGBA_8888; // srcRgaBuffer.format; + bRgbBuffer.phy_addr = 0; // (void *) buffer->phyAddr; + bRgbBuffer.vir_addr = 0; // buffer->virAddr; + bRgbBuffer.color_space_mode = dstRgaBuffer.color_space_mode; + bRgbBuffer.fd = (int32_t)buffer->phyAddr; + int ret = memcpy_s(&prect, sizeof(drect), &drect, sizeof(drect)); + if (!ret) { + printf("memcpy_s failed!\n"); + } + ret = improcess(srcRgaBuffer, bRgbBuffer, dstRgaBuffer, srect, prect, drect, usage); + if (ret != IM_STATUS_SUCCESS) { + DISPLAY_LOGE("gfx improcess %{public}s", imStrError(ret)); + } else { + ret = imcopy(bRgbBuffer, dstRgaBuffer); + if (ret != IM_STATUS_SUCCESS) { + DISPLAY_LOGE("gfx improcess %{public}s", imStrError(ret)); + } + } + grallocFucs->FreeMem(buffer); + } + } else { + ret = improcess(srcRgaBuffer, dstRgaBuffer, bRgbBuffer, srect, drect, prect, usage); + if (ret != IM_STATUS_SUCCESS) { + DISPLAY_LOGE("gfx improcess %{public}s", imStrError(ret)); + } + } + if (ret != IM_STATUS_SUCCESS) + return DISPLAY_FAILURE; + else + return DISPLAY_SUCCESS; +} + +int32_t rkBlit(ISurface *srcSurface, IRect *srcRect, ISurface *dstSurface, IRect *dstRect, GfxOpt *opt) +{ + CHECK_NULLPOINTER_RETURN_VALUE(srcSurface, DISPLAY_NULL_PTR); + CHECK_NULLPOINTER_RETURN_VALUE(srcRect, DISPLAY_NULL_PTR); + CHECK_NULLPOINTER_RETURN_VALUE(dstSurface, DISPLAY_NULL_PTR); + CHECK_NULLPOINTER_RETURN_VALUE(dstRect, DISPLAY_NULL_PTR); + CHECK_NULLPOINTER_RETURN_VALUE(opt, DISPLAY_NULL_PTR); + + if (doFlit(srcSurface, srcRect, dstSurface, dstRect, opt) < 0) + return DISPLAY_FAILURE; + else + return DISPLAY_SUCCESS; +} + +int32_t rkSync(int32_t timeOut) +{ + return DISPLAY_SUCCESS; +} + +int32_t GfxInitialize(GfxFuncs **funcs) +{ + DISPLAY_CHK_RETURN((funcs == NULL), DISPLAY_PARAM_ERR, DISPLAY_LOGE("info is null")); + GfxFuncs *gfxFuncs = (GfxFuncs *)malloc(sizeof(GfxFuncs)); + DISPLAY_CHK_RETURN((gfxFuncs == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("gfxFuncs is nullptr")); + errno_t eok = memset_s((void *)gfxFuncs, sizeof(GfxFuncs), 0, sizeof(GfxFuncs)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + free(gfxFuncs); + return DISPLAY_FAILURE; + } + gfxFuncs->InitGfx = rkInitGfx; + gfxFuncs->DeinitGfx = rkDeinitGfx; + gfxFuncs->FillRect = rkFillRect; + gfxFuncs->Blit = rkBlit; + gfxFuncs->Sync = rkSync; + *funcs = gfxFuncs; + + return DISPLAY_SUCCESS; +} + +int32_t GfxUninitialize(GfxFuncs *funcs) +{ + CHECK_NULLPOINTER_RETURN_VALUE(funcs, DISPLAY_NULL_PTR); + free(funcs); + DISPLAY_LOGI("%s: gfx uninitialize success", __func__); + return DISPLAY_SUCCESS; +} diff --git a/hardware/display/src/display_gralloc/display_gralloc.c b/hardware/display/src/display_gralloc/display_gralloc.c new file mode 100644 index 0000000000000000000000000000000000000000..2be67aa2f58057fcca76082f1b3cbcc0f9b22716 --- /dev/null +++ b/hardware/display/src/display_gralloc/display_gralloc.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "display_gralloc.h" +#include +#include +#include "display_common.h" +#include "display_gralloc_gbm.h" + +int32_t AllocMem(const AllocInfo *info, BufferHandle **handle) +{ + DISPLAY_CHK_RETURN((info == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("info is null")); + DISPLAY_CHK_RETURN((handle == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (info->usage & HBM_USE_MEM_DMA) { + return GbmAllocMem(info, handle); + } +#endif + DISPLAY_LOGE("the usage is not support 0x%{public}" PRIx64 "", info->usage); + return DISPLAY_NOT_SUPPORT; +} + +void FreeMem(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((handle == NULL), DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (handle->usage & HBM_USE_MEM_DMA) { + GbmFreeMem(handle); + return; + } +#endif +} + +void *Mmap(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN((handle == NULL), NULL, DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (handle->usage & HBM_USE_MEM_DMA) { + return GbmMmap(handle); + } +#endif + return NULL; +} + +int32_t Unmap(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN((handle == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (handle->usage & HBM_USE_MEM_DMA) { + return GbmUnmap(handle); + } +#endif + return DISPLAY_NOT_SUPPORT; +} + +int32_t FlushCache(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN((handle == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (handle->usage & HBM_USE_MEM_DMA) { + return GbmFlushCache(handle); + } +#endif + return DISPLAY_NOT_SUPPORT; +} + +int32_t InvalidateCache(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN((handle == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("handle is null")); +#ifdef GRALLOC_GBM_SUPPORT + if (handle->usage & HBM_USE_MEM_DMA) { + return GbmInvalidateCache(handle); + } +#endif + return DISPLAY_NOT_SUPPORT; +} + +int32_t GrallocUninitialize(GrallocFuncs *funcs) +{ + DISPLAY_CHK_RETURN(funcs == NULL, DISPLAY_PARAM_ERR, DISPLAY_LOGE("funcs is null")); + DISPLAY_DEBUGLOG(); +#ifdef GRALLOC_GBM_SUPPORT + if (GbmGrallocUninitialize() != DISPLAY_SUCCESS) { + DISPLAY_LOGE("gbm uninit failed"); + } +#endif + free(funcs); + return DISPLAY_SUCCESS; +} + +int32_t GrallocInitialize(GrallocFuncs **funcs) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN((funcs == NULL), DISPLAY_PARAM_ERR, DISPLAY_LOGE("funcs is null")); + GrallocFuncs *grallocFuncs = (GrallocFuncs *)malloc(sizeof(GrallocFuncs)); + DISPLAY_CHK_RETURN((grallocFuncs == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("memset_s failed")); + errno_t eok = memset_s(grallocFuncs, sizeof(GrallocFuncs), 0, sizeof(GrallocFuncs)); + DISPLAY_CHK_RETURN((eok != EOK), DISPLAY_FAILURE, DISPLAY_LOGE("memset_s failed")); + // initialize gbm gralloc +#ifdef GRALLOC_GBM_SUPPORT + int ret = GbmGrallocInitialize(); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), ret, DISPLAY_LOGE("gbm initial"); + free(grallocFuncs)); +#endif + grallocFuncs->AllocMem = AllocMem; + grallocFuncs->FreeMem = FreeMem; + grallocFuncs->Mmap = Mmap; + grallocFuncs->Unmap = Unmap; + grallocFuncs->InvalidateCache = InvalidateCache; + grallocFuncs->FlushCache = FlushCache; + *funcs = grallocFuncs; + return DISPLAY_SUCCESS; +} diff --git a/hardware/display/src/display_gralloc/display_gralloc_gbm.c b/hardware/display/src/display_gralloc/display_gralloc_gbm.c new file mode 100644 index 0000000000000000000000000000000000000000..872a54d71e4d7cdc4b5283f28e3467cf2d2f7d25 --- /dev/null +++ b/hardware/display/src/display_gralloc/display_gralloc_gbm.c @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "display_gralloc_gbm.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wayland_drm_auth_client.h" +#include "drm_fourcc.h" +#include "hisilicon_drm.h" +#include "hi_gbm.h" +#include "hdf_dlist.h" +#include "display_gralloc_private.h" +#include "display_common.h" + +const char *g_drmFileNode = "/dev/dri/renderD128"; +static GrallocManager *g_grallocManager = NULL; +static pthread_mutex_t g_lock; + +typedef struct { + uint32_t drmFormat; + PixelFormat pixFormat; +} PixelFormatConvertTbl; + +typedef struct { + uint32_t value; + const char *str; +} ValueStrMap; + +static GrallocManager *GetGrallocManager(void) +{ + if (g_grallocManager == NULL) { + g_grallocManager = (GrallocManager *)malloc(sizeof(GrallocManager)); + errno_t eok = memset_s(g_grallocManager, sizeof(GrallocManager), 0, sizeof(GrallocManager)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + } + if (g_grallocManager == NULL) { + DISPLAY_LOGE("gralloc manager malloc failed"); + } + } + return g_grallocManager; +} + +const char *GetPixelFmtStr(PixelFormat format) +{ + static const ValueStrMap pixelStrMaps[] = { + {PIXEL_FMT_CLUT8, "PIXEL_FMT_CLUT8"}, {PIXEL_FMT_CLUT1, "PIXEL_FMT_CLUT1"}, + {PIXEL_FMT_CLUT4, "PIXEL_FMT_CLUT4"}, {PIXEL_FMT_RGB_565, "PIXEL_FMT_RGB_565"}, + {PIXEL_FMT_RGBA_5658, "IXEL_FMT_RGBA_5658"}, {PIXEL_FMT_RGBX_4444, "PIXEL_FMT_RGBX_4444"}, + {PIXEL_FMT_RGBA_4444, "PIXEL_FMT_RGBA_4444"}, {PIXEL_FMT_RGB_444, "PIXEL_FMT_RGB_444"}, + {PIXEL_FMT_RGBX_5551, "PIXEL_FMT_RGBX_5551"}, {PIXEL_FMT_RGBA_5551, "PIXEL_FMT_RGBA_5551"}, + {PIXEL_FMT_RGB_555, "PIXEL_FMT_RGB_555"}, {PIXEL_FMT_RGBX_8888, "PIXEL_FMT_RGBX_8888"}, + {PIXEL_FMT_RGBA_8888, "PIXEL_FMT_RGBA_8888"}, {PIXEL_FMT_RGB_888, "PIXEL_FMT_RGB_888"}, + {PIXEL_FMT_BGR_565, "PIXEL_FMT_BGR_565"}, {PIXEL_FMT_BGRX_4444, "PIXEL_FMT_BGRX_4444"}, + {PIXEL_FMT_BGRA_4444, "PIXEL_FMT_BGRA_4444"}, {PIXEL_FMT_BGRX_5551, "PIXEL_FMT_BGRX_5551"}, + {PIXEL_FMT_BGRA_5551, "PIXEL_FMT_BGRA_5551"}, {PIXEL_FMT_BGRX_8888, "PIXEL_FMT_BGRX_8888"}, + {PIXEL_FMT_BGRA_8888, "PIXEL_FMT_BGRA_8888"}, {PIXEL_FMT_YUV_422_I, "PIXEL_FMT_YUV_422_I"}, + {PIXEL_FMT_YUV_422_I, "PIXEL_FMT_YUV_422_I"}, {PIXEL_FMT_YCBCR_422_SP, "PIXEL_FMT_YCBCR_422_SP"}, + {PIXEL_FMT_YCRCB_422_SP, "PIXEL_FMT_YCRCB_422_SP"}, {PIXEL_FMT_YCBCR_420_SP, "PIXEL_FMT_YCBCR_420_SP"}, + {PIXEL_FMT_YCRCB_420_SP, "PIXEL_FMT_YCRCB_420_SP"}, {PIXEL_FMT_YCBCR_422_P, "PIXEL_FMT_YCBCR_422_P"}, + {PIXEL_FMT_YCRCB_422_P, "PIXEL_FMT_YCRCB_422_P"}, {PIXEL_FMT_YCBCR_420_P, "PIXEL_FMT_YCBCR_420_P"}, + {PIXEL_FMT_YCRCB_420_P, "PIXEL_FMT_YCRCB_420_P"}, {PIXEL_FMT_YUYV_422_PKG, "PIXEL_FMT_YUYV_422_PKG"}, + {PIXEL_FMT_UYVY_422_PKG, "PIXEL_FMT_UYVY_422_PKG"}, {PIXEL_FMT_YVYU_422_PKG, "PIXEL_FMT_YVYU_422_PKG"}, + {PIXEL_FMT_VYUY_422_PKG, "PIXEL_FMT_VYUY_422_PKG"}, {PIXEL_FMT_BUTT, "PIXEL_FMT_BUTT"}, + }; + static const char *unknown = "unknown format"; + for (uint32_t i = 0; i < sizeof(pixelStrMaps) / sizeof(pixelStrMaps[0]); i++) { + if (pixelStrMaps[i].value == format) { + return pixelStrMaps[i].str; + } + } + DISPLAY_LOGE("GetPixelFmtStr unknown format %{public}d", format); + return unknown; +} + +const char *GetDrmFmtStr(uint32_t format) +{ + static const ValueStrMap formatStrMaps[] = { + {DRM_FORMAT_C8, "DRM_FORMAT_C8" }, {DRM_FORMAT_R8, "DRM_FORMAT_R8" }, + {DRM_FORMAT_R16, "DRM_FORMAT_R16"}, {DRM_FORMAT_RG88, "DRM_FORMAT_RG88"}, + {DRM_FORMAT_GR88, "DRM_FORMAT_GR88"}, {DRM_FORMAT_RG1616, "DRM_FORMAT_RG1616"}, + {DRM_FORMAT_GR1616, "DRM_FORMAT_GR1616"}, {DRM_FORMAT_RGB332, "DRM_FORMAT_RGB332"}, + {DRM_FORMAT_BGR233, "DRM_FORMAT_BGR233"}, {DRM_FORMAT_XRGB4444, "DRM_FORMAT_XRGB4444"}, + {DRM_FORMAT_XBGR4444, "DRM_FORMAT_XBGR4444"}, {DRM_FORMAT_RGBX4444, "DRM_FORMAT_RGBX4444"}, + {DRM_FORMAT_BGRX4444, "DRM_FORMAT_BGRX4444"}, {DRM_FORMAT_ARGB4444, "DRM_FORMAT_ARGB4444"}, + {DRM_FORMAT_ABGR4444, "DRM_FORMAT_ABGR4444"}, {DRM_FORMAT_RGBA4444, "DRM_FORMAT_RGBA4444"}, + {DRM_FORMAT_BGRA4444, "DRM_FORMAT_BGRA4444"}, {DRM_FORMAT_XRGB1555, "DRM_FORMAT_XRGB1555"}, + {DRM_FORMAT_XBGR1555, "DRM_FORMAT_XBGR1555"}, {DRM_FORMAT_RGBX5551, "DRM_FORMAT_RGBX5551"}, + {DRM_FORMAT_BGRX5551, "DRM_FORMAT_BGRX5551"}, {DRM_FORMAT_ARGB1555, "DRM_FORMAT_ARGB1555"}, + {DRM_FORMAT_ABGR1555, "DRM_FORMAT_ABGR1555"}, {DRM_FORMAT_RGBA5551, "DRM_FORMAT_RGBA5551"}, + {DRM_FORMAT_BGRA5551, "DRM_FORMAT_BGRA5551"}, {DRM_FORMAT_RGB565, "DRM_FORMAT_RGB565"}, + {DRM_FORMAT_BGR565, "DRM_FORMAT_BGR565"}, {DRM_FORMAT_RGB888, "DRM_FORMAT_RGB888"}, + {DRM_FORMAT_BGR888, "DRM_FORMAT_BGR888"}, {DRM_FORMAT_XRGB8888, "DRM_FORMAT_XRGB8888"}, + {DRM_FORMAT_XBGR8888, "DRM_FORMAT_XBGR8888"}, {DRM_FORMAT_RGBX8888, "DRM_FORMAT_RGBX8888"}, + {DRM_FORMAT_BGRX8888, "DRM_FORMAT_BGRX8888"}, {DRM_FORMAT_ARGB8888, "DRM_FORMAT_ARGB8888"}, + {DRM_FORMAT_ABGR8888, "DRM_FORMAT_ABGR8888"}, {DRM_FORMAT_RGBA8888, "DRM_FORMAT_RGBA8888"}, + {DRM_FORMAT_BGRA8888, "DRM_FORMAT_BGRA8888"}, {DRM_FORMAT_XRGB2101010, "DRM_FORMAT_XRGB2101010"}, + {DRM_FORMAT_BGRX1010102, "DRM_FORMAT_BGRX1010102"}, {DRM_FORMAT_ARGB2101010, "DRM_FORMAT_ARGB2101010"}, + {DRM_FORMAT_ABGR2101010, "DRM_FORMAT_ABGR2101010"}, {DRM_FORMAT_RGBA1010102, "DRM_FORMAT_RGBA1010102"}, + {DRM_FORMAT_YVYU, "DRM_FORMAT_YVYU"}, {DRM_FORMAT_UYVY, "DRM_FORMAT_UYVY"}, + {DRM_FORMAT_VYUY, "DRM_FORMAT_VYUY"}, {DRM_FORMAT_AYUV, "DRM_FORMAT_AYUV"}, + {DRM_FORMAT_NV12, "DRM_FORMAT_NV12"}, {DRM_FORMAT_NV21, "DRM_FORMAT_NV21"}, + {DRM_FORMAT_NV16, "DRM_FORMAT_NV16"}, {DRM_FORMAT_NV61, "DRM_FORMAT_NV61"}, + {DRM_FORMAT_NV24, "DRM_FORMAT_NV24"}, {DRM_FORMAT_NV42, "DRM_FORMAT_NV42"}, + {DRM_FORMAT_YUV410, "DRM_FORMAT_YUV410"}, {DRM_FORMAT_YVU410, "DRM_FORMAT_YVU410"}, + {DRM_FORMAT_YUV411, "DRM_FORMAT_YUV411"}, {DRM_FORMAT_YVU411, "DRM_FORMAT_YVU411"}, + {DRM_FORMAT_YUV420, "DRM_FORMAT_YUV420"}, {DRM_FORMAT_YVU420, "DRM_FORMAT_YVU420"}, + {DRM_FORMAT_YUV422, "DRM_FORMAT_YUV422"}, {DRM_FORMAT_YVU422, "DRM_FORMAT_YVU422"}, + {DRM_FORMAT_YUV444, "DRM_FORMAT_YUV444"}, {DRM_FORMAT_YVU444, "DRM_FORMAT_YVU444"}, + }; + + static const char *unknown = "unknown drm format"; + for (uint32_t i = 0; i < sizeof(formatStrMaps) / sizeof(formatStrMaps[0]); i++) { + if (formatStrMaps[i].value == format) { + return formatStrMaps[i].str; + } + } + DISPLAY_LOGE("GetDrmFmtStr unknown format %{public}d", format); + return unknown; +} + +static uint32_t ConvertFormatToDrm(PixelFormat fmtIn) +{ + static const PixelFormatConvertTbl convertTable[] = { + {DRM_FORMAT_RGBX8888, PIXEL_FMT_RGBX_8888}, {DRM_FORMAT_RGBA8888, PIXEL_FMT_RGBA_8888}, + {DRM_FORMAT_RGB888, PIXEL_FMT_RGB_888}, {DRM_FORMAT_RGB565, PIXEL_FMT_BGR_565}, + {DRM_FORMAT_BGRX4444, PIXEL_FMT_BGRX_4444}, {DRM_FORMAT_BGRA4444, PIXEL_FMT_BGRA_4444}, + {DRM_FORMAT_RGBA4444, PIXEL_FMT_RGBA_4444}, {DRM_FORMAT_RGBX4444, PIXEL_FMT_RGBX_4444}, + {DRM_FORMAT_BGRX5551, PIXEL_FMT_BGRX_5551}, {DRM_FORMAT_BGRA5551, PIXEL_FMT_BGRA_5551}, + {DRM_FORMAT_BGRX8888, PIXEL_FMT_BGRX_8888}, {DRM_FORMAT_BGRA8888, PIXEL_FMT_BGRA_8888}, + {DRM_FORMAT_NV12, PIXEL_FMT_YCBCR_420_SP}, {DRM_FORMAT_NV21, PIXEL_FMT_YCRCB_420_SP}, + {DRM_FORMAT_YUV420, PIXEL_FMT_YCBCR_420_P}, {DRM_FORMAT_YVU420, PIXEL_FMT_YCRCB_420_P}, + {DRM_FORMAT_NV16, PIXEL_FMT_YCBCR_422_SP}, {DRM_FORMAT_NV61, PIXEL_FMT_YCRCB_422_SP}, + {DRM_FORMAT_YUV422, PIXEL_FMT_YCBCR_422_P}, {DRM_FORMAT_YVU422, PIXEL_FMT_YCRCB_422_P}, + }; + uint32_t fmtOut = 0; + for (uint32_t i = 0; i < sizeof(convertTable) / sizeof(convertTable[0]); i++) { + if (convertTable[i].pixFormat == fmtIn) { + fmtOut = convertTable[i].drmFormat; + } + } + DISPLAY_DEBUGLOG("fmtIn %{public}d : %{public}s, outFmt %{public}d : %{public}s", fmtIn, GetPixelFmtStr(fmtIn), fmtOut, + GetDrmFmtStr(fmtOut)); + return fmtOut; +} + +static uint64_t ConvertUsageToGbm(uint64_t inUsage) +{ + uint64_t outUsage = GBM_BO_USE_TEXTURING; + if (inUsage & HBM_USE_CPU_READ) { + outUsage |= GBM_BO_USE_SW_READ_OFTEN; + } + if (inUsage & HBM_USE_CPU_WRITE) { + outUsage |= GBM_BO_USE_SW_WRITE_OFTEN; + } + DISPLAY_DEBUGLOG("outUsage 0x%{public}" PRIx64 "", outUsage); + return outUsage; +} + +static int32_t InitGbmDevice(const char *drmFile, GrallocManager *grallocManager) +{ + DISPLAY_DEBUGLOG(); + if (grallocManager->gbmDevice == NULL) { + char path[PATH_MAX] = {0}; + if (realpath(drmFile, path) == NULL) { + DISPLAY_LOGE(" drm File : %{public}s is not a realpath, errno: %{public}s", drmFile, strerror(errno)); + return DISPLAY_PARAM_ERR; + } + int drmFd = open(path, O_RDWR); + if (drmFd < 0) { + DISPLAY_LOGE("drm file:%{public}s open failed %{public}s", drmFile, strerror(errno)); + return DISPLAY_FD_ERR; + } + /* + if (WaylandDrmAuth(drmFd) != AUTH_SCUCCESS) { + DISPLAY_LOGE("drm authentication failed, may have no permission to allocate memory"); + } + */ + drmDropMaster(drmFd); + struct gbm_device *gbmDevice = hdi_gbm_create_device(drmFd); + grallocManager->drmFd = drmFd; + if (gbmDevice == NULL) { + close(drmFd); + grallocManager->drmFd = -1; + DISPLAY_LOGE("gbm device create failed"); + return DISPLAY_FAILURE; + } + grallocManager->gbmDevice = gbmDevice; + grallocManager->drmFd = drmFd; + DListHeadInit(&grallocManager->gbmBoHead); + } + return DISPLAY_SUCCESS; +} + +static void DeInitGbmDevice(GrallocManager *grallocManager) +{ + DISPLAY_DEBUGLOG(); + hdi_gbm_device_destroy(grallocManager->gbmDevice); + if (grallocManager->drmFd > 0) { + close(grallocManager->drmFd); + grallocManager->drmFd = -1; + } + grallocManager->gbmDevice = NULL; +} + +static int32_t DmaBufferSync(const BufferHandle *handle, bool start) +{ + DISPLAY_DEBUGLOG(); + struct dma_buf_sync syncPrm; + errno_t eok = memset_s(&syncPrm, sizeof(syncPrm), 0, sizeof(syncPrm)); + DISPLAY_CHK_RETURN((eok != EOK), DISPLAY_PARAM_ERR, DISPLAY_LOGE("dma buffer sync memset_s failed")); + + if (handle->usage & HBM_USE_CPU_WRITE) { + syncPrm.flags |= DMA_BUF_SYNC_WRITE; + } + + if (handle->usage & HBM_USE_CPU_READ) { + syncPrm.flags |= DMA_BUF_SYNC_READ; + } + + if (start) { + syncPrm.flags |= DMA_BUF_SYNC_START; + } else { + syncPrm.flags |= DMA_BUF_SYNC_END; + } + int retry = 6; + int ret; + do { + ret = ioctl(handle->fd, DMA_BUF_IOCTL_SYNC, &syncPrm); + } while ((retry--) && (ret != -EAGAIN) && (ret != -EINTR)); + + if (ret < 0) { + DISPLAY_LOGE("sync failed"); + return DISPLAY_SYS_BUSY; + } + return DISPLAY_SUCCESS; +} + +static void InitBufferHandle(struct gbm_bo *bo, int fd, const AllocInfo *info, PriBufferHandle *buffer) +{ + BufferHandle *bufferHandle = &(buffer->hdl); + bufferHandle->fd = fd; + bufferHandle->reserveFds = 0; + bufferHandle->reserveInts = 0; + bufferHandle->stride = hdi_gbm_bo_get_stride(bo); + bufferHandle->width = hdi_gbm_bo_get_width(bo); + bufferHandle->height = hdi_gbm_bo_get_height(bo); + bufferHandle->usage = info->usage; + bufferHandle->format = info->format; + bufferHandle->virAddr = NULL; + bufferHandle->size = hdi_gbm_bo_get_stride(bo) * hdi_gbm_bo_get_height(bo); +} + +int32_t GbmAllocMem(const AllocInfo *info, BufferHandle **buffer) +{ + DISPLAY_CHK_RETURN((info == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("info is null")); + DISPLAY_CHK_RETURN((buffer == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("buffer is null")); + PriBufferHandle *priBuffer = NULL; + uint32_t drmFmt = ConvertFormatToDrm(info->format); + DISPLAY_CHK_RETURN((drmFmt == INVALID_PIXEL_FMT), DISPLAY_NOT_SUPPORT, + DISPLAY_LOGE("format %{public}d can not support", info->format)); + DISPLAY_DEBUGLOG("requeset width %{public}d, heigt %{public}d, format %{public}d", + info->width, info->height, drmFmt); + + GRALLOC_LOCK(); + GrallocManager *grallocManager = GetGrallocManager(); + DISPLAY_CHK_RETURN((grallocManager == NULL), DISPLAY_PARAM_ERR, DISPLAY_LOGE("gralloc manager failed"); + GRALLOC_UNLOCK()); + struct gbm_bo *bo = + hdi_gbm_bo_create(grallocManager->gbmDevice, info->width, info->height, drmFmt, ConvertUsageToGbm(info->usage)); + DISPLAY_CHK_RETURN((bo == NULL), DISPLAY_NOMEM, DISPLAY_LOGE("gbm create bo failed"); GRALLOC_UNLOCK()); + + int fd = hdi_gbm_bo_get_fd(bo); + DISPLAY_CHK_RETURN((fd < 0), DISPLAY_FD_ERR, DISPLAY_LOGE("gbm can not get fd"); hdi_gbm_bo_destroy(bo); \ + GRALLOC_UNLOCK()); + + priBuffer = (PriBufferHandle *)malloc(sizeof(PriBufferHandle)); + DISPLAY_CHK_RETURN((priBuffer == NULL), DISPLAY_NULL_PTR, DISPLAY_LOGE("bufferhandle malloc failed"); goto error); + + errno_t eok = memset_s(priBuffer, sizeof(PriBufferHandle), 0, sizeof(PriBufferHandle)); + if (eok != EOK) { + DISPLAY_LOGE("memset_s failed"); + } + DISPLAY_CHK_RETURN((eok != EOK), DISPLAY_PARAM_ERR, DISPLAY_LOGE("memset_s failed"); goto error); + + InitBufferHandle(bo, fd, info, priBuffer); + *buffer = &priBuffer->hdl; + hdi_gbm_bo_destroy(bo); + GRALLOC_UNLOCK(); + return DISPLAY_SUCCESS; +error: + close(fd); + hdi_gbm_bo_destroy(bo); + if (priBuffer != NULL) { + free(priBuffer); + } + GRALLOC_UNLOCK(); + return DISPLAY_FAILURE; +} + +static void CloseBufferHandle(BufferHandle *handle) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((handle == NULL), DISPLAY_LOGE("buffer is null")); + if (handle->fd >= 0) { + close(handle->fd); + handle->fd = -1; + } + const uint32_t reserveFds = handle->reserveFds; + for (uint32_t i = 0; i < reserveFds; i++) { + if (handle->reserve[i] >= 0) { + close(handle->reserve[i]); + handle->reserve[i] = -1; + } + } +} + +void GbmFreeMem(BufferHandle *buffer) +{ + DISPLAY_DEBUGLOG(); + DISPLAY_CHK_RETURN_NOT_VALUE((buffer == NULL), DISPLAY_LOGE("buffer is null")); + if ((buffer->virAddr != NULL) && (GbmUnmap(buffer) != DISPLAY_SUCCESS)) { + DISPLAY_LOGE("freeMem unmap buffer failed"); + } + CloseBufferHandle(buffer); + free(buffer); +} + +void *GbmMmap(BufferHandle *buffer) +{ + void *virAddr = NULL; + DISPLAY_DEBUGLOG(); + if (buffer == NULL) { + DISPLAY_LOGE("gbmmap the buffer handle is NULL"); + return NULL; + } + if (buffer->virAddr != NULL) { + DISPLAY_DEBUGLOG("the buffer has virtual addr"); + return buffer->virAddr; + } + virAddr = mmap(NULL, buffer->size, PROT_READ | PROT_WRITE, MAP_SHARED, buffer->fd, 0); + if (virAddr == MAP_FAILED) { + DISPLAY_LOGE("mmap failed errno %{public}s, fd : %{public}d", strerror(errno), buffer->fd); + } + buffer->virAddr = virAddr; + return virAddr; +} + +int32_t GbmUnmap(BufferHandle *buffer) +{ + DISPLAY_DEBUGLOG(); + if (buffer == NULL) { + DISPLAY_LOGE("gbmumap the buffer handle is null"); + return DISPLAY_NULL_PTR; + } + + if (buffer->virAddr == NULL) { + DISPLAY_LOGE("virAddr is NULL , has not map the buffer"); + return DISPLAY_PARAM_ERR; + } + int ret = munmap(buffer->virAddr, buffer->size); + if (ret != 0) { + DISPLAY_LOGE("munmap failed err: %{public}s", strerror(errno)); + return DISPLAY_FAILURE; + } + buffer->virAddr = NULL; + return DISPLAY_SUCCESS; +} + +int32_t GbmInvalidateCache(BufferHandle *buffer) +{ + DISPLAY_DEBUGLOG(); + return DmaBufferSync(buffer, true); +} + +int32_t GbmFlushCache(BufferHandle *buffer) +{ + DISPLAY_DEBUGLOG(); + return DmaBufferSync(buffer, false); +} + +int32_t GbmGrallocUninitialize(void) +{ + DISPLAY_DEBUGLOG(); + GRALLOC_LOCK(); + GrallocManager *grallocManager = GetGrallocManager(); + DISPLAY_CHK_RETURN((grallocManager == NULL), DISPLAY_PARAM_ERR, DISPLAY_LOGE("gralloc manager failed"); \ + GRALLOC_UNLOCK()); + grallocManager->referCount--; + if (grallocManager->referCount < 0) { + DeInitGbmDevice(grallocManager); + free(g_grallocManager); + g_grallocManager = NULL; + } + GRALLOC_UNLOCK(); + return DISPLAY_SUCCESS; +} + +int32_t GbmGrallocInitialize(void) +{ + DISPLAY_DEBUGLOG(); + GRALLOC_LOCK(); + GrallocManager *grallocManager = GetGrallocManager(); + DISPLAY_CHK_RETURN((grallocManager == NULL), DISPLAY_PARAM_ERR, DISPLAY_LOGE("gralloc manager failed"); \ + GRALLOC_UNLOCK()); + int ret = InitGbmDevice(g_drmFileNode, grallocManager); + DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), ret, DISPLAY_LOGE("gralloc manager failed"); GRALLOC_UNLOCK()); + grallocManager->referCount++; + GRALLOC_UNLOCK(); + return DISPLAY_SUCCESS; +} \ No newline at end of file diff --git a/hardware/display/src/display_gralloc/display_gralloc_gbm.h b/hardware/display/src/display_gralloc/display_gralloc_gbm.h new file mode 100644 index 0000000000000000000000000000000000000000..c41252fe6bda23663f1c09c358f03c58919d0b56 --- /dev/null +++ b/hardware/display/src/display_gralloc/display_gralloc_gbm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef DISPLAY_GRALLOC_GBM_H +#define DISPLAY_GRALLOC_GBM_H +#include "display_type.h" +#include "hdf_dlist.h" +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + struct gbm_device *gbmDevice; + int drmFd; + struct DListHead gbmBoHead; + int32_t referCount; +} GrallocManager; + +typedef struct { + struct DListHead entry; + struct gbm_bo *bo; + int fd; +} GbmBoList; + +int32_t GbmAllocMem(const AllocInfo *info, BufferHandle **buffer); +void GbmFreeMem(BufferHandle *buffer); +void *GbmMmap(BufferHandle *buffer); +int32_t GbmUnmap(BufferHandle *buffer); +int32_t GbmInvalidateCache(BufferHandle *buffer); +int32_t GbmFlushCache(BufferHandle *buffer); +int32_t GbmGrallocUninitialize(void); +int32_t GbmGrallocInitialize(void); + +#ifdef GRALLOC_LOCK_DEBUG +#define GRALLOC_LOCK(format, ...) \ + do { \ + HDF_LOGE("[%{public}s@%{public}s:%{public}d]" format "\n", __FUNCTION__, __FILE__, __LINE__, ##__VA_ARGS__); \ + pthread_mutex_lock(&g_lock); \ + } while (0) + +#define GRALLOC_UNLOCK(format, ...) \ + do { \ + HDF_LOGE("[%{public}s@%{public}s:%{public}d]" format "\n", __FUNCTION__, __FILE__, __LINE__, ##__VA_ARGS__); \ + pthread_mutex_unlock(&g_lock); \ + } while (0) +#else +#define GRALLOC_LOCK(format, ...) \ + do { \ + pthread_mutex_lock(&g_lock); \ + } while (0) + +#define GRALLOC_UNLOCK(format, ...) \ + do { \ + pthread_mutex_unlock(&g_lock); \ + } while (0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // DISPLAY_GRALLOC_GBM_H diff --git a/hardware/display/src/display_gralloc/hi_gbm.c b/hardware/display/src/display_gralloc/hi_gbm.c new file mode 100644 index 0000000000000000000000000000000000000000..0c3c790c3668cb76116b84577afcd6a38e309b4d --- /dev/null +++ b/hardware/display/src/display_gralloc/hi_gbm.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hi_gbm.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "display_common.h" +#include "hi_gbm_internal.h" +#ifdef ROCKCHIP_CMA +#define ROCKCHIP_BO_CONTIG (1 << 0) +#endif + +typedef struct { + uint32_t numPlanes; + uint32_t radio[MAX_PLANES]; +} PlaneLayoutInfo; + +typedef struct { + uint32_t format; + uint32_t bitsPerPixel; // bits per pixel for first plane + const PlaneLayoutInfo *planes; +} FormatInfo; + +static const PlaneLayoutInfo g_yuv420SPLayout = { + .numPlanes = 2, + .radio = { 4, 2 }, +}; + +static const PlaneLayoutInfo g_yuv420PLayout = { + .numPlanes = 3, + .radio = { 4, 1, 1 }, +}; + +static const PlaneLayoutInfo g_yuv422SPLayout = { + .numPlanes = 2, + .radio = { 4, 4 }, +}; + +static const PlaneLayoutInfo g_yuv422PLayout = { + .numPlanes = 3, + .radio = { 4, 2, 2 }, +}; + +static const FormatInfo *GetFormatInfo(uint32_t format) +{ + static const FormatInfo fmtInfos[] = { + {DRM_FORMAT_RGBX8888, 32, NULL}, {DRM_FORMAT_RGBA8888, 32, NULL}, + {DRM_FORMAT_BGRX8888, 32, NULL}, {DRM_FORMAT_BGRA8888, 32, NULL}, + {DRM_FORMAT_RGB888, 24, NULL}, {DRM_FORMAT_RGB565, 16, NULL}, + {DRM_FORMAT_BGRX4444, 16, NULL}, {DRM_FORMAT_BGRA4444, 16, NULL}, + {DRM_FORMAT_RGBA4444, 16, NULL}, {DRM_FORMAT_RGBX4444, 16, NULL}, + {DRM_FORMAT_BGRX5551, 16, NULL}, {DRM_FORMAT_BGRA5551, 16, NULL}, + {DRM_FORMAT_NV12, 8, &g_yuv420SPLayout}, {DRM_FORMAT_NV21, 8, &g_yuv420SPLayout}, + {DRM_FORMAT_NV16, 8, &g_yuv422SPLayout}, {DRM_FORMAT_NV61, 8, &g_yuv422SPLayout}, + {DRM_FORMAT_YUV420, 8, &g_yuv420PLayout}, {DRM_FORMAT_YVU420, 8, &g_yuv420PLayout}, + {DRM_FORMAT_YUV422, 8, &g_yuv422PLayout}, {DRM_FORMAT_YVU422, 8, &g_yuv422PLayout}, + }; + + for (uint32_t i = 0; i < sizeof(fmtInfos) / sizeof(FormatInfo); i++) { + if (fmtInfos[i].format == format) { + return &fmtInfos[i]; + } + } + DISPLAY_LOGE("the format can not support"); + return NULL; +} + +void InitGbmBo(struct gbm_bo *bo, const struct drm_mode_create_dumb *dumb) +{ + DISPLAY_CHK_RETURN_NOT_VALUE((dumb == NULL), DISPLAY_LOGE("dumb is null")); + DISPLAY_CHK_RETURN_NOT_VALUE((bo == NULL), DISPLAY_LOGE("bo is null")); + bo->stride = dumb->pitch; + bo->size = dumb->size; + bo->handle = dumb->handle; +} + +static uint32_t AdjustStrideFromFormat(uint32_t format, uint32_t height) +{ + uint32_t tmpHeight = height; + const FormatInfo *fmtInfo = GetFormatInfo(format); + if ((fmtInfo != NULL) && (fmtInfo->planes != NULL)) { + uint32_t sum = fmtInfo->planes->radio[0]; + for (uint32_t i = 1; (i < fmtInfo->planes->numPlanes) && (i < MAX_PLANES); i++) { + sum += fmtInfo->planes->radio[i]; + } + if (sum > 0) { + tmpHeight = DIV_ROUND_UP((height * sum), fmtInfo->planes->radio[0]); + } + DISPLAY_DEBUGLOG("height adjust to : %{public}d", tmpHeight); + } + return tmpHeight; +} + +struct gbm_bo *hdi_gbm_bo_create(struct gbm_device *gbm, uint32_t width, uint32_t height, uint32_t format, + uint32_t usage) +{ + DISPLAY_UNUSED(usage); + int ret; + struct gbm_bo *bo; + struct drm_mode_create_dumb dumb = { 0 }; + const FormatInfo *fmtInfo = GetFormatInfo(format); + DISPLAY_CHK_RETURN((fmtInfo == NULL), NULL, DISPLAY_LOGE("formt: 0x%{public}x can not get layout info", format)); + bo = (struct gbm_bo *)calloc(1, sizeof(struct gbm_bo)); + DISPLAY_CHK_RETURN((bo == NULL), NULL, DISPLAY_LOGE("gbm bo create fialed no memery")); + (void)memset_s(bo, sizeof(struct gbm_bo), 0, sizeof(struct gbm_bo)); + bo->width = width; + bo->height = height; + bo->gbm = gbm; + bo->format = format; + // init create_dumb + dumb.height = ALIGN_UP(height, HEIGHT_ALIGN); + dumb.width = ALIGN_UP(AdjustStrideFromFormat(format, width), WIDTH_ALIGN); + dumb.flags = 0; + dumb.bpp = fmtInfo->bitsPerPixel; + ret = drmIoctl(gbm->fd, DRM_IOCTL_MODE_CREATE_DUMB, &dumb); + DISPLAY_LOGI("fmt 0x%{public}x create dumb width: %{public}d height: %{public}d bpp: %{public}u pitch %{public}d " + "size %{public}llu", + format, dumb.width, dumb.height, dumb.bpp, dumb.pitch, dumb.size); + DISPLAY_CHK_RETURN((ret != 0), NULL, DISPLAY_LOGE("DRM_IOCTL_MODE_CREATE_DUMB failed errno %{public}d", errno)); + InitGbmBo(bo, &dumb); + DISPLAY_LOGI( + "fmt 0x%{public}x create dumb width: %{public}d height: %{public}d stride %{public}d size %{public}u", format, + bo->width, bo->height, bo->stride, bo->size); + return bo; +} + +struct gbm_device *hdi_gbm_create_device(int fd) +{ + struct gbm_device *gbm; + gbm = (struct gbm_device *)calloc(1, sizeof(struct gbm_device)); + DISPLAY_CHK_RETURN((gbm == NULL), NULL, DISPLAY_LOGE("memory calloc failed")); + gbm->fd = fd; + return gbm; +} + +void hdi_gbm_device_destroy(struct gbm_device *gbm) +{ + free(gbm); +} + +uint32_t hdi_gbm_bo_get_stride(struct gbm_bo *bo) +{ + DISPLAY_CHK_RETURN((bo == NULL), 0, DISPLAY_LOGE("the bo is null")); + return bo->stride; +} + +uint32_t hdi_gbm_bo_get_width(struct gbm_bo *bo) +{ + DISPLAY_CHK_RETURN((bo == NULL), 0, DISPLAY_LOGE("the bo is null")); + return bo->width; +} + +uint32_t hdi_gbm_bo_get_height(struct gbm_bo *bo) +{ + DISPLAY_CHK_RETURN((bo == NULL), 0, DISPLAY_LOGE("the bo is null")); + return bo->height; +} + +void hdi_gbm_bo_destroy(struct gbm_bo *bo) +{ + int ret; + DISPLAY_CHK_RETURN_NOT_VALUE((bo == NULL), DISPLAY_LOGE("the bo is null")); + struct drm_mode_destroy_dumb dumb = { 0 }; + dumb.handle = bo->handle; + ret = drmIoctl(bo->gbm->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &dumb); + DISPLAY_CHK_RETURN_NOT_VALUE((ret), DISPLAY_LOGE("dumb buffer destroy failed errno %{public}d", errno)); + free(bo); +} + +int hdi_gbm_bo_get_fd(struct gbm_bo *bo) +{ + int fd, ret; + ret = drmPrimeHandleToFD(bo->gbm->fd, bo->handle, DRM_CLOEXEC | DRM_RDWR, &fd); + DISPLAY_CHK_RETURN((ret), -1, + DISPLAY_LOGE("drmPrimeHandleToFD failed ret: %{public}d errno: %{public}d", ret, errno)); + return fd; +} diff --git a/hardware/display/src/display_gralloc/hi_gbm.h b/hardware/display/src/display_gralloc/hi_gbm.h new file mode 100644 index 0000000000000000000000000000000000000000..906e286949d85c6fafb5fed7e5b14e8b9473c431 --- /dev/null +++ b/hardware/display/src/display_gralloc/hi_gbm.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HI_GBM_H +#define HI_GBM_H +#include + +#if defined(__cplusplus) +extern "C" { +#endif + +struct gbm_device; +struct gbm_bo; + +enum gbm_bo_flags { + /* * + * Buffer is going to be presented to the screen using an API such as KMS + */ + GBM_BO_USE_SCANOUT = (1 << 0), + /* * + * Buffer is going to be used as cursor + */ + GBM_BO_USE_CURSOR = (1 << 1), + /* * + * Deprecated + */ + GBM_BO_USE_CURSOR_64X64 = GBM_BO_USE_CURSOR, + /* * + * Buffer is to be used for rendering - for example it is going to be used + * as the storage for a color buffer + */ + GBM_BO_USE_RENDERING = (1 << 2), + /* * + * Deprecated + */ + GBM_BO_USE_WRITE = (1 << 3), + /* * + * Buffer is guaranteed to be laid out linearly in memory. That is, the + * buffer is laid out as an array with 'height' blocks, each block with + * length 'stride'. Each stride is in the same order as the rows of the + * buffer. This is intended to be used with buffers that will be accessed + * via dma-buf mmap(). + */ + GBM_BO_USE_LINEAR = (1 << 4), + /* * + * The buffer will be used as a texture that will be sampled from. + */ + GBM_BO_USE_TEXTURING = (1 << 5), + /* * + * The buffer will be written to by a camera subsystem. + */ + GBM_BO_USE_CAMERA_WRITE = (1 << 6), + /* * + * The buffer will be read from by a camera subsystem. + */ + GBM_BO_USE_CAMERA_READ = (1 << 7), + /* * + * Buffer inaccessible to unprivileged users. + */ + GBM_BO_USE_PROTECTED = (1 << 8), + /* * + * These flags specify the frequency of software access. These flags do not + * guarantee the buffer is linear, but do guarantee gbm_bo_map(..) will + * present a linear view. + */ + GBM_BO_USE_SW_READ_OFTEN = (1 << 9), + GBM_BO_USE_SW_READ_RARELY = (1 << 10), + GBM_BO_USE_SW_WRITE_OFTEN = (1 << 11), + GBM_BO_USE_SW_WRITE_RARELY = (1 << 12), + /* * + * The buffer will be written by a video decode accelerator. + */ + GBM_BO_USE_HW_VIDEO_DECODER = (1 << 13), +}; + +struct gbm_device *hdi_gbm_create_device(int fd); +void hdi_gbm_device_destroy(struct gbm_device *gbm); +struct gbm_bo *hdi_gbm_bo_create(struct gbm_device *gbm, uint32_t width, uint32_t height, + uint32_t format, uint32_t usage); +uint32_t hdi_gbm_bo_get_stride(struct gbm_bo *bo); +uint32_t hdi_gbm_bo_get_width(struct gbm_bo *bo); +uint32_t hdi_gbm_bo_get_height(struct gbm_bo *bo); +void hdi_gbm_bo_destroy(struct gbm_bo *bo); +int hdi_gbm_bo_get_fd(struct gbm_bo *bo); + +#if defined(__cplusplus) +} +#endif +#endif // HI_GBM_H diff --git a/hardware/display/src/display_gralloc/hi_gbm_internal.h b/hardware/display/src/display_gralloc/hi_gbm_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..3155bb669334833f45da03be5db37f6b47d59653 --- /dev/null +++ b/hardware/display/src/display_gralloc/hi_gbm_internal.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HI_GBM_INTERNEL_H +#define HI_GBM_INTERNEL_H + +#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) +#define ALIGN_UP(x, a) ((((x) + ((a)-1)) / (a)) * (a)) +#define HEIGHT_ALIGN 2U +#define WIDTH_ALIGN 8U + +#define MAX_PLANES 3 + +struct gbm_device { + int fd; +}; + +struct gbm_bo { + struct gbm_device *gbm; + uint32_t width; + uint32_t height; + uint32_t format; + uint32_t handle; + uint32_t stride; + uint32_t size; +}; + +#endif // HI_GBM_INTERNEL_H \ No newline at end of file diff --git a/hardware/display/src/display_gralloc/hisilicon_drm.h b/hardware/display/src/display_gralloc/hisilicon_drm.h new file mode 100644 index 0000000000000000000000000000000000000000..eed389e88acc3154ba29a3d0010f3a463b18f7b1 --- /dev/null +++ b/hardware/display/src/display_gralloc/hisilicon_drm.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef HISILICON_DRM_H +#define HISILICON_DRM_H + +#include "drm.h" + +#if defined(__cplusplus) +extern "C" { +#endif +#define DRM_HISILICON_GEM_FD_TO_PHYADDR 0x1 + +struct DrmHisiliconPhyaddr { + /* * return the physical address */ + __u64 phyaddr; + /* * dmabuf file descriptor */ + __s32 fd; +}; + +#define DRM_IOCTL_HISILICON_GEM_FD_TO_PHYADDR \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_HISILICON_GEM_FD_TO_PHYADDR, struct DrmHisiliconPhyaddr) + +#if defined(__cplusplus) +} +#endif + +#endif // HISILICON_DRM_H diff --git a/hardware/display/src/display_gralloc/wayland_drm_auth_client.c b/hardware/display/src/display_gralloc/wayland_drm_auth_client.c new file mode 100644 index 0000000000000000000000000000000000000000..d5b1cda395ed9826bc310d0004f96548b5836b5c --- /dev/null +++ b/hardware/display/src/display_gralloc/wayland_drm_auth_client.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "wayland_drm_auth_client.h" +#include +#include +#include "xf86drm.h" +#include "wayland-client.h" +#include "drm-auth-client-protocol.h" +#include "display_common.h" + +typedef struct { + struct wl_display *display; + struct wl_registry *registry; + struct wl_drm_auth *drmAuth; + enum wl_drm_auth_status authStatus; +} WaylandDisplay; + +const char *AUTH_INTERFACE_NAME = "wl_drm_auth"; + +static void AuthenticationStatus(void *data, struct wl_drm_auth *wlDrmAuth, uint32_t status) +{ + (void)wlDrmAuth; + DISPLAY_DEBUGLOG("AuthenticationStatus the status %{public}d", status); + WaylandDisplay *display = data; + display->authStatus = status; +} + +static const struct wl_drm_auth_listener g_drmAuthListener = { AuthenticationStatus }; + +static void RegistryHandleGlobal(void *data, struct wl_registry *registry, uint32_t id, const char *interface, + uint32_t version) +{ + WaylandDisplay *display = data; + DISPLAY_DEBUGLOG("interface global : %{public}s", interface); + if (strcmp(interface, wl_drm_auth_interface.name) == 0) { + display->drmAuth = wl_registry_bind(registry, id, &wl_drm_auth_interface, 1); + wl_drm_auth_add_listener(display->drmAuth, &g_drmAuthListener, display); + } +} + +static void RegistryHandleGlobalRemove(void *data, struct wl_registry *registry, uint32_t name) +{ + DISPLAY_DEBUGLOG("RegistryHandleGlobalRemove %{publuc}d name ", name); +} + +static const struct wl_registry_listener g_registrListener = { RegistryHandleGlobal, RegistryHandleGlobalRemove }; + +void DeInitWaylandClient(WaylandDisplay *display) +{ + DISPLAY_DEBUGLOG("DeInitWaylandClient"); + DISPLAY_CHK_RETURN_NOT_VALUE((display == NULL), DISPLAY_DEBUGLOG("display is NULL")); + if (display->registry != NULL) { + wl_registry_destroy(display->registry); + } + + if (display->display != NULL) { + wl_display_flush(display->display); + wl_display_disconnect(display->display); + } + free(display); +} + +WaylandDisplay *InitWaylandClient(void) +{ + WaylandDisplay *dsp; + int ret; + dsp = calloc(1, sizeof(WaylandDisplay)); + DISPLAY_CHK_RETURN((dsp == NULL), NULL, DISPLAY_LOGE("can not alloc memory errno : %{public}d", errno)); + dsp->display = wl_display_connect(NULL); + DISPLAY_CHK_RETURN((dsp->display == NULL), NULL, DISPLAY_LOGE("display connect failed, errno: %{public}d", errno); + DeInitWaylandClient(dsp)); + dsp->registry = wl_display_get_registry(dsp->display); + DISPLAY_CHK_RETURN((dsp->registry == NULL), NULL, DISPLAY_LOGE("can not get registry"); + DeInitWaylandClient(dsp)); + ret = wl_registry_add_listener(dsp->registry, &g_registrListener, dsp); + DISPLAY_CHK_RETURN((ret < 0), NULL, DISPLAY_LOGE("add listener failed")); + wl_display_roundtrip(dsp->display); // for get registry + wl_display_roundtrip(dsp->display); // for the listener will bind the service + return dsp; +} + +int32_t WaylandDrmAuth(int drmFd) +{ + WaylandDisplay *dsp; + drm_magic_t magic; + int ret; + dsp = InitWaylandClient(); + DISPLAY_CHK_RETURN((dsp == NULL), AUTH_FAILED, DISPLAY_LOGE("init wayland client failed")); + ret = drmGetMagic(drmFd, &magic); + DISPLAY_CHK_RETURN((ret != 0), AUTH_FAILED, DISPLAY_LOGE("can not get magic")); + DISPLAY_CHK_RETURN((dsp->drmAuth == NULL), AUTH_FAILED, DISPLAY_LOGE("drm auth service no find")); + wl_drm_auth_authenticate(dsp->drmAuth, magic); + wl_display_roundtrip(dsp->display); // wait for authenticate status return + DISPLAY_DEBUGLOG("the status of authenticate is %{public}d", dsp->authStatus); + if (dsp->authStatus == WL_DRM_AUTH_STATUS_SUCCESS) { + ret = AUTH_SCUCCESS; + } + DeInitWaylandClient(dsp); + return ret; +} diff --git a/hardware/display/src/display_gralloc/wayland_drm_auth_client.h b/hardware/display/src/display_gralloc/wayland_drm_auth_client.h new file mode 100644 index 0000000000000000000000000000000000000000..69be0fa04193612989e7fb62f207faf385455bf6 --- /dev/null +++ b/hardware/display/src/display_gralloc/wayland_drm_auth_client.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WAYLAND_DRM_AUTH_CLIENT_H +#define WAYLAND_DRM_AUTH_CLIENT_H +#include + +typedef enum { + AUTH_SCUCCESS = 0, /* * authenticate sucess */ + AUTH_FAILED = 1 /* * authenticate failed */ +} AuthStatus; + +/* * + * @brief authenticate the drm fd + * + * it will connect to the wayland server, and will block to authenticate the drm fd, then disconnect the wayland + * + * @param display Indicates the pointer of wayland display + * + * @param drmFd Indicates the file descriptor of drm device + * + * @return Returns AUTH_SCUCCESS if the operation is successful else returns AUTH_FAILED + * otherwise. + * @since 1.0 + * @version 1.0 + */ +int32_t WaylandDrmAuth(int drmFd); + +#endif // WAYLAND_DRM_AUTH_CLIENT_H diff --git a/hardware/gpu/BUILD.gn b/hardware/gpu/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..b6da2d6ef2e1663fa092bfa3cda0d15a1380bf4b --- /dev/null +++ b/hardware/gpu/BUILD.gn @@ -0,0 +1,46 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import("//build/ohos.gni") +import("//build/ohos/ndk/ndk.gni") + +config("libmali-bifrost-g52-g2p0-ohos") { + include_dirs = [ "include" ] + cflags = [ + "-Wno-incompatible-pointer-types", + "-Werror", + "-Wimplicit-function-declaration", + "-Wno-error=unused-variable", + ] + cflags = [] +} + +ohos_prebuilt_shared_library("mali-bifrost-g52-g2p0-ohos") { + if (target_cpu == "arm") { + source = "lib/libmali-bifrost-g52-g2p0-ohos.so" + } else if (target_cpu == "arm64") { + source = "lib64/libmali-bifrost-g52-g2p0-wayland.so" + } + install_images = [ chipset_base_dir ] + subsystem_name = "hdf" + part_name = "display_device_driver" + install_enable = true + symlink_target_name = [ + "libEGL.so", + "libGLESv1.so", + "libGLESv2.so", + "libGLESv3.so", + "libmali.so.0", + "libmali.so.1", + ] +} diff --git a/hardware/gpu/include/gbm.h b/hardware/gpu/include/gbm.h new file mode 100644 index 0000000000000000000000000000000000000000..1e8bc46f881ddca09ad721e11ebd5a8055da0d9d --- /dev/null +++ b/hardware/gpu/include/gbm.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2021 Huawei Device Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _GBM_H_ +#define _GBM_H_ + +#define __GBM__ 1 + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * \file gbm.h + * \brief Generic Buffer Manager + */ + +struct gbm_device; +struct gbm_bo; +struct gbm_iSurface; + +/** + * \mainpage The Generic Buffer Manager + * + * This module provides an abstraction that the caller can use to request a + * buffer from the underlying memory management system for the platform. + * + * This allows the creation of portable code whilst still allowing access to + * the underlying memory manager. + */ + +/** + * Abstraction representing the handle to a buffer allocated by the + * manager + */ +union gbm_bo_handle { + void *ptr; + int32_t s32; + uint32_t u32; + int64_t s64; + uint64_t u64; +}; + +/** Format of the allocated buffer */ +enum gbm_bo_format { + /** RGB with 8 bits per channel in a 32 bit value */ + GBM_BO_FORMAT_XRGB8888, + /** ARGB with 8 bits per channel in a 32 bit value */ + GBM_BO_FORMAT_ARGB8888 +}; + + +/** + * The FourCC format codes are taken from the drm_fourcc.h definition, and + * re-namespaced. New GBM formats must not be added, unless they are + * identical ports from drm_fourcc. + */ +#define __gbm_fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ + ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) + +#define GBM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ + +/* color index */ +#define GBM_FORMAT_C8 __gbm_fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ + +/* 8 bpp Red */ +#define GBM_FORMAT_R8 __gbm_fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ + +/* 16 bpp RG */ +#define GBM_FORMAT_GR88 __gbm_fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ + +/* 8 bpp RGB */ +#define GBM_FORMAT_RGB332 __gbm_fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ +#define GBM_FORMAT_BGR233 __gbm_fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ + +/* 16 bpp RGB */ +#define GBM_FORMAT_XRGB4444 __gbm_fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ +#define GBM_FORMAT_XBGR4444 __gbm_fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ +#define GBM_FORMAT_RGBX4444 __gbm_fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ +#define GBM_FORMAT_BGRX4444 __gbm_fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ + +#define GBM_FORMAT_ARGB4444 __gbm_fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ +#define GBM_FORMAT_ABGR4444 __gbm_fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ +#define GBM_FORMAT_RGBA4444 __gbm_fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ +#define GBM_FORMAT_BGRA4444 __gbm_fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ + +#define GBM_FORMAT_XRGB1555 __gbm_fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ +#define GBM_FORMAT_XBGR1555 __gbm_fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ +#define GBM_FORMAT_RGBX5551 __gbm_fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ +#define GBM_FORMAT_BGRX5551 __gbm_fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ + +#define GBM_FORMAT_ARGB1555 __gbm_fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ +#define GBM_FORMAT_ABGR1555 __gbm_fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ +#define GBM_FORMAT_RGBA5551 __gbm_fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ +#define GBM_FORMAT_BGRA5551 __gbm_fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ + +#define GBM_FORMAT_RGB565 __gbm_fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ +#define GBM_FORMAT_BGR565 __gbm_fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ + +/* 24 bpp RGB */ +#define GBM_FORMAT_RGB888 __gbm_fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ +#define GBM_FORMAT_BGR888 __gbm_fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ + +/* 32 bpp RGB */ +#define GBM_FORMAT_XRGB8888 __gbm_fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ +#define GBM_FORMAT_XBGR8888 __gbm_fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ +#define GBM_FORMAT_RGBX8888 __gbm_fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ +#define GBM_FORMAT_BGRX8888 __gbm_fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ + +#define GBM_FORMAT_ARGB8888 __gbm_fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ +#define GBM_FORMAT_ABGR8888 __gbm_fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ +#define GBM_FORMAT_RGBA8888 __gbm_fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ +#define GBM_FORMAT_BGRA8888 __gbm_fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ + +#define GBM_FORMAT_XRGB2101010 __gbm_fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ +#define GBM_FORMAT_XBGR2101010 __gbm_fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ +#define GBM_FORMAT_RGBX1010102 __gbm_fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ +#define GBM_FORMAT_BGRX1010102 __gbm_fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ + +#define GBM_FORMAT_ARGB2101010 __gbm_fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ +#define GBM_FORMAT_ABGR2101010 __gbm_fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ +#define GBM_FORMAT_RGBA1010102 __gbm_fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ +#define GBM_FORMAT_BGRA1010102 __gbm_fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ + +/* packed YCbCr */ +#define GBM_FORMAT_YUYV __gbm_fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ +#define GBM_FORMAT_YVYU __gbm_fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ +#define GBM_FORMAT_UYVY __gbm_fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ +#define GBM_FORMAT_VYUY __gbm_fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ + +#define GBM_FORMAT_AYUV __gbm_fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ + +/* + * 2 plane YCbCr + * index 0 = Y plane, [7:0] Y + * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian + * or + * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian + */ +#define GBM_FORMAT_NV12 __gbm_fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define GBM_FORMAT_NV21 __gbm_fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define GBM_FORMAT_NV16 __gbm_fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define GBM_FORMAT_NV61 __gbm_fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ + +/* + * 3 plane YCbCr + * index 0: Y plane, [7:0] Y + * index 1: Cb plane, [7:0] Cb + * index 2: Cr plane, [7:0] Cr + * or + * index 1: Cr plane, [7:0] Cr + * index 2: Cb plane, [7:0] Cb + */ +#define GBM_FORMAT_YUV410 __gbm_fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ +#define GBM_FORMAT_YVU410 __gbm_fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ +#define GBM_FORMAT_YUV411 __gbm_fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ +#define GBM_FORMAT_YVU411 __gbm_fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ +#define GBM_FORMAT_YUV420 __gbm_fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ +#define GBM_FORMAT_YVU420 __gbm_fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ +#define GBM_FORMAT_YUV422 __gbm_fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ +#define GBM_FORMAT_YVU422 __gbm_fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ +#define GBM_FORMAT_YUV444 __gbm_fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ +#define GBM_FORMAT_YVU444 __gbm_fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ + + +/** + * Flags to indicate the intended use for the buffer - these are passed into + * gbm_bo_create(). The caller must set the union of all the flags that are + * appropriate + * + * \sa Use gbm_device_is_format_supported() to check if the combination of format + * and use flags are supported + */ +enum gbm_bo_flags { + /** + * Buffer is going to be presented to the screen using an API such as KMS + */ + GBM_BO_USE_SCANOUT = (1 << 0), + /** + * Buffer is going to be used as cursor + */ + GBM_BO_USE_CURSOR = (1 << 1), + /** + * Deprecated + */ + GBM_BO_USE_CURSOR_64X64 = GBM_BO_USE_CURSOR, + /** + * Buffer is to be used for rendering - for example it is going to be used + * as the storage for a color buffer + */ + GBM_BO_USE_RENDERING = (1 << 2), + /** + * Buffer can be used for gbm_bo_write. This is guaranteed to work + * with GBM_BO_USE_CURSOR, but may not work for other combinations. + */ + GBM_BO_USE_WRITE = (1 << 3), + /** + * Buffer is linear, i.e. not tiled. + */ + GBM_BO_USE_LINEAR = (1 << 4), +}; + +int gbm_device_get_fd(struct gbm_device *gbm); + +const char *gbm_device_get_backend_name(struct gbm_device *gbm); + +int gbm_device_is_format_supported(struct gbm_device *gbm, uint32_t format, uint32_t usage); + +int gbm_device_get_format_modifier_plane_count(struct gbm_device *gbm, uint32_t format, uint64_t modifier); + +void gbm_device_destroy(struct gbm_device *gbm); + +struct gbm_device *gbm_create_device(int fd); + +struct gbm_bo *gbm_bo_create(struct gbm_device *gbm, uint32_t width, uint32_t height, uint32_t format, uint32_t flags); + +struct gbm_bo *gbm_bo_create_with_modifiers(struct gbm_device *gbm, + uint32_t width, + uint32_t height, + uint32_t format, + const uint64_t *modifiers, + const unsigned int count); + +#define GBM_BO_IMPORT_WL_BUFFER 0x5501 +#define GBM_BO_IMPORT_EGL_IMAGE 0x5502 +#define GBM_BO_IMPORT_FD 0x5503 +#define GBM_BO_IMPORT_FD_MODIFIER 0x5504 + +struct gbm_import_fd_data { + int fd; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; +}; + +struct gbm_import_fd_modifier_data { + uint32_t width; + uint32_t height; + uint32_t format; + uint32_t num_fds; + int fds[4]; + int strides[4]; + int offsets[4]; + uint64_t modifier; +}; + +struct gbm_bo *bm_bo_import(struct gbm_device *gbm, uint32_t type, void *buffer, uint32_t usage); + +/** + * Flags to indicate the type of mapping for the buffer - these are + * passed into gbm_bo_map(). The caller must set the union of all the + * flags that are appropriate. + * + * These flags are independent of the GBM_BO_USE_* creation flags. However, + * mapping the buffer may require copying to/from a staging buffer. + * + * See also: pipe_transfer_usage + */ +enum gbm_bo_transfer_flags { + /** + * Buffer contents read back (or accessed directly) at transfer + * create time. + */ + GBM_BO_TRANSFER_READ = (1 << 0), + /** + * Buffer contents will be written back at unmap time + * (or modified as a result of being accessed directly). + */ + GBM_BO_TRANSFER_WRITE = (1 << 1), + /** + * Read/modify/write + */ + GBM_BO_TRANSFER_READ_WRITE = (GBM_BO_TRANSFER_READ | GBM_BO_TRANSFER_WRITE), +}; + +void *gbm_bo_map(struct gbm_bo *bo, + uint32_t x, uint32_t y, uint32_t width, uint32_t height, + uint32_t flags, uint32_t *stride, void **map_data); + +void gbm_bo_unmap(struct gbm_bo *bo, void *map_data); + +uint32_t gbm_bo_get_width(struct gbm_bo *bo); + +uint32_t gbm_bo_get_height(struct gbm_bo *bo); + +uint32_t gbm_bo_get_stride(struct gbm_bo *bo); + +uint32_t gbm_bo_get_stride_for_plane(struct gbm_bo *bo, int plane); + +uint32_t gbm_bo_get_format(struct gbm_bo *bo); + +uint32_t gbm_bo_get_bpp(struct gbm_bo *bo); + +uint32_t gbm_bo_get_offset(struct gbm_bo *bo, int plane); + +struct gbm_device *gbm_bo_get_device(struct gbm_bo *bo); + +union gbm_bo_handle gbm_bo_get_handle(struct gbm_bo *bo); + +int gbm_bo_get_fd(struct gbm_bo *bo); + +uint64_t gbm_bo_get_modifier(struct gbm_bo *bo); + +int gbm_bo_get_plane_count(struct gbm_bo *bo); + +union gbm_bo_handle gbm_bo_get_handle_for_plane(struct gbm_bo *bo, int plane); + +int gbm_bo_write(struct gbm_bo *bo, const void *buf, size_t count); + +void gbm_bo_set_user_data(struct gbm_bo *bo, void *data, void (*destroy_user_data)(struct gbm_bo *, void *)); + +void *gbm_bo_get_user_data(struct gbm_bo *bo); + +void gbm_bo_destroy(struct gbm_bo *bo); + +struct gbm_iSurface *gbm_iSurface_create(struct gbm_device *gbm, + uint32_t width, uint32_t height, + uint32_t format, uint32_t flags); + +struct gbm_iSurface *gbm_iSurface_create_with_modifiers(struct gbm_device *gbm, + uint32_t width, uint32_t height, + uint32_t format, + const uint64_t *modifiers, + const unsigned int count); + +struct gbm_bo *gbm_iSurface_lock_front_buffer(struct gbm_iSurface *iSurface); + +void gbm_iSurface_release_buffer(struct gbm_iSurface *iSurface, struct gbm_bo *bo); + +int gbm_iSurface_has_free_buffers(struct gbm_iSurface *iSurface); + +void gbm_iSurface_destroy(struct gbm_iSurface *iSurface); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/gpu/lib/libmali-bifrost-g52-g2p0-ohos.so b/hardware/gpu/lib/libmali-bifrost-g52-g2p0-ohos.so new file mode 100644 index 0000000000000000000000000000000000000000..58f435e31ab2cb655f0b0a6d7691b52606161000 Binary files /dev/null and b/hardware/gpu/lib/libmali-bifrost-g52-g2p0-ohos.so differ diff --git a/hardware/gpu/lib64/libmali-bifrost-g52-g2p0-wayland.so b/hardware/gpu/lib64/libmali-bifrost-g52-g2p0-wayland.so new file mode 100644 index 0000000000000000000000000000000000000000..fb647f46aeb1443ff0ea00845e37509392b6017b Binary files /dev/null and b/hardware/gpu/lib64/libmali-bifrost-g52-g2p0-wayland.so differ diff --git a/hardware/isp/BUILD.gn b/hardware/isp/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..2690b6e5df7d58a2753d8c1386f3bcb3f6ffecf3 --- /dev/null +++ b/hardware/isp/BUILD.gn @@ -0,0 +1,62 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +import("//build/ohos.gni") + +ISP_DIR = "//device/soc/rockchip/hardware/isp" + +ohos_prebuilt_shared_library("librkaiq") { + if (target_cpu == "arm") { + source = "$ISP_DIR/lib/librkaiq.z.so" + } else { + source = "$ISP_DIR/lib64/librkaiq.z.so" + } + install_images = [ chipset_base_dir ] + subsystem_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("gc8034_RK-CMK-8M-2-v1_CK8401") { + source = "$ISP_DIR/etc/iqfiles/gc8034_RK-CMK-8M-2-v1_CK8401.json" + relative_install_dir = "iqfiles" + install_images = [ chipset_base_dir ] + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("iqfil") { + source = "$ISP_DIR/etc/iqfil.json" + relative_install_dir = "" + install_images = [ chipset_base_dir ] + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_executable("ispserver") { + if (target_cpu == "arm") { + source = "$ISP_DIR/bin/ispserver" + } else { + source = "$ISP_DIR/bin64/ispserver" + } + install_images = [ chipset_base_dir ] + part_name = "rockchip_products" + install_enable = true +} + +group("isp") { + deps = [ + ":gc8034_RK-CMK-8M-2-v1_CK8401", + ":iqfil", + ":ispserver", + ":librkaiq", + ] +} diff --git a/hardware/isp/bin/ispserver b/hardware/isp/bin/ispserver new file mode 100644 index 0000000000000000000000000000000000000000..ed2444235148e77713aad68c79a4599215fc2772 Binary files /dev/null and b/hardware/isp/bin/ispserver differ diff --git a/hardware/isp/bin64/ispserver b/hardware/isp/bin64/ispserver new file mode 100644 index 0000000000000000000000000000000000000000..c59ad612fea6974e54ec6c6fa3aa34ac53e4c83b Binary files /dev/null and b/hardware/isp/bin64/ispserver differ diff --git a/hardware/isp/etc/iqfil.json b/hardware/isp/etc/iqfil.json new file mode 100644 index 0000000000000000000000000000000000000000..6d892a2b54a877e2676802749c9c4b79dc80e57e --- /dev/null +++ b/hardware/isp/etc/iqfil.json @@ -0,0 +1,4650 @@ +{ + "sensor_calib": { + "resolution": { + "width": 3264, + "height": 2448 + }, + "Gain2Reg": { + "GainMode": "EXPGAIN_MODE_LINEAR", + "GainRange": [1, 16, 64, 0, 1, 64, 1024], + "GainRange_len": 7 + }, + "Time2Reg": { + "fCoeff": [0, 0, 1, 0.5] + }, + "CISGainSet": { + "CISAgainRange": { + "Min": 1, + "Max": 16 + }, + "CISExtraAgainRange": { + "Min": 1, + "Max": 1 + }, + "CISDgainRange": { + "Min": 1, + "Max": 1 + }, + "CISIspDgainRange": { + "Min": 1, + "Max": 1 + }, + "CISHdrGainIndSetEn": 1 + }, + "CISTimeSet": { + "Linear": { + "CISTimeRegMin": 4, + "CISLinTimeRegMaxFac": { + "fCoeff": [1, 4] + }, + "CISTimeRegOdevity": { + "fCoeff": [1, 0] + } + }, + "Hdr": [{ + "name": "HDR_TWO_FRAME", + "CISTimeRegUnEqualEn": 1, + "CISTimeRegMin": 4, + "CISHdrTimeRegSumFac": { + "fCoeff": [1, 4] + }, + "CISTimeRegMax": { + "Coeff": [0, 0, 0] + }, + "CISTimeRegOdevity": { + "fCoeff": [1, 0] + } + }, { + "name": "HDR_THREE_FRAME", + "CISTimeRegUnEqualEn": 1, + "CISTimeRegMin": 4, + "CISHdrTimeRegSumFac": { + "fCoeff": [1, 4] + }, + "CISTimeRegMax": { + "Coeff": [0, 0, 0] + }, + "CISTimeRegOdevity": { + "fCoeff": [1, 0] + } + }] + }, + "CISHdrSet": { + "hdr_en": 0, + "hdr_mode": "RK_AIQ_ISP_HDR_MODE_2_LINE_HDR", + "line_mode": "RK_AIQ_SENSOR_HDR_LINE_MODE_STAGGER" + }, + "CISDcgSet": { + "Linear": { + "support_en": 0, + "dcg_optype": "RK_AIQ_OP_MODE_AUTO", + "dcg_mode": { + "Coeff": [0, 0, 0] + }, + "dcg_ratio": 1, + "sync_switch": 0, + "lcg2hcg_gain_th": 32, + "hcg2lcg_gain_th": 16 + }, + "Hdr": { + "support_en": 0, + "dcg_optype": "RK_AIQ_OP_MODE_AUTO", + "dcg_mode": { + "Coeff": [0, 0, 0] + }, + "dcg_ratio": 3.5, + "sync_switch": 1, + "lcg2hcg_gain_th": 32, + "hcg2lcg_gain_th": 16 + } + }, + "CISExpUpdate": { + "Linear": { + "time_update": 2, + "gain_update": 2, + "dcg_update": 2 + }, + "Hdr": { + "time_update": 2, + "gain_update": 2, + "dcg_update": 1 + } + }, + "CISMinFps": 10, + "CISFlip": 3 + }, + "module_calib": { + "sensor_module": { + "FNumber": 1.6, + "EFL": 5.2, + "LensT": 90, + "IRCutT": 90 + } + }, + "main_scene": [{ + "name": "normal", + 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"luma_sigma": [48, 56, 64, 80, 96, 80, 64, 56], + "hf_clip": [64, 96, 12, 16, 19, 16, 12, 0], + "local_sharp_strength": [128, 128, 128, 128, 128, 128, 128, 128] + }, + "kernel_para": { + "prefilter_coeff": [0.2042, 0.1238, 0.0751], + "GaussianFilter_coeff": [0.2042, 0.1238, 0.0751], + "hfBilateralFilter_coeff": [0.2042, 0.1238, 0.0751] + } + }], + "Tuning_ISO_len": 13 + }], + "Setting_len": 2 + } + } + } + }], + "sub_scene_len": 1 + }], + "main_scene_len": 1, + "uapi": [], + "uapi_len": 0, + "sys_static_cfg": { + "algoSwitch": { + "enable": 0, + "enable_algos": [], + "enable_algos_len": 0 + } + } +} \ No newline at end of file diff --git a/hardware/isp/lib/librkaiq.z.so b/hardware/isp/lib/librkaiq.z.so new file mode 100644 index 0000000000000000000000000000000000000000..1e0c605527c700a956590c94d43864d164714432 Binary files /dev/null and b/hardware/isp/lib/librkaiq.z.so differ diff --git a/hardware/isp/lib64/librkaiq.z.so b/hardware/isp/lib64/librkaiq.z.so new file mode 100644 index 0000000000000000000000000000000000000000..6a54322a23aae1482288894795f23f7086e32ec1 Binary files /dev/null and b/hardware/isp/lib64/librkaiq.z.so differ diff --git a/hardware/mpp/BUILD.gn b/hardware/mpp/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..17b48da92f7c8925f97c2b07da44bf1a67661dde --- /dev/null +++ b/hardware/mpp/BUILD.gn @@ -0,0 +1,30 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import("//build/ohos.gni") +import("//build/ohos/ndk/ndk.gni") + +ohos_prebuilt_shared_library("libmpp") { + if (target_cpu == "arm") { + source = "lib/librockchip_mpp.z.so" + } else { + source = "lib64/librockchip_mpp.so" + } + install_images = [ chipset_base_dir ] + part_name = "rockchip_products" + install_enable = true +} + +group("mpp") { + deps = [ ":libmpp" ] +} diff --git a/hardware/mpp/include/mpi_enc_utils.h b/hardware/mpp/include/mpi_enc_utils.h new file mode 100644 index 0000000000000000000000000000000000000000..751025008475c7bc7f6bdf3befa005fb074a0fc1 --- /dev/null +++ b/hardware/mpp/include/mpi_enc_utils.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPI_ENC_UTILS_H__ +#define __MPI_ENC_UTILS_H__ + +#include + +#include "rk_venc_cmd.h" + +typedef struct MpiEncTestArgs_t { + MppCodingType type; + MppFrameFormat format; + + RK_S32 width; + RK_S32 height; +} MpiEncTestArgs; + +typedef struct { + // global flow control flag + RK_U32 frm_eos; + RK_U32 pkt_eos; + RK_S32 frame_count; + RK_U64 stream_size; + + // base flow context + MppCtx ctx; + MppApi *mpi; + MppEncCfg cfg; + + // input / output + MppBufferGroup buf_grp; + MppBuffer pkt_buf; + MppEncSeiMode sei_mode; + MppEncHeaderMode header_mode; + + // paramter for resource malloc + RK_U32 width; + RK_U32 height; + RK_U32 hor_stride; + RK_U32 ver_stride; + MppFrameFormat fmt; + MppCodingType type; + RK_S32 num_frames; + + // resources + size_t frame_size; + + RK_U32 split_mode; + RK_U32 split_arg; + + // rate control runtime parameter + + RK_S32 fps_in_flex; + RK_S32 fps_in_den; + RK_S32 fps_in_num; + RK_S32 fps_out_flex; + RK_S32 fps_out_den; + RK_S32 fps_out_num; + RK_S32 bps; + RK_S32 bps_max; + RK_S32 bps_min; + RK_S32 rc_mode; + RK_S32 gop_mode; + RK_S32 gop_len; + RK_S32 vi_len; +} MpiEncTestData; + +int hal_mpp_get_sps(void *ctx, unsigned char *buf, size_t *buf_size); +int hal_mpp_encode(void *ctx, int dma_fd, unsigned char *buf, size_t *buf_size); + +void *hal_mpp_ctx_create(MpiEncTestArgs *args); +void hal_mpp_ctx_delete(void *ctx); + +#endif /* __MPI_ENC_UTILS_H__ */ diff --git a/hardware/mpp/include/mpp_allocator.h b/hardware/mpp/include/mpp_allocator.h new file mode 100755 index 0000000000000000000000000000000000000000..85cff8ca86ecfc8c7ca0692528c9fb79dd73779f --- /dev/null +++ b/hardware/mpp/include/mpp_allocator.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_ALLOCATOR_H__ +#define __MPP_ALLOCATOR_H__ + +#include "rk_type.h" +#include "mpp_buffer.h" + +typedef void *MppAllocator; + +typedef struct MppAllocatorCfg_t { + // input + size_t alignment; + RK_U32 flags; +} MppAllocatorCfg; + +typedef struct MppAllocatorApi_t { + RK_U32 size; + RK_U32 version; + + MPP_RET (*alloc)(MppAllocator allocator, MppBufferInfo *data); + MPP_RET (*free)(MppAllocator allocator, MppBufferInfo *data); + MPP_RET (*import)(MppAllocator allocator, MppBufferInfo *data); + MPP_RET (*release)(MppAllocator allocator, MppBufferInfo *data); + MPP_RET (*mmap)(MppAllocator allocator, MppBufferInfo *data); +} MppAllocatorApi; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_allocator_get(MppAllocator *allocator, + MppAllocatorApi **api, MppBufferType type); +MPP_RET mpp_allocator_put(MppAllocator *allocator); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_ALLOCATOR_H__ */ + diff --git a/hardware/mpp/include/mpp_buffer.h b/hardware/mpp/include/mpp_buffer.h new file mode 100644 index 0000000000000000000000000000000000000000..e7bec934105e452e426af9c65201178594f6c3ff --- /dev/null +++ b/hardware/mpp/include/mpp_buffer.h @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_BUFFER_H__ +#define __MPP_BUFFER_H__ + +#include "rk_type.h" +#include "mpp_err.h" + +/* + * MppBuffer module has several functions: + * + * 1. buffer get / put / reference management / external commit / get info. + * this part is the basic user interface for MppBuffer. + * + * function: + * + * mpp_buffer_get + * mpp_buffer_put + * mpp_buffer_inc_ref + * mpp_buffer_commit + * mpp_buffer_info_get + * + * 2. user buffer working flow control abstraction. + * buffer should attach to certain group, and buffer mode control the buffer usage flow. + * this part is also a part of user interface. + * + * function: + * + * mpp_buffer_group_get + * mpp_buffer_group_normal_get + * mpp_buffer_group_limit_get + * mpp_buffer_group_put + * mpp_buffer_group_limit_config + * + * 3. buffer allocator management + * this part is for allocator on different os, it does not have user interface + * it will support normal buffer, ion buffer, Linux v4l2 vb2 buffer + * user can only use MppBufferType to choose. + * + */ + +/* + * mpp buffer group support two work flow mode: + * + * normal flow: all buffer are generated by MPP + * under this mode, buffer pool is maintained internally + * + * typical call flow: + * + * mpp_buffer_group_get() return A + * mpp_buffer_get(A) return a ref +1 -> used + * mpp_buffer_inc_ref(a) ref +1 + * mpp_buffer_put(a) ref -1 + * mpp_buffer_put(a) ref -1 -> unused + * mpp_buffer_group_put(A) + * + * commit flow: all buffer are commited out of MPP + * under this mode, buffers is commit by external api. + * normally MPP only use it but not generate it. + * + * typical call flow: + * + * ==== external allocator ==== + * mpp_buffer_group_get() return A + * mpp_buffer_commit(A, x) + * mpp_buffer_commit(A, y) + * + * ======= internal user ====== + * mpp_buffer_get(A) return a + * mpp_buffer_get(A) return b + * mpp_buffer_put(a) + * mpp_buffer_put(b) + * + * ==== external allocator ==== + * mpp_buffer_group_put(A) + * + * NOTE: commit interface required group handle to record group information + */ + +/* + * mpp buffer group has two buffer limit mode: normal and limit + * + * normal mode: allows any buffer size and always general new buffer is no unused buffer + * is available. + * This mode normally use with normal flow and is used for table / stream buffer + * + * limit mode : restrict the buffer's size and count in the buffer group. if try to calloc + * buffer with different size or extra count it will fail. + * This mode normally use with commit flow and is used for frame buffer + */ + +/* + * NOTE: normal mode is recommanded to work with normal flow, working with limit mode is not. + * limit mode is recommanded to work with commit flow, working with normal mode is not. + */ +typedef enum { + MPP_BUFFER_INTERNAL, + MPP_BUFFER_EXTERNAL, + MPP_BUFFER_MODE_BUTT, +} MppBufferMode; + +/* + * the mpp buffer has serval types: + * + * normal : normal malloc buffer for unit test or hardware simulation + * ion : use ion device under Linux, MppBuffer will encapsulte ion file handle + * ext_dma : the DMABUF(DMA buffers) come from the application + * drm : use the drm device interface for memory management + */ +typedef enum { + MPP_BUFFER_TYPE_NORMAL, + MPP_BUFFER_TYPE_ION, + MPP_BUFFER_TYPE_EXT_DMA, + MPP_BUFFER_TYPE_DRM, + MPP_BUFFER_TYPE_BUTT, +} MppBufferType; + +#define MPP_BUFFER_TYPE_MASK 0x0000FFFF + +/* + * MPP_BUFFER_FLAGS cooperate with MppBufferType + * 16 high bits of MppBufferType are used in flags + * + * eg: + * DRM CMA buffer : MPP_BUFFER_TYPE_DRM | MPP_BUFFER_FLAGS_CONTIG + * = 0x00010003 + * DRM SECURE buffer: MPP_BUFFER_TYPE_DRM | MPP_BUFFER_FLAGS_SECURE + * = 0x00080003 + * + * flags originate from drm_rockchip_gem_mem_type + */ + +#define MPP_BUFFER_FLAGS_MASK 0x000f0000 // ROCKCHIP_BO_MASK << 16 +#define MPP_BUFFER_FLAGS_CONTIG 0x00010000 // ROCKCHIP_BO_CONTIG << 16 +#define MPP_BUFFER_FLAGS_CACHABLE 0x00020000 // ROCKCHIP_BO_CACHABLE << 16 +#define MPP_BUFFER_FLAGS_WC 0x00040000 // ROCKCHIP_BO_WC << 16 +#define MPP_BUFFER_FLAGS_SECURE 0x00080000 // ROCKCHIP_BO_SECURE << 16 + +/* + * MppBufferInfo variable's meaning is different in different MppBufferType + * + * Common + * index - the buffer index used to track buffer in buffer pool + * size - the buffer size + * + * MPP_BUFFER_TYPE_NORMAL + * + * ptr - virtual address of normal malloced buffer + * fd - unused and set to -1, the allocator would return its + * internal buffer counter number + * + * MPP_BUFFER_TYPE_ION + * + * ptr - virtual address of ion buffer in user space + * hnd - ion handle in user space + * fd - ion buffer file handle for map / unmap + * + */ +typedef struct MppBufferInfo_t { + MppBufferType type; + size_t size; + void *ptr; + void *hnd; + int fd; + int index; +} MppBufferInfo; + +#define BUFFER_GROUP_SIZE_DEFAULT (SZ_1M*80) + +/* + * mpp_buffer_import_with_tag(MppBufferGroup group, MppBufferInfo *info, MppBuffer *buffer) + * + * 1. group - specified the MppBuffer to be attached to. + * group can be NULL then this buffer will attached to default legecy group + * Default to NULL on mpp_buffer_import case + * + * 2. info - input information for the output MppBuffer + * info can NOT be NULL. It must contain at least one of ptr/fd. + * + * 3. buffer - generated MppBuffer from MppBufferInfo. + * buffer can be NULL then the buffer is commit to group with unused status. + * Otherwise generated buffer will be directly got and ref_count increased. + * Default to NULL on mpp_buffer_commit case + * + * mpp_buffer_commit usage: + * + * Add a external buffer info to group. This buffer will be on unused status. + * Typical usage is on MediaPlayer gralloc Graphic buffer then commit these buffer + * to decoder's buffer group. Then decoder will recycle these buffer and return buffer reference + * to MediaPlayer for display. + * + * mpp_buffer_import usage: + * + * Transfer a external buffer info to MppBuffer but it is not expected to attached to certain + * buffer group. So the group is set to NULL. Then this buffer can be used for MppFrame/MppPacket. + * Typical usage is for image processing. Image processing normally will be a oneshot operation + * It does not need complicated group management. But in other hand mpp still need to know the + * imported buffer is leak or not and trace its usage inside mpp process. So we attach this kind + * of buffer to default misc buffer group for management. + */ +#define mpp_buffer_commit(group, info) \ + mpp_buffer_import_with_tag(group, info, NULL, MODULE_TAG, __FUNCTION__) + +#define mpp_buffer_import(buffer, info) \ + mpp_buffer_import_with_tag(NULL, info, buffer, MODULE_TAG, __FUNCTION__) + +#define mpp_buffer_get(group, buffer, size) \ + mpp_buffer_get_with_tag(group, buffer, size, MODULE_TAG, __FUNCTION__) + +#define mpp_buffer_put(buffer) \ + mpp_buffer_put_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_inc_ref(buffer) \ + mpp_buffer_inc_ref_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_info_get(buffer, info) \ + mpp_buffer_info_get_with_caller(buffer, info, __FUNCTION__) + +#define mpp_buffer_read(buffer, offset, data, size) \ + mpp_buffer_read_with_caller(buffer, offset, data, size, __FUNCTION__) + +#define mpp_buffer_write(buffer, offset, data, size) \ + mpp_buffer_write_with_caller(buffer, offset, data, size, __FUNCTION__) + +#define mpp_buffer_get_ptr(buffer) \ + mpp_buffer_get_ptr_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_get_fd(buffer) \ + mpp_buffer_get_fd_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_get_size(buffer) \ + mpp_buffer_get_size_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_get_index(buffer) \ + mpp_buffer_get_index_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_set_index(buffer, index) \ + mpp_buffer_set_index_with_caller(buffer, index, __FUNCTION__) + +#define mpp_buffer_get_offset(buffer) \ + mpp_buffer_get_offset_with_caller(buffer, __FUNCTION__) + +#define mpp_buffer_set_offset(buffer, offset) \ + mpp_buffer_set_offset_with_caller(buffer, offset, __FUNCTION__) + +#define mpp_buffer_group_get_internal(group, type, ...) \ + mpp_buffer_group_get(group, type, MPP_BUFFER_INTERNAL, MODULE_TAG, __FUNCTION__) + +#define mpp_buffer_group_get_external(group, type, ...) \ + mpp_buffer_group_get(group, type, MPP_BUFFER_EXTERNAL, MODULE_TAG, __FUNCTION__) + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * MppBuffer interface + * these interface will change value of group and buffer so before calling functions + * parameter need to be checked. + * + * IMPORTANT: + * mpp_buffer_import_with_tag - compounded interface for commit and import + * + */ +MPP_RET mpp_buffer_import_with_tag(MppBufferGroup group, MppBufferInfo *info, MppBuffer *buffer, + const char *tag, const char *caller); +MPP_RET mpp_buffer_get_with_tag(MppBufferGroup group, MppBuffer *buffer, size_t size, + const char *tag, const char *caller); +MPP_RET mpp_buffer_put_with_caller(MppBuffer buffer, const char *caller); +MPP_RET mpp_buffer_inc_ref_with_caller(MppBuffer buffer, const char *caller); + +MPP_RET mpp_buffer_info_get_with_caller(MppBuffer buffer, MppBufferInfo *info, const char *caller); +MPP_RET mpp_buffer_read_with_caller(MppBuffer buffer, size_t offset, void *data, size_t size, const char *caller); +MPP_RET mpp_buffer_write_with_caller(MppBuffer buffer, size_t offset, void *data, size_t size, const char *caller); +void *mpp_buffer_get_ptr_with_caller(MppBuffer buffer, const char *caller); +int mpp_buffer_get_fd_with_caller(MppBuffer buffer, const char *caller); +size_t mpp_buffer_get_size_with_caller(MppBuffer buffer, const char *caller); +int mpp_buffer_get_index_with_caller(MppBuffer buffer, const char *caller); +MPP_RET mpp_buffer_set_index_with_caller(MppBuffer buffer, int index, const char *caller); +size_t mpp_buffer_get_offset_with_caller(MppBuffer buffer, const char *caller); +MPP_RET mpp_buffer_set_offset_with_caller(MppBuffer buffer, size_t offset, const char *caller); + +MPP_RET mpp_buffer_group_get(MppBufferGroup *group, MppBufferType type, MppBufferMode mode, + const char *tag, const char *caller); +MPP_RET mpp_buffer_group_put(MppBufferGroup group); +MPP_RET mpp_buffer_group_clear(MppBufferGroup group); +RK_S32 mpp_buffer_group_unused(MppBufferGroup group); +size_t mpp_buffer_group_usage(MppBufferGroup group); +MppBufferMode mpp_buffer_group_mode(MppBufferGroup group); +MppBufferType mpp_buffer_group_type(MppBufferGroup group); + +/* + * size : 0 - no limit, other - max buffer size + * count : 0 - no limit, other - max buffer count + */ +MPP_RET mpp_buffer_group_limit_config(MppBufferGroup group, size_t size, RK_S32 count); + +RK_U32 mpp_buffer_total_now(void); +RK_U32 mpp_buffer_total_max(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_BUFFER_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_common.h b/hardware/mpp/include/mpp_common.h new file mode 100644 index 0000000000000000000000000000000000000000..82337f466e7ce8162e95c92b690d9781e4ec9fb2 --- /dev/null +++ b/hardware/mpp/include/mpp_common.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_COMMON_H__ +#define __MPP_COMMON_H__ + +#include "rk_type.h" + +#define MPP_TAG_SIZE 32 + +#define MPP_ABS(x) ((x) < (0) ? -(x) : (x)) + +#define MPP_MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MPP_MAX3(a, b, c) MPP_MAX(MPP_MAX(a, b), c) +#define MPP_MAX4(a, b, c, d) MPP_MAX((a), MPP_MAX3((b), (c), (d))) + +#define MPP_MIN(a, b) ((a) > (b) ? (b) : (a)) +#define MPP_MIN3(a, b, c) MPP_MIN(MPP_MIN(a, b), c) +#define MPP_MIN4(a, b, c, d) MPP_MIN((a), MPP_MIN3((b), (c), (d))) + +#define MPP_DIV(a, b) ((b) ? (a) / (b) : (a)) + +#define MPP_CLIP3(l, h, v) ((v) < (l) ? (l) : ((v) > (h) ? (h) : (v))) +#define MPP_SIGN(a) ((a) < (0) ? (-1) : (1)) +#define MPP_DIV_SIGN(a, b) (((a) + (MPP_SIGN(a) * (b)) / 2) / (b)) + +#define MPP_SWAP(type, a, b) do {type SWAP_tmp = b; b = a; a = SWAP_tmp; } while (0) +#define MPP_ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0])) +#define MPP_ALIGN(x, a) (((x)+(a)-1)&~((a)-1)) +#define MPP_VSWAP(a, b) { (a) ^= (b); (b) ^= (a); (a) ^= (b); } + +#define MPP_RB16(x) ((((const RK_U8*)(x))[0] << 8) | ((const RK_U8*)(x))[1]) +#define MPP_WB16(p, d) do { \ + ((RK_U8*)(p))[1] = (d); \ + ((RK_U8*)(p))[0] = (d)>>8; } while (0) + +#define MPP_RL16(x) ((((const RK_U8*)(x))[1] << 8) | \ + ((const RK_U8*)(x))[0]) +#define MPP_WL16(p, d) do { \ + ((RK_U8*)(p))[0] = (d); \ + ((RK_U8*)(p))[1] = (d)>>8; } while (0) + +#define MPP_RB32(x) ((((const RK_U8*)(x))[0] << 24) | \ + (((const RK_U8*)(x))[1] << 16) | \ + (((const RK_U8*)(x))[2] << 8) | \ + ((const RK_U8*)(x))[3]) +#define MPP_WB32(p, d) do { \ + ((RK_U8*)(p))[3] = (d); \ + ((RK_U8*)(p))[2] = (d)>>8; \ + ((RK_U8*)(p))[1] = (d)>>16; \ + ((RK_U8*)(p))[0] = (d)>>24; } while (0) + +#define MPP_RL32(x) ((((const RK_U8*)(x))[3] << 24) | \ + (((const RK_U8*)(x))[2] << 16) | \ + (((const RK_U8*)(x))[1] << 8) | \ + ((const RK_U8*)(x))[0]) +#define MPP_WL32(p, d) do { \ + ((RK_U8*)(p))[0] = (d); \ + ((RK_U8*)(p))[1] = (d)>>8; \ + ((RK_U8*)(p))[2] = (d)>>16; \ + ((RK_U8*)(p))[3] = (d)>>24; } while (0) + +#define MPP_RB64(x) (((RK_U64)((const RK_U8*)(x))[0] << 56) | \ + ((RK_U64)((const RK_U8*)(x))[1] << 48) | \ + ((RK_U64)((const RK_U8*)(x))[2] << 40) | \ + ((RK_U64)((const RK_U8*)(x))[3] << 32) | \ + ((RK_U64)((const RK_U8*)(x))[4] << 24) | \ + ((RK_U64)((const RK_U8*)(x))[5] << 16) | \ + ((RK_U64)((const RK_U8*)(x))[6] << 8) | \ + (RK_U64)((const RK_U8*)(x))[7]) +#define MPP_WB64(p, d) do { \ + ((RK_U8*)(p))[7] = (d); \ + ((RK_U8*)(p))[6] = (d)>>8; \ + ((RK_U8*)(p))[5] = (d)>>16; \ + ((RK_U8*)(p))[4] = (d)>>24; \ + ((RK_U8*)(p))[3] = (d)>>32; \ + ((RK_U8*)(p))[2] = (d)>>40; \ + ((RK_U8*)(p))[1] = (d)>>48; \ + ((RK_U8*)(p))[0] = (d)>>56; } while (0) + +#define MPP_RL64(x) (((RK_U64)((const RK_U8*)(x))[7] << 56) | \ + ((RK_U64)((const RK_U8*)(x))[6] << 48) | \ + ((RK_U64)((const RK_U8*)(x))[5] << 40) | \ + ((RK_U64)((const RK_U8*)(x))[4] << 32) | \ + ((RK_U64)((const RK_U8*)(x))[3] << 24) | \ + ((RK_U64)((const RK_U8*)(x))[2] << 16) | \ + ((RK_U64)((const RK_U8*)(x))[1] << 8) | \ + (RK_U64)((const RK_U8*)(x))[0]) +#define MPP_WL64(p, d) do { \ + ((RK_U8*)(p))[0] = (d); \ + ((RK_U8*)(p))[1] = (d)>>8; \ + ((RK_U8*)(p))[2] = (d)>>16; \ + ((RK_U8*)(p))[3] = (d)>>24; \ + ((RK_U8*)(p))[4] = (d)>>32; \ + ((RK_U8*)(p))[5] = (d)>>40; \ + ((RK_U8*)(p))[6] = (d)>>48; \ + ((RK_U8*)(p))[7] = (d)>>56; } while (0) + +#define MPP_RB24(x) ((((const RK_U8*)(x))[0] << 16) | \ + (((const RK_U8*)(x))[1] << 8) | \ + ((const RK_U8*)(x))[2]) +#define MPP_WB24(p, d) do { \ + ((RK_U8*)(p))[2] = (d); \ + ((RK_U8*)(p))[1] = (d)>>8; \ + ((RK_U8*)(p))[0] = (d)>>16; } while (0) + +#define MPP_RL24(x) ((((const RK_U8*)(x))[2] << 16) | \ + (((const RK_U8*)(x))[1] << 8) | \ + ((const RK_U8*)(x))[0]) + +#define MPP_WL24(p, d) do { \ + ((RK_U8*)(p))[0] = (d); \ + ((RK_U8*)(p))[1] = (d)>>8; \ + ((RK_U8*)(p))[2] = (d)>>16; } while (0) + +#include +#if defined(_WIN32) && !defined(__MINGW32CE__) +#define fseeko _fseeki64 + +#include +#include +#include +#define chdir _chdir +#define mkdir _mkdir +#define access _access +#define off_t _off_t + +#define R_OK 4 /* Test for read permission. */ +#define W_OK 2 /* Test for write permission. */ +#define X_OK 1 /* Test for execute permission. */ +#define F_OK 0 /* Test for existence. */ + +#elif defined(__MINGW32CE__) +#define fseeko fseeko64 +#else +#include +#include +#include +#include +#define mkdir(x) mkdir(x, S_IRWXU | S_IRGRP | S_IXGRP | S_IROTH | S_IXOTH) +#endif + +#define container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - offsetof(type, member))) + +#define __RETURN __Return +#define __FAILED __Failed + +#define ARG_T(t) t +#define ARG_N(a, b, c, d, N, ...) N +#define ARG_N_HELPER(...) ARG_T(ARG_N(__VA_ARGS__)) +#define COUNT_ARG(...) ARG_N_HELPER(__VA_ARGS__, 4, 3, 2, 1, 0) + +#define SZ_1K (1024) +#define SZ_2K (SZ_1K*2) +#define SZ_4K (SZ_1K*4) +#define SZ_8K (SZ_1K*8) +#define SZ_16K (SZ_1K*16) +#define SZ_32K (SZ_1K*32) +#define SZ_64K (SZ_1K*64) +#define SZ_128K (SZ_1K*128) +#define SZ_256K (SZ_1K*256) +#define SZ_512K (SZ_1K*512) +#define SZ_1M (SZ_1K*SZ_1K) +#define SZ_2M (SZ_1M*2) +#define SZ_4M (SZ_1M*4) +#define SZ_8M (SZ_1M*8) +#define SZ_16M (SZ_1M*16) +#define SZ_32M (SZ_1M*32) +#define SZ_64M (SZ_1M*64) +#define SZ_80M (SZ_1M*80) +#define SZ_128M (SZ_1M*128) + +#ifdef __cplusplus +extern "C" { +#endif + +RK_S32 mpp_log2(RK_U32 v); +RK_S32 mpp_log2_16bit(RK_U32 v); + +static __inline RK_S32 mpp_ceil_log2(RK_S32 x) +{ + return mpp_log2((x - 1) << 1); +} + +static __inline RK_S32 mpp_clip(RK_S32 a, RK_S32 amin, RK_S32 amax) +{ + if (a < amin) { + return amin; + } else if (a > amax) { + return amax; + } else { + return a; + } +} + +static __inline RK_U32 mpp_is_32bit(void) +{ + return ((sizeof(void *) == 4) ? (1) : (0)); +} + +RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_COMMON_H__ */ diff --git a/hardware/mpp/include/mpp_dev_defs.h b/hardware/mpp/include/mpp_dev_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..3fc52c52703ae1712550842a45afaa5785277517 --- /dev/null +++ b/hardware/mpp/include/mpp_dev_defs.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_DEV_DEFS_H__ +#define __MPP_DEV_DEFS_H__ + +/* + * Platform video codec hardware feature + */ +typedef enum MppClientType_e { + VPU_CLIENT_VDPU1 = 0, /* 0x00000001 */ + VPU_CLIENT_VDPU2 = 1, /* 0x00000002 */ + VPU_CLIENT_VDPU1_PP = 2, /* 0x00000004 */ + VPU_CLIENT_VDPU2_PP = 3, /* 0x00000008 */ + + VPU_CLIENT_HEVC_DEC = 8, /* 0x00000100 */ + VPU_CLIENT_RKVDEC = 9, /* 0x00000200 */ + VPU_CLIENT_AVSPLUS_DEC = 12, /* 0x00001000 */ + VPU_CLIENT_JPEG_DEC = 13, /* 0x00002000 */ + + VPU_CLIENT_RKVENC = 16, /* 0x00010000 */ + VPU_CLIENT_VEPU1 = 17, /* 0x00020000 */ + VPU_CLIENT_VEPU2 = 18, /* 0x00040000 */ + VPU_CLIENT_VEPU2_LITE = 19, /* 0x00080000 */ + VPU_CLIENT_VEPU22 = 24, /* 0x01000000 */ + + IEP_CLIENT_TYPE = 28, /* 0x10000000 */ + + VPU_CLIENT_BUTT, +} MppClientType; + +/* RK combined codec */ +#define HAVE_VDPU1 (1 << VPU_CLIENT_VDPU1) /* 0x00000001 */ +#define HAVE_VDPU2 (1 << VPU_CLIENT_VDPU2) /* 0x00000002 */ +#define HAVE_VDPU1_PP (1 << VPU_CLIENT_VDPU1_PP) /* 0x00000004 */ +#define HAVE_VDPU2_PP (1 << VPU_CLIENT_VDPU2_PP) /* 0x00000008 */ +/* RK standalone decoder */ +#define HAVE_HEVC_DEC (1 << VPU_CLIENT_HEVC_DEC) /* 0x00000100 */ +#define HAVE_RKVDEC (1 << VPU_CLIENT_RKVDEC) /* 0x00000200 */ +#define HAVE_AVSDEC (1 << VPU_CLIENT_AVSPLUS_DEC) /* 0x00001000 */ +#define HAVE_JPEG_DEC (1 << VPU_CLIENT_JPEG_DEC) /* 0x00002000 */ +/* RK standalone encoder */ +#define HAVE_RKVENC (1 << VPU_CLIENT_RKVENC) /* 0x00010000 */ +#define HAVE_VEPU1 (1 << VPU_CLIENT_VEPU1) /* 0x00020000 */ +#define HAVE_VEPU2 (1 << VPU_CLIENT_VEPU2) /* 0x00040000 */ +/* External encoder */ +#define HAVE_VEPU22 (1 << VPU_CLIENT_VEPU22) /* 0x01000000 */ +/* RK Image Enhance Processor for deinterlacing */ +#define HAVE_IEP (1 << IEP_CLIENT_TYPE) /* 0x10000000 */ + +/* Platform image process hardware feature */ +#define HAVE_IPP (0x00000001) +#define HAVE_RGA (0x00000002) +#define HAVE_RGA2 (0x00000004) + +#endif /* __MPP_DEV_DEFS_H__ */ diff --git a/hardware/mpp/include/mpp_device.h b/hardware/mpp/include/mpp_device.h new file mode 100644 index 0000000000000000000000000000000000000000..7f9238df489ec3e2be6cdd512996dac89aa62eb1 --- /dev/null +++ b/hardware/mpp/include/mpp_device.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_DEVICE_H__ +#define __MPP_DEVICE_H__ + +#include "mpp_err.h" +#include "mpp_dev_defs.h" + +typedef enum MppDevIoctlCmd_e { + /* device batch mode config */ + MPP_DEV_BATCH_ON, + MPP_DEV_BATCH_OFF, + + /* hardware operation setup config */ + MPP_DEV_REG_WR, + MPP_DEV_REG_RD, + MPP_DEV_REG_OFFSET, + MPP_DEV_RCB_INFO, + MPP_DEV_SET_INFO, + + MPP_DEV_CMD_SEND, + MPP_DEV_CMD_POLL, + + MPP_DEV_IOCTL_CMD_BUTT, +} MppDevIoctlCmd; + +/* for MPP_DEV_REG_WR */ +typedef struct MppDevRegWrCfg_t { + void *reg; + RK_U32 size; + RK_U32 offset; +} MppDevRegWrCfg; + +/* for MPP_DEV_REG_RD */ +typedef struct MppDevRegRdCfg_t { + void *reg; + RK_U32 size; + RK_U32 offset; +} MppDevRegRdCfg; + +/* for MPP_DEV_REG_OFFSET */ +typedef struct MppDevRegOffsetCfg_t { + RK_U32 reg_idx; + RK_U32 offset; +} MppDevRegOffsetCfg; + +/* for MPP_DEV_RCB_INFO */ +typedef struct MppDevRcbInfoCfg_t { + RK_U32 reg_idx; + RK_U32 size; +} MppDevRcbInfoCfg; + +/* for MPP_DEV_SET_INFO */ +typedef struct MppDevSetInfoCfg_t { + RK_U32 type; + RK_U32 flag; + RK_U64 data; +} MppDevInfoCfg; + +typedef struct MppDevApi_t { + const char *name; + RK_U32 ctx_size; + MPP_RET (*init)(void *ctx, MppClientType type); + MPP_RET (*deinit)(void *ctx); + + /* bat mode function */ + MPP_RET (*attach)(void *ctx); + MPP_RET (*detach)(void *ctx); + + /* config the cmd on preparing */ + MPP_RET (*reg_wr)(void *ctx, MppDevRegWrCfg *cfg); + MPP_RET (*reg_rd)(void *ctx, MppDevRegRdCfg *cfg); + MPP_RET (*reg_offset)(void *ctx, MppDevRegOffsetCfg *cfg); + MPP_RET (*rcb_info)(void *ctx, MppDevRcbInfoCfg *cfg); + MPP_RET (*set_info)(void *ctx, MppDevInfoCfg *cfg); + + /* send cmd to hardware */ + MPP_RET (*cmd_send)(void *ctx); + + /* poll cmd from hardware */ + MPP_RET (*cmd_poll)(void *ctx); +} MppDevApi; + +typedef void* MppDev; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_dev_init(MppDev *ctx, MppClientType type); +MPP_RET mpp_dev_deinit(MppDev ctx); + +MPP_RET mpp_dev_ioctl(MppDev ctx, RK_S32 cmd, void *param); + +/* special helper function for large address offset config */ +MPP_RET mpp_dev_set_reg_offset(MppDev dev, RK_S32 index, RK_U32 offset); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_DEVICE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_env.h b/hardware/mpp/include/mpp_env.h new file mode 100755 index 0000000000000000000000000000000000000000..12508814591e9fe74e509dd390be961f9506014d --- /dev/null +++ b/hardware/mpp/include/mpp_env.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_ENV_H__ +#define __MPP_ENV_H__ + +#include "rk_type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +RK_S32 mpp_env_get_u32(const char *name, RK_U32 *value, RK_U32 default_value); +RK_S32 mpp_env_get_str(const char *name, const char **value, const char *default_value); + +RK_S32 mpp_env_set_u32(const char *name, RK_U32 value); +RK_S32 mpp_env_set_str(const char *name, char *value); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_ENV_H__ */ + diff --git a/hardware/mpp/include/mpp_err.h b/hardware/mpp/include/mpp_err.h new file mode 100644 index 0000000000000000000000000000000000000000..f68040a23d39ae67b6e216325244b21f5c77e25d --- /dev/null +++ b/hardware/mpp/include/mpp_err.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_ERR_H__ +#define __MPP_ERR_H__ + +#define RK_OK 0 +#define RK_SUCCESS 0 + +typedef enum { + MPP_SUCCESS = RK_SUCCESS, + MPP_OK = RK_OK, + + MPP_NOK = -1, + MPP_ERR_UNKNOW = -2, + MPP_ERR_NULL_PTR = -3, + MPP_ERR_MALLOC = -4, + MPP_ERR_OPEN_FILE = -5, + MPP_ERR_VALUE = -6, + MPP_ERR_READ_BIT = -7, + MPP_ERR_TIMEOUT = -8, + MPP_ERR_PERM = -9, + + MPP_ERR_BASE = -1000, + + /* The error in stream processing */ + MPP_ERR_LIST_STREAM = MPP_ERR_BASE - 1, + MPP_ERR_INIT = MPP_ERR_BASE - 2, + MPP_ERR_VPU_CODEC_INIT = MPP_ERR_BASE - 3, + MPP_ERR_STREAM = MPP_ERR_BASE - 4, + MPP_ERR_FATAL_THREAD = MPP_ERR_BASE - 5, + MPP_ERR_NOMEM = MPP_ERR_BASE - 6, + MPP_ERR_PROTOL = MPP_ERR_BASE - 7, + MPP_FAIL_SPLIT_FRAME = MPP_ERR_BASE - 8, + MPP_ERR_VPUHW = MPP_ERR_BASE - 9, + MPP_EOS_STREAM_REACHED = MPP_ERR_BASE - 11, + MPP_ERR_BUFFER_FULL = MPP_ERR_BASE - 12, + MPP_ERR_DISPLAY_FULL = MPP_ERR_BASE - 13, +} MPP_RET; + +#endif /* __MPP_ERR_H__ */ diff --git a/hardware/mpp/include/mpp_eventfd.h b/hardware/mpp/include/mpp_eventfd.h new file mode 100644 index 0000000000000000000000000000000000000000..ed27db663ce12ed9678be009cb0dbd76d34a5bfd --- /dev/null +++ b/hardware/mpp/include/mpp_eventfd.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_EVENTFD_H__ +#define __MPP_EVENTFD_H__ + +#include "rk_type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +RK_S32 mpp_eventfd_get(RK_U32 init); +RK_S32 mpp_eventfd_put(RK_S32 fd); + +RK_S32 mpp_eventfd_read(RK_S32 fd, RK_U64 *val, RK_S64 timeout); +RK_S32 mpp_eventfd_write(RK_S32 fd, RK_U64 val); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_EVENTFD_H__ */ + diff --git a/hardware/mpp/include/mpp_frame.h b/hardware/mpp/include/mpp_frame.h new file mode 100644 index 0000000000000000000000000000000000000000..a00b4ff4e41b47449f6b50e032f4b96c638d426d --- /dev/null +++ b/hardware/mpp/include/mpp_frame.h @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_FRAME_H__ +#define __MPP_FRAME_H__ + +#include "mpp_buffer.h" + +/* + * bit definition for mode flag in MppFrame + */ +/* progressive frame */ +#define MPP_FRAME_FLAG_FRAME (0x00000000) +/* top field only */ +#define MPP_FRAME_FLAG_TOP_FIELD (0x00000001) +/* bottom field only */ +#define MPP_FRAME_FLAG_BOT_FIELD (0x00000002) +/* paired field */ +#define MPP_FRAME_FLAG_PAIRED_FIELD (MPP_FRAME_FLAG_TOP_FIELD|MPP_FRAME_FLAG_BOT_FIELD) +/* paired field with field order of top first */ +#define MPP_FRAME_FLAG_TOP_FIRST (0x00000004) +/* paired field with field order of bottom first */ +#define MPP_FRAME_FLAG_BOT_FIRST (0x00000008) +/* paired field with unknown field order (MBAFF) */ +#define MPP_FRAME_FLAG_DEINTERLACED (MPP_FRAME_FLAG_TOP_FIRST|MPP_FRAME_FLAG_BOT_FIRST) +#define MPP_FRAME_FLAG_FIELD_ORDER_MASK (0x0000000C) +// for multiview stream +#define MPP_FRAME_FLAG_VIEW_ID_MASK (0x000000f0) + +#define MPP_FRAME_FLAG_IEP_DEI_MASK (0x00000f00) +#define MPP_FRAME_FLAG_IEP_DEI_I2O1 (0x00000100) +#define MPP_FRAME_FLAG_IEP_DEI_I4O2 (0x00000200) +#define MPP_FRAME_FLAG_IEP_DEI_I4O1 (0x00000300) + +/* + * MPEG vs JPEG YUV range. + */ +typedef enum { + MPP_FRAME_RANGE_UNSPECIFIED = 0, + MPP_FRAME_RANGE_MPEG = 1, ///< the normal 219*2^(n-8) "MPEG" YUV ranges + MPP_FRAME_RANGE_JPEG = 2, ///< the normal 2^n-1 "JPEG" YUV ranges + MPP_FRAME_RANGE_NB, ///< Not part of ABI +} MppFrameColorRange; + +typedef enum { + MPP_FRAME_VIDEO_FMT_COMPONEMT = 0, + MPP_FRAME_VIDEO_FMT_PAL = 1, + MPP_FRAME_VIDEO_FMT_NTSC = 2, + MPP_FRAME_VIDEO_FMT_SECAM = 3, + MPP_FRAME_VIDEO_FMT_MAC = 4, + MPP_FRAME_VIDEO_FMT_UNSPECIFIED = 5, + MPP_FRAME_VIDEO_FMT_RESERVED0 = 6, + MPP_FRAME_VIDEO_FMT_RESERVED1 = 7, +} MppFrameVideoFormat; + +/* + * Chromaticity coordinates of the source primaries. + */ +typedef enum { + MPP_FRAME_PRI_RESERVED0 = 0, + MPP_FRAME_PRI_BT709 = 1, ///< also ITU-R BT1361 / IEC 61966-2-4 / SMPTE RP177 Annex B + MPP_FRAME_PRI_UNSPECIFIED = 2, + MPP_FRAME_PRI_RESERVED = 3, + MPP_FRAME_PRI_BT470M = 4, ///< also FCC Title 47 Code of Federal Regulations 73.682 (a)(20) + + MPP_FRAME_PRI_BT470BG = 5, ///< also ITU-R BT601-6 625 / ITU-R BT1358 625 / ITU-R BT1700 625 PAL & SECAM + MPP_FRAME_PRI_SMPTE170M = 6, ///< also ITU-R BT601-6 525 / ITU-R BT1358 525 / ITU-R BT1700 NTSC + MPP_FRAME_PRI_SMPTE240M = 7, ///< functionally identical to above + MPP_FRAME_PRI_FILM = 8, ///< colour filters using Illuminant C + MPP_FRAME_PRI_BT2020 = 9, ///< ITU-R BT2020 + MPP_FRAME_PRI_SMPTEST428_1 = 10, ///< SMPTE ST 428-1 (CIE 1931 XYZ) + MPP_FRAME_PRI_SMPTE431 = 11, ///< SMPTE ST 431-2 (2011) / DCI P3 + MPP_FRAME_PRI_SMPTE432 = 12, ///< SMPTE ST 432-1 (2010) / P3 D65 / Display P3 + MPP_FRAME_PRI_JEDEC_P22 = 22, ///< JEDEC P22 phosphors + MPP_FRAME_PRI_NB, ///< Not part of ABI +} MppFrameColorPrimaries; + +/* + * Color Transfer Characteristic. + */ +typedef enum { + MPP_FRAME_TRC_RESERVED0 = 0, + MPP_FRAME_TRC_BT709 = 1, ///< also ITU-R BT1361 + MPP_FRAME_TRC_UNSPECIFIED = 2, + MPP_FRAME_TRC_RESERVED = 3, + MPP_FRAME_TRC_GAMMA22 = 4, ///< also ITU-R BT470M / ITU-R BT1700 625 PAL & SECAM + MPP_FRAME_TRC_GAMMA28 = 5, ///< also ITU-R BT470BG + ///< also ITU-R BT601-6 525 or 625 / ITU-R BT1358 525 or 625 / ITU-R BT1700 NTSC + MPP_FRAME_TRC_SMPTE170M = 6, + MPP_FRAME_TRC_SMPTE240M = 7, + MPP_FRAME_TRC_LINEAR = 8, ///< "Linear transfer characteristics" + MPP_FRAME_TRC_LOG = 9, ///< "Logarithmic transfer characteristic (100:1 range)" + MPP_FRAME_TRC_LOG_SQRT = 10, ///< "Logarithmic transfer characteristic (100 * Sqrt(10) : 1 range)" + MPP_FRAME_TRC_IEC61966_2_4 = 11, ///< IEC 61966-2-4 + MPP_FRAME_TRC_BT1361_ECG = 12, ///< ITU-R BT1361 Extended Colour Gamut + MPP_FRAME_TRC_IEC61966_2_1 = 13, ///< IEC 61966-2-1 (sRGB or sYCC) + MPP_FRAME_TRC_BT2020_10 = 14, ///< ITU-R BT2020 for 10 bit system + MPP_FRAME_TRC_BT2020_12 = 15, ///< ITU-R BT2020 for 12 bit system + MPP_FRAME_TRC_SMPTEST2084 = 16, ///< SMPTE ST 2084 for 10-, 12-, 14- and 16-bit systems + MPP_FRAME_TRC_SMPTEST428_1 = 17, ///< SMPTE ST 428-1 + MPP_FRAME_TRC_ARIB_STD_B67 = 18, ///< ARIB STD-B67, known as "Hybrid log-gamma" + MPP_FRAME_TRC_NB, ///< Not part of ABI +} MppFrameColorTransferCharacteristic; + +/* + * YUV colorspace type. + */ +typedef enum { + MPP_FRAME_SPC_RGB = 0, ///< order of coefficients is actually GBR, also IEC 61966-2-1 (sRGB) + MPP_FRAME_SPC_BT709 = 1, ///< also ITU-R BT1361 / IEC 61966-2-4 xvYCC709 / SMPTE RP177 Annex B + MPP_FRAME_SPC_UNSPECIFIED = 2, + MPP_FRAME_SPC_RESERVED = 3, + MPP_FRAME_SPC_FCC = 4, ///< FCC Title 47 Code of Federal Regulations 73.682 (a)(20) + ///< also ITU-R BT601-6 625 / ITU-R BT1358 625 / ITU-R BT1700 625 PAL & SECAM / IEC 61966-2-4 xvYCC601 + MPP_FRAME_SPC_BT470BG = 5, + ///< also ITU-R BT601-6 525 / ITU-R BT1358 525 / ITU-R BT1700 NTSC / functionally identical to above + MPP_FRAME_SPC_SMPTE170M = 6, + MPP_FRAME_SPC_SMPTE240M = 7, + MPP_FRAME_SPC_YCOCG = 8, ///< Used by Dirac / VC-2 and H.264 FRext, see ITU-T SG16 + MPP_FRAME_SPC_BT2020_NCL = 9, ///< ITU-R BT2020 non-constant luminance system + MPP_FRAME_SPC_BT2020_CL = 10, ///< ITU-R BT2020 constant luminance system + MPP_FRAME_SPC_SMPTE2085 = 11, ///< SMPTE 2085, Y'D'zD'x + MPP_FRAME_SPC_CHROMA_DERIVED_NCL = 12, ///< Chromaticity-derived non-constant luminance system + MPP_FRAME_SPC_CHROMA_DERIVED_CL = 13, ///< Chromaticity-derived constant luminance system + MPP_FRAME_SPC_ICTCP = 14, ///< ITU-R BT.2100-0, ICtCp + MPP_FRAME_SPC_NB, ///< Not part of ABI +} MppFrameColorSpace; + +/* + * Location of chroma samples. + * + * Illustration showing the location of the first (top left) chroma sample of the + * image, the left shows only luma, the right + * shows the location of the chroma sample, the 2 could be imagined to overlay + * each other but are drawn separately due to limitations of ASCII + * + * 1st 2nd 1st 2nd horizontal luma sample positions + * v v v v + * ______ ______ + * 1st luma line > |X X ... |3 4 X ... X are luma samples, + * | |1 2 1-6 are possible chroma positions + * 2nd luma line > |X X ... |5 6 X ... 0 is undefined/unknown position + */ +typedef enum { + MPP_CHROMA_LOC_UNSPECIFIED = 0, + MPP_CHROMA_LOC_LEFT = 1, ///< mpeg2/4 4:2:0, h264 default for 4:2:0 + MPP_CHROMA_LOC_CENTER = 2, ///< mpeg1 4:2:0, jpeg 4:2:0, h263 4:2:0 + MPP_CHROMA_LOC_TOPLEFT = 3, ///< ITU-R 601, SMPTE 274M 296M S314M(DV 4:1:1), mpeg2 4:2:2 + MPP_CHROMA_LOC_TOP = 4, + MPP_CHROMA_LOC_BOTTOMLEFT = 5, + MPP_CHROMA_LOC_BOTTOM = 6, + MPP_CHROMA_LOC_NB, ///< Not part of ABI +} MppFrameChromaLocation; + +#define MPP_FRAME_FMT_MASK (0x000fffff) + +#define MPP_FRAME_FMT_COLOR_MASK (0x000f0000) +#define MPP_FRAME_FMT_YUV (0x00000000) +#define MPP_FRAME_FMT_RGB (0x00010000) + +#define MPP_FRAME_FBC_MASK (0x00f00000) +#define MPP_FRAME_FBC_NONE (0x00000000) +/* + * AFBC_V1 is for ISP output. + * It has default payload offset to be calculated * from width and height: + * Payload offset = MPP_ALIGN(MPP_ALIGN(width, 16) * MPP_ALIGN(height, 16) / 16, SZ_4K) + */ +#define MPP_FRAME_FBC_AFBC_V1 (0x00100000) +/* + * AFBC_V2 is for video decoder output. + * It stores payload offset in first 32-bit in header address + * Payload offset is always set to zero. + */ +#define MPP_FRAME_FBC_AFBC_V2 (0x00200000) + +#define MPP_FRAME_FMT_LE_MASK (0x01000000) + +#define MPP_FRAME_FMT_IS_YUV(fmt) ((((fmt) & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_YUV) && \ + (((fmt) & MPP_FRAME_FMT_MASK) < MPP_FMT_YUV_BUTT)) +#define MPP_FRAME_FMT_IS_RGB(fmt) ((((fmt) & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_RGB) && \ + (((fmt) & MPP_FRAME_FMT_MASK) < MPP_FMT_RGB_BUTT)) + +/* + * For MPP_FRAME_FBC_AFBC_V1 the 16byte aligned stride is used. + */ +#define MPP_FRAME_FMT_IS_FBC(fmt) ((fmt) & MPP_FRAME_FBC_MASK) + +#define MPP_FRAME_FMT_IS_LE(fmt) (((fmt) & MPP_FRAME_FMT_LE_MASK) == MPP_FRAME_FMT_LE_MASK) +#define MPP_FRAME_FMT_IS_BE(fmt) (((fmt) & MPP_FRAME_FMT_LE_MASK) == 0) + +/* mpp color format index definition */ +typedef enum { + MPP_FMT_YUV420SP = (MPP_FRAME_FMT_YUV + 0), /* YYYY... UV... (NV12) */ + /* + * A rockchip specific pixel format, without gap between pixel aganist + * the P010_10LE/P010_10BE + */ + MPP_FMT_YUV420SP_10BIT = (MPP_FRAME_FMT_YUV + 1), + MPP_FMT_YUV422SP = (MPP_FRAME_FMT_YUV + 2), /* YYYY... UVUV... (NV16) */ + MPP_FMT_YUV422SP_10BIT = (MPP_FRAME_FMT_YUV + 3), ///< Not part of ABI + MPP_FMT_YUV420P = (MPP_FRAME_FMT_YUV + 4), /* YYYY... U...V... (I420) */ + MPP_FMT_YUV420SP_VU = (MPP_FRAME_FMT_YUV + 5), /* YYYY... VUVUVU... (NV21) */ + MPP_FMT_YUV422P = (MPP_FRAME_FMT_YUV + 6), /* YYYY... UU...VV...(422P) */ + MPP_FMT_YUV422SP_VU = (MPP_FRAME_FMT_YUV + 7), /* YYYY... VUVUVU... (NV61) */ + MPP_FMT_YUV422_YUYV = (MPP_FRAME_FMT_YUV + 8), /* YUYVYUYV... (YUY2) */ + MPP_FMT_YUV422_YVYU = (MPP_FRAME_FMT_YUV + 9), /* YVYUYVYU... (YVY2) */ + MPP_FMT_YUV422_UYVY = (MPP_FRAME_FMT_YUV + 10), /* UYVYUYVY... (UYVY) */ + MPP_FMT_YUV422_VYUY = (MPP_FRAME_FMT_YUV + 11), /* VYUYVYUY... (VYUY) */ + MPP_FMT_YUV400 = (MPP_FRAME_FMT_YUV + 12), /* YYYY... */ + MPP_FMT_YUV440SP = (MPP_FRAME_FMT_YUV + 13), /* YYYY... UVUV... */ + MPP_FMT_YUV411SP = (MPP_FRAME_FMT_YUV + 14), /* YYYY... UV... */ + MPP_FMT_YUV444SP = (MPP_FRAME_FMT_YUV + 15), /* YYYY... UVUVUVUV... */ + MPP_FMT_YUV_BUTT, + + MPP_FMT_RGB565 = (MPP_FRAME_FMT_RGB + 0), /* 16-bit RGB */ + MPP_FMT_BGR565 = (MPP_FRAME_FMT_RGB + 1), /* 16-bit RGB */ + MPP_FMT_RGB555 = (MPP_FRAME_FMT_RGB + 2), /* 15-bit RGB */ + MPP_FMT_BGR555 = (MPP_FRAME_FMT_RGB + 3), /* 15-bit RGB */ + MPP_FMT_RGB444 = (MPP_FRAME_FMT_RGB + 4), /* 12-bit RGB */ + MPP_FMT_BGR444 = (MPP_FRAME_FMT_RGB + 5), /* 12-bit RGB */ + MPP_FMT_RGB888 = (MPP_FRAME_FMT_RGB + 6), /* 24-bit RGB */ + MPP_FMT_BGR888 = (MPP_FRAME_FMT_RGB + 7), /* 24-bit RGB */ + MPP_FMT_RGB101010 = (MPP_FRAME_FMT_RGB + 8), /* 30-bit RGB */ + MPP_FMT_BGR101010 = (MPP_FRAME_FMT_RGB + 9), /* 30-bit RGB */ + MPP_FMT_ARGB8888 = (MPP_FRAME_FMT_RGB + 10), /* 32-bit RGB */ + MPP_FMT_ABGR8888 = (MPP_FRAME_FMT_RGB + 11), /* 32-bit RGB */ + MPP_FMT_BGRA8888 = (MPP_FRAME_FMT_RGB + 12), /* 32-bit RGB */ + MPP_FMT_RGBA8888 = (MPP_FRAME_FMT_RGB + 13), /* 32-bit RGB */ + MPP_FMT_RGB_BUTT, + + MPP_FMT_BUTT, +} MppFrameFormat; + +/** + * Rational number (pair of numerator and denominator). + */ +typedef struct MppFrameRational { + RK_S32 num; ///< Numerator + RK_S32 den; ///< Denominator +} MppFrameRational; + +typedef struct MppFrameMasteringDisplayMetadata { + RK_U16 display_primaries[3][2]; + RK_U16 white_point[2]; + RK_U32 max_luminance; + RK_U32 min_luminance; +} MppFrameMasteringDisplayMetadata; + +typedef struct MppFrameContentLightMetadata { + RK_U16 MaxCLL; + RK_U16 MaxFALL; +} MppFrameContentLightMetadata; + +typedef enum { + MPP_FRAME_ERR_UNKNOW = 0x0001, + MPP_FRAME_ERR_UNSUPPORT = 0x0002, +} MPP_FRAME_ERR; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * MppFrame interface + */ +MPP_RET mpp_frame_init(MppFrame *frame); +MPP_RET mpp_frame_deinit(MppFrame *frame); +MppFrame mpp_frame_get_next(MppFrame frame); + +/* + * normal parameter + * + * offset_x + * <--------> + * + * <---------------+ hor_stride +---------------> + * + * +------------------------------------------------------+ ^ ^ + * | | | | + * | | | | offset_y + * | | | | + * | +--------------------------------+ ^ | | v + * | | | | | | + * | | | + | + + * | | | | + * | | valid data area | height | ver_stride + * | | | | + * | | | + | + + * | | | | | | + * | +--------------------------------+ v | | + * | | | + * | <----------+ width +---------> | | + * | | | + * +------------------------------------------------------+ v + * + */ +RK_U32 mpp_frame_get_width(const MppFrame frame); +void mpp_frame_set_width(MppFrame frame, RK_U32 width); +RK_U32 mpp_frame_get_height(const MppFrame frame); +void mpp_frame_set_height(MppFrame frame, RK_U32 height); +RK_U32 mpp_frame_get_hor_stride(const MppFrame frame); +void mpp_frame_set_hor_stride(MppFrame frame, RK_U32 hor_stride); +RK_U32 mpp_frame_get_ver_stride(const MppFrame frame); +void mpp_frame_set_ver_stride(MppFrame frame, RK_U32 ver_stride); +void mpp_frame_set_hor_stride_pixel(MppFrame frame, RK_U32 hor_stride_pixel); +RK_U32 mpp_frame_get_hor_stride_pixel(const MppFrame frame); + +RK_U32 mpp_frame_get_offset_x(const MppFrame frame); +void mpp_frame_set_offset_x(MppFrame frame, RK_U32 offset_x); +RK_U32 mpp_frame_get_offset_y(const MppFrame frame); +void mpp_frame_set_offset_y(MppFrame frame, RK_U32 offset_y); +RK_U32 mpp_frame_get_mode(const MppFrame frame); +void mpp_frame_set_mode(MppFrame frame, RK_U32 mode); +RK_U32 mpp_frame_get_discard(const MppFrame frame); +void mpp_frame_set_discard(MppFrame frame, RK_U32 discard); +RK_U32 mpp_frame_get_viewid(const MppFrame frame); +void mpp_frame_set_viewid(MppFrame frame, RK_U32 viewid); +RK_U32 mpp_frame_get_poc(const MppFrame frame); +void mpp_frame_set_poc(MppFrame frame, RK_U32 poc); +RK_S64 mpp_frame_get_pts(const MppFrame frame); +void mpp_frame_set_pts(MppFrame frame, RK_S64 pts); +RK_S64 mpp_frame_get_dts(const MppFrame frame); +void mpp_frame_set_dts(MppFrame frame, RK_S64 dts); +RK_U32 mpp_frame_get_errinfo(const MppFrame frame); +void mpp_frame_set_errinfo(MppFrame frame, RK_U32 errinfo); +size_t mpp_frame_get_buf_size(const MppFrame frame); +void mpp_frame_set_buf_size(MppFrame frame, size_t buf_size); +/* + * flow control parmeter + */ +RK_U32 mpp_frame_get_eos(const MppFrame frame); +void mpp_frame_set_eos(MppFrame frame, RK_U32 eos); +RK_U32 mpp_frame_get_info_change(const MppFrame frame); +void mpp_frame_set_info_change(MppFrame frame, RK_U32 info_change); + +/* + * buffer parameter + */ +MppBuffer mpp_frame_get_buffer(const MppFrame frame); +void mpp_frame_set_buffer(MppFrame frame, MppBuffer buffer); + +/* + * meta data parameter + */ +RK_S32 mpp_frame_has_meta(const MppFrame frame); +MppMeta mpp_frame_get_meta(const MppFrame frame); +void mpp_frame_set_meta(MppFrame frame, MppMeta meta); + +/* + * color related parameter + */ +MppFrameColorRange mpp_frame_get_color_range(const MppFrame frame); +void mpp_frame_set_color_range(MppFrame frame, MppFrameColorRange color_range); +MppFrameColorPrimaries mpp_frame_get_color_primaries(const MppFrame frame); +void mpp_frame_set_color_primaries(MppFrame frame, MppFrameColorPrimaries color_primaries); +MppFrameColorTransferCharacteristic mpp_frame_get_color_trc(const MppFrame frame); +void mpp_frame_set_color_trc(MppFrame frame, MppFrameColorTransferCharacteristic color_trc); +MppFrameColorSpace mpp_frame_get_colorspace(const MppFrame frame); +void mpp_frame_set_colorspace(MppFrame frame, MppFrameColorSpace colorspace); +MppFrameChromaLocation mpp_frame_get_chroma_location(const MppFrame frame); +void mpp_frame_set_chroma_location(MppFrame frame, MppFrameChromaLocation chroma_location); +MppFrameFormat mpp_frame_get_fmt(MppFrame frame); +void mpp_frame_set_fmt(MppFrame frame, MppFrameFormat fmt); +MppFrameRational mpp_frame_get_sar(const MppFrame frame); +void mpp_frame_set_sar(MppFrame frame, MppFrameRational sar); +MppFrameMasteringDisplayMetadata mpp_frame_get_mastering_display(const MppFrame frame); +void mpp_frame_set_mastering_display(MppFrame frame, MppFrameMasteringDisplayMetadata mastering_display); +MppFrameContentLightMetadata mpp_frame_get_content_light(const MppFrame frame); +void mpp_frame_set_content_light(MppFrame frame, MppFrameContentLightMetadata content_light); + +/* + * HDR parameter + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_FRAME_H__ */ diff --git a/hardware/mpp/include/mpp_hash.h b/hardware/mpp/include/mpp_hash.h new file mode 100644 index 0000000000000000000000000000000000000000..75b0e7a403039e57afb3b23ce7cb01abd0ed19b3 --- /dev/null +++ b/hardware/mpp/include/mpp_hash.h @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_HASH_H__ +#define __MPP_HASH_H__ + +#include + +#include "rk_type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GOLDEN_RATIO_32 0x61C88647 +#define GOLDEN_RATIO_64 0x61C8864680B583EBull + +#if __SIZEOF_POINTER__ == 4 +#define GOLDEN_RATIO_PRIME GOLDEN_RATIO_32 +#define hash_long(val, bits) hash_32(val, bits) +#elif __SIZEOF_POINTER__ == 8 +#define GOLDEN_RATIO_PRIME GOLDEN_RATIO_64 +#define hash_long(val, bits) hash_64(val, bits) +#else +#error __SIZEOF_POINTER__ not 4 or 8 +#endif + +struct hlist_node { + struct hlist_node *next, **pprev; +}; + +struct hlist_head { + struct hlist_node *first; +}; + +#define HLIST_HEAD_INIT { .first = NULL } +#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } +#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) + +#define LIST_POISON1 ((void *) 0x100) +#define LIST_POISON2 ((void *) 0x200) + +#define WRITE_ONCE(var, val) \ + (*((volatile typeof(val) *)(&(var))) = (val)) + +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) + +static inline void INIT_HLIST_NODE(struct hlist_node *h) +{ + h->next = NULL; + h->pprev = NULL; +} + +static inline int hlist_unhashed(const struct hlist_node *h) +{ + return !h->pprev; +} + +static inline int hlist_empty(const struct hlist_head *h) +{ + return !READ_ONCE(h->first); +} + +static inline void _hlist_del(struct hlist_node *n) +{ + struct hlist_node *next = n->next; + struct hlist_node **pprev = n->pprev; + + WRITE_ONCE(*pprev, next); + if (next) { + next->pprev = pprev; + } +} + +static inline void hlist_del(struct hlist_node *n) +{ + _hlist_del(n); + n->next = (struct hlist_node*)LIST_POISON1; + n->pprev = (struct hlist_node**)LIST_POISON2; +} + +static inline void hlist_del_init(struct hlist_node *n) +{ + if (!hlist_unhashed(n)) { + _hlist_del(n); + INIT_HLIST_NODE(n); + } +} + +static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) +{ + struct hlist_node *first = h->first; + n->next = first; + if (first) { + first->pprev = &n->next; + } + WRITE_ONCE(h->first, n); + n->pprev = &h->first; +} + +static inline void hlist_add_before(struct hlist_node *n, struct hlist_node *next) +{ + n->pprev = next->pprev; + n->next = next; + next->pprev = &n->next; + WRITE_ONCE(*(n->pprev), n); +} + +static inline void hlist_add_behind(struct hlist_node *n, struct hlist_node *prev) +{ + n->next = prev->next; + WRITE_ONCE(prev->next, n); + n->pprev = &prev->next; + + if (n->next) { + n->next->pprev = &n->next; + } +} + +static inline void hlist_add_fake(struct hlist_node *n) +{ + n->pprev = &n->next; +} + +static inline int hlist_fake(struct hlist_node *h) +{ + return h->pprev == &h->next; +} + +static inline int hlist_is_singular_node(struct hlist_node *n, struct hlist_head *h) +{ + return !n->next && n->pprev == &h->first; +} + +static inline void hlist_move_list(struct hlist_head *old, + struct hlist_head *_new) +{ + _new->first = old->first; + if (_new->first) { + _new->first->pprev = &_new->first; + } + old->first = NULL; +} + +#define hlist_entry(ptr, type, member) container_of(ptr, type, member) + +#define hlist_for_each(pos, head) \ + for ((pos) = (head)->first; (pos) ; (pos) = (pos)->next) + +#define hlist_for_each_safe(pos, n, head) \ + for ((pos) = (head)->first; (pos) && ( { n = (pos)->next; 1; } ); \ + (pos) = n) + +#define hlist_entry_safe(ptr, type, member) \ + ( { typeof(ptr) ____ptr = (ptr); \ + ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ + }) + +#define hlist_for_each_entry(pos, head, member) \ + for ((pos) = hlist_entry_safe((head)->first, typeof(*(pos)), member); \ + (pos); \ + (pos) = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#define hlist_for_each_entry_continue(pos, member) \ + for ((pos) = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member); \ + (pos); \ + (pos) = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#define hlist_for_each_entry_from(pos, member) \ + for (; (pos); \ + (pos) = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) + +#define hlist_for_each_entry_safe(pos, n, head, member) \ + for ((pos) = hlist_entry_safe((head)->first, typeof(*(pos)), member); \ + (pos) && ( { n = (pos)->member.next; 1; }); \ + (pos) = hlist_entry_safe(n, typeof(*(pos)), member)) + +#define DEFINE_HASHTABLE(name, bits) \ + struct hlist_head name[1 << (bits)] = \ + { [0 ... ((1 << (bits)) - 1)] = HLIST_HEAD_INIT } + +#define DECLARE_HASHTABLE(name, bits) \ + struct hlist_head name[1 << (bits)] + +#define ARRAY_SIZE(x) (sizeof((x)) / sizeof((x)[0])) + +#define ilog2(n) \ + ( \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + (n) & (1ULL << 1) ? 1 : 0 \ + ) + +#define HASH_SIZE(name) (ARRAY_SIZE(name)) +#define HASH_BITS(name) ilog2(HASH_SIZE(name)) + +/* Use hash_32 when possible to allow for fast 32bit hashing in 64bit kernels. */ +#define hash_min(val, bits) \ + (sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits)) + +#define hash_add(hashtable, node, key) \ + hlist_add_head(node, &(hashtable)[hash_min(key, HASH_BITS(hashtable))]) + +/** + * hash_empty - check whether a hashtable is empty + * @hashtable: hashtable to check + * + * This has to be a macro since HASH_BITS() will not work on pointers since + * it calculates the size during preprocessing. + */ +#define hash_empty(hashtable) __hash_empty(hashtable, HASH_SIZE(hashtable)) + +/** + * hash_for_each - iterate over a hashtable + * @name: hashtable to iterate + * @bkt: integer to use as bucket loop cursor + * @obj: the type * to use as a loop cursor for each entry + * @member: the name of the hlist_node within the struct + */ +#define hash_for_each(name, bkt, obj, member) \ + for ((bkt) = 0, (obj) = NULL; (obj) == NULL && (bkt) < HASH_SIZE(name); \ + (bkt)++) \ + hlist_for_each_entry((obj), &(name)[bkt], member) + +/** + * hash_for_each_safe - iterate over a hashtable safe against removal of + * hash entry + * @name: hashtable to iterate + * @bkt: integer to use as bucket loop cursor + * @tmp: a &struct used for temporary storage + * @obj: the type * to use as a loop cursor for each entry + * @member: the name of the hlist_node within the struct + */ +#define hash_for_each_safe(name, bkt, tmp, obj, member) \ + for ((bkt) = 0, (obj) = NULL; (obj) == NULL && (bkt) < HASH_SIZE(name); \ + (bkt)++) \ + hlist_for_each_entry_safe((obj), tmp, &(name)[bkt], member) + +#define hash_for_each_possible(name, obj, member, key) \ + hlist_for_each_entry((obj), &(name)[hash_min(key, HASH_BITS(name))], member) + +static inline RK_U32 hash_32(RK_U32 val, unsigned int bits) +{ + /* On some cpus multiply is faster, on others gcc will do shifts */ + RK_U32 hash = val * GOLDEN_RATIO_32; + + /* High bits are more random, so use them. */ + return hash >> (32 - bits); // 32:32bits +} + +static inline RK_U32 _hash_32(RK_U32 val) +{ + return val * GOLDEN_RATIO_32; +} + +static inline RK_U32 hash_64(RK_U64 val, unsigned int bits) +{ +#if __SIZEOF_POINTER__ == 8 // 8:sizeof pointer + /* 64x64-bit multiply is efficient on all 64-bit processors */ + return val * GOLDEN_RATIO_64 >> (64 - bits); +#else + /* Hash 64 bits using only 32x32-bit multiply. */ + return hash_32((RK_U32)val ^ ((val >> 32) * GOLDEN_RATIO_32), bits); +#endif +} + +static inline RK_U32 hash_ptr(const void *ptr, unsigned int bits) +{ + return hash_long((unsigned long)ptr, bits); +} + +/* This really should be called fold32_ptr; it does no hashing to speak of. */ +static inline RK_U32 hash32_ptr(const void *ptr) +{ + unsigned long val = (unsigned long)ptr; + +#if __SIZEOF_POINTER__ == 8 + val ^= (val >> 32); // 32:Shift 32 bits right +#endif + return (RK_U32)val; +} + +/** + * hash_hashed - check whether an object is in any hashtable + * @node: the &struct hlist_node of the object to be checked + */ +static inline bool hash_hashed(struct hlist_node *node) +{ + return !hlist_unhashed(node); +} + +static inline bool _hash_empty(struct hlist_head *ht, unsigned int sz) +{ + unsigned int i; + + for (i = 0; i < sz; i++) { + if (!hlist_empty(&ht[i])) { + return false; + } + } + return true; +} + +/** + * hash_del - remove an object from a hashtable + * @node: &struct hlist_node of the object to remove + */ +static inline void hash_del(struct hlist_node *node) +{ + hlist_del_init(node); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_HASH_H__ */ diff --git a/hardware/mpp/include/mpp_list.h b/hardware/mpp/include/mpp_list.h new file mode 100644 index 0000000000000000000000000000000000000000..fa169b5d1fd755d922759848249704c19c6c595b --- /dev/null +++ b/hardware/mpp/include/mpp_list.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_LIST_H__ +#define __MPP_LIST_H__ + +#include "rk_type.h" + +#include "mpp_thread.h" + +/* + * two list structures are defined, one for C++, the other for C + */ + +#ifdef __cplusplus + +// desctructor of list node +typedef void *(*node_destructor)(void *); + +struct mpp_list_node; + +class mpp_list : public MppMutexCond { +public: + mpp_list(node_destructor func = NULL); + ~mpp_list(); + + // for FIFO or FILO implement + // adding functions support simple structure like C struct or C++ class pointer, + // do not support C++ object + RK_S32 add_at_head(void *data, RK_S32 size); + RK_S32 add_at_tail(void *data, RK_S32 size); + // deleting function will copy the stored data to input pointer with size as size + // if NULL is passed to deleting functions, the node will be delete directly + RK_S32 del_at_head(void *data, RK_S32 size); + RK_S32 del_at_tail(void *data, RK_S32 size); + + // direct fifo operation + RK_S32 fifo_wr(void *data, RK_S32 size); + RK_S32 fifo_rd(void *data, RK_S32 *size); + + // for status check + RK_S32 list_is_empty(); + RK_S32 list_size(); + + // for vector implement - not implemented yet + // adding function will return a key + RK_S32 add_by_key(void *data, RK_S32 size, RK_U32 *key); + RK_S32 del_by_key(void *data, RK_S32 size, RK_U32 key); + RK_S32 show_by_key(void *data, RK_U32 key); + + RK_S32 flush(); + +private: + node_destructor destroy; + struct mpp_list_node *head; + RK_S32 count; + static RK_U32 keys; + static RK_U32 get_key(); + + mpp_list(const mpp_list &); + mpp_list &operator=(const mpp_list &); +}; +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +#define INIT_LIST_HEAD(ptr) do { \ + (ptr)->next = (ptr); (ptr)->prev = (ptr); \ + } while (0) + + +#define list_for_each_safe(pos, n, head) do { \ + for ((pos) = (head)->next, (n) = (pos)->next; (pos) != (head); \ + (pos) = (n), (n) = (pos)->next) \ + } while (0) + + +#define list_entry(ptr, type, member) \ + ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) + +#define list_first_entry(ptr, type, member) \ + list_entry((ptr)->next, type, member) + +#define list_last_entry(ptr, type, member) \ + list_entry((ptr)->prev, type, member) + +#define list_first_entry_or_null(ptr, type, member)({ \ + struct list_head *head__ = (ptr); \ + struct list_head *pos__ = head__->next; \ + pos__ != head__ ? list_entry(pos__, type, member) : NULL; \ +}) + +#define list_next_entry(pos, type, member) \ + list_entry((pos)->member.next, type, member) + +#define list_prev_entry(pos, type, member) \ + list_entry((pos)->member.prev, type, member) + +#define list_for_each_entry(pos, head, type, member) \ + for ((pos) = list_entry((head)->next, type, member); \ + &(pos)->member != (head); \ + (pos) = list_next_entry((pos), type, member)) + +#define list_for_each_entry_safe(pos, n, head, type, member) \ + for ((pos) = list_first_entry(head, type, member), \ + (n) = list_next_entry((pos), type, member); \ + &(pos)->member != (head); \ + (pos) = (n), (n) = list_next_entry(n, type, member)) + +#define list_for_each_entry_reverse(pos, head, type, member) \ + for ((pos) = list_last_entry(head, type, member); \ + &(pos)->member != (head); \ + (pos) = list_prev_entry((pos), type, member)) + +#define list_for_each_entry_safe_reverse(pos, n, head, type, member) \ + for ((pos) = list_last_entry(head, type, member), \ + (n) = list_prev_entry((pos), type, member); \ + &(pos)->member != (head); \ + (pos) = (n), (n) = list_prev_entry(n, type, member)) + +static __inline void _list_add(struct list_head * _new, + struct list_head * prev, + struct list_head * next) +{ + next->prev = _new; + _new->next = next; + _new->prev = prev; + prev->next = _new; +} + +static __inline void list_add(struct list_head *_new, struct list_head *head) +{ + _list_add(_new, head, head->next); +} + +static __inline void list_add_tail(struct list_head *_new, struct list_head *head) +{ + _list_add(_new, head->prev, head); +} + +static __inline void _list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} + +static __inline void list_del_init(struct list_head *entry) +{ + _list_del(entry->prev, entry->next); + + INIT_LIST_HEAD(entry); +} + +static __inline int list_is_last(const struct list_head *list, const struct list_head *head) +{ + return list->next == head; +} + +static __inline int list_empty(struct list_head *head) +{ + return head->next == head; +} + +#ifdef __cplusplus +} +#endif + + +#endif /* __MPP_LIST_H__ */ diff --git a/hardware/mpp/include/mpp_log.h b/hardware/mpp/include/mpp_log.h new file mode 100644 index 0000000000000000000000000000000000000000..f868f8e2244f3b4b0c7e3d0ae276464d1fc5afd7 --- /dev/null +++ b/hardware/mpp/include/mpp_log.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_LOG_H__ +#define __MPP_LOG_H__ + +#include +#include + +#include "rk_type.h" + +/* + * mpp runtime log system usage: + * mpp_err is for error status message, it will print for sure. + * mpp_log is for important message like open/close/reset/flush, it will print too. + * mpp_dbg is for all optional message. it can be controlled by debug and flag. + */ + +#define mpp_log(fmt, ...) _mpp_log(MODULE_TAG, fmt, NULL, ## __VA_ARGS__) +#define mpp_err(fmt, ...) _mpp_err(MODULE_TAG, fmt, NULL, ## __VA_ARGS__) + +#define _mpp_dbg(debug, flag, fmt, ...) \ + do { \ + if (debug & flag) \ + mpp_log(fmt, ## __VA_ARGS__); \ + } while (0) + +#define mpp_dbg(flag, fmt, ...) _mpp_dbg(mpp_debug, flag, fmt, ## __VA_ARGS__) + +/* + * _f function will add function name to the log + */ +#define mpp_log_f(fmt, ...) _mpp_log(MODULE_TAG, fmt, __FUNCTION__, ## __VA_ARGS__) +#define mpp_err_f(fmt, ...) _mpp_err(MODULE_TAG, fmt, __FUNCTION__, ## __VA_ARGS__) +#define _mpp_dbg_f(debug, flag, fmt, ...) \ + do { \ + if (debug & flag) \ + mpp_log_f(fmt, ## __VA_ARGS__); \ + } while (0) + +#define mpp_dbg_f(flag, fmt, ...) _mpp_dbg_f(mpp_debug, flag, fmt, ## __VA_ARGS__) + + +#define MPP_DBG_TIMING (0x00000001) +#define MPP_DBG_PTS (0x00000002) +#define MPP_DBG_INFO (0x00000004) +#define MPP_DBG_PLATFORM (0x00000010) + +#define MPP_DBG_DUMP_LOG (0x00000100) +#define MPP_DBG_DUMP_IN (0x00000200) +#define MPP_DBG_DUMP_OUT (0x00000400) +#define MPP_DBG_DUMP_CFG (0x00000800) + +#define mpp_dbg_pts(fmt, ...) mpp_dbg(MPP_DBG_PTS, fmt, ## __VA_ARGS__) +#define mpp_dbg_info(fmt, ...) mpp_dbg(MPP_DBG_INFO, fmt, ## __VA_ARGS__) +#define mpp_dbg_platform(fmt, ...) mpp_dbg(MPP_DBG_PLATFORM, fmt, ## __VA_ARGS__) + +#define MPP_ABORT (0x10000000) + +/* + * mpp_dbg usage: + * + * in h264d module define module debug flag variable like: h265d_debug + * then define h265d_dbg macro as follow : + * + * extern RK_U32 h265d_debug; + * + * #define H265D_DBG_FUNCTION (0x00000001) + * #define H265D_DBG_VPS (0x00000002) + * #define H265D_DBG_SPS (0x00000004) + * #define H265D_DBG_PPS (0x00000008) + * #define H265D_DBG_SLICE_HDR (0x00000010) + * + * #define h265d_dbg(flag, fmt, ...) mpp_dbg(h265d_debug, flag, fmt, ## __VA_ARGS__) + * + * finally use environment control the debug flag + * + * mpp_get_env_u32("h264d_debug", &h265d_debug, 0) + * + */ +/* + * sub-module debug flag usage example: + * +------+-------------------+ + * | 8bit | 24bit | + * +------+-------------------+ + * 0~15 bit: software debug print + * 16~23 bit: hardware debug print + * 24~31 bit: information print format + */ + +#define mpp_abort() do { \ + if (mpp_debug & MPP_ABORT) { \ + abort(); \ + } \ +} while (0) + +#define MPP_STRINGS(x) MPP_TO_STRING(x) +#define MPP_TO_STRING(x) #x + +#define mpp_assert(cond) do { \ + if (!(cond)) { \ + mpp_err("Assertion %s failed at %s:%d\n", \ + MPP_STRINGS(cond), __FUNCTION__, __LINE__); \ + mpp_abort(); \ + } \ +} while (0) + + +#ifdef __cplusplus +extern "C" { +#endif + +extern RK_U32 mpp_debug; + +void mpp_log_set_flag(RK_U32 flag); +RK_U32 mpp_log_get_flag(void); + +void _mpp_log(const char *tag, const char *fmt, const char *func, ...); +void _mpp_err(const char *tag, const char *fmt, const char *func, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_LOG_H__ */ diff --git a/hardware/mpp/include/mpp_mem.h b/hardware/mpp/include/mpp_mem.h new file mode 100644 index 0000000000000000000000000000000000000000..a884899627763f4b24a193af9e5f92accc08112a --- /dev/null +++ b/hardware/mpp/include/mpp_mem.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_MEM_H__ +#define __MPP_MEM_H__ + +#include + +#include "rk_type.h" +#include "mpp_err.h" + +#define mpp_malloc_with_caller(type, count, caller) \ + (type*)mpp_osal_malloc(caller, sizeof(type) * (count)) + +#define mpp_malloc(type, count) \ + (type*)mpp_osal_malloc(__FUNCTION__, sizeof(type) * (count)) + +#define mpp_malloc_size(type, size) \ + (type*)mpp_osal_malloc(__FUNCTION__, size) + +#define mpp_calloc_size(type, size) \ + (type*)mpp_osal_calloc(__FUNCTION__, size) + +#define mpp_calloc(type, count) \ + (type*)mpp_osal_calloc(__FUNCTION__, sizeof(type) * (count)) + +#define mpp_realloc(ptr, type, count) \ + (type*)mpp_osal_realloc(__FUNCTION__, ptr, sizeof(type) * (count)) + +#define mpp_free(ptr) \ + mpp_osal_free(__FUNCTION__, ptr) + +#define MPP_FREE(ptr) do { if (ptr) mpp_free(ptr); ptr = NULL; } while (0) +#define MPP_FCLOSE(fp) do { if (fp) fclose(fp); fp = NULL; } while (0) + +#ifdef __cplusplus +extern "C" { +#endif + +void *mpp_osal_malloc(const char *caller, size_t size); +void *mpp_osal_calloc(const char *caller, size_t size); +void *mpp_osal_realloc(const char *caller, void *ptr, size_t size); +void mpp_osal_free(const char *caller, void *ptr); + +void mpp_show_mem_status(void); +RK_U32 mpp_mem_total_now(void); +RK_U32 mpp_mem_total_max(void); + +/* + * mpp memory usage snapshot tool + * + * usage: + * call mpp_mem_get_snapshot on context init get one snapshot + * call mpp_mem_get_snapshot on context deinit get another snapshot + * call mpp_mem_diff_snapshot to show the difference between these two snapshot + * call mpp_mem_put_snapshot twice to release these two snapshot + */ +typedef void* MppMemSnapshot; + +MPP_RET mpp_mem_get_snapshot(MppMemSnapshot *hnd); +MPP_RET mpp_mem_put_snapshot(MppMemSnapshot *hnd); +MPP_RET mpp_mem_squash_snapshot(MppMemSnapshot hnd0, MppMemSnapshot hnd1); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_MEM_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_mem_pool.h b/hardware/mpp/include/mpp_mem_pool.h new file mode 100644 index 0000000000000000000000000000000000000000..ea890a4df71eff2d08b3397c053182d55d510433 --- /dev/null +++ b/hardware/mpp/include/mpp_mem_pool.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_MEM_POOL_H__ +#define __MPP_MEM_POOL_H__ + +#include +#include "mpp_mem.h" +#include "mpp_common.h" + +typedef void* MppMemPool; + +#ifdef __cplusplus +extern "C" { +#endif + +MppMemPool mpp_mem_pool_init(size_t size); +void mpp_mem_pool_deinit(MppMemPool pool); + +void *mpp_mem_pool_get(MppMemPool pool); +void mpp_mem_pool_put(MppMemPool pool, void *p); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_MEM_POOL_H__ */ diff --git a/hardware/mpp/include/mpp_meta.h b/hardware/mpp/include/mpp_meta.h new file mode 100644 index 0000000000000000000000000000000000000000..7b1f9599aecf5692858420dd5fe3dd11e262047e --- /dev/null +++ b/hardware/mpp/include/mpp_meta.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_META_H__ +#define __MPP_META_H__ + +#include +#include "rk_type.h" + +#define FOURCC_META(a, b, c, d) ((RK_U32)(a) << 24 | \ + ((RK_U32)(b) << 16) | \ + ((RK_U32)(c) << 8) | \ + ((RK_U32)(d) << 0)) + +/* + * Mpp Metadata definition + * + * Metadata is for information transmision in mpp. + * Mpp task will contain two meta data: + * + * 1. Data flow metadata + * This metadata contains information of input / output data flow. For example + * A. decoder input side task the input packet must be defined and output frame + * may not be defined. Then decoder will try malloc or use committed buffer to + * complete decoding. + * B. decoder output side task + * + * + * 2. Flow control metadata + * + */ +typedef enum MppMetaDataType_e { + /* + * mpp meta data of data flow + * reference counter will be used for these meta data type + */ + TYPE_FRAME = FOURCC_META('m', 'f', 'r', 'm'), + TYPE_PACKET = FOURCC_META('m', 'p', 'k', 't'), + TYPE_BUFFER = FOURCC_META('m', 'b', 'u', 'f'), + + /* mpp meta data of normal data type */ + TYPE_S32 = FOURCC_META('s', '3', '2', ' '), + TYPE_S64 = FOURCC_META('s', '6', '4', ' '), + TYPE_PTR = FOURCC_META('p', 't', 'r', ' '), +} MppMetaType; + +typedef enum MppMetaKey_e { + /* data flow key */ + KEY_INPUT_FRAME = FOURCC_META('i', 'f', 'r', 'm'), + KEY_INPUT_PACKET = FOURCC_META('i', 'p', 'k', 't'), + KEY_OUTPUT_FRAME = FOURCC_META('o', 'f', 'r', 'm'), + KEY_OUTPUT_PACKET = FOURCC_META('o', 'p', 'k', 't'), + /* output motion information for motion detection */ + KEY_MOTION_INFO = FOURCC_META('m', 'v', 'i', 'f'), + KEY_HDR_INFO = FOURCC_META('h', 'd', 'r', ' '), + + /* flow control key */ + KEY_INPUT_BLOCK = FOURCC_META('i', 'b', 'l', 'k'), + KEY_OUTPUT_BLOCK = FOURCC_META('o', 'b', 'l', 'k'), + KEY_INPUT_IDR_REQ = FOURCC_META('i', 'i', 'd', 'r'), /* input idr frame request flag */ + KEY_OUTPUT_INTRA = FOURCC_META('o', 'i', 'd', 'r'), /* output intra frame indicator */ + + /* mpp_frame / mpp_packet meta data info key */ + KEY_TEMPORAL_ID = FOURCC_META('t', 'l', 'i', 'd'), + KEY_LONG_REF_IDX = FOURCC_META('l', 't', 'i', 'd'), + KEY_ENC_AVERAGE_QP = FOURCC_META('a', 'v', 'g', 'q'), + KEY_ROI_DATA = FOURCC_META('r', 'o', 'i', ' '), + KEY_OSD_DATA = FOURCC_META('o', 's', 'd', ' '), + KEY_OSD_DATA2 = FOURCC_META('o', 's', 'd', '2'), + KEY_USER_DATA = FOURCC_META('u', 's', 'r', 'd'), + KEY_USER_DATAS = FOURCC_META('u', 'r', 'd', 's'), + + /* input motion list for smart p rate control */ + KEY_MV_LIST = FOURCC_META('m', 'v', 'l', 't'), + + /* frame long-term reference frame operation */ + KEY_ENC_MARK_LTR = FOURCC_META('m', 'l', 't', 'r'), + KEY_ENC_USE_LTR = FOURCC_META('u', 'l', 't', 'r'), + + /* MLVEC specified encoder feature */ + KEY_ENC_FRAME_QP = FOURCC_META('f', 'r', 'm', 'q'), + KEY_ENC_BASE_LAYER_PID = FOURCC_META('b', 'p', 'i', 'd'), +} MppMetaKey; + +#define mpp_meta_get(meta) mpp_meta_get_with_tag(meta, MODULE_TAG, __FUNCTION__) + +#include "mpp_frame.h" + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_meta_get_with_tag(MppMeta *meta, const char *tag, const char *caller); +MPP_RET mpp_meta_put(MppMeta meta); +RK_S32 mpp_meta_size(MppMeta meta); + +MPP_RET mpp_meta_set_s32(MppMeta meta, MppMetaKey key, RK_S32 val); +MPP_RET mpp_meta_set_s64(MppMeta meta, MppMetaKey key, RK_S64 val); +MPP_RET mpp_meta_set_ptr(MppMeta meta, MppMetaKey key, void *val); +MPP_RET mpp_meta_get_s32(MppMeta meta, MppMetaKey key, RK_S32 *val); +MPP_RET mpp_meta_get_s64(MppMeta meta, MppMetaKey key, RK_S64 *val); +MPP_RET mpp_meta_get_ptr(MppMeta meta, MppMetaKey key, void **val); + +MPP_RET mpp_meta_set_frame (MppMeta meta, MppMetaKey key, MppFrame frame); +MPP_RET mpp_meta_set_packet(MppMeta meta, MppMetaKey key, MppPacket packet); +MPP_RET mpp_meta_set_buffer(MppMeta meta, MppMetaKey key, MppBuffer buffer); +MPP_RET mpp_meta_get_frame (MppMeta meta, MppMetaKey key, MppFrame *frame); +MPP_RET mpp_meta_get_packet(MppMeta meta, MppMetaKey key, MppPacket *packet); +MPP_RET mpp_meta_get_buffer(MppMeta meta, MppMetaKey key, MppBuffer *buffer); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_META_H__ */ diff --git a/hardware/mpp/include/mpp_packet.h b/hardware/mpp/include/mpp_packet.h new file mode 100644 index 0000000000000000000000000000000000000000..72b27843fc9d37c237543aef67f6f1a4508b4be5 --- /dev/null +++ b/hardware/mpp/include/mpp_packet.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_PACKET_H__ +#define __MPP_PACKET_H__ + +#include "mpp_meta.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * MppPacket interface + * + * mpp_packet_init = mpp_packet_new + mpp_packet_set_data + mpp_packet_set_size + * mpp_packet_copy_init = mpp_packet_init + memcpy + */ +MPP_RET mpp_packet_new(MppPacket *packet); +MPP_RET mpp_packet_init(MppPacket *packet, void *data, size_t size); +MPP_RET mpp_packet_init_with_buffer(MppPacket *packet, MppBuffer buffer); +MPP_RET mpp_packet_copy_init(MppPacket *packet, const MppPacket src); +MPP_RET mpp_packet_deinit(MppPacket *packet); + +/* + * data : ( R/W ) start address of the whole packet memory + * size : ( R/W ) total size of the whole packet memory + * pos : ( R/W ) current access position of the whole packet memory, used for buffer read/write + * length : ( R/W ) the rest length from current position to end of buffer + * NOTE: normally length is updated only by set_pos, + * so set length must be used carefully for special usage + */ +void mpp_packet_set_data(MppPacket packet, void *data); +void mpp_packet_set_size(MppPacket packet, size_t size); +void mpp_packet_set_pos(MppPacket packet, void *pos); +void mpp_packet_set_length(MppPacket packet, size_t size); + +void* mpp_packet_get_data(const MppPacket packet); +void* mpp_packet_get_pos(const MppPacket packet); +size_t mpp_packet_get_size(const MppPacket packet); +size_t mpp_packet_get_length(const MppPacket packet); + + +void mpp_packet_set_pts(MppPacket packet, RK_S64 pts); +RK_S64 mpp_packet_get_pts(const MppPacket packet); +void mpp_packet_set_dts(MppPacket packet, RK_S64 dts); +RK_S64 mpp_packet_get_dts(const MppPacket packet); + +void mpp_packet_set_flag(MppPacket packet, RK_U32 flag); +RK_U32 mpp_packet_get_flag(const MppPacket packet); + +MPP_RET mpp_packet_set_eos(MppPacket packet); +MPP_RET mpp_packet_clr_eos(MppPacket packet); +RK_U32 mpp_packet_get_eos(MppPacket packet); +MPP_RET mpp_packet_set_extra_data(MppPacket packet); + +void mpp_packet_set_buffer(MppPacket packet, MppBuffer buffer); +MppBuffer mpp_packet_get_buffer(const MppPacket packet); + +/* + * data access interface + */ +MPP_RET mpp_packet_read(MppPacket packet, size_t offset, void *data, size_t size); +MPP_RET mpp_packet_write(MppPacket packet, size_t offset, void *data, size_t size); + +/* + * meta data access interface + */ +RK_S32 mpp_packet_has_meta(const MppPacket packet); +MppMeta mpp_packet_get_meta(const MppPacket packet); + +/* + * multi packet sequence interface for slice/split encoding/decoding + * partition - the packet is a part of a while image + * soi - Start Of Image + * eoi - End Of Image + */ +RK_U32 mpp_packet_is_partition(const MppPacket packet); +RK_U32 mpp_packet_is_soi(const MppPacket packet); +RK_U32 mpp_packet_is_eoi(const MppPacket packet); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_PACKET_H__ */ diff --git a/hardware/mpp/include/mpp_platform.h b/hardware/mpp/include/mpp_platform.h new file mode 100644 index 0000000000000000000000000000000000000000..bcf22c43be76bbd4e3a07e613cbb3e452941b683 --- /dev/null +++ b/hardware/mpp/include/mpp_platform.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_PLATFORM__ +#define __MPP_PLATFORM__ + +#include "rk_type.h" +#include "mpp_soc.h" + +/* + * Platform flag detection is for rockchip hardware platform detection + */ +typedef enum MppIoctlVersion_e { + IOCTL_VCODEC_SERVICE, + IOCTL_MPP_SERVICE_V1, + IOCTL_VERSION_BUTT, +} MppIoctlVersion; + +typedef enum MppKernelVersion_e { + KERNEL_UNKNOWN, + KERNEL_3_10, + KERNEL_4_4, + KERNEL_4_19, + KERNEL_VERSION_BUTT, +} MppKernelVersion; + +#ifdef __cplusplus +extern "C" { +#endif + +MppIoctlVersion mpp_get_ioctl_version(void); +MppKernelVersion mpp_get_kernel_version(void); +RK_U32 mpp_get_2d_hw_flag(void); +RK_U32 mpp_get_client_hw_id(RK_S32 client_type); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_PLATFORM__ */ diff --git a/hardware/mpp/include/mpp_queue.h b/hardware/mpp/include/mpp_queue.h new file mode 100755 index 0000000000000000000000000000000000000000..607842766eb552b670e75bf9903561876fa5a810 --- /dev/null +++ b/hardware/mpp/include/mpp_queue.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_QUEUE_H__ +#define __MPP_QUEUE_H__ + +#include "mpp_list.h" + +class MppQueue : public mpp_list { +public: + MppQueue(node_destructor func); + ~MppQueue(); + RK_S32 push(void *data, RK_S32 size); + RK_S32 pull(void *data, RK_S32 size); + RK_S32 flush(); +private: + sem_t mQueuePending; + int mFlushFlag; +}; + +#endif diff --git a/hardware/mpp/include/mpp_rc_api.h b/hardware/mpp/include/mpp_rc_api.h new file mode 100644 index 0000000000000000000000000000000000000000..397b57960e41c5e70294848e3de41676fd1a9e00 --- /dev/null +++ b/hardware/mpp/include/mpp_rc_api.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_RC_API_H__ +#define __MPP_RC_API_H__ + +#include "mpp_err.h" +#include "rk_venc_rc.h" +#include "mpp_rc_defs.h" + +/* + * Mpp rate control has three parts: + * + * 1. MPI user config module + * MppEncRcCfg structure is provided to user for overall rate control config + * Mpp will receive MppEncRcCfg from user, check parameter and set it to + * encoder. + * + * 2. Encoder rate control module + * Encoder will implement the rate control strategy required by users + * including CBR, VBR, AVBR and so on. + * This module only implement the target bit calculation behavior and + * quality restriction. And the quality level will be controlled by hal. + * + * 3. Hal rate control module + * Hal will implement the rate control on hardware. Hal will calculate the + * QP parameter for hardware according to the frame level target bit + * specified by the encoder. And the report the real bitrate and quality to + * encoder. + * + * The header defines the communication interfaces and structures used between + * MPI, encoder and hal. + */ + +typedef enum RcMode_e { + RC_VBR, + RC_CBR, + RC_FIXQP, + RC_AVBR, + RC_CVBR, + RC_QVBR, + RC_LEARNING, + RC_MODE_BUTT, +} RcMode; + +typedef enum GopMode_e { + NORMAL_P, + SMART_P, +} GopMode; + +/* + * frame rate parameters have great effect on rate control + * + * fps_in_flex + * 0 - fix input frame rate + * 1 - variable input frame rate + * + * fps_in_num + * input frame rate numerator, if 0 then default 30 + * + * fps_in_denorm + * input frame rate denorminator, if 0 then default 1 + * + * fps_out_flex + * 0 - fix output frame rate + * 1 - variable output frame rate + * + * fps_out_num + * output frame rate numerator, if 0 then default 30 + * + * fps_out_denorm + * output frame rate denorminator, if 0 then default 1 + */ +typedef struct RcFpsCfg_t { + RK_S32 fps_in_flex; + RK_S32 fps_in_num; + RK_S32 fps_in_denorm; + RK_S32 fps_out_flex; + RK_S32 fps_out_num; + RK_S32 fps_out_denorm; +} RcFpsCfg; + +typedef struct RcSuperframeCfg_t { + MppEncRcSuperFrameMode super_mode; + RK_U32 super_i_thd; + RK_U32 super_p_thd; + MppEncRcPriority rc_priority; +} RcSuperframeCfg; + +typedef struct RcDebreathCfg_t { + RK_U32 enable; + RK_U32 strength; +} RcDebreathCfg; + +typedef struct RcHierQPCfg_t { + RK_S32 hier_qp_en; + RK_S32 hier_qp_delta[4]; + RK_S32 hier_frame_num[4]; +} RcHierQPCfg; + +/* + * Control parameter from external config + * + * It will be updated on rc/prep/gopref config changed. + */ +typedef struct RcCfg_s { + /* encode image size */ + RK_S32 width; + RK_S32 height; + + /* Use rc_mode to find different api */ + RcMode mode; + + RcFpsCfg fps; + + GopMode gop_mode; + /* I frame gop len */ + RK_S32 igop; + /* visual gop len */ + RK_S32 vgop; + + /* bitrate parameter */ + RK_S32 bps_min; + RK_S32 bps_target; + RK_S32 bps_max; + RK_S32 stats_time; + + /* max I frame bit ratio to P frame bit */ + RK_S32 max_i_bit_prop; + RK_S32 min_i_bit_prop; + RK_S32 init_ip_ratio; + /* layer bitrate proportion */ + RK_S32 layer_bit_prop[4]; + + /* quality parameter */ + RK_S32 init_quality; + RK_S32 max_quality; + RK_S32 min_quality; + RK_S32 max_i_quality; + RK_S32 min_i_quality; + RK_S32 i_quality_delta; + RK_S32 vi_quality_delta; + /* layer quality proportion */ + RK_S32 layer_quality_delta[4]; + + /* reencode parameter */ + RK_S32 max_reencode_times; + + /* still / motion desision parameter */ + RK_S32 min_still_prop; + RK_S32 max_still_quality; + + /* + * vbr parameter + * + * vbr_hi_prop - high proportion bitrate for reduce quality + * vbr_lo_prop - low proportion bitrate for increase quality + */ + RK_S32 vbr_hi_prop; + RK_S32 vbr_lo_prop; + + MppEncRcDropFrmMode drop_mode; + RK_U32 drop_thd; + RK_U32 drop_gap; + + RcSuperframeCfg super_cfg; + RcDebreathCfg debreath_cfg; + RcHierQPCfg hier_qp_cfg; +} RcCfg; + +/* + * Different rate control strategy will be implemented by different API config + */ +typedef struct RcImplApi_t { + char *name; + MppCodingType type; + RK_U32 ctx_size; + + MPP_RET (*init)(void *ctx, RcCfg *cfg); + MPP_RET (*deinit)(void *ctx); + + MPP_RET (*check_drop)(void *ctx, EncRcTask *task); + MPP_RET (*check_reenc)(void *ctx, EncRcTask *task); + + /* + * frm_start - frame level rate control frm_start. + * The EncRcTaskInfo will be output to hal for hardware to implement. + * frm_end - frame level rate control frm_end. + * The EncRcTaskInfo is returned for real quality and bitrate. + */ + MPP_RET (*frm_start)(void *ctx, EncRcTask *task); + MPP_RET (*frm_end)(void *ctx, EncRcTask *task); + + /* + * hal_start - hardware level rate control start. + * The EncRcTaskInfo will be output to hal for hardware to implement. + * hal_end - hardware level rate control end. + * The EncRcTaskInfo is returned for real quality and bitrate. + */ + MPP_RET (*hal_start)(void *ctx, EncRcTask *task); + MPP_RET (*hal_end)(void *ctx, EncRcTask *task); +} RcImplApi; + +/* + * structures for RC API register and query + */ +typedef struct RcApiBrief_t { + const char *name; + MppCodingType type; +} RcApiBrief; + +typedef struct RcApiQueryAll_t { + /* input param for query */ + RcApiBrief *brief; + RK_S32 max_count; + + /* output query count */ + RK_S32 count; +} RcApiQueryAll; + +typedef struct RcApiQueryType_t { + /* input param for query */ + RcApiBrief *brief; + RK_S32 max_count; + MppCodingType type; + + /* output query count */ + RK_S32 count; +} RcApiQueryType; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET rc_api_add(const RcImplApi *api); +MPP_RET rc_brief_get_all(RcApiQueryAll *query); +MPP_RET rc_brief_get_by_type(RcApiQueryType *query); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_RC_API_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_rc_defs.h b/hardware/mpp/include/mpp_rc_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..57ad2a8d62bfac01e6362bc7041990b2b5b5014c --- /dev/null +++ b/hardware/mpp/include/mpp_rc_defs.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_RC_DEFS_H__ +#define __MPP_RC_DEFS_H__ + +#include "rk_venc_ref.h" + +#define MAX_CPB_REFS (8) + +/* + * EncFrmStatus controls record the encoding frame status and also control + * work flow of encoder. It is the communicat channel between encoder implement + * module, rate control module and hardware module. + * + * bit 0 ~ 31 frame status + * 0 ~ 15 current frame status + * 16 ~ 31 reference frame status + * bit 32 ~ 63 encoding flow control + */ +typedef union EncFrmStatus_u { + struct { + /* + * bit 0 ~ 31 frame status + */ + /* status flag */ + RK_U32 valid : 1; + /* + * 0 - write the reconstructed frame pixel to memory + * 1 - do not write the reconstructed frame pixel to memory + */ + RK_U32 non_recn : 1; + RK_U32 reserved0 : 2; + + /* reference status flag */ + /* + * 0 - inter frame + * 1 - intra frame + */ + RK_U32 is_intra : 1; + + /* + * Valid when is_intra is true + * 0 - normal intra frame + * 1 - IDR frame + */ + RK_U32 is_idr : 1; + + /* + * 0 - mark as reference frame + * 1 - mark as non-refernce frame + */ + RK_U32 is_non_ref : 1; + + /* + * Valid when is_non_ref is false + * 0 - mark as short-term reference frame + * 1 - mark as long-term refernce frame + */ + RK_U32 is_lt_ref : 1; + + /* bit 8 - 15 */ + RK_U32 lt_idx : 4; + RK_U32 temporal_id : 4; + + /* distance between current frame and reference frame */ + MppEncRefMode ref_mode : 6; + RK_S32 ref_arg : 8; + RK_S32 ref_dist : 2; + + /* + * bit 32 ~ 63 encoder flow control flags + */ + /* + * 0 - normal frame encoding + * 1 - current frame will be dropped + */ + RK_U32 drop : 1; + + /* + * 0 - rate control module does not change frame type parameter + * 1 - rate control module changes frame type parameter reencode is needed + * to reprocess the dpb process. Also this means dpb module will follow + * the frame status parameter provided by rate control module. + */ + RK_U32 re_dpb_proc : 1; + + /* + * 0 - current frame encoding is in normal flow + * 1 - current frame encoding is in reencode flow + */ + RK_U32 reencode : 1; + + /* + * When true current frame size is super large then the frame should be reencoded. + */ + RK_U32 super_frame : 1; + + /* + * When true currnet frame is force to encoded as software skip frame + */ + RK_U32 force_pskip : 1; + RK_U32 reserved1 : 3; + + /* reencode times */ + RK_U32 reencode_times : 8; + + /* sequential index for each frame */ + RK_U32 seq_idx : 16; + }; + RK_U64 val; +} EncFrmStatus; + +typedef struct EncCpbStatus_t { + RK_S32 seq_idx; + + EncFrmStatus curr; + EncFrmStatus refr; + + /* initial cpb status for current frame encoding */ + EncFrmStatus init[MAX_CPB_REFS]; + /* final cpb status after current frame encoding */ + EncFrmStatus final[MAX_CPB_REFS]; +} EncCpbStatus; + +#define ENC_RC_FORCE_QP (0x00000001) + +typedef struct EncRcForceCfg_t { + RK_U32 force_flag; + RK_S32 force_qp; + RK_U32 reserve[6]; +} EncRcForceCfg; + +/* + * communication channel between rc / hal / hardware + * + * rc -> hal bit_target / bit_max / bit_min + * hal -> hw quality_target / quality_max / quality_min + * hw -> rc / hal bit_real / quality_real / madi / madp + */ +typedef struct EncRcCommonInfo_t { + /* rc to hal */ + RK_S32 bit_target; + RK_S32 bit_max; + RK_S32 bit_min; + + RK_S32 quality_target; + RK_S32 quality_max; + RK_S32 quality_min; + + /* rc from hardware */ + RK_S32 bit_real; + RK_S32 quality_real; + RK_S32 madi; + RK_S32 madp; + + RK_U32 iblk4_prop; // scale 256 + RK_S32 reserve[15]; +} EncRcTaskInfo; + +typedef struct EncRcTask_s { + EncCpbStatus cpb; + EncFrmStatus frm; + EncRcTaskInfo info; + EncRcForceCfg force; + MppFrame frame; +} EncRcTask; + +#endif /* __MPP_RC_DEFS_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_runtime.h b/hardware/mpp/include/mpp_runtime.h new file mode 100644 index 0000000000000000000000000000000000000000..ef8a337cd09d700be2e22cb3579f0f5a2f9cb807 --- /dev/null +++ b/hardware/mpp/include/mpp_runtime.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_RUNTIME__ +#define __MPP_RUNTIME__ + +#include "mpp_buffer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Runtime function detection is to support different binary on different + * runtime environment. This is usefull on product environemnt. + */ +RK_U32 mpp_rt_allcator_is_valid(MppBufferType type); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_RUNTIME__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_server.h b/hardware/mpp/include/mpp_server.h new file mode 100644 index 0000000000000000000000000000000000000000..049b8871dcb66127dc15612fb47bb7e02fc2cfbe --- /dev/null +++ b/hardware/mpp/include/mpp_server.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_SERVER_H__ +#define __MPP_SERVER_H__ + +#include "mpp_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_server_attach(MppDev ctx); +MPP_RET mpp_server_detach(MppDev ctx); + +MPP_RET mpp_server_send_task(MppDev ctx); +MPP_RET mpp_server_wait_task(MppDev ctx, RK_S64 timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_SERVER_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_service.h b/hardware/mpp/include/mpp_service.h new file mode 100644 index 0000000000000000000000000000000000000000..89bc40f82d7acd456dfd4720ce8d03fcfd02fd70 --- /dev/null +++ b/hardware/mpp/include/mpp_service.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_SERVICE_H__ +#define __MPP_SERVICE_H__ + +#include +#include "rk_type.h" + +/* Use 'v' as magic number */ +#define MPP_IOC_MAGIC 'v' +#define MPP_IOC_CFG_V1 _IOW(MPP_IOC_MAGIC, 1, unsigned int) +#define MAX_REQ_NUM 16 + +#if __SIZEOF_POINTER__ == 4 +#define REQ_DATA_PTR(ptr) ((RK_U32)(ptr)) +#elif __SIZEOF_POINTER__ == 8 +#define REQ_DATA_PTR(ptr) ((RK_U64)(ptr)) +#endif + +/* define flags for mpp_request */ +#define MPP_FLAGS_MULTI_MSG (0x00000001) +#define MPP_FLAGS_LAST_MSG (0x00000002) +#define MPP_FLAGS_REG_FD_NO_TRANS (0x00000004) +#define MPP_FLAGS_SCL_FD_NO_TRANS (0x00000008) +#define MPP_FLAGS_REG_OFFSET_ALONE (0x00000010) +#define MPP_FLAGS_POLL_NON_BLOCK (0x00000020) +#define MPP_FLAGS_SECURE_MODE (0x00010000) + +/* mpp service capability description */ +typedef enum MppDevCmd_e { + MPP_DEV_GET_START = 0, + MPP_DEV_GET_MAX_WIDTH, + MPP_DEV_GET_MAX_HEIGHT, + MPP_DEV_GET_MIN_WIDTH, + MPP_DEV_GET_MIN_HEIGHT, + MPP_DEV_GET_MMU_STATUS, + + MPP_DEV_SET_START = 0x01000000, + MPP_DEV_SET_HARD_PLATFORM, // set paltform by user + MPP_DEV_ENABLE_POSTPROCCESS, + + MPP_DEV_PROP_BUTT, +} MppDevCmd; + +typedef enum MppServiceCmdType_e { + MPP_CMD_QUERY_BASE = 0, + MPP_CMD_PROBE_HW_SUPPORT = MPP_CMD_QUERY_BASE + 0, + MPP_CMD_QUERY_HW_ID = MPP_CMD_QUERY_BASE + 1, + MPP_CMD_QUERY_CMD_SUPPORT = MPP_CMD_QUERY_BASE + 2, + MPP_CMD_QUERY_BUTT, + + MPP_CMD_INIT_BASE = 0x100, + MPP_CMD_INIT_CLIENT_TYPE = MPP_CMD_INIT_BASE + 0, + MPP_CMD_INIT_DRIVER_DATA = MPP_CMD_INIT_BASE + 1, + MPP_CMD_INIT_TRANS_TABLE = MPP_CMD_INIT_BASE + 2, + MPP_CMD_INIT_BUTT, + + MPP_CMD_SEND_BASE = 0x200, + MPP_CMD_SET_REG_WRITE = MPP_CMD_SEND_BASE + 0, + MPP_CMD_SET_REG_READ = MPP_CMD_SEND_BASE + 1, + MPP_CMD_SET_REG_ADDR_OFFSET = MPP_CMD_SEND_BASE + 2, + MPP_CMD_SET_RCB_INFO = MPP_CMD_SEND_BASE + 3, + /* for batch process start a task of one session */ + MPP_CMD_SET_SESSION_FD = MPP_CMD_SEND_BASE + 4, + MPP_CMD_SEND_BUTT, + + MPP_CMD_POLL_BASE = 0x300, + MPP_CMD_POLL_HW_FINISH = MPP_CMD_POLL_BASE + 0, + MPP_CMD_POLL_BUTT, + + MPP_CMD_CONTROL_BASE = 0x400, + MPP_CMD_RESET_SESSION = MPP_CMD_CONTROL_BASE + 0, + MPP_CMD_TRANS_FD_TO_IOVA = MPP_CMD_CONTROL_BASE + 1, + MPP_CMD_RELEASE_FD = MPP_CMD_CONTROL_BASE + 2, + MPP_CMD_SEND_CODEC_INFO = MPP_CMD_CONTROL_BASE + 3, + MPP_CMD_BAT_CMD = MPP_CMD_CONTROL_BASE + 4, + MPP_CMD_CONTROL_BUTT, + + MPP_CMD_BUTT, +} MppServiceCmdType; + +typedef struct mppReqV1_t { + RK_U32 cmd; + RK_U32 flag; + RK_U32 size; + RK_U32 offset; + RK_U64 data_ptr; +} MppReqV1; + +typedef struct MppServiceCmdCap_t { + RK_U32 support_cmd; + RK_U32 query_cmd; + RK_U32 init_cmd; + RK_U32 send_cmd; + RK_U32 poll_cmd; + RK_U32 ctrl_cmd; +} MppServiceCmdCap; + +#ifdef __cplusplus +extern "C" { +#endif + +void check_mpp_service_cap(RK_U32 *codec_type, RK_U32 *hw_ids, MppServiceCmdCap *cap); +const MppServiceCmdCap *mpp_get_mpp_service_cmd_cap(void); +const char *mpp_get_mpp_service_name(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_SERVICE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_service_api.h b/hardware/mpp/include/mpp_service_api.h new file mode 100644 index 0000000000000000000000000000000000000000..6b861b0a8aa795a44cbd5c974aaa5f2e89e39672 --- /dev/null +++ b/hardware/mpp/include/mpp_service_api.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_SERVICE_API_H__ +#define __MPP_SERVICE_API_H__ + +#include "mpp_device.h" + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_SERVICE_API_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_soc.h b/hardware/mpp/include/mpp_soc.h new file mode 100644 index 0000000000000000000000000000000000000000..14d7f2c222c23a4dea98796242f4fb8517843067 --- /dev/null +++ b/hardware/mpp/include/mpp_soc.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_SOC_H__ +#define __MPP_SOC_H__ + +#include "mpp_dev_defs.h" + +/* Do NOT use this outside MPP it may be changed in new version */ +typedef enum RockchipSocType_e { + ROCKCHIP_SOC_AUTO, + ROCKCHIP_SOC_RK3036, + ROCKCHIP_SOC_RK3066, + ROCKCHIP_SOC_RK3188, + ROCKCHIP_SOC_RK3288, + ROCKCHIP_SOC_RK312X, + ROCKCHIP_SOC_RK3368, + ROCKCHIP_SOC_RK3399, + ROCKCHIP_SOC_RK3228H, + ROCKCHIP_SOC_RK3328, + ROCKCHIP_SOC_RK3228, + ROCKCHIP_SOC_RK3229, + ROCKCHIP_SOC_RV1108, + ROCKCHIP_SOC_RV1109, + ROCKCHIP_SOC_RV1126, + ROCKCHIP_SOC_RK3326, + ROCKCHIP_SOC_RK3128H, + ROCKCHIP_SOC_PX30, + ROCKCHIP_SOC_RK1808, + ROCKCHIP_SOC_RK3566, + ROCKCHIP_SOC_RK3568, + ROCKCHIP_SOC_BUTT, +} RockchipSocType; + +typedef struct MppDecHwCap_t { + RK_U32 cap_coding; + + MppClientType type : 8; + + RK_U32 cap_fbc : 4; + RK_U32 cap_4k : 1; + RK_U32 cap_8k : 1; + RK_U32 cap_colmv_buf : 1; + RK_U32 cap_hw_h265_rps : 1; + RK_U32 cap_hw_vp9_prob : 1; + RK_U32 cap_jpg_pp_out : 1; + RK_U32 cap_10bit : 1; + RK_U32 reserved : 13; +} MppDecHwCap; + +typedef struct MppEncHwCap_t { + RK_U32 cap_coding; + + MppClientType type : 8; + + RK_U32 cap_fbc : 4; + RK_U32 cap_4k : 1; + RK_U32 cap_8k : 1; + RK_U32 cap_hw_osd : 1; + RK_U32 cap_hw_roi : 1; + RK_U32 reserved : 16; +} MppEncHwCap; + +typedef struct { + const char *compatible; + const RockchipSocType soc_type; + const RK_U32 vcodec_type; + + /* Max 4 decoder cap */ + const MppDecHwCap *dec_caps[4]; + /* Max 4 encoder cap */ + const MppEncHwCap *enc_caps[4]; +} MppSocInfo; + +#ifdef __cplusplus +extern "C" { +#endif + +const char *mpp_get_soc_name(void); +RockchipSocType mpp_get_soc_type(void); +RK_U32 mpp_get_vcodec_type(void); + +const MppSocInfo *mpp_get_soc_info(void); +RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_SOC_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_task.h b/hardware/mpp/include/mpp_task.h new file mode 100644 index 0000000000000000000000000000000000000000..48de2d0866776d580530e076841de2ddd1d90b5d --- /dev/null +++ b/hardware/mpp/include/mpp_task.h @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_TASK_H__ +#define __MPP_TASK_H__ + +#include "mpp_meta.h" + +/* + * Advanced task flow + * Advanced task flow introduces three concepts: port, task and item + * + * Port is from OpenMAX + * Port has two type: input port and output port which are all for data transaction. + * Port work like a queue. task will be dequeue from or enqueue to one port. + * On input side user will dequeue task from input port, setup task and enqueue task + * back to input port. + * On output side user will dequeue task from output port, get the information from + * and then enqueue task back to output port. + * + * Task indicates one transaction on the port. + * Task has two working mode: async mode and sync mode + * If mpp is work in sync mode on task enqueue function return the task has been done + * If mpp is work in async mode on task enqueue function return the task is just put + * on the task queue for process. + * Task can carry different items. Task just like a container of items + * + * Item indicates MppPacket or MppFrame which is contained in one task + */ + +/* + * One mpp task queue has two ports: input and output + * + * The whole picture is: + * Top layer mpp has two ports: mpp_input_port and mpp_output_port + * But internally these two ports belongs to two task queue. + * The mpp_input_port is the mpp_input_task_queue's input port. + * The mpp_output_port is the mpp_output_task_queue's output port. + * + * Each port uses its task queue to communication + */ +typedef enum { + MPP_PORT_INPUT, + MPP_PORT_OUTPUT, + MPP_PORT_BUTT, +} MppPortType; + +/* + * Advance task work flow mode: + ****************************************************************************** + * 1. async mode (default_val) + * + * mpp_init(type, coding, MPP_WORK_ASYNC) + * + * input thread + * a - poll(input) + * b - dequeue(input, *task) + * c - task_set_item(packet/frame) + * d - enqueue(input, task) // when enqueue return the task is not done yet + * + * output thread + * a - poll(output) + * b - dequeue(output, *task) + * c - task_get_item(frame/packet) + * d - enqueue(output, task) + ****************************************************************************** + * 2. sync mode + * + * mpp_init(type, coding, MPP_WORK_SYNC) + * + * a - poll(input) + * b - dequeue(input, *task) + * c - task_set_item(packet/frame) + * d - enqueue(task) // when enqueue return the task is finished + ****************************************************************************** + */ +typedef enum { + MPP_TASK_ASYNC, + MPP_TASK_SYNC, + MPP_TASK_WORK_MODE_BUTT, +} MppTaskWorkMode; + +/* + * Mpp port poll type + * + * MPP_POLL_BLOCK - for block poll + * MPP_POLL_NON_BLOCK - for non-block poll + * small than MPP_POLL_MAX - for poll with timeout in ms + * small than MPP_POLL_BUTT or larger than MPP_POLL_MAX is invalid value + */ +typedef enum { + MPP_POLL_BUTT = -2, + MPP_POLL_BLOCK = -1, + MPP_POLL_NON_BLOCK = 0, + MPP_POLL_MAX = 8000, +} MppPollType; + +/* + * Mpp timeout define + * MPP_TIMEOUT_BLOCK - for block poll + * MPP_TIMEOUT_NON_BLOCK - for non-block poll + * small than MPP_TIMEOUT_MAX - for poll with timeout in ms + * small than MPP_TIMEOUT_BUTT or larger than MPP_TIMEOUT_MAX is invalid value + */ +#define MPP_TIMEOUT_BUTT (-2L) +#define MPP_TIMEOUT_BLOCK (-1L) +#define MPP_TIMEOUT_NON_BLOCK (0L) +#define MPP_TIMEOUT_MAX (8000L) + +/* + * MppTask is descriptor of a task which send to mpp for process + * mpp can support different type of work mode, for example: + * + * decoder: + * + * 1. typical decoder mode: + * input - MppPacket (normal cpu buffer, need cpu copy) + * output - MppFrame (ion/drm buffer in external/internal mode) + * 2. secure decoder mode: + * input - MppPacket (externel ion/drm buffer, cpu can not access) + * output - MppFrame (ion/drm buffer in external/internal mode, cpu can not access) + * + * interface usage: + * + * typical flow + * input side: + * task_dequeue(ctx, PORT_INPUT, &task); + * task_put_item(task, MODE_INPUT, packet) + * task_enqueue(ctx, PORT_INPUT, task); + * output side: + * task_dequeue(ctx, PORT_OUTPUT, &task); + * task_get_item(task, MODE_OUTPUT, &frame) + * task_enqueue(ctx, PORT_OUTPUT, task); + * + * secure flow + * input side: + * task_dequeue(ctx, PORT_INPUT, &task); + * task_put_item(task, MODE_INPUT, packet) + * task_put_item(task, MODE_OUTPUT, frame) // buffer will be specified here + * task_enqueue(ctx, PORT_INPUT, task); + * output side: + * task_dequeue(ctx, PORT_OUTPUT, &task); + * task_get_item(task, MODE_OUTPUT, &frame) + * task_enqueue(ctx, PORT_OUTPUT, task); + * + * encoder: + * + * 1. typical encoder mode: + * input - MppFrame (ion/drm buffer in external mode) + * output - MppPacket (normal cpu buffer, need cpu copy) + * 2. user input encoder mode: + * input - MppFrame (normal cpu buffer, need to build hardware table for this buffer) + * output - MppPacket (normal cpu buffer, need cpu copy) + * 3. secure encoder mode: + * input - MppFrame (ion/drm buffer in external mode, cpu can not access) + * output - MppPacket (externel ion/drm buffer, cpu can not access) + * + * typical / user input flow + * input side: + * task_dequeue(ctx, PORT_INPUT, &task); + * task_put_item(task, MODE_INPUT, frame) + * task_enqueue(ctx, PORT_INPUT, task); + * output side: + * task_dequeue(ctx, PORT_OUTPUT, &task); + * task_get_item(task, MODE_OUTPUT, &packet) + * task_enqueue(ctx, PORT_OUTPUT, task); + * + * secure flow + * input side: + * task_dequeue(ctx, PORT_INPUT, &task); + * task_put_item(task, MODE_OUTPUT, packet) // buffer will be specified here + * task_put_item(task, MODE_INPUT, frame) + * task_enqueue(ctx, PORT_INPUT, task); + * output side: + * task_dequeue(ctx, PORT_OUTPUT, &task); + * task_get_item(task, MODE_OUTPUT, &packet) + * task_get_item(task, MODE_OUTPUT, &frame) + * task_enqueue(ctx, PORT_OUTPUT, task); + * + * NOTE: this flow can specify the output frame. User will setup both intput frame and output packet + * buffer at the input side. Then at output side when user gets a finished task user can get the output + * packet and corresponding released input frame. + * + * image processing + * + * 1. typical image process mode: + * input - MppFrame (ion/drm buffer in external mode) + * output - MppFrame (ion/drm buffer in external mode) + * + * typical / user input flow + * input side: + * task_dequeue(ctx, PORT_INPUT, &task); + * task_put_item(task, MODE_INPUT, frame) + * task_enqueue(ctx, PORT_INPUT, task); + * output side: + * task_dequeue(ctx, PORT_OUTPUT, &task); + * task_get_item(task, MODE_OUTPUT, &frame) + * task_enqueue(ctx, PORT_OUTPUT, task); + */ +/* NOTE: use index rather then handle to descripbe task */ + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_task_meta_set_s32(MppTask task, MppMetaKey key, RK_S32 val); +MPP_RET mpp_task_meta_set_s64(MppTask task, MppMetaKey key, RK_S64 val); +MPP_RET mpp_task_meta_set_ptr(MppTask task, MppMetaKey key, void *val); +MPP_RET mpp_task_meta_set_frame (MppTask task, MppMetaKey key, MppFrame frame); +MPP_RET mpp_task_meta_set_packet(MppTask task, MppMetaKey key, MppPacket packet); +MPP_RET mpp_task_meta_set_buffer(MppTask task, MppMetaKey key, MppBuffer buffer); + +MPP_RET mpp_task_meta_get_s32(MppTask task, MppMetaKey key, RK_S32 *val, RK_S32 default_val); +MPP_RET mpp_task_meta_get_s64(MppTask task, MppMetaKey key, RK_S64 *val, RK_S64 default_val); +MPP_RET mpp_task_meta_get_ptr(MppTask task, MppMetaKey key, void **val, void *default_val); +MPP_RET mpp_task_meta_get_frame (MppTask task, MppMetaKey key, MppFrame *frame); +MPP_RET mpp_task_meta_get_packet(MppTask task, MppMetaKey key, MppPacket *packet); +MPP_RET mpp_task_meta_get_buffer(MppTask task, MppMetaKey key, MppBuffer *buffer); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_QUEUE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/mpp_thread.h b/hardware/mpp/include/mpp_thread.h new file mode 100644 index 0000000000000000000000000000000000000000..521b4b59a0df72295fb11ec45dede927ca824974 --- /dev/null +++ b/hardware/mpp/include/mpp_thread.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_THREAD_H__ +#define __MPP_THREAD_H__ + +#if defined(_WIN32) && !defined(__MINGW32CE__) + +/* + * NOTE: POSIX Threads for Win32 + * Downloaded from http://www.sourceware.org/pthreads-win32/ + */ +#include "semaphore.h" +#include "pthread.h" +#pragma comment(lib, "pthreadVC2.lib") + +/* + * add pthread_setname_np for windows + */ +int pthread_setname_np(pthread_t thread, const char *name); + +#else + +#include +#include +#include +#include + +#ifndef PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP +#define PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP PTHREAD_RECURSIVE_MUTEX_INITIALIZER +#endif + +#endif + +#define THREAD_NAME_LEN 16 + +typedef void *(*MppThreadFunc)(void *); + +typedef enum { + MPP_THREAD_UNINITED, + MPP_THREAD_RUNNING, + MPP_THREAD_WAITING, + MPP_THREAD_STOPPING, +} MppThreadStatus; + +#ifdef __cplusplus + +#include "mpp_log.h" + +class Mutex; +class Condition; + +/* + * for shorter type name and function name + */ +class Mutex { +public: + Mutex(); + ~Mutex(); + + void lock(); + void unlock(); + int trylock(); + + class Autolock { + public: + inline Autolock(Mutex* mutex, RK_U32 enable = 1) + : mEnabled(enable), mLock(*mutex) + { + if (mEnabled) + mLock.lock(); + } + inline ~Autolock() + { + if (mEnabled) + mLock.unlock(); + } + private: + RK_S32 mEnabled; + Mutex& mLock; + }; + +private: + friend class Condition; + + pthread_mutex_t mMutex; + + Mutex(const Mutex &); + Mutex &operator = (const Mutex&); +}; + +inline Mutex::Mutex() +{ + pthread_mutexattr_t attr; + pthread_mutexattr_init(&attr); + pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE); + pthread_mutex_init(&mMutex, &attr); + pthread_mutexattr_destroy(&attr); +} +inline Mutex::~Mutex() +{ + pthread_mutex_destroy(&mMutex); +} +inline void Mutex::lock() +{ + pthread_mutex_lock(&mMutex); +} +inline void Mutex::unlock() +{ + pthread_mutex_unlock(&mMutex); +} +inline int Mutex::trylock() +{ + return pthread_mutex_trylock(&mMutex); +} + +typedef Mutex::Autolock AutoMutex; + + +/* + * for shorter type name and function name + */ +class Condition { +public: + Condition(); + Condition(int type); + ~Condition(); + RK_S32 wait(Mutex& mutex); + RK_S32 wait(Mutex* mutex); + RK_S32 timedwait(Mutex& mutex, RK_S64 timeout); + RK_S32 timedwait(Mutex* mutex, RK_S64 timeout); + RK_S32 signal(); + RK_S32 broadcast(); + +private: + pthread_cond_t mCond; +}; + +inline Condition::Condition() +{ + pthread_cond_init(&mCond, NULL); +} +inline Condition::~Condition() +{ + pthread_cond_destroy(&mCond); +} +inline RK_S32 Condition::wait(Mutex& mutex) +{ + return pthread_cond_wait(&mCond, &mutex.mMutex); +} +inline RK_S32 Condition::wait(Mutex* mutex) +{ + return pthread_cond_wait(&mCond, &mutex->mMutex); +} +inline RK_S32 Condition::timedwait(Mutex& mutex, RK_S64 timeout) +{ + return timedwait(&mutex, timeout); +} +inline RK_S32 Condition::timedwait(Mutex* mutex, RK_S64 timeout) +{ + struct timespec ts; + + clock_gettime(CLOCK_REALTIME_COARSE, &ts); + + ts.tv_sec += timeout / 1000; // 1000:Get milliseconds + ts.tv_nsec += (timeout % 1000) * 1000000; // 1000:Get milliseconds // 1000000:Get seconds + /* Prevent the out of range at nanoseconds field */ + ts.tv_sec += ts.tv_nsec / 1000000000; // 1000000000:Get seconds + ts.tv_nsec %= 1000000000; // 1000000000:Get Get nanoseconds + + return pthread_cond_timedwait(&mCond, &mutex->mMutex, &ts); +} +inline RK_S32 Condition::signal() +{ + return pthread_cond_signal(&mCond); +} +inline RK_S32 Condition::broadcast() +{ + return pthread_cond_broadcast(&mCond); +} + +class MppMutexCond { +public: + MppMutexCond() {}; + ~MppMutexCond() {}; + + void lock() + { + mLock.lock(); + } + void unlock() + { + mLock.unlock(); + } + void trylock() + { + mLock.trylock(); + } + void wait() + { + mCondition.wait(mLock); + } + RK_S32 wait(RK_S64 timeout) + { + return mCondition.timedwait(mLock, timeout); + } + void signal() + { + mCondition.signal(); + } + void broadcast() + { + mCondition.broadcast(); + } + Mutex *mutex() + { + return &mLock; + } + +private: + Mutex mLock; + Condition mCondition; +}; + +// Thread lock / signal is distinguished by its source +typedef enum MppThreadSignal_e { + THREAD_WORK, // for working loop + THREAD_INPUT, // for thread input + THREAD_OUTPUT, // for thread output + THREAD_CONTROL, // for thread async control (reset) + THREAD_SIGNAL_BUTT, +} MppThreadSignal; + +#define THREAD_NORMAL 0 +#define THRE 0 + +class MppThread { +public: + MppThread(MppThreadFunc func, void *ctx, const char *name = NULL); + ~MppThread() {}; + + MppThreadStatus get_status(MppThreadSignal id = THREAD_WORK); + void set_status(MppThreadStatus status, MppThreadSignal id = THREAD_WORK); + void dump_status(); + + void start(); + void stop(); + + void lock(MppThreadSignal id = THREAD_WORK) + { + mpp_assert(id < THREAD_SIGNAL_BUTT); + mMutexCond[id].lock(); + } + + void unlock(MppThreadSignal id = THREAD_WORK) + { + mpp_assert(id < THREAD_SIGNAL_BUTT); + mMutexCond[id].unlock(); + } + + void wait(MppThreadSignal id = THREAD_WORK) + { + mpp_assert(id < THREAD_SIGNAL_BUTT); + MppThreadStatus status = mStatus[id]; + + mStatus[id] = MPP_THREAD_WAITING; + mMutexCond[id].wait(); + + // check the status is not changed then restore status + if (mStatus[id] == MPP_THREAD_WAITING) + mStatus[id] = status; + } + + void signal(MppThreadSignal id = THREAD_WORK) + { + mpp_assert(id < THREAD_SIGNAL_BUTT); + mMutexCond[id].signal(); + } + + Mutex *mutex(MppThreadSignal id = THREAD_WORK) + { + mpp_assert(id < THREAD_SIGNAL_BUTT); + return mMutexCond[id].mutex(); + } + +private: + pthread_t mThread; + MppMutexCond mMutexCond[THREAD_SIGNAL_BUTT]; + MppThreadStatus mStatus[THREAD_SIGNAL_BUTT]; + + MppThreadFunc mFunction; + char mName[THREAD_NAME_LEN]; + void *mContext; + + MppThread(); + MppThread(const MppThread &); + MppThread &operator=(const MppThread &); +}; + +#endif + +#endif /* __MPP_THREAD_H__ */ diff --git a/hardware/mpp/include/mpp_time.h b/hardware/mpp/include/mpp_time.h new file mode 100644 index 0000000000000000000000000000000000000000..0ef1c07cddbbab49916923d06fe9879992691b93 --- /dev/null +++ b/hardware/mpp/include/mpp_time.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_TIME_H__ +#define __MPP_TIME_H__ + +#include "rk_type.h" +#include "mpp_thread.h" + +#if defined(_WIN32) && !defined(__MINGW32CE__) +#include +#define msleep Sleep +#define sleep(x) Sleep((x)*1000) +#else +#include +#define msleep(x) usleep((x)*1000) +#endif + +typedef void* MppClock; +typedef void* MppTimer; +typedef void* MppStopwatch; + +#ifdef __cplusplus +extern "C" { +#endif + +RK_S64 mpp_time(void); +void mpp_time_diff(RK_S64 start, RK_S64 end, RK_S64 limit, const char *fmt); + +/* + * Clock create / destroy / enable / disable function + * Note when clock is create it is default disabled user need to call enable + * fucntion with enable = 1 to enable the clock. + * User can use enable function with enable = 0 to disable the clock. + */ +MppClock mpp_clock_get(const char *name); +void mpp_clock_put(MppClock clock); +void mpp_clock_enable(MppClock clock, RK_U32 enable); + +/* + * Clock basic operation function + * start : let clock start timing counter + * pause : let clock pause and return the diff to start time + * reset : let clock counter to all zero + */ +RK_S64 mpp_clock_start(MppClock clock); +RK_S64 mpp_clock_pause(MppClock clock); +RK_S64 mpp_clock_reset(MppClock clock); + +/* + * These clock helper function can only be call when clock is paused: + * mpp_clock_get_sum - Return clock sum up total value + * mpp_clock_get_count - Return clock sum up counter value + * mpp_clock_get_name - Return clock name + */ +RK_S64 mpp_clock_get_sum(MppClock clock); +RK_S64 mpp_clock_get_count(MppClock clock); +const char *mpp_clock_get_name(MppClock clock); + +/* + * MppTimer is for timer with callback function + * It will provide the ability to repeat doing something until it is + * disalble or put. + * + * Timer work flow + * + * 1. mpp_timer_get + * 2. mpp_timer_set_callback + * 3. mpp_timer_set_timing(initial, interval) + * 4. mpp_timer_set_enable(initial, 1) + * ... running ... + * 5. mpp_timer_set_enable(initial, 0) + * 6. mpp_timer_put + */ +MppTimer mpp_timer_get(const char *name); +void mpp_timer_set_callback(MppTimer timer, MppThreadFunc func, void *ctx); +void mpp_timer_set_timing(MppTimer timer, RK_S32 initial, RK_S32 interval); +void mpp_timer_set_enable(MppTimer timer, RK_S32 enable); +void mpp_timer_put(MppTimer timer); + +/* + * MppStopwatch is for timer to record event and time + * + * Stopwatch work flow + * + * 1. mpp_stopwatch_get + * 2. mpp_stopwatch_setup(max_count, show_on_exit) + * 3. mpp_stopwatch_record(event) + * ... running ... + * 4. mpp_stopwatch_record(event) + * 5. mpp_stopwatch_put (show events and time) + */ +MppStopwatch mpp_stopwatch_get(const char *name); +void mpp_stopwatch_set_show_on_exit(MppStopwatch stopwatch, RK_S32 show_on_exit); +void mpp_stopwatch_record(MppStopwatch stopwatch, const char *event); +void mpp_stopwatch_put(MppStopwatch timer); +RK_S64 mpp_stopwatch_elapsed_time(MppStopwatch stopwatch); + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +class mpp_time { +public: + mpp_time(const char *name = __FUNCTION__); + ~mpp_time(); +private: + const char *mName; + RK_S64 mStart; + RK_S64 mEnd; + + mpp_time(const AutoTiming &); + mpp_time &operator = (const AutoTiming&); +}; + +#endif + +#define AUTO_TIMER_STRING(name, cnt) name ## cnt +#define AUTO_TIMER_NAME_STRING(name, cnt) AUTO_TIMER_STRING(name, cnt) +#define AUTO_TIMER_NAME(name) AUTO_TIMER_NAME_STRING(name, __COUNTER__) +#define AUTO_TIMING() AutoTiming AUTO_TIMER_NAME(auto_timing)(__FUNCTION__) + +#endif /* __MPP_TIME_H__ */ diff --git a/hardware/mpp/include/mpp_trace.h b/hardware/mpp/include/mpp_trace.h new file mode 100644 index 0000000000000000000000000000000000000000..a65a98ac49ea6dfb35ed3cc6aaff8a5bd0d46395 --- /dev/null +++ b/hardware/mpp/include/mpp_trace.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MPP_TRACE_H__ +#define __MPP_TRACE_H__ + +#include "rk_type.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void mpp_trace_begin(const char* name); +void mpp_trace_end(const char* name); +void mpp_trace_async_begin(const char* name, RK_S32 cookie); +void mpp_trace_async_end(const char* name, RK_S32 cookie); +void mpp_trace_int32(const char* name, RK_S32 value); +void mpp_trace_int64(const char* name, RK_S64 value); + +#ifdef __cplusplus +} +#endif + +#endif /* __MPP_TRACE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/osal_2str.h b/hardware/mpp/include/osal_2str.h new file mode 100644 index 0000000000000000000000000000000000000000..b9084563726887b711ddc7a477c044eb2735f3ce --- /dev/null +++ b/hardware/mpp/include/osal_2str.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __OSAL_2STR_H__ +#define __OSAL_2STR_H__ + +#include "mpp_dev_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +const char *strof_client_type(MppClientType type); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/hardware/mpp/include/rk_mpi.h b/hardware/mpp/include/rk_mpi.h new file mode 100644 index 0000000000000000000000000000000000000000..0429f69fa62e5a29af6679cc28930da6dfdb1276 --- /dev/null +++ b/hardware/mpp/include/rk_mpi.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_MPI_H__ +#define __RK_MPI_H__ + +/** + * @addtogroup rk_mpi + * @brief Rockchip Media Process Interface + * @details Media Process Platform(MPP) provides application programming + * interface for the application layer, by which applications can + * call hardware encode and decode. Current MPP fully supports + * chipset RK3288/RK3228/RK3229/RK3399/RK3328/RV1108. Old chipset + * like RK29xx/RK30xx/RK31XX/RK3368 is partly supported due to lack + * of some hardware register generation module. + */ + +#include "rk_mpi_cmd.h" +#include "mpp_task.h" + +/** + * @ingroup rk_mpi + * @brief MPP main work function set + * @details all api function are seperated into two sets: data io api set + * and control api set + * + * (1). the data api set is for data input/output flow including: + * + * (1.1) simple data api set: + * + * decode : both send video stream packet to decoder and get video frame from + * decoder at the same time. + * + * encode : both send video frame to encoder and get encoded video stream from + * encoder at the same time. + * + * decode_put_packet: send video stream packet to decoder only, async interface + * + * decode_get_frame : get video frame from decoder only, async interface + * + * encode_put_frame : send video frame to encoder only, async interface + * + * encode_get_packet: get encoded video packet from encoder only, async interface + * + * (1.2) advanced task api set: + * + * poll : poll port for dequeue + * + * dequeue : pop a task from mpp task queue + * + * enqueue : push a task to mpp task queue + * + * (2). the control api set is for mpp context control including: + * + * control : similiar to ioctl in kernel driver, setup or get mpp internal parameter + * + * reset : clear all data in mpp context, discard all packet and frame, + * reset all components to initialized status + */ +typedef struct MppApi_t { + /** + * @brief size of struct MppApi + */ + RK_U32 size; + /** + * @brief mpp api version, generated by Git + */ + RK_U32 version; + + // simple data flow interface + /** + * @brief both send video stream packet to decoder and get video frame from + * decoder at the same time + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] packet The input video stream, its usage can refer mpp_packet.h. + * @param[out] frame The output picture, its usage can refer mpp_frame.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*decode)(MppCtx ctx, MppPacket packet, MppFrame *frame); + /** + * @brief send video stream packet to decoder only, async interface + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] packet The input video stream, its usage can refer mpp_packet.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*decode_put_packet)(MppCtx ctx, MppPacket packet); + /** + * @brief get video frame from decoder only, async interface + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[out] frame The output picture, its usage can refer mpp_frame.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*decode_get_frame)(MppCtx ctx, MppFrame *frame); + /** + * @brief both send video frame to encoder and get encoded video stream from + * encoder at the same time + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] frame The input video data, its usage can refer mpp_frame.h. + * @param[out] packet The output compressed data, its usage can refer mpp_packet.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*encode)(MppCtx ctx, MppFrame frame, MppPacket *packet); + /** + * @brief send video frame to encoder only, async interface + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] frame The input video data, its usage can refer mpp_frame.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*encode_put_frame)(MppCtx ctx, MppFrame frame); + /** + * @brief get encoded video packet from encoder only, async interface + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[out] packet The output compressed data, its usage can refer mpp_packet.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*encode_get_packet)(MppCtx ctx, MppPacket *packet); + + /** + * @brief ISP interface, will be supported in the future. + */ + MPP_RET (*isp)(MppCtx ctx, MppFrame dst, MppFrame src); + /** + * @brief ISP interface, will be supported in the future. + */ + MPP_RET (*isp_put_frame)(MppCtx ctx, MppFrame frame); + /** + * @brief ISP interface, will be supported in the future. + */ + MPP_RET (*isp_get_frame)(MppCtx ctx, MppFrame *frame); + + // advance data flow interface + /** + * @brief poll port for dequeue + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] type input port or output port which are both for data transaction + * @param[in] timeout mpp poll type, its usage can refer mpp_task.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*poll)(MppCtx ctx, MppPortType type, MppPollType timeout); + /** + * @brief dequeue MppTask, pop a task from mpp task queue + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] type input port or output port which are both for data transaction + * @param[out] task MppTask popped from mpp task queue, its usage can refer mpp_task.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*dequeue)(MppCtx ctx, MppPortType type, MppTask *task); + /** + * @brief enqueue MppTask, push a task to mpp task queue + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] type input port or output port which are both for data transaction + * @param[in] task MppTask which is sent to mpp for process, its usage can refer mpp_task.h. + * @return 0 and positive for success, negative for failure. The return + * value is an error code. For details, please refer mpp_err.h. + */ + MPP_RET (*enqueue)(MppCtx ctx, MppPortType type, MppTask task); + + // control interface + /** + * @brief discard all packet and frame, reset all component, + * for both decoder and encoder + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ + MPP_RET (*reset)(MppCtx ctx); + /** + * @brief control function for mpp property setting + * @param[in] ctx The context of mpp, created by mpp_create() and initiated + * by mpp_init(). + * @param[in] cmd The mpi command, its definition can refer rk_mpi_cmd.h. + * @param[in,out] param The mpi command parameter + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ + MPP_RET (*control)(MppCtx ctx, MpiCmd cmd, MppParam param); + + /** + * @brief The reserved segment, may be used in the future + */ + RK_U32 reserv[16]; +} MppApi; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup rk_mpi + * @brief Create empty context structure and mpi function pointers. + * Use functions in MppApi to access mpp services. + * @param[in,out] ctx pointer of the mpp context, refer to MpiImpl_t. + * @param[in,out] mpi pointer of mpi function, refer to MppApi. + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + * @note This interface creates base flow context, all function calls + * are based on it. + */ +MPP_RET mpp_create(MppCtx *ctx, MppApi **mpi); +/** + * @ingroup rk_mpi + * @brief Call after mpp_create to setup mpp type and video format. + * This function will call internal context init function. + * @param[in] ctx The context of mpp, created by mpp_create(). + * @param[in] type specify decoder or encoder, refer to MppCtxType. + * @param[in] coding specify video compression coding, refer to MppCodingType. + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ +MPP_RET mpp_init(MppCtx ctx, MppCtxType type, MppCodingType coding); +/** + * @ingroup rk_mpi + * @brief Call after mpp_init to start mpp working. + * Control SET_CFG can be called both before and after mpp_start. + * Before mpp_start is called both global param and dynamic param can be set. + * After mpp_start is called only dynamic param can be set. + * This funciton purpose is to stop recieving global param and do + * preparation for processing data flow. + * This function will call internal context start function. + * @param[in] ctx The context of mpp, created by mpp_create(). + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ +MPP_RET mpp_start(MppCtx ctx); +/** + * @ingroup rk_mpi + * @brief Call before mpp_destroy to stop mpp working. + * Control SET_CFG can be called after starting. + * Before mpp_stop is called only dynamic param can be set. + * After mpp_stop is called both global param and dynamic param can be set. + * This funciton purpose is to stop processing data and do preparation + * to receive global param. + * @param[in] ctx The context of mpp, created by mpp_create(). + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ +MPP_RET mpp_stop(MppCtx ctx); +/** + * @ingroup rk_mpi + * @brief Destroy mpp context and free both context and mpi structure, + * it matches with mpp_init(). + * @param[in] ctx The context of mpp, created by mpp_create(). + * @return 0 for success, others for failure. The return value is an + * error code. For details, please refer mpp_err.h. + */ +MPP_RET mpp_destroy(MppCtx ctx); +/** + * @ingroup rk_mpi + * @brief judge given format is supported or not by MPP. + * @param[in] type specify decoder or encoder, refer to MppCtxType. + * @param[in] coding specify video compression coding, refer to MppCodingType. + * @return 0 for support, -1 for unsupported. + */ +MPP_RET mpp_check_support_format(MppCtxType type, MppCodingType coding); +/** + * @ingroup rk_mpi + * @brief List all formats supported by MPP + * @param NULL no need to input parameter + * @return No return value. This function just prints format information supported + * by MPP on standard output. + */ +void mpp_show_support_format(void); +void mpp_show_color_format(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __RK_MPI_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/rk_mpi_cmd.h b/hardware/mpp/include/rk_mpi_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..09a45529f69ab221ba314b9a016a9a7bbbe3fba6 --- /dev/null +++ b/hardware/mpp/include/rk_mpi_cmd.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_MPI_CMD_H__ +#define __RK_MPI_CMD_H__ + +/* + * Command id bit usage is defined as follows: + * bit 20 - 23 - module id + * bit 16 - 19 - contex id + * bit 0 - 15 - command id + */ +#define CMD_MODULE_ID_MASK (0x00F00000) +#define CMD_MODULE_OSAL (0x00100000) +#define CMD_MODULE_MPP (0x00200000) +#define CMD_MODULE_CODEC (0x00300000) +#define CMD_MODULE_HAL (0x00400000) + +#define CMD_CTX_ID_MASK (0x000F0000) +#define CMD_CTX_ID_DEC (0x00010000) +#define CMD_CTX_ID_ENC (0x00020000) +#define CMD_CTX_ID_ISP (0x00030000) + +/* separate encoder / decoder control command to different segment */ +#define CMD_CFG_ID_MASK (0x0000FF00) + +/* decoder control command */ +#define CMD_DEC_CFG_ALL (0x00000000) +#define CMD_DEC_QUERY (0x00000100) +#define CMD_DEC_CFG (0x00000200) + +/* encoder control command */ +#define CMD_ENC_CFG_ALL (0x00000000) +#define CMD_ENC_CFG_RC_API (0x00000100) + +#define CMD_ENC_CFG_MISC (0x00008000) +#define CMD_ENC_CFG_SPLIT (0x00008100) +#define CMD_ENC_CFG_REF (0x00008200) +#define CMD_ENC_CFG_ROI (0x00008300) +#define CMD_ENC_CFG_OSD (0x00008400) + +typedef enum { + MPP_OSAL_CMD_BASE = CMD_MODULE_OSAL, + MPP_OSAL_CMD_END, + + MPP_CMD_BASE = CMD_MODULE_MPP, + MPP_ENABLE_DEINTERLACE, + MPP_SET_INPUT_BLOCK, /* deprecated */ + MPP_SET_INTPUT_BLOCK_TIMEOUT, /* deprecated */ + MPP_SET_OUTPUT_BLOCK, /* deprecated */ + MPP_SET_OUTPUT_BLOCK_TIMEOUT, /* deprecated */ + /* + * timeout setup, refer to MPP_TIMEOUT_XXX + * zero - non block + * negative - block with no timeout + * positive - timeout in milisecond + */ + MPP_SET_INPUT_TIMEOUT, /* parameter type RK_S64 */ + MPP_SET_OUTPUT_TIMEOUT, /* parameter type RK_S64 */ + MPP_CMD_END, + + MPP_CODEC_CMD_BASE = CMD_MODULE_CODEC, + MPP_CODEC_GET_FRAME_INFO, + MPP_CODEC_CMD_END, + + MPP_DEC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_DEC, + MPP_DEC_SET_FRAME_INFO, /* vpu api legacy control for buffer slot dimension init */ + MPP_DEC_SET_EXT_BUF_GROUP, /* IMPORTANT: set external buffer group to mpp decoder */ + MPP_DEC_SET_INFO_CHANGE_READY, + MPP_DEC_SET_PRESENT_TIME_ORDER, /* use input time order for output */ + MPP_DEC_SET_PARSER_SPLIT_MODE, /* Need to setup before init */ + MPP_DEC_SET_PARSER_FAST_MODE, /* Need to setup before init */ + MPP_DEC_GET_STREAM_COUNT, + MPP_DEC_GET_VPUMEM_USED_COUNT, + MPP_DEC_SET_VC1_EXTRA_DATA, + MPP_DEC_SET_OUTPUT_FORMAT, + MPP_DEC_SET_DISABLE_ERROR, /* When set it will disable sw/hw error (H.264 / H.265) */ + MPP_DEC_SET_IMMEDIATE_OUT, + MPP_DEC_SET_ENABLE_DEINTERLACE, /* MPP enable deinterlace by default. Vpuapi can disable it */ + + MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY, + /* query decoder runtime information for decode stage */ + MPP_DEC_QUERY, /* set and get MppDecQueryCfg structure */ + + CMD_DEC_CMD_CFG = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_CFG, + MPP_DEC_SET_CFG, /* set MppDecCfg structure */ + MPP_DEC_GET_CFG, /* get MppDecCfg structure */ + + MPP_DEC_CMD_END, + + MPP_ENC_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ENC, + /* basic encoder setup control */ + MPP_ENC_SET_CFG, /* set MppEncCfg structure */ + MPP_ENC_GET_CFG, /* get MppEncCfg structure */ + MPP_ENC_SET_PREP_CFG, /* deprecated set MppEncPrepCfg structure, use MPP_ENC_SET_CFG instead */ + MPP_ENC_GET_PREP_CFG, /* deprecated get MppEncPrepCfg structure, use MPP_ENC_GET_CFG instead */ + MPP_ENC_SET_RC_CFG, /* deprecated set MppEncRcCfg structure, use MPP_ENC_SET_CFG instead */ + MPP_ENC_GET_RC_CFG, /* deprecated get MppEncRcCfg structure, use MPP_ENC_GET_CFG instead */ + MPP_ENC_SET_CODEC_CFG, /* deprecated set MppEncCodecCfg structure, use MPP_ENC_SET_CFG instead */ + MPP_ENC_GET_CODEC_CFG, /* deprecated get MppEncCodecCfg structure, use MPP_ENC_GET_CFG instead */ + /* runtime encoder setup control */ + MPP_ENC_SET_IDR_FRAME, /* next frame will be encoded as intra frame */ + MPP_ENC_SET_OSD_LEGACY_0, /* deprecated */ + MPP_ENC_SET_OSD_LEGACY_1, /* deprecated */ + MPP_ENC_SET_OSD_LEGACY_2, /* deprecated */ + MPP_ENC_GET_HDR_SYNC, /* get vps / sps / pps which has better sync behavior parameter is MppPacket */ + MPP_ENC_GET_EXTRA_INFO, /* deprecated */ + MPP_ENC_SET_SEI_CFG, /* SEI: Supplement Enhancemant Information, parameter is MppSeiMode */ + MPP_ENC_GET_SEI_DATA, /* SEI: Supplement Enhancemant Information, parameter is MppPacket */ + MPP_ENC_PRE_ALLOC_BUFF, /* deprecated */ + MPP_ENC_SET_QP_RANGE, /* used for adjusting qp range, the parameter can be 1 or 2 */ + MPP_ENC_SET_ROI_CFG, /* set MppEncROICfg structure */ + MPP_ENC_SET_CTU_QP, /* for H265 Encoder,set CTU's size and QP */ + + /* User define rate control stategy API control */ + MPP_ENC_CFG_RC_API = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_RC_API, + /* + * Get RcApiQueryAll structure + * Get all available rate control stategy string and count + */ + MPP_ENC_GET_RC_API_ALL = MPP_ENC_CFG_RC_API + 1, + /* + * Get RcApiQueryType structure + * Get available rate control stategy string with certain type + */ + MPP_ENC_GET_RC_API_BY_TYPE = MPP_ENC_CFG_RC_API + 2, + /* + * Set RcImplApi structure + * Add new or update rate control stategy function pointers + */ + MPP_ENC_SET_RC_API_CFG = MPP_ENC_CFG_RC_API + 3, + /* + * Get RcApiBrief structure + * Get current used rate control stategy brief information (type and name) + */ + MPP_ENC_GET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 4, + /* + * Set RcApiBrief structure + * Set current used rate control stategy brief information (type and name) + */ + MPP_ENC_SET_RC_API_CURRENT = MPP_ENC_CFG_RC_API + 5, + + MPP_ENC_CFG_MISC = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_MISC, + /* set MppEncHeaderMode */ + MPP_ENC_SET_HEADER_MODE, + /* get MppEncHeaderMode */ + MPP_ENC_GET_HEADER_MODE, + + MPP_ENC_CFG_SPLIT = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_SPLIT, + /* set MppEncSliceSplit structure */ + MPP_ENC_SET_SPLIT, + /* get MppEncSliceSplit structure */ + MPP_ENC_GET_SPLIT, + + MPP_ENC_CFG_REF = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_REF, + /* set MppEncRefCfg structure */ + MPP_ENC_SET_REF_CFG, + + MPP_ENC_CFG_OSD = CMD_MODULE_CODEC | CMD_CTX_ID_ENC | CMD_ENC_CFG_OSD, + /* set OSD palette, parameter should be pointer to MppEncOSDPltCfg */ + MPP_ENC_SET_OSD_PLT_CFG, + /* get OSD palette, parameter should be pointer to MppEncOSDPltCfg */ + MPP_ENC_GET_OSD_PLT_CFG, + /* set OSD data with at most 8 regions, parameter should be pointer to MppEncOSDData */ + MPP_ENC_SET_OSD_DATA_CFG, + + MPP_ENC_CMD_END, + + MPP_ISP_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ISP, + MPP_ISP_CMD_END, + + MPP_HAL_CMD_BASE = CMD_MODULE_HAL, + MPP_HAL_CMD_END, + + MPI_CMD_BUTT, +} MpiCmd; + +#include "rk_vdec_cmd.h" +#include "rk_vdec_cfg.h" +#include "rk_venc_cmd.h" +#include "rk_venc_cfg.h" +#include "rk_venc_ref.h" + +#endif /* __RK_MPI_CMD_H__ */ diff --git a/hardware/mpp/include/rk_type.h b/hardware/mpp/include/rk_type.h new file mode 100644 index 0000000000000000000000000000000000000000..9adf3d0d987e494e73bee3bb4f612bbf98bf524e --- /dev/null +++ b/hardware/mpp/include/rk_type.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_TYPE_H__ +#define __RK_TYPE_H__ + +#include + +#if defined(_WIN32) && !defined(__MINGW32CE__) + +typedef unsigned char RK_U8; +typedef unsigned short RK_U16; +typedef unsigned int RK_U32; +typedef unsigned long RK_ULONG; +typedef unsigned __int64 RK_U64; + +typedef signed char RK_S8; +typedef signed short RK_S16; +typedef signed int RK_S32; +typedef signed long RK_LONG; +typedef signed __int64 RK_S64; + +#else + +typedef unsigned char RK_U8; +typedef unsigned short RK_U16; +typedef unsigned int RK_U32; +typedef unsigned long RK_ULONG; +typedef unsigned long long int RK_U64; + + +typedef signed char RK_S8; +typedef signed short RK_S16; +typedef signed int RK_S32; +typedef signed long RK_LONG; +typedef signed long long int RK_S64; + +#endif + +#ifndef MODULE_TAG +#define MODULE_TAG NULL +#endif + +/** + * @ingroup rk_mpi + * @brief The type of mpp context + * @details This type is used when calling mpp_init(), which including decoder, + * encoder and Image Signal Process(ISP). So far decoder and encoder + * are supported perfectly, and ISP will be supported in the future. + */ +typedef enum { + MPP_CTX_DEC, /**< decoder */ + MPP_CTX_ENC, /**< encoder */ + MPP_CTX_ISP, /**< isp */ + MPP_CTX_BUTT, /**< undefined */ +} MppCtxType; + +/** + * @ingroup rk_mpi + * @brief Enumeration used to define the possible video compression codings. + * sync with the omx_video.h + * + * @note This essentially refers to file extensions. If the coding is + * being used to specify the ENCODE type, then additional work + * must be done to configure the exact flavor of the compression + * to be used. For decode cases where the user application can + * not differentiate between MPEG-4 and H.264 bit streams, it is + * up to the codec to handle this. + */ +typedef enum { + MPP_VIDEO_CodingUnused, /**< Value when coding is N/A */ + MPP_VIDEO_CodingAutoDetect, /**< Autodetection of coding type */ + MPP_VIDEO_CodingMPEG2, /**< AKA: H.262 */ + MPP_VIDEO_CodingH263, /**< H.263 */ + MPP_VIDEO_CodingMPEG4, /**< MPEG-4 */ + MPP_VIDEO_CodingWMV, /**< Windows Media Video (WMV1,WMV2,WMV3)*/ + MPP_VIDEO_CodingRV, /**< all versions of Real Video */ + MPP_VIDEO_CodingAVC, /**< H.264/AVC */ + MPP_VIDEO_CodingMJPEG, /**< Motion JPEG */ + MPP_VIDEO_CodingVP8, /**< VP8 */ + MPP_VIDEO_CodingVP9, /**< VP9 */ + MPP_VIDEO_CodingVC1 = 0x01000000, /**< Windows Media Video (WMV1,WMV2,WMV3)*/ + MPP_VIDEO_CodingFLV1, /**< Sorenson H.263 */ + MPP_VIDEO_CodingDIVX3, /**< DIVX3 */ + MPP_VIDEO_CodingVP6, + MPP_VIDEO_CodingHEVC, /**< H.265/HEVC */ + MPP_VIDEO_CodingAVSPLUS, /**< AVS+ */ + MPP_VIDEO_CodingAVS, /**< AVS profile=0x20 */ + MPP_VIDEO_CodingKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ + MPP_VIDEO_CodingVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */ + MPP_VIDEO_CodingMax = 0x7FFFFFFF +} MppCodingType; + +/* + * All external interface object list here. + * The interface object is defined as void * for expandability + * The cross include between these objects will introduce extra + * compiling difficulty. So we move them together in this header. + * + * Object interface header list: + * + * MppCtx - rk_mpi.h + * MppParam - rk_mpi.h + * + * MppFrame - mpp_frame.h + * MppPacket - mpp_packet.h + * + * MppBuffer - mpp_buffer.h + * MppBufferGroup - mpp_buffer.h + * + * MppTask - mpp_task.h + * MppMeta - mpp_meta.h + */ + +typedef void* MppCtx; +typedef void* MppParam; + +typedef void* MppFrame; +typedef void* MppPacket; + +typedef void* MppBuffer; +typedef void* MppBufferGroup; + +typedef void* MppTask; +typedef void* MppMeta; + +#endif /* __RK_TYPE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/rk_vdec_cfg.h b/hardware/mpp/include/rk_vdec_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..a9b772d2e15ec26b3776a41430e7417909e1623e --- /dev/null +++ b/hardware/mpp/include/rk_vdec_cfg.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VDEC_CFG_H__ +#define __RK_VDEC_CFG_H__ + +#include "rk_type.h" +#include "mpp_err.h" + +typedef void* MppDecCfg; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_dec_cfg_init(MppDecCfg *cfg); +MPP_RET mpp_dec_cfg_deinit(MppDecCfg cfg); + +MPP_RET mpp_dec_cfg_set_s32(MppDecCfg cfg, const char *name, RK_S32 val); +MPP_RET mpp_dec_cfg_set_u32(MppDecCfg cfg, const char *name, RK_U32 val); +MPP_RET mpp_dec_cfg_set_s64(MppDecCfg cfg, const char *name, RK_S64 val); +MPP_RET mpp_dec_cfg_set_u64(MppDecCfg cfg, const char *name, RK_U64 val); +MPP_RET mpp_dec_cfg_set_ptr(MppDecCfg cfg, const char *name, void *val); + +MPP_RET mpp_dec_cfg_get_s32(MppDecCfg cfg, const char *name, RK_S32 *val); +MPP_RET mpp_dec_cfg_get_u32(MppDecCfg cfg, const char *name, RK_U32 *val); +MPP_RET mpp_dec_cfg_get_s64(MppDecCfg cfg, const char *name, RK_S64 *val); +MPP_RET mpp_dec_cfg_get_u64(MppDecCfg cfg, const char *name, RK_U64 *val); +MPP_RET mpp_dec_cfg_get_ptr(MppDecCfg cfg, const char *name, void **val); + +void mpp_dec_cfg_show(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __RK_VDEC_CFG_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/rk_vdec_cmd.h b/hardware/mpp/include/rk_vdec_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..f34dab6555b42e364d449761a81973b0ac18565c --- /dev/null +++ b/hardware/mpp/include/rk_vdec_cmd.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VDEC_CMD_H__ +#define __RK_VDEC_CMD_H__ + +#include "rk_type.h" + +/* + * decoder query interface is only for debug usage + */ +#define MPP_DEC_QUERY_STATUS (0x00000001) +#define MPP_DEC_QUERY_WAIT (0x00000002) +#define MPP_DEC_QUERY_FPS (0x00000004) +#define MPP_DEC_QUERY_BPS (0x00000008) +#define MPP_DEC_QUERY_DEC_IN_PKT (0x00000010) +#define MPP_DEC_QUERY_DEC_WORK (0x00000020) +#define MPP_DEC_QUERY_DEC_OUT_FRM (0x00000040) + +#define MPP_DEC_QUERY_ALL (MPP_DEC_QUERY_STATUS | \ + MPP_DEC_QUERY_WAIT | \ + MPP_DEC_QUERY_FPS | \ + MPP_DEC_QUERY_BPS | \ + MPP_DEC_QUERY_DEC_IN_PKT | \ + MPP_DEC_QUERY_DEC_WORK | \ + MPP_DEC_QUERY_DEC_OUT_FRM) + +typedef struct MppDecQueryCfg_t { + /* + * 32 bit query flag for query data check + * Each bit represent a query data switch. + * bit 0 - for querying decoder runtime status + * bit 1 - for querying decoder runtime waiting status + * bit 2 - for querying decoder realtime decode fps + * bit 3 - for querying decoder realtime input bps + * bit 4 - for querying decoder input packet count + * bit 5 - for querying decoder start hardware times + * bit 6 - for querying decoder output frame count + */ + RK_U32 query_flag; + + /* 64 bit query data output */ + RK_U32 rt_status; + RK_U32 rt_wait; + RK_U32 rt_fps; + RK_U32 rt_bps; + RK_U32 dec_in_pkt_cnt; + RK_U32 dec_hw_run_cnt; + RK_U32 dec_out_frm_cnt; +} MppDecQueryCfg; + +#endif /* __RK_VDEC_CMD_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/rk_venc_cfg.h b/hardware/mpp/include/rk_venc_cfg.h new file mode 100644 index 0000000000000000000000000000000000000000..c81ef8123693783ab1661013f6a50340d0766113 --- /dev/null +++ b/hardware/mpp/include/rk_venc_cfg.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VENC_CFG_H__ +#define __RK_VENC_CFG_H__ + +#include "rk_type.h" +#include "mpp_err.h" + +typedef void* MppEncCfg; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg); +MPP_RET mpp_enc_cfg_deinit(MppEncCfg cfg); + +MPP_RET mpp_enc_cfg_set_s32(MppEncCfg cfg, const char *name, RK_S32 val); +MPP_RET mpp_enc_cfg_set_u32(MppEncCfg cfg, const char *name, RK_U32 val); +MPP_RET mpp_enc_cfg_set_s64(MppEncCfg cfg, const char *name, RK_S64 val); +MPP_RET mpp_enc_cfg_set_u64(MppEncCfg cfg, const char *name, RK_U64 val); +MPP_RET mpp_enc_cfg_set_ptr(MppEncCfg cfg, const char *name, void *val); +MPP_RET mpp_enc_cfg_set_st(MppEncCfg cfg, const char *name, void *val); + +MPP_RET mpp_enc_cfg_get_s32(MppEncCfg cfg, const char *name, RK_S32 *val); +MPP_RET mpp_enc_cfg_get_u32(MppEncCfg cfg, const char *name, RK_U32 *val); +MPP_RET mpp_enc_cfg_get_s64(MppEncCfg cfg, const char *name, RK_S64 *val); +MPP_RET mpp_enc_cfg_get_u64(MppEncCfg cfg, const char *name, RK_U64 *val); +MPP_RET mpp_enc_cfg_get_ptr(MppEncCfg cfg, const char *name, void **val); +MPP_RET mpp_enc_cfg_get_st(MppEncCfg cfg, const char *name, void *val); + +void mpp_enc_cfg_show(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __RK_VENC_CFG_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/rk_venc_cmd.h b/hardware/mpp/include/rk_venc_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..ee2594a91527ee8c0d7b003595174f25427c5a8e --- /dev/null +++ b/hardware/mpp/include/rk_venc_cmd.h @@ -0,0 +1,1215 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VENC_CMD_H__ +#define __RK_VENC_CMD_H__ + +#include "mpp_frame.h" +#include "rk_venc_rc.h" + +/* + * Configure of encoder is very complicated. So we divide configures into + * four parts: + * + * 1. Rate control parameter + * This is quality and bitrate request from user. + * + * 2. Data source MppFrame parameter + * This is data source buffer information. + * Now it is PreP config + * PreP : Encoder Preprocess configuration + * + * 3. Video codec infomation + * This is user custormized stream information. + * including: + * H.264 / H.265 / vp8 / mjpeg + * + * 4. Misc parameter + * including: + * Split : Slice split configuration + * GopRef: Reference gop configuration + * ROI : Region Of Interest + * OSD : On Screen Display + * MD : Motion Detection + * + * The module transcation flow is as follows: + * + * + + + * User | Mpi/Mpp | EncImpl + * | | Hal + * | | + * +----------+ | +---------+ | +-----------+ + * | | | | +-----RcCfg-----> | + * | RcCfg +---------> | | | EncImpl | + * | | | | | +-Frame-----> | + * +----------+ | | | | | +--+-----^--+ + * | | | | | | | + * | | | | | | | + * +----------+ | | | | | syntax | + * | | | | | | | | | + * | MppFrame +---------> MppEnc +---+ | | result + * | | | | | | | | | + * +----------+ | | | | | | | + * | | | | | +--v-----+--+ + * | | | +-Frame-----> | + * +----------+ | | | | | | + * | | | | +---CodecCfg----> Hal | + * | CodecCfg +---------> | | | | + * | | | | <-----Extra-----> | + * +----------+ | +---------+ | +-----------+ + * | | + * | | + * + + + * + * The function call flow is shown below: + * + * mpi mpp_enc controller hal + * + + + + + * | | | | + * | | | | + * +----------init------------> | | + * | | | | + * | | | | + * | PrepCfg | | | + * +---------control----------> PrepCfg | | + * | +-----control-----> | + * | | | PrepCfg | + * | +--------------------------control--------> + * | | | allocate + * | | | buffer + * | | | | + * | RcCfg | | | + * +---------control----------> RcCfg | | + * | +-----control-----> | + * | | rc_init | + * | | | | + * | | | | + * | CodecCfg | | | + * +---------control----------> | CodecCfg | + * | +--------------------------control--------> + * | | | generate + * | | | sps/pps + * | | | Get extra info | + * | +--------------------------control--------> + * | Get extra info | | | + * +---------control----------> | | + * | | | | + * | | | | + * | ROICfg | | | + * +---------control----------> | ROICfg | + * | +--------------------------control--------> + * | | | | + * | OSDCfg | | | + * +---------control----------> | OSDCfg | + * | +--------------------------control--------> + * | | | | + * | MDCfg | | | + * +---------control----------> | MDCfg | + * | +--------------------------control--------> + * | | | | + * | Set extra info | | | + * +---------control----------> | Set extra info | + * | +--------------------------control--------> + * | | | | + * | task | | | + * +----------encode----------> task | | + * | +-----encode------> | + * | | encode | + * | | | syntax | + * | +--------------------------gen_reg--------> + * | | | | + * | | | | + * | +---------------------------start---------> + * | | | | + * | | | | + * | +---------------------------wait----------> + * | | | | + * | | callback | | + * | +-----------------> | + * +--OSD-MD--encode----------> | | + * | . | | | + * | . | | | + * | . | | | + * +--OSD-MD--encode----------> | | + * | | | | + * +----------deinit----------> | | + * + + + + + */ + +/* + * base working mode parameter + */ +typedef enum MppEncBaseCfgChange_e { + MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), + MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncBaseCfgChange; + +typedef struct MppEncBaseCfg_t { + RK_U32 change; + + RK_S32 low_delay; +} MppEncBaseCfg; + +/* + * Rate control parameter + */ +typedef enum MppEncRcCfgChange_e { + MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), + MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), + MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ + MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ + MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ + MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), + MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), + MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), + MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), + MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), + MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), + MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), + MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), + MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), + /* qp related change flag */ + MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), + MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), + MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), + MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), + MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), + MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), + MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), + MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), + MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), + MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), + MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), + MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncRcCfgChange; + +typedef enum MppEncRcQuality_e { + MPP_ENC_RC_QUALITY_WORST, + MPP_ENC_RC_QUALITY_WORSE, + MPP_ENC_RC_QUALITY_MEDIUM, + MPP_ENC_RC_QUALITY_BETTER, + MPP_ENC_RC_QUALITY_BEST, + MPP_ENC_RC_QUALITY_CQP, + MPP_ENC_RC_QUALITY_AQ_ONLY, + MPP_ENC_RC_QUALITY_BUTT +} MppEncRcQuality; + +typedef struct MppEncRcCfg_t { + RK_U32 change; + + /* + * rc_mode - rate control mode + * + * mpp provide two rate control mode: + * + * Constant Bit Rate (CBR) mode + * - paramter 'bps*' define target bps + * - paramter quality and qp will not take effect + * + * Variable Bit Rate (VBR) mode + * - paramter 'quality' define 5 quality levels + * - paramter 'bps*' is used as reference but not strict condition + * - special Constant QP (CQP) mode is under VBR mode + * CQP mode will work with qp in CodecCfg. But only use for test + * + * default: CBR + */ + MppEncRcMode rc_mode; + + /* + * quality - quality parameter, only takes effect in VBR mode + * + * Mpp does not give the direct parameter in different protocol. + * + * Mpp provide total 5 quality level: + * Worst - worse - Medium - better - best + * + * extra CQP level means special constant-qp (CQP) mode + * + * default value: Medium + */ + MppEncRcQuality quality; + + /* + * bit rate parameters + * mpp gives three bit rate control parameter for control + * bps_target - target bit rate, unit: bit per second + * bps_max - maximun bit rate, unit: bit per second + * bps_min - minimun bit rate, unit: bit per second + * if user need constant bit rate set parameters to the similar value + * if user need variable bit rate set parameters as they need + */ + RK_S32 bps_target; + RK_S32 bps_max; + RK_S32 bps_min; + + /* + * frame rate parameters have great effect on rate control + * + * fps_in_flex + * 0 - fix input frame rate + * 1 - variable input frame rate + * + * fps_in_num + * input frame rate numerator, if 0 then default 30 + * + * fps_in_denorm + * input frame rate denorminator, if 0 then default 1 + * + * fps_out_flex + * 0 - fix output frame rate + * 1 - variable output frame rate + * + * fps_out_num + * output frame rate numerator, if 0 then default 30 + * + * fps_out_denorm + * output frame rate denorminator, if 0 then default 1 + */ + RK_S32 fps_in_flex; + RK_S32 fps_in_num; + RK_S32 fps_in_denorm; + RK_S32 fps_out_flex; + RK_S32 fps_out_num; + RK_S32 fps_out_denorm; + + /* + * gop - group of picture, gap between Intra frame + * 0 for only 1 I frame the rest are all P frames + * 1 for all I frame + * 2 for I P I P I P + * 3 for I P P I P P + * etc... + */ + RK_S32 gop; + + /* + * skip_cnt - max continuous frame skip count + * 0 - frame skip is not allow + */ + RK_S32 skip_cnt; + + /* + * max_reenc_times - max reencode time for one frame + * 0 - reencode is not allowed + * 1~3 max reencode time is limited to 3 + */ + RK_U32 max_reenc_times; + + /* + * stats_time - the time of bitrate statistics + */ + RK_S32 stats_time; + + /* + * drop frame parameters + * used on bitrate is far over the max bitrate + * + * drop_mode + * + * MPP_ENC_RC_DROP_FRM_DISABLED + * - do not drop frame when bitrate overflow. + * MPP_ENC_RC_DROP_FRM_NORMAL + * - do not encode the dropped frame when bitrate overflow. + * MPP_ENC_RC_DROP_FRM_PSKIP + * - encode a all skip frame when bitrate overflow. + * + * drop_threshold + * + * The percentage threshold over max_bitrate for trigger frame drop. + * + * drop_gap + * The max continuous frame drop number + */ + MppEncRcDropFrmMode drop_mode; + RK_U32 drop_threshold; + RK_U32 drop_gap; + + MppEncRcSuperFrameMode super_mode; + RK_U32 super_i_thd; + RK_U32 super_p_thd; + + MppEncRcPriority rc_priority; + + RK_U32 debreath_en; + RK_U32 debre_strength; + RK_S32 max_i_prop; + RK_S32 min_i_prop; + RK_S32 init_ip_ratio; + + /* general qp control */ + RK_S32 qp_init; + RK_S32 qp_max; + RK_S32 qp_max_i; + RK_S32 qp_min; + RK_S32 qp_min_i; + RK_S32 qp_max_step; /* delta qp between each two P frame */ + RK_S32 qp_delta_ip; /* delta qp between I and P */ + RK_S32 qp_delta_vi; /* delta qp between vi and P */ + + RK_S32 hier_qp_en; + RK_S32 hier_qp_delta[4]; + RK_S32 hier_frame_num[4]; +} MppEncRcCfg; + + +typedef enum MppEncHwCfgChange_e { + /* qp related hardware config flag */ + MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), + MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), + MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), + MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), + MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), + MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), + MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncHwCfgChange; + +/* + * Hardware related rate control config + * + * This config will open some detail feature to external user to control + * hardware behavior directly. + */ +typedef struct MppEncHwCfg_t { + RK_U32 change; + + /* vepu541/vepu540 */ + RK_S32 qp_delta_row; /* delta qp between two row in P frame */ + RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ + RK_U32 aq_thrd_i[16]; + RK_U32 aq_thrd_p[16]; + RK_S32 aq_step_i[16]; + RK_S32 aq_step_p[16]; +} MppEncHwCfg; + +/* + * Mpp preprocess parameter + */ +typedef enum MppEncPrepCfgChange_e { + MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ + MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ + /* transform parameter */ + MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on ration */ + MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ + /* enhancement parameter */ + MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ + MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ + /* color related parameter */ + MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ + MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ + MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ + MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ + + MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncPrepCfgChange; + +/* + * Preprocess sharpen parameter + * + * 5x5 sharpen core + * + * enable_y - enable luma sharpen + * enable_uv - enable chroma sharpen + */ +typedef struct { + RK_U32 enable_y; + RK_U32 enable_uv; + RK_S32 coef[5]; + RK_S32 div; + RK_S32 threshold; +} MppEncPrepSharpenCfg; + +/* + * input frame rotation parameter + * 0 - disable rotation + * 1 - 90 degree + * 2 - 180 degree + * 3 - 270 degree + */ +typedef enum MppEncRotationCfg_e { + MPP_ENC_ROT_0, + MPP_ENC_ROT_90, + MPP_ENC_ROT_180, + MPP_ENC_ROT_270, + MPP_ENC_ROT_BUTT +} MppEncRotationCfg; + +typedef struct MppEncPrepCfg_t { + RK_U32 change; + + /* + * Mpp encoder input data dimension config + * + * width / height / hor_stride / ver_stride / format + * These information will be used for buffer allocation and rc config init + * The output format is always YUV420. So if input is RGB then color + * conversion will be done internally + */ + RK_S32 width; + RK_S32 height; + RK_S32 hor_stride; + RK_S32 ver_stride; + + /* + * Mpp encoder input data format config + */ + MppFrameFormat format; + MppFrameColorSpace color; + MppFrameColorPrimaries colorprim; + MppFrameColorTransferCharacteristic colortrc; + MppFrameColorRange range; + + MppEncRotationCfg rotation; + + /* + * input frame mirroring parameter + * 0 - disable mirroring + * 1 - horizontal mirroring + * 2 - vertical mirroring + */ + RK_S32 mirroring; + + RK_S32 denoise; + + MppEncPrepSharpenCfg sharpen; +} MppEncPrepCfg; + +/* + * Mpp Motion Detection parameter + * + * Mpp can output Motion Detection infomation for each frame. + * If user euqueue a encode task with KEY_MOTION_INFO by following function + * then encoder will output Motion Detection information to the buffer. + * + * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); + * + * Motion Detection information will be organized in this way: + * 1. Each 16x16 block will have a 32 bit block information which contains + * 15 bit SAD(Sum of Abstract Difference value + * 9 bit signed horizontal motion vector + * 8 bit signed vertical motion vector + * 2. The sequence of MD information in the buffer is corresponding to the + * block position in the frame, left-to right, top-to-bottom. + * 3. If the width of the frame is not a multiple of 256 pixels (16 macro + * blocks), DMA would extend the frame to a multiple of 256 pixels and + * the extended blocks' MD information are 32'h0000_0000. + * 4. Buffer must be ion buffer and 1024 byte aligned. + */ +typedef struct MppEncMDBlkInfo_t { + RK_U32 sad : 15; /* bit 0~14 - SAD */ + RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ + RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ +} MppEncMDBlkInfo; + +typedef enum MppEncHeaderMode_e { + /* default mode: attach vps/sps/pps only on first frame */ + MPP_ENC_HEADER_MODE_DEFAULT, + /* IDR mode: attach vps/sps/pps on each IDR frame */ + MPP_ENC_HEADER_MODE_EACH_IDR, + MPP_ENC_HEADER_MODE_BUTT, +} MppEncHeaderMode; + +typedef enum MppEncSeiMode_e { + MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ + MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ + MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ +} MppEncSeiMode; + +/* + * Mpp codec parameter + * parameter is defined from here + */ + +/* + * H.264 configurable parameter + */ +typedef enum MppEncH264CfgChange_e { + /* change on stream type */ + MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), + /* change on svc / profile / level */ + MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), + /* change on entropy_coding_mode / cabac_init_idc */ + MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), + + /* change on transform8x8_mode */ + MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), + /* change on constrained_intra_pred_mode */ + MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), + /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ + MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), + /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ + MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), + /* change on use_longterm */ + MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), + /* change on scaling_list_mode */ + MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), + /* change on poc type */ + MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), + /* change on log2 max poc lsb minus 4 */ + MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), + /* change on log2 max frame number minus 4 */ + MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), + /* change on gaps_in_frame_num_value_allowed_flag */ + MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), + + /* change on max_qp / min_qp */ + MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), + /* change on max_qp_i / min_qp_i */ + MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), + /* change on max_qp_step */ + MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), + /* change on qp_delta_ip */ + MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), + /* change on intra_refresh_mode / intra_refresh_arg */ + MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), + /* change on max long-term reference frame count */ + MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), + /* change on max temporal id */ + MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), + /* change on adding prefix nal */ + MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), + /* change on base layer priority id */ + MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), + + /* change on vui */ + MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), + MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncH264CfgChange; + +typedef struct MppEncH264Cfg_t { + RK_U32 change; + + /* + * H.264 stream format + * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' + * 1 - Plain NAL units without startcode + */ + RK_S32 stream_type; + + /* + * H.264 codec syntax config + * + * do NOT setup the three option below unless you are familiar with encoder detail + * poc_type - picture order count type 0 ~ 2 + * log2_max_poc_lsb - used in sps with poc_type 0, + * log2_max_frame_num - used in sps + */ + RK_U32 poc_type; + RK_U32 log2_max_poc_lsb; + RK_U32 log2_max_frame_num; + RK_U32 gaps_not_allowed; + + /* + * H.264 profile_idc parameter + * 66 - Baseline profile + * 77 - Main profile + * 100 - High profile + */ + RK_S32 profile; + + /* + * H.264 level_idc parameter + * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps + * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps + * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps + * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps + * 50 / 51 / 52 - 4K@30fps + */ + RK_S32 level; + + /* + * H.264 entropy coding method + * 0 - CAVLC + * 1 - CABAC + * When CABAC is select cabac_init_idc can be range 0~2 + */ + RK_S32 entropy_coding_mode; + RK_S32 cabac_init_idc; + + /* + * 8x8 intra prediction and 8x8 transform enable flag + * This flag can only be enable under High profile + * 0 : disable (BP/MP) + * 1 : enable (HP) + */ + RK_S32 transform8x8_mode; + + /* + * 0 : disable + * 1 : enable + */ + RK_S32 constrained_intra_pred_mode; + + /* + * 0 : flat scaling list + * 1 : default scaling list for all cases + * 2 : customized scaling list (not supported) + */ + RK_S32 scaling_list_mode; + + /* + * chroma qp offset (-12 - 12) + */ + RK_S32 chroma_cb_qp_offset; + RK_S32 chroma_cr_qp_offset; + + /* + * H.264 deblock filter mode flag + * 0 : enable + * 1 : disable + * 2 : disable deblocking filter at slice boundaries + * + * deblock filter offset alpha (-6 - 6) + * deblock filter offset beta (-6 - 6) + */ + RK_S32 deblock_disable; + RK_S32 deblock_offset_alpha; + RK_S32 deblock_offset_beta; + + /* + * H.264 long term reference picture enable flag + * 0 - disable + * 1 - enable + */ + RK_S32 use_longterm; + + /* + * quality config + * qp_max - 8 ~ 51 + * qp_max_i - 10 ~ 40 + * qp_min - 8 ~ 48 + * qp_min_i - 10 ~ 40 + * qp_max_step - max delta qp step between two frames + */ + RK_S32 qp_init; + RK_S16 qp_max; + RK_S16 qp_max_i; + RK_S16 qp_min; + RK_S16 qp_min_i; + RK_S16 qp_max_step; + RK_S16 qp_delta_ip; + + /* + * intra fresh config + * + * intra_refresh_mode + * 0 - no intra refresh + * 1 - intra refresh by MB row + * 2 - intra refresh by MB column + * 3 - intra refresh by MB gap + * + * intra_refresh_arg + * mode 0 - no effect + * mode 1 - refresh MB row number + * mode 2 - refresh MB colmn number + * mode 3 - refresh MB gap count + */ + RK_S32 intra_refresh_mode; + RK_S32 intra_refresh_arg; + + /* extra mode config */ + RK_S32 max_ltr_frames; + RK_S32 max_tid; + RK_S32 prefix_mode; + RK_S32 base_layer_pid; +} MppEncH264Cfg; + +#define H265E_MAX_ROI_NUMBER 64 + +typedef struct H265eRect_t { + RK_S32 left; + RK_S32 right; + RK_S32 top; + RK_S32 bottom; +} H265eRect; + +typedef struct H265eRoi_Region_t { + RK_U8 level; + H265eRect rect; +} H265eRoiRegion; + +/* + * roi region only can be setting when rc_enable = 1 + */ +typedef struct MppEncH265RoiCfg_t { + /* + * the value is defined by H265eCtuMethod + */ + + RK_U8 method; + /* + * the number of roi,the value must less than H265E_MAX_ROI_NUMBER + */ + RK_S32 num; + + /* delat qp using in roi region */ + RK_U32 delta_qp; + + /* roi region */ + H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; +} MppEncH265RoiCfg; + +typedef struct H265eCtuQp_t { + /* the qp value using in ctu region */ + RK_U32 qp; + + /* + * define the ctu region + * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size + * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates + */ + H265eRect rect; +} H265eCtu; + +typedef struct H265eCtuRegion_t { + /* + * the value is defined by H265eCtuMethod + */ + RK_U8 method; + + /* + * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER + */ + RK_S32 num; + + /* ctu region */ + H265eCtu ctu[H265E_MAX_ROI_NUMBER]; +} MppEncH265CtuCfg; + +/* + * define the method when set CTU/ROI parameters + * this value is using by method in H265eCtuRegion or H265eRoi struct + */ +typedef enum { + H265E_METHOD_CTU_SIZE, + H264E_METHOD_COORDINATE, +} H265eCtuMethod; + +/* + * H.265 configurable parameter + */ +typedef struct MppEncH265VuiCfg_t { + RK_U32 change; + RK_S32 vui_present; + RK_S32 vui_aspect_ratio; + RK_S32 vui_sar_size; + RK_S32 full_range; + RK_S32 time_scale; +} MppEncH265VuiCfg; + +typedef enum MppEncH265CfgChange_e { + /* change on stream type */ + MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), + MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), + MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), + MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), + MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), + MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), + MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), + MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), + MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), + MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), + MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), + MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), + MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), + MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), + MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), + MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), + MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), + MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), + MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), + MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), + MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), + MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), + MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncH265CfgChange; + +typedef struct MppEncH265SliceCfg_t { + /* default value: 0, means no slice split */ + RK_U32 split_enable; + + /* 0: by bits number; 1: by lcu line number */ + RK_U32 split_mode; + + /* + * when splitmode is 0, this value presents bits number, + * when splitmode is 1, this value presents lcu line number + */ + RK_U32 slice_size; + RK_U32 loop_filter_across_slices_enabled_flag; +} MppEncH265SliceCfg; + +typedef struct MppEncH265CuCfg_t { + RK_U32 cu32x32_en; /* default: 1 */ + RK_U32 cu16x16_en; /* default: 1 */ + RK_U32 cu8x8_en; /* default: 1 */ + RK_U32 cu4x4_en; /* default: 1 */ + + // intra pred + RK_U32 constrained_intra_pred_flag; /* default: 0 */ + RK_U32 strong_intra_smoothing_enabled_flag; /* INTRA_SMOOTH */ + RK_U32 pcm_enabled_flag; /* default: 0, enable ipcm */ + RK_U32 pcm_loop_filter_disabled_flag; +} MppEncH265CuCfg; + +typedef struct MppEncH265RefCfg_t { + RK_U32 num_lt_ref_pic; /* default: 0 */ +} MppEncH265RefCfg; + +typedef struct MppEncH265DblkCfg_t { + RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ + RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ + RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ +} MppEncH265DblkCfg_t; + +typedef struct MppEncH265SaoCfg_t { + RK_U32 slice_sao_luma_flag; + RK_U32 slice_sao_chroma_flag; +} MppEncH265SaoCfg; + +typedef struct MppEncH265TransCfg_t { + RK_U32 transquant_bypass_enabled_flag; + RK_U32 transform_skip_enabled_flag; + RK_U32 defalut_ScalingList_enable; /* default: 0 */ + RK_S32 cb_qp_offset; + RK_S32 cr_qp_offset; +} MppEncH265TransCfg; + +typedef struct MppEncH265MergeCfg_t { + RK_U32 max_mrg_cnd; + RK_U32 merge_up_flag; + RK_U32 merge_left_flag; +} MppEncH265MergesCfg; + +typedef struct MppEncH265EntropyCfg_t { + RK_U32 cabac_init_flag; /* default: 0 */ +} MppEncH265EntropyCfg; + +typedef struct MppEncH265Cfg_t { + RK_U32 change; + + /* H.265 codec syntax config */ + RK_S32 profile; + RK_S32 level; + RK_S32 tier; + + /* constraint intra prediction flag */ + RK_S32 const_intra_pred; + RK_S32 ctu_size; + RK_S32 max_cu_size; + RK_S32 tmvp_enable; + RK_S32 amp_enable; + RK_S32 wpp_enable; + RK_S32 merge_range; + RK_S32 sao_enable; + RK_U32 num_ref; + + /* quality config */ + RK_S32 max_qp; + RK_S32 min_qp; + RK_S32 max_i_qp; + RK_S32 min_i_qp; + RK_S32 ip_qp_delta; + RK_S32 max_delta_qp; + RK_S32 intra_qp; + RK_S32 gop_delta_qp; + RK_S32 qp_init; + RK_S32 qp_max_step; + RK_S32 raw_dealt_qp; + RK_U8 qpmax_map[8]; + RK_U8 qpmin_map[8]; + RK_S32 qpmap_mode; + + /* intra fresh config */ + RK_S32 intra_refresh_mode; + RK_S32 intra_refresh_arg; + + /* slice mode config */ + RK_S32 independ_slice_mode; + RK_S32 independ_slice_arg; + RK_S32 depend_slice_mode; + RK_S32 depend_slice_arg; + + MppEncH265CuCfg cu_cfg; + MppEncH265SliceCfg slice_cfg; + MppEncH265EntropyCfg entropy_cfg; + MppEncH265TransCfg trans_cfg; + MppEncH265SaoCfg sao_cfg; + MppEncH265DblkCfg_t dblk_cfg; + MppEncH265RefCfg ref_cfg; + MppEncH265MergesCfg merge_cfg; + + /* extra info */ + MppEncH265VuiCfg vui; + + MppEncH265CtuCfg ctu; + MppEncH265RoiCfg roi; +} MppEncH265Cfg; + +/* + * motion jpeg configurable parameter + */ +typedef enum MppEncJpegCfgChange_e { + /* change on quant parameter */ + MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), + MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), + MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), + MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncJpegCfgChange; + +typedef struct MppEncJpegCfg_t { + RK_U32 change; + RK_S32 quant; + /* + * quality factor config + * + * q_factor - 1 ~ 99 + * qf_max - 1 ~ 99 + * qf_min - 1 ~ 99 + * qtable_y: qtable for luma + * qtable_u: qtable for chroma + * qtable_v: default equal qtable_u + */ + RK_S32 q_factor; + RK_S32 qf_max; + RK_S32 qf_min; + RK_U8 *qtable_y; + RK_U8 *qtable_u; + RK_U8 *qtable_v; +} MppEncJpegCfg; + +/* + * vp8 configurable parameter + */ +typedef enum MppEncVP8CfgChange_e { + MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), + MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), + MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncVP8CfgChange; + +typedef struct MppEncVp8Cfg_t { + RK_U32 change; + RK_S32 quant; + + RK_S32 qp_init; + RK_S32 qp_max; + RK_S32 qp_max_i; + RK_S32 qp_min; + RK_S32 qp_min_i; + RK_S32 qp_max_step; + RK_S32 disable_ivf; +} MppEncVp8Cfg; + +/** + * @ingroup rk_mpi + * @brief MPP encoder codec configuration parameters + * @details The encoder codec configuration parameters are different for each + * compression codings. For example, H.264 encoder can configure + * profile, level, qp, etc. while jpeg encoder can configure qp + * only. The detailed parameters can refer the corresponding data + * structure such as MppEncH264Cfg and MppEncJpegCfg. This data + * structure is associated with MPP_ENC_SET_CODEC_CFG command. + */ +typedef struct MppEncCodecCfg_t { + MppCodingType coding; + + union { + RK_U32 change; + MppEncH264Cfg h264; + MppEncH265Cfg h265; + MppEncJpegCfg jpeg; + MppEncVp8Cfg vp8; + }; +} MppEncCodecCfg; + +typedef enum MppEncSliceSplit_e { + /* change on quant parameter */ + MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), + MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), + MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncSliceSplitChange; + +typedef enum MppEncSplitMode_e { + MPP_ENC_SPLIT_NONE, + MPP_ENC_SPLIT_BY_BYTE, + MPP_ENC_SPLIT_BY_CTU, +} MppEncSplitMode; + +typedef struct MppEncSliceSplit_t { + RK_U32 change; + + /* + * slice split mode + * + * MPP_ENC_SPLIT_NONE - No slice is split + * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number + * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number + */ + RK_U32 split_mode; + + /* + * slice split size parameter + * + * When split by byte number this value is the max byte number for each + * slice. + * When split by macroblock / ctu number this value is the MB/CTU number + * for each slice. + */ + RK_U32 split_arg; +} MppEncSliceSplit; + +/** + * @brief Mpp ROI parameter + * Region configure define a rectangle as ROI + * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. + * These parameters MUST retain in memory when encoder is running. + * Both absolute qp and relative qp are supported in vepu541. + * Only absolute qp is supported in rv1108 + */ +typedef struct MppEncROIRegion_t { + RK_U16 x; /**< horizontal position of top left corner */ + RK_U16 y; /**< vertical position of top left corner */ + RK_U16 w; /**< width of ROI rectangle */ + RK_U16 h; /**< height of ROI rectangle */ + RK_U16 intra; /**< flag of forced intra macroblock */ + RK_S16 quality; /**< absolute / relative qp of macroblock */ + RK_U16 qp_area_idx; /**< qp min max area select*/ + RK_U8 area_map_en; /**< enable area map */ + RK_U8 abs_qp_en; /**< absolute qp enable flag*/ +} MppEncROIRegion; + +/** + * @brief MPP encoder's ROI configuration + */ +typedef struct MppEncROICfg_t { + RK_U32 number; /**< ROI rectangle number */ + MppEncROIRegion *regions; /**< ROI parameters */ +} MppEncROICfg; + +/* + * Mpp OSD parameter + * + * Mpp OSD support total 8 regions + * Mpp OSD support 256-color palette two mode palette: + * 1. Configurable OSD palette + * When palette is set. + * 2. fixed OSD palette + * When palette is NULL. + * + * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, + * every level composed of 32 bits defined below: + * Y : 8 bits + * U : 8 bits + * V : 8 bits + * alpha : 8 bits + */ +#define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) +#define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|(16<<8)|210) +#define MPP_ENC_OSD_PLT_CYAN ((255<<24)|(16<<16)|(166<<8)|170) +#define MPP_ENC_OSD_PLT_GREEN ((255<<24)|(34<<16)|(54<<8)|145) +#define MPP_ENC_OSD_PLT_TRANS ((0<<24)|(222<<16)|(202<<8)|106) +#define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|(90<<8)| 81) +#define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) +#define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) + +typedef enum MppEncOSDPltType_e { + MPP_ENC_OSD_PLT_TYPE_DEFAULT, + MPP_ENC_OSD_PLT_TYPE_USERDEF, + MPP_ENC_OSD_PLT_TYPE_BUTT, +} MppEncOSDPltType; + +/* OSD palette value define */ +typedef union MppEncOSDPltVal_u { + struct { + RK_U32 v : 8; + RK_U32 u : 8; + RK_U32 y : 8; + RK_U32 alpha : 8; + }; + RK_U32 val; +} MppEncOSDPltVal; + +typedef struct MppEncOSDPlt_t { + MppEncOSDPltVal data[256]; +} MppEncOSDPlt; + +typedef enum MppEncOSDPltCfgChange_e { + MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ + MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ + MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), +} MppEncOSDPltCfgChange; + +typedef struct MppEncOSDPltCfg_t { + RK_U32 change; + MppEncOSDPltType type; + MppEncOSDPlt *plt; +} MppEncOSDPltCfg; + +/* position info is unit in 16 pixels(one MB), and + * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; + * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; + */ +typedef struct MppEncOSDRegion_t { + RK_U32 enable; + RK_U32 inverse; + RK_U32 start_mb_x; + RK_U32 start_mb_y; + RK_U32 num_mb_x; + RK_U32 num_mb_y; + RK_U32 buf_offset; +} MppEncOSDRegion; + +/* if num_region > 0 && region==NULL + * use old osd data + */ +typedef struct MppEncOSDData_t { + MppBuffer buf; + RK_U32 num_region; + MppEncOSDRegion region[8]; +} MppEncOSDData; + +typedef struct MppEncOSDRegion2_t { + RK_U32 enable; + RK_U32 inverse; + RK_U32 start_mb_x; + RK_U32 start_mb_y; + RK_U32 num_mb_x; + RK_U32 num_mb_y; + RK_U32 buf_offset; + MppBuffer buf; +} MppEncOSDRegion2; + +typedef struct MppEncOSDData2_t { + RK_U32 num_region; + MppEncOSDRegion2 region[8]; +} MppEncOSDData2; + +typedef struct MppEncUserData_t { + RK_U32 len; + void *pdata; +} MppEncUserData; + +typedef struct MppEncUserDataFull_t { + RK_U32 len; + RK_U8 *uuid; + void *pdata; +} MppEncUserDataFull; + +typedef struct MppEncUserDataSet_t { + RK_U32 count; + MppEncUserDataFull *datas; +} MppEncUserDataSet; + +#endif /* __RK_VENC_CMD_H__ */ diff --git a/hardware/mpp/include/rk_venc_rc.h b/hardware/mpp/include/rk_venc_rc.h new file mode 100644 index 0000000000000000000000000000000000000000..d58f9e29c73cd1a468989408c21660e210e384fb --- /dev/null +++ b/hardware/mpp/include/rk_venc_rc.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VENC_RC_H__ +#define __RK_VENC_RC_H__ + +/* Rate control parameter */ +typedef enum MppEncRcMode_e { + MPP_ENC_RC_MODE_VBR, + MPP_ENC_RC_MODE_CBR, + MPP_ENC_RC_MODE_FIXQP, + MPP_ENC_RC_MODE_AVBR, + MPP_ENC_RC_MODE_BUTT +} MppEncRcMode; + +typedef enum MppEncRcPriority_e { + MPP_ENC_RC_BY_BITRATE_FIRST, + MPP_ENC_RC_BY_FRM_SIZE_FIRST, + MPP_ENC_RC_PRIORITY_BUTT +} MppEncRcPriority; + +typedef enum MppEncRcDropFrmMode_e { + MPP_ENC_RC_DROP_FRM_DISABLED, + MPP_ENC_RC_DROP_FRM_NORMAL, + MPP_ENC_RC_DROP_FRM_PSKIP, + MPP_ENC_RC_DROP_FRM_BUTT +} MppEncRcDropFrmMode; + +typedef enum MppEncRcSuperFrameMode_t { + MPP_ENC_RC_SUPER_FRM_NONE, + MPP_ENC_RC_SUPER_FRM_DROP, + MPP_ENC_RC_SUPER_FRM_REENC, + MPP_ENC_RC_SUPER_FRM_BUTT +} MppEncRcSuperFrameMode; + +typedef enum MppEncRcGopMode_e { + MPP_ENC_RC_NORMAL_P, + MPP_ENC_RC_SMART_P, + MPP_ENC_RC_GOP_MODE_BUTT, +} MppEncRcGopMode; + +#endif /* __RK_VENC_RC_H__ */ diff --git a/hardware/mpp/include/rk_venc_ref.h b/hardware/mpp/include/rk_venc_ref.h new file mode 100644 index 0000000000000000000000000000000000000000..fff7d862c7d6c14307e4d20189475c1303dc20d6 --- /dev/null +++ b/hardware/mpp/include/rk_venc_ref.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RK_VENC_REF_H__ +#define __RK_VENC_REF_H__ + +#include "rk_type.h" +#include "mpp_err.h" + +/* + * MPP reference management system follows the model of H.264/H.265 reference + * frame mangement. + * + * The reference frame is defined into two type: long-term reference frame and + * short-refernce frame (lt_ref and st_ref). + * + * The lt_ref can be only indexed by long-term reference frame index (lt_idx). + * The st_ref can be indexed by its temporal id (tid) and previous count. + * + * MppEncRefMode defined the way for user to reference the required frame. + * + * Normal reference mode without argument + * REF_TO_PREV_REF_FRM - refer to previous reference frame in encode order (No matter Lt or St) + * REF_TO_PREV_ST_REF - refer to previous short-term reference frame + * REF_TO_PREV_LT_REF - refer to previous long-term reference frame + * REF_TO_PREV_INTRA - refer to previous Intra / IDR frame + * REF_TO_ST_REF_SETUP - refer to refernce frame defined in StRefSetup + * + * Normal reference mode with argument + * REF_TO_TEMPORAL_LAYER - refer to previous reference frame with temporal id argument + * REF_TO_LT_REF_IDX - refer to long-term reference frame with lt_ref_idx argument + * REF_TO_ST_PREV_N_REF - refer to short-term reference frame with diff frame_num argument + * + * Long-term reference only mode + * REF_TO_ST_REF_SETUP - use corresponding mode of original short-term reference frame + * + * Short-term reference only mode + * REF_TO_LT_REF_SETUP - indicate that this frame will be overwrited by long-term config + * + * By combining frames with these modes user can define many kinds of reference hierarchy + * structure. But normally user should use simplified preset hierarchy pattern. + * + * The rules for virtual cpb management is similiar to H.264/H.265 + * 1. When one frame is marked as long-term reference frame it will be kept in cpb until + * it is replaced by other frame with the same lt_idx or IDR frame. + * 2. When one frame is marked as short-term reference frame it will be inert into cpb when + * there is enough storage space. When the number of total sum of long-term and short-term + * reference frame excess the cpb size limit the oldest short-term frame will be removed. + * This is call sliding window in H.264. + */ + +/* max 4 temporal layer */ +#define MPP_ENC_MAX_TEMPORAL_LAYER_NUM 4 +/* max 4 long-term reference frame */ +#define MPP_ENC_MAX_LT_REF_NUM 16 + +/* + * Group Of Picture (GOP) config is separated into three parts: + * + * 1. Intra / IDR frame config + * igop - the interval of two intra / IDR frames + * + * 2. Long-term reference config (MppEncRefLtFrmCfg) + * + * Setup long-term reference index max lt_idx, loop interval and reference + * mode for auto long-term reference frame generation. The encoder will + * mark frame to be long-term reference frame with given interval. + * + * 2.1 lt_idx + * The long-term reference frame index is unique identifier for a long-term + * reference frame. + * The max long-term reference frame index should NOT larger than + * max_num_ref_frames in sps. + * + * 2.2 lt_gap + * When lt_gap is zero the long-term reference frame generation is disabled. + * When lt_gap is non-zero (usually 2~3 second interval) then the long-term + * reference frame will be generated for error recovery or smart hierarchy. + * + * 2.2 lt_delay + * The lt_delay is the delay time for generation of long-term reference frame. + * The start point of lt_delay is the IDR/intra frame genertaed by igop. + * + * 2.4 ref_mode: Long-term refernce frame reference mode + * NOTE: temporal id of longterm reference frame is always zero. + * + * Examples: + * Sequence has only one lt_ref 0 and setup one long-term reference frame + * every 300 frame. + * { + * .lt_idx = 0, + * .lt_gap = 300, + * .lt_delay = 0, + * } + * result: + * frame 0 ...... 299 300 301 ...... 599 600 601 + * lt_idx 0 xxxxxx x 0 x xxxxxx x 0 x + * + * Sequence has lt_ref from 0 to 2 and setup a long-term reference frame + * every 100 frame. + * { + * .lt_idx = 0, + * .lt_gap = 300, + * .lt_delay = 0, + * } + * { + * .lt_idx = 1, + * .lt_gap = 300, + * .lt_delay = 100, + * } + * { + * .lt_idx = 2, + * .lt_gap = 300, + * .lt_delay = 200, + * } + * result: + * frame 0 ... 99 100 101 ... 199 200 201 ... 299 300 301 + * lt_idx 0 xxx x 1 x xxx x 2 x xxx x 0 x + * + * 3. Short-term reference config (MppEncStRefSetup) + * + * 3.1 is_non_ref + * The is_non_ref indicated the current frame is reference frame or not. + * + * 3.2 temporal_id + * The temporal id of the current frame configure. + * + * 3.3 ref_mode: short-term refernce frame reference mode + * + * 3.4 repeat + * The repeat time of the short-term reference frame configure. + * The overall frame count with the same config is repeat + 1. + * + * Examples: + * + */ + +#define REF_MODE_MODE_MASK (0x1F) +#define REF_MODE_ARG_MASK (0xFFFF0000) + +typedef enum MppEncRefMode_e { + /* max 32 mode in 32-bit */ + /* for default ref global config */ + REF_MODE_GLOBAL, + REF_TO_PREV_REF_FRM = REF_MODE_GLOBAL, + REF_TO_PREV_ST_REF, + REF_TO_PREV_LT_REF, + REF_TO_PREV_INTRA, + + /* for global config with args */ + REF_MODE_GLOBAL_WITH_ARG = 0x4, + /* with ref arg as temporal layer id */ + REF_TO_TEMPORAL_LAYER = REF_MODE_GLOBAL_WITH_ARG, + /* with ref arg as long-term reference picture index */ + REF_TO_LT_REF_IDX, + /* with ref arg as short-term reference picture difference frame_num */ + REF_TO_ST_PREV_N_REF, + REF_MODE_GLOBAL_BUTT, + + /* for lt-ref */ + REF_MODE_LT = 0x18, + REF_TO_ST_REF_SETUP, + REF_MODE_LT_BUTT, + + /* for st-ref */ + REF_MODE_ST = 0x1C, + REF_TO_LT_REF_SETUP, + REF_MODE_ST_BUTT, +} MppEncRefMode; + +typedef struct MppEncRefLtFrmCfg_t { + RK_S32 lt_idx; /* lt_idx of the reference frame */ + RK_S32 temporal_id; /* temporal_id of the reference frame */ + MppEncRefMode ref_mode; + RK_S32 ref_arg; + RK_S32 lt_gap; /* gap between two lt-ref with same lt_idx */ + RK_S32 lt_delay; /* delay offset to igop start frame */ +} MppEncRefLtFrmCfg; + +typedef struct MppEncRefStFrmCfg_t { + RK_S32 is_non_ref; + RK_S32 temporal_id; + MppEncRefMode ref_mode; + RK_S32 ref_arg; + RK_S32 repeat; /* repeat times */ +} MppEncRefStFrmCfg; + +typedef struct MppEncRefPreset_t { + /* input parameter for query */ + const char *name; + RK_S32 max_lt_cnt; + RK_S32 max_st_cnt; + MppEncRefLtFrmCfg *lt_cfg; + MppEncRefStFrmCfg *st_cfg; + + /* output parameter */ + RK_S32 lt_cnt; + RK_S32 st_cnt; +} MppEncRefPreset; + +typedef void* MppEncRefCfg; + +#ifdef __cplusplus +extern "C" { +#endif + +MPP_RET mpp_enc_ref_cfg_init(MppEncRefCfg *ref); +MPP_RET mpp_enc_ref_cfg_deinit(MppEncRefCfg *ref); + +MPP_RET mpp_enc_ref_cfg_reset(MppEncRefCfg ref); +MPP_RET mpp_enc_ref_cfg_set_cfg_cnt(MppEncRefCfg ref, RK_S32 lt_cnt, RK_S32 st_cnt); +MPP_RET mpp_enc_ref_cfg_add_lt_cfg(MppEncRefCfg ref, RK_S32 cnt, MppEncRefLtFrmCfg *frm); +MPP_RET mpp_enc_ref_cfg_add_st_cfg(MppEncRefCfg ref, RK_S32 cnt, MppEncRefStFrmCfg *frm); +MPP_RET mpp_enc_ref_cfg_check(MppEncRefCfg ref); + +/* + * A new reference configure will restart a new gop and clear cpb by default. + * The keep cpb function will let encoder keeps the current cpb status and do NOT + * reset all the reference frame in cpb. + */ +MPP_RET mpp_enc_ref_cfg_set_keep_cpb(MppEncRefCfg ref, RK_S32 keep); +MPP_RET mpp_enc_ref_cfg_get_preset(MppEncRefPreset *preset); +MPP_RET mpp_enc_ref_cfg_show(MppEncRefCfg ref); + +#ifdef __cplusplus +} +#endif + +#endif /* __RK_VENC_REF_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/vcodec_service.h b/hardware/mpp/include/vcodec_service.h new file mode 100644 index 0000000000000000000000000000000000000000..5d4bc075c60ea63cc7098c978a3c86f019614cb9 --- /dev/null +++ b/hardware/mpp/include/vcodec_service.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VCODEC_SERVICE_H__ +#define __VCODEC_SERVICE_H__ + +#include "rk_type.h" + +#define EXTRA_INFO_MAGIC (0x4C4A46) + +#define VPU_IOC_MAGIC 'l' + +#define VPU_IOC_SET_CLIENT_TYPE _IOW(VPU_IOC_MAGIC, 1, unsigned long) +#define VPU_IOC_GET_HW_FUSE_STATUS _IOW(VPU_IOC_MAGIC, 2, unsigned long) +#define VPU_IOC_SET_REG _IOW(VPU_IOC_MAGIC, 3, unsigned long) +#define VPU_IOC_GET_REG _IOW(VPU_IOC_MAGIC, 4, unsigned long) + +#define VPU_IOC_SET_CLIENT_TYPE_U32 _IOW(VPU_IOC_MAGIC, 1, unsigned int) + +#define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size)) + +#define VDPU1_REGISTERS (101) +#define VDPU2_REGISTERS (159) +#define VDPU1_PP_REGISTERS (164) +#define VDPU2_PP_REGISTERS (184) +#define RKHEVC_REGISTERS (68) +#define RKVDEC_REGISTERS (78) +#define AVSD_REGISTERS (60) + +#define VEPU1_REGISTERS (164) +#define VEPU2_REGISTERS (184) +#define RKVENC_REGISTERS (140) + +#define EXTRA_INFO_SIZE (sizeof(RK_U32) * 34) + +#ifdef __cplusplus +extern "C" { +#endif + +const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding); + +#ifdef __cplusplus +} +#endif + +#endif /* __VCODEC_SERVICE_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/vcodec_service_api.h b/hardware/mpp/include/vcodec_service_api.h new file mode 100644 index 0000000000000000000000000000000000000000..1bff2cf1020c80f6dd0842d4c05e2f61c9759293 --- /dev/null +++ b/hardware/mpp/include/vcodec_service_api.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VCODEC_SERVICE_API_H__ +#define __VCODEC_SERVICE_API_H__ + +#include "mpp_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern const MppDevApi vcodec_service_api; + +#ifdef __cplusplus +} +#endif + +#endif /* __VCODEC_SERVICE_API_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/vpu.h b/hardware/mpp/include/vpu.h new file mode 100644 index 0000000000000000000000000000000000000000..8c2ea49e8199624275433fb56c1dfc7ff1fdcd44 --- /dev/null +++ b/hardware/mpp/include/vpu.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VPU_H__ +#define __VPU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rk_type.h" + +#define VPU_SUCCESS (0) +#define VPU_FAILURE (-1) + +#define VPU_HW_WAIT_OK VPU_SUCCESS +#define VPU_HW_WAIT_ERROR VPU_FAILURE +#define VPU_HW_WAIT_TIMEOUT 1 + +// vpu decoder 60 registers, size 240B +#define VPU_REG_NUM_DEC (60) +// vpu post processor 41 registers, size 164B +#define VPU_REG_NUM_PP (41) +// vpu decoder + post processor 101 registers, size 404B +#define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC+VPU_REG_NUM_PP) +// vpu encoder 96 registers, size 384B +#define VPU_REG_NUM_ENC (96) + +typedef enum { + VPU_ENC = 0x0, + VPU_DEC = 0x1, + VPU_PP = 0x2, + VPU_DEC_PP = 0x3, + VPU_DEC_HEVC = 0x4, + VPU_DEC_RKV = 0x5, + VPU_ENC_RKV = 0x6, + VPU_DEC_AVS = 0x7, + VPU_ENC_VEPU22 = 0x8, + VPU_TYPE_BUTT, +} VPU_CLIENT_TYPE; + +/* Hardware decoder configuration description */ + +typedef struct VPUHwDecConfig { + RK_U32 maxDecPicWidth; /* Maximum video decoding width supported */ + RK_U32 maxPpOutPicWidth; /* Maximum output width of Post-Processor */ + RK_U32 h264Support; /* HW supports h.264 */ + RK_U32 jpegSupport; /* HW supports JPEG */ + RK_U32 mpeg4Support; /* HW supports MPEG-4 */ + RK_U32 customMpeg4Support; /* HW supports custom MPEG-4 features */ + RK_U32 vc1Support; /* HW supports VC-1 Simple */ + RK_U32 mpeg2Support; /* HW supports MPEG-2 */ + RK_U32 ppSupport; /* HW supports post-processor */ + RK_U32 ppConfig; /* HW post-processor functions bitmask */ + RK_U32 sorensonSparkSupport; /* HW supports Sorenson Spark */ + RK_U32 refBufSupport; /* HW supports reference picture buffering */ + RK_U32 vp6Support; /* HW supports VP6 */ + RK_U32 vp7Support; /* HW supports VP7 */ + RK_U32 vp8Support; /* HW supports VP8 */ + RK_U32 avsSupport; /* HW supports AVS */ + RK_U32 jpegESupport; /* HW supports JPEG extensions */ + RK_U32 rvSupport; /* HW supports REAL */ + RK_U32 mvcSupport; /* HW supports H264 MVC extension */ +} VPUHwDecConfig_t; + +/* Hardware encoder configuration description */ + +typedef struct VPUHwEndConfig { + RK_U32 maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */ + RK_U32 h264Enabled; /* HW supports H.264 */ + RK_U32 jpegEnabled; /* HW supports JPEG */ + RK_U32 mpeg4Enabled; /* HW supports MPEG-4 */ + RK_U32 vsEnabled; /* HW supports video stabilization */ + RK_U32 rgbEnabled; /* HW supports RGB input */ + RK_U32 reg_size; /* HW bus type in use */ + RK_U32 reserv[2]; +} VPUHwEncConfig_t; + +typedef enum { + // common command + VPU_CMD_REGISTER, + VPU_CMD_REGISTER_ACK_OK, + VPU_CMD_REGISTER_ACK_FAIL, + VPU_CMD_UNREGISTER, + + VPU_SEND_CONFIG, + VPU_SEND_CONFIG_ACK_OK, + VPU_SEND_CONFIG_ACK_FAIL, + + VPU_GET_HW_INFO, + VPU_GET_HW_INFO_ACK_OK, + VPU_GET_HW_INFO_ACK_FAIL, + + VPU_CMD_BUTT, +} VPU_CMD_TYPE; + +int VPUClientInit(VPU_CLIENT_TYPE type); +RK_S32 VPUClientRelease(int socket); +RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs); +RK_S32 VPUClientSendReg2(RK_S32 socket, RK_S32 offset, RK_S32 size, void *param); +RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len); +RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size); +RK_S32 VPUClientGetIOMMUStatus(void); +RK_U32 VPUCheckSupportWidth(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __VPU_H__ */ \ No newline at end of file diff --git a/hardware/mpp/include/vpu_api.h b/hardware/mpp/include/vpu_api.h new file mode 100644 index 0000000000000000000000000000000000000000..cf0f76d80c33ffe801c4e1280b66e50ca793eaed --- /dev/null +++ b/hardware/mpp/include/vpu_api.h @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VPU_API_H__ +#define __VPU_API_H__ + +#include "rk_type.h" + +/** + * @brief rockchip media process interface + */ + +#define VPU_API_NOPTS_VALUE (0x8000000000000000LL) + +/* + * bit definition of ColorType in structure VPU_FRAME + */ +#define VPU_OUTPUT_FORMAT_TYPE_MASK (0x0000ffff) +#define VPU_OUTPUT_FORMAT_ARGB8888 (0x00000000) +#define VPU_OUTPUT_FORMAT_ABGR8888 (0x00000001) +#define VPU_OUTPUT_FORMAT_RGB888 (0x00000002) +#define VPU_OUTPUT_FORMAT_RGB565 (0x00000003) +#define VPU_OUTPUT_FORMAT_RGB555 (0x00000004) +#define VPU_OUTPUT_FORMAT_YUV420_SEMIPLANAR (0x00000005) +#define VPU_OUTPUT_FORMAT_YUV420_PLANAR (0x00000006) +#define VPU_OUTPUT_FORMAT_YUV422 (0x00000007) +#define VPU_OUTPUT_FORMAT_YUV444 (0x00000008) +#define VPU_OUTPUT_FORMAT_YCH420 (0x00000009) +#define VPU_OUTPUT_FORMAT_BIT_MASK (0x000f0000) +#define VPU_OUTPUT_FORMAT_BIT_8 (0x00000000) +#define VPU_OUTPUT_FORMAT_BIT_10 (0x00010000) +#define VPU_OUTPUT_FORMAT_BIT_12 (0x00020000) +#define VPU_OUTPUT_FORMAT_BIT_14 (0x00030000) +#define VPU_OUTPUT_FORMAT_BIT_16 (0x00040000) +#define VPU_OUTPUT_FORMAT_COLORSPACE_MASK (0x00f00000) +#define VPU_OUTPUT_FORMAT_COLORSPACE_BT709 (0x00100000) +#define VPU_OUTPUT_FORMAT_COLORSPACE_BT2020 (0x00200000) +#define VPU_OUTPUT_FORMAT_DYNCRANGE_MASK (0x0f000000) +#define VPU_OUTPUT_FORMAT_DYNCRANGE_SDR (0x00000000) +#define VPU_OUTPUT_FORMAT_DYNCRANGE_HDR10 (0x01000000) +#define VPU_OUTPUT_FORMAT_DYNCRANGE_HDR_HLG (0x02000000) +#define VPU_OUTPUT_FORMAT_DYNCRANGE_HDR_DOLBY (0x03000000) + +/** + * @brief input picture type + */ +typedef enum { + ENC_INPUT_YUV420_PLANAR = 0, /**< YYYY... UUUU... VVVV */ + ENC_INPUT_YUV420_SEMIPLANAR = 1, /**< YYYY... UVUVUV... */ + ENC_INPUT_YUV422_INTERLEAVED_YUYV = 2, /**< YUYVYUYV... */ + ENC_INPUT_YUV422_INTERLEAVED_UYVY = 3, /**< UYVYUYVY... */ + ENC_INPUT_RGB565 = 4, /**< 16-bit RGB */ + ENC_INPUT_BGR565 = 5, /**< 16-bit RGB */ + ENC_INPUT_RGB555 = 6, /**< 15-bit RGB */ + ENC_INPUT_BGR555 = 7, /**< 15-bit RGB */ + ENC_INPUT_RGB444 = 8, /**< 12-bit RGB */ + ENC_INPUT_BGR444 = 9, /**< 12-bit RGB */ + ENC_INPUT_RGB888 = 10, /**< 24-bit RGB */ + ENC_INPUT_BGR888 = 11, /**< 24-bit RGB */ + ENC_INPUT_RGB101010 = 12, /**< 30-bit RGB */ + ENC_INPUT_BGR101010 = 13 /**< 30-bit RGB */ +} EncInputPictureType; + +typedef enum VPU_API_CMD { + VPU_API_ENC_SETCFG, + VPU_API_ENC_GETCFG, + VPU_API_ENC_SETFORMAT, + VPU_API_ENC_SETIDRFRAME, + + VPU_API_ENABLE_DEINTERLACE, + VPU_API_SET_VPUMEM_CONTEXT, + VPU_API_USE_PRESENT_TIME_ORDER, + VPU_API_SET_DEFAULT_WIDTH_HEIGH, + VPU_API_SET_INFO_CHANGE, + VPU_API_USE_FAST_MODE, + VPU_API_DEC_GET_STREAM_COUNT, + VPU_API_GET_VPUMEM_USED_COUNT, + VPU_API_GET_FRAME_INFO, + VPU_API_SET_OUTPUT_BLOCK, + VPU_API_GET_EOS_STATUS, + VPU_API_SET_OUTPUT_MODE, + + /* get sps/pps header */ + VPU_API_GET_EXTRA_INFO = 0x200, + + VPU_API_SET_IMMEDIATE_OUT = 0x1000, + VPU_API_SET_PARSER_SPLIT_MODE, /* NOTE: should control before init */ + + VPU_API_ENC_VEPU22_START = 0x2000, + VPU_API_ENC_SET_VEPU22_CFG, + VPU_API_ENC_GET_VEPU22_CFG, + VPU_API_ENC_SET_VEPU22_CTU_QP, + VPU_API_ENC_SET_VEPU22_ROI, + + /* mlvec dynamic configure */ + VPU_API_ENC_MLVEC_CFG = 0x4000, + VPU_API_ENC_SET_MAX_TID, + VPU_API_ENC_SET_MARK_LTR, + VPU_API_ENC_SET_USE_LTR, + VPU_API_ENC_SET_FRAME_QP, + VPU_API_ENC_SET_BASE_LAYER_PID, +} VPU_API_CMD; + +typedef struct { + RK_U32 TimeLow; + RK_U32 TimeHigh; +} TIME_STAMP; + +typedef struct { + RK_U32 CodecType; + RK_U32 ImgWidth; + RK_U32 ImgHeight; + RK_U32 ImgHorStride; + RK_U32 ImgVerStride; + RK_U32 BufSize; +} VPU_GENERIC; + +typedef struct VPUMem { + RK_U32 phy_addr; + RK_U32 *vir_addr; + RK_U32 size; + RK_U32 *offset; +} VPUMemLinear_t; + +typedef struct tVPU_FRAME { + RK_U32 FrameBusAddr[2]; // 0: Y address; 1: UV address; + RK_U32 FrameWidth; // buffer horizontal stride + RK_U32 FrameHeight; // buffer vertical stride + RK_U32 OutputWidth; // deprecated + RK_U32 OutputHeight; // deprecated + RK_U32 DisplayWidth; // valid width for display + RK_U32 DisplayHeight; // valid height for display + RK_U32 CodingType; + RK_U32 FrameType; // frame; top_field_first; bot_field_first + RK_U32 ColorType; + RK_U32 DecodeFrmNum; + TIME_STAMP ShowTime; + RK_U32 ErrorInfo; // error information + RK_U32 employ_cnt; + VPUMemLinear_t vpumem; + struct tVPU_FRAME *next_frame; + union { + struct { + RK_U32 Res0[2]; + struct { + RK_U32 ColorPrimaries : 8; + RK_U32 ColorTransfer : 8; + RK_U32 ColorCoeffs : 8; + RK_U32 ColorRange : 1; + RK_U32 Res1 : 7; + }; + + RK_U32 Res2; + }; + + RK_U32 Res[4]; + }; +} VPU_FRAME; + +typedef struct VideoPacket { + RK_S64 pts; /* with unit of us */ + RK_S64 dts; /* with unit of us */ + RK_U8 *data; + RK_S32 size; + RK_U32 capability; + RK_U32 nFlags; +} VideoPacket_t; + +typedef struct DecoderOut { + RK_U8 *data; + RK_U32 size; + RK_S64 timeUs; + RK_S32 nFlags; +} DecoderOut_t; + +typedef struct ParserOut { + RK_U8 *data; + RK_U32 size; + RK_S64 timeUs; + RK_U32 nFlags; + RK_U32 width; + RK_U32 height; +} ParserOut_t; + +typedef struct EncInputStream { + RK_U8 *buf; + RK_S32 size; + RK_U32 bufPhyAddr; + RK_S64 timeUs; + RK_U32 nFlags; +} EncInputStream_t; + +typedef struct EncoderOut { + RK_U8 *data; + RK_S32 size; + RK_S64 timeUs; + RK_S32 keyFrame; +} EncoderOut_t; + +/* + * @brief Enumeration used to define the possible video compression codings. + * @note This essentially refers to file extensions. If the coding is + * being used to specify the ENCODE type, then additional work + * must be done to configure the exact flavor of the compression + * to be used. For decode cases where the user application can + * not differentiate between MPEG-4 and H.264 bit streams, it is + * up to the codec to handle this. + * + * sync with the omx_video.h + */ +typedef enum OMX_RK_VIDEO_CODINGTYPE { + OMX_RK_VIDEO_CodingUnused, /**< Value when coding is N/A */ + OMX_RK_VIDEO_CodingAutoDetect, /**< Autodetection of coding type */ + OMX_RK_VIDEO_CodingMPEG2, /**< AKA: H.262 */ + OMX_RK_VIDEO_CodingH263, /**< H.263 */ + OMX_RK_VIDEO_CodingMPEG4, /**< MPEG-4 */ + OMX_RK_VIDEO_CodingWMV, /**< Windows Media Video (WMV1,WMV2,WMV3)*/ + OMX_RK_VIDEO_CodingRV, /**< all versions of Real Video */ + OMX_RK_VIDEO_CodingAVC, /**< H.264/AVC */ + OMX_RK_VIDEO_CodingMJPEG, /**< Motion JPEG */ + OMX_RK_VIDEO_CodingVP8, /**< VP8 */ + OMX_RK_VIDEO_CodingVP9, /**< VP9 */ + OMX_RK_VIDEO_CodingVC1 = 0x01000000, /**< Windows Media Video (WMV1,WMV2,WMV3)*/ + OMX_RK_VIDEO_CodingFLV1, /**< Sorenson H.263 */ + OMX_RK_VIDEO_CodingDIVX3, /**< DIVX3 */ + OMX_RK_VIDEO_CodingVP6, + OMX_RK_VIDEO_CodingHEVC, /**< H.265/HEVC */ + OMX_RK_VIDEO_CodingAVS, /**< AVS+ */ + OMX_RK_VIDEO_CodingKhronosExtensions = 0x6F000000, /**< Reserved region for introducing Khronos Standard Extensions */ + OMX_RK_VIDEO_CodingVendorStartUnused = 0x7F000000, /**< Reserved region for introducing Vendor Extensions */ + OMX_RK_VIDEO_CodingMax = 0x7FFFFFFF +} OMX_RK_VIDEO_CODINGTYPE; + +typedef enum CODEC_TYPE { + CODEC_NONE, + CODEC_DECODER, + CODEC_ENCODER, + CODEC_BUTT, +} CODEC_TYPE; + +typedef enum VPU_API_ERR { + VPU_API_OK = 0, + VPU_API_ERR_UNKNOW = -1, + VPU_API_ERR_BASE = -1000, + VPU_API_ERR_LIST_STREAM = VPU_API_ERR_BASE - 1, + VPU_API_ERR_INIT = VPU_API_ERR_BASE - 2, + VPU_API_ERR_VPU_CODEC_INIT = VPU_API_ERR_BASE - 3, + VPU_API_ERR_STREAM = VPU_API_ERR_BASE - 4, + VPU_API_ERR_FATAL_THREAD = VPU_API_ERR_BASE - 5, + VPU_API_EOS_STREAM_REACHED = VPU_API_ERR_BASE - 11, + + VPU_API_ERR_BUTT, +} VPU_API_ERR; + +typedef enum VPU_FRAME_ERR { + VPU_FRAME_ERR_UNKNOW = 0x0001, + VPU_FRAME_ERR_UNSUPPORT = 0x0002, +} VPU_FRAME_ERR; + +typedef struct EncParameter { + RK_S32 width; + RK_S32 height; + RK_S32 rc_mode; /* 0 - CQP mode; 1 - CBR mode; 2 - FIXQP mode */ + RK_S32 bitRate; /* target bitrate */ + RK_S32 framerate; + RK_S32 qp; + RK_S32 enableCabac; + RK_S32 cabacInitIdc; + RK_S32 format; + RK_S32 intraPicRate; + RK_S32 framerateout; + RK_S32 profileIdc; + RK_S32 levelIdc; + RK_S32 reserved[3]; +} EncParameter_t; + +typedef struct EXtraCfg { + RK_S32 vc1extra_size; + RK_S32 vp6codeid; + RK_S32 tsformat; + RK_U32 ori_vpu; /* use origin vpu framework */ + /* below used in decode */ + RK_U32 mpp_mode; /* use mpp framework */ + RK_U32 bit_depth; /* 8 or 10 bit */ + RK_U32 yuv_format; /* 0:420 1:422 2:444 */ + RK_U32 reserved[16]; +} EXtraCfg_t; + +/** + * @brief vpu function interface + */ +typedef struct VpuCodecContext { + void* vpuApiObj; + + CODEC_TYPE codecType; + OMX_RK_VIDEO_CODINGTYPE videoCoding; + + RK_U32 width; + RK_U32 height; + void *extradata; + RK_S32 extradata_size; + + RK_U8 enableparsing; + + RK_S32 no_thread; + EXtraCfg_t extra_cfg; + + void* private_data; + + /* + ** 1: error state(not working) 0: working + */ + RK_S32 decoder_err; + + /** + * Allocate and initialize an VpuCodecContext. + * + * @param ctx The context of vpu api, allocated in this function. + * @param extraData The extra data of codec, some codecs need / can + * use extradata like Huffman tables, also live VC1 codec can + * use extradata to initialize itself. + * @param extra_size The size of extra data. + * + * @return 0 for init success, others for failure. + * @note check whether ctx has been allocated success after you do init. + */ + RK_S32 (*init)(struct VpuCodecContext *ctx, RK_U8 *extraData, RK_U32 extra_size); + /** + * @brief both send video stream packet to decoder and get video frame from + * decoder at the same time + * @param ctx The context of vpu codec + * @param pkt[in] Stream to be decoded + * @param aDecOut[out] Decoding frame + * @return 0 for decode success, others for failure. + */ + RK_S32 (*decode)(struct VpuCodecContext *ctx, VideoPacket_t *pkt, DecoderOut_t *aDecOut); + /** + * @brief both send video frame to encoder and get encoded video stream from + * encoder at the same time. + * @param ctx The context of vpu codec + * @param aEncInStrm[in] Frame to be encoded + * @param aEncOut[out] Encoding stream + * @return 0 for encode success, others for failure. + */ + RK_S32 (*encode)(struct VpuCodecContext *ctx, EncInputStream_t *aEncInStrm, EncoderOut_t *aEncOut); + /** + * @brief flush codec while do fast forward playing. + * @param ctx The context of vpu codec + * @return 0 for flush success, others for failure. + */ + RK_S32 (*flush)(struct VpuCodecContext *ctx); + RK_S32 (*control)(struct VpuCodecContext *ctx, VPU_API_CMD cmdType, void* param); + /** + * @brief send video stream packet to decoder only, async interface + * @param ctx The context of vpu codec + * @param pkt Stream to be decoded + * @return 0 for success, others for failure. + */ + RK_S32 (*decode_sendstream)(struct VpuCodecContext *ctx, VideoPacket_t *pkt); + /** + * @brief get video frame from decoder only, async interface + * @param ctx The context of vpu codec + * @param aDecOut Decoding frame + * @return 0 for success, others for failure. + */ + RK_S32 (*decode_getframe)(struct VpuCodecContext *ctx, DecoderOut_t *aDecOut); + /** + * @brief send video frame to encoder only, async interface + * @param ctx The context of vpu codec + * @param aEncInStrm Frame to be encoded + * @return 0 for success, others for failure. + */ + RK_S32 (*encoder_sendframe)(struct VpuCodecContext *ctx, EncInputStream_t *aEncInStrm); + /** + * @brief get encoded video packet from encoder only, async interface + * @param ctx The context of vpu codec + * @param aEncOut Encoding stream + * @return 0 for success, others for failure. + */ + RK_S32 (*encoder_getstream)(struct VpuCodecContext *ctx, EncoderOut_t *aEncOut); +} VpuCodecContext_t; + +/* allocated vpu codec context */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief open context of vpu + * @param ctx pointer of vpu codec context + */ +RK_S32 vpu_open_context(struct VpuCodecContext **ctx); +/** + * @brief close context of vpu + * @param ctx pointer of vpu codec context + */ +RK_S32 vpu_close_context(struct VpuCodecContext **ctx); + +#ifdef __cplusplus +} +#endif + +/* + * vpu_mem api + */ +#define vpu_display_mem_pool_FIELDS \ + RK_S32 (*commit_hdl)(vpu_display_mem_pool *p, RK_S32 hdl, RK_S32 size); \ + void* (*get_free)(vpu_display_mem_pool *p); \ + RK_S32 (*inc_used)(vpu_display_mem_pool *p, void *hdl); \ + RK_S32 (*put_used)(vpu_display_mem_pool *p, void *hdl); \ + RK_S32 (*reset)(vpu_display_mem_pool *p); \ + RK_S32 (*get_unused_num)(vpu_display_mem_pool *p); \ + RK_S32 buff_size; \ + float version; \ + RK_S32 res[18]; + +typedef struct vpu_display_mem_pool vpu_display_mem_pool; + +struct vpu_display_mem_pool { + vpu_display_mem_pool_FIELDS +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* + * vpu memory handle interface + */ +RK_S32 VPUMemJudgeIommu(void); +RK_S32 VPUMallocLinear(VPUMemLinear_t *p, RK_U32 size); +RK_S32 VPUFreeLinear(VPUMemLinear_t *p); +RK_S32 VPUMemDuplicate(VPUMemLinear_t *dst, VPUMemLinear_t *src); +RK_S32 VPUMemLink(VPUMemLinear_t *p); +RK_S32 VPUMemFlush(VPUMemLinear_t *p); +RK_S32 VPUMemClean(VPUMemLinear_t *p); +RK_S32 VPUMemInvalidate(VPUMemLinear_t *p); +RK_S32 VPUMemGetFD(VPUMemLinear_t *p); +RK_S32 VPUMallocLinearFromRender(VPUMemLinear_t *p, RK_U32 size, void *ctx); + +/* + * vpu memory allocator and manager interface + */ +vpu_display_mem_pool* open_vpu_memory_pool(void); +void close_vpu_memory_pool(vpu_display_mem_pool *p); +int create_vpu_memory_pool_allocator(vpu_display_mem_pool **ipool, int num, int size); +void release_vpu_memory_pool_allocator(vpu_display_mem_pool *ipool); + +#ifdef __cplusplus +} +#endif + +#endif /* __VPU_API_H__ */ diff --git a/hardware/mpp/lib/librockchip_mpp.z.so b/hardware/mpp/lib/librockchip_mpp.z.so new file mode 100755 index 0000000000000000000000000000000000000000..d9a331ed071b9d12d3deedc6498d44e4295ab389 Binary files /dev/null and b/hardware/mpp/lib/librockchip_mpp.z.so differ diff --git a/hardware/mpp/lib64/librockchip_mpp.so b/hardware/mpp/lib64/librockchip_mpp.so new file mode 100644 index 0000000000000000000000000000000000000000..97ba171d4c725c36ce692077e8c93645ab3f592e Binary files /dev/null and b/hardware/mpp/lib64/librockchip_mpp.so differ diff --git a/hardware/mpp/src/mpi_enc_utils.c b/hardware/mpp/src/mpi_enc_utils.c new file mode 100644 index 0000000000000000000000000000000000000000..e8c4643e963558abae6779542cb32bef25de5c7d --- /dev/null +++ b/hardware/mpp/src/mpi_enc_utils.c @@ -0,0 +1,900 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define MODULE_TAG "mpi_enc_utils" + +#include +#include "securec.h" +#include "mpp_mem.h" +#include "mpp_log.h" +#include "mpp_buffer.h" +#include "rk_mpi.h" +#include "mpp_common.h" +#include "mpi_enc_utils.h" + +static MPP_RET mpi_enc_gen_ref_cfg(MppEncRefCfg ref, RK_S32 gop_mode) +{ + MppEncRefLtFrmCfg lt_ref[4]; + MppEncRefStFrmCfg st_ref[16]; + RK_S32 lt_cnt = 0; + RK_S32 st_cnt = 0; + MPP_RET ret = 0; + + errno_t eok = memset_s(<_ref, sizeof(lt_ref), 0, sizeof(lt_ref)); + if (eok != EOK) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + eok = memset_s(&st_ref, sizeof(st_ref), 0, sizeof(st_ref)); + if (eok != EOK) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + + switch (gop_mode) { + case 3 : { + // tsvc4 + // /-> P1 /-> P3 /-> P5 /-> P7 + // / / / / + // //--------> P2 //--------> P6 + // // // + // ///---------------------> P4 + // /// + // P0 ------------------------------------------------> P8 + lt_cnt = 1; + + /* set 8 frame lt-ref gap */ + lt_ref[0].lt_idx = 0; + lt_ref[0].temporal_id = 0; + lt_ref[0].ref_mode = REF_TO_PREV_LT_REF; + lt_ref[0].lt_gap = 8; // 8:set 8 frame + lt_ref[0].lt_delay = 0; + + st_cnt = 9; + /* set tsvc4 st-ref struct */ + /* st 0 layer 0 - ref */ + st_ref[0].is_non_ref = 0; + st_ref[0].temporal_id = 0; + st_ref[0].ref_mode = REF_TO_TEMPORAL_LAYER; + st_ref[0].ref_arg = 0; + st_ref[0].repeat = 0; + /* st 1 layer 3 - non-ref */ + st_ref[1].is_non_ref = 1; + st_ref[1].temporal_id = 3; + st_ref[1].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[1].ref_arg = 0; + st_ref[1].repeat = 0; + /* st 2 layer 2 - ref */ + st_ref[2].is_non_ref = 0; + st_ref[2].temporal_id = 2; + st_ref[2].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[2].ref_arg = 0; + st_ref[2].repeat = 0; + /* st 3 layer 3 - non-ref */ + st_ref[3].is_non_ref = 1; + st_ref[3].temporal_id = 3; + st_ref[3].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[3].ref_arg = 0; + st_ref[3].repeat = 0; + /* st 4 layer 1 - ref */ + st_ref[4].is_non_ref = 0; + st_ref[4].temporal_id = 1; + st_ref[4].ref_mode = REF_TO_PREV_LT_REF; + st_ref[4].ref_arg = 0; + st_ref[4].repeat = 0; + /* st 5 layer 3 - non-ref */ + st_ref[5].is_non_ref = 1; + st_ref[5].temporal_id = 3; + st_ref[5].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[5].ref_arg = 0; + st_ref[5].repeat = 0; + /* st 6 layer 2 - ref */ + st_ref[6].is_non_ref = 0; + st_ref[6].temporal_id = 2; + st_ref[6].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[6].ref_arg = 0; + st_ref[6].repeat = 0; + /* st 7 layer 3 - non-ref */ + st_ref[7].is_non_ref = 1; + st_ref[7].temporal_id = 3; + st_ref[7].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[7].ref_arg = 0; + st_ref[7].repeat = 0; + /* st 8 layer 0 - ref */ + st_ref[8].is_non_ref = 0; + st_ref[8].temporal_id = 0; + st_ref[8].ref_mode = REF_TO_TEMPORAL_LAYER; + st_ref[8].ref_arg = 0; + st_ref[8].repeat = 0; + } + break; + case 2 : { + // tsvc3 + // /-> P1 /-> P3 + // / / + // //--------> P2 + // // + // P0/---------------------> P4 + lt_cnt = 0; + + st_cnt = 5; + /* set tsvc4 st-ref struct */ + /* st 0 layer 0 - ref */ + st_ref[0].is_non_ref = 0; + st_ref[0].temporal_id = 0; + st_ref[0].ref_mode = REF_TO_TEMPORAL_LAYER; + st_ref[0].ref_arg = 0; + st_ref[0].repeat = 0; + /* st 1 layer 2 - non-ref */ + st_ref[1].is_non_ref = 1; + st_ref[1].temporal_id = 2; + st_ref[1].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[1].ref_arg = 0; + st_ref[1].repeat = 0; + /* st 2 layer 1 - ref */ + st_ref[2].is_non_ref = 0; + st_ref[2].temporal_id = 1; + st_ref[2].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[2].ref_arg = 0; + st_ref[2].repeat = 0; + /* st 3 layer 2 - non-ref */ + st_ref[3].is_non_ref = 1; + st_ref[3].temporal_id = 2; + st_ref[3].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[3].ref_arg = 0; + st_ref[3].repeat = 0; + /* st 4 layer 0 - ref */ + st_ref[4].is_non_ref = 0; + st_ref[4].temporal_id = 0; + st_ref[4].ref_mode = REF_TO_TEMPORAL_LAYER; + st_ref[4].ref_arg = 0; + st_ref[4].repeat = 0; + } + break; + case 1 : { + // tsvc2 + // /-> P1 + // / + // P0--------> P2 + lt_cnt = 0; + + st_cnt = 3; + /* set tsvc4 st-ref struct */ + /* st 0 layer 0 - ref */ + st_ref[0].is_non_ref = 0; + st_ref[0].temporal_id = 0; + st_ref[0].ref_mode = REF_TO_TEMPORAL_LAYER; + st_ref[0].ref_arg = 0; + st_ref[0].repeat = 0; + /* st 1 layer 2 - non-ref */ + st_ref[1].is_non_ref = 1; + st_ref[1].temporal_id = 1; + st_ref[1].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[1].ref_arg = 0; + st_ref[1].repeat = 0; + /* st 2 layer 1 - ref */ + st_ref[2].is_non_ref = 0; + st_ref[2].temporal_id = 0; + st_ref[2].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[2].ref_arg = 0; + st_ref[2].repeat = 0; + } + break; + default : { + mpp_err_f("unsupport gop mode %d\n", gop_mode); + } + break; + } + + if (lt_cnt || st_cnt) { + ret = mpp_enc_ref_cfg_set_cfg_cnt(ref, lt_cnt, st_cnt); + + if (lt_cnt) + ret = mpp_enc_ref_cfg_add_lt_cfg(ref, lt_cnt, lt_ref); + + if (st_cnt) + ret = mpp_enc_ref_cfg_add_st_cfg(ref, st_cnt, st_ref); + + /* check and get dpb size */ + ret = mpp_enc_ref_cfg_check(ref); + } + + return ret; +} + +static MPP_RET mpi_enc_gen_smart_gop_ref_cfg(MppEncRefCfg ref, RK_S32 gop_len, RK_S32 vi_len) +{ + MppEncRefLtFrmCfg lt_ref[4]; + MppEncRefStFrmCfg st_ref[16]; + RK_S32 lt_cnt = 1; + RK_S32 st_cnt = 8; + RK_S32 pos = 0; + MPP_RET ret = 0; + + errno_t eok = memset_s(<_ref, sizeof(lt_ref), 0, sizeof(lt_ref)); + if (eok != EOK) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + eok = memset_s(&st_ref, sizeof(st_ref), 0, sizeof(st_ref)); + if (eok != EOK) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + + ret = mpp_enc_ref_cfg_set_cfg_cnt(ref, lt_cnt, st_cnt); + + /* set 8 frame lt-ref gap */ + lt_ref[0].lt_idx = 0; + lt_ref[0].temporal_id = 0; + lt_ref[0].ref_mode = REF_TO_PREV_LT_REF; + lt_ref[0].lt_gap = gop_len; + lt_ref[0].lt_delay = 0; + + mpp_enc_ref_cfg_add_lt_cfg(ref, 1, lt_ref); + + /* st 0 layer 0 - ref */ + st_ref[pos].is_non_ref = 0; + st_ref[pos].temporal_id = 0; + st_ref[pos].ref_mode = REF_TO_PREV_INTRA; + st_ref[pos].ref_arg = 0; + st_ref[pos].repeat = 0; + pos++; + + /* st 1 layer 1 - non-ref */ + if (vi_len > 1) { + st_ref[pos].is_non_ref = 0; + st_ref[pos].temporal_id = 1; + st_ref[pos].ref_mode = REF_TO_PREV_REF_FRM; + st_ref[pos].ref_arg = 0; + st_ref[pos].repeat = vi_len - 2; + pos++; + } + + st_ref[pos].is_non_ref = 0; + st_ref[pos].temporal_id = 0; + st_ref[pos].ref_mode = REF_TO_PREV_INTRA; + st_ref[pos].ref_arg = 0; + st_ref[pos].repeat = 0; + pos++; + + mpp_enc_ref_cfg_add_st_cfg(ref, pos, st_ref); + + /* check and get dpb size */ + ret = mpp_enc_ref_cfg_check(ref); + + return ret; +} + +/* ���˱������õ�һЩ����������ߣ�����ͼ���ʽ����������ʽ�ȣ�����������֪��ֱ����0 + * test_mpp_enc_cfg_setup�������Զ�����Ĭ�ϵIJ�����bps�� gop�Ȳ��� + */ +static MPP_RET test_ctx_init(MpiEncTestData **data, MpiEncTestArgs *cmd) +{ + MpiEncTestData *p = NULL; + MPP_RET ret = 0; + + if (!data || !cmd) { + mpp_err_f("invalid input data %p cmd %p\n", data, cmd); + return MPP_ERR_NULL_PTR; + } + + p = mpp_calloc(MpiEncTestData, 1); + if (!p) { + mpp_err_f("create MpiEncTestData failed\n"); + ret = MPP_ERR_MALLOC; + *data = p; + return ret; + } + + // get paramter from cmd + p->width = cmd->width; + p->height = cmd->height; + p->hor_stride = MPP_ALIGN(cmd->width, 16); // 16:hor_stride + p->ver_stride = MPP_ALIGN(cmd->height, 16); // 16:ver_stride + p->fmt = cmd->format; + p->type = cmd->type; + + // update resource parameter + switch (p->fmt & MPP_FRAME_FMT_MASK) { + case MPP_FMT_YUV420SP: + case MPP_FMT_YUV420P: { + p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 3 / 2; + } + break; + + case MPP_FMT_YUV422_YUYV : + case MPP_FMT_YUV422_YVYU : + case MPP_FMT_YUV422_UYVY : + case MPP_FMT_YUV422_VYUY : + case MPP_FMT_YUV422P : + case MPP_FMT_YUV422SP : + case MPP_FMT_RGB444 : + case MPP_FMT_BGR444 : + case MPP_FMT_RGB555 : + case MPP_FMT_BGR555 : + case MPP_FMT_RGB565 : + case MPP_FMT_BGR565 : { + p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2; + } + break; + default: { + p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 4; + } + break; + } + *data = p; + return ret; +} + +static MPP_RET test_ctx_deinit(MpiEncTestData **data) +{ + MpiEncTestData *p = NULL; + + if (!data) { + mpp_err_f("invalid input data %p\n", data); + return MPP_ERR_NULL_PTR; + } + p = *data; + if (p) { + MPP_FREE(p); + *data = NULL; + } + return MPP_OK; +} + +static MPP_RET test_mpp_enc_cfg_setup(MpiEncTestData *p) +{ + MPP_RET ret; + MppApi *mpi; + MppCtx ctx; + MppEncCfg cfg; + + if (p == NULL) + return MPP_ERR_NULL_PTR; + + mpi = p->mpi; + ctx = p->ctx; + cfg = p->cfg; + + /* setup default parameter */ + if (p->fps_in_den == 0) + p->fps_in_den = 1; + if (p->fps_in_num == 0) + p->fps_in_num = 30; + if (p->fps_out_den == 0) + p->fps_out_den = 1; + if (p->fps_out_num == 0) + p->fps_out_num = 30; + + /* ����Ĭ��bps */ + if (!p->bps) + p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den); + + mpp_enc_cfg_set_s32(cfg, "prep:width", p->width); + mpp_enc_cfg_set_s32(cfg, "prep:height", p->height); + mpp_enc_cfg_set_s32(cfg, "prep:hor_stride", p->hor_stride); + mpp_enc_cfg_set_s32(cfg, "prep:ver_stride", p->ver_stride); + mpp_enc_cfg_set_s32(cfg, "prep:format", p->fmt); + + mpp_enc_cfg_set_s32(cfg, "rc:mode", p->rc_mode); + + /* fix input / output frame rate */ + mpp_enc_cfg_set_s32(cfg, "rc:fps_in_flex", p->fps_in_flex); + mpp_enc_cfg_set_s32(cfg, "rc:fps_in_num", p->fps_in_num); + mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denorm", p->fps_in_den); + mpp_enc_cfg_set_s32(cfg, "rc:fps_out_flex", p->fps_out_flex); + mpp_enc_cfg_set_s32(cfg, "rc:fps_out_num", p->fps_out_num); + mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denorm", p->fps_out_den); + mpp_enc_cfg_set_s32(cfg, "rc:gop", p->gop_len ? p->gop_len : p->fps_out_num * 2); + + /* drop frame or not when bitrate overflow */ + mpp_enc_cfg_set_u32(cfg, "rc:drop_mode", MPP_ENC_RC_DROP_FRM_DISABLED); + mpp_enc_cfg_set_u32(cfg, "rc:drop_thd", 20); /* 20% of max bps */ + mpp_enc_cfg_set_u32(cfg, "rc:drop_gap", 1); /* Do not continuous drop frame */ + + /* setup bitrate for different rc_mode */ + mpp_enc_cfg_set_s32(cfg, "rc:bps_target", p->bps); + switch (p->rc_mode) { + case MPP_ENC_RC_MODE_FIXQP : { + /* do not setup bitrate on FIXQP mode */ + } + break; + case MPP_ENC_RC_MODE_CBR : { + /* CBR mode has narrow bound */ + mpp_enc_cfg_set_s32(cfg, "rc:bps_max", p->bps_max ? p->bps_max : p->bps * 17 / 16); + mpp_enc_cfg_set_s32(cfg, "rc:bps_min", p->bps_min ? p->bps_min : p->bps * 15 / 16); + } + break; + case MPP_ENC_RC_MODE_VBR : + case MPP_ENC_RC_MODE_AVBR : { + /* VBR mode has wide bound */ + mpp_enc_cfg_set_s32(cfg, "rc:bps_max", p->bps_max ? p->bps_max : p->bps * 17 / 16); + mpp_enc_cfg_set_s32(cfg, "rc:bps_min", p->bps_min ? p->bps_min : p->bps * 1 / 16); + } + break; + default : { + /* default use CBR mode */ + mpp_enc_cfg_set_s32(cfg, "rc:bps_max", p->bps_max ? p->bps_max : p->bps * 17 / 16); + mpp_enc_cfg_set_s32(cfg, "rc:bps_min", p->bps_min ? p->bps_min : p->bps * 15 / 16); + } + break; + } + + /* setup qp for different codec and rc_mode */ + switch (p->type) { + case MPP_VIDEO_CodingAVC : + case MPP_VIDEO_CodingHEVC : { + switch (p->rc_mode) { + case MPP_ENC_RC_MODE_FIXQP : { + mpp_enc_cfg_set_s32(cfg, "rc:qp_init", 20); // 20:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_max", 20); // 20:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min", 20); // 20:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_max_i", 20); // 20:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min_i", 20); // 20:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_ip", 2); + } + break; + case MPP_ENC_RC_MODE_CBR : + case MPP_ENC_RC_MODE_VBR : + case MPP_ENC_RC_MODE_AVBR : { + mpp_enc_cfg_set_s32(cfg, "rc:qp_init", 26); // 26:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_max", 51); // 51:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min", 10); // 10:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_max_i", 51); // 51:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min_i", 10); // 10:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_ip", 2); + } + break; + default : { + mpp_err_f("unsupport encoder rc mode %d\n", p->rc_mode); + } + break; + } + } + break; + case MPP_VIDEO_CodingVP8 : { + /* vp8 only setup base qp range */ + mpp_enc_cfg_set_s32(cfg, "rc:qp_init", 40); // 40:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_max", 127); // 127:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min", 0); + mpp_enc_cfg_set_s32(cfg, "rc:qp_max_i", 127); // 127:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "rc:qp_min_i", 0); + mpp_enc_cfg_set_s32(cfg, "rc:qp_ip", 6); // 6:mpp cfg value + } + break; + case MPP_VIDEO_CodingMJPEG : { + /* jpeg use special codec config to control qtable */ + mpp_enc_cfg_set_s32(cfg, "jpeg:q_factor", 80); // 80:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "jpeg:qf_max", 99); // 99:mpp cfg value + mpp_enc_cfg_set_s32(cfg, "jpeg:qf_min", 1); + } + break; + default : { + } + break; + } + + /* setup codec */ + mpp_enc_cfg_set_s32(cfg, "codec:type", p->type); + switch (p->type) { + case MPP_VIDEO_CodingAVC : { + /* + * H.264 profile_idc parameter + * 66 - Baseline profile + * 77 - Main profile + * 100 - High profile + */ + mpp_enc_cfg_set_s32(cfg, "h264:profile", 100); + /* + * H.264 level_idc parameter + * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps + * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps + * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps + * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps + * 50 / 51 / 52 - 4K@30fps + */ + mpp_enc_cfg_set_s32(cfg, "h264:level", 40); + mpp_enc_cfg_set_s32(cfg, "h264:cabac_en", 1); + mpp_enc_cfg_set_s32(cfg, "h264:cabac_idc", 0); + mpp_enc_cfg_set_s32(cfg, "h264:trans8x8", 1); + } + break; + case MPP_VIDEO_CodingHEVC : + case MPP_VIDEO_CodingMJPEG : + case MPP_VIDEO_CodingVP8 : { + } + break; + default : { + mpp_err_f("unsupport encoder coding type %d\n", p->type); + } + break; + } + + p->split_mode = 0; + p->split_arg = 0; + + mpp_env_get_u32("split_mode", &p->split_mode, MPP_ENC_SPLIT_NONE); + mpp_env_get_u32("split_arg", &p->split_arg, 0); + + if (p->split_mode) { + mpp_log("%p split_mode %d split_arg %d\n", ctx, p->split_mode, p->split_arg); + mpp_enc_cfg_set_s32(cfg, "split:mode", p->split_mode); + mpp_enc_cfg_set_s32(cfg, "split:arg", p->split_arg); + } + + ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg); + if (ret) { + mpp_err("mpi control enc set cfg failed ret %d\n", ret); + return ret; + } + + /* optional */ + p->sei_mode = MPP_ENC_SEI_MODE_ONE_FRAME; + ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode); + if (ret) { + mpp_err("mpi control enc set sei cfg failed ret %d\n", ret); + return ret; + } + + if (p->type == MPP_VIDEO_CodingAVC || p->type == MPP_VIDEO_CodingHEVC) { + p->header_mode = MPP_ENC_HEADER_MODE_EACH_IDR; + ret = mpi->control(ctx, MPP_ENC_SET_HEADER_MODE, &p->header_mode); + if (ret) { + mpp_err("mpi control enc set header mode failed ret %d\n", ret); + return ret; + } + } + + RK_U32 gop_mode = p->gop_mode; + + mpp_env_get_u32("gop_mode", &gop_mode, gop_mode); + if (gop_mode) { + MppEncRefCfg ref; + + mpp_enc_ref_cfg_init(&ref); + + if (p->gop_mode < 4) { + mpi_enc_gen_ref_cfg(ref, gop_mode); + } else { + mpi_enc_gen_smart_gop_ref_cfg(ref, p->gop_len, p->vi_len); + } + ret = mpi->control(ctx, MPP_ENC_SET_REF_CFG, ref); + if (ret) { + mpp_err("mpi control enc set ref cfg failed ret %d\n", ret); + return ret; + } + mpp_enc_ref_cfg_deinit(&ref); + } + return ret; +} + +static void test_mpp_frame_set_param(MppFrame frame, MpiEncTestData *p) +{ + mpp_frame_set_width(frame, p->width); + mpp_frame_set_height(frame, p->height); + mpp_frame_set_hor_stride(frame, p->hor_stride); + mpp_frame_set_ver_stride(frame, p->ver_stride); + mpp_frame_set_fmt(frame, p->fmt); + mpp_frame_set_eos(frame, p->frm_eos); +} + +static void test_mpp_ctx_cleanup(MpiEncTestData *p) +{ + if (!p) { + mpp_err("test_mpp_ctx_cleanup p == NULL\n"); + return; + } + + if (p->mpi->reset) { + p->mpi->reset(p->ctx); + } + + if (p->ctx) { + mpp_destroy(p->ctx); + p->ctx = NULL; + } + + if (p->cfg) { + mpp_enc_cfg_deinit(p->cfg); + p->cfg = NULL; + } + + if (p->pkt_buf) { + mpp_buffer_put(p->pkt_buf); + p->pkt_buf = NULL; + } + + if (p->buf_grp) { + mpp_buffer_group_put(p->buf_grp); + p->buf_grp = NULL; + } + + test_ctx_deinit(&p); +} + +int hal_mpp_get_sps(void *ctx, unsigned char *buf, size_t *buf_size) +{ + int ret; + MppApi *mpi; + MppCtx mpp_ctx; + MppPacket packet = NULL; + MpiEncTestData *p = (MpiEncTestData *)ctx; + errno_t eok; + + if (!p) { + mpp_err("mpi control enc get extra info failed\n"); + return MPP_NOK; + } + mpi = p->mpi; + mpp_ctx = p->ctx; + + /* + * Can use packet with normal malloc buffer as input not pkt_buf. + * Please refer to vpu_api_legacy.cpp for normal buffer case. + * Using pkt_buf buffer here is just for simplifing demo. + */ + + mpp_packet_init_with_buffer(&packet, p->pkt_buf); + /* NOTE: It is important to clear output packet length!! */ + mpp_packet_set_length(packet, 0); + + // ����һ��H264��H265ר�õ�һЩ���� + if (p->type == MPP_VIDEO_CodingAVC || p->type == MPP_VIDEO_CodingHEVC) { + ret = mpi->control(mpp_ctx, MPP_ENC_GET_HDR_SYNC, packet); + if (ret) { + mpp_err("mpi control enc get extra info failed\n"); + ret = MPP_NOK; + mpp_packet_deinit(&packet); + return ret; + } + } + + void *ptr = mpp_packet_get_pos(packet); + size_t len = mpp_packet_get_length(packet); + if (*buf_size < len) { + mpp_err("mpi buffer size too small\n"); + ret = MPP_NOK; + mpp_packet_deinit(&packet); + return ret; + } + + eok = memcpy_s(buf, len, ptr, len); + if (eok != EOK) { + mpp_err("memcpy_s failed\n"); + return MPP_NOK; + } + + *buf_size = len; + + ret = MPP_OK; + mpp_packet_deinit(&packet); + return ret; +} + +int hal_mpp_encode(void *ctx, int dma_fd, unsigned char *buf, size_t *buf_size) +{ + if (!ctx) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + + MPP_RET ret = 0; + MppFrame frame = NULL; + MppMeta meta = NULL; + MppPacket packet = NULL; + MpiEncTestData *p = (MpiEncTestData *)ctx; + MppApi *mpi = p->mpi; + RK_U32 eoi = 1; + RK_U32 packet_num = 0; + MppBuffer cam_buf = NULL; + MppBufferInfo info; + + errno_t eok = memset_s(&info, sizeof(MppBufferInfo), 0, sizeof(MppBufferInfo)); + if (eok != EOK) { + mpp_err("memset_s failed\n"); + return MPP_NOK; + } + info.type = MPP_BUFFER_TYPE_EXT_DMA; + info.fd = dma_fd; + info.size = p->frame_size & 0x07ffffff; + info.index = (p->frame_size & 0xf8000000) >> 27; + + ret = mpp_buffer_import(&cam_buf, &info); + if (ret != MPP_SUCCESS) { + mpp_err_f("mpp_buffer_import failed\n"); + return MPP_NOK; + } + + ret = mpp_frame_init(&frame); + if (ret) { + mpp_err_f("mpp_frame_init failed\n"); + return MPP_NOK; + } + + /* set frame size info */ + test_mpp_frame_set_param(frame, p); + + /* set frame data include fd */ + mpp_frame_set_buffer(frame, cam_buf); + + /* packet init */ + mpp_packet_init_with_buffer(&packet, p->pkt_buf); + /* NOTE: It is important to clear output packet length!! */ + mpp_packet_set_length(packet, 0); + + meta = mpp_frame_get_meta(frame); + mpp_meta_set_packet(meta, KEY_OUTPUT_PACKET, packet); + + /* + * NOTE: in non-block mode the frame can be resent. + * The default input timeout mode is block. + * + * User should release the input frame to meet the requirements of + * resource creator must be the resource destroyer. + */ + ret = mpi->encode_put_frame(p->ctx, frame); + if (ret) { + mpp_err("mpp encode put frame failed\n"); + mpp_frame_deinit(&frame); + if (cam_buf) { + mpp_buffer_put(cam_buf); + } + mpp_packet_deinit(&packet); + return ret; + } + + mpp_frame_deinit(&frame); + + packet_num = 0; + + do { + ret = mpi->encode_get_packet(p->ctx, &packet); + if (ret) { + mpp_err("mpp encode get packet failed\n"); + if (cam_buf) { + mpp_buffer_put(cam_buf); + } + mpp_packet_deinit(&packet); + return ret; + } + + mpp_assert(packet); + + if (packet) { + /* for low delay partition encoding */ + if (mpp_packet_is_partition(packet)) { + eoi = mpp_packet_is_eoi(packet); + } + + p->frame_count += eoi; + packet_num++; + } + } while (!eoi); + + void *ptr = mpp_packet_get_pos(packet); + size_t len = mpp_packet_get_length(packet); + + if (packet_num != 1) { + mpp_err("packet_num %u != 1\n"); + ret = MPP_NOK; + if (cam_buf) { + mpp_buffer_put(cam_buf); + } + mpp_packet_deinit(&packet); + return ret; + } + + if (*buf_size < len) { + mpp_err("mpi buffer size too small\n"); + ret = MPP_NOK; + if (cam_buf) { + mpp_buffer_put(cam_buf); + } + mpp_packet_deinit(&packet); + return ret; + } + + eok = memcpy_s(buf, len, ptr, len); + if (eok != EOK) { + mpp_err("memcpy_s failed\n"); + return MPP_NOK; + } + + *buf_size = len; + + ret = MPP_OK; + if (cam_buf) + mpp_buffer_put(cam_buf); + + mpp_packet_deinit(&packet); + return ret; +} + +void *hal_mpp_ctx_create(MpiEncTestArgs *args) +{ + MPP_RET ret = 0; + MpiEncTestData *p = NULL; + MppPollType timeout = MPP_POLL_BLOCK; + + /* ��ʼ��һ�³��õIJ������ã�cmd�����ñȽ϶� */ + ret = test_ctx_init(&p, args); + if (ret) { + mpp_err_f("test data init failed ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + ret = mpp_buffer_group_get_internal(&p->buf_grp, MPP_BUFFER_TYPE_DRM); + if (ret) { + mpp_err_f("failed to get mpp buffer group ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + /* pkt_buf�����Ա���?���Ǹ�packetʹ�õ�buffer */ + ret = mpp_buffer_get(p->buf_grp, &p->pkt_buf, p->frame_size); + if (ret) { + mpp_err_f("failed to get buffer for output packet ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + // encoder demo + ret = mpp_create(&p->ctx, &p->mpi); + if (ret) { + mpp_err("mpp_create failed ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + mpp_log("%p mpi_enc_test encoder test start w %d h %d type %d\n", + p->ctx, p->width, p->height, p->type); + + ret = p->mpi->control(p->ctx, MPP_SET_OUTPUT_TIMEOUT, &timeout); + if (MPP_OK != ret) { + mpp_err("mpi control set output timeout %d ret %d\n", timeout, ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + ret = mpp_init(p->ctx, MPP_CTX_ENC, p->type); + if (ret) { + mpp_err("mpp_init failed ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + ret = mpp_enc_cfg_init(&p->cfg); + if (ret) { + mpp_err_f("mpp_enc_cfg_init failed ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + ret = test_mpp_enc_cfg_setup(p); + if (ret) { + mpp_err_f("test mpp setup failed ret %d\n", ret); + mpp_err("%p mpi_enc_test failed ret %d\n", p->ctx, ret); + return NULL; + } + + return p; +} + +void hal_mpp_ctx_delete(void *ctx) +{ + test_mpp_ctx_cleanup(ctx); +} diff --git a/hardware/rga/BUILD.gn b/hardware/rga/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..9a671167fe4b7d98f31e59953b303bda9e3e0827 --- /dev/null +++ b/hardware/rga/BUILD.gn @@ -0,0 +1,27 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import("//build/ohos.gni") +import("//build/ohos/ndk/ndk.gni") + +ohos_prebuilt_shared_library("librga") { + if (target_cpu == "arm") { + source = "lib/librga.z.so" + } else if (target_cpu == "arm64") { + source = "lib64/librga.z.so" + } + install_images = [ chipset_base_dir ] + subsystem_name = "hdf" + part_name = "camera_device_driver" + install_enable = true +} diff --git a/hardware/rga/include/GrallocOps.h b/hardware/rga/include/GrallocOps.h new file mode 100755 index 0000000000000000000000000000000000000000..4c5ca522b0f4d5233bce42af87566c800b66d259 --- /dev/null +++ b/hardware/rga/include/GrallocOps.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _rk_graphic_buffer_h_ +#define _rk_graphic_buffer_h_ +#endif // _rk_graphic_buffer_h_ diff --git a/hardware/rga/include/RgaApi.h b/hardware/rga/include/RgaApi.h new file mode 100755 index 0000000000000000000000000000000000000000..9acb9541a90883b2ef98a9ffefbc7b04cfb8d213 --- /dev/null +++ b/hardware/rga/include/RgaApi.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _rockchip_rga_c_h_ +#define _rockchip_rga_c_h_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "drmrga.h" +#include "rga.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +/* + * Compatible with the old version of C interface.The new + * version of the C interface no longer requires users to + * initialize rga, so RgaInit and RgaDeInit are just for + * compatibility with the old C interface, so please do + * not use ctx, because it is usually a NULL. + */ +#define RgaInit(ctx) ( { \ + int ret = 0; \ + ret = c_RkRgaInit(); \ + c_RkRgaGetContext(ctx); \ + ret; \ +}) +#define RgaDeInit(ctx) { \ + (void)(ctx); /* unused */ \ + c_RkRgaDeInit(); \ +} +#define RgaBlit(...) c_RkRgaBlit(__VA_ARGS__) +#define RgaCollorFill(...) c_RkRgaColorFill(__VA_ARGS__) +#define RgaFlush() c_RkRgaFlush() + +int c_RkRgaInit(void); +void c_RkRgaDeInit(void); +void c_RkRgaGetContext(void **ctx); +int c_RkRgaBlit(rga_info_t *src, rga_info_t *dst, rga_info_t *src1); +int c_RkRgaColorFill(rga_info_t *dst); +int c_RkRgaFlush(void); + +int c_RkRgaGetAllocBuffer(bo_t *bo_info, int width, int height, int bpp); +int c_RkRgaGetAllocBufferCache(bo_t *bo_info, int width, int height, int bpp); +int c_RkRgaGetMmap(bo_t *bo_info); +int c_RkRgaUnmap(bo_t *bo_info); +int c_RkRgaFree(bo_t *bo_info); +int c_RkRgaGetBufferFd(bo_t *bo_info, int *fd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _rockchip_rga_c_h_ */ diff --git a/hardware/rga/include/RgaMutex.h b/hardware/rga/include/RgaMutex.h new file mode 100755 index 0000000000000000000000000000000000000000..092ef94b52ac00f0585eaa86437a42f34a22448c --- /dev/null +++ b/hardware/rga/include/RgaMutex.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + * Authors: + * PutinLee + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _LIBS_RGA_MUTEX_H +#define _LIBS_RGA_MUTEX_H + +#include +#include +#include + +#include + + +// Enable thread safety attributes only with clang. +// The attributes can be safely erased when compiling with other compilers. +#if defined(__clang__) && (!defined(SWIG)) +#define THREAD_ANNOTATION_ATTRIBUTE__(x) __attribute__((x)) +#else +#define THREAD_ANNOTATION_ATTRIBUTE__(x) // no-op +#endif + +#define CAPABILITY(x) THREAD_ANNOTATION_ATTRIBUTE__(capability(x)) + +#define SCOPED_CAPABILITY THREAD_ANNOTATION_ATTRIBUTE__(scoped_lockable) + +#define GUARDED_BY(x) THREAD_ANNOTATION_ATTRIBUTE__(guarded_by(x)) + +#define PT_GUARDED_BY(x) THREAD_ANNOTATION_ATTRIBUTE__(pt_guarded_by(x)) + +#define ACQUIRED_BEFORE(...) THREAD_ANNOTATION_ATTRIBUTE__(acquired_before(__VA_ARGS__)) + +#define ACQUIRED_AFTER(...) THREAD_ANNOTATION_ATTRIBUTE__(acquired_after(__VA_ARGS__)) + +#define REQUIRES(...) THREAD_ANNOTATION_ATTRIBUTE__(requires_capability(__VA_ARGS__)) + +#define REQUIRES_SHARED(...) THREAD_ANNOTATION_ATTRIBUTE__(requires_shared_capability(__VA_ARGS__)) + +#define ACQUIRE(...) THREAD_ANNOTATION_ATTRIBUTE__(acquire_capability(__VA_ARGS__)) + +#define ACQUIRE_SHARED(...) THREAD_ANNOTATION_ATTRIBUTE__(acquire_shared_capability(__VA_ARGS__)) + +#define RELEASE(...) THREAD_ANNOTATION_ATTRIBUTE__(release_capability(__VA_ARGS__)) + +#define RELEASE_SHARED(...) THREAD_ANNOTATION_ATTRIBUTE__(release_shared_capability(__VA_ARGS__)) + +#define TRY_ACQUIRE(...) THREAD_ANNOTATION_ATTRIBUTE__(try_acquire_capability(__VA_ARGS__)) + +#define TRY_ACQUIRE_SHARED(...) \ + THREAD_ANNOTATION_ATTRIBUTE__(try_acquire_shared_capability(__VA_ARGS__)) + +#define EXCLUDES(...) THREAD_ANNOTATION_ATTRIBUTE__(locks_excluded(__VA_ARGS__)) + +#define ASSERT_CAPABILITY(x) THREAD_ANNOTATION_ATTRIBUTE__(assert_capability(x)) + +#define ASSERT_SHARED_CAPABILITY(x) THREAD_ANNOTATION_ATTRIBUTE__(assert_shared_capability(x)) + +#define RETURN_CAPABILITY(x) THREAD_ANNOTATION_ATTRIBUTE__(lock_returned(x)) + +#define NO_THREAD_SAFETY_ANALYSIS THREAD_ANNOTATION_ATTRIBUTE__(no_thread_safety_analysis) + +class Condition; + +/* + * NOTE: This class is for code that builds on Win32. Its usage is + * deprecated for code which doesn't build for Win32. New code which + * doesn't build for Win32 should use std::mutex and std::lock_guard instead. + * + * Simple mutex class. The implementation is system-dependent. + * + * The mutex must be unlocked by the thread that locked it. They are not + * recursive, i.e. the same thread can't lock it multiple times. + */ +class CAPABILITY("mutex") Mutex { + public: + enum { + PRIVATE = 0, + SHARED = 1 + }; + + Mutex(); + explicit Mutex(const char* name); + explicit Mutex(int type, const char* name = nullptr); + ~Mutex(); + + // lock or unlock the mutex + int32_t lock() ACQUIRE(); + void unlock() RELEASE(); + + // lock if possible; returns 0 on success, error otherwise + int32_t tryLock() TRY_ACQUIRE(0); + + int32_t timedLock(int64_t timeoutNs) TRY_ACQUIRE(0); + + // Manages the mutex automatically. It'll be locked when Autolock is + // constructed and released when Autolock goes out of scope. + class SCOPED_CAPABILITY Autolock { + public: + inline explicit Autolock(Mutex& mutex) ACQUIRE(mutex) : mLock(mutex) { + mLock.lock(); + } + inline explicit Autolock(Mutex* mutex) ACQUIRE(mutex) : mLock(*mutex) { + mLock.lock(); + } + inline ~Autolock() RELEASE() { + mLock.unlock(); + } + + private: + Mutex& mLock; + // Cannot be copied or moved - declarations only + Autolock(const Autolock&); + Autolock& operator=(const Autolock&); + }; + + private: + friend class Condition; + + // A mutex cannot be copied + Mutex(const Mutex&); + Mutex& operator=(const Mutex&); + + pthread_mutex_t mMutex; +}; + +// --------------------------------------------------------------------------- +inline Mutex::Mutex() { + pthread_mutex_init(&mMutex, nullptr); +} +inline Mutex::Mutex(__attribute__((unused)) const char* name) { + pthread_mutex_init(&mMutex, nullptr); +} +inline Mutex::Mutex(int type, __attribute__((unused)) const char* name) { + if (type == SHARED) { + pthread_mutexattr_t attr; + pthread_mutexattr_init(&attr); + pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED); + pthread_mutex_init(&mMutex, &attr); + pthread_mutexattr_destroy(&attr); + } else { + pthread_mutex_init(&mMutex, nullptr); + } +} +inline Mutex::~Mutex() { + pthread_mutex_destroy(&mMutex); +} +inline int32_t Mutex::lock() { + return -pthread_mutex_lock(&mMutex); +} +inline void Mutex::unlock() { + pthread_mutex_unlock(&mMutex); +} +inline int32_t Mutex::tryLock() { + return -pthread_mutex_trylock(&mMutex); +} +inline int32_t Mutex::timedLock(int64_t timeoutNs) { + timespec now; + clock_gettime(CLOCK_REALTIME, &now); + timeoutNs += now.tv_sec * 1000000000 + now.tv_nsec; // 1000000000:unit conversion + const struct timespec ts = { + static_cast(timeoutNs / 1000000000), // 1000000000:unit conversion + static_cast(timeoutNs % 1000000000), // 1000000000:unit conversion + }; + return -pthread_mutex_timedlock(&mMutex, &ts); +} + +// --------------------------------------------------------------------------- + +/* + * Automatic mutex. Declare one of these at the top of a function. + * When the function returns, it will go out of scope, and release the + * mutex. + */ + +typedef Mutex::Autolock AutoMutex; +#endif // _LIBS_RGA_MUTEX_H \ No newline at end of file diff --git a/hardware/rga/include/RgaSingleton.h b/hardware/rga/include/RgaSingleton.h new file mode 100755 index 0000000000000000000000000000000000000000..ff371f1e9fe90483fc871c4ea0f16ea87e22c23d --- /dev/null +++ b/hardware/rga/include/RgaSingleton.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _LIBS_RGA_SINGLETON_H +#define _LIBS_RGA_SINGLETON_H + +#include "RgaMutex.h" + +#if defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wundefined-var-template" +#endif + +template +class Singleton { +public: + static TYPE& getInstance() + { + Mutex::Autolock _l(sLock); + TYPE* instance = sInstance; + if (instance == nullptr) { + instance = new TYPE(); + sInstance = instance; + } + return *instance; + } + static bool hasInstance() + { + Mutex::Autolock _l(sLock); + return sInstance != nullptr; + } + +protected: + ~Singleton() { } + Singleton() { } + +private: + Singleton(const Singleton&); + Singleton& operator = (const Singleton&); + static Mutex sLock; + static TYPE* sInstance; +}; + +#if defined(__clang__) +#pragma clang diagnostic pop +#endif + +#define RGA_SINGLETON_STATIC_INSTANCE(TYPE) \ + template<> ::Mutex \ + (::Singleton< TYPE >::sLock)(::Mutex::PRIVATE); \ + template<> TYPE* ::Singleton< TYPE >::sInstance(nullptr); /* NOLINT */ \ + template class ::Singleton< TYPE >; + +#endif //_LIBS_RGA_SINGLETON_H diff --git a/hardware/rga/include/RgaUtils.h b/hardware/rga/include/RgaUtils.h new file mode 100755 index 0000000000000000000000000000000000000000..27f9394d8e0435a4dd852819e76f3237a850f0c4 --- /dev/null +++ b/hardware/rga/include/RgaUtils.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _rga_utils_h_ +#define _rga_utils_h_ + +// ------------------------------------------------------------------------------- +float get_bpp_from_format(int format); +int get_buf_from_file(void *buf, int f, int sw, int sh, int index); +int output_buf_data_to_file(void *buf, int f, int sw, int sh, int index); +const char *translate_format_str(int format); +#endif + diff --git a/hardware/rga/include/RockchipRga.h b/hardware/rga/include/RockchipRga.h new file mode 100755 index 0000000000000000000000000000000000000000..f67e96ce41925e3087247f7e3cc12e9243507aa6 --- /dev/null +++ b/hardware/rga/include/RockchipRga.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _rockchip_rga_h_ +#define _rockchip_rga_h_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "drmrga.h" +#include "GrallocOps.h" +#include "RgaUtils.h" +#include "rga.h" + +////////////////////////////////////////////////////////////////////////////////// +#include "RgaSingleton.h" + +class RockchipRga : public Singleton { +public: + + static inline RockchipRga& get() { + return getInstance(); + } + + int RkRgaInit(); + void RkRgaDeInit(); + void RkRgaGetContext(void **ctx); + int RkRgaAllocBuffer(int drm_fd /* input */, bo_t *bo_info, + int width, int height, int bpp, int flags); + int RkRgaFreeBuffer(int drm_fd /* input */, bo_t *bo_info); + int RkRgaGetAllocBuffer(bo_t *bo_info, int width, int height, int bpp); + int RkRgaGetAllocBufferExt(bo_t *bo_info, int width, int height, int bpp, int flags); + int RkRgaGetAllocBufferCache(bo_t *bo_info, int width, int height, int bpp); + int RkRgaGetMmap(bo_t *bo_info); + int RkRgaUnmap(bo_t *bo_info); + int RkRgaFree(bo_t *bo_info); + int RkRgaGetBufferFd(bo_t *bo_info, int *fd); + int RkRgaBlit(rga_info *src, rga_info *dst, rga_info *src1); + int RkRgaCollorFill(rga_info *dst); + int RkRgaCollorPalette(rga_info *src, rga_info *dst, rga_info *lut); + int RkRgaFlush(); + void RkRgaSetLogOnceFlag(int log) + { + mLogOnce = log; + } + void RkRgaSetAlwaysLogFlag(bool log) + { + mLogAlways = log; + } + void RkRgaLogOutRgaReq(struct rga_req rgaReg); + int RkRgaLogOutUserPara(rga_info *rgaInfo); + inline bool RkRgaIsReady() + { + return mSupportRga; + } + + RockchipRga(); + ~RockchipRga(); +private: + bool mSupportRga; + int mLogOnce; + int mLogAlways; + void *mContext; + + friend class Singleton; +}; +#endif diff --git a/hardware/rga/include/drmrga.h b/hardware/rga/include/drmrga.h new file mode 100755 index 0000000000000000000000000000000000000000..c23db2c5aabd1c4d763982fb67b5edaf4d382bf4 --- /dev/null +++ b/hardware/rga/include/drmrga.h @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _rk_drm_rga_ +#define _rk_drm_rga_ + +/* flip source image horizontally (around the vertical axis) */ +#define HAL_TRANSFORM_FLIP_H 0x01 +/* flip source image vertically (around the horizontal axis) */ +#define HAL_TRANSFORM_FLIP_V 0x02 +/* rotate source image 90 degrees clockwise */ +#define HAL_TRANSFORM_ROT_90 0x04 +/* rotate source image 180 degrees */ +#define HAL_TRANSFORM_ROT_180 0x03 +/* rotate source image 270 degrees clockwise */ +#define HAL_TRANSFORM_ROT_270 0x07 + +#define HAL_TRANSFORM_FLIP_H_V 0x08 + +/*****************************************************************************/ + +/* for compatibility */ + +#define DRM_RGA_TRANSFORM_ROT_MASK 0x0000000F +#define DRM_RGA_TRANSFORM_ROT_0 0x00000000 +#define DRM_RGA_TRANSFORM_ROT_90 HAL_TRANSFORM_ROT_90 +#define DRM_RGA_TRANSFORM_ROT_180 HAL_TRANSFORM_ROT_180 +#define DRM_RGA_TRANSFORM_ROT_270 HAL_TRANSFORM_ROT_270 + +#define DRM_RGA_TRANSFORM_FLIP_MASK 0x00000003 +#define DRM_RGA_TRANSFORM_FLIP_H HAL_TRANSFORM_FLIP_H +#define DRM_RGA_TRANSFORM_FLIP_V HAL_TRANSFORM_FLIP_V + +enum { + AWIDTH = 0, + AHEIGHT, + ASTRIDE, + AFORMAT, + ASIZE, + ATYPE, +}; +/*****************************************************************************/ + +/* memory type definitions. */ +enum drm_rockchip_gem_mem_type { + /* Physically Continuous memory and used as default. */ + ROCKCHIP_BO_CONTIG = 1 << 0, + /* cachable mapping. */ + ROCKCHIP_BO_CACHABLE = 1 << 1, + /* write-combine mapping. */ + ROCKCHIP_BO_WC = 1 << 2, + ROCKCHIP_BO_SECURE = 1 << 3, + ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE | + ROCKCHIP_BO_WC | ROCKCHIP_BO_SECURE +}; + +typedef struct bo { + int fd; + void *ptr; + size_t size; + size_t offset; + size_t pitch; + unsigned handle; +} bo_t; + +/* + @value size: user not need care about.For avoid read/write out of memory + */ +typedef struct rga_rect { + int xoffset; + int yoffset; + int width; + int height; + int wstride; + int hstride; + int format; + int size; +} rga_rect_t; + +typedef struct rga_nn { + int nn_flag; + int scale_r; + int scale_g; + int scale_b; + int offset_r; + int offset_g; + int offset_b; +} rga_nn_t; + +typedef struct rga_dither { + int enable; + int mode; + int lut0_l; + int lut0_h; + int lut1_l; + int lut1_h; +} rga_dither_t; + +/* + @value fd: use fd to share memory, it can be ion shard fd,and dma fd. + @value virAddr:userspace address + @value phyAddr:use phy address + @value hnd: use buffer_handle_t + */ +typedef struct rga_info { + int fd; + void *virAddr; + void *phyAddr; + unsigned hnd; + int format; + rga_rect_t rect; + unsigned int blend; + int bufferSize; + int rotation; + int color; + int testLog; + int mmuFlag; + int colorkey_en; + int colorkey_mode; + int colorkey_max; + int colorkey_min; + int scale_mode; + int color_space_mode; + int sync_mode; + rga_nn_t nn; + rga_dither_t dither; + int rop_code; + int reserve[127]; +} rga_info_t; + + +typedef struct drm_rga { + rga_rect_t src; + rga_rect_t dst; +} drm_rga_t; + +/* + @fun rga_set_rect:For use to set the rects esayly + + @param rect:The rect user want to set,like setting the src rect: + drm_rga_t rects; + rga_set_rect(rects.src,0,0,1920,1080,1920,NV12); + mean to set the src rect to the value. + */ +static inline int rga_set_rect(rga_rect_t *rect, int x, int y, int w, int h, int sw, int sh, int f) +{ + if (!rect) { + return -EINVAL; + } + rect->xoffset = x; + rect->yoffset = y; + rect->width = w; + rect->height = h; + rect->wstride = sw; + rect->hstride = sh; + rect->format = f; + return 0; +} + +static inline void rga_set_rotation(rga_info_t *info, int angle) +{ + if (angle == 90) { // 90:HAL_TRANSFORM_ROT + info->rotation = HAL_TRANSFORM_ROT_90; + } else if (angle == 180) { // 180:HAL_TRANSFORM_ROT + info->rotation = HAL_TRANSFORM_ROT_180; + } else if (angle == 270) { // 270:HAL_TRANSFORM_ROT + info->rotation = HAL_TRANSFORM_ROT_270; + } +} +/*****************************************************************************/ + +#endif diff --git a/hardware/rga/include/im2d.h b/hardware/rga/include/im2d.h new file mode 100755 index 0000000000000000000000000000000000000000..640d25770278fc398500a6fbefe6832d43220f40 --- /dev/null +++ b/hardware/rga/include/im2d.h @@ -0,0 +1,908 @@ +/* + * Copyright (C) 2020 Rockchip Electronics Co., Ltd. + * Authors: + * PutinLee + * Cerf Yu + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _im2d_h_ +#define _im2d_h_ + +#include "securec.h" +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef IM_API +#define IM_API /* define API export as needed */ +#endif + +typedef enum { + /* Rotation */ + IM_HAL_TRANSFORM_ROT_90 = 1 << 0, + IM_HAL_TRANSFORM_ROT_180 = 1 << 1, + IM_HAL_TRANSFORM_ROT_270 = 1 << 2, + IM_HAL_TRANSFORM_FLIP_H = 1 << 3, + IM_HAL_TRANSFORM_FLIP_V = 1 << 4, + IM_HAL_TRANSFORM_FLIP_H_V = 1 << 5, + IM_HAL_TRANSFORM_MASK = 0x3f, + + /* + * Blend + * Additional blend usage, can be used with both source and target configs. + * If none of the below is set, the default "SRC over DST" is applied. + */ + IM_ALPHA_BLEND_SRC_OVER = 1 << 6, /* Default, Porter-Duff "SRC over DST" */ + IM_ALPHA_BLEND_SRC = 1 << 7, /* Porter-Duff "SRC" */ + IM_ALPHA_BLEND_DST = 1 << 8, /* Porter-Duff "DST" */ + IM_ALPHA_BLEND_SRC_IN = 1 << 9, /* Porter-Duff "SRC in DST" */ + IM_ALPHA_BLEND_DST_IN = 1 << 10, /* Porter-Duff "DST in SRC" */ + IM_ALPHA_BLEND_SRC_OUT = 1 << 11, /* Porter-Duff "SRC out DST" */ + IM_ALPHA_BLEND_DST_OUT = 1 << 12, /* Porter-Duff "DST out SRC" */ + IM_ALPHA_BLEND_DST_OVER = 1 << 13, /* Porter-Duff "DST over SRC" */ + IM_ALPHA_BLEND_SRC_ATOP = 1 << 14, /* Porter-Duff "SRC ATOP" */ + IM_ALPHA_BLEND_DST_ATOP = 1 << 15, /* Porter-Duff "DST ATOP" */ + IM_ALPHA_BLEND_XOR = 1 << 16, /* Xor */ + IM_ALPHA_BLEND_MASK = 0x1ffc0, + + IM_ALPHA_COLORKEY_NORMAL = 1 << 17, + IM_ALPHA_COLORKEY_INVERTED = 1 << 18, + IM_ALPHA_COLORKEY_MASK = 0x60000, + + IM_SYNC = 1 << 19, + IM_ASYNC = 1 << 26, + IM_CROP = 1 << 20, /* Unused */ + IM_COLOR_FILL = 1 << 21, + IM_COLOR_PALETTE = 1 << 22, + IM_NN_QUANTIZE = 1 << 23, + IM_ROP = 1 << 24, + IM_ALPHA_BLEND_PRE_MUL = 1 << 25, +} IM_USAGE; + +typedef enum { + IM_ROP_AND = 0x88, + IM_ROP_OR = 0xee, + IM_ROP_NOT_DST = 0x55, + IM_ROP_NOT_SRC = 0x33, + IM_ROP_XOR = 0xf6, + IM_ROP_NOT_XOR = 0xf9, +} IM_ROP_CODE; + +typedef enum { + IM_RGA_SUPPORT_FORMAT_ERROR_INDEX = 0, + IM_RGA_SUPPORT_FORMAT_RGB_INDEX, + IM_RGA_SUPPORT_FORMAT_RGB_OTHER_INDEX, + IM_RGA_SUPPORT_FORMAT_BPP_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_8_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_10_INDEX, + IM_RGA_SUPPORT_FORMAT_YUYV_420_INDEX, + IM_RGA_SUPPORT_FORMAT_YUYV_422_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_400_INDEX, + IM_RGA_SUPPORT_FORMAT_Y4_INDEX, + IM_RGA_SUPPORT_FORMAT_MASK_INDEX, +} IM_RGA_SUPPORT_FORMAT_INDEX; + +typedef enum { + IM_RGA_SUPPORT_FORMAT_ERROR = 1 << IM_RGA_SUPPORT_FORMAT_ERROR_INDEX, + IM_RGA_SUPPORT_FORMAT_RGB = 1 << IM_RGA_SUPPORT_FORMAT_RGB_INDEX, + IM_RGA_SUPPORT_FORMAT_RGB_OTHER = 1 << IM_RGA_SUPPORT_FORMAT_RGB_OTHER_INDEX, + IM_RGA_SUPPORT_FORMAT_BPP = 1 << IM_RGA_SUPPORT_FORMAT_BPP_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_8 = 1 << IM_RGA_SUPPORT_FORMAT_YUV_8_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_10 = 1 << IM_RGA_SUPPORT_FORMAT_YUV_10_INDEX, + IM_RGA_SUPPORT_FORMAT_YUYV_420 = 1 << IM_RGA_SUPPORT_FORMAT_YUYV_420_INDEX, + IM_RGA_SUPPORT_FORMAT_YUYV_422 = 1 << IM_RGA_SUPPORT_FORMAT_YUYV_422_INDEX, + IM_RGA_SUPPORT_FORMAT_YUV_400 = 1 << IM_RGA_SUPPORT_FORMAT_YUV_400_INDEX, + IM_RGA_SUPPORT_FORMAT_Y4 = 1 << IM_RGA_SUPPORT_FORMAT_Y4_INDEX, + IM_RGA_SUPPORT_FORMAT_MASK = ~((~(unsigned int)0x0 << IM_RGA_SUPPORT_FORMAT_MASK_INDEX) | 1), +} IM_RGA_SUPPORT_FORMAT; + +typedef enum { + IM_RGA_SUPPORT_FEATURE_ERROR_INDEX = 0, + IM_RGA_SUPPORT_FEATURE_COLOR_FILL_INDEX, + IM_RGA_SUPPORT_FEATURE_COLOR_PALETTE_INDEX, + IM_RGA_SUPPORT_FEATURE_ROP_INDEX, + IM_RGA_SUPPORT_FEATURE_QUANTIZE_INDEX, + IM_RGA_SUPPORT_FEATURE_SRC1_R2Y_CSC_INDEX, + IM_RGA_SUPPORT_FEATURE_DST_FULL_CSC_INDEX, + IM_RGA_SUPPORT_FEATURE_MASK_INDEX, +} IM_RGA_SUPPORT_FEATURE_INDEX; + +typedef enum { + IM_RGA_SUPPORT_FEATURE_ERROR = 1 << IM_RGA_SUPPORT_FEATURE_ERROR_INDEX, + IM_RGA_SUPPORT_FEATURE_COLOR_FILL = 1 << IM_RGA_SUPPORT_FEATURE_COLOR_FILL_INDEX, + IM_RGA_SUPPORT_FEATURE_COLOR_PALETTE = 1 << IM_RGA_SUPPORT_FEATURE_COLOR_PALETTE_INDEX, + IM_RGA_SUPPORT_FEATURE_ROP = 1 << IM_RGA_SUPPORT_FEATURE_ROP_INDEX, + IM_RGA_SUPPORT_FEATURE_QUANTIZE = 1 << IM_RGA_SUPPORT_FEATURE_QUANTIZE_INDEX, + IM_RGA_SUPPORT_FEATURE_SRC1_R2Y_CSC = 1 << IM_RGA_SUPPORT_FEATURE_SRC1_R2Y_CSC_INDEX, + IM_RGA_SUPPORT_FEATURE_DST_FULL_CSC = 1 << IM_RGA_SUPPORT_FEATURE_DST_FULL_CSC_INDEX, + IM_RGA_SUPPORT_FEATURE_MASK = ~((~(unsigned int)0x0 << IM_RGA_SUPPORT_FEATURE_MASK_INDEX) | 1), +} IM_RGA_SUPPORT_FEATURE; + +/* Status codes, returned by any blit function */ +typedef enum { + IM_STATUS_NOERROR = 2, + IM_STATUS_SUCCESS = 1, + IM_STATUS_NOT_SUPPORTED = -1, + IM_STATUS_OUT_OF_MEMORY = -2, + IM_STATUS_INVALID_PARAM = -3, + IM_STATUS_ILLEGAL_PARAM = -4, + IM_STATUS_FAILED = 0, +} IM_STATUS; + +/* Status codes, returned by any blit function */ +typedef enum { + IM_YUV_TO_RGB_BT601_LIMIT = 1 << 0, + IM_YUV_TO_RGB_BT601_FULL = 2 << 0, + IM_YUV_TO_RGB_BT709_LIMIT = 3 << 0, + IM_YUV_TO_RGB_MASK = 3 << 0, + IM_RGB_TO_YUV_BT601_FULL = 1 << 2, + IM_RGB_TO_YUV_BT601_LIMIT = 2 << 2, + IM_RGB_TO_YUV_BT709_LIMIT = 3 << 2, + IM_RGB_TO_YUV_MASK = 3 << 2, + IM_RGB_TO_Y4 = 1 << 4, + IM_RGB_TO_Y4_DITHER = 2 << 4, + IM_RGB_TO_Y1_DITHER = 3 << 4, + IM_Y4_MASK = 3 << 4, + IM_RGB_FULL = 1 << 8, + IM_RGB_CLIP = 2 << 8, + IM_YUV_BT601_LIMIT_RANGE = 3 << 8, + IM_YUV_BT601_FULL_RANGE = 4 << 8, + IM_YUV_BT709_LIMIT_RANGE = 5 << 8, + IM_YUV_BT709_FULL_RANGE = 6 << 8, + IM_FULL_CSC_MASK = 0xf << 8, + IM_COLOR_SPACE_DEFAULT = 0, +} IM_COLOR_SPACE_MODE; + +typedef enum { + IM_UP_SCALE, + IM_DOWN_SCALE, +} IM_SCALE; + +typedef enum { + INTER_NEAREST, + INTER_LINEAR, + INTER_CUBIC, +} IM_SCALE_MODE; + +/* Get RGA basic information index */ +typedef enum { + RGA_VENDOR = 0, + RGA_VERSION, + RGA_MAX_INPUT, + RGA_MAX_OUTPUT, + RGA_SCALE_LIMIT, + RGA_INPUT_FORMAT, + RGA_OUTPUT_FORMAT, + RGA_FEATURE, + RGA_EXPECTED, + RGA_ALL, +} IM_INFORMATION; + +/*rga version index*/ +typedef enum { + RGA_V_ERR = 0x0, + RGA_1 = 0x1, + RGA_1_PLUS = 0x2, + RGA_2 = 0x3, + RGA_2_LITE0 = 0x4, + RGA_2_LITE1 = 0x5, + RGA_2_ENHANCE = 0x6, +} RGA_VERSION_NUM; + +typedef struct { + RGA_VERSION_NUM version; + unsigned int input_resolution; + unsigned int output_resolution; + unsigned int scale_limit; + unsigned int performance; + unsigned int input_format; + unsigned int output_format; + unsigned int feature; + char reserved[28]; +} rga_info_table_entry; + +/* Rectangle definition */ +typedef struct { + int x; /* upper-left x */ + int y; /* upper-left y */ + int width; /* width */ + int height; /* height */ +} im_rect; + +typedef struct { + int max; /* The Maximum value of the color key */ + int min; /* The minimum value of the color key */ +} im_colorkey_range; + + +typedef struct im_nn { + int scale_r; /* scaling factor on R channal */ + int scale_g; /* scaling factor on G channal */ + int scale_b; /* scaling factor on B channal */ + int offset_r; /* offset on R channal */ + int offset_g; /* offset on G channal */ + int offset_b; /* offset on B channal */ +} im_nn_t; + +/* im_info definition */ +typedef struct { + void* vir_addr; /* virtual address */ + void* phy_addr; /* physical address */ + int fd; /* shared fd */ + int width; /* width */ + int height; /* height */ + int wstride; /* wstride */ + int hstride; /* hstride */ + int format; /* format */ + int color_space_mode; /* color_space_mode */ + int color; /* color, used by color fill */ + int global_alpha; /* global_alpha */ + im_colorkey_range colorkey_range; /* range value of color key */ + im_nn_t nn; + int rop_code; +} rga_buffer_t; + +/* + * @return error message string + */ +#define imStrError(...) \ + ({ \ + const char* err; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + err = imStrError_t(IM_STATUS_INVALID_PARAM); \ + } else if (argc == 1){ \ + err = imStrError_t((IM_STATUS)args[0]); \ + } else { \ + err = ("Fatal error, imStrError() too many parameters\n"); \ + printf("Fatal error, imStrError() too many parameters\n"); \ + } \ + err; \ + }) +IM_API const char* imStrError_t(IM_STATUS status); + +/* + * @return rga_buffer_t + */ +#define wrapbuffer_virtualaddr(vir_addr, width, height, format, ...) \ + ({ \ + rga_buffer_t buffer; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + buffer = wrapbuffer_virtualaddr_t(vir_addr, width, height, width, height, format); \ + } else if (argc == 2){ \ + buffer = wrapbuffer_virtualaddr_t(vir_addr, width, height, args[0], args[1], format); \ + } else { \ + printf("invalid parameter\n"); \ + } \ + buffer; \ + }) + +#define wrapbuffer_physicaladdr(phy_addr, width, height, format, ...) \ + ({ \ + rga_buffer_t buffer; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + buffer = wrapbuffer_physicaladdr_t(phy_addr, width, height, width, height, format); \ + } else if (argc == 2){ \ + buffer = wrapbuffer_physicaladdr_t(phy_addr, width, height, args[0], args[1], format); \ + } else { \ + printf("invalid parameter\n"); \ + } \ + buffer; \ + }) + +#define wrapbuffer_fd(fd, width, height, format, ...) \ + ({ \ + rga_buffer_t buffer; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + buffer = wrapbuffer_fd_t(fd, width, height, width, height, format); \ + } else if (argc == 2){ \ + buffer = wrapbuffer_fd_t(fd, width, height, args[0], args[1], format); \ + } else { \ + printf("invalid parameter\n"); \ + } \ + buffer; \ + }) + +IM_API rga_buffer_t wrapbuffer_virtualaddr_t( + void* vir_addr, + int width, + int height, + int wstride, + int hstride, + int format); +IM_API rga_buffer_t wrapbuffer_physicaladdr_t(void* phy_addr, + int width, + int height, + int wstride, + int hstride, + int format); +IM_API rga_buffer_t wrapbuffer_fd_t(int fd, int width, int height, int wstride, int hstride, int format); + +/* + * Get RGA basic information, supported resolution, supported format, etc. + * + * @param name + * RGA_VENDOR + * RGA_VERSION + * RGA_MAX_INPUT + * RGA_MAX_OUTPUT + * RGA_INPUT_FORMAT + * RGA_OUTPUT_FORMAT + * RGA_EXPECTED + * RGA_ALL + * + * @returns a usage describing properties of RGA. + */ +IM_API IM_STATUS rga_get_info(rga_info_table_entry *return_table); + +/* + * Query RGA basic information, supported resolution, supported format, etc. + * + * @param name + * RGA_VENDOR + * RGA_VERSION + * RGA_MAX_INPUT + * RGA_MAX_OUTPUT + * RGA_INPUT_FORMAT + * RGA_OUTPUT_FORMAT + * RGA_EXPECTED + * RGA_ALL + * + * @returns a string describing properties of RGA. + */ +IM_API const char* querystring(int name); + +/* + * check RGA basic information, supported resolution, supported format, etc. + * + * @param src + * @param dst + * @param src_rect + * @param dst_rect + * @param mode_usage + * + * @returns no error or else negative error code. + */ +#define imcheck(src, dst, src_rect, dst_rect, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_NOERROR; \ + rga_buffer_t pat; \ + im_rect pat_rect; \ + errno_t eok = memset_s(&pat, sizeof(rga_buffer_t), 0, sizeof(rga_buffer_t)); \ + if (!eok) { \ + printf("memset_s failed!\n"); \ + } \ + eok = memset_s(&pat_rect, sizeof(im_rect), 0, sizeof(im_rect)); \ + if (!eok) { \ + printf("memset_s failed!\n"); \ + } \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcheck_t(src, dst, pat, src_rect, dst_rect, pat_rect, 0); \ + } else if (argc == 1){ \ + ret = imcheck_t(src, dst, pat, src_rect, dst_rect, pat_rect, args[0]); \ + } else { \ + ret = IM_STATUS_FAILED; \ + printf("check failed\n"); \ + } \ + ret; \ + }) +#define imcheck_composite(src, dst, pat, src_rect, dst_rect, pat_rect, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_NOERROR; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcheck_t(src, dst, pat, src_rect, dst_rect, pat_rect, 0); \ + } else if (argc == 1){ \ + ret = imcheck_t(src, dst, pat, src_rect, dst_rect, pat_rect, args[0]); \ + } else { \ + ret = IM_STATUS_FAILED; \ + printf("check failed\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imcheck_t(const rga_buffer_t src, const rga_buffer_t dst, const rga_buffer_t pat, + const im_rect src_rect, const im_rect dst_rect, const im_rect pat_rect, const int mdoe_usage); + +/* + * Resize + * + * @param src + * @param dst + * @param fx + * @param fy + * @param interpolation + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imresize(src, dst, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + double args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(double); \ + if (argc == 0) { \ + ret = imresize_t(src, dst, 0, 0, INTER_LINEAR, 1); \ + } else if (argc == 2){ \ + ret = imresize_t(src, dst, args[0], args[1], INTER_LINEAR, 1); \ + } else if (argc == 3){ \ + ret = imresize_t(src, dst, args[0], args[1], (int)args[2], 1); \ + } else if (argc == 4){ \ + ret = imresize_t(src, dst, args[0], args[1], (int)args[2], (int)args[3]); \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +#define impyramid(src, dst, direction) \ + imresize_t(src, \ + dst, \ + (direction) == IM_UP_SCALE ? 0.5 : 2, \ + (direction) == IM_UP_SCALE ? 0.5 : 2, \ + INTER_LINEAR, 1) + +IM_API IM_STATUS imresize_t(const rga_buffer_t src, rga_buffer_t dst, double fx, double fy, int interpolation, int sync); + +/* + * Crop + * + * @param src + * @param dst + * @param rect + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imcrop(src, dst, rect, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcrop_t(src, dst, rect, 1); \ + } else if (argc == 1){ \ + ret = imcrop_t(src, dst, rect, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imcrop_t(const rga_buffer_t src, rga_buffer_t dst, im_rect rect, int sync); + +/* + * rotation + * + * @param src + * @param dst + * @param rotation + * IM_HAL_TRANSFORM_ROT_90 + * IM_HAL_TRANSFORM_ROT_180 + * IM_HAL_TRANSFORM_ROT_270 + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imrotate(src, dst, rotation, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imrotate_t(src, dst, rotation, 1); \ + } else if (argc == 1){ \ + ret = imrotate_t(src, dst, rotation, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imrotate_t(const rga_buffer_t src, rga_buffer_t dst, int rotation, int sync); + +/* + * flip + * + * @param src + * @param dst + * @param mode + * IM_HAL_TRANSFORM_FLIP_H + * IM_HAL_TRANSFORM_FLIP_V + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imflip(src, dst, mode, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imflip_t(src, dst, mode, 1); \ + } else if (argc == 1){ \ + ret = imflip_t(src, dst, mode, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imflip_t (const rga_buffer_t src, rga_buffer_t dst, int mode, int sync); + +/* + * fill/reset/draw + * + * @param src + * @param dst + * @param rect + * @param color + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imfill(buf, rect, color, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imfill_t(buf, rect, color, 1); \ + } else if (argc == 1){ \ + ret = imfill_t(buf, rect, color, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +#define imreset(buf, rect, color, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imfill_t(buf, rect, color, 1); \ + } else if (argc == 1){ \ + ret = imfill_t(buf, rect, color, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +#define imdraw(buf, rect, color, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imfill_t(buf, rect, color, 1); \ + } else if (argc == 1){ \ + ret = imfill_t(buf, rect, color, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imfill_t(rga_buffer_t dst, im_rect rect, int color, int sync); + +/* + * palette + * + * @param src + * @param dst + * @param lut + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define impalette(src, dst, lut, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = impalette_t(src, dst, lut, 1); \ + } else if (argc == 1){ \ + ret = impalette_t(src, dst, lut, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS impalette_t(rga_buffer_t src, rga_buffer_t dst, rga_buffer_t lut, int sync); + +/* + * translate + * + * @param src + * @param dst + * @param x + * @param y + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imtranslate(src, dst, x, y, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imtranslate_t(src, dst, x, y, 1); \ + } else if (argc == 1){ \ + ret = imtranslate_t(src, dst, x, y, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imtranslate_t(const rga_buffer_t src, rga_buffer_t dst, int x, int y, int sync); + +/* + * copy + * + * @param src + * @param dst + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imcopy(src, dst, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcopy_t(src, dst, 1); \ + } else if (argc == 1){ \ + ret = imcopy_t(src, dst, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imcopy_t(const rga_buffer_t src, rga_buffer_t dst, int sync); + +/* + * blend (SRC + DST -> DST or SRCA + SRCB -> DST) + * + * @param srcA + * @param srcB can be NULL. + * @param dst + * @param mode + * IM_ALPHA_BLEND_MODE + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imblend(srcA, dst, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + rga_buffer_t srcB; \ + errno_t eok = memset_s(&srcB, sizeof(rga_buffer_t), 0x00, sizeof(rga_buffer_t)); \ + if (!eok) { \ + printf("memset_s failed!\n"); \ + } \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imblend_t(srcA, srcB, dst, IM_ALPHA_BLEND_SRC_OVER, 1); \ + } else if (argc == 1){ \ + ret = imblend_t(srcA, srcB, dst, args[0], 1); \ + } else if (argc == 2){ \ + ret = imblend_t(srcA, srcB, dst, args[0], args[1]); \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +#define imcomposite(srcA, srcB, dst, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imblend_t(srcA, srcB, dst, IM_ALPHA_BLEND_SRC_OVER, 1); \ + } else if (argc == 1){ \ + ret = imblend_t(srcA, srcB, dst, args[0], 1); \ + } else if (argc == 2){ \ + ret = imblend_t(srcA, srcB, dst, args[0], args[1]); \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imblend_t(const rga_buffer_t srcA, const rga_buffer_t srcB, rga_buffer_t dst, int mode, int sync); + +/* + * color key + * + * @param src + * @param dst + * @param colorkey_range + * max color + * min color + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imcolorkey(src, dst, range, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcolorkey_t(src, dst, range, IM_ALPHA_COLORKEY_NORMAL, 1); \ + } else if (argc == 1){ \ + ret = imcolorkey_t(src, dst, range, args[0], 1); \ + } else if (argc == 2){ \ + ret = imcolorkey_t(src, dst, range, args[0], args[1]); \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imcolorkey_t(const rga_buffer_t src, rga_buffer_t dst, im_colorkey_range range, int mode, int sync); + +/* + * format convert + * + * @param src + * @param dst + * @param sfmt + * @param dfmt + * @param mode + * color space mode: IM_COLOR_SPACE_MODE + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imcvtcolor(src, dst, sfmt, dfmt, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imcvtcolor_t(src, dst, sfmt, dfmt, IM_COLOR_SPACE_DEFAULT, 1); \ + } else if (argc == 1){ \ + ret = imcvtcolor_t(src, dst, sfmt, dfmt, args[0], 1); \ + } else if (argc == 2){ \ + ret = imcvtcolor_t(src, dst, sfmt, dfmt, args[0], args[1]); \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imcvtcolor_t(rga_buffer_t src, rga_buffer_t dst, int sfmt, int dfmt, int mode, int sync); + +/* + * nn quantize + * + * @param src + * @param dst + * @param nninfo + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imquantize(src, dst, nn_info, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imquantize_t(src, dst, nn_info, 1); \ + } else if (argc == 1){ \ + ret = imquantize_t(src, dst, nn_info, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) + +IM_API IM_STATUS imquantize_t(const rga_buffer_t src, rga_buffer_t dst, im_nn_t nn_info, int sync); + +/* + * ROP + * + * @param src + * @param dst + * @param rop_code + * @param sync + * wait until operation complete + * + * @returns success or else negative error code. + */ +#define imrop(src, dst, rop_code, ...) \ + ({ \ + IM_STATUS ret = IM_STATUS_SUCCESS; \ + int args[] = {__VA_ARGS__}; \ + int argc = sizeof(args)/sizeof(int); \ + if (argc == 0) { \ + ret = imrop_t(src, dst, rop_code, 1); \ + } else if (argc == 1){ \ + ret = imrop_t(src, dst, rop_code, args[0]);; \ + } else { \ + ret = IM_STATUS_INVALID_PARAM; \ + printf("invalid parameter\n"); \ + } \ + ret; \ + }) +IM_API IM_STATUS imrop_t(const rga_buffer_t src, rga_buffer_t dst, int rop_code, int sync); + +/* + * process + * + * @param src + * @param dst + * @param usage + * @param ... + * wait until operation complete + * + * @returns success or else negative error code. + */ +IM_API IM_STATUS improcess(rga_buffer_t src, rga_buffer_t dst, rga_buffer_t pat, im_rect srect, im_rect drect, im_rect prect, int usage); + +/* + * block until all execution is complete + * + * @returns success or else negative error code. + */ +IM_API IM_STATUS imsync(void); + +#ifdef __cplusplus +} +#endif +#endif /* _im2d_h_ */ diff --git a/hardware/rga/include/platform_gralloc4.h b/hardware/rga/include/platform_gralloc4.h new file mode 100755 index 0000000000000000000000000000000000000000..2f3ae79cde1b02f88761520d6a67d14f9755b78a --- /dev/null +++ b/hardware/rga/include/platform_gralloc4.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* -------------------------------------------------------------------------------------------------------- + * File: platform_gralloc4.h + * + * Desc: 声明对 buffer_handle_t 实例的 get metadata, import_buffer/free_buffer, lock_buffer/unlock_buffer 等接口. + * 这些接口都将基于 IMapper 4.0 (gralloc 4.0) 实现. + * + * ----------------------------------------------------------------------------------- + * < 习语 和 缩略语 > : + * + * ----------------------------------------------------------------------------------- + * Usage: + * + * Note: + * + * Author: ChenZhen + * + * Log: + * init. + ----Fri Aug 28 10:10:14 2020 + * + * -------------------------------------------------------------------------------------------------------- + */ + + +#ifndef __PLATFORM_GRALLOC4_H__ +#define __PLATFORM_GRALLOC4_H__ + + +/* --------------------------------------------------------------------------------------------------------- + * Include Files + * --------------------------------------------------------------------------------------------------------- + */ +#include + +#include + +#include +#include + +#include + +/* --------------------------------------------------------------------------------------------------------- + * Macros Definition + * --------------------------------------------------------------------------------------------------------- + */ + + +namespace gralloc4 { +/* --------------------------------------------------------------------------------------------------------- + * Types and Structures Definition + * --------------------------------------------------------------------------------------------------------- + */ + + +/* --------------------------------------------------------------------------------------------------------- + * Global Functions' Prototype + * --------------------------------------------------------------------------------------------------------- + */ + +/* + * 获取 'handle' 引用的 graphic_buffer 的 internal_format. + */ +uint64_t get_internal_format(buffer_handle_t handle); + +int get_width(buffer_handle_t handle, uint64_t* width); + +int get_height(buffer_handle_t handle, uint64_t* height); + +int get_pixel_stride(buffer_handle_t handle, int* pixel_stride); + +int get_byte_stride(buffer_handle_t handle, int* byte_stride); + +int get_format_requested(buffer_handle_t handle, int* format_requested); + +int get_usage(buffer_handle_t handle, uint64_t* usage); + +int get_allocation_size(buffer_handle_t handle, uint64_t* usage); + +int get_share_fd(buffer_handle_t handle, int* share_fd); + +void unlock(buffer_handle_t bufferHandle); + +void freeBuffer(buffer_handle_t handle); + +/* --------------------------------------------------------------------------------------------------------- + * Inline Functions Implementation + * --------------------------------------------------------------------------------------------------------- + */ +} + +#endif /* __PLATFORM_GRALLOC4_H__ */ diff --git a/hardware/rga/include/rga.h b/hardware/rga/include/rga.h new file mode 100755 index 0000000000000000000000000000000000000000..5a2172845724d3178a3ec3f3c365475bfc913474 --- /dev/null +++ b/hardware/rga/include/rga.h @@ -0,0 +1,654 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd. + * Authors: + * Zhiqin Wei + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _RGA_DRIVER_H_ +#define _RGA_DRIVER_H_ +#include +#ifdef __cplusplus +extern "C" +{ +#endif + +#define RGA_BLIT_SYNC 0x5017 +#define RGA_BLIT_ASYNC 0x5018 +#define RGA_FLUSH 0x5019 +#define RGA_GET_RESULT 0x501a +#define RGA_GET_VERSION 0x501b + +#define RGA2_BLIT_SYNC 0x6017 +#define RGA2_BLIT_ASYNC 0x6018 +#define RGA2_FLUSH 0x6019 +#define RGA2_GET_RESULT 0x601a +#define RGA2_GET_VERSION 0x601b +#define RGA2_GET_VERSION 0x601b + +#define RGA_REG_CTRL_LEN 0x8 /* 8 */ +#define RGA_REG_CMD_LEN 0x1c /* 28 */ +#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ + + + +#ifndef ENABLE +#define ENABLE 1 +#endif + + +#ifndef DISABLE +#define DISABLE 0 +#endif + + + +/* RGA process mode enum */ +enum { + bitblt_mode = 0x0, + color_palette_mode = 0x1, + color_fill_mode = 0x2, + line_point_drawing_mode = 0x3, + blur_sharp_filter_mode = 0x4, + pre_scaling_mode = 0x5, + update_palette_table_mode = 0x6, + update_patten_buff_mode = 0x7, +}; + + +enum { + rop_enable_mask = 0x2, + dither_enable_mask = 0x8, + fading_enable_mask = 0x10, + PD_enbale_mask = 0x20, +}; + +enum { + yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ + yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ + yuv2rgb_mode2 = 0x2, /* BT.709 */ + + rgb2yuv_601_full = 0x1 << 8, + rgb2yuv_709_full = 0x2 << 8, + yuv2yuv_601_limit_2_709_limit = 0x3 << 8, + yuv2yuv_601_limit_2_709_full = 0x4 << 8, + yuv2yuv_709_limit_2_601_limit = 0x5 << 8, + yuv2yuv_709_limit_2_601_full = 0x6 << 8, // not support + yuv2yuv_601_full_2_709_limit = 0x7 << 8, + yuv2yuv_601_full_2_709_full = 0x8 << 8, // not support + yuv2yuv_709_full_2_601_limit = 0x9 << 8, // not support + yuv2yuv_709_full_2_601_full = 0xa << 8, // not support + full_csc_mask = 0xf00, +}; + +/* RGA rotate mode */ +enum { + rotate_mode0 = 0x0, /* no rotate */ + rotate_mode1 = 0x1, /* rotate */ + rotate_mode2 = 0x2, /* x_mirror */ + rotate_mode3 = 0x3, /* y_mirror */ +}; + +enum { + color_palette_mode0 = 0x0, /* 1K */ + color_palette_mode1 = 0x1, /* 2K */ + color_palette_mode2 = 0x2, /* 4K */ + color_palette_mode3 = 0x3, /* 8K */ +}; + +enum { + BB_BYPASS = 0x0, /* no rotate */ + BB_ROTATE = 0x1, /* rotate */ + BB_X_MIRROR = 0x2, /* x_mirror */ + BB_Y_MIRROR = 0x3 /* y_mirror */ +}; + +enum { + nearby = 0x0, /* no rotate */ + bilinear = 0x1, /* rotate */ + bicubic = 0x2, /* x_mirror */ +}; + + + + + +/* +// Alpha Red Green Blue +{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 +{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 +{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 +{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 +{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 +{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 +{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 +{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 + +*/ +/* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, + * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ +typedef enum _Rga_SURF_FORMAT { + RK_FORMAT_RGBA_8888 = 0x0 << 8, + RK_FORMAT_RGBX_8888 = 0x1 << 8, + RK_FORMAT_RGB_888 = 0x2 << 8, + RK_FORMAT_BGRA_8888 = 0x3 << 8, + RK_FORMAT_RGB_565 = 0x4 << 8, + RK_FORMAT_RGBA_5551 = 0x5 << 8, + RK_FORMAT_RGBA_4444 = 0x6 << 8, + RK_FORMAT_BGR_888 = 0x7 << 8, + + RK_FORMAT_YCbCr_422_SP = 0x8 << 8, + RK_FORMAT_YCbCr_422_P = 0x9 << 8, + RK_FORMAT_YCbCr_420_SP = 0xa << 8, + RK_FORMAT_YCbCr_420_P = 0xb << 8, + + RK_FORMAT_YCrCb_422_SP = 0xc << 8, + RK_FORMAT_YCrCb_422_P = 0xd << 8, + RK_FORMAT_YCrCb_420_SP = 0xe << 8, + RK_FORMAT_YCrCb_420_P = 0xf << 8, + + RK_FORMAT_BPP1 = 0x10 << 8, + RK_FORMAT_BPP2 = 0x11 << 8, + RK_FORMAT_BPP4 = 0x12 << 8, + RK_FORMAT_BPP8 = 0x13 << 8, + + RK_FORMAT_Y4 = 0x14 << 8, + RK_FORMAT_YCbCr_400 = 0x15 << 8, + + RK_FORMAT_BGRX_8888 = 0x16 << 8, + + RK_FORMAT_YVYU_422 = 0x18 << 8, + RK_FORMAT_YVYU_420 = 0x19 << 8, + RK_FORMAT_VYUY_422 = 0x1a << 8, + RK_FORMAT_VYUY_420 = 0x1b << 8, + RK_FORMAT_YUYV_422 = 0x1c << 8, + RK_FORMAT_YUYV_420 = 0x1d << 8, + RK_FORMAT_UYVY_422 = 0x1e << 8, + RK_FORMAT_UYVY_420 = 0x1f << 8, + + RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, + RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, + RK_FORMAT_YCbCr_422_10b_SP = 0x22 << 8, + RK_FORMAT_YCrCb_422_10b_SP = 0x23 << 8, + + RK_FORMAT_BGR_565 = 0x24 << 8, + RK_FORMAT_BGRA_5551 = 0x25 << 8, + RK_FORMAT_BGRA_4444 = 0x26 << 8, + RK_FORMAT_UNKNOWN = 0x100 << 8, +} RgaSURF_FORMAT; + + +typedef struct rga_img_info_t { +#if defined(__arm64__) || defined(__aarch64__) + unsigned long yrgb_addr; /* yrgb mem addr */ + unsigned long uv_addr; /* cb/cr mem addr */ + unsigned long v_addr; /* cr mem addr */ +#else + unsigned int yrgb_addr; /* yrgb mem addr */ + unsigned int uv_addr; /* cb/cr mem addr */ + unsigned int v_addr; /* cr mem addr */ +#endif + unsigned int format; // definition by RK_FORMAT + unsigned short act_w; + unsigned short act_h; + unsigned short x_offset; + unsigned short y_offset; + + unsigned short vir_w; + unsigned short vir_h; + + unsigned short endian_mode; // for BPP + unsigned short alpha_swap; +} +rga_img_info_t; + + +typedef struct mdp_img_act { + unsigned short w; // width + unsigned short h; // height + short x_off; // x offset for the vir + short y_off; // y offset for the vir +} +mdp_img_act; + + + +typedef struct RANGE { + unsigned short min; + unsigned short max; +} +RANGE; + +typedef struct POINT { + unsigned short x; + unsigned short y; +} +POINT; + +typedef struct RECT { + unsigned short xmin; + unsigned short xmax; // width - 1 + unsigned short ymin; + unsigned short ymax; // height - 1 +} RECT; + +typedef struct RGB { + unsigned char r; + unsigned char g; + unsigned char b; + unsigned char res; +}RGB; + + +typedef struct MMU { + unsigned char mmu_en; +#if defined(__arm64__) || defined(__aarch64__) + unsigned long base_addr; +#else + unsigned int base_addr; +#endif + unsigned int mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size */ +} MMU; + + + + +typedef struct COLOR_FILL { + short gr_x_a; + short gr_y_a; + short gr_x_b; + short gr_y_b; + short gr_x_g; + short gr_y_g; + short gr_x_r; + short gr_y_r; +} +COLOR_FILL; + +typedef struct FADING { + unsigned char b; + unsigned char g; + unsigned char r; + unsigned char res; +} +FADING; + + +typedef struct line_draw_t { + POINT start_point; /* LineDraw_start_point */ + POINT end_point; /* LineDraw_end_point */ + unsigned int color; /* LineDraw_color */ + unsigned int flag; /* (enum) LineDrawing mode sel */ + unsigned int line_width; /* range 1~16 */ +} +line_draw_t; + +/* color space convert coefficient. */ +typedef struct csc_coe_t { + int16_t r_v; + int16_t g_y; + int16_t b_u; + int32_t off; +} csc_coe_t; + +typedef struct full_csc_t { + unsigned char flag; + csc_coe_t coe_y; + csc_coe_t coe_u; + csc_coe_t coe_v; +} full_csc_t; + +struct rga_req { + unsigned char render_mode; /* (enum) process mode sel */ + + rga_img_info_t src; /* src image info */ + rga_img_info_t dst; /* dst image info */ + rga_img_info_t pat; /* patten image info */ + +#if defined(__arm64__) || defined(__aarch64__) + unsigned long rop_mask_addr; /* rop4 mask addr */ + unsigned long LUT_addr; /* LUT addr */ +#else + unsigned int rop_mask_addr; /* rop4 mask addr */ + unsigned int LUT_addr; /* LUT addr */ +#endif + + RECT clip; /* dst clip window default value is dst_vir */ + /* value from [0, w-1] / [0, h-1] */ + + int sina; /* dst angle default value 0 16.16 scan from table */ + int cosa; /* dst angle default value 0 16.16 scan from table */ + + unsigned short alpha_rop_flag; /* alpha rop process flag */ + /* ([0] = 1 alpha_rop_enable) */ + /* ([1] = 1 rop enable) */ + /* ([2] = 1 fading_enable) */ + /* ([3] = 1 PD_enable) */ + /* ([4] = 1 alpha cal_mode_sel) */ + /* ([5] = 1 dither_enable) */ + /* ([6] = 1 gradient fill mode sel) */ + /* ([7] = 1 AA_enable) */ + /* ([8] = 1 nn_quantize) */ + /* ([9] = 1 Real color mode) */ + + unsigned char scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ + + unsigned int color_key_max; /* color key max */ + unsigned int color_key_min; /* color key min */ + + unsigned int fg_color; /* foreground color */ + unsigned int bg_color; /* background color */ + + COLOR_FILL gr_color; /* color fill use gradient */ + + line_draw_t line_draw_info; + + FADING fading; + + unsigned char PD_mode; /* porter duff alpha mode sel */ + + unsigned char alpha_global_value; /* global alpha value */ + + unsigned short rop_code; /* rop2/3/4 code scan from rop code table */ + + unsigned char bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type */ + + unsigned char palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ + + unsigned char yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ + + unsigned char endian_mode; /* 0/big endian 1/little endian */ + + unsigned char rotate_mode; /* (enum) rotate mode */ + /* 0x0, no rotate */ + /* 0x1, rotate */ + /* 0x2, x_mirror */ + /* 0x3, y_mirror */ + + unsigned char color_fill_mode; /* 0 solid color / 1 patten color */ + + MMU mmu_info; /* mmu information */ + + unsigned char alpha_rop_mode; /* ([0~1] alpha mode) */ + /* ([2~3] rop mode) */ + /* ([4] zero mode en) */ + /* ([5] dst alpha mode) (RGA1) */ + + unsigned char src_trans_mode; + + unsigned char dither_mode; + + full_csc_t full_csc; /* full color space convert */ + + unsigned char CMD_fin_int_enable; + + /* completion is reported through a callback */ + void (*complete)(int retval); +}; + +int RGA_set_src_act_info( + struct rga_req *req, + unsigned int width, /* act width */ + unsigned int height, /* act height */ + unsigned int x_off, /* x_off */ + unsigned int y_off /* y_off */ +); + +#if defined(__arm64__) || defined(__aarch64__) +int RGA_set_src_vir_info( + struct rga_req *req, + unsigned long yrgb_addr, /* yrgb_addr */ + unsigned long uv_addr, /* uv_addr */ + unsigned long v_addr, /* v_addr */ + unsigned int vir_w, /* vir width */ + unsigned int vir_h, /* vir height */ + unsigned char format, /* format */ + unsigned char a_swap_en /* only for 32bit RGB888 format */ +); +#else +int RGA_set_src_vir_info( + struct rga_req *req, + unsigned int yrgb_addr, /* yrgb_addr */ + unsigned int uv_addr, /* uv_addr */ + unsigned int v_addr, /* v_addr */ + unsigned int vir_w, /* vir width */ + unsigned int vir_h, /* vir height */ + unsigned char format, /* format */ + unsigned char a_swap_en /* only for 32bit RGB888 format */ +); +#endif + +int RGA_set_dst_act_info( + struct rga_req *req, + unsigned int width, /* act width */ + unsigned int height, /* act height */ + unsigned int x_off, /* x_off */ + unsigned int y_off /* y_off */ +); + +#if defined(__arm64__) || defined(__aarch64__) +int RGA_set_dst_vir_info( + struct rga_req *msg, + unsigned long yrgb_addr, /* yrgb_addr */ + unsigned long uv_addr, /* uv_addr */ + unsigned long v_addr, /* v_addr */ + unsigned int vir_w, /* vir width */ + unsigned int vir_h, /* vir height */ + RECT *clip, /* clip window */ + unsigned char format, /* format */ + unsigned char a_swap_en +); +#else +int RGA_set_dst_vir_info( + struct rga_req *msg, + unsigned int yrgb_addr, /* yrgb_addr */ + unsigned int uv_addr, /* uv_addr */ + unsigned int v_addr, /* v_addr */ + unsigned int vir_w, /* vir width */ + unsigned int vir_h, /* vir height */ + RECT *clip, /* clip window */ + unsigned char format, /* format */ + unsigned char a_swap_en +); +#endif + +int RGA_set_pat_info( + struct rga_req *msg, + unsigned int width, + unsigned int height, + unsigned int x_off, + unsigned int y_off, + unsigned int pat_format +); + +#if defined(__arm64__) || defined(__aarch64__) +int RGA_set_rop_mask_info( + struct rga_req *msg, + unsigned long rop_mask_addr, + unsigned int rop_mask_endian_mode +); +#else +int RGA_set_rop_mask_info( + struct rga_req *msg, + unsigned int rop_mask_addr, + unsigned int rop_mask_endian_mode +); +#endif + +int RGA_set_alpha_en_info( + struct rga_req *msg, + unsigned int alpha_cal_mode, /* 0:alpha' = alpha + (alpha>>7) | alpha' = alpha */ + unsigned int alpha_mode, /* 0 global alpha / 1 per pixel alpha / 2 mix mode */ + unsigned int global_a_value, + unsigned int PD_en, /* porter duff alpha mode en */ + unsigned int PD_mode, + unsigned int dst_alpha_en ); /* use dst alpha */ + +int RGA_set_rop_en_info( + struct rga_req *msg, + unsigned int ROP_mode, + unsigned int ROP_code, + unsigned int color_mode, + unsigned int solid_color +); + + +int RGA_set_fading_en_info( + struct rga_req *msg, + unsigned char r, + unsigned char g, + unsigned char b +); + +int RGA_set_src_trans_mode_info( + struct rga_req *msg, + unsigned char trans_mode, + unsigned char a_en, + unsigned char b_en, + unsigned char g_en, + unsigned char r_en, + unsigned char color_key_min, + unsigned char color_key_max, + unsigned char zero_mode_en +); + + +int RGA_set_bitblt_mode( + struct rga_req *msg, + unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic + unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror + unsigned int angle, // rotate angle + unsigned int dither_en, // dither en flag + unsigned int AA_en, // AA flag + unsigned int yuv2rgb_mode +); + + +int RGA_set_color_palette_mode( + struct rga_req *msg, + unsigned char palette_mode, /* 1bpp/2bpp/4bpp/8bpp */ + unsigned char endian_mode, /* src endian mode sel */ + unsigned int bpp1_0_color, /* BPP1 = 0 */ + unsigned int bpp1_1_color /* BPP1 = 1 */ +); + + +int RGA_set_color_fill_mode( + struct rga_req *msg, + COLOR_FILL *gr_color, /* gradient color part */ + unsigned char gr_satur_mode, /* saturation mode */ + unsigned char cf_mode, /* patten fill or solid fill */ + unsigned int color, /* solid color */ + unsigned short pat_width, /* pattern width */ + unsigned short pat_height, /* pattern height */ + unsigned char pat_x_off, /* pattern x offset */ + unsigned char pat_y_off, /* pattern y offset */ + unsigned char aa_en /* alpha en */ +); + + +int RGA_set_line_point_drawing_mode( + struct rga_req *msg, + POINT sp, /* start point */ + POINT ep, /* end point */ + unsigned int color, /* line point drawing color */ + unsigned int line_width, /* line width */ + unsigned char AA_en, /* AA en */ + unsigned char last_point_en /* last point en */ +); + + +int RGA_set_blur_sharp_filter_mode( + struct rga_req *msg, + unsigned char filter_mode, /* blur/sharpness */ + unsigned char filter_type, /* filter intensity */ + unsigned char dither_en /* dither_en flag */ +); + +int RGA_set_pre_scaling_mode( + struct rga_req *msg, + unsigned char dither_en +); + +#if defined(__arm64__) || defined(__aarch64__) +int RGA_update_palette_table_mode( + struct rga_req *msg, + unsigned long LUT_addr, /* LUT table addr */ + unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ +); +#else +int RGA_update_palette_table_mode( + struct rga_req *msg, + unsigned int LUT_addr, /* LUT table addr */ + unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ +); +#endif + +int RGA_set_update_patten_buff_mode( + struct rga_req *msg, + unsigned int pat_addr, /* patten addr */ + unsigned int w, /* patten width */ + unsigned int h, /* patten height */ + unsigned int format /* patten format */ +); + +#if defined(__arm64__) || defined(__aarch64__) +int RGA_set_mmu_info( + struct rga_req *msg, + unsigned char mmu_en, + unsigned char src_flush, + unsigned char dst_flush, + unsigned char cmd_flush, + unsigned long base_addr, + unsigned char page_size +); +#else +int RGA_set_mmu_info( + struct rga_req *msg, + unsigned char mmu_en, + unsigned char src_flush, + unsigned char dst_flush, + unsigned char cmd_flush, + unsigned int base_addr, + unsigned char page_size +); +#endif + +void rga_set_fds_offsets( + struct rga_req *rga_request, + unsigned short src_fd, + unsigned short dst_fd, + unsigned int src_offset, + unsigned int dst_offset); + +int RGA_set_src_fence_flag( + struct rga_req *msg, + int acq_fence, + int src_flag +); + + +int RGA_set_dst_fence_flag( + struct rga_req *msg, + int dst_flag +); + +int RGA_get_dst_fence( + struct rga_req *msg +); +#ifdef __cplusplus +} +#endif + +#endif /*_RK29_IPP_DRIVER_H_*/ diff --git a/hardware/rga/lib/librga.z.so b/hardware/rga/lib/librga.z.so new file mode 100644 index 0000000000000000000000000000000000000000..105dea363c24d100a0b45e00e782a5d0a6235675 Binary files /dev/null and b/hardware/rga/lib/librga.z.so differ diff --git a/hardware/rga/lib64/librga.z.so b/hardware/rga/lib64/librga.z.so new file mode 100644 index 0000000000000000000000000000000000000000..aabdcca575804349c72e6ccb0b6b85fb52ca8825 Binary files /dev/null and b/hardware/rga/lib64/librga.z.so differ diff --git a/hardware/wifi/BUILD.gn b/hardware/wifi/BUILD.gn new file mode 100755 index 0000000000000000000000000000000000000000..436c9aae5609ba54223737fcb0cdfc2d427b2eb8 --- /dev/null +++ b/hardware/wifi/BUILD.gn @@ -0,0 +1,101 @@ +# Copyright (C) 2021 HiHope Open Source Organization . +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +import("//build/ohos.gni") + +AP6XXX_ETC_DIR = "//device/soc/rockchip/hardware/wifi/ap6xxx" +DNS_CONFIG_DIR = "//device/soc/rockchip/hardware/wifi" +WIFI_LIB_DIR = "//device/soc/rockchip/hardware/wifi/lib" +WIFI_BIN_DIR = "//device/soc/rockchip/hardware/wifi/bin" + +ohos_prebuilt_etc("clm_bcm43752a2_ag.blob") { + source = "$AP6XXX_ETC_DIR/clm_bcm43752a2_ag.blob" + install_images = [ vendor_base_dir ] + relative_install_dir = "firmware" + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("fw_bcm43752a2_ag_apsta.bin") { + source = "$AP6XXX_ETC_DIR/fw_bcm43752a2_ag_apsta.bin" + install_images = [ vendor_base_dir ] + relative_install_dir = "firmware" + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("fw_bcm43752a2_ag.bin") { + source = "$AP6XXX_ETC_DIR/fw_bcm43752a2_ag.bin" + install_images = [ vendor_base_dir ] + relative_install_dir = "firmware" + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("nvram_ap6275s.txt") { + source = "$AP6XXX_ETC_DIR/nvram_ap6275s.txt" + install_images = [ vendor_base_dir ] + relative_install_dir = "firmware" + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_etc("resolv.conf") { + source = "$DNS_CONFIG_DIR/etc/resolv.conf" + install_images = [ "system" ] + part_name = "rockchip_products" + install_enable = true +} + +ohos_prebuilt_executable("wpa_cli") { + install_enable = true + source = "$WIFI_BIN_DIR/wpa_cli" + module_install_dir = "bin" + install_images = [ "system" ] + part_name = "rockchip_products" +} + +ohos_prebuilt_executable("wpa_supplicant") { + install_enable = true + source = "$WIFI_BIN_DIR/wpa_supplicant" + module_install_dir = "bin" + install_images = [ "system" ] + part_name = "rockchip_products" +} + +ohos_prebuilt_shared_library("libwpa.z.so") { + source = "$WIFI_LIB_DIR/libwpa.z.so" + module_install_dir = "lib" + install_images = [ "system" ] + part_name = "rockchip_products" +} + +ohos_prebuilt_shared_library("libwpa_client.z.so") { + source = "$WIFI_LIB_DIR/libwpa_client.z.so" + module_install_dir = "lib" + install_images = [ "system" ] + part_name = "rockchip_products" +} + +group("ap6xxx") { + deps = [ + ":clm_bcm43752a2_ag.blob", + ":fw_bcm43752a2_ag.bin", + ":fw_bcm43752a2_ag_apsta.bin", + ":libwpa.z.so", + ":libwpa_client.z.so", + ":nvram_ap6275s.txt", + ":resolv.conf", + ":wpa_cli", + ":wpa_supplicant", + ] +} diff --git a/hardware/wifi/ap6xxx/clm_bcm43752a2_ag.blob b/hardware/wifi/ap6xxx/clm_bcm43752a2_ag.blob new file mode 100644 index 0000000000000000000000000000000000000000..9fabd6346c5231ac9e2e76827d018defb9b37a3e Binary files /dev/null and b/hardware/wifi/ap6xxx/clm_bcm43752a2_ag.blob differ diff --git a/hardware/wifi/ap6xxx/fw_bcm43752a2_ag.bin b/hardware/wifi/ap6xxx/fw_bcm43752a2_ag.bin new file mode 100644 index 0000000000000000000000000000000000000000..41fb330a5a93f6a842c53d55e220e895d7301811 Binary files /dev/null and b/hardware/wifi/ap6xxx/fw_bcm43752a2_ag.bin differ diff --git a/hardware/wifi/ap6xxx/fw_bcm43752a2_ag_apsta.bin b/hardware/wifi/ap6xxx/fw_bcm43752a2_ag_apsta.bin new file mode 100644 index 0000000000000000000000000000000000000000..41fb330a5a93f6a842c53d55e220e895d7301811 Binary files /dev/null and b/hardware/wifi/ap6xxx/fw_bcm43752a2_ag_apsta.bin differ diff --git a/hardware/wifi/ap6xxx/nvram_ap6275s.txt b/hardware/wifi/ap6xxx/nvram_ap6275s.txt new file mode 100644 index 0000000000000000000000000000000000000000..757b436bda59f2f2f797d16d0079d8a2df6be3d4 --- /dev/null +++ b/hardware/wifi/ap6xxx/nvram_ap6275s.txt @@ -0,0 +1,356 @@ +# AP6275S_NVRAM_V1.4_20201116 +# AP6275S v00 WLBGA reference board, iPA version. + +# SSID generated using Alberto's boardssid.py script: +# ********************SUMMARY******************** +# Board Name: AP6275S_V00 +#SSID: 0x086d +#macmid: 0x02df +# Successfully made SSID entry in sromdefs.tcl. +# Successfully made macmid entry in sromdefs.tcl. +# Successfully made SSID entry in tblssid.py. +# ************************************************* +# $ Copyright Broadcom $ +# +# +# <> +NVRAMRev=$Rev: 844050 $ +sromrev=11 +boardrev=0x1213 +boardtype=0x08ed +boardflags=0x00400201 +boardflags2=0xc0800000 +boardflags3=0x40002180 +#boardnum=57410 +macaddr=00:90:4c:12:d0:01 +jtag_irw=38 + +#Regulatory specific +ccode=0 +regrev=0 + +# Board specific +vendid=0x14e4 +devid=0x449d +manfid=0x2d0 +antswitch=0 +pdgain5g=0 +pdgain2g=0 +aa2g=3 +aa5g=3 +agbg0=2 +agbg1=2 +aga0=2 +aga1=2 +extpagain2g=2 +extpagain5g=2 +rxgains2gelnagaina0=0 +rxgains2gtrisoa0=0 +rxgains2gtrelnabypa0=0 +rxgains5gelnagaina0=0 +rxgains5gtrisoa0=0 +rxgains5gtrelnabypa0=0 +rxgains5gmelnagaina0=0 +rxgains5gmtrisoa0=0 +rxgains5gmtrelnabypa0=0 +rxgains5ghelnagaina0=0 +rxgains5ghtrisoa0=0 +rxgains5ghtrelnabypa0=0 +rxgains2gelnagaina1=0 +rxgains2gtrisoa1=0 +rxgains2gtrelnabypa1=0 +rxgains5gelnagaina1=0 +rxgains5gtrisoa1=0 +rxgains5gtrelnabypa1=0 +rxgains5gmelnagaina1=0 +rxgains5gmtrisoa1=0 +rxgains5gmtrelnabypa1=0 +rxgains5ghelnagaina1=0 +rxgains5ghtrisoa1=0 +rxgains5ghtrelnabypa1=0 + +#RSSI related +# 2G +rssicorrnorm_c0=4,4 +rssicorrnorm_c1=4,4 +# 5G +rssicorrnorm5g_c0=5,5,5,5,5,5,5,5,5,5,5,5 +rssicorrnorm5g_c1=4,4,4,4,4,4,4,4,4,4,4,4 + + +#Two range TSSI +tworangetssi2g=0 +tworangetssi5g=0 +lowpowerrange2g=0 +lowpowerrange5g=0 +low_adc_rate_en=1 +# NOTE :================================================================================ +# To run TPC with Two Range TSSI ,set tworangetssi2g = 1 and lowpowerrange2g = 0 +# To run TPC with Single Range TSSI, set tworangetssi2g = 0 +# To run TPC please READ instructions near pa2ga0 and pa2ga1 as well +# To generate PA params for Low Range set tworangetssi2g = 0 and lowpowerrange2g to 1 +# To generate PA params for High Range set tworangetssi2g = 1 and lowpowerrange2g to 1 +# ====================================================================================== + +#Related to FW Download. Host may use this +nocrc=1 + +otpimagesize=502 + +xtalfreq=37400 + +txchain=3 +rxchain=3 + +cckdigfilttype=2 + +#bit mask for slice capability bit 0:2G bit 1:5G +bandcap=3 + +#TXBF Related +rpcal2g=0 +rpcal5gb0=0 +rpcal5gb1=0 +rpcal5gb2=0 +rpcal5gb3=0 + + +#FDSS Related +fdss_level_2g=4,4 +fdss_interp_en=1 +fdss_level_5g=4,4 +fdss_level_11ax_2g=3,3 +fdss_level_11ax_2g_ch1=3,3 +fdss_level_11ax_2g_ch11=3,3 +fdss_level_11ax_5g=3,3 + +#Tempsense Related +tempthresh=110 +tempoffset=40 +rawtempsense=0x1ff +phycal_tempdelta=15 +temps_period=15 +temps_hysteresis=15 + +#------------- TSSI Related ------------- + +tssipos2g=1 +tssipos5g=1 +AvVmid_c0=2,127,4,92,4,91,4,91,4,94 +AvVmid_c1=2,127,4,93,4,93,4,95,3,110 +# CCK in case of multi mode 2 +pa2gccka0=-71,9683,-1064 +pa2gccka1=-59,9596,-1046 +# OFDM in case of multi_mode 2 +pa2ga0=-131,6980,-771 +pa2ga1=-119,7130,-776 +pa5ga0=-150,6098,-730,-141,6312,-729,-127,6151,-723,-136,5935,-702 +#pa5ga0=-150,6098,-730,-141,6312,-729,-136,6050,-713,-179,5504,-688 +#pa5ga1=-143,5954,-705,-136,6243,-722,-100,6496,-727,-89,7190,-798 +pa5ga1=-148,6016,-719,-136,6243,-722,-123,6019,-711,-89,7190,-798 + +# Max power and offsets +maxp2ga0=86 +maxp2ga1=91 +maxp5ga0=75,76,68,68 +maxp5ga1=73,76,70,76 +subband5gver=0x4 +paparambwver=3 +cckpwroffset0=-5 +cckpwroffset1=-3 +pdoffset40ma0=0x4433 +pdoffset80ma0=0x3232 +pdoffset40ma1=0x2333 +pdoffset80ma1=0x1222 +cckbw202gpo=0x1111 +cckbw20ul2gpo=0x0000 +mcsbw202gpo=0x65544332 +mcsbw402gpo=0xEC444332 +dot11agofdmhrbw202gpo=0x4433 +ofdmlrbw202gpo=0x0022 +mcsbw205glpo=0x87544441 +mcsbw405glpo=0xB6443332 +mcsbw805glpo=0xCC553332 +mcsbw1605glpo=0 +mcsbw205gmpo=0x98544440 +mcsbw405gmpo=0xB6443332 +mcsbw805gmpo=0xBB553332 +mcsbw1605gmpo=0 +mcsbw205ghpo=0x98422230 +mcsbw405ghpo=0xB7554442 +mcsbw805ghpo=0xCC442221 +powoffs2gtna0=-3,-2,-2,-2,-1,-1,-1,-1,-1,-1,-1,-1,-1,0 +powoffs2gtna1=-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0 +mcs1024qam2gpo=0xCCAA +mcs1024qam5glpo=0xFFFFCB +mcs1024qam5gmpo=0xFFEECB +mcs1024qam5ghpo=0xFFFFED +mcs1024qam5gx1po=0xEECCCC +mcs1024qam5gx2po=0xEECCCC +mcs8poexp=0 +mcs9poexp=0 +mcs10poexp=0 + +# 5G power offset per channel for band edge channel +powoffs5g20mtna0=0,0,0,0,0,0,0 +powoffs5g20mtna1=0,0,0,0,0,0,0 +powoffs5g40mtna0=0,0,0,0,0 +powoffs5g40mtna1=0,0,0,0,0 +powoffs5g80mtna0=0,0,0,0,0 +powoffs5g80mtna1=0,0,0,0,0 +mcs11poexp=0 + +#LTE Coex Related +ltecxmux=0 +ltecxpadnum=0x0504 +ltecxfnsel=0x44 +ltecxgcigpio=0x04 +#OOB params +#device_wake_opt=1 +host_wake_opt=0 + +# SWCTRL Related + +swctrlmap_2g=0x10101010,0x06030401,0x04011010,0x000000,0x3FF +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +swctrlmap_5g=0x80408040,0x21240120,0x01208040,0x000000,0x3FF +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 +clb2gslice0core0=0x01b +clb2gslice1core0=0x000 +clb5gslice0core0=0x064 +clb5gslice1core0=0x000 +clb2gslice0core1=0x056 +clb2gslice1core1=0x000 +clb5gslice0core1=0x0a1 +clb5gslice1core1=0x000 +btc_prisel_ant_mask=0x2 +clb_swctrl_smask_ant0=0x27f +clb_swctrl_smask_ant1=0x2f7 + + +#BT Coex 1:TDM +btc_mode=1 + +# --- PAPD Cal related params ---- +txwbpapden=0 # 0:NBPAPD 1:WBPAPD +# NB PAPD Cal params +nb_eps_offset=470,470 +nb_bbmult=66,66 +nb_papdcalidx=6,6 +nb_txattn=2,2 +nb_rxattn=1,1 +nb_eps_stopidx=63 +epsilonoff_5g20_c0=0,1,1,-1 +epsilonoff_5g40_c0=0,1,1,1 +epsilonoff_5g80_c0=1,0,1,1 +epsilonoff_5g20_c1=1,0,0,-1 +epsilonoff_5g40_c1=0,0,0,0 +epsilonoff_5g80_c1=1,0,1,1 +epsilonoff_2g20_c0=0 +epsilonoff_2g20_c1=0 + +# energy detect threshold +ed_thresh2g=-67 +ed_thresh5g=-67 +# energy detect threshold for EU +eu_edthresh2g=-67 +eu_edthresh5g=-67 + +#rpcal coef for imptxbf +rpcal5gb0=238 +rpcal5gb1=228 +rpcal5gb2=222 +rpcal5gb3=229 +rpcal2g=15 +ocl=0 +bt_coex_chdep_div=1 + +# OLPC Related +disable_olpc=0 +olpc_thresh5g=32 +olpc_anchor5g=40 +olpc_thresh2g=32 +olpc_anchor2g=40 + +#PAPR related +paprdis=0 +paprrmcsgamma2g=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain2g=128,128,128,0,0,0,0,0,0,0,0,0 +paprrmcsgamma2g_ch13=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain2g_ch13=128,128,128,0,0,0,0,0,0,0,0,0 +paprrmcsgamma2g_ch1=500,550,550,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain2g_ch1=128,128,128,0,0,0,0,0,0,0,0,0 +paprrmcsgamma5g20=500,500,500,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain5g20=128,128,128,0,0,0,0,0,0,0,0,0 +paprrmcsgamma5g40=600,600,600,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain5g40=128,128,128,0,0,0,0,0,0,0,0,0 +paprrmcsgamma5g80=-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1 +paprrmcsgain5g80=0,0,0,0,0,0,0,0,0,0,0,0 + +# Enable papd for cck when target pwr ge 16dBm +cckpapd_pwrthresh=64 + +## ULOFDMA Board limit PPRs for 2G20 ## +ruppr2g20bpska0=0x8421 +ruppr2g20bpska1=0x8421 +ruppr2g20qpska0=0x8421 +ruppr2g20qpska1=0x8421 +ruppr2g20qam16a0=0x10842 +ruppr2g20qam16a1=0x10842 +ruppr2g20qam64a0=0x18C63 +ruppr2g20qam64a1=0x18C63 +ruppr2g20qam256a0=0x318C6 +ruppr2g20qam256a1=0x318C6 +ruppr2g20qam1024a0=0x5AD6B +ruppr2g20qam1024a1=0x5AD6B +## ULOFDMA Board limit PPRs for 5G20 ## +ruppr5g20bpska0=0x30421 +ruppr5g20bpska1=0x30421 +ruppr5g20qpska0=0x30421 +ruppr5g20qpska1=0x30421 +ruppr5g20qam16a0=0x30842 +ruppr5g20qam16a1=0x30842 +ruppr5g20qam64a0=0x314A5 +ruppr5g20qam64a1=0x314A5 +ruppr5g20qam256a0=0x4A529 +ruppr5g20qam256a1=0x4A529 +ruppr5g20qam1024a0=0x7294A +ruppr5g20qam1024a1=0x7294A +## ULOFDMA Board limit PPRs for 5G40 ## +ruppr5g40bpska0=0x508421 +ruppr5g40bpska1=0x508421 +ruppr5g40qpska0=0x508421 +ruppr5g40qpska1=0x508421 +ruppr5g40qam16a0=0x508421 +ruppr5g40qam16a1=0x508421 +ruppr5g40qam64a0=0x518C63 +ruppr5g40qam64a1=0x518C63 +ruppr5g40qam256a0=0xA42108 +ruppr5g40qam256a1=0xA42108 +ruppr5g40qam1024a0=0xE68421 +ruppr5g40qam1024a1=0xE68421 +## ULOFDMA Board limit PPRs for 5G80 ## +ruppr5g80bpska0=0xC108421 +ruppr5g80bpska1=0xC108421 +ruppr5g80qpska0=0xC108421 +ruppr5g80qpska1=0xC108421 +ruppr5g80qam16a0=0xC108421 +ruppr5g80qam16a1=0xC108421 +ruppr5g80qam64a0=0x14418C63 +ruppr5g80qam64a1=0x14418C63 +ruppr5g80qam256a0=0x2C94A529 +ruppr5g80qam256a1=0x2C94A529 +ruppr5g80qam1024a0=0x3CD60000 +ruppr5g80qam1024a1=0x3CD60000 + +muxenab=0x10 + +# ########### BTC Dynctl profile params ############ +# flags:bit0 - dynctl enabled, bit1 dynamic desense, bit2 dynamic mode, bit 3 TX power control +#btcdyn_flags=1 + +#btcdyn_default_btc_mode=5 +#btcdyn_msw_rows=0 +#btcdyn_dsns_rows=0 +#btc_params1007=100 +#btc_params1017=4 \ No newline at end of file diff --git a/hardware/wifi/bin/wpa_cli b/hardware/wifi/bin/wpa_cli new file mode 100644 index 0000000000000000000000000000000000000000..30892371ed74f2227bb5c9d6a13e78d4562355a4 Binary files /dev/null and b/hardware/wifi/bin/wpa_cli differ diff --git a/hardware/wifi/bin/wpa_supplicant b/hardware/wifi/bin/wpa_supplicant new file mode 100644 index 0000000000000000000000000000000000000000..f2d2c48ee5c0f9049725a35222d97d9fb615ac7b Binary files /dev/null and b/hardware/wifi/bin/wpa_supplicant differ diff --git a/hardware/wifi/etc/resolv.conf b/hardware/wifi/etc/resolv.conf new file mode 100644 index 0000000000000000000000000000000000000000..f5d24a1ad6f3cd7d1f4fbb8b705401518dedbf17 --- /dev/null +++ b/hardware/wifi/etc/resolv.conf @@ -0,0 +1,2 @@ +nameserver 114.114.114.114 +nameserver 8.8.8.8 diff --git a/hardware/wifi/lib/libwpa.z.so b/hardware/wifi/lib/libwpa.z.so new file mode 100644 index 0000000000000000000000000000000000000000..39e61829a77594dcb7b7c15eb79c0c5f1de7c04b Binary files /dev/null and b/hardware/wifi/lib/libwpa.z.so differ diff --git a/hardware/wifi/lib/libwpa_client.z.so b/hardware/wifi/lib/libwpa_client.z.so new file mode 100644 index 0000000000000000000000000000000000000000..94f06e4c43acd705f790cb357415b2e2428866f4 Binary files /dev/null and b/hardware/wifi/lib/libwpa_client.z.so differ diff --git a/hardware/wifi/proc/sys/net/ipv4/ping_group_range b/hardware/wifi/proc/sys/net/ipv4/ping_group_range new file mode 100644 index 0000000000000000000000000000000000000000..f4a3074921b639afe08ccd441bf506df7f65ac7f --- /dev/null +++ b/hardware/wifi/proc/sys/net/ipv4/ping_group_range @@ -0,0 +1 @@ +0 10 \ No newline at end of file