# openenv

**Repository Path**: openlotus/openenv

## Basic Information

- **Project Name**: openenv
- **Description**: an verification solution for riscv core
- **Primary Language**: Verilog
- **License**: Apache-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 0
- **Created**: 2023-05-17
- **Last Updated**: 2024-07-09

## Categories & Tags

**Categories**: Uncategorized

**Tags**: riscv, Core

## README

# openenv

#### 介绍
This repository is an verification solution for riscv core,contains some open source core design（Ariane\Ibex\lowerisc_ip\rift2core）, UVM testbench, Google DV,Spike.

#### 项目架构
1. 验证整体框架
![验证整体框架](vrf/cfg/image.png)

2.Real time compare between DUT result and Spike RM
#### 安装教程

    1.Setup EDA tools( Revrsion above VCS_2017 and Xcelium_2019)
    2.Setup riscv gcc spike DV  (suggested gcc-8.3.0 or above)
      [DV](http://github.com/google/riscv-dv)   
      [Spike](http://github.com/riscv/riscv-isa-sim)  
      Note: ../configure--prefix=$RISCV --enable-commitlog （编译时需要打开日志开关）  
      [GCC](http://github.com/riscv/riscv-gnu-toolchain)  
    3.Modify the scripts as your local path(**/openenv/scripts/set_env.sh, setup_CDNS.sh or setup_synopsys.sh as you needed)
    4.Source the scripts (scripts/set_env.sh)

#### 使用说明
1. Determine your configuration {optional}

    boot_address as your core (you can set the macro in the vrf/cfg/tb.f )
2. Run make with vrf/sim/Makefile  
     **DV**  
    setp1  
      For dv32:   
      ```  
      make run_dv type=dv32  
      make get_seq32 type=dv32    
      For rv64:  
      make run_dv type=dv64  
      make get_seq64 type=dv64  
      ```
    setp2 cfg.mk 
      ``` 
      make regress type=dv32 cpu_len=ibex_32 mode=ibex_32  
      make regress type=dv32 cpu_len=ariane_32 mode=ariane_32  
      make regress type=dv64 cpu_len=ariane_64 mode=ariane_64  
      ```
     Example：Single TC simulation  
    ```
    make run tc=cpu_sanity swtc=riscv_arithmetic_basic_test_0 type=dv32 cpu_len=ibex_32 wave=fsdb mode=output_dir
    ```
    step3
    ```
    make verdi&
    ```

    **RV**  
    setp1  
    For rv32:  
    ```
    make run_rv32 type=rv32 rv_name=rv32ui  
    make get_seq32 type=rv32  
    ```
    For rv64:  
    ```
    make run_rv64 type=rv64 rv_name=rv32ui  
    make get_seq64 type=rv64  `make get_seq64 type=rv64`  
    ```
    setp2 cfg.mk  
    ``` 
    make regress type=rv32 cpu_len=ibex_32 mode=ibex_32
    make regress type=rv32 cpu_len=ariane_32 mode=ariane_32  
    make regress type=rv64 cpu_len=ariane_64 mode=ariane_64  
    ```

    **Example：Single TC simulation    
    ```
    make run tc=cpu_sanity swtc=add type=rv32 cpu_len=ibex_32 wave=fsdb mode=output_dir
    ```
    step3 
    ```   
    make verdi&  
    ```

#### 参与贡献

1.  PCL



#### 特技

1.  使用 Readme\_XXX.md 来支持不同的语言，例如 Readme\_en.md, Readme\_zh.md
2.  Gitee 官方博客 [blog.gitee.com](https://blog.gitee.com)
3.  你可以 [https://gitee.com/explore](https://gitee.com/explore) 这个地址来了解 Gitee 上的优秀开源项目
4.  [GVP](https://gitee.com/gvp) 全称是 Gitee 最有价值开源项目，是综合评定出的优秀开源项目
5.  Gitee 官方提供的使用手册 [https://gitee.com/help](https://gitee.com/help)
6.  Gitee 封面人物是一档用来展示 Gitee 会员风采的栏目 [https://gitee.com/gitee-stars/](https://gitee.com/gitee-stars/)