# FengLin-I开源TSN芯片规范

**Repository Path**: opentsn/FengLin-I

## Basic Information

- **Project Name**: FengLin-I开源TSN芯片规范
- **Description**: 集合包含所有和FengLin-I开源TSN芯片相关的设计规范文档
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 2
- **Created**: 2022-07-29
- **Last Updated**: 2024-12-02

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

No README documentation available for this project.