diff --git a/Dockerfile b/Dockerfile index e855da543ec05c5205d6c75dcfb909bbd0d026cd..ac653d2ef3179dfce778be9a8a7a94354cbcc426 100755 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,3 @@ -# syntax=docker/dockerfile:1.5-labs ARG BASE_IMAGE=ubuntu:22.04 FROM ${BASE_IMAGE} LABEL maintainer="harry0789@qq.com" @@ -17,8 +16,9 @@ ADD ${IEDA_REPO} ${IEDA_WORKSPACE} RUN ln -sf /usr/share/zoneinfo/${TZ} /etc/localtime && \ bash ${IEDA_WORKSPACE}/build.sh -i mirror && \ - apt-get autoremove -y && apt-get clean -y && \ - bash ${IEDA_WORKSPACE}/build.sh -b ${iEDA_BINARY_DIR} && \ + apt-get autoremove -y && apt-get clean -y + +RUN bash ${IEDA_WORKSPACE}/build.sh -b ${iEDA_BINARY_DIR} && \ bash ${IEDA_WORKSPACE}/build.sh -y -d -n WORKDIR ${IEDA_WORKSPACE} diff --git a/scripts/design/ics55_gcd/.gitignore b/scripts/design/ics55_gcd/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..81fd7e54a944f965671122e45e3e479f1bc005fe --- /dev/null +++ b/scripts/design/ics55_gcd/.gitignore @@ -0,0 +1,11 @@ +*.gds +*.gz +*.lib +*.v +*.def +*.txt +*.log +*.rpt +*.spef +iEDA +iEDA_gui diff --git a/scripts/design/ics55_gcd/README.md b/scripts/design/ics55_gcd/README.md new file mode 100644 index 0000000000000000000000000000000000000000..b6e5204facf2ffc7656ce706be0f7cfb86668332 --- /dev/null +++ b/scripts/design/ics55_gcd/README.md @@ -0,0 +1,13 @@ +# ICS55 GCD + +This directory contains the scripts and configuration files to run iEDA on the GCD design. + +To run this flow, please refer to the `run_iEDA.sh` script located in this directory. + +ICS55 PDK is required to run this design. Please ensure you have downloaded ICS55 PDK and set the `PDK_DIR` environment variable to point to the iPD foundry scripts directory. ICS55 PDK is available at: [icsprout55-pdk](https://github.com/openecos-projects/icsprout55-pdk) + +Run flow with: + +```bash +PDK_DIR=/home/test/iPD-git/scripts/foundry/ics55 ./run_iEDA.sh +``` \ No newline at end of file diff --git a/scripts/design/ics55_gcd/default.sdc b/scripts/design/ics55_gcd/default.sdc new file mode 100644 index 0000000000000000000000000000000000000000..5595b3c3eca6d33cad28548c2e317b1258bdb3b6 --- /dev/null +++ b/scripts/design/ics55_gcd/default.sdc @@ -0,0 +1,9 @@ +set clk_name core_clock +set clk_port_name clk +set clk_expect_freq_mhz 100 +set clk_period [expr 1000.0 / $clk_expect_freq_mhz] +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port diff --git a/scripts/design/ics55_gcd/iEDA_config/cts_default_config.json b/scripts/design/ics55_gcd/iEDA_config/cts_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..752e340f5f319fa860ddfd7c9a1205366d8a331e --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/cts_default_config.json @@ -0,0 +1,59 @@ +{ + "use_skew_tree_alg": "ON", + "router_type": "GOCA", + "delay_type": "elmore", + "cluster_type": "kmeans", + "skew_bound": "0.08", + "max_buf_tran": "1.0", + "max_sink_tran": "1.0", + "max_cap": "0.5", + "max_fanout": "32", + "min_length": "50", + "max_length": "400", + "scale_size": 50, + "cluster_size": 32, + "routing_layer": [ + 5, + 6 + ], + "buffer_type": [ + "BUFX8H7L", + "BUFX12H7L", + "BUFX16H7L", + "BUFX20H7L" + ], + "root_buffer_type": "BUFX20H7L", + "root_buffer_required": "OFF", + "inherit_root": "OFF", + "break_long_wire": "OFF", + "level_max_length": [ + "400", + "350" + ], + "level_max_fanout": [ + 32, + 12 + ], + "level_max_cap": [ + "0.5" + ], + "level_skew_bound": [ + "0.08" + ], + "level_cluster_ratio": [ + "1", + "0.9" + ], + "shift_level": 1, + "latency_opt_level": 1, + "global_latency_opt_ratio": "0.5", + "local_latency_opt_ratio": "0.9", + "external_model": [], + "use_netlist": "OFF", + "net_list": [ + { + "clock_name": "core_clock", + "net_name": "clk" + } + ] +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/db_default_config.json b/scripts/design/ics55_gcd/iEDA_config/db_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..d8a64fbf31b240d3b09dc20e90da62a520b8bd97 --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/db_default_config.json @@ -0,0 +1,16 @@ +{ + "INPUT": { + "tech_lef_path": "", + "lef_paths": "", + "def_path": "", + "verilog_path": "", + "lib_path": "", + "sdc_path": "" + }, + "OUTPUT": { + "output_dir_path": "./result/" + }, + "LayerSettings": { + "routing_layer_1st": "MET2" + } +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/drc_default_config.json b/scripts/design/ics55_gcd/iEDA_config/drc_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/scripts/design/ics55_gcd/iEDA_config/flow_config.json b/scripts/design/ics55_gcd/iEDA_config/flow_config.json new file mode 100644 index 0000000000000000000000000000000000000000..ff00cd0bc4b8d3f463c0e27f814f9a4c87b8d290 --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/flow_config.json @@ -0,0 +1,12 @@ +{ + "ConfigPath": { + "idb_path": "$CONFIG_DIR/db_default_config.json", + "ifp_path": "$CONFIG_DIR/fp_default_config.json", + "ipl_path": "$CONFIG_DIR/pl_default_config.json", + "irt_path": "$CONFIG_DIR/rt_default_config.json", + "idrc_path": "$CONFIG_DIR/drc_default_config.json", + "icts_path": "$CONFIG_DIR/cts_default_config.json", + "ito_path": "$CONFIG_DIR/to_default_config.json", + "ipnp_path": "$CONFIG_DIR/pnp_default_config.json" + } +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/fp_default_config.json b/scripts/design/ics55_gcd/iEDA_config/fp_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/scripts/design/ics55_gcd/iEDA_config/no_default_config_fixfanout.json b/scripts/design/ics55_gcd/iEDA_config/no_default_config_fixfanout.json new file mode 100644 index 0000000000000000000000000000000000000000..baceac794a06db2ae63ad41aa54308b5f5d43093 --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/no_default_config_fixfanout.json @@ -0,0 +1,13 @@ +{ + "file_path": { + "design_work_space": "${RESULT_DIR}/no", + "sdc_file": "unused", + "lib_files": "unused", + "lef_files": "unused", + "def_file": "unused", + "output_def": "unused", + "report_file": "${RESULT_DIR}/no/report.txt" + }, + "insert_buffer": "BUFX3H7R", + "max_fanout": 16 +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/pl_default_config.json b/scripts/design/ics55_gcd/iEDA_config/pl_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..8cfff433f51519e10f0225966070b9d6180229fd --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/pl_default_config.json @@ -0,0 +1,63 @@ +{ + "PL": { + "is_max_length_opt": 0, + "max_length_constraint": 1000000, + "is_timing_effort": 0, + "is_congestion_effort": 0, + "ignore_net_degree": 100, + "num_threads": 16, + "info_iter_num": 10, + "GP": { + "Wirelength": { + "init_wirelength_coef": 0.25, + "reference_hpwl": 446000000, + "min_wirelength_force_bar": -300 + }, + "Density": { + "target_density": 0.6, + "is_adaptive_bin": 1, + "bin_cnt_x": 128, + "bin_cnt_y": 128 + }, + "Nesterov": { + "max_iter": 2000, + "max_backtrack": 10, + "init_density_penalty": 0.00008, + "target_overflow": 0.1, + "initial_prev_coordi_update_coef": 100, + "min_precondition": 1.0, + "min_phi_coef": 0.95, + "max_phi_coef": 1.05 + } + }, + "BUFFER": { + "max_buffer_num": 10000, + "buffer_type": [ + "BUFX3H7R" + ] + }, + "LG": { + "max_displacement": 1000000, + "global_right_padding": 0 + }, + "DP": { + "max_displacement": 1000000, + "global_right_padding": 0, + "enable_networkflow": 0 + }, + "Filler": { + "first_iter": [ + "FILLER64H7R", + "FILLER32H7R", + "FILLER16H7R" + ], + "second_iter": [ + "FILLER8H7R", + "FILLER4H7R", + "FILLER2H7R", + "FILLER1H7R" + ], + "min_filler_width": 1 + } + } +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/pnp_default_config.json b/scripts/design/ics55_gcd/iEDA_config/pnp_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..c93aea3fa0feda4c5b2945dac12aae9473c6c228 --- /dev/null +++ b/scripts/design/ics55_gcd/iEDA_config/pnp_default_config.json @@ -0,0 +1,76 @@ +{ + "timing": { + "design_workspace": "" + }, + "power": { + "power_net_name": "VDD" + }, + "egr": { + "map_path": "" + }, + "grid": { + "power_layers": [ + 9, + 8, + 7, + 6, + 5, + 4, + 3 + ], + "ho_region_num": 2, + "ver_region_num": 2 + }, + "simulated_annealing": { + "initial_temp": 100.0, + "cooling_rate": 0.95, + "min_temp": 0.1, + "iterations_per_temp": 10, + "ir_drop_weight": 0.6, + "overflow_weight": 0.4, + "modifiable_layer_min": 3, + "modifiable_layer_max": 6 + }, + "templates": { + "horizontal": [ + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 19200.0, + "offset": 8000.0 + }, + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 38400.0, + "offset": 8000.0 + }, + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 38400.0, + "offset": 27200.0 + } + ], + "vertical": [ + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 19200.0, + "offset": 8000.0 + }, + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 38400.0, + "offset": 8000.0 + }, + { + "width": 8000.0, + "pg_offset": 1600.0, + "space": 38400.0, + "offset": 27200.0 + } + ] + } +} \ No newline at end of file diff --git a/scripts/design/ics55_gcd/iEDA_config/rt_default_config.json b/scripts/design/ics55_gcd/iEDA_config/rt_default_config.json new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/scripts/design/ics55_gcd/result/verilog/gcd_nl.v b/scripts/design/ics55_gcd/result/verilog/gcd_nl.v new file mode 100644 index 0000000000000000000000000000000000000000..1b181cfc34a492e24609f1fea4f5c8b656f3b9c2 --- /dev/null +++ b/scripts/design/ics55_gcd/result/verilog/gcd_nl.v @@ -0,0 +1,2248 @@ +/* Generated by Yosys 0.54+23 (git sha1 513f0f16d, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3) */ + +module gcd(clk, \req_msg[0] , \req_msg[1] , \req_msg[2] , \req_msg[3] , \req_msg[4] , \req_msg[5] , \req_msg[6] , \req_msg[7] , \req_msg[8] , \req_msg[9] , \req_msg[10] , \req_msg[11] , \req_msg[12] , \req_msg[13] , \req_msg[14] , \req_msg[15] , \req_msg[16] , \req_msg[17] , \req_msg[18] , \req_msg[19] +, \req_msg[20] , \req_msg[21] , \req_msg[22] , \req_msg[23] , \req_msg[24] , \req_msg[25] , \req_msg[26] , \req_msg[27] , \req_msg[28] , \req_msg[29] , \req_msg[30] , \req_msg[31] , req_rdy, req_val, reset, \resp_msg[0] , \resp_msg[1] , \resp_msg[2] , \resp_msg[3] , \resp_msg[4] , \resp_msg[5] +, \resp_msg[6] , \resp_msg[7] , \resp_msg[8] , \resp_msg[9] , \resp_msg[10] , \resp_msg[11] , \resp_msg[12] , \resp_msg[13] , \resp_msg[14] , \resp_msg[15] , resp_rdy, resp_val); + wire _000_; + wire _001_; + wire _002_; + wire _003_; + wire _004_; + wire _005_; + wire _006_; + wire _007_; + wire _008_; + wire _009_; + wire _010_; + wire _011_; + wire _012_; + wire _013_; + wire _014_; + wire _015_; + wire _016_; + wire _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire _039_; + wire _040_; + wire _041_; + wire _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire _047_; + wire _048_; + wire _049_; + wire _050_; + wire _051_; + wire _052_; + wire _053_; + wire _054_; + wire _055_; + wire _056_; + wire _057_; + wire _058_; + wire _059_; + wire _060_; + wire _061_; + wire _062_; + wire _063_; + wire _064_; + wire _065_; + wire _066_; + wire _067_; + wire _068_; + wire _069_; + wire _070_; + wire _071_; + wire _072_; + wire _073_; + wire _074_; + wire _075_; + wire _076_; + wire _077_; + wire _078_; + wire _079_; + wire _080_; + wire _081_; + wire _082_; + wire _083_; + wire _084_; + wire _085_; + wire _086_; + wire _087_; + wire _088_; + wire _089_; + wire _090_; + wire _091_; + wire _092_; + wire _093_; + wire _094_; + wire _095_; + wire _096_; + wire _097_; + wire _098_; + wire _099_; + wire _100_; + wire _101_; + wire _102_; + wire _103_; + wire _104_; + wire _105_; + wire _106_; + wire _107_; + wire _108_; + wire _109_; + wire _110_; + wire _111_; + wire _112_; + wire _113_; + wire _114_; + wire _115_; + wire _116_; + wire _117_; + wire _118_; + wire _119_; + wire _120_; + wire _121_; + wire _122_; + wire _123_; + wire _124_; + wire _125_; + wire _126_; + wire _127_; + wire _128_; + wire _129_; + wire _130_; + wire _131_; + wire _132_; + wire _133_; + wire _134_; + wire _135_; + wire _136_; + wire _137_; + wire _138_; + wire _139_; + wire _140_; + wire _141_; + wire _142_; + wire _143_; + wire _144_; + wire _145_; + wire _146_; + wire _147_; + wire _148_; + wire _149_; + wire _150_; + wire _151_; + wire _152_; + wire _153_; + wire _154_; + wire _155_; + wire _156_; + wire _157_; + wire _158_; + wire _159_; + wire _160_; + wire _161_; + wire _162_; + wire _163_; + wire _164_; + wire _165_; + wire _166_; + wire _167_; + wire _168_; + wire _169_; + wire _170_; + wire _171_; + wire _172_; + wire _173_; + wire _174_; + wire _175_; + wire _176_; + wire _177_; + wire _178_; + wire _179_; + wire _180_; + wire _181_; + wire _182_; + wire _183_; + wire _184_; + wire _185_; + wire _186_; + wire _187_; + wire _188_; + wire _189_; + wire _190_; + wire _191_; + wire _192_; + wire _193_; + wire _194_; + wire _195_; + wire _196_; + wire _197_; + wire _198_; + wire _199_; + wire _200_; + wire _201_; + wire _202_; + wire _203_; + wire _204_; + wire _205_; + wire _206_; + wire _207_; + wire _208_; + wire _209_; + wire _210_; + wire _211_; + wire _212_; + wire _213_; + wire _214_; + wire _215_; + wire _216_; + wire _217_; + wire _218_; + wire _219_; + wire _220_; + wire _221_; + wire _222_; + wire _223_; + wire _224_; + wire _225_; + wire _226_; + wire _227_; + wire _228_; + wire _229_; + wire _230_; + wire _231_; + wire _232_; + wire _233_; + wire _234_; + wire _235_; + wire _236_; + wire _237_; + wire _238_; + wire _239_; + wire _240_; + wire _241_; + wire _242_; + wire _243_; + wire _244_; + wire _245_; + wire _246_; + wire _247_; + wire _248_; + wire _249_; + wire _250_; + wire _251_; + wire _252_; + wire _253_; + wire _254_; + wire _255_; + wire _256_; + wire _257_; + wire _258_; + wire _259_; + wire _260_; + wire _261_; + wire _262_; + wire _263_; + wire _264_; + wire _265_; + wire _266_; + wire _267_; + wire _268_; + wire _269_; + wire _270_; + wire _271_; + input clk; + wire clk; + wire \ctrl.curr_state__0_0_ ; + wire \ctrl.curr_state__0_1_ ; + wire \dpath.a_lt_b$in0_0_ ; + wire \dpath.a_lt_b$in0_10_ ; + wire \dpath.a_lt_b$in0_11_ ; + wire \dpath.a_lt_b$in0_12_ ; + wire \dpath.a_lt_b$in0_13_ ; + wire \dpath.a_lt_b$in0_14_ ; + wire \dpath.a_lt_b$in0_15_ ; + wire \dpath.a_lt_b$in0_1_ ; + wire \dpath.a_lt_b$in0_2_ ; + wire \dpath.a_lt_b$in0_3_ ; + wire \dpath.a_lt_b$in0_4_ ; + wire \dpath.a_lt_b$in0_5_ ; + wire \dpath.a_lt_b$in0_6_ ; + wire \dpath.a_lt_b$in0_7_ ; + wire \dpath.a_lt_b$in0_8_ ; + wire \dpath.a_lt_b$in0_9_ ; + wire \dpath.a_lt_b$in1_0_ ; + wire \dpath.a_lt_b$in1_10_ ; + wire \dpath.a_lt_b$in1_11_ ; + wire \dpath.a_lt_b$in1_12_ ; + wire \dpath.a_lt_b$in1_13_ ; + wire \dpath.a_lt_b$in1_14_ ; + wire \dpath.a_lt_b$in1_15_ ; + wire \dpath.a_lt_b$in1_1_ ; + wire \dpath.a_lt_b$in1_2_ ; + wire \dpath.a_lt_b$in1_3_ ; + wire \dpath.a_lt_b$in1_4_ ; + wire \dpath.a_lt_b$in1_5_ ; + wire \dpath.a_lt_b$in1_6_ ; + wire \dpath.a_lt_b$in1_7_ ; + wire \dpath.a_lt_b$in1_8_ ; + wire \dpath.a_lt_b$in1_9_ ; + input \req_msg[0] ; + wire \req_msg[0] ; + input \req_msg[10] ; + wire \req_msg[10] ; + input \req_msg[11] ; + wire \req_msg[11] ; + input \req_msg[12] ; + wire \req_msg[12] ; + input \req_msg[13] ; + wire \req_msg[13] ; + input \req_msg[14] ; + wire \req_msg[14] ; + input \req_msg[15] ; + wire \req_msg[15] ; + input \req_msg[16] ; + wire \req_msg[16] ; + input \req_msg[17] ; + wire \req_msg[17] ; + input \req_msg[18] ; + wire \req_msg[18] ; + input \req_msg[19] ; + wire \req_msg[19] ; + input \req_msg[1] ; + wire \req_msg[1] ; + input \req_msg[20] ; + wire \req_msg[20] ; + input \req_msg[21] ; + wire \req_msg[21] ; + input \req_msg[22] ; + wire \req_msg[22] ; + input \req_msg[23] ; + wire \req_msg[23] ; + input \req_msg[24] ; + wire \req_msg[24] ; + input \req_msg[25] ; + wire \req_msg[25] ; + input \req_msg[26] ; + wire \req_msg[26] ; + input \req_msg[27] ; + wire \req_msg[27] ; + input \req_msg[28] ; + wire \req_msg[28] ; + input \req_msg[29] ; + wire \req_msg[29] ; + input \req_msg[2] ; + wire \req_msg[2] ; + input \req_msg[30] ; + wire \req_msg[30] ; + input \req_msg[31] ; + wire \req_msg[31] ; + input \req_msg[3] ; + wire \req_msg[3] ; + input \req_msg[4] ; + wire \req_msg[4] ; + input \req_msg[5] ; + wire \req_msg[5] ; + input \req_msg[6] ; + wire \req_msg[6] ; + input \req_msg[7] ; + wire \req_msg[7] ; + input \req_msg[8] ; + wire \req_msg[8] ; + input \req_msg[9] ; + wire \req_msg[9] ; + output req_rdy; + wire req_rdy; + input req_val; + wire req_val; + input reset; + wire reset; + output \resp_msg[0] ; + wire \resp_msg[0] ; + output \resp_msg[10] ; + wire \resp_msg[10] ; + output \resp_msg[11] ; + wire \resp_msg[11] ; + output \resp_msg[12] ; + wire \resp_msg[12] ; + output \resp_msg[13] ; + wire \resp_msg[13] ; + output \resp_msg[14] ; + wire \resp_msg[14] ; + output \resp_msg[15] ; + wire \resp_msg[15] ; + output \resp_msg[1] ; + wire \resp_msg[1] ; + output \resp_msg[2] ; + wire \resp_msg[2] ; + output \resp_msg[3] ; + wire \resp_msg[3] ; + output \resp_msg[4] ; + wire \resp_msg[4] ; + output \resp_msg[5] ; + wire \resp_msg[5] ; + output \resp_msg[6] ; + wire \resp_msg[6] ; + output \resp_msg[7] ; + wire \resp_msg[7] ; + output \resp_msg[8] ; + wire \resp_msg[8] ; + output \resp_msg[9] ; + wire \resp_msg[9] ; + input resp_rdy; + wire resp_rdy; + output resp_val; + wire resp_val; + INVX0P7H7L _272_ ( + .A(\ctrl.curr_state__0_1_ ), + .Y(_102_) + ); + BUFX1P4H7L _273_ ( + .A(_102_), + .Y(_103_) + ); + OAI21X1H7L _274_ ( + .A0(_092_), + .A1(_098_), + .B0(_102_), + .Y(_104_) + ); + NAND2X1H7L _275_ ( + .A(_099_), + .B(_104_), + .Y(_105_) + ); + OAOI211X0P5H7L _276_ ( + .A0(_103_), + .A1(resp_rdy), + .B0(_105_), + .C0(reset), + .Y(_001_) + ); + INVX0P5H7R _277_ ( + .A(\ctrl.curr_state__0_0_ ), + .Y(_106_) + ); + BUFX1P4H7L _278_ ( + .A(_106_), + .Y(_107_) + ); + NAND2X0P5H7R _279_ ( + .A(_107_), + .B(\req_msg[16] ), + .Y(_108_) + ); + NAND2X0P5H7R _280_ ( + .A(\dpath.a_lt_b$in0_0_ ), + .B(\dpath.a_lt_b$in1_0_ ), + .Y(_109_) + ); + NAND2BX1P4H7L _281_ ( + .AN(\dpath.a_lt_b$in1_0_ ), + .B(_093_), + .Y(_110_) + ); + OAI211X1P4H7L _282_ ( + .A0(_093_), + .A1(_109_), + .B0(_110_), + .C0(_099_), + .Y(_111_) + ); + OAOI211X0P5H7R _283_ ( + .A0(\dpath.a_lt_b$in1_0_ ), + .A1(_106_), + .B0(_102_), + .C0(\dpath.a_lt_b$in0_0_ ), + .Y(_112_) + ); + AOI31X0P7H7L _284_ ( + .A0(_103_), + .A1(_108_), + .A2(_111_), + .B0(_112_), + .Y(_002_) + ); + BUFX0P5H7R _285_ ( + .A(\ctrl.curr_state__0_1_ ), + .Y(_113_) + ); + NOR2X0P5H7R _286_ ( + .A(_106_), + .B(_113_), + .Y(_114_) + ); + OAI31X0P5H7R _287_ ( + .A0(_065_), + .A1(_059_), + .A2(_056_), + .B0(_055_), + .Y(_115_) + ); + NOR2BX1H7R _288_ ( + .AN(_068_), + .B(_073_), + .Z(_116_) + ); + NAND2X0P5H7R _289_ ( + .A(\dpath.a_lt_b$in1_9_ ), + .B(_069_), + .Y(_117_) + ); + NOR2X0P5H7R _290_ ( + .A(\dpath.a_lt_b$in1_9_ ), + .B(_069_), + .Y(_118_) + ); + AOI21X1P4H7L _291_ ( + .A0(\dpath.a_lt_b$in0_9_ ), + .A1(_117_), + .B0(_118_), + .Y(_119_) + ); + AOI21X1P4H7L _292_ ( + .A0(_115_), + .A1(_116_), + .B0(_119_), + .Y(_120_) + ); + NOR3X1P4H7L _293_ ( + .A(_051_), + .B(_062_), + .C(_119_), + .Y(_121_) + ); + OR3X1H7R _294_ ( + .A(\dpath.a_lt_b$in0_10_ ), + .B(_120_), + .C(_121_), + .Y(_122_) + ); + OAI21X0P5H7R _295_ ( + .A0(_120_), + .A1(_121_), + .B0(\dpath.a_lt_b$in0_10_ ), + .Y(_123_) + ); + AND2X1H7R _296_ ( + .A(_088_), + .B(_089_), + .Y(_124_) + ); + OAI32X2H7L _297_ ( + .A0(_043_), + .A1(_076_), + .A2(_084_), + .B0(_124_), + .B1(_077_), + .Y(_125_) + ); + AOI21X1P4H7L _298_ ( + .A0(_122_), + .A1(_123_), + .B0(_125_), + .Y(_126_) + ); + XNOR2X1H7L _299_ ( + .A(\dpath.a_lt_b$in1_10_ ), + .B(_126_), + .Y(_127_) + ); + OR3X1H7R _300_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[26] ), + .Y(_128_) + ); + OAI21X0P5H7R _301_ ( + .A0(\dpath.a_lt_b$in0_10_ ), + .A1(_103_), + .B0(_128_), + .Y(_129_) + ); + AOI21X0P5H7L _302_ ( + .A0(_114_), + .A1(_127_), + .B0(_129_), + .Y(_003_) + ); + NAND2BX0P5H7R _303_ ( + .AN(\dpath.a_lt_b$in0_10_ ), + .B(\dpath.a_lt_b$in1_10_ ), + .Y(_130_) + ); + OAOI211X1P4H7L _304_ ( + .A0(_120_), + .A1(_121_), + .B0(_130_), + .C0(_040_), + .Y(_131_) + ); + XNOR2X1H7L _305_ ( + .A(\dpath.a_lt_b$in0_11_ ), + .B(_131_), + .Y(_132_) + ); + OR3X1P4H7L _306_ ( + .A(\dpath.a_lt_b$in1_11_ ), + .B(_125_), + .C(_132_), + .Y(_133_) + ); + OAI21X0P5H7R _307_ ( + .A0(_125_), + .A1(_132_), + .B0(\dpath.a_lt_b$in1_11_ ), + .Y(_134_) + ); + OR3X1H7R _308_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[27] ), + .Y(_135_) + ); + OAI21X0P5H7R _309_ ( + .A0(\dpath.a_lt_b$in0_11_ ), + .A1(_102_), + .B0(_135_), + .Y(_136_) + ); + AOI31X0P7H7L _310_ ( + .A0(_114_), + .A1(_133_), + .A2(_134_), + .B0(_136_), + .Y(_004_) + ); + OR3X1H7R _311_ ( + .A(\dpath.a_lt_b$in0_12_ ), + .B(_043_), + .C(_076_), + .Y(_137_) + ); + OAI21X0P5H7R _312_ ( + .A0(_043_), + .A1(_076_), + .B0(\dpath.a_lt_b$in0_12_ ), + .Y(_138_) + ); + AOI21X1H7L _313_ ( + .A0(_137_), + .A1(_138_), + .B0(_092_), + .Y(_139_) + ); + XNOR2X1H7L _314_ ( + .A(\dpath.a_lt_b$in1_12_ ), + .B(_139_), + .Y(_140_) + ); + OR3X1H7R _315_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[28] ), + .Y(_141_) + ); + OAI21X0P5H7R _316_ ( + .A0(\dpath.a_lt_b$in0_12_ ), + .A1(_103_), + .B0(_141_), + .Y(_142_) + ); + AOI21X0P5H7L _317_ ( + .A0(_114_), + .A1(_140_), + .B0(_142_), + .Y(_005_) + ); + INVX0P5H7R _318_ ( + .A(_085_), + .Y(_143_) + ); + OAI2BB1X1H7L _319_ ( + .A0N(_143_), + .A1N(_043_), + .B0(_078_), + .Y(_144_) + ); + MUX2X1P4H7L _320_ ( + .A(_144_), + .B(_143_), + .S0(_076_), + .Y(_145_) + ); + XOR2X1P4H7L _321_ ( + .A(\dpath.a_lt_b$in0_13_ ), + .B(_145_), + .Y(_146_) + ); + OR3X1P4H7L _322_ ( + .A(\dpath.a_lt_b$in1_13_ ), + .B(_125_), + .C(_146_), + .Y(_147_) + ); + OAI21X1H7L _323_ ( + .A0(_125_), + .A1(_146_), + .B0(\dpath.a_lt_b$in1_13_ ), + .Y(_148_) + ); + OR3X1H7R _324_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[29] ), + .Y(_149_) + ); + OAI21X0P5H7R _325_ ( + .A0(\dpath.a_lt_b$in0_13_ ), + .A1(_102_), + .B0(_149_), + .Y(_150_) + ); + AOI31X0P7H7L _326_ ( + .A0(_114_), + .A1(_147_), + .A2(_148_), + .B0(_150_), + .Y(_006_) + ); + OR2X3H7L _327_ ( + .A(_043_), + .B(_076_), + .Y(_151_) + ); + NAND2BX0P5H7R _328_ ( + .AN(\dpath.a_lt_b$in1_13_ ), + .B(\dpath.a_lt_b$in0_13_ ), + .Y(_152_) + ); + NOR2BX1H7L _329_ ( + .AN(\dpath.a_lt_b$in1_13_ ), + .B(\dpath.a_lt_b$in0_13_ ), + .Z(_153_) + ); + AOI21X0P5H7R _330_ ( + .A0(_078_), + .A1(_152_), + .B0(_153_), + .Y(_154_) + ); + XNOR2X0P5H7R _331_ ( + .A(\dpath.a_lt_b$in0_14_ ), + .B(_154_), + .Y(_155_) + ); + INVX0P5H7R _332_ ( + .A(_155_), + .Y(_156_) + ); + AOI21X0P5H7R _333_ ( + .A0(_085_), + .A1(_152_), + .B0(_153_), + .Y(_157_) + ); + XNOR2X0P5H7R _334_ ( + .A(\dpath.a_lt_b$in0_14_ ), + .B(_157_), + .Y(_158_) + ); + OAI21X0P5H7R _335_ ( + .A0(_043_), + .A1(_076_), + .B0(_158_), + .Y(_159_) + ); + OAOI211X4H7L _336_ ( + .A0(_151_), + .A1(_156_), + .B0(_159_), + .C0(_092_), + .Y(_160_) + ); + XNOR2X1H7L _337_ ( + .A(\dpath.a_lt_b$in1_14_ ), + .B(_160_), + .Y(_161_) + ); + OR3X1H7R _338_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[30] ), + .Y(_162_) + ); + OAI21X0P5H7R _339_ ( + .A0(\dpath.a_lt_b$in0_14_ ), + .A1(_102_), + .B0(_162_), + .Y(_163_) + ); + AOI21X0P7H7L _340_ ( + .A0(_114_), + .A1(_161_), + .B0(_163_), + .Y(_007_) + ); + MUXI2X0P5H7R _341_ ( + .A(\dpath.a_lt_b$in1_15_ ), + .B(_077_), + .S0(_083_), + .Y(_164_) + ); + OAI2BB1X0P5H7R _342_ ( + .A0N(\dpath.a_lt_b$in0_15_ ), + .A1N(_088_), + .B0(\dpath.a_lt_b$in1_15_ ), + .Y(_165_) + ); + OAI211X1H7L _343_ ( + .A0(_151_), + .A1(_164_), + .B0(_165_), + .C0(_114_), + .Y(_166_) + ); + AOI31X0P5H7R _344_ ( + .A0(_077_), + .A1(_088_), + .A2(_151_), + .B0(_166_), + .Y(_167_) + ); + NOR2X0P5H7R _345_ ( + .A(\dpath.a_lt_b$in0_15_ ), + .B(_103_), + .Y(_168_) + ); + NOR3X0P5H7R _346_ ( + .A(_099_), + .B(_035_), + .C(\req_msg[31] ), + .Y(_169_) + ); + NOR3X0P7H7L _347_ ( + .A(_167_), + .B(_168_), + .C(_169_), + .Y(_008_) + ); + BUFX0P5H7R _348_ ( + .A(_113_), + .Y(_170_) + ); + NAND2X0P5H7R _349_ ( + .A(_107_), + .B(\req_msg[17] ), + .Y(_171_) + ); + NAND2X0P5H7R _350_ ( + .A(\dpath.a_lt_b$in0_1_ ), + .B(_170_), + .Y(_172_) + ); + NAND2BX0P5H7R _351_ ( + .AN(\dpath.a_lt_b$in0_0_ ), + .B(\dpath.a_lt_b$in1_0_ ), + .Y(_173_) + ); + NAND2BX0P5H7R _352_ ( + .AN(\dpath.a_lt_b$in0_1_ ), + .B(\dpath.a_lt_b$in1_1_ ), + .Y(_174_) + ); + NAND2BX0P5H7R _353_ ( + .AN(\dpath.a_lt_b$in1_1_ ), + .B(\dpath.a_lt_b$in0_1_ ), + .Y(_175_) + ); + NAND2X0P5H7R _354_ ( + .A(_174_), + .B(_175_), + .Y(_176_) + ); + XNOR2X0P5H7R _355_ ( + .A(_173_), + .B(_176_), + .Y(\resp_msg[1] ) + ); + MUX2X1P4H7L _356_ ( + .A(\resp_msg[1] ), + .B(\dpath.a_lt_b$in1_1_ ), + .S0(_092_), + .Y(_177_) + ); + OAI211X1P4H7L _357_ ( + .A0(_099_), + .A1(\req_msg[17] ), + .B0(_177_), + .C0(_103_), + .Y(_178_) + ); + OAI211X1H7L _358_ ( + .A0(_170_), + .A1(_171_), + .B0(_172_), + .C0(_178_), + .Y(_009_) + ); + NAND2X0P5H7R _359_ ( + .A(_107_), + .B(\req_msg[18] ), + .Y(_179_) + ); + NAND2X0P5H7R _360_ ( + .A(\dpath.a_lt_b$in0_2_ ), + .B(_170_), + .Y(_180_) + ); + OAI2XB1X0P5H7R _361_ ( + .A0(_173_), + .A1N(_175_), + .B0(_174_), + .Y(_181_) + ); + AND2X1H7R _362_ ( + .A(_046_), + .B(_048_), + .Y(_182_) + ); + XNOR2X0P5H7R _363_ ( + .A(_181_), + .B(_182_), + .Y(\resp_msg[2] ) + ); + MUX2X1P4H7L _364_ ( + .A(\resp_msg[2] ), + .B(\dpath.a_lt_b$in1_2_ ), + .S0(_092_), + .Y(_183_) + ); + OAI211X1P4H7L _365_ ( + .A0(\dpath.a_lt_b$in0_2_ ), + .A1(_102_), + .B0(_183_), + .C0(_099_), + .Y(_184_) + ); + OAI211X1H7L _366_ ( + .A0(_170_), + .A1(_179_), + .B0(_180_), + .C0(_184_), + .Y(_010_) + ); + NOR2BX1H7R _367_ ( + .AN(\req_msg[19] ), + .B(\ctrl.curr_state__0_0_ ), + .Z(_185_) + ); + AOI21X0P5H7R _368_ ( + .A0(\dpath.a_lt_b$in1_3_ ), + .A1(_034_), + .B0(_185_), + .Y(_186_) + ); + NAND2X0P5H7R _369_ ( + .A(_047_), + .B(_048_), + .Y(_187_) + ); + NAND2BX0P5H7R _370_ ( + .AN(_049_), + .B(_050_), + .Y(_188_) + ); + XNOR2X0P5H7R _371_ ( + .A(_187_), + .B(_188_), + .Y(\resp_msg[3] ) + ); + AOI211X1P4H7L _372_ ( + .A0(\ctrl.curr_state__0_0_ ), + .A1(\resp_msg[3] ), + .B0(_185_), + .C0(_092_), + .Y(_189_) + ); + AOI211X1P4H7L _373_ ( + .A0(_092_), + .A1(_186_), + .B0(_189_), + .C0(_035_), + .Y(_190_) + ); + AO21X0P5H7L _374_ ( + .A0(\dpath.a_lt_b$in0_3_ ), + .A1(_170_), + .B0(_190_), + .Y(_011_) + ); + AOAI211X1P4H7L _375_ ( + .A0(_047_), + .A1(_048_), + .B0(_049_), + .C0(_050_), + .Y(_191_) + ); + XNOR2X0P5H7R _376_ ( + .A(_191_), + .B(_060_), + .Y(\resp_msg[4] ) + ); + MUX2X3H7L _377_ ( + .A(\resp_msg[4] ), + .B(\dpath.a_lt_b$in1_4_ ), + .S0(_092_), + .Y(_192_) + ); + NOR3BX0P5H7R _378_ ( + .AN(\req_msg[20] ), + .B(_035_), + .C(_034_), + .Y(_193_) + ); + AO221X0P5H7L _379_ ( + .A0(\dpath.a_lt_b$in0_4_ ), + .A1(_035_), + .B0(_114_), + .B1(_192_), + .C0(_193_), + .Y(_012_) + ); + NOR2BX1H7R _380_ ( + .AN(\dpath.a_lt_b$in0_4_ ), + .B(\dpath.a_lt_b$in1_4_ ), + .Z(_194_) + ); + AOI31X0P5H7R _381_ ( + .A0(_047_), + .A1(_048_), + .A2(_050_), + .B0(_049_), + .Y(_195_) + ); + NOR2BX1P4H7R _382_ ( + .AN(\dpath.a_lt_b$in1_4_ ), + .B(\dpath.a_lt_b$in0_4_ ), + .Z(_196_) + ); + AOI2BB1X0P5H7R _383_ ( + .A0N(_194_), + .A1N(_195_), + .B0(_196_), + .Y(_197_) + ); + XOR2X0P5H7R _384_ ( + .A(_054_), + .B(_197_), + .Y(\resp_msg[5] ) + ); + NAND2BX1P4H7L _385_ ( + .AN(\dpath.a_lt_b$in1_5_ ), + .B(_093_), + .Y(_198_) + ); + OAI211X1P4H7L _386_ ( + .A0(_093_), + .A1(\resp_msg[5] ), + .B0(_198_), + .C0(_099_), + .Y(_199_) + ); + AOI21X0P5H7R _387_ ( + .A0(_107_), + .A1(\req_msg[21] ), + .B0(_035_), + .Y(_200_) + ); + AOI2BB2X1H7L _388_ ( + .A0N(\dpath.a_lt_b$in0_5_ ), + .A1N(_103_), + .B0(_199_), + .B1(_200_), + .Y(_013_) + ); + OR2X0P5H7R _389_ ( + .A(_058_), + .B(_059_), + .Y(_201_) + ); + AOI2BB1X0P5H7R _390_ ( + .A0N(\dpath.a_lt_b$in1_5_ ), + .A1N(_196_), + .B0(\dpath.a_lt_b$in0_5_ ), + .Y(_202_) + ); + AOI21X0P5H7R _391_ ( + .A0(\dpath.a_lt_b$in1_5_ ), + .A1(_196_), + .B0(_202_), + .Y(_203_) + ); + OA31X1P4H7L _392_ ( + .A0(_194_), + .A1(_191_), + .A2(_053_), + .B0(_203_), + .Y(_204_) + ); + XNOR2X0P5H7R _393_ ( + .A(_201_), + .B(_204_), + .Y(\resp_msg[6] ) + ); + NAND2BX1P4H7L _394_ ( + .AN(\dpath.a_lt_b$in1_6_ ), + .B(_093_), + .Y(_205_) + ); + OAI211X1P4H7L _395_ ( + .A0(_093_), + .A1(\resp_msg[6] ), + .B0(_205_), + .C0(_099_), + .Y(_206_) + ); + AOI21X0P5H7R _396_ ( + .A0(_107_), + .A1(\req_msg[22] ), + .B0(_035_), + .Y(_207_) + ); + AOI2BB2X1H7L _397_ ( + .A0N(\dpath.a_lt_b$in0_6_ ), + .A1N(_103_), + .B0(_206_), + .B1(_207_), + .Y(_014_) + ); + AOI2XB1X0P5H7R _398_ ( + .A0(_204_), + .A1N(_058_), + .B0(_059_), + .Y(_208_) + ); + XNOR2X0P5H7R _399_ ( + .A(_057_), + .B(_208_), + .Y(\resp_msg[7] ) + ); + MUXI2X1H7L _400_ ( + .A(\resp_msg[7] ), + .B(\dpath.a_lt_b$in1_7_ ), + .S0(_093_), + .Y(_209_) + ); + AOI21X0P5H7R _401_ ( + .A0(_107_), + .A1(\req_msg[23] ), + .B0(_035_), + .Y(_210_) + ); + NOR2X0P5H7R _402_ ( + .A(\dpath.a_lt_b$in0_7_ ), + .B(_103_), + .Y(_211_) + ); + OAOI211X1H7L _403_ ( + .A0(_107_), + .A1(_209_), + .B0(_210_), + .C0(_211_), + .Y(_015_) + ); + OA21X0P7H7R _404_ ( + .A0(_051_), + .A1(_062_), + .B0(_066_), + .Y(_212_) + ); + XNOR2X0P5H7R _405_ ( + .A(\dpath.a_lt_b$in0_8_ ), + .B(_212_), + .Y(_213_) + ); + OR3X0P5H7L _406_ ( + .A(\dpath.a_lt_b$in1_8_ ), + .B(_093_), + .C(_213_), + .Y(_214_) + ); + OAI21X0P5H7R _407_ ( + .A0(_093_), + .A1(_213_), + .B0(\dpath.a_lt_b$in1_8_ ), + .Y(_215_) + ); + OR3X1H7R _408_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[24] ), + .Y(_216_) + ); + OAI21X0P5H7R _409_ ( + .A0(\dpath.a_lt_b$in0_8_ ), + .A1(_102_), + .B0(_216_), + .Y(_217_) + ); + AOI31X0P7H7L _410_ ( + .A0(_114_), + .A1(_214_), + .A2(_215_), + .B0(_217_), + .Y(_016_) + ); + AOI211X0P5H7R _411_ ( + .A0(_068_), + .A1(_212_), + .B0(_069_), + .C0(\dpath.a_lt_b$in0_9_ ), + .Y(_218_) + ); + AOA211X1H7L _412_ ( + .A0(_068_), + .A1(_212_), + .B0(_069_), + .C0(\dpath.a_lt_b$in0_9_ ), + .Y(_219_) + ); + NOR3X1P4H7L _413_ ( + .A(_125_), + .B(_218_), + .C(_219_), + .Y(_220_) + ); + XNOR2X1H7L _414_ ( + .A(\dpath.a_lt_b$in1_9_ ), + .B(_220_), + .Y(_221_) + ); + OR3X1H7R _415_ ( + .A(_034_), + .B(_113_), + .C(\req_msg[25] ), + .Y(_222_) + ); + OAI21X0P5H7R _416_ ( + .A0(\dpath.a_lt_b$in0_9_ ), + .A1(_102_), + .B0(_222_), + .Y(_223_) + ); + AOI21X0P5H7L _417_ ( + .A0(_114_), + .A1(_221_), + .B0(_223_), + .Y(_017_) + ); + BUFX0P5H7R _418_ ( + .A(_113_), + .Y(_224_) + ); + NOR2BX16H7L _419_ ( + .AN(_092_), + .B(_106_), + .Z(_225_) + ); + BUFX20H7L _420_ ( + .A(_225_), + .Y(_226_) + ); + AOI22X1P4H7L _421_ ( + .A0(_107_), + .A1(\req_msg[0] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_0_ ), + .Y(_227_) + ); + OAI21X4H7L _422_ ( + .A0(_106_), + .A1(_091_), + .B0(_102_), + .Y(_228_) + ); + BUFX3H7L _423_ ( + .A(_228_), + .Y(_229_) + ); + NAND2X0P5H7R _424_ ( + .A(\dpath.a_lt_b$in1_0_ ), + .B(_229_), + .Y(_230_) + ); + OAI21X1H7L _425_ ( + .A0(_224_), + .A1(_227_), + .B0(_230_), + .Y(_018_) + ); + AOI22X1P4H7L _426_ ( + .A0(_107_), + .A1(\req_msg[10] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_10_ ), + .Y(_231_) + ); + NAND2X0P5H7L _427_ ( + .A(\dpath.a_lt_b$in1_10_ ), + .B(_229_), + .Y(_232_) + ); + OAI21X1H7L _428_ ( + .A0(_224_), + .A1(_231_), + .B0(_232_), + .Y(_019_) + ); + AOI22X1P4H7L _429_ ( + .A0(_107_), + .A1(\req_msg[11] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_11_ ), + .Y(_233_) + ); + NAND2X0P5H7L _430_ ( + .A(\dpath.a_lt_b$in1_11_ ), + .B(_229_), + .Y(_234_) + ); + OAI21X1H7L _431_ ( + .A0(_224_), + .A1(_233_), + .B0(_234_), + .Y(_020_) + ); + BUFX1P4H7L _432_ ( + .A(_106_), + .Y(_235_) + ); + AOI22X1P4H7L _433_ ( + .A0(_235_), + .A1(\req_msg[12] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_12_ ), + .Y(_236_) + ); + NAND2X0P5H7R _434_ ( + .A(\dpath.a_lt_b$in1_12_ ), + .B(_229_), + .Y(_237_) + ); + OAI21X1H7L _435_ ( + .A0(_224_), + .A1(_236_), + .B0(_237_), + .Y(_021_) + ); + AOI22X1P4H7L _436_ ( + .A0(_235_), + .A1(\req_msg[13] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_13_ ), + .Y(_238_) + ); + NAND2X0P5H7R _437_ ( + .A(\dpath.a_lt_b$in1_13_ ), + .B(_229_), + .Y(_239_) + ); + OAI21X1H7L _438_ ( + .A0(_224_), + .A1(_238_), + .B0(_239_), + .Y(_022_) + ); + AOI22X1P4H7L _439_ ( + .A0(_235_), + .A1(\req_msg[14] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_14_ ), + .Y(_240_) + ); + NAND2X0P5H7R _440_ ( + .A(\dpath.a_lt_b$in1_14_ ), + .B(_229_), + .Y(_241_) + ); + OAI21X1H7L _441_ ( + .A0(_224_), + .A1(_240_), + .B0(_241_), + .Y(_023_) + ); + AOAI211X0P5H7R _442_ ( + .A0(\dpath.a_lt_b$in0_15_ ), + .A1(_099_), + .B0(_035_), + .C0(\dpath.a_lt_b$in1_15_ ), + .Y(_242_) + ); + OAI2BB1X0P5H7R _443_ ( + .A0N(\req_msg[15] ), + .A1N(req_rdy), + .B0(_242_), + .Y(_024_) + ); + AOI22X1P4H7L _444_ ( + .A0(_235_), + .A1(\req_msg[1] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_1_ ), + .Y(_243_) + ); + NAND2X0P5H7R _445_ ( + .A(\dpath.a_lt_b$in1_1_ ), + .B(_229_), + .Y(_244_) + ); + OAI21X1H7L _446_ ( + .A0(_224_), + .A1(_243_), + .B0(_244_), + .Y(_025_) + ); + AOI22X1P4H7L _447_ ( + .A0(_235_), + .A1(\req_msg[2] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_2_ ), + .Y(_245_) + ); + NAND2X0P5H7R _448_ ( + .A(\dpath.a_lt_b$in1_2_ ), + .B(_229_), + .Y(_246_) + ); + OAI21X1H7L _449_ ( + .A0(_224_), + .A1(_245_), + .B0(_246_), + .Y(_026_) + ); + AOI22X1P4H7L _450_ ( + .A0(_235_), + .A1(\req_msg[3] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_3_ ), + .Y(_247_) + ); + NAND2X0P5H7L _451_ ( + .A(\dpath.a_lt_b$in1_3_ ), + .B(_229_), + .Y(_248_) + ); + OAI21X1H7L _452_ ( + .A0(_224_), + .A1(_247_), + .B0(_248_), + .Y(_027_) + ); + AOI22X1P4H7L _453_ ( + .A0(_235_), + .A1(\req_msg[4] ), + .B0(_226_), + .B1(\dpath.a_lt_b$in0_4_ ), + .Y(_249_) + ); + NAND2X0P5H7L _454_ ( + .A(\dpath.a_lt_b$in1_4_ ), + .B(_229_), + .Y(_250_) + ); + OAI21X1H7L _455_ ( + .A0(_224_), + .A1(_249_), + .B0(_250_), + .Y(_028_) + ); + AOI22X1P4H7L _456_ ( + .A0(_235_), + .A1(\req_msg[5] ), + .B0(_225_), + .B1(\dpath.a_lt_b$in0_5_ ), + .Y(_251_) + ); + NAND2X0P5H7R _457_ ( + .A(\dpath.a_lt_b$in1_5_ ), + .B(_228_), + .Y(_252_) + ); + OAI21X0P5H7L _458_ ( + .A0(_170_), + .A1(_251_), + .B0(_252_), + .Y(_029_) + ); + AOI22X1P4H7L _459_ ( + .A0(_235_), + .A1(\req_msg[6] ), + .B0(_225_), + .B1(\dpath.a_lt_b$in0_6_ ), + .Y(_253_) + ); + NAND2X0P5H7R _460_ ( + .A(\dpath.a_lt_b$in1_6_ ), + .B(_228_), + .Y(_254_) + ); + OAI21X0P5H7L _461_ ( + .A0(_170_), + .A1(_253_), + .B0(_254_), + .Y(_030_) + ); + AOI22X1P4H7L _462_ ( + .A0(_235_), + .A1(\req_msg[7] ), + .B0(_225_), + .B1(\dpath.a_lt_b$in0_7_ ), + .Y(_255_) + ); + NAND2X0P5H7R _463_ ( + .A(\dpath.a_lt_b$in1_7_ ), + .B(_228_), + .Y(_256_) + ); + OAI21X0P5H7L _464_ ( + .A0(_170_), + .A1(_255_), + .B0(_256_), + .Y(_031_) + ); + AOI22X1H7L _465_ ( + .A0(_106_), + .A1(\req_msg[8] ), + .B0(_225_), + .B1(\dpath.a_lt_b$in0_8_ ), + .Y(_257_) + ); + NAND2X0P5H7R _466_ ( + .A(\dpath.a_lt_b$in1_8_ ), + .B(_228_), + .Y(_258_) + ); + OAI21X0P5H7L _467_ ( + .A0(_170_), + .A1(_257_), + .B0(_258_), + .Y(_032_) + ); + AOI22X1H7L _468_ ( + .A0(_106_), + .A1(\req_msg[9] ), + .B0(_225_), + .B1(\dpath.a_lt_b$in0_9_ ), + .Y(_259_) + ); + NAND2X0P5H7R _469_ ( + .A(\dpath.a_lt_b$in1_9_ ), + .B(_228_), + .Y(_260_) + ); + OAI21X0P5H7L _470_ ( + .A0(_170_), + .A1(_259_), + .B0(_260_), + .Y(_033_) + ); + XOR2X0P5H7R _471_ ( + .A(\dpath.a_lt_b$in0_0_ ), + .B(\dpath.a_lt_b$in1_0_ ), + .Y(\resp_msg[0] ) + ); + AOI21X1P4H7L _472_ ( + .A0(_068_), + .A1(_212_), + .B0(_069_), + .Y(_261_) + ); + OAI21X0P5H7R _473_ ( + .A0(_073_), + .A1(_261_), + .B0(_072_), + .Y(_262_) + ); + XNOR2X0P5H7L _474_ ( + .A(_067_), + .B(_262_), + .Y(\resp_msg[10] ) + ); + OAI31X0P5H7R _475_ ( + .A0(_040_), + .A1(_120_), + .A2(_121_), + .B0(_130_), + .Y(_263_) + ); + XNOR2X0P5H7R _476_ ( + .A(_071_), + .B(_263_), + .Y(\resp_msg[11] ) + ); + INVX0P5H7R _477_ ( + .A(\dpath.a_lt_b$in1_12_ ), + .Y(_264_) + ); + NAND3X0P5H7R _478_ ( + .A(_264_), + .B(_137_), + .C(_138_), + .Y(_265_) + ); + AOI21X0P5H7R _479_ ( + .A0(_137_), + .A1(_138_), + .B0(_264_), + .Y(_266_) + ); + NOR2BX1H7L _480_ ( + .AN(_265_), + .B(_266_), + .Z(\resp_msg[12] ) + ); + OAI2BB1X1P4H7L _481_ ( + .A0N(_143_), + .A1N(_151_), + .B0(_078_), + .Y(_267_) + ); + NOR2BX1H7R _482_ ( + .AN(_152_), + .B(_153_), + .Z(_268_) + ); + XOR2X0P5H7R _483_ ( + .A(_267_), + .B(_268_), + .Y(\resp_msg[13] ) + ); + OAI21X0P5H7R _484_ ( + .A0(_151_), + .A1(_156_), + .B0(_159_), + .Y(_269_) + ); + XOR2X0P5H7L _485_ ( + .A(\dpath.a_lt_b$in1_14_ ), + .B(_269_), + .Y(\resp_msg[14] ) + ); + MUX2X1P4H7L _486_ ( + .A(_083_), + .B(_088_), + .S0(_151_), + .Y(_270_) + ); + NAND2BX0P5H7R _487_ ( + .AN(_077_), + .B(_089_), + .Y(_271_) + ); + XNOR2X0P7H7L _488_ ( + .A(_270_), + .B(_271_), + .Y(\resp_msg[15] ) + ); + XNOR2X0P5H7R _489_ ( + .A(_212_), + .B(_070_), + .Y(\resp_msg[8] ) + ); + XOR2X0P5H7R _490_ ( + .A(_074_), + .B(_261_), + .Y(\resp_msg[9] ) + ); + NOR2X0P5H7R _491_ ( + .A(_099_), + .B(_103_), + .Y(resp_val) + ); + BUFX1P4H7L _492_ ( + .A(\ctrl.curr_state__0_0_ ), + .Y(_034_) + ); + BUFX1P4H7L _493_ ( + .A(\ctrl.curr_state__0_1_ ), + .Y(_035_) + ); + NOR2X0P5H7R _494_ ( + .A(_034_), + .B(_035_), + .Y(req_rdy) + ); + AOI2XB1X1H7L _495_ ( + .A0(\dpath.a_lt_b$in0_8_ ), + .A1N(\dpath.a_lt_b$in1_8_ ), + .B0(\dpath.a_lt_b$in0_9_ ), + .Y(_036_) + ); + NAND3BX0P5H7R _496_ ( + .AN(\dpath.a_lt_b$in1_8_ ), + .B(\dpath.a_lt_b$in0_8_ ), + .C(\dpath.a_lt_b$in0_9_ ), + .Y(_037_) + ); + NOR2BX1H7R _497_ ( + .AN(\dpath.a_lt_b$in1_10_ ), + .B(\dpath.a_lt_b$in0_10_ ), + .Z(_038_) + ); + OAOI211X0P7H7L _498_ ( + .A0(\dpath.a_lt_b$in1_9_ ), + .A1(_036_), + .B0(_037_), + .C0(_038_), + .Y(_039_) + ); + NOR2BX1H7L _499_ ( + .AN(\dpath.a_lt_b$in0_10_ ), + .B(\dpath.a_lt_b$in1_10_ ), + .Z(_040_) + ); + NAND2BX1H7L _500_ ( + .AN(\dpath.a_lt_b$in0_11_ ), + .B(\dpath.a_lt_b$in1_11_ ), + .Y(_041_) + ); + NOR2BX1H7R _501_ ( + .AN(\dpath.a_lt_b$in0_11_ ), + .B(\dpath.a_lt_b$in1_11_ ), + .Z(_042_) + ); + OAO211X2H7L _502_ ( + .A0(_039_), + .A1(_040_), + .B0(_041_), + .C0(_042_), + .Y(_043_) + ); + NAND3BX4H7L _503_ ( + .AN(\dpath.a_lt_b$in0_0_ ), + .B(\dpath.a_lt_b$in1_0_ ), + .C(\dpath.a_lt_b$in1_1_ ), + .Y(_044_) + ); + AOI2XB1X4H7L _504_ ( + .A0(\dpath.a_lt_b$in1_0_ ), + .A1N(\dpath.a_lt_b$in0_0_ ), + .B0(\dpath.a_lt_b$in1_1_ ), + .Y(_045_) + ); + NAND2BX1P4H7R _505_ ( + .AN(\dpath.a_lt_b$in0_2_ ), + .B(\dpath.a_lt_b$in1_2_ ), + .Y(_046_) + ); + AOAI211X4H7L _506_ ( + .A0(\dpath.a_lt_b$in0_1_ ), + .A1(_044_), + .B0(_045_), + .C0(_046_), + .Y(_047_) + ); + NAND2BX0P5H7L _507_ ( + .AN(\dpath.a_lt_b$in1_2_ ), + .B(\dpath.a_lt_b$in0_2_ ), + .Y(_048_) + ); + NOR2BX1P4H7L _508_ ( + .AN(\dpath.a_lt_b$in1_3_ ), + .B(\dpath.a_lt_b$in0_3_ ), + .Z(_049_) + ); + NAND2BX0P5H7R _509_ ( + .AN(\dpath.a_lt_b$in1_3_ ), + .B(\dpath.a_lt_b$in0_3_ ), + .Y(_050_) + ); + AOA211X4H7L _510_ ( + .A0(_047_), + .A1(_048_), + .B0(_049_), + .C0(_050_), + .Y(_051_) + ); + NOR2BX1H7R _511_ ( + .AN(\dpath.a_lt_b$in1_5_ ), + .B(\dpath.a_lt_b$in0_5_ ), + .Z(_052_) + ); + NOR2BX1H7R _512_ ( + .AN(\dpath.a_lt_b$in0_5_ ), + .B(\dpath.a_lt_b$in1_5_ ), + .Z(_053_) + ); + NOR2X1P4H7L _513_ ( + .A(_052_), + .B(_053_), + .Y(_054_) + ); + NAND2BX1P4H7L _514_ ( + .AN(\dpath.a_lt_b$in0_7_ ), + .B(\dpath.a_lt_b$in1_7_ ), + .Y(_055_) + ); + NOR2BX1H7L _515_ ( + .AN(\dpath.a_lt_b$in0_7_ ), + .B(\dpath.a_lt_b$in1_7_ ), + .Z(_056_) + ); + NOR2BX3H7L _516_ ( + .AN(_055_), + .B(_056_), + .Z(_057_) + ); + NOR2BX4H7R _517_ ( + .AN(\dpath.a_lt_b$in1_6_ ), + .B(\dpath.a_lt_b$in0_6_ ), + .Z(_058_) + ); + NOR2BX2H7L _518_ ( + .AN(\dpath.a_lt_b$in0_6_ ), + .B(\dpath.a_lt_b$in1_6_ ), + .Z(_059_) + ); + XOR2X3H7L _519_ ( + .A(\dpath.a_lt_b$in0_4_ ), + .B(\dpath.a_lt_b$in1_4_ ), + .Y(_060_) + ); + NOR3X6H7R _520_ ( + .A(_058_), + .B(_059_), + .C(_060_), + .Y(_061_) + ); + NAND3X6H7L _521_ ( + .A(_054_), + .B(_057_), + .C(_061_), + .Y(_062_) + ); + AOI2XB1X1H7L _522_ ( + .A0(\dpath.a_lt_b$in0_4_ ), + .A1N(\dpath.a_lt_b$in1_4_ ), + .B0(\dpath.a_lt_b$in0_5_ ), + .Y(_063_) + ); + NAND3BX0P7H7R _523_ ( + .AN(\dpath.a_lt_b$in1_4_ ), + .B(\dpath.a_lt_b$in0_4_ ), + .C(\dpath.a_lt_b$in0_5_ ), + .Y(_064_) + ); + OAOI211X2H7L _524_ ( + .A0(\dpath.a_lt_b$in1_5_ ), + .A1(_063_), + .B0(_064_), + .C0(_058_), + .Y(_065_) + ); + OAOI211X3H7L _525_ ( + .A0(_065_), + .A1(_059_), + .B0(_055_), + .C0(_056_), + .Y(_066_) + ); + NOR2X0P7H7L _526_ ( + .A(_038_), + .B(_040_), + .Y(_067_) + ); + NAND2BX6H7L _527_ ( + .AN(\dpath.a_lt_b$in1_8_ ), + .B(\dpath.a_lt_b$in0_8_ ), + .Y(_068_) + ); + NOR2BX1P4H7L _528_ ( + .AN(\dpath.a_lt_b$in1_8_ ), + .B(\dpath.a_lt_b$in0_8_ ), + .Z(_069_) + ); + NOR2BX1H7R _529_ ( + .AN(_068_), + .B(_069_), + .Z(_070_) + ); + NOR2BX1H7L _530_ ( + .AN(_041_), + .B(_042_), + .Z(_071_) + ); + NAND2BX0P7H7R _531_ ( + .AN(\dpath.a_lt_b$in0_9_ ), + .B(\dpath.a_lt_b$in1_9_ ), + .Y(_072_) + ); + NOR2BX1H7R _532_ ( + .AN(\dpath.a_lt_b$in0_9_ ), + .B(\dpath.a_lt_b$in1_9_ ), + .Z(_073_) + ); + NOR2BX1P4H7L _533_ ( + .AN(_072_), + .B(_073_), + .Z(_074_) + ); + NAND4X2H7L _534_ ( + .A(_067_), + .B(_070_), + .C(_071_), + .D(_074_), + .Y(_075_) + ); + OAOI211X4H7L _535_ ( + .A0(_051_), + .A1(_062_), + .B0(_066_), + .C0(_075_), + .Y(_076_) + ); + NOR2BX1P4H7L _536_ ( + .AN(\dpath.a_lt_b$in0_15_ ), + .B(\dpath.a_lt_b$in1_15_ ), + .Z(_077_) + ); + NAND2BX6H7L _537_ ( + .AN(\dpath.a_lt_b$in1_12_ ), + .B(\dpath.a_lt_b$in0_12_ ), + .Y(_078_) + ); + OAI2BB1X1H7L _538_ ( + .A0N(\dpath.a_lt_b$in1_13_ ), + .A1N(_078_), + .B0(\dpath.a_lt_b$in0_13_ ), + .Y(_079_) + ); + OR2X0P7H7L _539_ ( + .A(\dpath.a_lt_b$in1_13_ ), + .B(_078_), + .Y(_080_) + ); + NOR2BX1H7R _540_ ( + .AN(\dpath.a_lt_b$in1_14_ ), + .B(\dpath.a_lt_b$in0_14_ ), + .Z(_081_) + ); + NAND2BX0P5H7R _541_ ( + .AN(\dpath.a_lt_b$in1_14_ ), + .B(\dpath.a_lt_b$in0_14_ ), + .Y(_082_) + ); + AOAI211X1P4H7L _542_ ( + .A0(_079_), + .A1(_080_), + .B0(_081_), + .C0(_082_), + .Y(_083_) + ); + OR2X1P4H7R _543_ ( + .A(_077_), + .B(_083_), + .Y(_084_) + ); + NOR2BX4H7L _544_ ( + .AN(\dpath.a_lt_b$in1_12_ ), + .B(\dpath.a_lt_b$in0_12_ ), + .Z(_085_) + ); + OAI2BB1X1H7L _545_ ( + .A0N(\dpath.a_lt_b$in1_13_ ), + .A1N(_085_), + .B0(\dpath.a_lt_b$in0_13_ ), + .Y(_086_) + ); + OR2X0P5H7L _546_ ( + .A(\dpath.a_lt_b$in1_13_ ), + .B(_085_), + .Y(_087_) + ); + AOAI211X0P5H7L _547_ ( + .A0(_086_), + .A1(_087_), + .B0(_081_), + .C0(_082_), + .Y(_088_) + ); + NAND2BX0P5H7R _548_ ( + .AN(\dpath.a_lt_b$in0_15_ ), + .B(\dpath.a_lt_b$in1_15_ ), + .Y(_089_) + ); + OA21X1H7L _549_ ( + .A0(_077_), + .A1(_088_), + .B0(_089_), + .Y(_090_) + ); + OAI31X4H7L _550_ ( + .A0(_043_), + .A1(_076_), + .A2(_084_), + .B0(_090_), + .Y(_091_) + ); + BUFX16H7L _551_ ( + .A(_091_), + .Y(_092_) + ); + BUFX12H7L _552_ ( + .A(_092_), + .Y(_093_) + ); + NOR4X0P5H7R _553_ ( + .A(\dpath.a_lt_b$in1_3_ ), + .B(\dpath.a_lt_b$in1_2_ ), + .C(\dpath.a_lt_b$in1_1_ ), + .D(\dpath.a_lt_b$in1_0_ ), + .Y(_094_) + ); + NOR4X0P5H7R _554_ ( + .A(\dpath.a_lt_b$in1_15_ ), + .B(\dpath.a_lt_b$in1_6_ ), + .C(\dpath.a_lt_b$in1_5_ ), + .D(\dpath.a_lt_b$in1_4_ ), + .Y(_095_) + ); + NOR4X0P5H7R _555_ ( + .A(\dpath.a_lt_b$in1_11_ ), + .B(\dpath.a_lt_b$in1_10_ ), + .C(\dpath.a_lt_b$in1_9_ ), + .D(\dpath.a_lt_b$in1_8_ ), + .Y(_096_) + ); + NOR4X0P5H7R _556_ ( + .A(\dpath.a_lt_b$in1_14_ ), + .B(\dpath.a_lt_b$in1_13_ ), + .C(\dpath.a_lt_b$in1_12_ ), + .D(\dpath.a_lt_b$in1_7_ ), + .Y(_097_) + ); + NAND4X0P5H7R _557_ ( + .A(_094_), + .B(_095_), + .C(_096_), + .D(_097_), + .Y(_098_) + ); + BUFX1P4H7L _558_ ( + .A(\ctrl.curr_state__0_0_ ), + .Y(_099_) + ); + OAI31X1P4H7L _559_ ( + .A0(_035_), + .A1(_093_), + .A2(_098_), + .B0(_099_), + .Y(_100_) + ); + NAND2X0P5H7R _560_ ( + .A(req_val), + .B(req_rdy), + .Y(_101_) + ); + AOI21X0P5H7L _561_ ( + .A0(_100_), + .A1(_101_), + .B0(reset), + .Y(_000_) + ); + DFFQX1H7R \ctrl.curr_state__0_0__reg_p ( + .CK(clk), + .D(_000_), + .Q(\ctrl.curr_state__0_0_ ) + ); + DFFQX1H7R \ctrl.curr_state__0_1__reg_p ( + .CK(clk), + .D(_001_), + .Q(\ctrl.curr_state__0_1_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_0__reg_p ( + .CK(clk), + .D(_002_), + .Q(\dpath.a_lt_b$in0_0_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_10__reg_p ( + .CK(clk), + .D(_003_), + .Q(\dpath.a_lt_b$in0_10_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_11__reg_p ( + .CK(clk), + .D(_004_), + .Q(\dpath.a_lt_b$in0_11_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_12__reg_p ( + .CK(clk), + .D(_005_), + .Q(\dpath.a_lt_b$in0_12_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_13__reg_p ( + .CK(clk), + .D(_006_), + .Q(\dpath.a_lt_b$in0_13_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_14__reg_p ( + .CK(clk), + .D(_007_), + .Q(\dpath.a_lt_b$in0_14_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_15__reg_p ( + .CK(clk), + .D(_008_), + .Q(\dpath.a_lt_b$in0_15_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_1__reg_p ( + .CK(clk), + .D(_009_), + .Q(\dpath.a_lt_b$in0_1_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_2__reg_p ( + .CK(clk), + .D(_010_), + .Q(\dpath.a_lt_b$in0_2_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_3__reg_p ( + .CK(clk), + .D(_011_), + .Q(\dpath.a_lt_b$in0_3_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_4__reg_p ( + .CK(clk), + .D(_012_), + .Q(\dpath.a_lt_b$in0_4_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_5__reg_p ( + .CK(clk), + .D(_013_), + .Q(\dpath.a_lt_b$in0_5_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_6__reg_p ( + .CK(clk), + .D(_014_), + .Q(\dpath.a_lt_b$in0_6_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_7__reg_p ( + .CK(clk), + .D(_015_), + .Q(\dpath.a_lt_b$in0_7_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_8__reg_p ( + .CK(clk), + .D(_016_), + .Q(\dpath.a_lt_b$in0_8_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in0_9__reg_p ( + .CK(clk), + .D(_017_), + .Q(\dpath.a_lt_b$in0_9_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_0__reg_p ( + .CK(clk), + .D(_018_), + .Q(\dpath.a_lt_b$in1_0_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_10__reg_p ( + .CK(clk), + .D(_019_), + .Q(\dpath.a_lt_b$in1_10_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_11__reg_p ( + .CK(clk), + .D(_020_), + .Q(\dpath.a_lt_b$in1_11_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_12__reg_p ( + .CK(clk), + .D(_021_), + .Q(\dpath.a_lt_b$in1_12_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_13__reg_p ( + .CK(clk), + .D(_022_), + .Q(\dpath.a_lt_b$in1_13_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_14__reg_p ( + .CK(clk), + .D(_023_), + .Q(\dpath.a_lt_b$in1_14_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_15__reg_p ( + .CK(clk), + .D(_024_), + .Q(\dpath.a_lt_b$in1_15_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_1__reg_p ( + .CK(clk), + .D(_025_), + .Q(\dpath.a_lt_b$in1_1_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_2__reg_p ( + .CK(clk), + .D(_026_), + .Q(\dpath.a_lt_b$in1_2_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_3__reg_p ( + .CK(clk), + .D(_027_), + .Q(\dpath.a_lt_b$in1_3_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_4__reg_p ( + .CK(clk), + .D(_028_), + .Q(\dpath.a_lt_b$in1_4_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_5__reg_p ( + .CK(clk), + .D(_029_), + .Q(\dpath.a_lt_b$in1_5_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_6__reg_p ( + .CK(clk), + .D(_030_), + .Q(\dpath.a_lt_b$in1_6_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_7__reg_p ( + .CK(clk), + .D(_031_), + .Q(\dpath.a_lt_b$in1_7_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_8__reg_p ( + .CK(clk), + .D(_032_), + .Q(\dpath.a_lt_b$in1_8_ ) + ); + DFFQX1H7R \dpath.a_lt_b$in1_9__reg_p ( + .CK(clk), + .D(_033_), + .Q(\dpath.a_lt_b$in1_9_ ) + ); +endmodule diff --git a/scripts/design/ics55_gcd/run_iEDA.sh b/scripts/design/ics55_gcd/run_iEDA.sh new file mode 100755 index 0000000000000000000000000000000000000000..463d42cf38f24bf11e8f1d8b19e88c0367463452 --- /dev/null +++ b/scripts/design/ics55_gcd/run_iEDA.sh @@ -0,0 +1,69 @@ +#!/bin/bash +set -e + +TOP_NAME="gcd" +CLK_PORT_NAME="clk" +echo "Running iEDA Netlist-to-GDS flow for design: $TOP_NAME (clock port: $CLK_PORT_NAME)" + +# Ensure PDK_DIR is provided in the environment (must be exported); abort if missing. +if [ -z "${PDK_DIR:-}" ]; then + echo "Error: PDK_DIR is not set. Please export PDK_DIR before running this script." + exit 1 +fi +export TECH_LEF="${PDK_DIR}/prtech/techLEF/N551P6M_ieda.lef" +export LEF_STDCELL="${PDK_DIR}/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/lef/ics55_LLSC_H7CR_ieda.lef \ +${PDK_DIR}/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/lef/ics55_LLSC_H7CL_ieda.lef" +export LIB_STDCELL="${PDK_DIR}/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/liberty/ics55_LLSC_H7CL_ss_rcworst_1p08_125_nldm.lib \ +${PDK_DIR}/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/liberty/ics55_LLSC_H7CR_ss_rcworst_1p08_125_nldm.lib" +export TAPCELL="FILLTAPH7R" +export TAP_DISTANCE=58 +export ENDCAP="FILLTAPH7R" + +export WORKSPACE=$(cd "$(dirname "$0")";pwd) + +# (fixed) iEDA setting +export RESULT_DIR=$WORKSPACE/result +export IEDA_CONFIG_DIR=$WORKSPACE/iEDA_config +export IEDA_TCL_SCRIPT_DIR=$WORKSPACE/script +export TCL_SCRIPT_DIR=$WORKSPACE/script +export DEF_DIR=$WORKSPACE/result +export SDC_FILE=$WORKSPACE/default.sdc + +export IEDA_BINARY="${IEDA_BINARY:-$WORKSPACE/../../../bin/iEDA}" + +if [ ! -x "$IEDA_BINARY" ]; then + echo "Warning: IEDA binary '$IEDA_BINARY' not found or not executable." +fi + +# Set configuration by design name +export TOP_NAME="$TOP_NAME" +export CLK_PORT_NAME="$CLK_PORT_NAME" +export NETLIST_FILE="$WORKSPACE/result/verilog/${TOP_NAME}_nl.v" +export SDC_FILE="$WORKSPACE/default.sdc" + +if [ ! -f "$NETLIST_FILE" ]; then + echo "Error: Netlist file '$NETLIST_FILE' does not exist." + exit 1 +fi + +export USE_FIXED_BBOX=False +export CORE_UTIL=0.5 +# export DIE_AREA="0.0 0.0 150 150" +# export CORE_AREA="20 20 130 130" + + +IEDA_TCL_SCRIPTS="iFP_script/run_iFP.tcl +iNO_script/run_iNO_fix_fanout.tcl +iPL_script/run_iPL.tcl +iCTS_script/run_iCTS.tcl +iPL_script/run_iPL_legalization.tcl +iRT_script/run_iRT.tcl +iPL_script/run_iPL_filler.tcl +DB_script/run_def_to_gds_text.tcl +" + +for SCRIPT in $IEDA_TCL_SCRIPTS; do + echo ">>> Running step: $STEP_NAME" + echo ">>> $ iEDA -script ${IEDA_TCL_SCRIPT_DIR}/${SCRIPT}" + $IEDA_BINARY -script "${IEDA_TCL_SCRIPT_DIR}/${SCRIPT}" +done diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lef.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lef.tcl new file mode 100755 index 0000000000000000000000000000000000000000..bb81fec95932ac0c3de294ec6571a3f3c7ade50f --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lef.tcl @@ -0,0 +1,5 @@ +#=========================================================== +## read tech lef and lef +#=========================================================== +tech_lef_init -path $TECH_LEF_PATH +lef_init -path $LEF_PATH diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lib.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lib.tcl new file mode 100755 index 0000000000000000000000000000000000000000..ae3aa64712e3707a56eb0d832f006cbc083bb6f3 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lib.tcl @@ -0,0 +1,4 @@ +#=========================================================== +## read lib +#=========================================================== +db_init -lib_path $LIB_PATH diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lib_drv.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_drv.tcl new file mode 100755 index 0000000000000000000000000000000000000000..3d204c04fc2a869084b0425d8dfd75a87b8ebb12 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_drv.tcl @@ -0,0 +1,4 @@ +#=========================================================== +## read lib +#=========================================================== +db_init -lib_path $LIB_PATH_DRV diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lib_fixfanout.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_fixfanout.tcl new file mode 100755 index 0000000000000000000000000000000000000000..c87a525c920775c2f0815efa046d8a5c4d0f99e8 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_fixfanout.tcl @@ -0,0 +1,4 @@ +#=========================================================== +## read lib +#=========================================================== +db_init -lib_path $LIB_PATH_FIXFANOUT diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lib_hold.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_hold.tcl new file mode 100755 index 0000000000000000000000000000000000000000..2ef1e0234fe814df62e58ef255c7c086a6458f3c --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_hold.tcl @@ -0,0 +1,4 @@ +#=========================================================== +## read lib +#=========================================================== +db_init -lib_path $LIB_PATH_HOLD diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_lib_setup.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_setup.tcl new file mode 100755 index 0000000000000000000000000000000000000000..d68cde13e03991b7663ae9c5c2aa054ee6300878 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_lib_setup.tcl @@ -0,0 +1,4 @@ +#=========================================================== +## read lib +#=========================================================== +db_init -lib_path $LIB_PATH_SETUP diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_sdc.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_sdc.tcl new file mode 100755 index 0000000000000000000000000000000000000000..ab2c19b2f3a9ecd37e949b1386bd540e44c0ead0 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_sdc.tcl @@ -0,0 +1,6 @@ +#=========================================================== +## read sdc +#=========================================================== +if {[info exists ::env(SDC_FILE)] && $SDC_FILE ne ""} { + db_init -sdc_path $SDC_FILE +} diff --git a/scripts/design/ics55_gcd/script/DB_script/db_init_spef.tcl b/scripts/design/ics55_gcd/script/DB_script/db_init_spef.tcl new file mode 100755 index 0000000000000000000000000000000000000000..5d3ca46eb6a5953c6a63fbc9d8d56ca4c372bd98 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_init_spef.tcl @@ -0,0 +1,6 @@ +#=========================================================== +## read spef +#=========================================================== +db_init -spef_path $SPEF_PATH + + diff --git a/scripts/design/ics55_gcd/script/DB_script/db_path_setting.tcl b/scripts/design/ics55_gcd/script/DB_script/db_path_setting.tcl new file mode 100755 index 0000000000000000000000000000000000000000..c97bb9d3b37bd6ecc196a583c2d52fbd8b853786 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/db_path_setting.tcl @@ -0,0 +1,42 @@ +if {[info exists ::env(SDC_FILE)]} { + set SDC_FILE "$::env(SDC_FILE)" +} + +if {[info exists ::env(SPEF_FILE)]} { + set SPEF_PATH $::env(SPEF_FILE) +} + +#=========================================================== +## set tech lef path +#=========================================================== +set TECH_LEF_PATH $::env(TECH_LEF) + +#=========================================================== +## set lef path +#=========================================================== +set LEF_PATH $::env(LEF_STDCELL) + +#=========================================================== +## set common lib path +#=========================================================== +set LIB_PATH $::env(LIB_STDCELL) + +#=========================================================== +## set fix fanout lib path +#=========================================================== +set LIB_PATH_FIXFANOUT ${LIB_PATH} + +#=========================================================== +## set drv lib path +#=========================================================== +set LIB_PATH_DRV ${LIB_PATH} + +#=========================================================== +## set hold lib path +#=========================================================== +set LIB_PATH_HOLD ${LIB_PATH} + +#=========================================================== +## set setup lib path +#=========================================================== +set LIB_PATH_SETUP ${LIB_PATH} diff --git a/scripts/design/ics55_gcd/script/DB_script/env_var_setup.tcl b/scripts/design/ics55_gcd/script/DB_script/env_var_setup.tcl new file mode 100644 index 0000000000000000000000000000000000000000..0e68bc4e106a8ea22e593be6ad6c7a63b15ac038 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/env_var_setup.tcl @@ -0,0 +1,22 @@ + +set env_vars { + NUM_THREADS + RESULT_DIR + INPUT_DEF + OUTPUT_DEF + OUTPUT_VERILOG + DESIGN_STAT_TEXT + DESIGN_STAT_JSON + TOOL_METRICS_JSON + TOOL_REPORT_DIR + SPEF_PATH + SDC_FILE + GDS_FILE + LAYOUT_JSON_FILE +} + +foreach var $env_vars { + if { [info exists ::env($var)] } { + set $var $::env($var) + } +} diff --git a/scripts/design/ics55_gcd/script/DB_script/run_db.tcl b/scripts/design/ics55_gcd/script/DB_script/run_db.tcl new file mode 100755 index 0000000000000000000000000000000000000000..7f96cb6cf282c826aad2577314a753672e792a19 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_db.tcl @@ -0,0 +1,36 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iRT_result.def + +#=========================================================== +## save def & verilog +#=========================================================== +def_save -path $::env(RESULT_DIR)/data_out.def +netlist_save -path $::env(RESULT_DIR)/data_out.v + +#=========================================================== +## Exit +#=========================================================== +flow_exit + diff --git a/scripts/design/ics55_gcd/script/DB_script/run_db_checknet.tcl b/scripts/design/ics55_gcd/script/DB_script/run_db_checknet.tcl new file mode 100755 index 0000000000000000000000000000000000000000..75c84d2d902216f367d52c13e73492efdb5f487e --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_db_checknet.tcl @@ -0,0 +1,33 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iRT_result.def + +#check_net -name xxx +check_all_net + +#=========================================================== +## Exit +#=========================================================== +flow_exit + diff --git a/scripts/design/ics55_gcd/script/DB_script/run_db_report_evl.tcl b/scripts/design/ics55_gcd/script/DB_script/run_db_report_evl.tcl new file mode 100644 index 0000000000000000000000000000000000000000..2bbc65df4a5f6429b36f74e08fd0872f84b70735 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_db_report_evl.tcl @@ -0,0 +1,32 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/asic_top_1220.def + +report_wirelength -path "$::env(RESULT_DIR)/report/wirelength.rpt" +report_congestion -path "$::env(RESULT_DIR)/report/congestion.rpt" + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/DB_script/run_def_to_gds_text.tcl b/scripts/design/ics55_gcd/script/DB_script/run_def_to_gds_text.tcl new file mode 100755 index 0000000000000000000000000000000000000000..343968dc8e18ba8c42a6332618b8e91205494444 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_def_to_gds_text.tcl @@ -0,0 +1,55 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" +# override by "$::env(RESULT_DIR)" if exist + +# input variables +set INPUT_DEF "$RESULT_DIR/iPL_filler_result.def" + +# output files +set GDS_FILE "$RESULT_DIR/final_design.gds2" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## save gds +#=========================================================== +gds_save -path $GDS_FILE + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/DB_script/run_def_to_json_text.tcl b/scripts/design/ics55_gcd/script/DB_script/run_def_to_json_text.tcl new file mode 100755 index 0000000000000000000000000000000000000000..0bb4a862f7ec4a5a1506ea11b3d3f7fee542a7ec --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_def_to_json_text.tcl @@ -0,0 +1,57 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" +# override by "$::env(RESULT_DIR)" if exist + +# input variables +set INPUT_DEF "$RESULT_DIR/iPL_filler_result.def" + +# output files +set LAYOUT_JSON_FILE "$RESULT_DIR/final_design.json" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## save json +## Full layer information instance:(-discard li/mcon/nwell/pwell/met/via) +## use (-discard null) to choose all layer +#=========================================================== +json_save -path $LAYOUT_JSON_FILE -discard null + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/DB_script/run_def_to_verilog.tcl b/scripts/design/ics55_gcd/script/DB_script/run_def_to_verilog.tcl new file mode 100755 index 0000000000000000000000000000000000000000..c768f5d8e28d27f1f1a38635097790b1e199e44f --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_def_to_verilog.tcl @@ -0,0 +1,34 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $RESULT_DIR/iPL_result.def + +#=========================================================== +## save verilog +#=========================================================== +netlist_save -path $RESULT_DIR/verilog.v -exclude_cell_names {} + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/DB_script/run_feature_summary.tcl b/scripts/design/ics55_gcd/script/DB_script/run_feature_summary.tcl new file mode 100755 index 0000000000000000000000000000000000000000..874baa31f8a1b91ba7d47d1158a8d089fd3c211e --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_feature_summary.tcl @@ -0,0 +1,35 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iRT_result.def + +#=========================================================== +## save def & verilog +#=========================================================== +feature_summary -path $::env(RESULT_DIR)/feature/summary_irt.json -step route + +#=========================================================== +## Exit +#=========================================================== +flow_exit + diff --git a/scripts/design/ics55_gcd/script/DB_script/run_netlist_to_def.tcl b/scripts/design/ics55_gcd/script/DB_script/run_netlist_to_def.tcl new file mode 100755 index 0000000000000000000000000000000000000000..c2afb13d0f2467ade0f68dd80291691a2f53e230 --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_netlist_to_def.tcl @@ -0,0 +1,39 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read verilog +#=========================================================== +verilog_init -path $RESULT_DIR/verilog/gcd.v -top gcd + +#=========================================================== +## save def +#=========================================================== +def_save -path $RESULT_DIR/netlist_result.def + +#=========================================================== +## save verilog +#=========================================================== +netlist_save -path $RESULT_DIR/netlist_result.v -exclude_cell_names {} + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/DB_script/run_read_verilog.tcl b/scripts/design/ics55_gcd/script/DB_script/run_read_verilog.tcl new file mode 100755 index 0000000000000000000000000000000000000000..535149170c4534244253b5d0fa6e308368f2479e --- /dev/null +++ b/scripts/design/ics55_gcd/script/DB_script/run_read_verilog.tcl @@ -0,0 +1,36 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read verilog +#=========================================================== +verilog_init -path $::env(RESULT_DIR)/iRT_result.v -top gcd + +#=========================================================== +## save def +#=========================================================== +def_save -path $::env(RESULT_DIR)/data_out.def +#netlist_save -path $::env(RESULT_DIR)/iRT_result.v + +#=========================================================== +## Exit +#=========================================================== +flow_exit + diff --git a/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS.tcl b/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS.tcl new file mode 100755 index 0000000000000000000000000000000000000000..fe50cd0e49f90f93c046eb7f48a635bd4ffa5e7c --- /dev/null +++ b/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS.tcl @@ -0,0 +1,92 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# input files +set INPUT_DEF "$RESULT_DIR/iPL_result.def" + +# output files +set TOOL_REPORT_DIR "$RESULT_DIR/cts" +set OUTPUT_DEF "$RESULT_DIR/iCTS_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iCTS_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/cts_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/cts_stat.json" +set TOOL_METRICS_JSON "$RESULT_DIR/metric/iCTS_metrics.json" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## run CTS +#=========================================================== +run_cts -config $IEDA_CONFIG_DIR/cts_default_config.json -work_dir $TOOL_REPORT_DIR + +#=========================================================== +## def & netlist +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +report_db -path $DESIGN_STAT_TEXT +feature_summary -path $DESIGN_STAT_JSON -step CTS + +feature_tool -path $TOOL_METRICS_JSON -step CTS + +#=========================================================== +## report CTS +#=========================================================== +cts_report -path $RESULT_DIR/cts + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS_STA.tcl b/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS_STA.tcl new file mode 100755 index 0000000000000000000000000000000000000000..ea23bd11457560d11338546d1414b54b12909efb --- /dev/null +++ b/scripts/design/ics55_gcd/script/iCTS_script/run_iCTS_STA.tcl @@ -0,0 +1,45 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iCTS_result.def + +#=========================================================== +## run STA +#=========================================================== + +run_sta -output $::env(RESULT_DIR)/cts/sta/ + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iFP_script/module/add_stripe.tcl b/scripts/design/ics55_gcd/script/iFP_script/module/add_stripe.tcl new file mode 100755 index 0000000000000000000000000000000000000000..aef92f8f968bfc015f81cde09d191f9f9fb485a5 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iFP_script/module/add_stripe.tcl @@ -0,0 +1,6 @@ +create_grid -layer_name "MET1" -net_name_power VDD -net_name_ground VSS -width 0.16 -offset 0 +create_stripe -layer_name "MET4" -net_name_power VDD -net_name_ground VSS -width 1 -pitch 16 -offset 0.5 +create_stripe -layer_name "MET5" -net_name_power VDD -net_name_ground VSS -width 1 -pitch 16 -offset 0.5 + +connect_two_layer -layers "MET1 MET4" +connect_two_layer -layers "MET4 MET5" diff --git a/scripts/design/ics55_gcd/script/iFP_script/module/create_tracks.tcl b/scripts/design/ics55_gcd/script/iFP_script/module/create_tracks.tcl new file mode 100755 index 0000000000000000000000000000000000000000..59c76a254d63bf8ff5a15b6eb7521a20cd2d6526 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iFP_script/module/create_tracks.tcl @@ -0,0 +1,8 @@ +# ics55 +gern_track -layer MET1 -x_start 0 -x_step 200 -y_start 0 -y_step 200 +gern_track -layer MET2 -x_start 0 -x_step 200 -y_start 0 -y_step 200 +gern_track -layer MET3 -x_start 0 -x_step 200 -y_start 0 -y_step 200 +gern_track -layer MET4 -x_start 0 -x_step 200 -y_start 0 -y_step 200 +gern_track -layer MET5 -x_start 0 -x_step 200 -y_start 0 -y_step 200 +gern_track -layer T4M2 -x_start 0 -x_step 800 -y_start 0 -y_step 800 +gern_track -layer RDL -x_start 0 -x_step 5000 -y_start 0 -y_step 5000 \ No newline at end of file diff --git a/scripts/design/ics55_gcd/script/iFP_script/module/global_net.tcl b/scripts/design/ics55_gcd/script/iFP_script/module/global_net.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1f0866c3b46efe354e8d033feaa3556beee70739 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iFP_script/module/global_net.tcl @@ -0,0 +1,14 @@ +add_pdn_io -net_name VDD -direction INOUT -is_power 1 +add_pdn_io -net_name VDDIO -direction INOUT -is_power 1 +add_pdn_io -net_name VSS -direction INOUT -is_power 0 +add_pdn_io -net_name VSSIO -direction INOUT -is_power 0 + +global_net_connect -net_name VDD -instance_pin_name VDD1 -is_power 1 +global_net_connect -net_name VDD -instance_pin_name VDD -is_power 1 +global_net_connect -net_name VDD -instance_pin_name VNW -is_power 1 +global_net_connect -net_name VSS -instance_pin_name VSS1 -is_power 0 +global_net_connect -net_name VSS -instance_pin_name VSS -is_power 0 +global_net_connect -net_name VSS -instance_pin_name VPW -is_power 0 +global_net_connect -net_name VDDIO -instance_pin_name VDDIO -is_power 1 +global_net_connect -net_name VSSIO -instance_pin_name VSSIO -is_power 0 + diff --git a/scripts/design/ics55_gcd/script/iFP_script/module/set_clocknet.tcl b/scripts/design/ics55_gcd/script/iFP_script/module/set_clocknet.tcl new file mode 100755 index 0000000000000000000000000000000000000000..268df98a42c9dbf7221c73348231320d1358c159 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iFP_script/module/set_clocknet.tcl @@ -0,0 +1 @@ +set_net -net_name clk -type CLOCK \ No newline at end of file diff --git a/scripts/design/ics55_gcd/script/iFP_script/run_iFP.tcl b/scripts/design/ics55_gcd/script/iFP_script/run_iFP.tcl new file mode 100755 index 0000000000000000000000000000000000000000..ac30772e7a835735eb1faa75773cfb666725753a --- /dev/null +++ b/scripts/design/ics55_gcd/script/iFP_script/run_iFP.tcl @@ -0,0 +1,136 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" +# override by "$::env(RESULT_DIR)" if exist + +# input files +set NETLIST_FILE "$::env(NETLIST_FILE)" + +# input variables +set TOP_NAME "$::env(TOP_NAME)" +set CLK_PORT_NAME "$::env(CLK_PORT_NAME)" +set USE_FIXED_BBOX "$::env(USE_FIXED_BBOX)" +puts "iFP: USE_FIXED_BBOX $USE_FIXED_BBOX" +if { $USE_FIXED_BBOX == "False" } { + set CORE_UTIL "$::env(CORE_UTIL)" +} else { + set DIE_BBOX "$::env(DIE_BBOX)" + set CORE_BBOX "$::env(CORE_BBOX)" +} +set TAPCELL "$::env(TAPCELL)" +set TAP_DISTANCE "$::env(TAP_DISTANCE)" +set ENDCAP "$::env(ENDCAP)" + +# output files +set OUTPUT_DEF "$RESULT_DIR/iFP_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iFP_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/floorplan_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/floorplan_stat.json" +# override by : +# "$::env(OUTPUT_DEF)" +# "$::env(DESIGN_STAT_TEXT)" +# "$::env(DESIGN_STAT_JSON)" +# if exist + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read verilog +#=========================================================== +verilog_init -path $NETLIST_FILE -top $TOP_NAME + +#=========================================================== +## init floorplan +#=========================================================== +set PLACE_SITE core7 +set IO_SITE core7 +set CORNER_SITE core7 + +if { $USE_FIXED_BBOX == "False" } { + puts "iFP: init with core_util $CORE_UTIL" + init_floorplan \ + -core_util $CORE_UTIL \ + -core_site $PLACE_SITE \ + -io_site $IO_SITE \ + -corner_site $CORNER_SITE +} else { + puts "iFP: init with fixed area die $DIE_BBOX, and core $CORE_BBOX" + init_floorplan \ + -die_area $DIE_BBOX \ + -core_area $CORE_BBOX \ + -core_site $PLACE_SITE \ + -io_site $IO_SITE \ + -corner_site $CORNER_SITE +} + +source $IEDA_TCL_SCRIPT_DIR/iFP_script/module/create_tracks.tcl + +#=========================================================== +## Place IO Port +#=========================================================== +# -sides "left right top bottom", src/interface/tcl/tcl_ifp/tcl_io.cpp:30 +auto_place_pins -layer MET3 -width 300 -height 600 + +#=========================================================== +## Tap Cell +#=========================================================== +tapcell \ + -tapcell $TAPCELL \ + -distance $TAP_DISTANCE \ + -endcap $ENDCAP + +#=========================================================== +## PDN +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/iFP_script/module/global_net.tcl +source $IEDA_TCL_SCRIPT_DIR/iFP_script/module/add_stripe.tcl + +#=========================================================== +## set clock net +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/iFP_script/module/set_clocknet.tcl + +#=========================================================== +## save def +#=========================================================== +def_save -path $OUTPUT_DEF +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +report_db -path $DESIGN_STAT_TEXT +feature_summary -step floorplan -path $DESIGN_STAT_JSON + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iNO_script/run_iNO_fix_fanout.tcl b/scripts/design/ics55_gcd/script/iNO_script/run_iNO_fix_fanout.tcl new file mode 100755 index 0000000000000000000000000000000000000000..59f62f65d302601850902d23c3c1749e4f7975f0 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iNO_script/run_iNO_fix_fanout.tcl @@ -0,0 +1,98 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# input variables +if { [info exists ::env(USE_VERILOG)] && [string tolower $::env(USE_VERILOG)] == "true" } { + set USE_VERILOG true + set TOP_NAME "$::env(TOP_NAME)" + set INPUT_VERILOG "$::env(INPUT_VERILOG)" +} else { + set USE_VERILOG false + set INPUT_DEF "$RESULT_DIR/iFP_result.def" +} + +# output files +set OUTPUT_DEF "$RESULT_DIR/iNO_fix_fanout_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iNO_fix_fanout_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/fix_fanout_db.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/fix_fanout_db.json" +# set TOOL_METRICS_JSON "$RESULT_DIR/metric/iNO_metrics.json" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read verilog/def +#=========================================================== +if { $USE_VERILOG } { + verilog_init -path $INPUT_VERILOG -top $TOP_NAME +} else { + def_init -path $INPUT_DEF +} + +#=========================================================== +## run TO to fix fanout +#=========================================================== +run_no_fixfanout -config $IEDA_CONFIG_DIR/no_default_config_fixfanout.json + +#=========================================================== +## save def +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary and metrics +#=========================================================== +report_db -path $DESIGN_STAT_TEXT +feature_summary -step fixFanout -path $DESIGN_STAT_JSON + +# Disable because the STA result is not correct +# feature_tool -step fixFanout -path $TOOL_METRICS_JSON + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iPL_script/run_iPL.tcl b/scripts/design/ics55_gcd/script/iPL_script/run_iPL.tcl new file mode 100755 index 0000000000000000000000000000000000000000..3584195a7f3f79b5973b89a04d45c015bb051e59 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iPL_script/run_iPL.tcl @@ -0,0 +1,88 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# input files +set INPUT_DEF "$RESULT_DIR/iNO_fix_fanout_result.def" + +# output files +set OUTPUT_DEF "$RESULT_DIR/iPL_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iPL_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/placement_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/placement_stat.json" +set TOOL_METRICS_JSON "$RESULT_DIR/metric/iPL_metrics.json" +set TOOL_REPORT_DIR "$RESULT_DIR/pl" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## run Placer +#=========================================================== +run_placer -config $IEDA_CONFIG_DIR/pl_default_config.json + +#=========================================================== +## save def +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report +#=========================================================== +# report_db -path $DESIGN_STAT_TEXT +# feature_summary -path $DESIGN_STAT_JSON -step place + +# feature_tool -path $TOOL_METRICS_JSON -step place +# feature_cong_map -dir $TOOL_REPORT_DIR -step place + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iPL_script/run_iPL_filler.tcl b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_filler.tcl new file mode 100755 index 0000000000000000000000000000000000000000..e2e11917d8b9f70db11615bdb79fae5d7ef5b7e8 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_filler.tcl @@ -0,0 +1,74 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# input files +set INPUT_DEF "$RESULT_DIR/iRT_result.def" + +# output files +set OUTPUT_DEF "$RESULT_DIR/iPL_filler_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iPL_filler_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/filler_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/filler_stat.json" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env setup +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## run Filler +#=========================================================== +run_filler -config $IEDA_CONFIG_DIR/pl_default_config.json + +#=========================================================== +## save def +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +report_db -path $DESIGN_STAT_TEXT +feature_summary -path $DESIGN_STAT_JSON -step filler + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iPL_script/run_iPL_gui.tcl b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_gui.tcl new file mode 100755 index 0000000000000000000000000000000000000000..a1af1812eb2d2509aaf7d33bf317c96a222a4474 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_gui.tcl @@ -0,0 +1,38 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +#def_init -path $::env(RESULT_DIR)/iTO_fix_fanout_result.def + +#=========================================================== +## run Placer +#=========================================================== +#run_placer -config $::env(CONFIG_DIR)/pl_default_config.json + +#=========================================================== +## run gui +#=========================================================== +def_init -path $::env(RESULT_DIR)/iPL_result.def +gui_start -type global_place +gui_show_pl -dir $::env(RESULT_DIR)/pl/gui/ + + diff --git a/scripts/design/ics55_gcd/script/iPL_script/run_iPL_legalization.tcl b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_legalization.tcl new file mode 100755 index 0000000000000000000000000000000000000000..0ab0c3d2d2c6f0a312c37d89b1a8724d69e37b53 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iPL_script/run_iPL_legalization.tcl @@ -0,0 +1,83 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# input files +set INPUT_DEF "$RESULT_DIR/iCTS_result.def" + +# output files +set OUTPUT_DEF "$RESULT_DIR/iPL_lg_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iPL_lg_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/legalization_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/legalization_stat.json" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## run Placer +#=========================================================== +run_incremental_flow -config $IEDA_CONFIG_DIR/pl_default_config.json + +#=========================================================== +## save def +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +# report_db -path $DESIGN_STAT_TEXT +# feature_summary -path $DESIGN_STAT_JSON -step legalization + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iRT_script/run_iRT.tcl b/scripts/design/ics55_gcd/script/iRT_script/run_iRT.tcl new file mode 100755 index 0000000000000000000000000000000000000000..39c001a199e1f29e521a2354da86d3a4e6042e56 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iRT_script/run_iRT.tcl @@ -0,0 +1,105 @@ +#=========================================================== + +#=========================================================== +set RESULT_DIR "./result" + +# inputs +set INPUT_DEF "$RESULT_DIR/iPL_lg_result.def" +set NUM_THREADS 64 +set FAST_ROUTE 0 +if { [info exists ::env(FAST_ROUTE)] && [string tolower $::env(FAST_ROUTE)] == "true" } { + set FAST_ROUTE 1 +} + +# output files +set OUTPUT_DEF "$RESULT_DIR/iRT_result.def" +set OUTPUT_VERILOG "$RESULT_DIR/iRT_result.v" +set DESIGN_STAT_TEXT "$RESULT_DIR/report/routing_stat.rpt" +set DESIGN_STAT_JSON "$RESULT_DIR/report/routing_stat.json" +set TOOL_METRICS_JSON "$RESULT_DIR/metric/iRT_routing_metrics.json" +set TOOL_REPORT_DIR "$RESULT_DIR/report/rt/" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $INPUT_DEF + +#=========================================================== +## run Router +#=========================================================== +init_notification + +init_rt -temp_directory_path $TOOL_REPORT_DIR \ + -bottom_routing_layer "MET2" \ + -top_routing_layer "MET5" \ + -thread_number $NUM_THREADS \ + -output_inter_result 0 \ + -enable_notification 0 \ + -enable_fast_mode $FAST_ROUTE + +run_rt + +destroy_rt + +# report_timing -stage "dr" +feature_tool -path $TOOL_METRICS_JSON -step route + +#=========================================================== +## save def & netlist +#=========================================================== +def_save -path $OUTPUT_DEF + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $OUTPUT_VERILOG -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +report_db -path $DESIGN_STAT_TEXT +feature_summary -path $DESIGN_STAT_JSON -step route + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iRT_script/run_iRT_DRC.tcl b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_DRC.tcl new file mode 100755 index 0000000000000000000000000000000000000000..4070c19b683cb042dea6a110560502ca73448ddb --- /dev/null +++ b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_DRC.tcl @@ -0,0 +1,37 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iRT_result.def + +#=========================================================== +## run DRC and save result +#=========================================================== +run_drc -config $::env(CONFIG_DIR)/drc_default_config.json -path $::env(RESULT_DIR)/report/drc/iRT_drc.rpt +save_drc -path $::env(RESULT_DIR)/drc/detail.drc + +#read_drc -path $::env(RESULT_DIR)/drc/detail.drc + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iRT_script/run_iRT_STA.tcl b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_STA.tcl new file mode 100755 index 0000000000000000000000000000000000000000..a0e06787ad86bdc8a5d600a201efc9915ef59542 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_STA.tcl @@ -0,0 +1,56 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iRT_result.def + +#=========================================================== +## run STA +#=========================================================== +init_sta -output $::env(RESULT_DIR)/rt/sta/ + +init_rt -temp_directory_path "$::env(RESULT_DIR)/rt/" \ + -bottom_routing_layer "met1" \ + -top_routing_layer "met4" \ + -enable_timing 1 + +# run_rt -flow vr +run_rt + +report_timing -stage "dr" + +destroy_rt + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iRT_script/run_iRT_with_drc.tcl b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_with_drc.tcl new file mode 100755 index 0000000000000000000000000000000000000000..ba4865bd9504a2a8c438a3f5f559fbbd5e301b74 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iRT_script/run_iRT_with_drc.tcl @@ -0,0 +1,75 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $::env(CONFIG_DIR)/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $::env(CONFIG_DIR)/db_default_config.json -output_dir_path $::env(RESULT_DIR) + +#=========================================================== +## reset data path +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $::env(TCL_SCRIPT_DIR)/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $::env(RESULT_DIR)/iPL_lg_result.def + +set temp_folder_path $::env(RESULT_DIR)/rt/ + +init_drc_api + +init_rt -temp_directory_path $temp_folder_path \ + -log_level 0 \ + -thread_number 8 \ + -bottom_routing_layer "" \ + -top_routing_layer "" \ + -ra_initial_penalty 100 \ + -ra_penalty_drop_rate 0.8 \ + -ra_outer_max_iter_num 10 \ + -ra_inner_max_iter_num 10 + +run_rt -flow "dr" + +destroy_rt + +destroy_drc_api + + +#=========================================================== +## save def & netlist +#=========================================================== +def_save -path $::env(RESULT_DIR)/iRT_result.def + +#=========================================================== +## save netlist +#=========================================================== +netlist_save -path $::env(RESULT_DIR)/iRT_result.v -exclude_cell_names {} + +#=========================================================== +## report db summary +#=========================================================== +report_db -path "$::env(RESULT_DIR)/report/rt_db.rpt" + +#=========================================================== +## Exit +#=========================================================== +flow_exit diff --git a/scripts/design/ics55_gcd/script/iSTA_script/init_iSTA.tcl b/scripts/design/ics55_gcd/script/iSTA_script/init_iSTA.tcl new file mode 100755 index 0000000000000000000000000000000000000000..393bbdc55468c23778e30ef3e41947b344f15f6e --- /dev/null +++ b/scripts/design/ics55_gcd/script/iSTA_script/init_iSTA.tcl @@ -0,0 +1,40 @@ +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read def +#=========================================================== +def_init -path $RESULT_DIR/iPL_result.def + +#=========================================================== +## run STA +#=========================================================== +init_sta -output $RESULT_DIR/sta/timing.log + diff --git a/scripts/design/ics55_gcd/script/iSTA_script/report_iSTA.tcl b/scripts/design/ics55_gcd/script/iSTA_script/report_iSTA.tcl new file mode 100755 index 0000000000000000000000000000000000000000..e006c31feee0a5f2fc8f8ea2a2fcd48b1d2777b7 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iSTA_script/report_iSTA.tcl @@ -0,0 +1,5 @@ +#=========================================================== +## run STA +#=========================================================== +report_sta -output $RESULT_DIR/sta/timing.log + diff --git a/scripts/design/ics55_gcd/script/iSTA_script/run_iSTA.tcl b/scripts/design/ics55_gcd/script/iSTA_script/run_iSTA.tcl new file mode 100755 index 0000000000000000000000000000000000000000..a49e99295485f51da2744ed7f43b7adddb3b1b58 --- /dev/null +++ b/scripts/design/ics55_gcd/script/iSTA_script/run_iSTA.tcl @@ -0,0 +1,71 @@ +#=========================================================== +set RESULT_DIR "./result" + +# input variables +if { [info exists ::env(USE_VERILOG)] && [string tolower $::env(USE_VERILOG)] == "true" } { + set USE_VERILOG true + set TOP_NAME "$::env(TOP_NAME)" + set INPUT_VERILOG "$::env(INPUT_VERILOG)" +} else { + set USE_VERILOG false +} + +# output files +set TOOL_REPORT_DIR "$RESULT_DIR/sta/" + +# script path +set IEDA_CONFIG_DIR "$::env(IEDA_CONFIG_DIR)" +set IEDA_TCL_SCRIPT_DIR "$::env(IEDA_TCL_SCRIPT_DIR)" + +#=========================================================== +# override variables from env +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/env_var_setup.tcl + +#=========================================================== +## init flow config +#=========================================================== +flow_init -config $IEDA_CONFIG_DIR/flow_config.json + +#=========================================================== +## read db config +#=========================================================== +db_init -config $IEDA_CONFIG_DIR/db_default_config.json -output_dir_path $RESULT_DIR + +#=========================================================== +## reset data path +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_path_setting.tcl + +#=========================================================== +## reset lib +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lib.tcl + +#=========================================================== +## reset sdc +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_sdc.tcl + +#=========================================================== +## read lef +#=========================================================== +source $IEDA_TCL_SCRIPT_DIR/DB_script/db_init_lef.tcl + +#=========================================================== +## read verilog/def +#=========================================================== +if { $USE_VERILOG } { + verilog_init -path $INPUT_VERILOG -top $TOP_NAME +} else { + def_init -path $INPUT_DEF +} +#=========================================================== +## run STA +#=========================================================== +run_sta -output $TOOL_REPORT_DIR + +#=========================================================== +## Exit +#=========================================================== +flow_exit